wcd938x.c 82 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "internal.h"
  23. #include "wcd938x-registers.h"
  24. #define WCD938X_DRV_NAME "wcd938x_codec"
  25. #define NUM_SWRS_DT_PARAMS 5
  26. #define WCD938X_VERSION_1_0 1
  27. #define WCD938X_VERSION_ENTRY_SIZE 32
  28. #define ADC_MODE_VAL_HIFI 0x01
  29. #define ADC_MODE_VAL_LO_HIF 0x02
  30. #define ADC_MODE_VAL_NORMAL 0x03
  31. #define ADC_MODE_VAL_LP 0x05
  32. #define ADC_MODE_VAL_ULP1 0x09
  33. #define ADC_MODE_VAL_ULP2 0x0B
  34. enum {
  35. WCD9380 = 0,
  36. WCD9385,
  37. WCD9385FX,
  38. };
  39. enum {
  40. CODEC_TX = 0,
  41. CODEC_RX,
  42. };
  43. enum {
  44. WCD_ADC1 = 0,
  45. WCD_ADC2,
  46. WCD_ADC3,
  47. WCD_ADC4,
  48. ALLOW_BUCK_DISABLE,
  49. HPH_COMP_DELAY,
  50. HPH_PA_DELAY,
  51. };
  52. enum {
  53. ADC_MODE_INVALID = 0,
  54. ADC_MODE_HIFI,
  55. ADC_MODE_LO_HIF,
  56. ADC_MODE_NORMAL,
  57. ADC_MODE_LP,
  58. ADC_MODE_ULP1,
  59. ADC_MODE_ULP2,
  60. };
  61. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  62. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  63. static int wcd938x_handle_post_irq(void *data);
  64. static int wcd938x_reset(struct device *dev);
  65. static int wcd938x_reset_low(struct device *dev);
  66. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  67. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  68. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  69. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  70. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  71. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  72. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  73. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  74. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  75. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  76. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  77. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  78. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  79. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  80. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  81. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  82. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  83. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  84. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  85. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  86. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  87. };
  88. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  89. .name = "wcd938x",
  90. .irqs = wcd938x_irqs,
  91. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  92. .num_regs = 3,
  93. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  94. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  95. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  96. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  97. .use_ack = 1,
  98. .runtime_pm = false,
  99. .handle_post_irq = wcd938x_handle_post_irq,
  100. .irq_drv_data = NULL,
  101. };
  102. static int wcd938x_handle_post_irq(void *data)
  103. {
  104. struct wcd938x_priv *wcd938x = data;
  105. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  106. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  107. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  108. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  109. wcd938x->tx_swr_dev->slave_irq_pending =
  110. ((sts1 || sts2 || sts3) ? true : false);
  111. return IRQ_HANDLED;
  112. }
  113. static int wcd938x_init_reg(struct snd_soc_component *component)
  114. {
  115. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  116. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  117. /* 1 msec delay as per HW requirement */
  118. usleep_range(1000, 1010);
  119. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  120. /* 1 msec delay as per HW requirement */
  121. usleep_range(1000, 1010);
  122. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  123. 0x10, 0x00);
  124. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  125. 0xF0, 0x80);
  126. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  127. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  128. /* 10 msec delay as per HW requirement */
  129. usleep_range(10000, 10010);
  130. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  131. snd_soc_component_update_bits(component, WCD938X_HPH_OCP_CTL,
  132. 0xFF, 0x3A);
  133. snd_soc_component_update_bits(component, WCD938X_RX_OCP_CTL,
  134. 0x0F, 0x02);
  135. snd_soc_component_update_bits(component, WCD938X_HPH_R_TEST,
  136. 0x01, 0x01);
  137. snd_soc_component_update_bits(component, WCD938X_HPH_L_TEST,
  138. 0x01, 0x01);
  139. snd_soc_component_update_bits(component,
  140. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  141. 0xF0, 0x00);
  142. snd_soc_component_update_bits(component,
  143. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  144. 0x1F, 0x15);
  145. snd_soc_component_update_bits(component,
  146. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  147. 0x1F, 0x15);
  148. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  149. 0xC0, 0x80);
  150. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  151. 0x02, 0x02);
  152. return 0;
  153. }
  154. static int wcd938x_set_port_params(struct snd_soc_component *component,
  155. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  156. u8 *ch_mask, u32 *ch_rate,
  157. u8 *port_type, u8 path)
  158. {
  159. int i, j;
  160. u8 num_ports = 0;
  161. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  162. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  163. switch (path) {
  164. case CODEC_RX:
  165. map = &wcd938x->rx_port_mapping;
  166. num_ports = wcd938x->num_rx_ports;
  167. break;
  168. case CODEC_TX:
  169. map = &wcd938x->tx_port_mapping;
  170. num_ports = wcd938x->num_tx_ports;
  171. break;
  172. default:
  173. dev_err(component->dev, "%s Invalid path selected %u\n",
  174. __func__, path);
  175. return -EINVAL;
  176. }
  177. for (i = 0; i <= num_ports; i++) {
  178. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  179. if ((*map)[i][j].slave_port_type == slv_prt_type)
  180. goto found;
  181. }
  182. }
  183. found:
  184. if (i > num_ports || j == MAX_CH_PER_PORT) {
  185. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  186. __func__, slv_prt_type);
  187. return -EINVAL;
  188. }
  189. *port_id = i;
  190. *num_ch = (*map)[i][j].num_ch;
  191. *ch_mask = (*map)[i][j].ch_mask;
  192. *ch_rate = (*map)[i][j].ch_rate;
  193. *port_type = (*map)[i][j].master_port_type;
  194. return 0;
  195. }
  196. static int wcd938x_parse_port_mapping(struct device *dev,
  197. char *prop, u8 path)
  198. {
  199. u32 *dt_array, map_size, map_length;
  200. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  201. u32 slave_port_type, master_port_type;
  202. u32 i, ch_iter = 0;
  203. int ret = 0;
  204. u8 *num_ports = NULL;
  205. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  206. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  207. switch (path) {
  208. case CODEC_RX:
  209. map = &wcd938x->rx_port_mapping;
  210. num_ports = &wcd938x->num_rx_ports;
  211. break;
  212. case CODEC_TX:
  213. map = &wcd938x->tx_port_mapping;
  214. num_ports = &wcd938x->num_tx_ports;
  215. break;
  216. default:
  217. dev_err(dev, "%s Invalid path selected %u\n",
  218. __func__, path);
  219. return -EINVAL;
  220. }
  221. if (!of_find_property(dev->of_node, prop,
  222. &map_size)) {
  223. dev_err(dev, "missing port mapping prop %s\n", prop);
  224. ret = -EINVAL;
  225. goto err_port_map;
  226. }
  227. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  228. dt_array = kzalloc(map_size, GFP_KERNEL);
  229. if (!dt_array) {
  230. ret = -ENOMEM;
  231. goto err_alloc;
  232. }
  233. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  234. NUM_SWRS_DT_PARAMS * map_length);
  235. if (ret) {
  236. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  237. __func__, prop);
  238. goto err_pdata_fail;
  239. }
  240. for (i = 0; i < map_length; i++) {
  241. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  242. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  243. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  244. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  245. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  246. if (port_num != old_port_num)
  247. ch_iter = 0;
  248. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  249. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  250. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  251. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  252. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  253. old_port_num = port_num;
  254. }
  255. *num_ports = port_num;
  256. kfree(dt_array);
  257. return 0;
  258. err_pdata_fail:
  259. kfree(dt_array);
  260. err_alloc:
  261. err_port_map:
  262. return ret;
  263. }
  264. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  265. u8 slv_port_type, u8 enable)
  266. {
  267. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  268. u8 port_id, num_ch, ch_mask, port_type;
  269. u32 ch_rate;
  270. u8 num_port = 1;
  271. int ret = 0;
  272. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  273. &num_ch, &ch_mask, &ch_rate,
  274. &port_type, CODEC_TX);
  275. if (ret)
  276. return ret;
  277. if (enable)
  278. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  279. num_port, &ch_mask, &ch_rate,
  280. &num_ch, &port_type);
  281. else
  282. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  283. num_port, &ch_mask, &port_type);
  284. return ret;
  285. }
  286. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  287. u8 slv_port_type, u8 enable)
  288. {
  289. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  290. u8 port_id, num_ch, ch_mask, port_type;
  291. u32 ch_rate;
  292. u8 num_port = 1;
  293. int ret = 0;
  294. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  295. &num_ch, &ch_mask, &ch_rate,
  296. &port_type, CODEC_RX);
  297. if (ret)
  298. return ret;
  299. if (enable)
  300. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  301. num_port, &ch_mask, &ch_rate,
  302. &num_ch, &port_type);
  303. else
  304. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  305. num_port, &ch_mask, &port_type);
  306. return ret;
  307. }
  308. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  309. {
  310. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  311. if (wcd938x->rx_clk_cnt == 0) {
  312. snd_soc_component_update_bits(component,
  313. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  314. snd_soc_component_update_bits(component,
  315. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  316. snd_soc_component_update_bits(component,
  317. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  318. snd_soc_component_update_bits(component,
  319. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  320. snd_soc_component_update_bits(component,
  321. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  322. snd_soc_component_update_bits(component,
  323. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  324. }
  325. wcd938x->rx_clk_cnt++;
  326. return 0;
  327. }
  328. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  329. {
  330. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  331. wcd938x->rx_clk_cnt--;
  332. if (wcd938x->rx_clk_cnt == 0) {
  333. snd_soc_component_update_bits(component,
  334. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  335. snd_soc_component_update_bits(component,
  336. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  337. snd_soc_component_update_bits(component,
  338. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  339. snd_soc_component_update_bits(component,
  340. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  341. snd_soc_component_update_bits(component,
  342. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  343. }
  344. return 0;
  345. }
  346. /*
  347. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  348. * @component: handle to snd_soc_component *
  349. *
  350. * return wcd938x_mbhc handle or error code in case of failure
  351. */
  352. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  353. {
  354. struct wcd938x_priv *wcd938x;
  355. if (!component) {
  356. pr_err("%s: Invalid params, NULL component\n", __func__);
  357. return NULL;
  358. }
  359. wcd938x = snd_soc_component_get_drvdata(component);
  360. if (!wcd938x) {
  361. pr_err("%s: wcd938x is NULL\n", __func__);
  362. return NULL;
  363. }
  364. return wcd938x->mbhc;
  365. }
  366. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  367. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  368. struct snd_kcontrol *kcontrol,
  369. int event)
  370. {
  371. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  372. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  373. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  374. w->name, event);
  375. switch (event) {
  376. case SND_SOC_DAPM_PRE_PMU:
  377. wcd938x_rx_clk_enable(component);
  378. snd_soc_component_update_bits(component,
  379. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  380. snd_soc_component_update_bits(component,
  381. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  382. snd_soc_component_update_bits(component,
  383. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  384. break;
  385. case SND_SOC_DAPM_POST_PMU:
  386. snd_soc_component_update_bits(component,
  387. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  388. if (wcd938x->comp1_enable) {
  389. snd_soc_component_update_bits(component,
  390. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  391. /* 5msec compander delay as per HW requirement */
  392. if (!wcd938x->comp2_enable ||
  393. (snd_soc_component_read32(component,
  394. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  395. usleep_range(5000, 5010);
  396. snd_soc_component_update_bits(component,
  397. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  398. } else {
  399. snd_soc_component_update_bits(component,
  400. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  401. 0x02, 0x00);
  402. snd_soc_component_update_bits(component,
  403. WCD938X_HPH_L_EN, 0x20, 0x20);
  404. }
  405. break;
  406. case SND_SOC_DAPM_POST_PMD:
  407. snd_soc_component_update_bits(component,
  408. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  409. 0x0F, 0x01);
  410. break;
  411. }
  412. return 0;
  413. }
  414. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  415. struct snd_kcontrol *kcontrol,
  416. int event)
  417. {
  418. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  419. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  420. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  421. w->name, event);
  422. switch (event) {
  423. case SND_SOC_DAPM_PRE_PMU:
  424. wcd938x_rx_clk_enable(component);
  425. snd_soc_component_update_bits(component,
  426. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  427. snd_soc_component_update_bits(component,
  428. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  429. snd_soc_component_update_bits(component,
  430. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  431. break;
  432. case SND_SOC_DAPM_POST_PMU:
  433. snd_soc_component_update_bits(component,
  434. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  435. if (wcd938x->comp2_enable) {
  436. snd_soc_component_update_bits(component,
  437. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  438. /* 5msec compander delay as per HW requirement */
  439. if (!wcd938x->comp1_enable ||
  440. (snd_soc_component_read32(component,
  441. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  442. usleep_range(5000, 5010);
  443. snd_soc_component_update_bits(component,
  444. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  445. } else {
  446. snd_soc_component_update_bits(component,
  447. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  448. 0x01, 0x00);
  449. snd_soc_component_update_bits(component,
  450. WCD938X_HPH_R_EN, 0x20, 0x20);
  451. }
  452. break;
  453. case SND_SOC_DAPM_POST_PMD:
  454. snd_soc_component_update_bits(component,
  455. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  456. 0x0F, 0x01);
  457. break;
  458. }
  459. return 0;
  460. }
  461. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  462. struct snd_kcontrol *kcontrol,
  463. int event)
  464. {
  465. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  466. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  467. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  468. w->name, event);
  469. switch (event) {
  470. case SND_SOC_DAPM_PRE_PMU:
  471. wcd938x_rx_clk_enable(component);
  472. snd_soc_component_update_bits(component,
  473. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  474. snd_soc_component_update_bits(component,
  475. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  476. snd_soc_component_update_bits(component,
  477. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  478. /* 5 msec delay as per HW requirement */
  479. usleep_range(5000, 5010);
  480. snd_soc_component_update_bits(component, WCD938X_FLYBACK_EN,
  481. 0x04, 0x00);
  482. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  483. WCD_CLSH_EVENT_PRE_DAC,
  484. WCD_CLSH_STATE_EAR,
  485. wcd938x->hph_mode);
  486. break;
  487. case SND_SOC_DAPM_POST_PMD:
  488. break;
  489. };
  490. return 0;
  491. }
  492. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  493. struct snd_kcontrol *kcontrol,
  494. int event)
  495. {
  496. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  497. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  498. int ret = 0;
  499. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  500. w->name, event);
  501. switch (event) {
  502. case SND_SOC_DAPM_PRE_PMU:
  503. wcd938x_rx_clk_enable(component);
  504. snd_soc_component_update_bits(component,
  505. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  506. snd_soc_component_update_bits(component,
  507. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  508. snd_soc_component_update_bits(component,
  509. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  510. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  511. WCD_CLSH_EVENT_PRE_DAC,
  512. WCD_CLSH_STATE_AUX,
  513. wcd938x->hph_mode);
  514. break;
  515. case SND_SOC_DAPM_POST_PMD:
  516. wcd938x_rx_clk_disable(component);
  517. snd_soc_component_update_bits(component,
  518. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  519. break;
  520. };
  521. return ret;
  522. }
  523. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  524. struct snd_kcontrol *kcontrol,
  525. int event)
  526. {
  527. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  528. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  529. int ret = 0;
  530. int hph_mode = wcd938x->hph_mode;
  531. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  532. w->name, event);
  533. switch (event) {
  534. case SND_SOC_DAPM_PRE_PMU:
  535. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  536. wcd938x->rx_swr_dev->dev_num,
  537. true);
  538. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  539. WCD_CLSH_EVENT_PRE_DAC,
  540. WCD_CLSH_STATE_HPHR,
  541. hph_mode);
  542. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  543. 0x10, 0x10);
  544. /* 100 usec delay as per HW requirement */
  545. usleep_range(100, 110);
  546. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  547. break;
  548. case SND_SOC_DAPM_POST_PMU:
  549. /*
  550. * 7ms sleep is required if compander is enabled as per
  551. * HW requirement. If compander is disabled, then
  552. * 20ms delay is required.
  553. */
  554. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  555. if (!wcd938x->comp2_enable)
  556. usleep_range(20000, 20100);
  557. else
  558. usleep_range(7000, 7100);
  559. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  560. }
  561. snd_soc_component_update_bits(component,
  562. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  563. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  564. snd_soc_component_update_bits(component,
  565. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  566. if (wcd938x->update_wcd_event)
  567. wcd938x->update_wcd_event(wcd938x->handle,
  568. WCD_BOLERO_EVT_RX_MUTE,
  569. (WCD_RX2 << 0x10));
  570. break;
  571. case SND_SOC_DAPM_PRE_PMD:
  572. if (wcd938x->update_wcd_event)
  573. wcd938x->update_wcd_event(wcd938x->handle,
  574. WCD_BOLERO_EVT_RX_MUTE,
  575. (WCD_RX2 << 0x10 | 0x1));
  576. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  577. WCD_EVENT_PRE_HPHR_PA_OFF,
  578. &wcd938x->mbhc->wcd_mbhc);
  579. break;
  580. case SND_SOC_DAPM_POST_PMD:
  581. /* 7 msec delay as per HW requirement */
  582. usleep_range(7000, 7010);
  583. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  584. WCD_EVENT_POST_HPHR_PA_OFF,
  585. &wcd938x->mbhc->wcd_mbhc);
  586. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  587. 0x10, 0x00);
  588. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  589. WCD_CLSH_EVENT_POST_PA,
  590. WCD_CLSH_STATE_HPHR,
  591. hph_mode);
  592. break;
  593. };
  594. return ret;
  595. }
  596. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  597. struct snd_kcontrol *kcontrol,
  598. int event)
  599. {
  600. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  601. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  602. int ret = 0;
  603. int hph_mode = wcd938x->hph_mode;
  604. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  605. w->name, event);
  606. switch (event) {
  607. case SND_SOC_DAPM_PRE_PMU:
  608. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  609. wcd938x->rx_swr_dev->dev_num,
  610. true);
  611. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  612. WCD_CLSH_EVENT_PRE_DAC,
  613. WCD_CLSH_STATE_HPHL,
  614. hph_mode);
  615. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  616. 0x20, 0x20);
  617. /* 100 usec delay as per HW requirement */
  618. usleep_range(100, 110);
  619. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  620. break;
  621. case SND_SOC_DAPM_POST_PMU:
  622. /*
  623. * 7ms sleep is required if compander is enabled as per
  624. * HW requirement. If compander is disabled, then
  625. * 20ms delay is required.
  626. */
  627. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  628. if (!wcd938x->comp1_enable)
  629. usleep_range(20000, 20100);
  630. else
  631. usleep_range(7000, 7100);
  632. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  633. }
  634. snd_soc_component_update_bits(component,
  635. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  636. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  637. snd_soc_component_update_bits(component,
  638. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  639. if (wcd938x->update_wcd_event)
  640. wcd938x->update_wcd_event(wcd938x->handle,
  641. WCD_BOLERO_EVT_RX_MUTE,
  642. (WCD_RX1 << 0x10));
  643. break;
  644. case SND_SOC_DAPM_PRE_PMD:
  645. if (wcd938x->update_wcd_event)
  646. wcd938x->update_wcd_event(wcd938x->handle,
  647. WCD_BOLERO_EVT_RX_MUTE,
  648. (WCD_RX1 << 0x10 | 0x1));
  649. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  650. WCD_EVENT_PRE_HPHL_PA_OFF,
  651. &wcd938x->mbhc->wcd_mbhc);
  652. break;
  653. case SND_SOC_DAPM_POST_PMD:
  654. /* 7 msec delay as per HW requirement */
  655. usleep_range(7000, 7010);
  656. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  657. WCD_EVENT_POST_HPHL_PA_OFF,
  658. &wcd938x->mbhc->wcd_mbhc);
  659. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  660. 0x20, 0x00);
  661. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  662. WCD_CLSH_EVENT_POST_PA,
  663. WCD_CLSH_STATE_HPHL,
  664. hph_mode);
  665. break;
  666. };
  667. return ret;
  668. }
  669. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  670. struct snd_kcontrol *kcontrol,
  671. int event)
  672. {
  673. struct snd_soc_component *component =
  674. snd_soc_dapm_to_component(w->dapm);
  675. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  676. int hph_mode = wcd938x->hph_mode;
  677. int ret = 0;
  678. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  679. w->name, event);
  680. switch (event) {
  681. case SND_SOC_DAPM_PRE_PMU:
  682. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  683. wcd938x->rx_swr_dev->dev_num,
  684. true);
  685. break;
  686. case SND_SOC_DAPM_POST_PMU:
  687. /* 1 msec delay as per HW requirement */
  688. usleep_range(1000, 1010);
  689. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  690. snd_soc_component_update_bits(component,
  691. WCD938X_ANA_RX_SUPPLIES,
  692. 0x20, 0x20);
  693. if (wcd938x->update_wcd_event)
  694. wcd938x->update_wcd_event(wcd938x->handle,
  695. WCD_BOLERO_EVT_RX_MUTE,
  696. (WCD_RX3 << 0x10));
  697. break;
  698. case SND_SOC_DAPM_PRE_PMD:
  699. if (wcd938x->update_wcd_event)
  700. wcd938x->update_wcd_event(wcd938x->handle,
  701. WCD_BOLERO_EVT_RX_MUTE,
  702. (WCD_RX3 << 0x10 | 0x1));
  703. break;
  704. case SND_SOC_DAPM_POST_PMD:
  705. /* 1 msec delay as per HW requirement */
  706. usleep_range(1000, 1010);
  707. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  708. WCD_CLSH_EVENT_POST_PA,
  709. WCD_CLSH_STATE_AUX,
  710. hph_mode);
  711. break;
  712. };
  713. return ret;
  714. }
  715. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  716. struct snd_kcontrol *kcontrol,
  717. int event)
  718. {
  719. struct snd_soc_component *component =
  720. snd_soc_dapm_to_component(w->dapm);
  721. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  722. int hph_mode = wcd938x->hph_mode;
  723. int ret = 0;
  724. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  725. w->name, event);
  726. switch (event) {
  727. case SND_SOC_DAPM_PRE_PMU:
  728. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  729. wcd938x->rx_swr_dev->dev_num,
  730. true);
  731. break;
  732. case SND_SOC_DAPM_POST_PMU:
  733. /* 6 msec delay as per HW requirement */
  734. usleep_range(6000, 6010);
  735. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  736. snd_soc_component_update_bits(component,
  737. WCD938X_ANA_RX_SUPPLIES,
  738. 0x02, 0x02);
  739. if (wcd938x->update_wcd_event)
  740. wcd938x->update_wcd_event(wcd938x->handle,
  741. WCD_BOLERO_EVT_RX_MUTE,
  742. (WCD_RX1 << 0x10));
  743. break;
  744. case SND_SOC_DAPM_PRE_PMD:
  745. if (wcd938x->update_wcd_event)
  746. wcd938x->update_wcd_event(wcd938x->handle,
  747. WCD_BOLERO_EVT_RX_MUTE,
  748. (WCD_RX1 << 0x10 | 0x1));
  749. break;
  750. case SND_SOC_DAPM_POST_PMD:
  751. /* 7 msec delay as per HW requirement */
  752. usleep_range(7000, 7010);
  753. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  754. WCD_CLSH_EVENT_POST_PA,
  755. WCD_CLSH_STATE_EAR,
  756. hph_mode);
  757. snd_soc_component_update_bits(component, WCD938X_FLYBACK_EN,
  758. 0x04, 0x04);
  759. break;
  760. };
  761. return ret;
  762. }
  763. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  764. struct snd_kcontrol *kcontrol,
  765. int event)
  766. {
  767. struct snd_soc_component *component =
  768. snd_soc_dapm_to_component(w->dapm);
  769. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  770. int mode = wcd938x->hph_mode;
  771. int ret = 0;
  772. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  773. w->name, event);
  774. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  775. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  776. wcd938x_rx_connect_port(component, CLSH,
  777. SND_SOC_DAPM_EVENT_ON(event));
  778. }
  779. if (SND_SOC_DAPM_EVENT_OFF(event))
  780. ret = swr_slvdev_datapath_control(
  781. wcd938x->rx_swr_dev,
  782. wcd938x->rx_swr_dev->dev_num,
  783. false);
  784. return ret;
  785. }
  786. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  787. struct snd_kcontrol *kcontrol,
  788. int event)
  789. {
  790. struct snd_soc_component *component =
  791. snd_soc_dapm_to_component(w->dapm);
  792. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  793. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  794. w->name, event);
  795. switch (event) {
  796. case SND_SOC_DAPM_PRE_PMU:
  797. wcd938x_rx_connect_port(component, HPH_L, true);
  798. if (wcd938x->comp1_enable)
  799. wcd938x_rx_connect_port(component, COMP_L, true);
  800. break;
  801. case SND_SOC_DAPM_POST_PMD:
  802. wcd938x_rx_connect_port(component, HPH_L, false);
  803. if (wcd938x->comp1_enable)
  804. wcd938x_rx_connect_port(component, COMP_L, false);
  805. wcd938x_rx_clk_disable(component);
  806. snd_soc_component_update_bits(component,
  807. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  808. 0x01, 0x00);
  809. break;
  810. };
  811. return 0;
  812. }
  813. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  814. struct snd_kcontrol *kcontrol, int event)
  815. {
  816. struct snd_soc_component *component =
  817. snd_soc_dapm_to_component(w->dapm);
  818. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  819. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  820. w->name, event);
  821. switch (event) {
  822. case SND_SOC_DAPM_PRE_PMU:
  823. wcd938x_rx_connect_port(component, HPH_R, true);
  824. if (wcd938x->comp2_enable)
  825. wcd938x_rx_connect_port(component, COMP_R, true);
  826. break;
  827. case SND_SOC_DAPM_POST_PMD:
  828. wcd938x_rx_connect_port(component, HPH_R, false);
  829. if (wcd938x->comp2_enable)
  830. wcd938x_rx_connect_port(component, COMP_R, false);
  831. wcd938x_rx_clk_disable(component);
  832. snd_soc_component_update_bits(component,
  833. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  834. 0x02, 0x00);
  835. break;
  836. };
  837. return 0;
  838. }
  839. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  840. struct snd_kcontrol *kcontrol,
  841. int event)
  842. {
  843. struct snd_soc_component *component =
  844. snd_soc_dapm_to_component(w->dapm);
  845. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  846. w->name, event);
  847. switch (event) {
  848. case SND_SOC_DAPM_PRE_PMU:
  849. wcd938x_rx_connect_port(component, LO, true);
  850. break;
  851. case SND_SOC_DAPM_POST_PMD:
  852. wcd938x_rx_connect_port(component, LO, false);
  853. /* 6 msec delay as per HW requirement */
  854. usleep_range(6000, 6010);
  855. wcd938x_rx_clk_disable(component);
  856. snd_soc_component_update_bits(component,
  857. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  858. break;
  859. }
  860. return 0;
  861. }
  862. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  863. struct snd_kcontrol *kcontrol,
  864. int event)
  865. {
  866. struct snd_soc_component *component =
  867. snd_soc_dapm_to_component(w->dapm);
  868. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  869. u16 dmic_clk_reg;
  870. s32 *dmic_clk_cnt;
  871. unsigned int dmic;
  872. char *wname;
  873. int ret = 0;
  874. wname = strpbrk(w->name, "012345");
  875. if (!wname) {
  876. dev_err(component->dev, "%s: widget not found\n", __func__);
  877. return -EINVAL;
  878. }
  879. ret = kstrtouint(wname, 10, &dmic);
  880. if (ret < 0) {
  881. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  882. __func__);
  883. return -EINVAL;
  884. }
  885. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  886. w->name, event);
  887. switch (dmic) {
  888. case 0:
  889. case 1:
  890. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  891. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  892. break;
  893. case 2:
  894. case 3:
  895. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  896. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  897. break;
  898. case 4:
  899. case 5:
  900. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  901. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  902. break;
  903. case 6:
  904. case 7:
  905. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  906. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  907. break;
  908. default:
  909. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  910. __func__);
  911. return -EINVAL;
  912. };
  913. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  914. __func__, event, dmic, *dmic_clk_cnt);
  915. switch (event) {
  916. case SND_SOC_DAPM_PRE_PMU:
  917. snd_soc_component_update_bits(component,
  918. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  919. /* enable clock scaling */
  920. snd_soc_component_update_bits(component,
  921. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  922. snd_soc_component_update_bits(component,
  923. dmic_clk_reg, 0x07, 0x02);
  924. snd_soc_component_update_bits(component,
  925. dmic_clk_reg, 0x08, 0x08);
  926. snd_soc_component_update_bits(component,
  927. dmic_clk_reg, 0x70, 0x20);
  928. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), true);
  929. break;
  930. case SND_SOC_DAPM_POST_PMD:
  931. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), false);
  932. break;
  933. };
  934. return 0;
  935. }
  936. /*
  937. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  938. * @micb_mv: micbias in mv
  939. *
  940. * return register value converted
  941. */
  942. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  943. {
  944. /* min micbias voltage is 1V and maximum is 2.85V */
  945. if (micb_mv < 1000 || micb_mv > 2850) {
  946. pr_err("%s: unsupported micbias voltage\n", __func__);
  947. return -EINVAL;
  948. }
  949. return (micb_mv - 1000) / 50;
  950. }
  951. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  952. /*
  953. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  954. * @component: handle to snd_soc_component *
  955. * @req_volt: micbias voltage to be set
  956. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  957. *
  958. * return 0 if adjustment is success or error code in case of failure
  959. */
  960. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  961. int req_volt, int micb_num)
  962. {
  963. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  964. int cur_vout_ctl, req_vout_ctl;
  965. int micb_reg, micb_val, micb_en;
  966. int ret = 0;
  967. switch (micb_num) {
  968. case MIC_BIAS_1:
  969. micb_reg = WCD938X_ANA_MICB1;
  970. break;
  971. case MIC_BIAS_2:
  972. micb_reg = WCD938X_ANA_MICB2;
  973. break;
  974. case MIC_BIAS_3:
  975. micb_reg = WCD938X_ANA_MICB3;
  976. break;
  977. case MIC_BIAS_4:
  978. micb_reg = WCD938X_ANA_MICB4;
  979. break;
  980. default:
  981. return -EINVAL;
  982. }
  983. mutex_lock(&wcd938x->micb_lock);
  984. /*
  985. * If requested micbias voltage is same as current micbias
  986. * voltage, then just return. Otherwise, adjust voltage as
  987. * per requested value. If micbias is already enabled, then
  988. * to avoid slow micbias ramp-up or down enable pull-up
  989. * momentarily, change the micbias value and then re-enable
  990. * micbias.
  991. */
  992. micb_val = snd_soc_component_read32(component, micb_reg);
  993. micb_en = (micb_val & 0xC0) >> 6;
  994. cur_vout_ctl = micb_val & 0x3F;
  995. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  996. if (req_vout_ctl < 0) {
  997. ret = -EINVAL;
  998. goto exit;
  999. }
  1000. if (cur_vout_ctl == req_vout_ctl) {
  1001. ret = 0;
  1002. goto exit;
  1003. }
  1004. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1005. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1006. req_volt, micb_en);
  1007. if (micb_en == 0x1)
  1008. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1009. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1010. if (micb_en == 0x1) {
  1011. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1012. /*
  1013. * Add 2ms delay as per HW requirement after enabling
  1014. * micbias
  1015. */
  1016. usleep_range(2000, 2100);
  1017. }
  1018. exit:
  1019. mutex_unlock(&wcd938x->micb_lock);
  1020. return ret;
  1021. }
  1022. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1023. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1024. struct snd_kcontrol *kcontrol,
  1025. int event)
  1026. {
  1027. struct snd_soc_component *component =
  1028. snd_soc_dapm_to_component(w->dapm);
  1029. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1030. int ret = 0;
  1031. switch (event) {
  1032. case SND_SOC_DAPM_PRE_PMU:
  1033. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1034. wcd938x->tx_swr_dev->dev_num,
  1035. true);
  1036. break;
  1037. case SND_SOC_DAPM_POST_PMD:
  1038. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1039. wcd938x->tx_swr_dev->dev_num,
  1040. false);
  1041. break;
  1042. };
  1043. return ret;
  1044. }
  1045. static int wcd938x_get_adc_mode(int val)
  1046. {
  1047. int ret = 0;
  1048. switch (val) {
  1049. case ADC_MODE_INVALID:
  1050. ret = ADC_MODE_VAL_NORMAL;
  1051. break;
  1052. case ADC_MODE_HIFI:
  1053. ret = ADC_MODE_VAL_HIFI;
  1054. break;
  1055. case ADC_MODE_LO_HIF:
  1056. ret = ADC_MODE_VAL_LO_HIF;
  1057. break;
  1058. case ADC_MODE_NORMAL:
  1059. ret = ADC_MODE_VAL_NORMAL;
  1060. break;
  1061. case ADC_MODE_LP:
  1062. ret = ADC_MODE_VAL_LP;
  1063. break;
  1064. case ADC_MODE_ULP1:
  1065. ret = ADC_MODE_VAL_ULP1;
  1066. break;
  1067. case ADC_MODE_ULP2:
  1068. ret = ADC_MODE_VAL_ULP2;
  1069. break;
  1070. default:
  1071. ret = -EINVAL;
  1072. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1073. break;
  1074. }
  1075. return ret;
  1076. }
  1077. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1078. struct snd_kcontrol *kcontrol,
  1079. int event){
  1080. int mode;
  1081. struct snd_soc_component *component =
  1082. snd_soc_dapm_to_component(w->dapm);
  1083. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1084. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1085. w->name, event);
  1086. switch (event) {
  1087. case SND_SOC_DAPM_PRE_PMU:
  1088. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1089. if (mode < 0) {
  1090. dev_info(component->dev,
  1091. "%s: invalid mode, setting to normal mode\n",
  1092. __func__);
  1093. mode = ADC_MODE_VAL_NORMAL;
  1094. }
  1095. snd_soc_component_update_bits(component,
  1096. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1097. snd_soc_component_update_bits(component,
  1098. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1099. snd_soc_component_update_bits(component,
  1100. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1101. switch (w->shift) {
  1102. case 0:
  1103. snd_soc_component_update_bits(component,
  1104. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1105. mode);
  1106. break;
  1107. case 1:
  1108. snd_soc_component_update_bits(component,
  1109. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1110. mode << 4);
  1111. break;
  1112. case 2:
  1113. snd_soc_component_update_bits(component,
  1114. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1115. mode);
  1116. break;
  1117. case 3:
  1118. snd_soc_component_update_bits(component,
  1119. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1120. mode << 4);
  1121. break;
  1122. default:
  1123. break;
  1124. }
  1125. set_bit(w->shift, &wcd938x->status_mask);
  1126. wcd938x_tx_connect_port(component, ADC1 + (w->shift), true);
  1127. break;
  1128. case SND_SOC_DAPM_POST_PMD:
  1129. wcd938x_tx_connect_port(component, ADC1 + (w->shift), false);
  1130. snd_soc_component_update_bits(component,
  1131. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1132. clear_bit(w->shift, &wcd938x->status_mask);
  1133. break;
  1134. };
  1135. return 0;
  1136. }
  1137. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1138. int channel, int mode)
  1139. {
  1140. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1141. int ret = 0;
  1142. switch (channel) {
  1143. case 0:
  1144. reg = WCD938X_ANA_TX_CH2;
  1145. mask = 0x40;
  1146. break;
  1147. case 1:
  1148. reg = WCD938X_ANA_TX_CH2;
  1149. mask = 0x20;
  1150. break;
  1151. case 2:
  1152. reg = WCD938X_ANA_TX_CH4;
  1153. mask = 0x40;
  1154. break;
  1155. case 3:
  1156. reg = WCD938X_ANA_TX_CH4;
  1157. mask = 0x20;
  1158. break;
  1159. default:
  1160. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1161. ret = -EINVAL;
  1162. break;
  1163. }
  1164. if (!mode)
  1165. val = 0x00;
  1166. else
  1167. val = mask;
  1168. if (!ret)
  1169. snd_soc_component_update_bits(component, reg, mask, val);
  1170. return ret;
  1171. }
  1172. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1173. struct snd_kcontrol *kcontrol, int event)
  1174. {
  1175. struct snd_soc_component *component =
  1176. snd_soc_dapm_to_component(w->dapm);
  1177. int ret = 0;
  1178. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1179. w->name, event);
  1180. switch (event) {
  1181. case SND_SOC_DAPM_PRE_PMU:
  1182. snd_soc_component_update_bits(component,
  1183. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1184. snd_soc_component_update_bits(component,
  1185. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1186. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1187. snd_soc_component_update_bits(component,
  1188. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x30, 0x30);
  1189. snd_soc_component_update_bits(component,
  1190. WCD938X_ANA_TX_CH1, 0x80, 0x80);
  1191. snd_soc_component_update_bits(component,
  1192. WCD938X_ANA_TX_CH2, 0x80, 0x80);
  1193. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1194. break;
  1195. case SND_SOC_DAPM_POST_PMD:
  1196. snd_soc_component_update_bits(component,
  1197. WCD938X_ANA_TX_CH1, 0x80, 0x00);
  1198. snd_soc_component_update_bits(component,
  1199. WCD938X_ANA_TX_CH2, 0x80, 0x00);
  1200. snd_soc_component_update_bits(component,
  1201. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1202. snd_soc_component_update_bits(component,
  1203. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1204. snd_soc_component_update_bits(component,
  1205. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1206. break;
  1207. };
  1208. return ret;
  1209. }
  1210. int wcd938x_micbias_control(struct snd_soc_component *component,
  1211. int micb_num, int req, bool is_dapm)
  1212. {
  1213. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1214. int micb_index = micb_num - 1;
  1215. u16 micb_reg;
  1216. int pre_off_event = 0, post_off_event = 0;
  1217. int post_on_event = 0, post_dapm_off = 0;
  1218. int post_dapm_on = 0;
  1219. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1220. dev_err(component->dev,
  1221. "%s: Invalid micbias index, micb_ind:%d\n",
  1222. __func__, micb_index);
  1223. return -EINVAL;
  1224. }
  1225. switch (micb_num) {
  1226. case MIC_BIAS_1:
  1227. micb_reg = WCD938X_ANA_MICB1;
  1228. break;
  1229. case MIC_BIAS_2:
  1230. micb_reg = WCD938X_ANA_MICB2;
  1231. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1232. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1233. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1234. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1235. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1236. break;
  1237. case MIC_BIAS_3:
  1238. micb_reg = WCD938X_ANA_MICB3;
  1239. break;
  1240. case MIC_BIAS_4:
  1241. micb_reg = WCD938X_ANA_MICB4;
  1242. break;
  1243. default:
  1244. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1245. __func__, micb_num);
  1246. return -EINVAL;
  1247. };
  1248. mutex_lock(&wcd938x->micb_lock);
  1249. switch (req) {
  1250. case MICB_PULLUP_ENABLE:
  1251. wcd938x->pullup_ref[micb_index]++;
  1252. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1253. (wcd938x->micb_ref[micb_index] == 0))
  1254. snd_soc_component_update_bits(component, micb_reg,
  1255. 0xC0, 0x80);
  1256. break;
  1257. case MICB_PULLUP_DISABLE:
  1258. if (wcd938x->pullup_ref[micb_index] > 0)
  1259. wcd938x->pullup_ref[micb_index]--;
  1260. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1261. (wcd938x->micb_ref[micb_index] == 0))
  1262. snd_soc_component_update_bits(component, micb_reg,
  1263. 0xC0, 0x00);
  1264. break;
  1265. case MICB_ENABLE:
  1266. wcd938x->micb_ref[micb_index]++;
  1267. if (wcd938x->micb_ref[micb_index] == 1) {
  1268. snd_soc_component_update_bits(component,
  1269. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1270. snd_soc_component_update_bits(component,
  1271. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1272. snd_soc_component_update_bits(component,
  1273. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1274. snd_soc_component_update_bits(component,
  1275. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1276. snd_soc_component_update_bits(component,
  1277. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1278. snd_soc_component_update_bits(component,
  1279. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1280. snd_soc_component_update_bits(component,
  1281. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1282. snd_soc_component_update_bits(component,
  1283. micb_reg, 0xC0, 0x40);
  1284. if (post_on_event)
  1285. blocking_notifier_call_chain(
  1286. &wcd938x->mbhc->notifier,
  1287. post_on_event,
  1288. &wcd938x->mbhc->wcd_mbhc);
  1289. }
  1290. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1291. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1292. post_dapm_on,
  1293. &wcd938x->mbhc->wcd_mbhc);
  1294. break;
  1295. case MICB_DISABLE:
  1296. if (wcd938x->micb_ref[micb_index] > 0)
  1297. wcd938x->micb_ref[micb_index]--;
  1298. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1299. (wcd938x->pullup_ref[micb_index] > 0))
  1300. snd_soc_component_update_bits(component, micb_reg,
  1301. 0xC0, 0x80);
  1302. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1303. (wcd938x->pullup_ref[micb_index] == 0)) {
  1304. if (pre_off_event && wcd938x->mbhc)
  1305. blocking_notifier_call_chain(
  1306. &wcd938x->mbhc->notifier,
  1307. pre_off_event,
  1308. &wcd938x->mbhc->wcd_mbhc);
  1309. snd_soc_component_update_bits(component, micb_reg,
  1310. 0xC0, 0x00);
  1311. if (post_off_event && wcd938x->mbhc)
  1312. blocking_notifier_call_chain(
  1313. &wcd938x->mbhc->notifier,
  1314. post_off_event,
  1315. &wcd938x->mbhc->wcd_mbhc);
  1316. }
  1317. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1318. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1319. post_dapm_off,
  1320. &wcd938x->mbhc->wcd_mbhc);
  1321. break;
  1322. };
  1323. dev_dbg(component->dev,
  1324. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1325. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1326. wcd938x->pullup_ref[micb_index]);
  1327. mutex_unlock(&wcd938x->micb_lock);
  1328. return 0;
  1329. }
  1330. EXPORT_SYMBOL(wcd938x_micbias_control);
  1331. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1332. {
  1333. int ret = 0;
  1334. uint8_t devnum = 0;
  1335. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1336. if (ret) {
  1337. dev_err(&swr_dev->dev,
  1338. "%s get devnum %d for dev addr %lx failed\n",
  1339. __func__, devnum, swr_dev->addr);
  1340. swr_remove_device(swr_dev);
  1341. return ret;
  1342. }
  1343. swr_dev->dev_num = devnum;
  1344. return 0;
  1345. }
  1346. static int wcd938x_event_notify(struct notifier_block *block,
  1347. unsigned long val,
  1348. void *data)
  1349. {
  1350. u16 event = (val & 0xffff);
  1351. int ret = 0;
  1352. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1353. struct snd_soc_component *component = wcd938x->component;
  1354. struct wcd_mbhc *mbhc;
  1355. switch (event) {
  1356. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1357. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1358. snd_soc_component_update_bits(component,
  1359. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1360. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1361. }
  1362. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1363. snd_soc_component_update_bits(component,
  1364. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1365. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1366. }
  1367. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1368. snd_soc_component_update_bits(component,
  1369. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1370. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1371. }
  1372. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1373. snd_soc_component_update_bits(component,
  1374. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1375. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1376. }
  1377. break;
  1378. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1379. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1380. 0xC0, 0x00);
  1381. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1382. 0x80, 0x00);
  1383. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1384. 0x80, 0x00);
  1385. break;
  1386. case BOLERO_WCD_EVT_SSR_DOWN:
  1387. wcd938x_reset_low(wcd938x->dev);
  1388. break;
  1389. case BOLERO_WCD_EVT_SSR_UP:
  1390. wcd938x_reset(wcd938x->dev);
  1391. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1392. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1393. regcache_mark_dirty(wcd938x->regmap);
  1394. regcache_sync(wcd938x->regmap);
  1395. /* Initialize MBHC module */
  1396. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1397. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1398. if (ret) {
  1399. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1400. __func__);
  1401. } else {
  1402. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1403. }
  1404. break;
  1405. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1406. snd_soc_component_update_bits(component,
  1407. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1408. ((val >> 0x10) << 0x01));
  1409. break;
  1410. default:
  1411. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1412. break;
  1413. }
  1414. return 0;
  1415. }
  1416. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1417. int event)
  1418. {
  1419. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1420. int micb_num;
  1421. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1422. __func__, w->name, event);
  1423. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1424. micb_num = MIC_BIAS_1;
  1425. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1426. micb_num = MIC_BIAS_2;
  1427. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1428. micb_num = MIC_BIAS_3;
  1429. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1430. micb_num = MIC_BIAS_4;
  1431. else
  1432. return -EINVAL;
  1433. switch (event) {
  1434. case SND_SOC_DAPM_PRE_PMU:
  1435. wcd938x_micbias_control(component, micb_num,
  1436. MICB_ENABLE, true);
  1437. break;
  1438. case SND_SOC_DAPM_POST_PMU:
  1439. /* 1 msec delay as per HW requirement */
  1440. usleep_range(1000, 1100);
  1441. break;
  1442. case SND_SOC_DAPM_POST_PMD:
  1443. wcd938x_micbias_control(component, micb_num,
  1444. MICB_DISABLE, true);
  1445. break;
  1446. };
  1447. return 0;
  1448. }
  1449. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1450. struct snd_kcontrol *kcontrol,
  1451. int event)
  1452. {
  1453. return __wcd938x_codec_enable_micbias(w, event);
  1454. }
  1455. static inline int wcd938x_tx_path_get(const char *wname)
  1456. {
  1457. int ret = 0;
  1458. unsigned int path_num;
  1459. char *widget_name = NULL;
  1460. char *w_name = NULL;
  1461. char *path_num_char = NULL;
  1462. char *path_name = NULL;
  1463. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  1464. if (!widget_name)
  1465. return -EINVAL;
  1466. w_name = widget_name;
  1467. path_name = strsep(&widget_name, " ");
  1468. if (!path_name) {
  1469. pr_err("%s: Invalid widget name = %s\n",
  1470. __func__, widget_name);
  1471. ret = -EINVAL;
  1472. goto err;
  1473. }
  1474. path_name = widget_name;
  1475. path_num_char = strpbrk(path_name, "0123");
  1476. if (!path_num_char) {
  1477. pr_err("%s: tx path index not found\n",
  1478. __func__);
  1479. ret = -EINVAL;
  1480. goto err;
  1481. }
  1482. ret = kstrtouint(path_num_char, 10, &path_num);
  1483. if (ret < 0)
  1484. pr_err("%s: Invalid tx path = %s\n",
  1485. __func__, w_name);
  1486. err:
  1487. kfree(w_name);
  1488. return ret;
  1489. }
  1490. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  1491. struct snd_ctl_elem_value *ucontrol)
  1492. {
  1493. struct snd_soc_dapm_widget *widget =
  1494. snd_soc_dapm_kcontrol_widget(kcontrol);
  1495. struct snd_soc_component *component =
  1496. snd_soc_kcontrol_component(kcontrol);
  1497. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1498. u32 path = 0;
  1499. if (!widget || !widget->name || !wcd938x || !component)
  1500. return -EINVAL;
  1501. path = wcd938x_tx_path_get(widget->name);
  1502. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  1503. return 0;
  1504. }
  1505. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  1506. struct snd_ctl_elem_value *ucontrol)
  1507. {
  1508. struct snd_soc_dapm_widget *widget =
  1509. snd_soc_dapm_kcontrol_widget(kcontrol);
  1510. struct snd_soc_component *component =
  1511. snd_soc_kcontrol_component(kcontrol);
  1512. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1513. u32 mode_val;
  1514. u32 path = 0;
  1515. if (!widget || !widget->name || !wcd938x || !component)
  1516. return -EINVAL;
  1517. path = wcd938x_tx_path_get(widget->name);
  1518. mode_val = ucontrol->value.enumerated.item[0];
  1519. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1520. wcd938x->tx_mode[path] = mode_val;
  1521. return 0;
  1522. }
  1523. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1524. struct snd_ctl_elem_value *ucontrol)
  1525. {
  1526. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1527. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1528. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  1529. return 0;
  1530. }
  1531. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1532. struct snd_ctl_elem_value *ucontrol)
  1533. {
  1534. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1535. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1536. u32 mode_val;
  1537. mode_val = ucontrol->value.enumerated.item[0];
  1538. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1539. if (mode_val == 0) {
  1540. dev_info(component->dev,
  1541. "%s:Invalid HPH Mode, default to class_AB\n",
  1542. __func__);
  1543. mode_val = 3; /* enum will be updated later */
  1544. }
  1545. wcd938x->hph_mode = mode_val;
  1546. return 0;
  1547. }
  1548. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  1549. struct snd_ctl_elem_value *ucontrol)
  1550. {
  1551. struct snd_soc_component *component =
  1552. snd_soc_kcontrol_component(kcontrol);
  1553. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1554. bool hphr;
  1555. struct soc_multi_mixer_control *mc;
  1556. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1557. hphr = mc->shift;
  1558. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  1559. wcd938x->comp1_enable;
  1560. return 0;
  1561. }
  1562. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  1563. struct snd_ctl_elem_value *ucontrol)
  1564. {
  1565. struct snd_soc_component *component =
  1566. snd_soc_kcontrol_component(kcontrol);
  1567. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1568. int value = ucontrol->value.integer.value[0];
  1569. bool hphr;
  1570. struct soc_multi_mixer_control *mc;
  1571. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1572. hphr = mc->shift;
  1573. if (hphr)
  1574. wcd938x->comp2_enable = value;
  1575. else
  1576. wcd938x->comp1_enable = value;
  1577. return 0;
  1578. }
  1579. static const char * const tx_mode_mux_text[] = {
  1580. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  1581. "ADC_ULP1", "ADC_ULP2",
  1582. };
  1583. static const struct soc_enum tx_mode_mux_enum =
  1584. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  1585. tx_mode_mux_text);
  1586. static const char * const rx_hph_mode_mux_text[] = {
  1587. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1588. "CLS_H_ULP", "CLS_AB_HIFI",
  1589. };
  1590. static const struct soc_enum rx_hph_mode_mux_enum =
  1591. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1592. rx_hph_mode_mux_text);
  1593. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  1594. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1595. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  1596. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  1597. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1598. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  1599. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1600. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  1601. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1602. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  1603. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1604. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1605. wcd938x_get_compander, wcd938x_set_compander),
  1606. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1607. wcd938x_get_compander, wcd938x_set_compander),
  1608. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  1609. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  1610. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  1611. analog_gain),
  1612. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  1613. analog_gain),
  1614. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  1615. analog_gain),
  1616. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  1617. analog_gain),
  1618. };
  1619. static const struct snd_kcontrol_new adc1_switch[] = {
  1620. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1621. };
  1622. static const struct snd_kcontrol_new adc2_switch[] = {
  1623. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1624. };
  1625. static const struct snd_kcontrol_new adc3_switch[] = {
  1626. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1627. };
  1628. static const struct snd_kcontrol_new adc4_switch[] = {
  1629. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1630. };
  1631. static const struct snd_kcontrol_new dmic1_switch[] = {
  1632. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1633. };
  1634. static const struct snd_kcontrol_new dmic2_switch[] = {
  1635. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1636. };
  1637. static const struct snd_kcontrol_new dmic3_switch[] = {
  1638. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1639. };
  1640. static const struct snd_kcontrol_new dmic4_switch[] = {
  1641. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1642. };
  1643. static const struct snd_kcontrol_new dmic5_switch[] = {
  1644. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1645. };
  1646. static const struct snd_kcontrol_new dmic6_switch[] = {
  1647. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1648. };
  1649. static const struct snd_kcontrol_new dmic7_switch[] = {
  1650. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1651. };
  1652. static const struct snd_kcontrol_new dmic8_switch[] = {
  1653. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1654. };
  1655. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1656. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1657. };
  1658. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1659. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1660. };
  1661. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1662. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1663. };
  1664. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1665. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1666. };
  1667. static const char * const adc2_mux_text[] = {
  1668. "INP2", "INP3"
  1669. };
  1670. static const struct soc_enum adc2_enum =
  1671. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  1672. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1673. static const struct snd_kcontrol_new tx_adc2_mux =
  1674. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1675. static const char * const adc3_mux_text[] = {
  1676. "INP4", "INP6"
  1677. };
  1678. static const struct soc_enum adc3_enum =
  1679. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  1680. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  1681. static const struct snd_kcontrol_new tx_adc3_mux =
  1682. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  1683. static const char * const adc4_mux_text[] = {
  1684. "INP5", "INP7"
  1685. };
  1686. static const struct soc_enum adc4_enum =
  1687. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  1688. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  1689. static const struct snd_kcontrol_new tx_adc4_mux =
  1690. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  1691. static const char * const rdac3_mux_text[] = {
  1692. "RX1", "RX3"
  1693. };
  1694. static const char * const hdr12_mux_text[] = {
  1695. "NO_HDR12", "HDR12"
  1696. };
  1697. static const struct soc_enum hdr12_enum =
  1698. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  1699. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  1700. static const struct snd_kcontrol_new tx_hdr12_mux =
  1701. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  1702. static const char * const hdr34_mux_text[] = {
  1703. "NO_HDR34", "HDR34"
  1704. };
  1705. static const struct soc_enum hdr34_enum =
  1706. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  1707. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  1708. static const struct snd_kcontrol_new tx_hdr34_mux =
  1709. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  1710. static const struct soc_enum rdac3_enum =
  1711. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  1712. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  1713. static const struct snd_kcontrol_new rx_rdac3_mux =
  1714. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  1715. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  1716. /*input widgets*/
  1717. SND_SOC_DAPM_INPUT("AMIC1"),
  1718. SND_SOC_DAPM_INPUT("AMIC2"),
  1719. SND_SOC_DAPM_INPUT("AMIC3"),
  1720. SND_SOC_DAPM_INPUT("AMIC4"),
  1721. SND_SOC_DAPM_INPUT("AMIC5"),
  1722. SND_SOC_DAPM_INPUT("AMIC6"),
  1723. SND_SOC_DAPM_INPUT("AMIC7"),
  1724. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  1725. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  1726. SND_SOC_DAPM_INPUT("IN3_AUX"),
  1727. /*tx widgets*/
  1728. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  1729. wcd938x_codec_enable_adc,
  1730. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1731. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  1732. wcd938x_codec_enable_adc,
  1733. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1734. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  1735. wcd938x_codec_enable_adc,
  1736. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1737. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  1738. wcd938x_codec_enable_adc,
  1739. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1740. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  1741. wcd938x_codec_enable_dmic,
  1742. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1743. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  1744. wcd938x_codec_enable_dmic,
  1745. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1746. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  1747. wcd938x_codec_enable_dmic,
  1748. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1749. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  1750. wcd938x_codec_enable_dmic,
  1751. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1752. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  1753. wcd938x_codec_enable_dmic,
  1754. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1755. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  1756. wcd938x_codec_enable_dmic,
  1757. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1758. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  1759. wcd938x_codec_enable_dmic,
  1760. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1761. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  1762. wcd938x_codec_enable_dmic,
  1763. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1764. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  1765. NULL, 0, wcd938x_enable_req,
  1766. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1767. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  1768. NULL, 0, wcd938x_enable_req,
  1769. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1770. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  1771. NULL, 0, wcd938x_enable_req,
  1772. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1773. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  1774. NULL, 0, wcd938x_enable_req,
  1775. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1776. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  1777. &tx_adc2_mux),
  1778. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  1779. &tx_adc3_mux),
  1780. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  1781. &tx_adc4_mux),
  1782. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  1783. &tx_hdr12_mux),
  1784. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  1785. &tx_hdr34_mux),
  1786. /*tx mixers*/
  1787. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  1788. adc1_switch, ARRAY_SIZE(adc1_switch),
  1789. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1790. SND_SOC_DAPM_POST_PMD),
  1791. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  1792. adc2_switch, ARRAY_SIZE(adc2_switch),
  1793. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1794. SND_SOC_DAPM_POST_PMD),
  1795. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  1796. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  1797. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1798. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
  1799. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  1800. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1801. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  1802. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  1803. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1804. SND_SOC_DAPM_POST_PMD),
  1805. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  1806. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  1807. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1808. SND_SOC_DAPM_POST_PMD),
  1809. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  1810. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  1811. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1812. SND_SOC_DAPM_POST_PMD),
  1813. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  1814. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  1815. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1816. SND_SOC_DAPM_POST_PMD),
  1817. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  1818. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  1819. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1820. SND_SOC_DAPM_POST_PMD),
  1821. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  1822. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  1823. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1824. SND_SOC_DAPM_POST_PMD),
  1825. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0,
  1826. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  1827. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1828. SND_SOC_DAPM_POST_PMD),
  1829. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0,
  1830. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  1831. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1832. SND_SOC_DAPM_POST_PMD),
  1833. /* micbias widgets*/
  1834. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  1835. wcd938x_codec_enable_micbias,
  1836. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1837. SND_SOC_DAPM_POST_PMD),
  1838. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  1839. wcd938x_codec_enable_micbias,
  1840. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1841. SND_SOC_DAPM_POST_PMD),
  1842. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  1843. wcd938x_codec_enable_micbias,
  1844. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1845. SND_SOC_DAPM_POST_PMD),
  1846. SND_SOC_DAPM_MICBIAS_E("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  1847. wcd938x_codec_enable_micbias,
  1848. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1849. SND_SOC_DAPM_POST_PMD),
  1850. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  1851. wcd938x_enable_clsh,
  1852. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1853. /*rx widgets*/
  1854. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  1855. wcd938x_codec_enable_ear_pa,
  1856. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1857. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1858. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  1859. wcd938x_codec_enable_aux_pa,
  1860. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1861. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1862. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  1863. wcd938x_codec_enable_hphl_pa,
  1864. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1865. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1866. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  1867. wcd938x_codec_enable_hphr_pa,
  1868. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1869. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1870. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  1871. wcd938x_codec_hphl_dac_event,
  1872. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1873. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1874. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  1875. wcd938x_codec_hphr_dac_event,
  1876. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1877. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1878. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  1879. wcd938x_codec_ear_dac_event,
  1880. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1881. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1882. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  1883. wcd938x_codec_aux_dac_event,
  1884. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1885. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1886. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  1887. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  1888. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  1889. SND_SOC_DAPM_POST_PMD),
  1890. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  1891. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  1892. SND_SOC_DAPM_POST_PMD),
  1893. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  1894. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  1895. SND_SOC_DAPM_POST_PMD),
  1896. /* rx mixer widgets*/
  1897. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  1898. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  1899. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  1900. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  1901. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  1902. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  1903. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  1904. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  1905. /*output widgets tx*/
  1906. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  1907. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  1908. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  1909. SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
  1910. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  1911. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  1912. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  1913. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  1914. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  1915. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  1916. SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
  1917. SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
  1918. /*output widgets rx*/
  1919. SND_SOC_DAPM_OUTPUT("EAR"),
  1920. SND_SOC_DAPM_OUTPUT("AUX"),
  1921. SND_SOC_DAPM_OUTPUT("HPHL"),
  1922. SND_SOC_DAPM_OUTPUT("HPHR"),
  1923. };
  1924. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  1925. {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
  1926. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  1927. {"ADC1 REQ", NULL, "ADC1"},
  1928. {"ADC1", NULL, "AMIC1"},
  1929. {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
  1930. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  1931. {"ADC2 REQ", NULL, "ADC2"},
  1932. {"ADC2", NULL, "HDR12 MUX"},
  1933. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  1934. {"HDR12 MUX", "HDR12", "AMIC1"},
  1935. {"ADC2 MUX", "INP3", "AMIC3"},
  1936. {"ADC2 MUX", "INP2", "AMIC2"},
  1937. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  1938. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  1939. {"ADC3 REQ", NULL, "ADC3"},
  1940. {"ADC3", NULL, "HDR34 MUX"},
  1941. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  1942. {"HDR34 MUX", "HDR34", "AMIC5"},
  1943. {"ADC3 MUX", "INP4", "AMIC4"},
  1944. {"ADC3 MUX", "INP6", "AMIC6"},
  1945. {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
  1946. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  1947. {"ADC4 REQ", NULL, "ADC4"},
  1948. {"ADC4", NULL, "ADC4 MUX"},
  1949. {"ADC4 MUX", "INP5", "AMIC5"},
  1950. {"ADC4 MUX", "INP7", "AMIC7"},
  1951. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  1952. {"DMIC1_MIXER", "Switch", "DMIC1"},
  1953. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  1954. {"DMIC2_MIXER", "Switch", "DMIC2"},
  1955. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  1956. {"DMIC3_MIXER", "Switch", "DMIC3"},
  1957. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  1958. {"DMIC4_MIXER", "Switch", "DMIC4"},
  1959. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  1960. {"DMIC5_MIXER", "Switch", "DMIC5"},
  1961. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  1962. {"DMIC6_MIXER", "Switch", "DMIC6"},
  1963. {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
  1964. {"DMIC7_MIXER", "Switch", "DMIC7"},
  1965. {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
  1966. {"DMIC8_MIXER", "Switch", "DMIC8"},
  1967. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  1968. {"RX1", NULL, "IN1_HPHL"},
  1969. {"RDAC1", NULL, "RX1"},
  1970. {"HPHL_RDAC", "Switch", "RDAC1"},
  1971. {"HPHL PGA", NULL, "HPHL_RDAC"},
  1972. {"HPHL", NULL, "HPHL PGA"},
  1973. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  1974. {"RX2", NULL, "IN2_HPHR"},
  1975. {"RDAC2", NULL, "RX2"},
  1976. {"HPHR_RDAC", "Switch", "RDAC2"},
  1977. {"HPHR PGA", NULL, "HPHR_RDAC"},
  1978. {"HPHR", NULL, "HPHR PGA"},
  1979. {"IN3_AUX", NULL, "CLS_H_PORT"},
  1980. {"RX3", NULL, "IN3_AUX"},
  1981. {"RDAC4", NULL, "RX3"},
  1982. {"AUX_RDAC", "Switch", "RDAC4"},
  1983. {"AUX PGA", NULL, "AUX_RDAC"},
  1984. {"AUX", NULL, "AUX PGA"},
  1985. {"RDAC3_MUX", "RX3", "RX3"},
  1986. {"RDAC3_MUX", "RX1", "RX1"},
  1987. {"RDAC3", NULL, "RDAC3_MUX"},
  1988. {"EAR_RDAC", "Switch", "RDAC3"},
  1989. {"EAR PGA", NULL, "EAR_RDAC"},
  1990. {"EAR", NULL, "EAR PGA"},
  1991. };
  1992. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  1993. void *file_private_data,
  1994. struct file *file,
  1995. char __user *buf, size_t count,
  1996. loff_t pos)
  1997. {
  1998. struct wcd938x_priv *priv;
  1999. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  2000. int len = 0;
  2001. priv = (struct wcd938x_priv *) entry->private_data;
  2002. if (!priv) {
  2003. pr_err("%s: wcd938x priv is null\n", __func__);
  2004. return -EINVAL;
  2005. }
  2006. switch (priv->version) {
  2007. case WCD938X_VERSION_1_0:
  2008. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  2009. break;
  2010. default:
  2011. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2012. }
  2013. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2014. }
  2015. static struct snd_info_entry_ops wcd938x_info_ops = {
  2016. .read = wcd938x_version_read,
  2017. };
  2018. /*
  2019. * wcd938x_info_create_codec_entry - creates wcd938x module
  2020. * @codec_root: The parent directory
  2021. * @component: component instance
  2022. *
  2023. * Creates wcd938x module and version entry under the given
  2024. * parent directory.
  2025. *
  2026. * Return: 0 on success or negative error code on failure.
  2027. */
  2028. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2029. struct snd_soc_component *component)
  2030. {
  2031. struct snd_info_entry *version_entry;
  2032. struct wcd938x_priv *priv;
  2033. struct snd_soc_card *card;
  2034. if (!codec_root || !component)
  2035. return -EINVAL;
  2036. priv = snd_soc_component_get_drvdata(component);
  2037. if (priv->entry) {
  2038. dev_dbg(priv->dev,
  2039. "%s:wcd938x module already created\n", __func__);
  2040. return 0;
  2041. }
  2042. card = component->card;
  2043. priv->entry = snd_info_create_subdir(codec_root->module,
  2044. "wcd938x", codec_root);
  2045. if (!priv->entry) {
  2046. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  2047. __func__);
  2048. return -ENOMEM;
  2049. }
  2050. version_entry = snd_info_create_card_entry(card->snd_card,
  2051. "version",
  2052. priv->entry);
  2053. if (!version_entry) {
  2054. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  2055. __func__);
  2056. return -ENOMEM;
  2057. }
  2058. version_entry->private_data = priv;
  2059. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  2060. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2061. version_entry->c.ops = &wcd938x_info_ops;
  2062. if (snd_info_register(version_entry) < 0) {
  2063. snd_info_free_entry(version_entry);
  2064. return -ENOMEM;
  2065. }
  2066. priv->version_entry = version_entry;
  2067. return 0;
  2068. }
  2069. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  2070. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  2071. {
  2072. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2073. struct snd_soc_dapm_context *dapm =
  2074. snd_soc_component_get_dapm(component);
  2075. int variant;
  2076. int ret = -EINVAL;
  2077. dev_info(component->dev, "%s()\n", __func__);
  2078. wcd938x = snd_soc_component_get_drvdata(component);
  2079. if (!wcd938x)
  2080. return -EINVAL;
  2081. wcd938x->component = component;
  2082. snd_soc_component_init_regmap(component, wcd938x->regmap);
  2083. variant = (snd_soc_component_read32(component,
  2084. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2085. wcd938x->variant = variant;
  2086. wcd938x->fw_data = devm_kzalloc(component->dev,
  2087. sizeof(*(wcd938x->fw_data)),
  2088. GFP_KERNEL);
  2089. if (!wcd938x->fw_data) {
  2090. dev_err(component->dev, "Failed to allocate fw_data\n");
  2091. ret = -ENOMEM;
  2092. goto err;
  2093. }
  2094. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  2095. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  2096. WCD9XXX_CODEC_HWDEP_NODE, component);
  2097. if (ret < 0) {
  2098. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2099. goto err_hwdep;
  2100. }
  2101. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  2102. if (ret) {
  2103. pr_err("%s: mbhc initialization failed\n", __func__);
  2104. goto err_hwdep;
  2105. }
  2106. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2107. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2108. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2109. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2110. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  2111. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  2112. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  2113. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2114. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2115. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2116. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2117. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2118. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2119. snd_soc_dapm_ignore_suspend(dapm, "DMIC7_OUTPUT");
  2120. snd_soc_dapm_ignore_suspend(dapm, "DMIC8_OUTPUT");
  2121. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2122. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2123. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2124. snd_soc_dapm_ignore_suspend(dapm, "ADC4_OUTPUT");
  2125. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2126. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2127. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2128. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2129. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2130. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2131. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2132. snd_soc_dapm_sync(dapm);
  2133. wcd_cls_h_init(&wcd938x->clsh_info);
  2134. wcd938x_init_reg(component);
  2135. wcd938x->version = WCD938X_VERSION_1_0;
  2136. /* Register event notifier */
  2137. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  2138. if (wcd938x->register_notifier) {
  2139. ret = wcd938x->register_notifier(wcd938x->handle,
  2140. &wcd938x->nblock,
  2141. true);
  2142. if (ret) {
  2143. dev_err(component->dev,
  2144. "%s: Failed to register notifier %d\n",
  2145. __func__, ret);
  2146. return ret;
  2147. }
  2148. }
  2149. return ret;
  2150. err_hwdep:
  2151. wcd938x->fw_data = NULL;
  2152. err:
  2153. return ret;
  2154. }
  2155. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  2156. {
  2157. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2158. if (!wcd938x) {
  2159. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  2160. __func__);
  2161. return;
  2162. }
  2163. if (wcd938x->register_notifier)
  2164. wcd938x->register_notifier(wcd938x->handle,
  2165. &wcd938x->nblock,
  2166. false);
  2167. }
  2168. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  2169. .name = WCD938X_DRV_NAME,
  2170. .probe = wcd938x_soc_codec_probe,
  2171. .remove = wcd938x_soc_codec_remove,
  2172. .controls = wcd938x_snd_controls,
  2173. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  2174. .dapm_widgets = wcd938x_dapm_widgets,
  2175. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  2176. .dapm_routes = wcd938x_audio_map,
  2177. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  2178. };
  2179. static int wcd938x_reset(struct device *dev)
  2180. {
  2181. struct wcd938x_priv *wcd938x = NULL;
  2182. int rc = 0;
  2183. int value = 0;
  2184. if (!dev)
  2185. return -ENODEV;
  2186. wcd938x = dev_get_drvdata(dev);
  2187. if (!wcd938x)
  2188. return -EINVAL;
  2189. if (!wcd938x->rst_np) {
  2190. dev_err(dev, "%s: reset gpio device node not specified\n",
  2191. __func__);
  2192. return -EINVAL;
  2193. }
  2194. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  2195. if (value > 0)
  2196. return 0;
  2197. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2198. if (rc) {
  2199. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2200. __func__);
  2201. return rc;
  2202. }
  2203. /* 20us sleep required after pulling the reset gpio to LOW */
  2204. usleep_range(20, 30);
  2205. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  2206. if (rc) {
  2207. dev_err(dev, "%s: wcd active state request fail!\n",
  2208. __func__);
  2209. return rc;
  2210. }
  2211. /* 20us sleep required after pulling the reset gpio to HIGH */
  2212. usleep_range(20, 30);
  2213. return rc;
  2214. }
  2215. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  2216. u32 *val)
  2217. {
  2218. int rc = 0;
  2219. rc = of_property_read_u32(dev->of_node, name, val);
  2220. if (rc)
  2221. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2222. __func__, name, dev->of_node->full_name);
  2223. return rc;
  2224. }
  2225. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  2226. struct wcd938x_micbias_setting *mb)
  2227. {
  2228. u32 prop_val = 0;
  2229. int rc = 0;
  2230. /* MB1 */
  2231. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2232. NULL)) {
  2233. rc = wcd938x_read_of_property_u32(dev,
  2234. "qcom,cdc-micbias1-mv",
  2235. &prop_val);
  2236. if (!rc)
  2237. mb->micb1_mv = prop_val;
  2238. } else {
  2239. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2240. __func__);
  2241. }
  2242. /* MB2 */
  2243. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2244. NULL)) {
  2245. rc = wcd938x_read_of_property_u32(dev,
  2246. "qcom,cdc-micbias2-mv",
  2247. &prop_val);
  2248. if (!rc)
  2249. mb->micb2_mv = prop_val;
  2250. } else {
  2251. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2252. __func__);
  2253. }
  2254. /* MB3 */
  2255. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2256. NULL)) {
  2257. rc = wcd938x_read_of_property_u32(dev,
  2258. "qcom,cdc-micbias3-mv",
  2259. &prop_val);
  2260. if (!rc)
  2261. mb->micb3_mv = prop_val;
  2262. } else {
  2263. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2264. __func__);
  2265. }
  2266. }
  2267. static int wcd938x_reset_low(struct device *dev)
  2268. {
  2269. struct wcd938x_priv *wcd938x = NULL;
  2270. int rc = 0;
  2271. if (!dev)
  2272. return -ENODEV;
  2273. wcd938x = dev_get_drvdata(dev);
  2274. if (!wcd938x)
  2275. return -EINVAL;
  2276. if (!wcd938x->rst_np) {
  2277. dev_err(dev, "%s: reset gpio device node not specified\n",
  2278. __func__);
  2279. return -EINVAL;
  2280. }
  2281. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2282. if (rc) {
  2283. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2284. __func__);
  2285. return rc;
  2286. }
  2287. /* 20us sleep required after pulling the reset gpio to LOW */
  2288. usleep_range(20, 30);
  2289. return rc;
  2290. }
  2291. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  2292. {
  2293. struct wcd938x_pdata *pdata = NULL;
  2294. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  2295. GFP_KERNEL);
  2296. if (!pdata)
  2297. return NULL;
  2298. pdata->rst_np = of_parse_phandle(dev->of_node,
  2299. "qcom,wcd-rst-gpio-node", 0);
  2300. if (!pdata->rst_np) {
  2301. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2302. __func__, "qcom,wcd-rst-gpio-node",
  2303. dev->of_node->full_name);
  2304. return NULL;
  2305. }
  2306. /* Parse power supplies */
  2307. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2308. &pdata->num_supplies);
  2309. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2310. dev_err(dev, "%s: no power supplies defined for codec\n",
  2311. __func__);
  2312. return NULL;
  2313. }
  2314. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2315. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2316. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  2317. return pdata;
  2318. }
  2319. static int wcd938x_bind(struct device *dev)
  2320. {
  2321. int ret = 0, i = 0;
  2322. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  2323. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2324. /*
  2325. * Add 5msec delay to provide sufficient time for
  2326. * soundwire auto enumeration of slave devices as
  2327. * as per HW requirement.
  2328. */
  2329. usleep_range(5000, 5010);
  2330. ret = component_bind_all(dev, wcd938x);
  2331. if (ret) {
  2332. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2333. __func__, ret);
  2334. return ret;
  2335. }
  2336. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2337. if (!wcd938x->rx_swr_dev) {
  2338. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2339. __func__);
  2340. ret = -ENODEV;
  2341. goto err;
  2342. }
  2343. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2344. if (!wcd938x->tx_swr_dev) {
  2345. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2346. __func__);
  2347. ret = -ENODEV;
  2348. goto err;
  2349. }
  2350. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  2351. &wcd938x_regmap_config);
  2352. if (!wcd938x->regmap) {
  2353. dev_err(dev, "%s: Regmap init failed\n",
  2354. __func__);
  2355. goto err;
  2356. }
  2357. /* Set all interupts as edge triggered */
  2358. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  2359. regmap_write(wcd938x->regmap,
  2360. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2361. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  2362. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  2363. wcd938x->irq_info.codec_name = "WCD938X";
  2364. wcd938x->irq_info.regmap = wcd938x->regmap;
  2365. wcd938x->irq_info.dev = dev;
  2366. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  2367. if (ret) {
  2368. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  2369. __func__, ret);
  2370. goto err;
  2371. }
  2372. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  2373. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  2374. NULL, 0);
  2375. if (ret) {
  2376. dev_err(dev, "%s: Codec registration failed\n",
  2377. __func__);
  2378. goto err_irq;
  2379. }
  2380. return ret;
  2381. err_irq:
  2382. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2383. err:
  2384. component_unbind_all(dev, wcd938x);
  2385. return ret;
  2386. }
  2387. static void wcd938x_unbind(struct device *dev)
  2388. {
  2389. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2390. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2391. snd_soc_unregister_component(dev);
  2392. component_unbind_all(dev, wcd938x);
  2393. }
  2394. static const struct of_device_id wcd938x_dt_match[] = {
  2395. { .compatible = "qcom,wcd938x-codec" },
  2396. {}
  2397. };
  2398. static const struct component_master_ops wcd938x_comp_ops = {
  2399. .bind = wcd938x_bind,
  2400. .unbind = wcd938x_unbind,
  2401. };
  2402. static int wcd938x_compare_of(struct device *dev, void *data)
  2403. {
  2404. return dev->of_node == data;
  2405. }
  2406. static void wcd938x_release_of(struct device *dev, void *data)
  2407. {
  2408. of_node_put(data);
  2409. }
  2410. static int wcd938x_add_slave_components(struct device *dev,
  2411. struct component_match **matchptr)
  2412. {
  2413. struct device_node *np, *rx_node, *tx_node;
  2414. np = dev->of_node;
  2415. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2416. if (!rx_node) {
  2417. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2418. return -ENODEV;
  2419. }
  2420. of_node_get(rx_node);
  2421. component_match_add_release(dev, matchptr,
  2422. wcd938x_release_of,
  2423. wcd938x_compare_of,
  2424. rx_node);
  2425. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  2426. if (!tx_node) {
  2427. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2428. return -ENODEV;
  2429. }
  2430. of_node_get(tx_node);
  2431. component_match_add_release(dev, matchptr,
  2432. wcd938x_release_of,
  2433. wcd938x_compare_of,
  2434. tx_node);
  2435. return 0;
  2436. }
  2437. static int wcd938x_wakeup(void *handle, bool enable)
  2438. {
  2439. struct wcd938x_priv *priv;
  2440. if (!handle) {
  2441. pr_err("%s: NULL handle\n", __func__);
  2442. return -EINVAL;
  2443. }
  2444. priv = (struct wcd938x_priv *)handle;
  2445. if (!priv->tx_swr_dev) {
  2446. pr_err("%s: tx swr dev is NULL\n", __func__);
  2447. return -EINVAL;
  2448. }
  2449. if (enable)
  2450. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2451. else
  2452. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2453. }
  2454. static int wcd938x_probe(struct platform_device *pdev)
  2455. {
  2456. struct component_match *match = NULL;
  2457. struct wcd938x_priv *wcd938x = NULL;
  2458. struct wcd938x_pdata *pdata = NULL;
  2459. struct wcd_ctrl_platform_data *plat_data = NULL;
  2460. struct device *dev = &pdev->dev;
  2461. int ret;
  2462. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  2463. GFP_KERNEL);
  2464. if (!wcd938x)
  2465. return -ENOMEM;
  2466. dev_set_drvdata(dev, wcd938x);
  2467. pdata = wcd938x_populate_dt_data(dev);
  2468. if (!pdata) {
  2469. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2470. return -EINVAL;
  2471. }
  2472. dev->platform_data = pdata;
  2473. wcd938x->rst_np = pdata->rst_np;
  2474. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  2475. pdata->regulator, pdata->num_supplies);
  2476. if (!wcd938x->supplies) {
  2477. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2478. __func__);
  2479. return ret;
  2480. }
  2481. plat_data = dev_get_platdata(dev->parent);
  2482. if (!plat_data) {
  2483. dev_err(dev, "%s: platform data from parent is NULL\n",
  2484. __func__);
  2485. return -EINVAL;
  2486. }
  2487. wcd938x->handle = (void *)plat_data->handle;
  2488. if (!wcd938x->handle) {
  2489. dev_err(dev, "%s: handle is NULL\n", __func__);
  2490. return -EINVAL;
  2491. }
  2492. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  2493. if (!wcd938x->update_wcd_event) {
  2494. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2495. __func__);
  2496. return -EINVAL;
  2497. }
  2498. wcd938x->register_notifier = plat_data->register_notifier;
  2499. if (!wcd938x->register_notifier) {
  2500. dev_err(dev, "%s: register_notifier api is null!\n",
  2501. __func__);
  2502. return -EINVAL;
  2503. }
  2504. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  2505. pdata->regulator,
  2506. pdata->num_supplies);
  2507. if (ret) {
  2508. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2509. __func__);
  2510. return ret;
  2511. }
  2512. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  2513. CODEC_RX);
  2514. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  2515. CODEC_TX);
  2516. if (ret) {
  2517. dev_err(dev, "Failed to read port mapping\n");
  2518. goto err;
  2519. }
  2520. ret = wcd938x_add_slave_components(dev, &match);
  2521. if (ret)
  2522. goto err;
  2523. wcd938x_reset(dev);
  2524. wcd938x->wakeup = wcd938x_wakeup;
  2525. return component_master_add_with_match(dev,
  2526. &wcd938x_comp_ops, match);
  2527. err:
  2528. return ret;
  2529. }
  2530. static int wcd938x_remove(struct platform_device *pdev)
  2531. {
  2532. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  2533. dev_set_drvdata(&pdev->dev, NULL);
  2534. return 0;
  2535. }
  2536. #ifdef CONFIG_PM_SLEEP
  2537. static int wcd938x_suspend(struct device *dev)
  2538. {
  2539. return 0;
  2540. }
  2541. static int wcd938x_resume(struct device *dev)
  2542. {
  2543. return 0;
  2544. }
  2545. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  2546. SET_SYSTEM_SLEEP_PM_OPS(
  2547. wcd938x_suspend,
  2548. wcd938x_resume
  2549. )
  2550. };
  2551. #endif
  2552. static struct platform_driver wcd938x_codec_driver = {
  2553. .probe = wcd938x_probe,
  2554. .remove = wcd938x_remove,
  2555. .driver = {
  2556. .name = "wcd938x_codec",
  2557. .owner = THIS_MODULE,
  2558. .of_match_table = of_match_ptr(wcd938x_dt_match),
  2559. #ifdef CONFIG_PM_SLEEP
  2560. .pm = &wcd938x_dev_pm_ops,
  2561. #endif
  2562. },
  2563. };
  2564. module_platform_driver(wcd938x_codec_driver);
  2565. MODULE_DESCRIPTION("WCD938X Codec driver");
  2566. MODULE_LICENSE("GPL v2");