sde_kms.c 130 KB

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  1. /*
  2. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  3. * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (C) 2013 Red Hat
  5. * Author: Rob Clark <[email protected]>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  20. #include <drm/drm_crtc.h>
  21. #include <drm/drm_fixed.h>
  22. #include <drm/drm_panel.h>
  23. #include <linux/debugfs.h>
  24. #include <linux/of_address.h>
  25. #include <linux/of_irq.h>
  26. #include <linux/dma-buf.h>
  27. #include <linux/memblock.h>
  28. #include <linux/soc/qcom/panel_event_notifier.h>
  29. #include <drm/drm_atomic_uapi.h>
  30. #include <drm/drm_probe_helper.h>
  31. #include "msm_drv.h"
  32. #include "msm_mmu.h"
  33. #include "msm_gem.h"
  34. #include "dsi_display.h"
  35. #include "dsi_drm.h"
  36. #include "sde_wb.h"
  37. #include "dp_display.h"
  38. #include "dp_drm.h"
  39. #include "dp_mst_drm.h"
  40. #include "sde_kms.h"
  41. #include "sde_core_irq.h"
  42. #include "sde_formats.h"
  43. #include "sde_hw_vbif.h"
  44. #include "sde_vbif.h"
  45. #include "sde_encoder.h"
  46. #include "sde_plane.h"
  47. #include "sde_crtc.h"
  48. #include "sde_color_processing.h"
  49. #include "sde_reg_dma.h"
  50. #include "sde_connector.h"
  51. #include "sde_vm.h"
  52. #include <linux/qcom_scm.h>
  53. #include <linux/qcom-iommu-util.h>
  54. #include "soc/qcom/secure_buffer.h"
  55. #include <linux/qtee_shmbridge.h>
  56. #ifdef CONFIG_DRM_SDE_VM
  57. #include <linux/gunyah/gh_irq_lend.h>
  58. #endif
  59. #define CREATE_TRACE_POINTS
  60. #include "sde_trace.h"
  61. /* defines for secure channel call */
  62. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  63. #define MDP_DEVICE_ID 0x1A
  64. #define DEMURA_REGION_NAME_MAX 32
  65. EXPORT_TRACEPOINT_SYMBOL(tracing_mark_write);
  66. static const char * const iommu_ports[] = {
  67. "mdp_0",
  68. };
  69. /**
  70. * Controls size of event log buffer. Specified as a power of 2.
  71. */
  72. #define SDE_EVTLOG_SIZE 1024
  73. /*
  74. * To enable overall DRM driver logging
  75. * # echo 0x2 > /sys/module/drm/parameters/debug
  76. *
  77. * To enable DRM driver h/w logging
  78. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  79. *
  80. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  81. */
  82. #define SDE_DEBUGFS_DIR "msm_sde"
  83. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  84. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  85. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  86. /**
  87. * sdecustom - enable certain driver customizations for sde clients
  88. * Enabling this modifies the standard DRM behavior slightly and assumes
  89. * that the clients have specific knowledge about the modifications that
  90. * are involved, so don't enable this unless you know what you're doing.
  91. *
  92. * Parts of the driver that are affected by this setting may be located by
  93. * searching for invocations of the 'sde_is_custom_client()' function.
  94. *
  95. * This is disabled by default.
  96. */
  97. static bool sdecustom = true;
  98. module_param(sdecustom, bool, 0400);
  99. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  100. static int sde_kms_hw_init(struct msm_kms *kms);
  101. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  102. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  103. static int _sde_kms_register_events(struct msm_kms *kms,
  104. struct drm_mode_object *obj, u32 event, bool en);
  105. bool sde_is_custom_client(void)
  106. {
  107. return sdecustom;
  108. }
  109. #if IS_ENABLED(CONFIG_DEBUG_FS)
  110. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  111. {
  112. struct msm_drm_private *priv;
  113. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  114. return NULL;
  115. priv = sde_kms->dev->dev_private;
  116. return priv->debug_root;
  117. }
  118. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  119. {
  120. void *p;
  121. int rc;
  122. void *debugfs_root;
  123. p = sde_hw_util_get_log_mask_ptr();
  124. if (!sde_kms || !p)
  125. return -EINVAL;
  126. debugfs_root = sde_debugfs_get_root(sde_kms);
  127. if (!debugfs_root)
  128. return -EINVAL;
  129. /* allow debugfs_root to be NULL */
  130. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  131. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  132. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  133. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  134. if (rc) {
  135. SDE_ERROR("failed to init perf %d\n", rc);
  136. return rc;
  137. }
  138. sde_rm_debugfs_init(&sde_kms->rm, debugfs_root);
  139. if (sde_kms->catalog->qdss_count)
  140. debugfs_create_u32("qdss", 0600, debugfs_root,
  141. (u32 *)&sde_kms->qdss_enabled);
  142. debugfs_create_u32("pm_suspend_clk_dump", 0600, debugfs_root,
  143. (u32 *)&sde_kms->pm_suspend_clk_dump);
  144. return 0;
  145. }
  146. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  147. {
  148. struct sde_kms *sde_kms = to_sde_kms(kms);
  149. /* don't need to NULL check debugfs_root */
  150. if (sde_kms) {
  151. sde_debugfs_vbif_destroy(sde_kms);
  152. sde_debugfs_core_irq_destroy(sde_kms);
  153. }
  154. }
  155. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  156. {
  157. int i;
  158. struct device *dev = sde_kms->dev->dev;
  159. SDE_INFO("runtime PM suspended:%d", pm_runtime_suspended(dev));
  160. for (i = 0; i < sde_kms->dsi_display_count; i++)
  161. dsi_display_dump_clks_state(sde_kms->dsi_displays[i]);
  162. return 0;
  163. }
  164. #else
  165. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  166. {
  167. return 0;
  168. }
  169. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  170. {
  171. }
  172. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  173. {
  174. return 0;
  175. }
  176. #endif /* CONFIG_DEBUG_FS */
  177. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  178. struct drm_crtc *crtc)
  179. {
  180. struct drm_encoder *encoder;
  181. struct drm_device *dev;
  182. int ret;
  183. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  184. SDE_ERROR("invalid params\n");
  185. return;
  186. }
  187. if (!crtc->state->enable) {
  188. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  189. return;
  190. }
  191. if (!crtc->state->active) {
  192. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  193. return;
  194. }
  195. dev = crtc->dev;
  196. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  197. if (encoder->crtc != crtc)
  198. continue;
  199. /*
  200. * Video Mode - Wait for VSYNC
  201. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  202. * complete
  203. */
  204. SDE_EVT32_VERBOSE(DRMID(crtc));
  205. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  206. if (ret && ret != -EWOULDBLOCK) {
  207. SDE_ERROR(
  208. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  209. crtc->base.id, encoder->base.id, ret);
  210. break;
  211. }
  212. }
  213. }
  214. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  215. struct drm_crtc *crtc, bool enable)
  216. {
  217. struct drm_device *dev;
  218. struct msm_drm_private *priv;
  219. struct sde_mdss_cfg *sde_cfg;
  220. struct drm_plane *plane;
  221. int i, ret;
  222. dev = sde_kms->dev;
  223. priv = dev->dev_private;
  224. sde_cfg = sde_kms->catalog;
  225. ret = sde_vbif_halt_xin_mask(sde_kms,
  226. sde_cfg->sui_block_xin_mask, enable);
  227. if (ret) {
  228. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  229. return ret;
  230. }
  231. if (enable) {
  232. for (i = 0; i < priv->num_planes; i++) {
  233. plane = priv->planes[i];
  234. sde_plane_secure_ctrl_xin_client(plane, crtc);
  235. }
  236. }
  237. return 0;
  238. }
  239. /**
  240. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  241. * @sde_kms: Pointer to sde_kms struct
  242. * @vimd: switch the stage 2 translation to this VMID
  243. */
  244. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  245. {
  246. struct device dummy = {};
  247. dma_addr_t dma_handle;
  248. uint32_t num_sids;
  249. uint32_t *sec_sid;
  250. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  251. int ret = 0, i;
  252. struct qtee_shm shm;
  253. bool qtee_en = qtee_shmbridge_is_enabled();
  254. phys_addr_t mem_addr;
  255. u64 mem_size;
  256. num_sids = sde_cfg->sec_sid_mask_count;
  257. if (!num_sids) {
  258. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  259. return -EINVAL;
  260. }
  261. if (qtee_en) {
  262. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  263. &shm);
  264. if (ret)
  265. return -ENOMEM;
  266. sec_sid = (uint32_t *) shm.vaddr;
  267. mem_addr = shm.paddr;
  268. /**
  269. * SMMUSecureModeSwitch requires the size to be number of SID's
  270. * but shm allocates size in pages. Modify the args as per
  271. * client requirement.
  272. */
  273. mem_size = sizeof(uint32_t) * num_sids;
  274. } else {
  275. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  276. if (!sec_sid)
  277. return -ENOMEM;
  278. mem_addr = virt_to_phys(sec_sid);
  279. mem_size = sizeof(uint32_t) * num_sids;
  280. }
  281. for (i = 0; i < num_sids; i++) {
  282. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  283. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  284. }
  285. ret = dma_coerce_mask_and_coherent(&dummy, DMA_BIT_MASK(64));
  286. if (ret) {
  287. SDE_ERROR("Failed to set dma mask for dummy dev %d\n", ret);
  288. goto map_error;
  289. }
  290. set_dma_ops(&dummy, NULL);
  291. dma_handle = dma_map_single(&dummy, sec_sid,
  292. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  293. if (dma_mapping_error(&dummy, dma_handle)) {
  294. SDE_ERROR("dma_map_single for dummy dev failed vmid 0x%x\n",
  295. vmid);
  296. goto map_error;
  297. }
  298. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  299. vmid, num_sids, qtee_en);
  300. ret = qcom_scm_mem_protect_sd_ctrl(MDP_DEVICE_ID, mem_addr,
  301. mem_size, vmid);
  302. if (ret)
  303. SDE_ERROR("Error:scm_call2, vmid %d, ret%d\n",
  304. vmid, ret);
  305. SDE_EVT32(MEM_PROTECT_SD_CTRL_SWITCH, MDP_DEVICE_ID, mem_size,
  306. vmid, qtee_en, num_sids, ret);
  307. dma_unmap_single(&dummy, dma_handle,
  308. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  309. map_error:
  310. if (qtee_en)
  311. qtee_shmbridge_free_shm(&shm);
  312. else
  313. kfree(sec_sid);
  314. return ret;
  315. }
  316. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  317. {
  318. u32 ret;
  319. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  320. return 0;
  321. /* detach_all_contexts */
  322. ret = sde_kms_mmu_detach(sde_kms, false);
  323. if (ret) {
  324. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  325. goto mmu_error;
  326. }
  327. ret = _sde_kms_scm_call(sde_kms, vmid);
  328. if (ret) {
  329. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  330. goto scm_error;
  331. }
  332. return 0;
  333. scm_error:
  334. sde_kms_mmu_attach(sde_kms, false);
  335. mmu_error:
  336. atomic_dec(&sde_kms->detach_all_cb);
  337. return ret;
  338. }
  339. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, u32 vmid,
  340. u32 old_vmid)
  341. {
  342. u32 ret;
  343. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  344. return 0;
  345. ret = _sde_kms_scm_call(sde_kms, vmid);
  346. if (ret) {
  347. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  348. goto scm_error;
  349. }
  350. /* attach_all_contexts */
  351. ret = sde_kms_mmu_attach(sde_kms, false);
  352. if (ret) {
  353. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  354. goto mmu_error;
  355. }
  356. return 0;
  357. mmu_error:
  358. _sde_kms_scm_call(sde_kms, old_vmid);
  359. scm_error:
  360. atomic_inc(&sde_kms->detach_all_cb);
  361. return ret;
  362. }
  363. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  364. {
  365. u32 ret;
  366. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  367. return 0;
  368. /* detach secure_context */
  369. ret = sde_kms_mmu_detach(sde_kms, true);
  370. if (ret) {
  371. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  372. goto mmu_error;
  373. }
  374. ret = _sde_kms_scm_call(sde_kms, vmid);
  375. if (ret) {
  376. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  377. goto scm_error;
  378. }
  379. return 0;
  380. scm_error:
  381. sde_kms_mmu_attach(sde_kms, true);
  382. mmu_error:
  383. atomic_dec(&sde_kms->detach_sec_cb);
  384. return ret;
  385. }
  386. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, u32 vmid,
  387. u32 old_vmid)
  388. {
  389. u32 ret;
  390. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  391. return 0;
  392. ret = _sde_kms_scm_call(sde_kms, vmid);
  393. if (ret) {
  394. goto scm_error;
  395. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  396. }
  397. ret = sde_kms_mmu_attach(sde_kms, true);
  398. if (ret) {
  399. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  400. goto mmu_error;
  401. }
  402. return 0;
  403. mmu_error:
  404. _sde_kms_scm_call(sde_kms, old_vmid);
  405. scm_error:
  406. atomic_inc(&sde_kms->detach_sec_cb);
  407. return ret;
  408. }
  409. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  410. struct drm_crtc *crtc, bool enable)
  411. {
  412. int ret;
  413. if (enable) {
  414. ret = pm_runtime_resume_and_get(sde_kms->dev->dev);
  415. if (ret < 0) {
  416. SDE_ERROR("failed to enable power resource %d\n", ret);
  417. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  418. return ret;
  419. }
  420. sde_crtc_misr_setup(crtc, true, 1);
  421. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  422. if (ret) {
  423. sde_crtc_misr_setup(crtc, false, 0);
  424. pm_runtime_put_sync(sde_kms->dev->dev);
  425. return ret;
  426. }
  427. } else {
  428. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  429. sde_crtc_misr_setup(crtc, false, 0);
  430. pm_runtime_put_sync(sde_kms->dev->dev);
  431. }
  432. return 0;
  433. }
  434. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  435. bool post_commit)
  436. {
  437. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  438. int old_smmu_state = smmu_state->state;
  439. int ret = 0;
  440. u32 vmid;
  441. if (!sde_kms || !crtc) {
  442. SDE_ERROR("invalid argument(s)\n");
  443. return -EINVAL;
  444. }
  445. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  446. post_commit, smmu_state->sui_misr_state,
  447. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  448. if ((!smmu_state->transition_type) ||
  449. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  450. /* Bail out */
  451. return 0;
  452. /* enable sui misr if requested, before the transition */
  453. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  454. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  455. if (ret) {
  456. smmu_state->sui_misr_state = NONE;
  457. goto end;
  458. }
  459. }
  460. mutex_lock(&sde_kms->secure_transition_lock);
  461. switch (smmu_state->state) {
  462. case DETACH_ALL_REQ:
  463. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  464. if (!ret)
  465. smmu_state->state = DETACHED;
  466. break;
  467. case ATTACH_ALL_REQ:
  468. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL,
  469. VMID_CP_SEC_DISPLAY);
  470. if (!ret) {
  471. smmu_state->state = ATTACHED;
  472. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  473. }
  474. break;
  475. case DETACH_SEC_REQ:
  476. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  477. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  478. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  479. if (!ret)
  480. smmu_state->state = DETACHED_SEC;
  481. break;
  482. case ATTACH_SEC_REQ:
  483. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  484. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  485. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL, vmid);
  486. if (!ret) {
  487. smmu_state->state = ATTACHED;
  488. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  489. }
  490. break;
  491. default:
  492. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  493. DRMID(crtc), smmu_state->state,
  494. smmu_state->transition_type);
  495. ret = -EINVAL;
  496. break;
  497. }
  498. mutex_unlock(&sde_kms->secure_transition_lock);
  499. /* disable sui misr if requested, after the transition */
  500. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  501. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  502. if (ret)
  503. goto end;
  504. }
  505. end:
  506. smmu_state->transition_error = false;
  507. if (ret) {
  508. smmu_state->transition_error = true;
  509. SDE_ERROR(
  510. "crtc%d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  511. DRMID(crtc), old_smmu_state, smmu_state->state,
  512. smmu_state->secure_level, ret);
  513. smmu_state->state = smmu_state->prev_state;
  514. smmu_state->secure_level = smmu_state->prev_secure_level;
  515. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ)
  516. _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  517. }
  518. SDE_DEBUG("crtc %d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  519. DRMID(crtc), old_smmu_state, smmu_state->state,
  520. smmu_state->secure_level, ret);
  521. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->prev_state,
  522. smmu_state->transition_type,
  523. smmu_state->transition_error,
  524. smmu_state->secure_level, smmu_state->prev_secure_level,
  525. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  526. smmu_state->sui_misr_state = NONE;
  527. smmu_state->transition_type = NONE;
  528. return ret;
  529. }
  530. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  531. struct drm_atomic_state *state)
  532. {
  533. struct drm_crtc *crtc;
  534. struct drm_crtc_state *old_crtc_state;
  535. struct drm_plane_state *old_plane_state, *new_plane_state;
  536. struct drm_plane *plane;
  537. struct drm_plane_state *plane_state;
  538. struct sde_kms *sde_kms = to_sde_kms(kms);
  539. struct drm_device *dev = sde_kms->dev;
  540. int i, ops = 0, ret = 0;
  541. bool old_valid_fb = false;
  542. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  543. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  544. if (!crtc->state || !crtc->state->active)
  545. continue;
  546. /*
  547. * It is safe to assume only one active crtc,
  548. * and compatible translation modes on the
  549. * planes staged on this crtc.
  550. * otherwise validation would have failed.
  551. * For this CRTC,
  552. */
  553. /*
  554. * 1. Check if old state on the CRTC has planes
  555. * staged with valid fbs
  556. */
  557. for_each_old_plane_in_state(state, plane, plane_state, i) {
  558. if (!plane_state->crtc)
  559. continue;
  560. if (plane_state->fb) {
  561. old_valid_fb = true;
  562. break;
  563. }
  564. }
  565. /*
  566. * 2.Get the operations needed to be performed before
  567. * secure transition can be initiated.
  568. */
  569. ops = sde_crtc_get_secure_transition_ops(crtc,
  570. old_crtc_state, old_valid_fb);
  571. if (ops < 0) {
  572. SDE_ERROR("invalid secure operations %x\n", ops);
  573. return ops;
  574. }
  575. if (!ops) {
  576. smmu_state->transition_error = false;
  577. goto no_ops;
  578. }
  579. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  580. crtc->base.id, ops, crtc->state);
  581. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  582. /* 3. Perform operations needed for secure transition */
  583. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  584. SDE_DEBUG("wait_for_transfer_done\n");
  585. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  586. }
  587. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  588. SDE_DEBUG("cleanup planes\n");
  589. drm_atomic_helper_cleanup_planes(dev, state);
  590. for_each_oldnew_plane_in_state(state, plane,
  591. old_plane_state, new_plane_state, i)
  592. sde_plane_destroy_fb(old_plane_state);
  593. }
  594. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  595. SDE_DEBUG("secure ctrl\n");
  596. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  597. }
  598. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  599. SDE_DEBUG("prepare planes %d",
  600. crtc->state->plane_mask);
  601. drm_atomic_crtc_for_each_plane(plane,
  602. crtc) {
  603. const struct drm_plane_helper_funcs *funcs;
  604. plane_state = plane->state;
  605. funcs = plane->helper_private;
  606. SDE_DEBUG("psde:%d FB[%u]\n",
  607. plane->base.id,
  608. plane->fb->base.id);
  609. if (!funcs)
  610. continue;
  611. if (funcs->prepare_fb(plane, plane_state)) {
  612. ret = funcs->prepare_fb(plane,
  613. plane_state);
  614. if (ret)
  615. return ret;
  616. }
  617. }
  618. }
  619. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  620. SDE_DEBUG("secure operations completed\n");
  621. }
  622. no_ops:
  623. return 0;
  624. }
  625. static int _sde_kms_release_shared_buffer(unsigned int mem_addr,
  626. unsigned int splash_buffer_size,
  627. unsigned int ramdump_base,
  628. unsigned int ramdump_buffer_size)
  629. {
  630. unsigned long pfn_start, pfn_end, pfn_idx;
  631. int ret = 0;
  632. if (!mem_addr || !splash_buffer_size) {
  633. SDE_ERROR("invalid params\n");
  634. return -EINVAL;
  635. }
  636. /* leave ramdump memory only if base address matches */
  637. if (ramdump_base == mem_addr &&
  638. ramdump_buffer_size <= splash_buffer_size) {
  639. mem_addr += ramdump_buffer_size;
  640. splash_buffer_size -= ramdump_buffer_size;
  641. }
  642. pfn_start = mem_addr >> PAGE_SHIFT;
  643. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  644. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  645. free_reserved_page(pfn_to_page(pfn_idx));
  646. return ret;
  647. }
  648. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  649. struct sde_splash_mem *splash)
  650. {
  651. struct msm_mmu *mmu = NULL;
  652. int ret = 0;
  653. if (!sde_kms->aspace[0]) {
  654. SDE_ERROR("aspace not found for sde kms node\n");
  655. return -EINVAL;
  656. }
  657. mmu = sde_kms->aspace[0]->mmu;
  658. if (!mmu) {
  659. SDE_ERROR("mmu not found for aspace\n");
  660. return -EINVAL;
  661. }
  662. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  663. SDE_ERROR("invalid input params for map\n");
  664. return -EINVAL;
  665. }
  666. if (!splash->ref_cnt) {
  667. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  668. splash->splash_buf_base,
  669. splash->splash_buf_size,
  670. IOMMU_READ | IOMMU_NOEXEC);
  671. if (ret)
  672. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  673. }
  674. splash->ref_cnt++;
  675. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  676. splash->splash_buf_base,
  677. splash->splash_buf_size,
  678. splash->ref_cnt);
  679. return ret;
  680. }
  681. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  682. {
  683. int i = 0;
  684. int ret = 0;
  685. struct sde_splash_mem *region;
  686. if (!sde_kms)
  687. return -EINVAL;
  688. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  689. region = sde_kms->splash_data.splash_display[i].splash;
  690. ret = _sde_kms_splash_mem_get(sde_kms, region);
  691. if (ret)
  692. return ret;
  693. /* Demura is optional and need not exist */
  694. region = sde_kms->splash_data.splash_display[i].demura;
  695. if (region) {
  696. ret = _sde_kms_splash_mem_get(sde_kms, region);
  697. if (ret)
  698. return ret;
  699. }
  700. }
  701. return ret;
  702. }
  703. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  704. struct sde_splash_mem *splash)
  705. {
  706. struct msm_mmu *mmu = NULL;
  707. int rc = 0;
  708. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  709. SDE_ERROR("invalid params\n");
  710. return -EINVAL;
  711. }
  712. mmu = sde_kms->aspace[0]->mmu;
  713. if (!splash || !splash->ref_cnt ||
  714. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  715. return -EINVAL;
  716. splash->ref_cnt--;
  717. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  718. splash->splash_buf_base, splash->ref_cnt);
  719. if (!splash->ref_cnt) {
  720. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  721. splash->splash_buf_size);
  722. rc = _sde_kms_release_shared_buffer(splash->splash_buf_base,
  723. splash->splash_buf_size, splash->ramdump_base,
  724. splash->ramdump_size);
  725. splash->splash_buf_base = 0;
  726. splash->splash_buf_size = 0;
  727. }
  728. return rc;
  729. }
  730. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  731. {
  732. int i = 0;
  733. int ret = 0, failure = 0;
  734. struct sde_splash_mem *region;
  735. if (!sde_kms || !sde_kms->splash_data.num_splash_regions)
  736. return -EINVAL;
  737. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  738. region = sde_kms->splash_data.splash_display[i].splash;
  739. ret = _sde_kms_splash_mem_put(sde_kms, region);
  740. if (ret) {
  741. failure = 1;
  742. pr_err("Error unmapping splash mem for display %d\n",
  743. i);
  744. }
  745. /* Demura is optional and need not exist */
  746. region = sde_kms->splash_data.splash_display[i].demura;
  747. if (region) {
  748. ret = _sde_kms_splash_mem_put(sde_kms, region);
  749. if (ret) {
  750. failure = 1;
  751. pr_err("Error unmapping demura mem for display %d\n",
  752. i);
  753. }
  754. }
  755. }
  756. if (failure)
  757. ret = -EINVAL;
  758. return ret;
  759. }
  760. static int _sde_kms_get_blank(struct drm_crtc_state *crtc_state,
  761. struct drm_connector_state *conn_state)
  762. {
  763. int lp_mode, blank;
  764. if (crtc_state->active)
  765. lp_mode = sde_connector_get_property(conn_state,
  766. CONNECTOR_PROP_LP);
  767. else
  768. lp_mode = SDE_MODE_DPMS_OFF;
  769. switch (lp_mode) {
  770. case SDE_MODE_DPMS_ON:
  771. blank = DRM_PANEL_EVENT_UNBLANK;
  772. break;
  773. case SDE_MODE_DPMS_LP1:
  774. case SDE_MODE_DPMS_LP2:
  775. blank = DRM_PANEL_EVENT_BLANK_LP;
  776. break;
  777. case SDE_MODE_DPMS_OFF:
  778. default:
  779. blank = DRM_PANEL_EVENT_BLANK;
  780. break;
  781. }
  782. return blank;
  783. }
  784. static void _sde_kms_drm_check_dpms(struct drm_atomic_state *old_state,
  785. bool is_pre_commit)
  786. {
  787. struct panel_event_notification notification;
  788. struct drm_connector *connector;
  789. struct drm_connector_state *old_conn_state;
  790. struct drm_crtc_state *old_crtc_state;
  791. struct drm_crtc *crtc;
  792. struct sde_connector *c_conn;
  793. int i, old_mode, new_mode, old_fps, new_fps;
  794. enum panel_event_notifier_tag panel_type;
  795. for_each_old_connector_in_state(old_state, connector,
  796. old_conn_state, i) {
  797. crtc = connector->state->crtc ? connector->state->crtc :
  798. old_conn_state->crtc;
  799. if (!crtc)
  800. continue;
  801. new_fps = drm_mode_vrefresh(&crtc->state->mode);
  802. new_mode = _sde_kms_get_blank(crtc->state, connector->state);
  803. if (old_conn_state->crtc) {
  804. old_crtc_state = drm_atomic_get_existing_crtc_state(
  805. old_state, old_conn_state->crtc);
  806. old_fps = drm_mode_vrefresh(&old_crtc_state->mode);
  807. old_mode = _sde_kms_get_blank(old_crtc_state,
  808. old_conn_state);
  809. } else {
  810. old_fps = 0;
  811. old_mode = DRM_PANEL_EVENT_BLANK;
  812. }
  813. if ((old_mode != new_mode) || (old_fps != new_fps)) {
  814. c_conn = to_sde_connector(connector);
  815. SDE_EVT32(old_mode, new_mode, old_fps, new_fps,
  816. c_conn->panel, crtc->state->active,
  817. old_conn_state->crtc);
  818. pr_debug("change detected for connector:%s (power mode %d->%d, fps %d->%d)\n",
  819. c_conn->name, old_mode, new_mode, old_fps, new_fps);
  820. /* If suspend resume and fps change are happening
  821. * at the same time, give preference to power mode
  822. * changes rather than fps change.
  823. */
  824. if ((old_mode == new_mode) && (old_fps != new_fps))
  825. new_mode = DRM_PANEL_EVENT_FPS_CHANGE;
  826. if (!c_conn->panel)
  827. continue;
  828. panel_type = sde_encoder_is_primary_display(
  829. connector->encoder) ?
  830. PANEL_EVENT_NOTIFICATION_PRIMARY :
  831. PANEL_EVENT_NOTIFICATION_SECONDARY;
  832. notification.notif_type = new_mode;
  833. notification.panel = c_conn->panel;
  834. notification.notif_data.old_fps = old_fps;
  835. notification.notif_data.new_fps = new_fps;
  836. notification.notif_data.early_trigger = is_pre_commit;
  837. panel_event_notification_trigger(panel_type,
  838. &notification);
  839. }
  840. }
  841. }
  842. static struct drm_crtc *sde_kms_vm_get_vm_crtc(
  843. struct drm_atomic_state *state)
  844. {
  845. int i;
  846. enum sde_crtc_vm_req vm_req = VM_REQ_NONE;
  847. struct drm_crtc *crtc, *vm_crtc = NULL;
  848. struct drm_crtc_state *new_cstate, *old_cstate;
  849. struct sde_crtc_state *vm_cstate;
  850. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  851. if (!new_cstate->active && !old_cstate->active)
  852. continue;
  853. vm_cstate = to_sde_crtc_state(new_cstate);
  854. vm_req = sde_crtc_get_property(vm_cstate,
  855. CRTC_PROP_VM_REQ_STATE);
  856. if (vm_req != VM_REQ_NONE) {
  857. SDE_DEBUG("valid vm request:%d found on crtc-%d\n",
  858. vm_req, crtc->base.id);
  859. vm_crtc = crtc;
  860. break;
  861. }
  862. }
  863. return vm_crtc;
  864. }
  865. int sde_kms_vm_primary_prepare_commit(struct sde_kms *sde_kms,
  866. struct drm_atomic_state *state)
  867. {
  868. struct drm_device *ddev;
  869. struct drm_crtc *crtc;
  870. struct drm_crtc_state *new_cstate;
  871. struct drm_encoder *encoder;
  872. struct drm_connector *connector;
  873. struct sde_vm_ops *vm_ops;
  874. struct sde_crtc_state *cstate;
  875. struct drm_connector_list_iter iter;
  876. enum sde_crtc_vm_req vm_req;
  877. int rc = 0;
  878. ddev = sde_kms->dev;
  879. vm_ops = sde_vm_get_ops(sde_kms);
  880. if (!vm_ops)
  881. return -EINVAL;
  882. crtc = sde_kms_vm_get_vm_crtc(state);
  883. if (!crtc)
  884. return 0;
  885. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  886. cstate = to_sde_crtc_state(new_cstate);
  887. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  888. if (vm_req != VM_REQ_ACQUIRE)
  889. return 0;
  890. /* enable MDSS irq line */
  891. sde_irq_update(&sde_kms->base, true);
  892. /* clear the stale IRQ status bits */
  893. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  894. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  895. /* enable the display path IRQ's */
  896. drm_for_each_encoder_mask(encoder, crtc->dev,
  897. crtc->state->encoder_mask) {
  898. if (sde_encoder_in_clone_mode(encoder))
  899. continue;
  900. sde_encoder_irq_control(encoder, true);
  901. }
  902. /* Schedule ESD work */
  903. drm_connector_list_iter_begin(ddev, &iter);
  904. drm_for_each_connector_iter(connector, &iter)
  905. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  906. sde_connector_schedule_status_work(connector, true);
  907. drm_connector_list_iter_end(&iter);
  908. /* enable vblank events */
  909. drm_crtc_vblank_on(crtc);
  910. sde_dbg_set_hw_ownership_status(true);
  911. /* handle non-SDE pre_acquire */
  912. if (vm_ops->vm_client_post_acquire)
  913. rc = vm_ops->vm_client_post_acquire(sde_kms);
  914. return rc;
  915. }
  916. int sde_kms_vm_trusted_prepare_commit(struct sde_kms *sde_kms,
  917. struct drm_atomic_state *state)
  918. {
  919. struct drm_device *ddev;
  920. struct drm_plane *plane;
  921. struct drm_crtc *crtc;
  922. struct drm_crtc_state *new_cstate;
  923. struct sde_crtc_state *cstate;
  924. enum sde_crtc_vm_req vm_req;
  925. ddev = sde_kms->dev;
  926. crtc = sde_kms_vm_get_vm_crtc(state);
  927. if (!crtc)
  928. return 0;
  929. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  930. cstate = to_sde_crtc_state(new_cstate);
  931. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  932. if (vm_req != VM_REQ_ACQUIRE)
  933. return 0;
  934. /* Clear the stale IRQ status bits */
  935. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  936. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  937. /* Program the SID's for the trusted VM */
  938. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  939. sde_plane_set_sid(plane, 1);
  940. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 1);
  941. sde_dbg_set_hw_ownership_status(true);
  942. return 0;
  943. }
  944. static void sde_kms_prepare_commit(struct msm_kms *kms,
  945. struct drm_atomic_state *state)
  946. {
  947. struct sde_kms *sde_kms;
  948. struct msm_drm_private *priv;
  949. struct drm_device *dev;
  950. struct drm_encoder *encoder;
  951. struct drm_crtc *crtc;
  952. struct drm_crtc_state *cstate;
  953. struct sde_vm_ops *vm_ops;
  954. int i, rc;
  955. if (!kms)
  956. return;
  957. sde_kms = to_sde_kms(kms);
  958. dev = sde_kms->dev;
  959. if (!dev || !dev->dev_private)
  960. return;
  961. priv = dev->dev_private;
  962. SDE_ATRACE_BEGIN("prepare_commit");
  963. rc = pm_runtime_resume_and_get(sde_kms->dev->dev);
  964. if (rc < 0) {
  965. SDE_ERROR("failed to enable power resources %d\n", rc);
  966. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  967. goto end;
  968. }
  969. if (sde_kms->first_kickoff) {
  970. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  971. sde_kms->first_kickoff = false;
  972. }
  973. for_each_new_crtc_in_state(state, crtc, cstate, i) {
  974. drm_for_each_encoder_mask(encoder, dev, cstate->encoder_mask) {
  975. if (sde_encoder_prepare_commit(encoder) == -ETIMEDOUT) {
  976. SDE_ERROR("crtc:%d, initiating hw reset\n",
  977. DRMID(crtc));
  978. sde_encoder_needs_hw_reset(encoder);
  979. sde_crtc_set_needs_hw_reset(crtc);
  980. }
  981. }
  982. }
  983. /*
  984. * NOTE: for secure use cases we want to apply the new HW
  985. * configuration only after completing preparation for secure
  986. * transitions prepare below if any transtions is required.
  987. */
  988. sde_kms_prepare_secure_transition(kms, state);
  989. vm_ops = sde_vm_get_ops(sde_kms);
  990. if (!vm_ops)
  991. goto end_vm;
  992. if (vm_ops->vm_prepare_commit)
  993. vm_ops->vm_prepare_commit(sde_kms, state);
  994. end_vm:
  995. _sde_kms_drm_check_dpms(state, true);
  996. end:
  997. SDE_ATRACE_END("prepare_commit");
  998. }
  999. static void sde_kms_commit(struct msm_kms *kms,
  1000. struct drm_atomic_state *old_state)
  1001. {
  1002. struct sde_kms *sde_kms;
  1003. struct drm_crtc *crtc;
  1004. struct drm_crtc_state *old_crtc_state;
  1005. int i;
  1006. if (!kms || !old_state)
  1007. return;
  1008. sde_kms = to_sde_kms(kms);
  1009. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  1010. SDE_ERROR("power resource is not enabled\n");
  1011. return;
  1012. }
  1013. SDE_ATRACE_BEGIN("sde_kms_commit");
  1014. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1015. if (crtc->state->active) {
  1016. SDE_EVT32(DRMID(crtc), old_state);
  1017. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  1018. }
  1019. }
  1020. SDE_ATRACE_END("sde_kms_commit");
  1021. }
  1022. static void _sde_kms_free_splash_display_data(struct sde_kms *sde_kms,
  1023. struct sde_splash_display *splash_display)
  1024. {
  1025. if (!sde_kms || !splash_display ||
  1026. !sde_kms->splash_data.num_splash_displays)
  1027. return;
  1028. if (sde_kms->splash_data.num_splash_regions) {
  1029. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  1030. if (splash_display->demura)
  1031. _sde_kms_splash_mem_put(sde_kms,
  1032. splash_display->demura);
  1033. }
  1034. sde_kms->splash_data.num_splash_displays--;
  1035. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  1036. sde_kms->splash_data.num_splash_displays);
  1037. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  1038. }
  1039. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  1040. struct drm_crtc *crtc)
  1041. {
  1042. struct msm_drm_private *priv;
  1043. struct sde_splash_display *splash_display;
  1044. int i;
  1045. if (!sde_kms || !crtc)
  1046. return;
  1047. priv = sde_kms->dev->dev_private;
  1048. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  1049. return;
  1050. SDE_EVT32(DRMID(crtc), crtc->state->active,
  1051. sde_kms->splash_data.num_splash_displays);
  1052. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  1053. splash_display = &sde_kms->splash_data.splash_display[i];
  1054. if (splash_display->encoder &&
  1055. crtc == splash_display->encoder->crtc)
  1056. break;
  1057. }
  1058. if (i >= MAX_DSI_DISPLAYS)
  1059. return;
  1060. if (splash_display->cont_splash_enabled) {
  1061. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  1062. splash_display, false);
  1063. _sde_kms_free_splash_display_data(sde_kms, splash_display);
  1064. }
  1065. /* remove the votes if all displays are done with splash */
  1066. if (!sde_kms->splash_data.num_splash_displays) {
  1067. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  1068. sde_power_data_bus_set_quota(&priv->phandle, i,
  1069. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  1070. priv->phandle.ib_quota[i] ? priv->phandle.ib_quota[i] :
  1071. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  1072. pm_runtime_put_sync(sde_kms->dev->dev);
  1073. }
  1074. }
  1075. static void sde_kms_cancel_delayed_work(struct drm_crtc *crtc)
  1076. {
  1077. struct drm_connector *connector;
  1078. struct drm_connector_list_iter iter;
  1079. struct drm_encoder *encoder;
  1080. /* Cancel CRTC work */
  1081. sde_crtc_cancel_delayed_work(crtc);
  1082. /* Cancel ESD work */
  1083. drm_connector_list_iter_begin(crtc->dev, &iter);
  1084. drm_for_each_connector_iter(connector, &iter)
  1085. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  1086. sde_connector_schedule_status_work(connector, false);
  1087. drm_connector_list_iter_end(&iter);
  1088. /* Cancel Idle-PC work */
  1089. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) {
  1090. if (sde_encoder_in_clone_mode(encoder))
  1091. continue;
  1092. sde_encoder_cancel_delayed_work(encoder);
  1093. }
  1094. }
  1095. int sde_kms_vm_pre_release(struct sde_kms *sde_kms,
  1096. struct drm_atomic_state *state, bool is_primary)
  1097. {
  1098. struct drm_crtc *crtc;
  1099. struct drm_encoder *encoder;
  1100. int rc = 0;
  1101. crtc = sde_kms_vm_get_vm_crtc(state);
  1102. if (!crtc)
  1103. return 0;
  1104. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1105. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1106. sde_kms_cancel_delayed_work(crtc);
  1107. /* disable SDE irq's */
  1108. drm_for_each_encoder_mask(encoder, crtc->dev,
  1109. crtc->state->encoder_mask) {
  1110. if (sde_encoder_in_clone_mode(encoder))
  1111. continue;
  1112. sde_encoder_irq_control(encoder, false);
  1113. }
  1114. if (is_primary) {
  1115. /* disable IRQ line */
  1116. sde_irq_update(&sde_kms->base, false);
  1117. /* disable vblank events */
  1118. drm_crtc_vblank_off(crtc);
  1119. /* reset sw state */
  1120. sde_crtc_reset_sw_state(crtc);
  1121. }
  1122. sde_dbg_set_hw_ownership_status(false);
  1123. return rc;
  1124. }
  1125. int sde_kms_vm_trusted_post_commit(struct sde_kms *sde_kms,
  1126. struct drm_atomic_state *state)
  1127. {
  1128. struct sde_vm_ops *vm_ops;
  1129. struct drm_device *ddev;
  1130. struct drm_crtc *crtc;
  1131. struct drm_plane *plane;
  1132. struct sde_crtc_state *cstate;
  1133. struct drm_crtc_state *new_cstate;
  1134. enum sde_crtc_vm_req vm_req;
  1135. int rc = 0;
  1136. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1137. return -EINVAL;
  1138. vm_ops = sde_vm_get_ops(sde_kms);
  1139. ddev = sde_kms->dev;
  1140. crtc = sde_kms_vm_get_vm_crtc(state);
  1141. if (!crtc)
  1142. return 0;
  1143. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  1144. cstate = to_sde_crtc_state(new_cstate);
  1145. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1146. if (vm_req != VM_REQ_RELEASE)
  1147. return 0;
  1148. sde_kms_vm_pre_release(sde_kms, state, false);
  1149. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  1150. sde_plane_set_sid(plane, 0);
  1151. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 0);
  1152. sde_vm_lock(sde_kms);
  1153. if (vm_ops->vm_release)
  1154. rc = vm_ops->vm_release(sde_kms);
  1155. sde_vm_unlock(sde_kms);
  1156. return rc;
  1157. }
  1158. int sde_kms_vm_primary_post_commit(struct sde_kms *sde_kms,
  1159. struct drm_atomic_state *state)
  1160. {
  1161. struct sde_vm_ops *vm_ops;
  1162. struct sde_crtc_state *cstate;
  1163. struct drm_crtc *crtc;
  1164. struct drm_crtc_state *new_cstate;
  1165. enum sde_crtc_vm_req vm_req;
  1166. int rc = 0;
  1167. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1168. return -EINVAL;
  1169. vm_ops = sde_vm_get_ops(sde_kms);
  1170. crtc = sde_kms_vm_get_vm_crtc(state);
  1171. if (!crtc)
  1172. return 0;
  1173. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  1174. cstate = to_sde_crtc_state(new_cstate);
  1175. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1176. if (vm_req != VM_REQ_RELEASE)
  1177. return 0;
  1178. /* handle SDE pre-release */
  1179. rc = sde_kms_vm_pre_release(sde_kms, state, true);
  1180. if (rc) {
  1181. SDE_ERROR("sde vm pre_release failed, rc=%d\n", rc);
  1182. goto exit;
  1183. }
  1184. /* properly handoff color processing features */
  1185. sde_cp_crtc_vm_primary_handoff(crtc);
  1186. /* handle non-SDE clients pre-release */
  1187. if (vm_ops->vm_client_pre_release) {
  1188. rc = vm_ops->vm_client_pre_release(sde_kms);
  1189. if (rc) {
  1190. SDE_ERROR("sde vm client pre_release failed, rc=%d\n",
  1191. rc);
  1192. goto exit;
  1193. }
  1194. }
  1195. sde_vm_lock(sde_kms);
  1196. /* release HW */
  1197. if (vm_ops->vm_release) {
  1198. rc = vm_ops->vm_release(sde_kms);
  1199. if (rc)
  1200. SDE_ERROR("sde vm assign failed, rc=%d\n", rc);
  1201. }
  1202. sde_vm_unlock(sde_kms);
  1203. _sde_crtc_vm_release_notify(crtc);
  1204. exit:
  1205. return rc;
  1206. }
  1207. static void sde_kms_complete_commit(struct msm_kms *kms,
  1208. struct drm_atomic_state *old_state)
  1209. {
  1210. struct sde_kms *sde_kms;
  1211. struct msm_drm_private *priv;
  1212. struct drm_crtc *crtc;
  1213. struct drm_crtc_state *old_crtc_state;
  1214. struct drm_connector *connector;
  1215. struct drm_connector_state *old_conn_state;
  1216. struct msm_display_conn_params params;
  1217. struct sde_vm_ops *vm_ops;
  1218. int i, rc = 0;
  1219. if (!kms || !old_state)
  1220. return;
  1221. sde_kms = to_sde_kms(kms);
  1222. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  1223. return;
  1224. priv = sde_kms->dev->dev_private;
  1225. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  1226. SDE_ERROR("power resource is not enabled\n");
  1227. return;
  1228. }
  1229. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  1230. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1231. sde_crtc_complete_commit(crtc, old_crtc_state);
  1232. /* complete secure transitions if any */
  1233. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  1234. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  1235. }
  1236. for_each_old_connector_in_state(old_state, connector,
  1237. old_conn_state, i) {
  1238. struct sde_connector *c_conn;
  1239. c_conn = to_sde_connector(connector);
  1240. if (!c_conn->ops.post_kickoff)
  1241. continue;
  1242. memset(&params, 0, sizeof(params));
  1243. sde_connector_complete_qsync_commit(connector, &params);
  1244. rc = c_conn->ops.post_kickoff(connector, &params);
  1245. if (rc) {
  1246. pr_err("Connector Post kickoff failed rc=%d\n",
  1247. rc);
  1248. }
  1249. }
  1250. vm_ops = sde_vm_get_ops(sde_kms);
  1251. if (vm_ops && vm_ops->vm_post_commit) {
  1252. rc = vm_ops->vm_post_commit(sde_kms, old_state);
  1253. if (rc)
  1254. SDE_ERROR("vm post commit failed, rc = %d\n",
  1255. rc);
  1256. }
  1257. _sde_kms_drm_check_dpms(old_state, false);
  1258. pm_runtime_put_sync(sde_kms->dev->dev);
  1259. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  1260. _sde_kms_release_splash_resource(sde_kms, crtc);
  1261. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  1262. SDE_ATRACE_END("sde_kms_complete_commit");
  1263. }
  1264. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  1265. struct drm_crtc *crtc)
  1266. {
  1267. struct drm_encoder *encoder;
  1268. struct drm_device *dev;
  1269. int ret;
  1270. bool cwb_disabling;
  1271. if (!kms || !crtc || !crtc->state) {
  1272. SDE_ERROR("invalid params\n");
  1273. return;
  1274. }
  1275. dev = crtc->dev;
  1276. if (!crtc->state->enable) {
  1277. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  1278. return;
  1279. }
  1280. if (!crtc->state->active) {
  1281. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  1282. return;
  1283. }
  1284. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  1285. SDE_ERROR("power resource is not enabled\n");
  1286. return;
  1287. }
  1288. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  1289. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1290. cwb_disabling = false;
  1291. if (encoder->crtc != crtc) {
  1292. cwb_disabling = sde_encoder_is_cwb_disabling(encoder,
  1293. crtc);
  1294. if (!cwb_disabling)
  1295. continue;
  1296. }
  1297. /*
  1298. * Wait for post-flush if necessary to delay before
  1299. * plane_cleanup. For example, wait for vsync in case of video
  1300. * mode panels. This may be a no-op for command mode panels.
  1301. */
  1302. SDE_EVT32_VERBOSE(DRMID(crtc));
  1303. ret = sde_encoder_wait_for_event(encoder, cwb_disabling ?
  1304. MSM_ENC_TX_COMPLETE : MSM_ENC_COMMIT_DONE);
  1305. if (ret && ret != -EWOULDBLOCK) {
  1306. SDE_ERROR("wait for commit done returned %d\n", ret);
  1307. sde_crtc_request_frame_reset(crtc, encoder);
  1308. break;
  1309. }
  1310. sde_crtc_complete_flip(crtc, NULL);
  1311. if (cwb_disabling)
  1312. sde_encoder_virt_reset(encoder);
  1313. }
  1314. sde_crtc_static_cache_read_kickoff(crtc);
  1315. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  1316. }
  1317. static void sde_kms_prepare_fence(struct msm_kms *kms,
  1318. struct drm_atomic_state *old_state)
  1319. {
  1320. struct drm_crtc *crtc;
  1321. struct drm_crtc_state *old_crtc_state;
  1322. int i;
  1323. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  1324. SDE_ERROR("invalid argument(s)\n");
  1325. return;
  1326. }
  1327. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  1328. /* old_state actually contains updated crtc pointers */
  1329. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1330. if (crtc->state->active || crtc->state->active_changed)
  1331. sde_crtc_prepare_commit(crtc, old_crtc_state);
  1332. }
  1333. SDE_ATRACE_END("sde_kms_prepare_fence");
  1334. }
  1335. /**
  1336. * _sde_kms_get_displays - query for underlying display handles and cache them
  1337. * @sde_kms: Pointer to sde kms structure
  1338. * Returns: Zero on success
  1339. */
  1340. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  1341. {
  1342. int rc = -ENOMEM;
  1343. if (!sde_kms) {
  1344. SDE_ERROR("invalid sde kms\n");
  1345. return -EINVAL;
  1346. }
  1347. /* dsi */
  1348. sde_kms->dsi_displays = NULL;
  1349. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  1350. if (sde_kms->dsi_display_count) {
  1351. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  1352. sizeof(void *),
  1353. GFP_KERNEL);
  1354. if (!sde_kms->dsi_displays) {
  1355. SDE_ERROR("failed to allocate dsi displays\n");
  1356. goto exit_deinit_dsi;
  1357. }
  1358. sde_kms->dsi_display_count =
  1359. dsi_display_get_active_displays(sde_kms->dsi_displays,
  1360. sde_kms->dsi_display_count);
  1361. }
  1362. /* wb */
  1363. sde_kms->wb_displays = NULL;
  1364. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  1365. if (sde_kms->wb_display_count) {
  1366. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  1367. sizeof(void *),
  1368. GFP_KERNEL);
  1369. if (!sde_kms->wb_displays) {
  1370. SDE_ERROR("failed to allocate wb displays\n");
  1371. goto exit_deinit_wb;
  1372. }
  1373. sde_kms->wb_display_count =
  1374. wb_display_get_displays(sde_kms->wb_displays,
  1375. sde_kms->wb_display_count);
  1376. }
  1377. /* dp */
  1378. sde_kms->dp_displays = NULL;
  1379. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  1380. if (sde_kms->dp_display_count) {
  1381. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  1382. sizeof(void *), GFP_KERNEL);
  1383. if (!sde_kms->dp_displays) {
  1384. SDE_ERROR("failed to allocate dp displays\n");
  1385. goto exit_deinit_dp;
  1386. }
  1387. sde_kms->dp_display_count =
  1388. dp_display_get_displays(sde_kms->dp_displays,
  1389. sde_kms->dp_display_count);
  1390. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  1391. }
  1392. return 0;
  1393. exit_deinit_dp:
  1394. kfree(sde_kms->dp_displays);
  1395. sde_kms->dp_stream_count = 0;
  1396. sde_kms->dp_display_count = 0;
  1397. sde_kms->dp_displays = NULL;
  1398. exit_deinit_wb:
  1399. kfree(sde_kms->wb_displays);
  1400. sde_kms->wb_display_count = 0;
  1401. sde_kms->wb_displays = NULL;
  1402. exit_deinit_dsi:
  1403. kfree(sde_kms->dsi_displays);
  1404. sde_kms->dsi_display_count = 0;
  1405. sde_kms->dsi_displays = NULL;
  1406. return rc;
  1407. }
  1408. /**
  1409. * _sde_kms_release_displays - release cache of underlying display handles
  1410. * @sde_kms: Pointer to sde kms structure
  1411. */
  1412. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  1413. {
  1414. if (!sde_kms) {
  1415. SDE_ERROR("invalid sde kms\n");
  1416. return;
  1417. }
  1418. kfree(sde_kms->wb_displays);
  1419. sde_kms->wb_displays = NULL;
  1420. sde_kms->wb_display_count = 0;
  1421. kfree(sde_kms->dsi_displays);
  1422. sde_kms->dsi_displays = NULL;
  1423. sde_kms->dsi_display_count = 0;
  1424. }
  1425. /**
  1426. * _sde_kms_setup_displays - create encoders, bridges and connectors
  1427. * for underlying displays
  1428. * @dev: Pointer to drm device structure
  1429. * @priv: Pointer to private drm device data
  1430. * @sde_kms: Pointer to sde kms structure
  1431. * Returns: Zero on success
  1432. */
  1433. static int _sde_kms_setup_displays(struct drm_device *dev,
  1434. struct msm_drm_private *priv,
  1435. struct sde_kms *sde_kms)
  1436. {
  1437. static const struct sde_connector_ops dsi_ops = {
  1438. .set_info_blob = dsi_conn_set_info_blob,
  1439. .detect = dsi_conn_detect,
  1440. .get_modes = dsi_connector_get_modes,
  1441. .pre_destroy = dsi_connector_put_modes,
  1442. .mode_valid = dsi_conn_mode_valid,
  1443. .get_info = dsi_display_get_info,
  1444. .set_backlight = dsi_display_set_backlight,
  1445. .soft_reset = dsi_display_soft_reset,
  1446. .pre_kickoff = dsi_conn_pre_kickoff,
  1447. .clk_ctrl = dsi_display_clk_ctrl,
  1448. .set_power = dsi_display_set_power,
  1449. .get_mode_info = dsi_conn_get_mode_info,
  1450. .get_dst_format = dsi_display_get_dst_format,
  1451. .post_kickoff = dsi_conn_post_kickoff,
  1452. .check_status = dsi_display_check_status,
  1453. .enable_event = dsi_conn_enable_event,
  1454. .cmd_transfer = dsi_display_cmd_transfer,
  1455. .cont_splash_config = dsi_display_cont_splash_config,
  1456. .cont_splash_res_disable = dsi_display_cont_splash_res_disable,
  1457. .get_panel_vfp = dsi_display_get_panel_vfp,
  1458. .get_default_lms = dsi_display_get_default_lms,
  1459. .cmd_receive = dsi_display_cmd_receive,
  1460. .install_properties = NULL,
  1461. .set_allowed_mode_switch = dsi_conn_set_allowed_mode_switch,
  1462. .set_dyn_bit_clk = dsi_conn_set_dyn_bit_clk,
  1463. .get_qsync_min_fps = dsi_conn_get_qsync_min_fps,
  1464. .get_avr_step_req = dsi_display_get_avr_step_req_fps,
  1465. .prepare_commit = dsi_conn_prepare_commit,
  1466. .set_submode_info = dsi_conn_set_submode_blob_info,
  1467. .get_num_lm_from_mode = dsi_conn_get_lm_from_mode,
  1468. };
  1469. static const struct sde_connector_ops wb_ops = {
  1470. .post_init = sde_wb_connector_post_init,
  1471. .set_info_blob = sde_wb_connector_set_info_blob,
  1472. .detect = sde_wb_connector_detect,
  1473. .get_modes = sde_wb_connector_get_modes,
  1474. .set_property = sde_wb_connector_set_property,
  1475. .get_info = sde_wb_get_info,
  1476. .soft_reset = NULL,
  1477. .get_mode_info = sde_wb_get_mode_info,
  1478. .get_dst_format = NULL,
  1479. .check_status = NULL,
  1480. .cmd_transfer = NULL,
  1481. .cont_splash_config = NULL,
  1482. .cont_splash_res_disable = NULL,
  1483. .get_panel_vfp = NULL,
  1484. .cmd_receive = NULL,
  1485. .install_properties = NULL,
  1486. .set_dyn_bit_clk = NULL,
  1487. .set_allowed_mode_switch = NULL,
  1488. };
  1489. static const struct sde_connector_ops dp_ops = {
  1490. .post_init = dp_connector_post_init,
  1491. .detect = dp_connector_detect,
  1492. .get_modes = dp_connector_get_modes,
  1493. .atomic_check = dp_connector_atomic_check,
  1494. .mode_valid = dp_connector_mode_valid,
  1495. .get_info = dp_connector_get_info,
  1496. .get_mode_info = dp_connector_get_mode_info,
  1497. .post_open = dp_connector_post_open,
  1498. .check_status = NULL,
  1499. .set_colorspace = dp_connector_set_colorspace,
  1500. .config_hdr = dp_connector_config_hdr,
  1501. .cmd_transfer = NULL,
  1502. .cont_splash_config = NULL,
  1503. .cont_splash_res_disable = NULL,
  1504. .get_panel_vfp = NULL,
  1505. .update_pps = dp_connector_update_pps,
  1506. .cmd_receive = NULL,
  1507. .install_properties = dp_connector_install_properties,
  1508. .set_allowed_mode_switch = NULL,
  1509. .set_dyn_bit_clk = NULL,
  1510. };
  1511. struct msm_display_info info;
  1512. struct drm_encoder *encoder;
  1513. void *display, *connector;
  1514. int i, max_encoders;
  1515. int rc = 0;
  1516. u32 dsc_count = 0, mixer_count = 0;
  1517. u32 max_dp_dsc_count, max_dp_mixer_count;
  1518. if (!dev || !priv || !sde_kms) {
  1519. SDE_ERROR("invalid argument(s)\n");
  1520. return -EINVAL;
  1521. }
  1522. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1523. sde_kms->dp_display_count +
  1524. sde_kms->dp_stream_count;
  1525. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1526. max_encoders = ARRAY_SIZE(priv->encoders);
  1527. SDE_ERROR("capping number of displays to %d", max_encoders);
  1528. }
  1529. /* wb */
  1530. for (i = 0; i < sde_kms->wb_display_count &&
  1531. priv->num_encoders < max_encoders; ++i) {
  1532. display = sde_kms->wb_displays[i];
  1533. encoder = NULL;
  1534. memset(&info, 0x0, sizeof(info));
  1535. rc = sde_wb_get_info(NULL, &info, display);
  1536. if (rc) {
  1537. SDE_ERROR("wb get_info %d failed\n", i);
  1538. continue;
  1539. }
  1540. encoder = sde_encoder_init(dev, &info);
  1541. if (IS_ERR_OR_NULL(encoder)) {
  1542. SDE_ERROR("encoder init failed for wb %d\n", i);
  1543. continue;
  1544. }
  1545. rc = sde_wb_drm_init(display, encoder);
  1546. if (rc) {
  1547. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1548. sde_encoder_destroy(encoder);
  1549. continue;
  1550. }
  1551. connector = sde_connector_init(dev,
  1552. encoder,
  1553. 0,
  1554. display,
  1555. &wb_ops,
  1556. DRM_CONNECTOR_POLL_HPD,
  1557. DRM_MODE_CONNECTOR_VIRTUAL);
  1558. if (connector) {
  1559. priv->encoders[priv->num_encoders++] = encoder;
  1560. priv->connectors[priv->num_connectors++] = connector;
  1561. } else {
  1562. SDE_ERROR("wb %d connector init failed\n", i);
  1563. sde_wb_drm_deinit(display);
  1564. sde_encoder_destroy(encoder);
  1565. }
  1566. }
  1567. /* dsi */
  1568. for (i = 0; i < sde_kms->dsi_display_count &&
  1569. priv->num_encoders < max_encoders; ++i) {
  1570. display = sde_kms->dsi_displays[i];
  1571. encoder = NULL;
  1572. memset(&info, 0x0, sizeof(info));
  1573. rc = dsi_display_get_info(NULL, &info, display);
  1574. if (rc) {
  1575. SDE_ERROR("dsi get_info %d failed\n", i);
  1576. continue;
  1577. }
  1578. encoder = sde_encoder_init(dev, &info);
  1579. if (IS_ERR_OR_NULL(encoder)) {
  1580. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1581. continue;
  1582. }
  1583. rc = dsi_display_drm_bridge_init(display, encoder);
  1584. if (rc) {
  1585. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1586. sde_encoder_destroy(encoder);
  1587. continue;
  1588. }
  1589. connector = sde_connector_init(dev,
  1590. encoder,
  1591. dsi_display_get_drm_panel(display),
  1592. display,
  1593. &dsi_ops,
  1594. DRM_CONNECTOR_POLL_HPD,
  1595. DRM_MODE_CONNECTOR_DSI);
  1596. if (connector) {
  1597. priv->encoders[priv->num_encoders++] = encoder;
  1598. priv->connectors[priv->num_connectors++] = connector;
  1599. } else {
  1600. SDE_ERROR("dsi %d connector init failed\n", i);
  1601. dsi_display_drm_bridge_deinit(display);
  1602. sde_encoder_destroy(encoder);
  1603. continue;
  1604. }
  1605. rc = dsi_display_drm_ext_bridge_init(display,
  1606. encoder, connector);
  1607. if (rc) {
  1608. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1609. dsi_display_drm_bridge_deinit(display);
  1610. sde_connector_destroy(connector);
  1611. sde_encoder_destroy(encoder);
  1612. }
  1613. dsc_count += info.dsc_count;
  1614. mixer_count += info.lm_count;
  1615. if (dsi_display_has_dsc_switch_support(display))
  1616. sde_kms->dsc_switch_support = true;
  1617. }
  1618. if (sde_kms->catalog->allowed_dsc_reservation_switch &&
  1619. !sde_kms->dsc_switch_support) {
  1620. SDE_DEBUG("dsc switch not supported\n");
  1621. sde_kms->catalog->allowed_dsc_reservation_switch = 0;
  1622. }
  1623. max_dp_mixer_count = sde_kms->catalog->mixer_count > mixer_count ?
  1624. sde_kms->catalog->mixer_count - mixer_count : 0;
  1625. max_dp_dsc_count = sde_kms->catalog->dsc_count > dsc_count ?
  1626. sde_kms->catalog->dsc_count - dsc_count : 0;
  1627. if (sde_kms->catalog->allowed_dsc_reservation_switch &
  1628. SDE_DP_DSC_RESERVATION_SWITCH)
  1629. max_dp_dsc_count = sde_kms->catalog->dsc_count;
  1630. /* dp */
  1631. for (i = 0; i < sde_kms->dp_display_count &&
  1632. priv->num_encoders < max_encoders; ++i) {
  1633. int idx;
  1634. display = sde_kms->dp_displays[i];
  1635. encoder = NULL;
  1636. memset(&info, 0x0, sizeof(info));
  1637. rc = dp_connector_get_info(NULL, &info, display);
  1638. if (rc) {
  1639. SDE_ERROR("dp get_info %d failed\n", i);
  1640. continue;
  1641. }
  1642. encoder = sde_encoder_init(dev, &info);
  1643. if (IS_ERR_OR_NULL(encoder)) {
  1644. SDE_ERROR("dp encoder init failed %d\n", i);
  1645. continue;
  1646. }
  1647. rc = dp_drm_bridge_init(display, encoder,
  1648. max_dp_mixer_count, max_dp_dsc_count);
  1649. if (rc) {
  1650. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1651. sde_encoder_destroy(encoder);
  1652. continue;
  1653. }
  1654. connector = sde_connector_init(dev,
  1655. encoder,
  1656. NULL,
  1657. display,
  1658. &dp_ops,
  1659. DRM_CONNECTOR_POLL_HPD,
  1660. DRM_MODE_CONNECTOR_DisplayPort);
  1661. if (connector) {
  1662. priv->encoders[priv->num_encoders++] = encoder;
  1663. priv->connectors[priv->num_connectors++] = connector;
  1664. } else {
  1665. SDE_ERROR("dp %d connector init failed\n", i);
  1666. dp_drm_bridge_deinit(display);
  1667. sde_encoder_destroy(encoder);
  1668. }
  1669. /* update display cap to MST_MODE for DP MST encoders */
  1670. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1671. for (idx = 0; idx < sde_kms->dp_stream_count &&
  1672. priv->num_encoders < max_encoders; idx++) {
  1673. info.h_tile_instance[0] = idx;
  1674. encoder = sde_encoder_init(dev, &info);
  1675. if (IS_ERR_OR_NULL(encoder)) {
  1676. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1677. continue;
  1678. }
  1679. rc = dp_mst_drm_bridge_init(display, encoder);
  1680. if (rc) {
  1681. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1682. i, rc);
  1683. sde_encoder_destroy(encoder);
  1684. continue;
  1685. }
  1686. priv->encoders[priv->num_encoders++] = encoder;
  1687. }
  1688. }
  1689. return 0;
  1690. }
  1691. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1692. {
  1693. struct msm_drm_private *priv;
  1694. int i;
  1695. if (!sde_kms) {
  1696. SDE_ERROR("invalid sde_kms\n");
  1697. return;
  1698. } else if (!sde_kms->dev) {
  1699. SDE_ERROR("invalid dev\n");
  1700. return;
  1701. } else if (!sde_kms->dev->dev_private) {
  1702. SDE_ERROR("invalid dev_private\n");
  1703. return;
  1704. }
  1705. priv = sde_kms->dev->dev_private;
  1706. for (i = 0; i < priv->num_crtcs; i++)
  1707. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1708. priv->num_crtcs = 0;
  1709. for (i = 0; i < priv->num_planes; i++)
  1710. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1711. priv->num_planes = 0;
  1712. for (i = 0; i < priv->num_connectors; i++)
  1713. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1714. priv->num_connectors = 0;
  1715. for (i = 0; i < priv->num_encoders; i++)
  1716. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1717. priv->num_encoders = 0;
  1718. _sde_kms_release_displays(sde_kms);
  1719. }
  1720. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1721. {
  1722. struct drm_device *dev;
  1723. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1724. struct drm_crtc *crtc;
  1725. struct msm_drm_private *priv;
  1726. struct sde_mdss_cfg *catalog;
  1727. int primary_planes_idx = 0, i, ret;
  1728. int max_crtc_count;
  1729. u32 sspp_id[MAX_PLANES];
  1730. u32 master_plane_id[MAX_PLANES];
  1731. u32 num_virt_planes = 0;
  1732. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1733. SDE_ERROR("invalid sde_kms\n");
  1734. return -EINVAL;
  1735. }
  1736. dev = sde_kms->dev;
  1737. priv = dev->dev_private;
  1738. catalog = sde_kms->catalog;
  1739. ret = sde_core_irq_domain_add(sde_kms);
  1740. if (ret)
  1741. goto fail_irq;
  1742. /*
  1743. * Query for underlying display drivers, and create connectors,
  1744. * bridges and encoders for them.
  1745. */
  1746. if (!_sde_kms_get_displays(sde_kms))
  1747. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1748. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1749. /* Create the planes */
  1750. for (i = 0; i < catalog->sspp_count; i++) {
  1751. bool primary = true;
  1752. if (primary_planes_idx >= max_crtc_count)
  1753. primary = false;
  1754. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1755. (1UL << max_crtc_count) - 1, 0);
  1756. if (IS_ERR(plane)) {
  1757. SDE_ERROR("sde_plane_init failed\n");
  1758. ret = PTR_ERR(plane);
  1759. goto fail;
  1760. }
  1761. priv->planes[priv->num_planes++] = plane;
  1762. if (primary)
  1763. primary_planes[primary_planes_idx++] = plane;
  1764. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1765. sde_is_custom_client()) {
  1766. int priority =
  1767. catalog->sspp[i].sblk->smart_dma_priority;
  1768. sspp_id[priority - 1] = catalog->sspp[i].id;
  1769. master_plane_id[priority - 1] = plane->base.id;
  1770. num_virt_planes++;
  1771. }
  1772. }
  1773. /* Initialize smart DMA virtual planes */
  1774. for (i = 0; i < num_virt_planes; i++) {
  1775. plane = sde_plane_init(dev, sspp_id[i], false,
  1776. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1777. if (IS_ERR(plane)) {
  1778. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1779. ret = PTR_ERR(plane);
  1780. goto fail;
  1781. }
  1782. priv->planes[priv->num_planes++] = plane;
  1783. }
  1784. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1785. /* Create one CRTC per encoder */
  1786. for (i = 0; i < max_crtc_count; i++) {
  1787. crtc = sde_crtc_init(dev, primary_planes[i]);
  1788. if (IS_ERR(crtc)) {
  1789. ret = PTR_ERR(crtc);
  1790. goto fail;
  1791. }
  1792. priv->crtcs[priv->num_crtcs++] = crtc;
  1793. }
  1794. if (sde_is_custom_client()) {
  1795. /* All CRTCs are compatible with all planes */
  1796. for (i = 0; i < priv->num_planes; i++)
  1797. priv->planes[i]->possible_crtcs =
  1798. (1 << priv->num_crtcs) - 1;
  1799. }
  1800. /* All CRTCs are compatible with all encoders */
  1801. for (i = 0; i < priv->num_encoders; i++)
  1802. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1803. return 0;
  1804. fail:
  1805. _sde_kms_drm_obj_destroy(sde_kms);
  1806. fail_irq:
  1807. sde_core_irq_domain_fini(sde_kms);
  1808. return ret;
  1809. }
  1810. /**
  1811. * sde_kms_timeline_status - provides current timeline status
  1812. * This API should be called without mode config lock.
  1813. * @dev: Pointer to drm device
  1814. */
  1815. void sde_kms_timeline_status(struct drm_device *dev)
  1816. {
  1817. struct drm_crtc *crtc;
  1818. struct drm_connector *conn;
  1819. struct drm_connector_list_iter conn_iter;
  1820. if (!dev) {
  1821. SDE_ERROR("invalid drm device node\n");
  1822. return;
  1823. }
  1824. drm_for_each_crtc(crtc, dev)
  1825. sde_crtc_timeline_status(crtc);
  1826. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1827. /*
  1828. *Probably locked from last close dumping status anyway
  1829. */
  1830. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1831. drm_connector_list_iter_begin(dev, &conn_iter);
  1832. drm_for_each_connector_iter(conn, &conn_iter)
  1833. sde_conn_timeline_status(conn);
  1834. drm_connector_list_iter_end(&conn_iter);
  1835. return;
  1836. }
  1837. mutex_lock(&dev->mode_config.mutex);
  1838. drm_connector_list_iter_begin(dev, &conn_iter);
  1839. drm_for_each_connector_iter(conn, &conn_iter)
  1840. sde_conn_timeline_status(conn);
  1841. drm_connector_list_iter_end(&conn_iter);
  1842. mutex_unlock(&dev->mode_config.mutex);
  1843. }
  1844. static int sde_kms_postinit(struct msm_kms *kms)
  1845. {
  1846. struct sde_kms *sde_kms = to_sde_kms(kms);
  1847. struct drm_device *dev;
  1848. struct drm_crtc *crtc;
  1849. int rc;
  1850. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1851. SDE_ERROR("invalid sde_kms\n");
  1852. return -EINVAL;
  1853. }
  1854. dev = sde_kms->dev;
  1855. rc = _sde_debugfs_init(sde_kms);
  1856. if (rc)
  1857. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1858. drm_for_each_crtc(crtc, dev)
  1859. sde_crtc_post_init(dev, crtc);
  1860. return rc;
  1861. }
  1862. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1863. struct drm_encoder *encoder)
  1864. {
  1865. return rate;
  1866. }
  1867. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1868. struct platform_device *pdev)
  1869. {
  1870. struct drm_device *dev;
  1871. struct msm_drm_private *priv;
  1872. struct sde_vm_ops *vm_ops;
  1873. int i;
  1874. if (!sde_kms || !pdev)
  1875. return;
  1876. dev = sde_kms->dev;
  1877. if (!dev)
  1878. return;
  1879. priv = dev->dev_private;
  1880. if (!priv)
  1881. return;
  1882. if (sde_kms->genpd_init) {
  1883. sde_kms->genpd_init = false;
  1884. pm_genpd_remove(&sde_kms->genpd);
  1885. of_genpd_del_provider(pdev->dev.of_node);
  1886. }
  1887. vm_ops = sde_vm_get_ops(sde_kms);
  1888. if (vm_ops && vm_ops->vm_deinit)
  1889. vm_ops->vm_deinit(sde_kms, vm_ops);
  1890. if (sde_kms->hw_intr)
  1891. sde_hw_intr_destroy(sde_kms->hw_intr);
  1892. sde_kms->hw_intr = NULL;
  1893. if (sde_kms->power_event)
  1894. sde_power_handle_unregister_event(
  1895. &priv->phandle, sde_kms->power_event);
  1896. _sde_kms_release_displays(sde_kms);
  1897. _sde_kms_unmap_all_splash_regions(sde_kms);
  1898. if (sde_kms->catalog) {
  1899. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1900. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1901. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1902. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1903. }
  1904. }
  1905. if (sde_kms->rm_init)
  1906. sde_rm_destroy(&sde_kms->rm);
  1907. sde_kms->rm_init = false;
  1908. if (sde_kms->catalog)
  1909. sde_hw_catalog_deinit(sde_kms->catalog);
  1910. sde_kms->catalog = NULL;
  1911. if (sde_kms->sid)
  1912. msm_iounmap(pdev, sde_kms->sid);
  1913. sde_kms->sid = NULL;
  1914. if (sde_kms->reg_dma)
  1915. msm_iounmap(pdev, sde_kms->reg_dma);
  1916. sde_kms->reg_dma = NULL;
  1917. if (sde_kms->vbif[VBIF_NRT])
  1918. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1919. sde_kms->vbif[VBIF_NRT] = NULL;
  1920. if (sde_kms->vbif[VBIF_RT])
  1921. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1922. sde_kms->vbif[VBIF_RT] = NULL;
  1923. if (sde_kms->mmio)
  1924. msm_iounmap(pdev, sde_kms->mmio);
  1925. sde_kms->mmio = NULL;
  1926. sde_reg_dma_deinit();
  1927. _sde_kms_mmu_destroy(sde_kms);
  1928. }
  1929. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1930. {
  1931. int i;
  1932. if (!sde_kms)
  1933. return -EINVAL;
  1934. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1935. struct msm_mmu *mmu;
  1936. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1937. if (!aspace)
  1938. continue;
  1939. mmu = sde_kms->aspace[i]->mmu;
  1940. if (secure_only &&
  1941. !aspace->mmu->funcs->is_domain_secure(mmu))
  1942. continue;
  1943. /* cleanup aspace before detaching */
  1944. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1945. SDE_DEBUG("Detaching domain:%d\n", i);
  1946. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1947. ARRAY_SIZE(iommu_ports));
  1948. aspace->domain_attached = false;
  1949. }
  1950. return 0;
  1951. }
  1952. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1953. {
  1954. int i;
  1955. if (!sde_kms)
  1956. return -EINVAL;
  1957. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1958. struct msm_mmu *mmu;
  1959. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1960. if (!aspace)
  1961. continue;
  1962. mmu = sde_kms->aspace[i]->mmu;
  1963. if (secure_only &&
  1964. !aspace->mmu->funcs->is_domain_secure(mmu))
  1965. continue;
  1966. SDE_DEBUG("Attaching domain:%d\n", i);
  1967. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1968. ARRAY_SIZE(iommu_ports));
  1969. aspace->domain_attached = true;
  1970. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1971. }
  1972. return 0;
  1973. }
  1974. static void sde_kms_destroy(struct msm_kms *kms)
  1975. {
  1976. struct sde_kms *sde_kms;
  1977. struct drm_device *dev;
  1978. if (!kms) {
  1979. SDE_ERROR("invalid kms\n");
  1980. return;
  1981. }
  1982. sde_kms = to_sde_kms(kms);
  1983. dev = sde_kms->dev;
  1984. if (!dev || !dev->dev) {
  1985. SDE_ERROR("invalid device\n");
  1986. return;
  1987. }
  1988. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1989. kfree(sde_kms);
  1990. }
  1991. static void sde_kms_helper_clear_dim_layers(struct drm_atomic_state *state, struct drm_crtc *crtc)
  1992. {
  1993. struct drm_crtc_state *crtc_state = NULL;
  1994. struct sde_crtc_state *c_state;
  1995. if (!state || !crtc) {
  1996. SDE_ERROR("invalid params\n");
  1997. return;
  1998. }
  1999. crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
  2000. c_state = to_sde_crtc_state(crtc_state);
  2001. _sde_crtc_clear_dim_layers_v1(crtc_state);
  2002. set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, c_state->dirty);
  2003. }
  2004. static int sde_kms_set_crtc_for_conn(struct drm_device *dev,
  2005. struct drm_encoder *enc, struct drm_atomic_state *state)
  2006. {
  2007. struct drm_connector *conn = NULL;
  2008. struct drm_connector *tmp_conn = NULL;
  2009. struct drm_connector_list_iter conn_iter;
  2010. struct drm_crtc_state *crtc_state = NULL;
  2011. struct drm_connector_state *conn_state = NULL;
  2012. int ret = 0;
  2013. drm_connector_list_iter_begin(dev, &conn_iter);
  2014. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2015. if (enc == tmp_conn->state->best_encoder) {
  2016. conn = tmp_conn;
  2017. break;
  2018. }
  2019. }
  2020. drm_connector_list_iter_end(&conn_iter);
  2021. if (!conn || !enc->crtc) {
  2022. SDE_ERROR("invalid params for enc:%d\n", DRMID(enc));
  2023. return -EINVAL;
  2024. }
  2025. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2026. if (IS_ERR(crtc_state)) {
  2027. ret = PTR_ERR(crtc_state);
  2028. SDE_ERROR("error %d getting crtc %d state\n",
  2029. ret, DRMID(enc->crtc));
  2030. return ret;
  2031. }
  2032. conn_state = drm_atomic_get_connector_state(state, conn);
  2033. if (IS_ERR(conn_state)) {
  2034. ret = PTR_ERR(conn_state);
  2035. SDE_ERROR("error %d getting connector %d state\n",
  2036. ret, DRMID(conn));
  2037. return ret;
  2038. }
  2039. crtc_state->active = true;
  2040. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2041. if (ret)
  2042. SDE_ERROR("error %d setting the crtc\n", ret);
  2043. return ret;
  2044. }
  2045. static void _sde_kms_plane_force_remove(struct drm_plane *plane,
  2046. struct drm_atomic_state *state)
  2047. {
  2048. struct drm_plane_state *plane_state;
  2049. int ret = 0;
  2050. plane_state = drm_atomic_get_plane_state(state, plane);
  2051. if (IS_ERR(plane_state)) {
  2052. ret = PTR_ERR(plane_state);
  2053. SDE_ERROR("error %d getting plane %d state\n",
  2054. ret, plane->base.id);
  2055. return;
  2056. }
  2057. plane->old_fb = plane->fb;
  2058. SDE_DEBUG("disabling plane %d\n", plane->base.id);
  2059. ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
  2060. if (ret != 0)
  2061. SDE_ERROR("error %d disabling plane %d\n", ret,
  2062. plane->base.id);
  2063. drm_atomic_set_fb_for_plane(plane_state, NULL);
  2064. }
  2065. static int _sde_kms_remove_fbs(struct sde_kms *sde_kms, struct drm_file *file,
  2066. struct drm_atomic_state *state)
  2067. {
  2068. struct drm_device *dev = sde_kms->dev;
  2069. struct drm_framebuffer *fb, *tfb;
  2070. struct list_head fbs;
  2071. struct drm_plane *plane;
  2072. struct drm_crtc *crtc = NULL;
  2073. unsigned int crtc_mask = 0;
  2074. int ret = 0;
  2075. INIT_LIST_HEAD(&fbs);
  2076. list_for_each_entry_safe(fb, tfb, &file->fbs, filp_head) {
  2077. if (drm_framebuffer_read_refcount(fb) > 1) {
  2078. list_move_tail(&fb->filp_head, &fbs);
  2079. drm_for_each_plane(plane, dev) {
  2080. if (plane->state && plane->state->fb == fb) {
  2081. if (plane->state->crtc)
  2082. crtc_mask |= drm_crtc_mask(plane->state->crtc);
  2083. _sde_kms_plane_force_remove(plane, state);
  2084. }
  2085. }
  2086. } else {
  2087. list_del_init(&fb->filp_head);
  2088. drm_framebuffer_put(fb);
  2089. }
  2090. }
  2091. if (list_empty(&fbs)) {
  2092. SDE_DEBUG("skip commit as no fb(s)\n");
  2093. return 0;
  2094. }
  2095. drm_for_each_crtc(crtc, dev) {
  2096. if ((crtc_mask & drm_crtc_mask(crtc)) && crtc->state->active) {
  2097. struct drm_encoder *drm_enc;
  2098. drm_for_each_encoder_mask(drm_enc, crtc->dev,
  2099. crtc->state->encoder_mask) {
  2100. ret = sde_kms_set_crtc_for_conn(dev, drm_enc, state);
  2101. if (ret)
  2102. goto error;
  2103. }
  2104. sde_kms_helper_clear_dim_layers(state, crtc);
  2105. }
  2106. }
  2107. SDE_EVT32(state, crtc_mask);
  2108. SDE_DEBUG("null commit after removing all the pipes\n");
  2109. ret = drm_atomic_commit(state);
  2110. error:
  2111. if (ret) {
  2112. /*
  2113. * move the fbs back to original list, so it would be
  2114. * handled during drm_release
  2115. */
  2116. list_for_each_entry_safe(fb, tfb, &fbs, filp_head)
  2117. list_move_tail(&fb->filp_head, &file->fbs);
  2118. if (ret == -EDEADLK || ret == -ERESTARTSYS)
  2119. SDE_DEBUG("atomic commit failed in preclose, ret:%d\n", ret);
  2120. else
  2121. SDE_ERROR("atomic commit failed in preclose, ret:%d\n", ret);
  2122. goto end;
  2123. }
  2124. while (!list_empty(&fbs)) {
  2125. fb = list_first_entry(&fbs, typeof(*fb), filp_head);
  2126. list_del_init(&fb->filp_head);
  2127. drm_framebuffer_put(fb);
  2128. }
  2129. end:
  2130. return ret;
  2131. }
  2132. static void sde_kms_preclose(struct msm_kms *kms, struct drm_file *file)
  2133. {
  2134. struct sde_kms *sde_kms = to_sde_kms(kms);
  2135. struct drm_device *dev = sde_kms->dev;
  2136. struct msm_drm_private *priv = dev->dev_private;
  2137. unsigned int i;
  2138. struct drm_atomic_state *state = NULL;
  2139. struct drm_modeset_acquire_ctx ctx;
  2140. int ret = 0;
  2141. /* cancel pending flip event */
  2142. for (i = 0; i < priv->num_crtcs; i++)
  2143. sde_crtc_complete_flip(priv->crtcs[i], file);
  2144. drm_modeset_acquire_init(&ctx, 0);
  2145. retry:
  2146. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2147. if (ret == -EDEADLK) {
  2148. drm_modeset_backoff(&ctx);
  2149. goto retry;
  2150. } else if (WARN_ON(ret)) {
  2151. goto end;
  2152. }
  2153. state = drm_atomic_state_alloc(dev);
  2154. if (!state) {
  2155. ret = -ENOMEM;
  2156. goto end;
  2157. }
  2158. state->acquire_ctx = &ctx;
  2159. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  2160. ret = _sde_kms_remove_fbs(sde_kms, file, state);
  2161. if (ret != -EDEADLK && ret != -ERESTARTSYS)
  2162. break;
  2163. drm_atomic_state_clear(state);
  2164. drm_modeset_backoff(&ctx);
  2165. }
  2166. end:
  2167. if (state)
  2168. drm_atomic_state_put(state);
  2169. SDE_DEBUG("sde preclose done, ret:%d\n", ret);
  2170. drm_modeset_drop_locks(&ctx);
  2171. drm_modeset_acquire_fini(&ctx);
  2172. }
  2173. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  2174. struct drm_atomic_state *state)
  2175. {
  2176. struct drm_device *dev = sde_kms->dev;
  2177. struct drm_plane *plane;
  2178. struct drm_plane_state *plane_state;
  2179. struct drm_crtc *crtc;
  2180. struct drm_crtc_state *crtc_state;
  2181. struct drm_connector *conn;
  2182. struct drm_connector_state *conn_state;
  2183. struct drm_connector_list_iter conn_iter;
  2184. int ret = 0;
  2185. drm_for_each_plane(plane, dev) {
  2186. plane_state = drm_atomic_get_plane_state(state, plane);
  2187. if (IS_ERR(plane_state)) {
  2188. ret = PTR_ERR(plane_state);
  2189. SDE_ERROR("error %d getting plane %d state\n",
  2190. ret, DRMID(plane));
  2191. return ret;
  2192. }
  2193. ret = sde_plane_helper_reset_custom_properties(plane,
  2194. plane_state);
  2195. if (ret) {
  2196. SDE_ERROR("error %d resetting plane props %d\n",
  2197. ret, DRMID(plane));
  2198. return ret;
  2199. }
  2200. }
  2201. drm_for_each_crtc(crtc, dev) {
  2202. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  2203. if (IS_ERR(crtc_state)) {
  2204. ret = PTR_ERR(crtc_state);
  2205. SDE_ERROR("error %d getting crtc %d state\n",
  2206. ret, DRMID(crtc));
  2207. return ret;
  2208. }
  2209. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  2210. if (ret) {
  2211. SDE_ERROR("error %d resetting crtc props %d\n",
  2212. ret, DRMID(crtc));
  2213. return ret;
  2214. }
  2215. }
  2216. drm_connector_list_iter_begin(dev, &conn_iter);
  2217. drm_for_each_connector_iter(conn, &conn_iter) {
  2218. conn_state = drm_atomic_get_connector_state(state, conn);
  2219. if (IS_ERR(conn_state)) {
  2220. ret = PTR_ERR(conn_state);
  2221. SDE_ERROR("error %d getting connector %d state\n",
  2222. ret, DRMID(conn));
  2223. return ret;
  2224. }
  2225. ret = sde_connector_helper_reset_custom_properties(conn,
  2226. conn_state);
  2227. if (ret) {
  2228. SDE_ERROR("error %d resetting connector props %d\n",
  2229. ret, DRMID(conn));
  2230. return ret;
  2231. }
  2232. }
  2233. drm_connector_list_iter_end(&conn_iter);
  2234. return ret;
  2235. }
  2236. static void sde_kms_lastclose(struct msm_kms *kms)
  2237. {
  2238. struct sde_kms *sde_kms;
  2239. struct drm_device *dev;
  2240. struct drm_atomic_state *state;
  2241. struct drm_modeset_acquire_ctx ctx;
  2242. int ret;
  2243. if (!kms) {
  2244. SDE_ERROR("invalid argument\n");
  2245. return;
  2246. }
  2247. sde_kms = to_sde_kms(kms);
  2248. dev = sde_kms->dev;
  2249. drm_modeset_acquire_init(&ctx, 0);
  2250. state = drm_atomic_state_alloc(dev);
  2251. if (!state) {
  2252. ret = -ENOMEM;
  2253. goto out_ctx;
  2254. }
  2255. state->acquire_ctx = &ctx;
  2256. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  2257. retry:
  2258. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2259. if (ret)
  2260. goto out_state;
  2261. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  2262. if (ret)
  2263. goto out_state;
  2264. ret = drm_atomic_commit(state);
  2265. out_state:
  2266. if (ret == -EDEADLK)
  2267. goto backoff;
  2268. drm_atomic_state_put(state);
  2269. out_ctx:
  2270. drm_modeset_drop_locks(&ctx);
  2271. drm_modeset_acquire_fini(&ctx);
  2272. if (ret)
  2273. SDE_ERROR("kms lastclose failed: %d\n", ret);
  2274. SDE_EVT32(ret, SDE_EVTLOG_FUNC_EXIT);
  2275. return;
  2276. backoff:
  2277. drm_atomic_state_clear(state);
  2278. drm_modeset_backoff(&ctx);
  2279. SDE_EVT32(ret, SDE_EVTLOG_FUNC_CASE1);
  2280. goto retry;
  2281. }
  2282. static int _sde_kms_validate_vm_request(struct drm_atomic_state *state, struct sde_kms *sde_kms,
  2283. enum sde_crtc_vm_req vm_req, bool vm_owns_hw)
  2284. {
  2285. struct drm_crtc *crtc, *active_crtc = NULL, *global_active_crtc = NULL;
  2286. struct drm_crtc_state *new_cstate, *old_cstate, *active_cstate;
  2287. struct drm_encoder *encoder;
  2288. struct drm_connector *connector;
  2289. struct drm_connector_state *new_connstate;
  2290. struct sde_vm_ops *vm_ops = sde_vm_get_ops(sde_kms);
  2291. struct sde_mdss_cfg *catalog = sde_kms->catalog;
  2292. struct sde_connector *sde_conn;
  2293. struct dsi_display *dsi_display;
  2294. uint32_t i, commit_crtc_cnt = 0, global_crtc_cnt = 0;
  2295. uint32_t crtc_encoder_cnt = 0;
  2296. enum sde_crtc_idle_pc_state idle_pc_state;
  2297. int rc = 0;
  2298. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  2299. struct sde_crtc_state *new_state = NULL;
  2300. if (!new_cstate->active && !old_cstate->active)
  2301. continue;
  2302. new_state = to_sde_crtc_state(new_cstate);
  2303. idle_pc_state = sde_crtc_get_property(new_state, CRTC_PROP_IDLE_PC_STATE);
  2304. active_crtc = crtc;
  2305. active_cstate = new_cstate;
  2306. commit_crtc_cnt++;
  2307. }
  2308. list_for_each_entry(crtc, &sde_kms->dev->mode_config.crtc_list, head) {
  2309. if (!crtc->state->active)
  2310. continue;
  2311. global_crtc_cnt++;
  2312. global_active_crtc = crtc;
  2313. }
  2314. if (active_crtc) {
  2315. drm_for_each_encoder_mask(encoder, active_crtc->dev, active_cstate->encoder_mask)
  2316. crtc_encoder_cnt++;
  2317. }
  2318. for_each_new_connector_in_state(state, connector, new_connstate, i) {
  2319. int conn_mask = active_cstate->connector_mask;
  2320. if (drm_connector_mask(connector) & conn_mask) {
  2321. sde_conn = to_sde_connector(connector);
  2322. dsi_display = (struct dsi_display *) sde_conn->display;
  2323. SDE_EVT32(DRMID(connector), DRMID(active_crtc), i, dsi_display->type,
  2324. dsi_display->trusted_vm_env);
  2325. SDE_DEBUG("VM display:%s, conn:%d, crtc:%d, type:%d, tvm:%d\n",
  2326. dsi_display->name, DRMID(connector), DRMID(active_crtc),
  2327. dsi_display->type, dsi_display->trusted_vm_env);
  2328. break;
  2329. }
  2330. }
  2331. /* Check for single crtc commits only on valid VM requests */
  2332. if (active_crtc && global_active_crtc &&
  2333. (commit_crtc_cnt > catalog->max_trusted_vm_displays ||
  2334. global_crtc_cnt > catalog->max_trusted_vm_displays ||
  2335. active_crtc != global_active_crtc)) {
  2336. SDE_ERROR("VM switch failed; MAX:%d a_cnt:%d g_cnt:%d a_crtc:%d g_crtc:%d\n",
  2337. catalog->max_trusted_vm_displays, commit_crtc_cnt, global_crtc_cnt,
  2338. DRMID(active_crtc), DRMID(global_active_crtc));
  2339. return -E2BIG;
  2340. } else if ((vm_req == VM_REQ_RELEASE) &&
  2341. ((idle_pc_state == IDLE_PC_ENABLE) ||
  2342. (crtc_encoder_cnt > TRUSTED_VM_MAX_ENCODER_PER_CRTC))) {
  2343. /*
  2344. * disable idle-pc before releasing the HW
  2345. * allow only specified number of encoders on a given crtc
  2346. */
  2347. SDE_ERROR("VM switch failed; idle-pc:%d max:%d encoder_cnt:%d\n",
  2348. idle_pc_state, TRUSTED_VM_MAX_ENCODER_PER_CRTC, crtc_encoder_cnt);
  2349. return -EINVAL;
  2350. }
  2351. if ((vm_req == VM_REQ_ACQUIRE) && !vm_owns_hw) {
  2352. rc = vm_ops->vm_acquire(sde_kms);
  2353. if (rc) {
  2354. SDE_ERROR("VM acquire failed; hw_owner:%d, rc:%d\n", vm_owns_hw, rc);
  2355. return rc;
  2356. }
  2357. if (vm_ops->vm_resource_init)
  2358. rc = vm_ops->vm_resource_init(sde_kms, state);
  2359. }
  2360. return rc;
  2361. }
  2362. static int sde_kms_check_vm_request(struct msm_kms *kms,
  2363. struct drm_atomic_state *state)
  2364. {
  2365. struct sde_kms *sde_kms;
  2366. struct drm_crtc *crtc;
  2367. struct drm_crtc_state *new_cstate, *old_cstate;
  2368. struct sde_vm_ops *vm_ops;
  2369. enum sde_crtc_vm_req old_vm_req = VM_REQ_NONE, new_vm_req = VM_REQ_NONE;
  2370. int i, rc = 0;
  2371. bool vm_req_active = false;
  2372. bool vm_owns_hw;
  2373. if (!kms || !state)
  2374. return -EINVAL;
  2375. sde_kms = to_sde_kms(kms);
  2376. vm_ops = sde_vm_get_ops(sde_kms);
  2377. if (!vm_ops)
  2378. return 0;
  2379. if (!vm_ops->vm_request_valid || !vm_ops->vm_owns_hw || !vm_ops->vm_acquire)
  2380. return -EINVAL;
  2381. /* check for an active vm request */
  2382. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  2383. struct sde_crtc_state *old_state = NULL, *new_state = NULL;
  2384. if (!new_cstate->active && !old_cstate->active)
  2385. continue;
  2386. new_state = to_sde_crtc_state(new_cstate);
  2387. new_vm_req = sde_crtc_get_property(new_state, CRTC_PROP_VM_REQ_STATE);
  2388. old_state = to_sde_crtc_state(old_cstate);
  2389. old_vm_req = sde_crtc_get_property(old_state, CRTC_PROP_VM_REQ_STATE);
  2390. /* No active request if the transition is from VM_REQ_NONE to VM_REQ_NONE */
  2391. if (old_vm_req || new_vm_req) {
  2392. if (!vm_req_active) {
  2393. sde_vm_lock(sde_kms);
  2394. vm_owns_hw = sde_vm_owns_hw(sde_kms);
  2395. }
  2396. rc = vm_ops->vm_request_valid(sde_kms, old_vm_req, new_vm_req);
  2397. if (rc) {
  2398. SDE_ERROR(
  2399. "VM transition check failed; o_state:%d, n_state:%d, hw_owner:%d, rc:%d\n",
  2400. old_vm_req, new_vm_req, vm_owns_hw, rc);
  2401. sde_vm_unlock(sde_kms);
  2402. vm_req_active = false;
  2403. break;
  2404. } else if (old_vm_req == VM_REQ_ACQUIRE && new_vm_req == VM_REQ_NONE) {
  2405. SDE_DEBUG("VM transition valid; ignore further checks\n");
  2406. if (!vm_req_active)
  2407. sde_vm_unlock(sde_kms);
  2408. } else {
  2409. vm_req_active = true;
  2410. }
  2411. }
  2412. }
  2413. /* validate active requests and perform acquire if necessary */
  2414. if (vm_req_active) {
  2415. rc = _sde_kms_validate_vm_request(state, sde_kms, new_vm_req, vm_owns_hw);
  2416. sde_vm_unlock(sde_kms);
  2417. SDE_EVT32(old_vm_req, new_vm_req, vm_req_active, vm_owns_hw, rc);
  2418. SDE_DEBUG("VM o_state:%d, n_state:%d, hw_owner:%d, rc:%d\n", old_vm_req, new_vm_req,
  2419. vm_req_active ? vm_owns_hw : -1, rc);
  2420. }
  2421. return rc;
  2422. }
  2423. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  2424. struct drm_atomic_state *state)
  2425. {
  2426. struct sde_kms *sde_kms;
  2427. struct drm_device *dev;
  2428. struct drm_crtc *crtc;
  2429. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  2430. struct drm_crtc_state *crtc_state;
  2431. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  2432. bool sec_session = false, global_sec_session = false;
  2433. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  2434. int i;
  2435. if (!kms || !state) {
  2436. return -EINVAL;
  2437. SDE_ERROR("invalid arguments\n");
  2438. }
  2439. sde_kms = to_sde_kms(kms);
  2440. dev = sde_kms->dev;
  2441. /* iterate state object for active secure/non-secure crtc */
  2442. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  2443. if (!crtc_state->active)
  2444. continue;
  2445. active_crtc_cnt++;
  2446. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  2447. &fb_sec, &fb_sec_dir);
  2448. if (fb_sec_dir)
  2449. sec_session = true;
  2450. cur_crtc = crtc;
  2451. }
  2452. /* iterate global list for active and secure/non-secure crtc */
  2453. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2454. if (!crtc->state->active)
  2455. continue;
  2456. global_active_crtc_cnt++;
  2457. /* update only when crtc is not the same as current crtc */
  2458. if (crtc != cur_crtc) {
  2459. fb_ns = fb_sec = fb_sec_dir = 0;
  2460. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  2461. &fb_sec, &fb_sec_dir);
  2462. if (fb_sec_dir)
  2463. global_sec_session = true;
  2464. global_crtc = crtc;
  2465. }
  2466. }
  2467. if (!global_sec_session && !sec_session)
  2468. return 0;
  2469. /*
  2470. * - fail crtc commit, if secure-camera/secure-ui session is
  2471. * in-progress in any other display
  2472. * - fail secure-camera/secure-ui crtc commit, if any other display
  2473. * session is in-progress
  2474. */
  2475. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  2476. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  2477. SDE_ERROR(
  2478. "crtc%d secure check failed global_active:%d active:%d\n",
  2479. cur_crtc ? cur_crtc->base.id : -1,
  2480. global_active_crtc_cnt, active_crtc_cnt);
  2481. return -EPERM;
  2482. /*
  2483. * As only one crtc is allowed during secure session, the crtc
  2484. * in this commit should match with the global crtc
  2485. */
  2486. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  2487. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  2488. cur_crtc->base.id, sec_session,
  2489. global_crtc->base.id, global_sec_session);
  2490. return -EPERM;
  2491. }
  2492. return 0;
  2493. }
  2494. static void sde_kms_vm_res_release(struct msm_kms *kms,
  2495. struct drm_atomic_state *state)
  2496. {
  2497. struct drm_crtc *crtc;
  2498. struct drm_crtc_state *new_cstate;
  2499. struct sde_crtc_state *cstate;
  2500. struct sde_vm_ops *vm_ops;
  2501. enum sde_crtc_vm_req vm_req;
  2502. struct sde_kms *sde_kms = to_sde_kms(kms);
  2503. vm_ops = sde_vm_get_ops(sde_kms);
  2504. if (!vm_ops)
  2505. return;
  2506. crtc = sde_kms_vm_get_vm_crtc(state);
  2507. if (!crtc)
  2508. return;
  2509. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  2510. cstate = to_sde_crtc_state(new_cstate);
  2511. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  2512. if (vm_req != VM_REQ_ACQUIRE)
  2513. return;
  2514. sde_vm_lock(sde_kms);
  2515. if (vm_ops->vm_acquire_fail_handler)
  2516. vm_ops->vm_acquire_fail_handler(sde_kms);
  2517. sde_vm_unlock(sde_kms);
  2518. }
  2519. static int sde_kms_atomic_check(struct msm_kms *kms,
  2520. struct drm_atomic_state *state)
  2521. {
  2522. struct sde_kms *sde_kms;
  2523. struct drm_device *dev;
  2524. int ret;
  2525. if (!kms || !state)
  2526. return -EINVAL;
  2527. sde_kms = to_sde_kms(kms);
  2528. dev = sde_kms->dev;
  2529. SDE_ATRACE_BEGIN("atomic_check");
  2530. if (sde_kms_is_suspend_blocked(dev)) {
  2531. SDE_DEBUG("suspended, skip atomic_check\n");
  2532. ret = -EBUSY;
  2533. goto end;
  2534. }
  2535. ret = sde_kms_check_vm_request(kms, state);
  2536. if (ret) {
  2537. SDE_ERROR("vm switch request checks failed\n");
  2538. goto end;
  2539. }
  2540. ret = drm_atomic_helper_check(dev, state);
  2541. if (ret)
  2542. goto vm_clean_up;
  2543. /*
  2544. * Check if any secure transition(moving CRTC between secure and
  2545. * non-secure state and vice-versa) is allowed or not. when moving
  2546. * to secure state, planes with fb_mode set to dir_translated only can
  2547. * be staged on the CRTC, and only one CRTC can be active during
  2548. * Secure state
  2549. */
  2550. ret = sde_kms_check_secure_transition(kms, state);
  2551. if (ret)
  2552. goto vm_clean_up;
  2553. goto end;
  2554. vm_clean_up:
  2555. sde_kms_vm_res_release(kms, state);
  2556. end:
  2557. SDE_ATRACE_END("atomic_check");
  2558. return ret;
  2559. }
  2560. static struct msm_gem_address_space*
  2561. _sde_kms_get_address_space(struct msm_kms *kms,
  2562. unsigned int domain)
  2563. {
  2564. struct sde_kms *sde_kms;
  2565. if (!kms) {
  2566. SDE_ERROR("invalid kms\n");
  2567. return NULL;
  2568. }
  2569. sde_kms = to_sde_kms(kms);
  2570. if (!sde_kms) {
  2571. SDE_ERROR("invalid sde_kms\n");
  2572. return NULL;
  2573. }
  2574. if (domain >= MSM_SMMU_DOMAIN_MAX)
  2575. return NULL;
  2576. return (sde_kms->aspace[domain] &&
  2577. sde_kms->aspace[domain]->domain_attached) ?
  2578. sde_kms->aspace[domain] : NULL;
  2579. }
  2580. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  2581. unsigned int domain)
  2582. {
  2583. struct sde_kms *sde_kms;
  2584. struct msm_gem_address_space *aspace;
  2585. if (!kms) {
  2586. SDE_ERROR("invalid kms\n");
  2587. return NULL;
  2588. }
  2589. sde_kms = to_sde_kms(kms);
  2590. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  2591. SDE_ERROR("invalid params\n");
  2592. return NULL;
  2593. }
  2594. aspace = _sde_kms_get_address_space(kms, domain);
  2595. return (aspace && aspace->domain_attached) ?
  2596. msm_gem_get_aspace_device(aspace) : NULL;
  2597. }
  2598. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  2599. {
  2600. struct drm_device *dev = NULL;
  2601. struct sde_kms *sde_kms = NULL;
  2602. struct drm_connector *connector = NULL;
  2603. struct drm_connector_list_iter conn_iter;
  2604. struct sde_connector *sde_conn = NULL;
  2605. if (!kms) {
  2606. SDE_ERROR("invalid kms\n");
  2607. return;
  2608. }
  2609. sde_kms = to_sde_kms(kms);
  2610. dev = sde_kms->dev;
  2611. if (!dev) {
  2612. SDE_ERROR("invalid device\n");
  2613. return;
  2614. }
  2615. if (!dev->mode_config.poll_enabled)
  2616. return;
  2617. mutex_lock(&dev->mode_config.mutex);
  2618. drm_connector_list_iter_begin(dev, &conn_iter);
  2619. drm_for_each_connector_iter(connector, &conn_iter) {
  2620. /* Only handle HPD capable connectors. */
  2621. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  2622. continue;
  2623. sde_conn = to_sde_connector(connector);
  2624. if (sde_conn->ops.post_open)
  2625. sde_conn->ops.post_open(&sde_conn->base,
  2626. sde_conn->display);
  2627. }
  2628. drm_connector_list_iter_end(&conn_iter);
  2629. mutex_unlock(&dev->mode_config.mutex);
  2630. }
  2631. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  2632. struct sde_splash_display *splash_display,
  2633. struct drm_crtc *crtc)
  2634. {
  2635. struct msm_drm_private *priv;
  2636. struct drm_plane *plane;
  2637. struct sde_splash_mem *splash;
  2638. struct sde_splash_mem *demura;
  2639. struct sde_plane_state *pstate;
  2640. struct sde_sspp_index_info *pipe_info;
  2641. enum sde_sspp pipe_id;
  2642. bool is_virtual;
  2643. int i;
  2644. if (!sde_kms || !splash_display || !crtc) {
  2645. SDE_ERROR("invalid input args\n");
  2646. return -EINVAL;
  2647. }
  2648. priv = sde_kms->dev->dev_private;
  2649. pipe_info = &splash_display->pipe_info;
  2650. splash = splash_display->splash;
  2651. demura = splash_display->demura;
  2652. for (i = 0; i < priv->num_planes; i++) {
  2653. plane = priv->planes[i];
  2654. pipe_id = sde_plane_pipe(plane);
  2655. is_virtual = is_sde_plane_virtual(plane);
  2656. if ((is_virtual && test_bit(pipe_id, pipe_info->virt_pipes)) ||
  2657. (!is_virtual && test_bit(pipe_id, pipe_info->pipes))) {
  2658. if (splash && sde_plane_validate_src_addr(plane,
  2659. splash->splash_buf_base,
  2660. splash->splash_buf_size)) {
  2661. if (!demura || sde_plane_validate_src_addr(
  2662. plane, demura->splash_buf_base,
  2663. demura->splash_buf_size)) {
  2664. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  2665. pipe_id, DRMID(crtc));
  2666. continue;
  2667. }
  2668. }
  2669. plane->state->crtc = crtc;
  2670. crtc->state->plane_mask |= drm_plane_mask(plane);
  2671. pstate = to_sde_plane_state(plane->state);
  2672. pstate->cont_splash_populated = true;
  2673. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  2674. DRMID(crtc), DRMID(plane), is_virtual);
  2675. }
  2676. }
  2677. return 0;
  2678. }
  2679. static int sde_kms_inform_cont_splash_res_disable(struct msm_kms *kms,
  2680. struct dsi_display *dsi_display)
  2681. {
  2682. void *display;
  2683. struct drm_encoder *encoder = NULL;
  2684. struct msm_display_info info;
  2685. struct drm_device *dev;
  2686. struct sde_kms *sde_kms;
  2687. struct drm_connector_list_iter conn_iter;
  2688. struct drm_connector *connector = NULL;
  2689. struct sde_connector *sde_conn = NULL;
  2690. int rc = 0;
  2691. sde_kms = to_sde_kms(kms);
  2692. dev = sde_kms->dev;
  2693. display = dsi_display;
  2694. if (dsi_display) {
  2695. if (dsi_display->bridge->base.encoder) {
  2696. encoder = dsi_display->bridge->base.encoder;
  2697. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2698. }
  2699. memset(&info, 0x0, sizeof(info));
  2700. rc = dsi_display_get_info(NULL, &info, display);
  2701. if (rc) {
  2702. SDE_ERROR("%s: dsi get_info failed: %d\n",
  2703. __func__, rc);
  2704. encoder = NULL;
  2705. }
  2706. }
  2707. drm_connector_list_iter_begin(dev, &conn_iter);
  2708. drm_for_each_connector_iter(connector, &conn_iter) {
  2709. struct drm_encoder *c_encoder;
  2710. drm_connector_for_each_possible_encoder(connector,
  2711. c_encoder)
  2712. break;
  2713. if (!c_encoder) {
  2714. SDE_ERROR("c_encoder not found\n");
  2715. return -EINVAL;
  2716. }
  2717. /**
  2718. * Inform cont_splash is disabled to each interface/connector.
  2719. * This is currently supported for DSI interface.
  2720. */
  2721. sde_conn = to_sde_connector(connector);
  2722. if (sde_conn && sde_conn->ops.cont_splash_res_disable) {
  2723. if (!dsi_display || !encoder) {
  2724. sde_conn->ops.cont_splash_res_disable
  2725. (sde_conn->display);
  2726. } else if (c_encoder->base.id == encoder->base.id) {
  2727. /**
  2728. * This handles dual DSI
  2729. * configuration where one DSI
  2730. * interface has cont_splash
  2731. * enabled and the other doesn't.
  2732. */
  2733. sde_conn->ops.cont_splash_res_disable
  2734. (sde_conn->display);
  2735. break;
  2736. }
  2737. }
  2738. }
  2739. drm_connector_list_iter_end(&conn_iter);
  2740. return 0;
  2741. }
  2742. static int sde_kms_vm_trusted_cont_splash_res_init(struct sde_kms *sde_kms)
  2743. {
  2744. int i;
  2745. void *display;
  2746. struct dsi_display *dsi_display;
  2747. struct drm_encoder *encoder;
  2748. if (!sde_kms)
  2749. return -EINVAL;
  2750. if (!sde_in_trusted_vm(sde_kms))
  2751. return 0;
  2752. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  2753. display = sde_kms->dsi_displays[i];
  2754. dsi_display = (struct dsi_display *)display;
  2755. if (!dsi_display->bridge->base.encoder) {
  2756. SDE_ERROR("no encoder on dsi display:%d", i);
  2757. return -EINVAL;
  2758. }
  2759. encoder = dsi_display->bridge->base.encoder;
  2760. encoder->possible_crtcs = 1 << i;
  2761. SDE_DEBUG(
  2762. "dsi-display:%d encoder id[%d]=%d name=%s crtcs=%x\n", i,
  2763. encoder->index, encoder->base.id,
  2764. encoder->name, encoder->possible_crtcs);
  2765. }
  2766. return 0;
  2767. }
  2768. static struct drm_display_mode *_sde_kms_get_splash_mode(
  2769. struct sde_kms *sde_kms, struct drm_connector *connector,
  2770. struct drm_atomic_state *state)
  2771. {
  2772. struct drm_display_mode *mode, *cur_mode = NULL;
  2773. struct drm_crtc *crtc;
  2774. struct drm_crtc_state *new_cstate, *old_cstate;
  2775. u32 i = 0;
  2776. if (sde_kms->splash_data.type == SDE_SPLASH_HANDOFF) {
  2777. list_for_each_entry(mode, &connector->modes, head) {
  2778. if (mode->type & DRM_MODE_TYPE_PREFERRED) {
  2779. cur_mode = mode;
  2780. break;
  2781. }
  2782. }
  2783. } else if (state) {
  2784. /* get the mode from first atomic_check phase for trusted_vm*/
  2785. for_each_oldnew_crtc_in_state(state, crtc, old_cstate,
  2786. new_cstate, i) {
  2787. if (!new_cstate->active && !old_cstate->active)
  2788. continue;
  2789. list_for_each_entry(mode, &connector->modes, head) {
  2790. if (drm_mode_equal(&new_cstate->mode, mode)) {
  2791. cur_mode = mode;
  2792. break;
  2793. }
  2794. }
  2795. }
  2796. }
  2797. return cur_mode;
  2798. }
  2799. static int sde_kms_cont_splash_config(struct msm_kms *kms,
  2800. struct drm_atomic_state *state)
  2801. {
  2802. void *display;
  2803. struct dsi_display *dsi_display;
  2804. struct msm_display_info info;
  2805. struct drm_encoder *encoder = NULL;
  2806. struct drm_crtc *crtc = NULL;
  2807. int i, rc = 0;
  2808. struct drm_display_mode *drm_mode = NULL;
  2809. struct drm_device *dev;
  2810. struct msm_drm_private *priv;
  2811. struct sde_kms *sde_kms;
  2812. struct drm_connector_list_iter conn_iter;
  2813. struct drm_connector *connector = NULL;
  2814. struct sde_connector *sde_conn = NULL;
  2815. struct sde_splash_display *splash_display;
  2816. if (!kms) {
  2817. SDE_ERROR("invalid kms\n");
  2818. return -EINVAL;
  2819. }
  2820. sde_kms = to_sde_kms(kms);
  2821. dev = sde_kms->dev;
  2822. if (!dev) {
  2823. SDE_ERROR("invalid device\n");
  2824. return -EINVAL;
  2825. }
  2826. rc = sde_kms_vm_trusted_cont_splash_res_init(sde_kms);
  2827. if (rc) {
  2828. SDE_ERROR("failed vm cont splash resource init, rc=%d", rc);
  2829. return -EINVAL;
  2830. }
  2831. if (((sde_kms->splash_data.type == SDE_SPLASH_HANDOFF)
  2832. && (!sde_kms->splash_data.num_splash_regions)) ||
  2833. !sde_kms->splash_data.num_splash_displays) {
  2834. DRM_INFO("cont_splash feature not enabled\n");
  2835. sde_kms_inform_cont_splash_res_disable(kms, NULL);
  2836. return rc;
  2837. }
  2838. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  2839. sde_kms->splash_data.num_splash_displays,
  2840. sde_kms->dsi_display_count);
  2841. /* dsi */
  2842. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  2843. struct sde_crtc_state *cstate;
  2844. struct sde_connector_state *conn_state;
  2845. display = sde_kms->dsi_displays[i];
  2846. dsi_display = (struct dsi_display *)display;
  2847. splash_display = &sde_kms->splash_data.splash_display[i];
  2848. if (!splash_display->cont_splash_enabled) {
  2849. SDE_DEBUG("display->name = %s splash not enabled\n",
  2850. dsi_display->name);
  2851. sde_kms_inform_cont_splash_res_disable(kms,
  2852. dsi_display);
  2853. continue;
  2854. }
  2855. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  2856. if (dsi_display->bridge->base.encoder) {
  2857. encoder = dsi_display->bridge->base.encoder;
  2858. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2859. }
  2860. memset(&info, 0x0, sizeof(info));
  2861. rc = dsi_display_get_info(NULL, &info, display);
  2862. if (rc) {
  2863. SDE_ERROR("dsi get_info %d failed\n", i);
  2864. encoder = NULL;
  2865. continue;
  2866. }
  2867. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  2868. ((info.is_connected) ? "true" : "false"),
  2869. info.display_type);
  2870. if (!encoder) {
  2871. SDE_ERROR("encoder not initialized\n");
  2872. return -EINVAL;
  2873. }
  2874. priv = sde_kms->dev->dev_private;
  2875. encoder->crtc = priv->crtcs[i];
  2876. crtc = encoder->crtc;
  2877. splash_display->encoder = encoder;
  2878. SDE_DEBUG("for dsi-display:%d crtc id[%d]:%d enc id[%d]:%d\n",
  2879. i, crtc->index, crtc->base.id, encoder->index,
  2880. encoder->base.id);
  2881. mutex_lock(&dev->mode_config.mutex);
  2882. drm_connector_list_iter_begin(dev, &conn_iter);
  2883. drm_for_each_connector_iter(connector, &conn_iter) {
  2884. struct drm_encoder *c_encoder;
  2885. drm_connector_for_each_possible_encoder(connector,
  2886. c_encoder)
  2887. break;
  2888. if (!c_encoder) {
  2889. SDE_ERROR("c_encoder not found\n");
  2890. mutex_unlock(&dev->mode_config.mutex);
  2891. return -EINVAL;
  2892. }
  2893. /**
  2894. * SDE_KMS doesn't attach more than one encoder to
  2895. * a DSI connector. So it is safe to check only with
  2896. * the first encoder entry. Revisit this logic if we
  2897. * ever have to support continuous splash for
  2898. * external displays in MST configuration.
  2899. */
  2900. if (c_encoder->base.id == encoder->base.id)
  2901. break;
  2902. }
  2903. drm_connector_list_iter_end(&conn_iter);
  2904. if (!connector) {
  2905. SDE_ERROR("connector not initialized\n");
  2906. mutex_unlock(&dev->mode_config.mutex);
  2907. return -EINVAL;
  2908. }
  2909. mutex_unlock(&dev->mode_config.mutex);
  2910. crtc->state->encoder_mask = drm_encoder_mask(encoder);
  2911. crtc->state->connector_mask = drm_connector_mask(connector);
  2912. connector->state->crtc = crtc;
  2913. drm_mode = _sde_kms_get_splash_mode(sde_kms, connector, state);
  2914. if (!drm_mode) {
  2915. SDE_ERROR("drm_mode not found; handoff_type:%d\n",
  2916. sde_kms->splash_data.type);
  2917. return -EINVAL;
  2918. }
  2919. SDE_DEBUG(
  2920. "drm_mode->name:%s, type:0x%x, flags:0x%x, handoff_type:%d\n",
  2921. drm_mode->name, drm_mode->type,
  2922. drm_mode->flags, sde_kms->splash_data.type);
  2923. /* Update CRTC drm structure */
  2924. crtc->state->active = true;
  2925. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  2926. if (rc) {
  2927. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  2928. return rc;
  2929. }
  2930. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  2931. drm_mode_copy(&crtc->mode, drm_mode);
  2932. cstate = to_sde_crtc_state(crtc->state);
  2933. cstate->cont_splash_populated = true;
  2934. /* Update encoder structure */
  2935. sde_encoder_update_caps_for_cont_splash(encoder,
  2936. splash_display, true);
  2937. sde_crtc_update_cont_splash_settings(crtc);
  2938. sde_conn = to_sde_connector(connector);
  2939. if (sde_conn && sde_conn->ops.cont_splash_config)
  2940. sde_conn->ops.cont_splash_config(sde_conn->display);
  2941. conn_state = to_sde_connector_state(connector->state);
  2942. conn_state->cont_splash_populated = true;
  2943. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  2944. splash_display, crtc);
  2945. if (rc) {
  2946. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  2947. return rc;
  2948. }
  2949. }
  2950. return rc;
  2951. }
  2952. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  2953. {
  2954. struct sde_kms *sde_kms;
  2955. if (!kms) {
  2956. SDE_ERROR("invalid kms\n");
  2957. return false;
  2958. }
  2959. sde_kms = to_sde_kms(kms);
  2960. return sde_kms->splash_data.num_splash_displays;
  2961. }
  2962. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  2963. const struct drm_display_mode *mode,
  2964. const struct msm_resource_caps_info *res, u32 *num_lm)
  2965. {
  2966. struct sde_kms *sde_kms;
  2967. s64 mode_clock_hz = 0;
  2968. s64 max_mdp_clock_hz = 0;
  2969. s64 max_lm_width = 0;
  2970. s64 hdisplay_fp = 0;
  2971. s64 htotal_fp = 0;
  2972. s64 vtotal_fp = 0;
  2973. s64 vrefresh_fp = 0;
  2974. s64 mdp_fudge_factor = 0;
  2975. s64 num_lm_fp = 0;
  2976. s64 lm_clk_fp = 0;
  2977. s64 lm_width_fp = 0;
  2978. int rc = 0;
  2979. if (!num_lm) {
  2980. SDE_ERROR("invalid num_lm pointer\n");
  2981. return -EINVAL;
  2982. }
  2983. /* default to 1 layer mixer */
  2984. *num_lm = 1;
  2985. if (!kms || !mode || !res) {
  2986. SDE_ERROR("invalid input args\n");
  2987. return -EINVAL;
  2988. }
  2989. sde_kms = to_sde_kms(kms);
  2990. max_mdp_clock_hz = drm_int2fixp(sde_kms->perf.max_core_clk_rate);
  2991. max_lm_width = drm_int2fixp(res->max_mixer_width);
  2992. hdisplay_fp = drm_int2fixp(mode->hdisplay);
  2993. htotal_fp = drm_int2fixp(mode->htotal);
  2994. vtotal_fp = drm_int2fixp(mode->vtotal);
  2995. vrefresh_fp = drm_int2fixp(drm_mode_vrefresh(mode));
  2996. mdp_fudge_factor = drm_fixp_from_fraction(105, 100);
  2997. /* mode clock = [(h * v * fps * 1.05) / (num_lm)] */
  2998. mode_clock_hz = drm_fixp_mul(htotal_fp, vtotal_fp);
  2999. mode_clock_hz = drm_fixp_mul(mode_clock_hz, vrefresh_fp);
  3000. mode_clock_hz = drm_fixp_mul(mode_clock_hz, mdp_fudge_factor);
  3001. if (mode_clock_hz > max_mdp_clock_hz ||
  3002. hdisplay_fp > max_lm_width) {
  3003. *num_lm = 0;
  3004. do {
  3005. *num_lm += 2;
  3006. num_lm_fp = drm_int2fixp(*num_lm);
  3007. lm_clk_fp = drm_fixp_div(mode_clock_hz, num_lm_fp);
  3008. lm_width_fp = drm_fixp_div(hdisplay_fp, num_lm_fp);
  3009. if (*num_lm > 4) {
  3010. rc = -EINVAL;
  3011. goto error;
  3012. }
  3013. } while (lm_clk_fp > max_mdp_clock_hz ||
  3014. lm_width_fp > max_lm_width);
  3015. mode_clock_hz = lm_clk_fp;
  3016. }
  3017. SDE_DEBUG("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%u max_clk=%llu\n",
  3018. mode->name, mode->htotal, mode->vtotal, drm_mode_vrefresh(mode),
  3019. *num_lm, drm_fixp2int(mode_clock_hz),
  3020. sde_kms->perf.max_core_clk_rate);
  3021. return 0;
  3022. error:
  3023. SDE_ERROR("required mode clk exceeds max mdp clk\n");
  3024. SDE_ERROR("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%u max_clk=%llu\n",
  3025. mode->name, mode->htotal, mode->vtotal, drm_mode_vrefresh(mode),
  3026. *num_lm, drm_fixp2int(mode_clock_hz),
  3027. sde_kms->perf.max_core_clk_rate);
  3028. return rc;
  3029. }
  3030. static int sde_kms_get_dsc_count(const struct msm_kms *kms,
  3031. u32 hdisplay, u32 *num_dsc)
  3032. {
  3033. struct sde_kms *sde_kms;
  3034. uint32_t max_dsc_width;
  3035. if (!num_dsc) {
  3036. SDE_ERROR("invalid num_dsc pointer\n");
  3037. return -EINVAL;
  3038. }
  3039. *num_dsc = 0;
  3040. if (!kms || !hdisplay) {
  3041. SDE_ERROR("invalid input args\n");
  3042. return -EINVAL;
  3043. }
  3044. sde_kms = to_sde_kms(kms);
  3045. max_dsc_width = sde_kms->catalog->max_dsc_width;
  3046. *num_dsc = DIV_ROUND_UP(hdisplay, max_dsc_width);
  3047. SDE_DEBUG("h=%d, max_dsc_width=%d, num_dsc=%d\n",
  3048. hdisplay, max_dsc_width,
  3049. *num_dsc);
  3050. return 0;
  3051. }
  3052. static void _sde_kms_null_commit(struct drm_device *dev,
  3053. struct drm_encoder *enc)
  3054. {
  3055. struct drm_modeset_acquire_ctx ctx;
  3056. struct drm_atomic_state *state = NULL;
  3057. int retry_cnt = 0;
  3058. int ret = 0;
  3059. drm_modeset_acquire_init(&ctx, 0);
  3060. retry:
  3061. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  3062. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  3063. drm_modeset_backoff(&ctx);
  3064. retry_cnt++;
  3065. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  3066. goto retry;
  3067. } else if (WARN_ON(ret)) {
  3068. goto end;
  3069. }
  3070. state = drm_atomic_state_alloc(dev);
  3071. if (!state) {
  3072. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  3073. goto end;
  3074. }
  3075. state->acquire_ctx = &ctx;
  3076. ret = sde_kms_set_crtc_for_conn(dev, enc, state);
  3077. if (ret)
  3078. goto end;
  3079. ret = drm_atomic_commit(state);
  3080. if (ret)
  3081. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  3082. end:
  3083. if (state)
  3084. drm_atomic_state_put(state);
  3085. drm_modeset_drop_locks(&ctx);
  3086. drm_modeset_acquire_fini(&ctx);
  3087. }
  3088. void sde_kms_display_early_wakeup(struct drm_device *dev,
  3089. const int32_t connector_id)
  3090. {
  3091. struct drm_connector_list_iter conn_iter;
  3092. struct drm_connector *conn;
  3093. struct drm_encoder *drm_enc;
  3094. drm_connector_list_iter_begin(dev, &conn_iter);
  3095. drm_for_each_connector_iter(conn, &conn_iter) {
  3096. if (connector_id != DRM_MSM_WAKE_UP_ALL_DISPLAYS &&
  3097. connector_id != conn->base.id)
  3098. continue;
  3099. if (conn->state && conn->state->best_encoder)
  3100. drm_enc = conn->state->best_encoder;
  3101. else
  3102. drm_enc = conn->encoder;
  3103. if (drm_enc)
  3104. sde_encoder_early_wakeup(drm_enc);
  3105. }
  3106. drm_connector_list_iter_end(&conn_iter);
  3107. }
  3108. static void _sde_kms_pm_suspend_idle_helper(struct sde_kms *sde_kms,
  3109. struct device *dev)
  3110. {
  3111. int i, ret, crtc_id = 0;
  3112. struct drm_device *ddev = dev_get_drvdata(dev);
  3113. struct drm_connector *conn;
  3114. struct drm_connector_list_iter conn_iter;
  3115. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  3116. drm_connector_list_iter_begin(ddev, &conn_iter);
  3117. drm_for_each_connector_iter(conn, &conn_iter) {
  3118. uint64_t lp;
  3119. lp = sde_connector_get_lp(conn);
  3120. if (lp != SDE_MODE_DPMS_LP2)
  3121. continue;
  3122. if (sde_encoder_in_clone_mode(conn->encoder))
  3123. continue;
  3124. crtc_id = drm_crtc_index(conn->state->crtc);
  3125. if (priv->disp_thread[crtc_id].thread)
  3126. kthread_flush_worker(
  3127. &priv->disp_thread[crtc_id].worker);
  3128. ret = sde_encoder_wait_for_event(conn->encoder,
  3129. MSM_ENC_TX_COMPLETE);
  3130. if (ret && ret != -EWOULDBLOCK) {
  3131. SDE_ERROR(
  3132. "[conn: %d] wait for commit done returned %d\n",
  3133. conn->base.id, ret);
  3134. } else if (!ret) {
  3135. if (priv->event_thread[crtc_id].thread)
  3136. kthread_flush_worker(
  3137. &priv->event_thread[crtc_id].worker);
  3138. sde_encoder_idle_request(conn->encoder);
  3139. }
  3140. }
  3141. drm_connector_list_iter_end(&conn_iter);
  3142. for (i = 0; i < priv->num_crtcs; i++) {
  3143. if (priv->disp_thread[i].thread)
  3144. kthread_flush_worker(
  3145. &priv->disp_thread[i].worker);
  3146. if (priv->event_thread[i].thread)
  3147. kthread_flush_worker(
  3148. &priv->event_thread[i].worker);
  3149. }
  3150. kthread_flush_worker(&priv->pp_event_worker);
  3151. }
  3152. struct msm_display_mode *sde_kms_get_msm_mode(struct drm_connector_state *conn_state)
  3153. {
  3154. struct sde_connector_state *sde_conn_state;
  3155. if (!conn_state)
  3156. return NULL;
  3157. sde_conn_state = to_sde_connector_state(conn_state);
  3158. return &sde_conn_state->msm_mode;
  3159. }
  3160. static int sde_kms_pm_suspend(struct device *dev)
  3161. {
  3162. struct drm_device *ddev;
  3163. struct drm_modeset_acquire_ctx ctx;
  3164. struct drm_connector *conn;
  3165. struct drm_encoder *enc;
  3166. struct drm_connector_list_iter conn_iter;
  3167. struct drm_atomic_state *state = NULL;
  3168. struct sde_kms *sde_kms;
  3169. int ret = 0, num_crtcs = 0;
  3170. if (!dev)
  3171. return -EINVAL;
  3172. ddev = dev_get_drvdata(dev);
  3173. if (!ddev || !ddev_to_msm_kms(ddev))
  3174. return -EINVAL;
  3175. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  3176. SDE_EVT32(0);
  3177. /* disable hot-plug polling */
  3178. drm_kms_helper_poll_disable(ddev);
  3179. /* if a display stuck in CS trigger a null commit to complete handoff */
  3180. drm_for_each_encoder(enc, ddev) {
  3181. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  3182. _sde_kms_null_commit(ddev, enc);
  3183. }
  3184. /* acquire modeset lock(s) */
  3185. drm_modeset_acquire_init(&ctx, 0);
  3186. retry:
  3187. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  3188. if (ret)
  3189. goto unlock;
  3190. /* save current state for resume */
  3191. if (sde_kms->suspend_state)
  3192. drm_atomic_state_put(sde_kms->suspend_state);
  3193. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  3194. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  3195. ret = PTR_ERR(sde_kms->suspend_state);
  3196. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  3197. sde_kms->suspend_state = NULL;
  3198. goto unlock;
  3199. }
  3200. /* create atomic state to disable all CRTCs */
  3201. state = drm_atomic_state_alloc(ddev);
  3202. if (!state) {
  3203. ret = -ENOMEM;
  3204. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  3205. goto unlock;
  3206. }
  3207. state->acquire_ctx = &ctx;
  3208. drm_connector_list_iter_begin(ddev, &conn_iter);
  3209. drm_for_each_connector_iter(conn, &conn_iter) {
  3210. struct drm_crtc_state *crtc_state;
  3211. uint64_t lp;
  3212. if (!conn->state || !conn->state->crtc ||
  3213. conn->dpms != DRM_MODE_DPMS_ON ||
  3214. sde_encoder_in_clone_mode(conn->encoder))
  3215. continue;
  3216. lp = sde_connector_get_lp(conn);
  3217. if (lp == SDE_MODE_DPMS_LP1) {
  3218. /* transition LP1->LP2 on pm suspend */
  3219. ret = sde_connector_set_property_for_commit(conn, state,
  3220. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  3221. if (ret) {
  3222. DRM_ERROR("failed to set lp2 for conn %d\n",
  3223. conn->base.id);
  3224. drm_connector_list_iter_end(&conn_iter);
  3225. goto unlock;
  3226. }
  3227. }
  3228. if (lp != SDE_MODE_DPMS_LP2) {
  3229. /* force CRTC to be inactive */
  3230. crtc_state = drm_atomic_get_crtc_state(state,
  3231. conn->state->crtc);
  3232. if (IS_ERR_OR_NULL(crtc_state)) {
  3233. DRM_ERROR("failed to get crtc %d state\n",
  3234. conn->state->crtc->base.id);
  3235. drm_connector_list_iter_end(&conn_iter);
  3236. goto unlock;
  3237. }
  3238. if (lp != SDE_MODE_DPMS_LP1)
  3239. crtc_state->active = false;
  3240. ++num_crtcs;
  3241. }
  3242. }
  3243. drm_connector_list_iter_end(&conn_iter);
  3244. /* check for nothing to do */
  3245. if (num_crtcs == 0) {
  3246. DRM_DEBUG("all crtcs are already in the off state\n");
  3247. sde_kms->suspend_block = true;
  3248. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  3249. goto unlock;
  3250. }
  3251. /* commit the "disable all" state */
  3252. ret = drm_atomic_commit(state);
  3253. if (ret < 0) {
  3254. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  3255. goto unlock;
  3256. }
  3257. sde_kms->suspend_block = true;
  3258. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  3259. unlock:
  3260. if (state) {
  3261. drm_atomic_state_put(state);
  3262. state = NULL;
  3263. }
  3264. if (ret == -EDEADLK) {
  3265. drm_modeset_backoff(&ctx);
  3266. goto retry;
  3267. }
  3268. drm_modeset_drop_locks(&ctx);
  3269. drm_modeset_acquire_fini(&ctx);
  3270. /*
  3271. * pm runtime driver avoids multiple runtime_suspend API call by
  3272. * checking runtime_status. However, this call helps when there is a
  3273. * race condition between pm_suspend call and doze_suspend/power_off
  3274. * commit. It removes the extra vote from suspend and adds it back
  3275. * later to allow power collapse during pm_suspend call
  3276. */
  3277. pm_runtime_put_sync(dev);
  3278. pm_runtime_get_noresume(dev);
  3279. /* dump clock state before entering suspend */
  3280. if (sde_kms->pm_suspend_clk_dump)
  3281. _sde_kms_dump_clks_state(sde_kms);
  3282. return ret;
  3283. }
  3284. static int sde_kms_pm_resume(struct device *dev)
  3285. {
  3286. struct drm_device *ddev;
  3287. struct sde_kms *sde_kms;
  3288. struct drm_modeset_acquire_ctx ctx;
  3289. int ret, i;
  3290. if (!dev)
  3291. return -EINVAL;
  3292. ddev = dev_get_drvdata(dev);
  3293. if (!ddev || !ddev_to_msm_kms(ddev))
  3294. return -EINVAL;
  3295. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  3296. SDE_EVT32(sde_kms->suspend_state != NULL);
  3297. drm_mode_config_reset(ddev);
  3298. drm_modeset_acquire_init(&ctx, 0);
  3299. retry:
  3300. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  3301. if (ret == -EDEADLK) {
  3302. drm_modeset_backoff(&ctx);
  3303. goto retry;
  3304. } else if (WARN_ON(ret)) {
  3305. goto end;
  3306. }
  3307. sde_kms->suspend_block = false;
  3308. if (sde_kms->suspend_state) {
  3309. sde_kms->suspend_state->acquire_ctx = &ctx;
  3310. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  3311. ret = drm_atomic_helper_commit_duplicated_state(
  3312. sde_kms->suspend_state, &ctx);
  3313. if (ret != -EDEADLK)
  3314. break;
  3315. drm_modeset_backoff(&ctx);
  3316. }
  3317. if (ret < 0)
  3318. DRM_ERROR("failed to restore state, %d\n", ret);
  3319. drm_atomic_state_put(sde_kms->suspend_state);
  3320. sde_kms->suspend_state = NULL;
  3321. }
  3322. end:
  3323. drm_modeset_drop_locks(&ctx);
  3324. drm_modeset_acquire_fini(&ctx);
  3325. /* enable hot-plug polling */
  3326. drm_kms_helper_poll_enable(ddev);
  3327. return 0;
  3328. }
  3329. static const struct msm_kms_funcs kms_funcs = {
  3330. .hw_init = sde_kms_hw_init,
  3331. .postinit = sde_kms_postinit,
  3332. .irq_preinstall = sde_irq_preinstall,
  3333. .irq_postinstall = sde_irq_postinstall,
  3334. .irq_uninstall = sde_irq_uninstall,
  3335. .irq = sde_irq,
  3336. .preclose = sde_kms_preclose,
  3337. .lastclose = sde_kms_lastclose,
  3338. .prepare_fence = sde_kms_prepare_fence,
  3339. .prepare_commit = sde_kms_prepare_commit,
  3340. .commit = sde_kms_commit,
  3341. .complete_commit = sde_kms_complete_commit,
  3342. .get_msm_mode = sde_kms_get_msm_mode,
  3343. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  3344. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  3345. .check_modified_format = sde_format_check_modified_format,
  3346. .atomic_check = sde_kms_atomic_check,
  3347. .get_format = sde_get_msm_format,
  3348. .round_pixclk = sde_kms_round_pixclk,
  3349. .display_early_wakeup = sde_kms_display_early_wakeup,
  3350. .pm_suspend = sde_kms_pm_suspend,
  3351. .pm_resume = sde_kms_pm_resume,
  3352. .destroy = sde_kms_destroy,
  3353. .debugfs_destroy = sde_kms_debugfs_destroy,
  3354. .cont_splash_config = sde_kms_cont_splash_config,
  3355. .register_events = _sde_kms_register_events,
  3356. .get_address_space = _sde_kms_get_address_space,
  3357. .get_address_space_device = _sde_kms_get_address_space_device,
  3358. .postopen = _sde_kms_post_open,
  3359. .check_for_splash = sde_kms_check_for_splash,
  3360. .get_mixer_count = sde_kms_get_mixer_count,
  3361. .get_dsc_count = sde_kms_get_dsc_count,
  3362. };
  3363. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  3364. {
  3365. int i;
  3366. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  3367. if (!sde_kms->aspace[i])
  3368. continue;
  3369. msm_gem_address_space_put(sde_kms->aspace[i]);
  3370. sde_kms->aspace[i] = NULL;
  3371. }
  3372. return 0;
  3373. }
  3374. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  3375. {
  3376. struct msm_mmu *mmu;
  3377. int i, ret;
  3378. #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0))
  3379. int early_map = 0;
  3380. #endif
  3381. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev)
  3382. return -EINVAL;
  3383. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  3384. struct msm_gem_address_space *aspace;
  3385. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  3386. if (IS_ERR(mmu)) {
  3387. ret = PTR_ERR(mmu);
  3388. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  3389. i, ret);
  3390. continue;
  3391. }
  3392. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  3393. mmu, "sde");
  3394. if (IS_ERR(aspace)) {
  3395. ret = PTR_ERR(aspace);
  3396. mmu->funcs->destroy(mmu);
  3397. goto fail;
  3398. }
  3399. sde_kms->aspace[i] = aspace;
  3400. aspace->domain_attached = true;
  3401. /* Mapping splash memory block */
  3402. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  3403. sde_kms->splash_data.num_splash_regions) {
  3404. ret = _sde_kms_map_all_splash_regions(sde_kms);
  3405. if (ret) {
  3406. SDE_ERROR("failed to map ret:%d\n", ret);
  3407. goto enable_trans_fail;
  3408. }
  3409. }
  3410. /*
  3411. * disable early-map which would have been enabled during
  3412. * bootup by smmu through the device-tree hint for cont-spash
  3413. */
  3414. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3415. ret = mmu->funcs->enable_smmu_translations(mmu);
  3416. if (ret) {
  3417. SDE_ERROR("failed to enable_s1_translations ret:%d\n", ret);
  3418. goto enable_trans_fail;
  3419. }
  3420. #else
  3421. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  3422. &early_map);
  3423. if (ret) {
  3424. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  3425. ret, early_map);
  3426. goto enable_trans_fail;
  3427. }
  3428. #endif
  3429. }
  3430. sde_kms->base.aspace = sde_kms->aspace[0];
  3431. return 0;
  3432. enable_trans_fail:
  3433. _sde_kms_unmap_all_splash_regions(sde_kms);
  3434. fail:
  3435. _sde_kms_mmu_destroy(sde_kms);
  3436. return ret;
  3437. }
  3438. static void sde_kms_init_rot_sid_hw(struct sde_kms *sde_kms)
  3439. {
  3440. if (!sde_kms || !sde_kms->hw_sid || sde_in_trusted_vm(sde_kms))
  3441. return;
  3442. sde_hw_set_rotator_sid(sde_kms->hw_sid);
  3443. }
  3444. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  3445. {
  3446. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  3447. return;
  3448. if (sde_kms->hw_mdp->ops.reset_ubwc)
  3449. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  3450. sde_kms->catalog);
  3451. }
  3452. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  3453. {
  3454. struct sde_vbif_set_qos_params qos_params;
  3455. struct sde_mdss_cfg *catalog;
  3456. if (!sde_kms->catalog)
  3457. return;
  3458. catalog = sde_kms->catalog;
  3459. memset(&qos_params, 0, sizeof(qos_params));
  3460. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  3461. qos_params.xin_id = catalog->dma_cfg.xin_id;
  3462. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  3463. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  3464. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  3465. }
  3466. static int _sde_kms_active_override(struct sde_kms *sde_kms, bool enable)
  3467. {
  3468. struct sde_hw_uidle *uidle;
  3469. if (!sde_kms) {
  3470. SDE_ERROR("invalid kms\n");
  3471. return -EINVAL;
  3472. }
  3473. uidle = sde_kms->hw_uidle;
  3474. if (uidle && uidle->ops.active_override_enable)
  3475. uidle->ops.active_override_enable(uidle, enable);
  3476. return 0;
  3477. }
  3478. static void _sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
  3479. {
  3480. struct device *cpu_dev;
  3481. int cpu = 0;
  3482. u32 cpu_irq_latency = sde_kms->catalog->perf.cpu_irq_latency;
  3483. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3484. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3485. return;
  3486. }
  3487. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3488. cpu_dev = get_cpu_device(cpu);
  3489. if (!cpu_dev) {
  3490. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3491. cpu);
  3492. continue;
  3493. }
  3494. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3495. dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
  3496. cpu_irq_latency);
  3497. else
  3498. dev_pm_qos_add_request(cpu_dev,
  3499. &sde_kms->pm_qos_irq_req[cpu],
  3500. DEV_PM_QOS_RESUME_LATENCY,
  3501. cpu_irq_latency);
  3502. }
  3503. }
  3504. static void _sde_kms_remove_pm_qos_irq_request(struct sde_kms *sde_kms)
  3505. {
  3506. struct device *cpu_dev;
  3507. int cpu = 0;
  3508. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3509. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3510. return;
  3511. }
  3512. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3513. cpu_dev = get_cpu_device(cpu);
  3514. if (!cpu_dev) {
  3515. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3516. cpu);
  3517. continue;
  3518. }
  3519. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3520. dev_pm_qos_remove_request(
  3521. &sde_kms->pm_qos_irq_req[cpu]);
  3522. }
  3523. }
  3524. void sde_kms_cpu_vote_for_irq(struct sde_kms *sde_kms, bool enable)
  3525. {
  3526. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  3527. mutex_lock(&priv->phandle.phandle_lock);
  3528. if (enable && atomic_inc_return(&sde_kms->irq_vote_count) == 1)
  3529. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3530. else if (!enable && atomic_dec_return(&sde_kms->irq_vote_count) == 0)
  3531. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3532. mutex_unlock(&priv->phandle.phandle_lock);
  3533. }
  3534. static void sde_kms_irq_affinity_notify(
  3535. struct irq_affinity_notify *affinity_notify,
  3536. const cpumask_t *mask)
  3537. {
  3538. struct msm_drm_private *priv;
  3539. struct sde_kms *sde_kms = container_of(affinity_notify,
  3540. struct sde_kms, affinity_notify);
  3541. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  3542. return;
  3543. priv = sde_kms->dev->dev_private;
  3544. mutex_lock(&priv->phandle.phandle_lock);
  3545. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3546. // save irq cpu mask
  3547. sde_kms->irq_cpu_mask = *mask;
  3548. // request vote with updated irq cpu mask
  3549. if (atomic_read(&sde_kms->irq_vote_count))
  3550. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3551. mutex_unlock(&priv->phandle.phandle_lock);
  3552. }
  3553. static void sde_kms_irq_affinity_release(struct kref *ref) {}
  3554. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  3555. {
  3556. struct sde_kms *sde_kms = usr;
  3557. struct msm_kms *msm_kms;
  3558. msm_kms = &sde_kms->base;
  3559. if (!sde_kms)
  3560. return;
  3561. SDE_DEBUG("event_type:%d\n", event_type);
  3562. SDE_EVT32_VERBOSE(event_type);
  3563. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  3564. sde_irq_update(msm_kms, true);
  3565. sde_kms->first_kickoff = true;
  3566. /**
  3567. * Rotator sid needs to be programmed since uefi doesn't
  3568. * configure it during continuous splash
  3569. */
  3570. sde_kms_init_rot_sid_hw(sde_kms);
  3571. if (sde_kms->splash_data.num_splash_displays ||
  3572. sde_in_trusted_vm(sde_kms))
  3573. return;
  3574. sde_vbif_init_memtypes(sde_kms);
  3575. sde_kms_init_shared_hw(sde_kms);
  3576. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  3577. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  3578. sde_irq_update(msm_kms, false);
  3579. sde_kms->first_kickoff = false;
  3580. if (sde_in_trusted_vm(sde_kms))
  3581. return;
  3582. _sde_kms_active_override(sde_kms, true);
  3583. if (!is_sde_rsc_available(SDE_RSC_INDEX))
  3584. sde_vbif_axi_halt_request(sde_kms);
  3585. }
  3586. }
  3587. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  3588. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  3589. {
  3590. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3591. int rc = -EINVAL;
  3592. SDE_DEBUG("\n");
  3593. rc = pm_runtime_resume_and_get(sde_kms->dev->dev);
  3594. rc = (rc > 0) ? 0 : rc;
  3595. SDE_EVT32(rc, genpd->device_count);
  3596. return rc;
  3597. }
  3598. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  3599. {
  3600. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3601. SDE_DEBUG("\n");
  3602. pm_runtime_put_sync(sde_kms->dev->dev);
  3603. SDE_EVT32(genpd->device_count);
  3604. return 0;
  3605. }
  3606. static int _sde_kms_get_demura_plane_data(struct sde_splash_data *data)
  3607. {
  3608. int i = 0;
  3609. int ret = 0;
  3610. int count = 0;
  3611. struct device_node *parent, *node;
  3612. struct resource r;
  3613. char node_name[DEMURA_REGION_NAME_MAX];
  3614. struct sde_splash_mem *mem;
  3615. struct sde_splash_display *splash_display;
  3616. if (!data->num_splash_displays) {
  3617. SDE_DEBUG("no splash displays. skipping\n");
  3618. return 0;
  3619. }
  3620. /**
  3621. * It is expected that each active demura block will have
  3622. * its own memory region defined.
  3623. */
  3624. parent = of_find_node_by_path("/reserved-memory");
  3625. for (i = 0; i < data->num_splash_displays; i++) {
  3626. splash_display = &data->splash_display[i];
  3627. snprintf(&node_name[0], DEMURA_REGION_NAME_MAX,
  3628. "demura_region_%d", i);
  3629. splash_display->demura = NULL;
  3630. node = of_find_node_by_name(parent, node_name);
  3631. if (!node) {
  3632. SDE_DEBUG("no Demura node %s! disp count: %d\n",
  3633. node_name, data->num_splash_displays);
  3634. continue;
  3635. } else if (of_address_to_resource(node, 0, &r)) {
  3636. SDE_ERROR("invalid data for:%s\n", node_name);
  3637. ret = -EINVAL;
  3638. break;
  3639. }
  3640. mem = &data->demura_mem[i];
  3641. mem->splash_buf_base = (unsigned long)r.start;
  3642. mem->splash_buf_size = (r.end - r.start) + 1;
  3643. if (!mem->splash_buf_base && !mem->splash_buf_size) {
  3644. SDE_DEBUG("dummy splash mem for disp %d. Skipping\n",
  3645. (i+1));
  3646. continue;
  3647. } else if (!mem->splash_buf_base || !mem->splash_buf_size) {
  3648. SDE_ERROR("mem for disp %d invalid: add:%lx size:%lx\n",
  3649. (i+1), mem->splash_buf_base,
  3650. mem->splash_buf_size);
  3651. continue;
  3652. }
  3653. mem->ref_cnt = 0;
  3654. splash_display->demura = mem;
  3655. count++;
  3656. SDE_DEBUG("demura mem for disp:%d add:%lx size:%x\n", (i + 1),
  3657. mem->splash_buf_base,
  3658. mem->splash_buf_size);
  3659. }
  3660. if (!ret && !count)
  3661. SDE_DEBUG("no demura regions for cont. splash found!\n");
  3662. return ret;
  3663. }
  3664. static int _sde_kms_get_splash_data(struct sde_splash_data *data)
  3665. {
  3666. int i = 0;
  3667. int ret = 0;
  3668. struct device_node *parent, *node, *node1;
  3669. struct resource r, r1;
  3670. const char *node_name = "splash_region";
  3671. struct sde_splash_mem *mem;
  3672. bool share_splash_mem = false;
  3673. int num_displays, num_regions;
  3674. struct sde_splash_display *splash_display;
  3675. if (!data)
  3676. return -EINVAL;
  3677. memset(data, 0, sizeof(*data));
  3678. parent = of_find_node_by_path("/reserved-memory");
  3679. if (!parent) {
  3680. SDE_ERROR("failed to find reserved-memory node\n");
  3681. return -EINVAL;
  3682. }
  3683. node = of_find_node_by_name(parent, node_name);
  3684. if (!node) {
  3685. SDE_DEBUG("failed to find node %s\n", node_name);
  3686. return -EINVAL;
  3687. }
  3688. node1 = of_find_node_by_name(NULL, "disp_rdump_region");
  3689. if (!node1)
  3690. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  3691. /**
  3692. * Support sharing a single splash memory for all the built in displays
  3693. * and also independent splash region per displays. Incase of
  3694. * independent splash region for each connected display, dtsi node of
  3695. * cont_splash_region should be collection of all memory regions
  3696. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  3697. */
  3698. num_displays = dsi_display_get_num_of_displays();
  3699. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  3700. data->num_splash_displays = num_displays;
  3701. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  3702. if (num_displays > num_regions) {
  3703. share_splash_mem = true;
  3704. pr_info(":%d displays share same splash buf\n", num_displays);
  3705. }
  3706. for (i = 0; i < num_displays; i++) {
  3707. splash_display = &data->splash_display[i];
  3708. if (!i || !share_splash_mem) {
  3709. if (of_address_to_resource(node, i, &r)) {
  3710. SDE_ERROR("invalid data for:%s\n", node_name);
  3711. return -EINVAL;
  3712. }
  3713. mem = &data->splash_mem[i];
  3714. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  3715. SDE_DEBUG("failed to find ramdump memory\n");
  3716. mem->ramdump_base = 0;
  3717. mem->ramdump_size = 0;
  3718. } else {
  3719. mem->ramdump_base = (unsigned long)r1.start;
  3720. mem->ramdump_size = (r1.end - r1.start) + 1;
  3721. }
  3722. mem->splash_buf_base = (unsigned long)r.start;
  3723. mem->splash_buf_size = (r.end - r.start) + 1;
  3724. mem->ref_cnt = 0;
  3725. splash_display->splash = mem;
  3726. data->num_splash_regions++;
  3727. } else {
  3728. data->splash_display[i].splash = &data->splash_mem[0];
  3729. }
  3730. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  3731. splash_display->splash->splash_buf_base,
  3732. splash_display->splash->splash_buf_size);
  3733. }
  3734. data->type = SDE_SPLASH_HANDOFF;
  3735. ret = _sde_kms_get_demura_plane_data(data);
  3736. return ret;
  3737. }
  3738. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  3739. struct platform_device *platformdev)
  3740. {
  3741. int rc = -EINVAL;
  3742. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  3743. if (IS_ERR(sde_kms->mmio)) {
  3744. rc = PTR_ERR(sde_kms->mmio);
  3745. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  3746. sde_kms->mmio = NULL;
  3747. goto error;
  3748. }
  3749. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  3750. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  3751. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  3752. sde_kms->mmio_len,
  3753. msm_get_phys_addr(platformdev, "mdp_phys"),
  3754. SDE_DBG_SDE);
  3755. if (rc)
  3756. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  3757. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys", "vbif_phys");
  3758. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  3759. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  3760. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  3761. sde_kms->vbif[VBIF_RT] = NULL;
  3762. goto error;
  3763. }
  3764. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev, "vbif_phys");
  3765. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  3766. sde_kms->vbif_len[VBIF_RT],
  3767. msm_get_phys_addr(platformdev, "vbif_phys"),
  3768. SDE_DBG_VBIF_RT);
  3769. if (rc)
  3770. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  3771. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys", "vbif_nrt_phys");
  3772. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  3773. sde_kms->vbif[VBIF_NRT] = NULL;
  3774. SDE_DEBUG("VBIF NRT is not defined");
  3775. } else {
  3776. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev, "vbif_nrt_phys");
  3777. }
  3778. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys", "regdma_phys");
  3779. if (IS_ERR(sde_kms->reg_dma)) {
  3780. sde_kms->reg_dma = NULL;
  3781. SDE_DEBUG("REG_DMA is not defined");
  3782. } else {
  3783. unsigned long mdp_addr = msm_get_phys_addr(platformdev, "mdp_phys");
  3784. sde_kms->reg_dma_len = msm_iomap_size(platformdev, "regdma_phys");
  3785. sde_kms->reg_dma_off = msm_get_phys_addr(platformdev, "regdma_phys") - mdp_addr;
  3786. rc = sde_dbg_reg_register_base("reg_dma", sde_kms->reg_dma,
  3787. sde_kms->reg_dma_len,
  3788. msm_get_phys_addr(platformdev, "regdma_phys"),
  3789. SDE_DBG_LUTDMA);
  3790. if (rc)
  3791. SDE_ERROR("dbg base register reg_dma failed: %d\n", rc);
  3792. }
  3793. sde_kms->sid = msm_ioremap(platformdev, "sid_phys", "sid_phys");
  3794. if (IS_ERR(sde_kms->sid)) {
  3795. SDE_DEBUG("sid register is not defined: %d\n", rc);
  3796. sde_kms->sid = NULL;
  3797. } else {
  3798. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  3799. rc = sde_dbg_reg_register_base("sid", sde_kms->sid,
  3800. sde_kms->sid_len,
  3801. msm_get_phys_addr(platformdev, "sid_phys"),
  3802. SDE_DBG_SID);
  3803. if (rc)
  3804. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  3805. }
  3806. error:
  3807. return rc;
  3808. }
  3809. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  3810. struct sde_kms *sde_kms)
  3811. {
  3812. int rc = 0;
  3813. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  3814. sde_kms->genpd.name = dev->unique;
  3815. sde_kms->genpd.power_off = sde_kms_pd_disable;
  3816. sde_kms->genpd.power_on = sde_kms_pd_enable;
  3817. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  3818. if (rc < 0) {
  3819. SDE_ERROR("failed to init genpd provider %s: %d\n",
  3820. sde_kms->genpd.name, rc);
  3821. return rc;
  3822. }
  3823. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  3824. &sde_kms->genpd);
  3825. if (rc < 0) {
  3826. SDE_ERROR("failed to add genpd provider %s: %d\n",
  3827. sde_kms->genpd.name, rc);
  3828. pm_genpd_remove(&sde_kms->genpd);
  3829. return rc;
  3830. }
  3831. sde_kms->genpd_init = true;
  3832. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  3833. }
  3834. return rc;
  3835. }
  3836. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  3837. struct drm_device *dev,
  3838. struct msm_drm_private *priv)
  3839. {
  3840. struct sde_rm *rm = NULL;
  3841. int i, rc = -EINVAL;
  3842. sde_kms->catalog = sde_hw_catalog_init(dev);
  3843. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  3844. rc = PTR_ERR(sde_kms->catalog);
  3845. if (!sde_kms->catalog)
  3846. rc = -EINVAL;
  3847. SDE_ERROR("catalog init failed: %d\n", rc);
  3848. sde_kms->catalog = NULL;
  3849. goto power_error;
  3850. }
  3851. sde_kms->core_rev = sde_kms->catalog->hw_rev;
  3852. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  3853. /* initialize power domain if defined */
  3854. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  3855. if (rc) {
  3856. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  3857. goto genpd_err;
  3858. }
  3859. rc = _sde_kms_mmu_init(sde_kms);
  3860. if (rc) {
  3861. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  3862. goto power_error;
  3863. }
  3864. /* Initialize reg dma block which is a singleton */
  3865. sde_kms->catalog->dma_cfg.base_off = sde_kms->reg_dma_off;
  3866. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  3867. sde_kms->dev);
  3868. if (rc) {
  3869. SDE_ERROR("failed: reg dma init failed\n");
  3870. goto power_error;
  3871. }
  3872. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  3873. rm = &sde_kms->rm;
  3874. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  3875. sde_kms->dev);
  3876. if (rc) {
  3877. SDE_ERROR("rm init failed: %d\n", rc);
  3878. goto power_error;
  3879. }
  3880. sde_kms->rm_init = true;
  3881. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  3882. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  3883. rc = PTR_ERR(sde_kms->hw_intr);
  3884. SDE_ERROR("hw_intr init failed: %d\n", rc);
  3885. sde_kms->hw_intr = NULL;
  3886. goto hw_intr_init_err;
  3887. }
  3888. /*
  3889. * Attempt continuous splash handoff only if reserved
  3890. * splash memory is found & release resources on any error
  3891. * in finding display hw config in splash
  3892. */
  3893. if (sde_kms->splash_data.num_splash_regions) {
  3894. struct sde_splash_display *display;
  3895. int ret, display_count =
  3896. sde_kms->splash_data.num_splash_displays;
  3897. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3898. &sde_kms->splash_data, sde_kms->catalog);
  3899. for (i = 0; i < display_count; i++) {
  3900. display = &sde_kms->splash_data.splash_display[i];
  3901. /*
  3902. * free splash region on resource init failure and
  3903. * cont-splash disabled case
  3904. */
  3905. if (!display->cont_splash_enabled || ret)
  3906. _sde_kms_free_splash_display_data(
  3907. sde_kms, display);
  3908. }
  3909. }
  3910. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  3911. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  3912. rc = PTR_ERR(sde_kms->hw_mdp);
  3913. if (!sde_kms->hw_mdp)
  3914. rc = -EINVAL;
  3915. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  3916. sde_kms->hw_mdp = NULL;
  3917. goto power_error;
  3918. }
  3919. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  3920. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  3921. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  3922. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  3923. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  3924. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  3925. if (!sde_kms->hw_vbif[vbif_idx])
  3926. rc = -EINVAL;
  3927. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  3928. sde_kms->hw_vbif[vbif_idx] = NULL;
  3929. goto power_error;
  3930. }
  3931. }
  3932. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  3933. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  3934. sde_kms->mmio_len, sde_kms->catalog);
  3935. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  3936. rc = PTR_ERR(sde_kms->hw_uidle);
  3937. if (!sde_kms->hw_uidle)
  3938. rc = -EINVAL;
  3939. /* uidle is optional, so do not make it a fatal error */
  3940. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  3941. sde_kms->hw_uidle = NULL;
  3942. rc = 0;
  3943. }
  3944. } else {
  3945. sde_kms->hw_uidle = NULL;
  3946. }
  3947. if (sde_kms->sid) {
  3948. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  3949. sde_kms->sid_len, sde_kms->catalog);
  3950. if (IS_ERR_OR_NULL(sde_kms->hw_sid)) {
  3951. rc = PTR_ERR(sde_kms->hw_sid);
  3952. SDE_ERROR("failed to init sid %d\n", rc);
  3953. sde_kms->hw_sid = NULL;
  3954. goto power_error;
  3955. }
  3956. }
  3957. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  3958. &priv->phandle, "core_clk");
  3959. if (rc) {
  3960. SDE_ERROR("failed to init perf %d\n", rc);
  3961. goto perf_err;
  3962. }
  3963. /*
  3964. * set the disable_immediate flag when driver supports the precise vsync
  3965. * timestamp as the DRM hooks for vblank timestamp/counters would be set
  3966. * based on the feature
  3967. */
  3968. if (test_bit(SDE_FEATURE_HW_VSYNC_TS, sde_kms->catalog->features))
  3969. dev->vblank_disable_immediate = true;
  3970. /*
  3971. * _sde_kms_drm_obj_init should create the DRM related objects
  3972. * i.e. CRTCs, planes, encoders, connectors and so forth
  3973. */
  3974. rc = _sde_kms_drm_obj_init(sde_kms);
  3975. if (rc) {
  3976. SDE_ERROR("modeset init failed: %d\n", rc);
  3977. goto drm_obj_init_err;
  3978. }
  3979. return 0;
  3980. genpd_err:
  3981. drm_obj_init_err:
  3982. sde_core_perf_destroy(&sde_kms->perf);
  3983. hw_intr_init_err:
  3984. perf_err:
  3985. power_error:
  3986. return rc;
  3987. }
  3988. int _sde_kms_get_tvm_inclusion_mem(struct sde_mdss_cfg *catalog, struct list_head *mem_list)
  3989. {
  3990. struct list_head temp_head;
  3991. struct msm_io_mem_entry *io_mem;
  3992. int rc, i = 0;
  3993. INIT_LIST_HEAD(&temp_head);
  3994. for (i = 0; i < catalog->tvm_reg_count; i++) {
  3995. struct resource *res = &catalog->tvm_reg[i];
  3996. io_mem = kzalloc(sizeof(struct msm_io_mem_entry), GFP_KERNEL);
  3997. if (!io_mem) {
  3998. rc = -ENOMEM;
  3999. goto parse_fail;
  4000. }
  4001. io_mem->base = res->start;
  4002. io_mem->size = resource_size(res);
  4003. list_add(&io_mem->list, &temp_head);
  4004. }
  4005. list_splice(&temp_head, mem_list);
  4006. return 0;
  4007. parse_fail:
  4008. msm_dss_clean_io_mem(&temp_head);
  4009. return rc;
  4010. }
  4011. #ifdef CONFIG_DRM_SDE_VM
  4012. int sde_kms_get_io_resources(struct sde_kms *sde_kms, struct msm_io_res *io_res)
  4013. {
  4014. struct platform_device *pdev = to_platform_device(sde_kms->dev->dev);
  4015. int rc = 0;
  4016. rc = msm_dss_get_io_mem(pdev, &io_res->mem);
  4017. if (rc) {
  4018. SDE_ERROR("failed to get io mem for KMS, rc = %d\n", rc);
  4019. return rc;
  4020. }
  4021. rc = msm_dss_get_pmic_io_mem(pdev, &io_res->mem);
  4022. if (rc) {
  4023. SDE_ERROR("failed to get io mem for pmic, rc:%d\n", rc);
  4024. return rc;
  4025. }
  4026. rc = msm_dss_get_io_irq(pdev, &io_res->irq, GH_IRQ_LABEL_SDE);
  4027. if (rc) {
  4028. SDE_ERROR("failed to get io irq for KMS");
  4029. return rc;
  4030. }
  4031. rc = _sde_kms_get_tvm_inclusion_mem(sde_kms->catalog, &io_res->mem);
  4032. if (rc) {
  4033. SDE_ERROR("failed to get tvm inclusion mem ranges");
  4034. return rc;
  4035. }
  4036. return rc;
  4037. }
  4038. #endif
  4039. static int sde_kms_hw_init(struct msm_kms *kms)
  4040. {
  4041. struct sde_kms *sde_kms;
  4042. struct drm_device *dev;
  4043. struct msm_drm_private *priv;
  4044. struct platform_device *platformdev;
  4045. int i, irq_num, rc = -EINVAL;
  4046. if (!kms) {
  4047. SDE_ERROR("invalid kms\n");
  4048. goto end;
  4049. }
  4050. sde_kms = to_sde_kms(kms);
  4051. dev = sde_kms->dev;
  4052. if (!dev || !dev->dev) {
  4053. SDE_ERROR("invalid device\n");
  4054. goto end;
  4055. }
  4056. platformdev = to_platform_device(dev->dev);
  4057. priv = dev->dev_private;
  4058. if (!priv) {
  4059. SDE_ERROR("invalid private data\n");
  4060. goto end;
  4061. }
  4062. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  4063. if (rc)
  4064. goto error;
  4065. rc = _sde_kms_get_splash_data(&sde_kms->splash_data);
  4066. if (rc)
  4067. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  4068. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  4069. if (rc)
  4070. goto error;
  4071. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  4072. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  4073. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  4074. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  4075. mutex_init(&sde_kms->secure_transition_lock);
  4076. atomic_set(&sde_kms->detach_sec_cb, 0);
  4077. atomic_set(&sde_kms->detach_all_cb, 0);
  4078. atomic_set(&sde_kms->irq_vote_count, 0);
  4079. /*
  4080. * Support format modifiers for compression etc.
  4081. */
  4082. dev->mode_config.allow_fb_modifiers = true;
  4083. /*
  4084. * Handle (re)initializations during power enable
  4085. */
  4086. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  4087. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  4088. SDE_POWER_EVENT_POST_ENABLE |
  4089. SDE_POWER_EVENT_PRE_DISABLE,
  4090. sde_kms_handle_power_event, sde_kms, "kms");
  4091. if (sde_kms->splash_data.num_splash_displays) {
  4092. SDE_DEBUG("Skipping MDP Resources disable\n");
  4093. } else {
  4094. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  4095. sde_power_data_bus_set_quota(&priv->phandle, i,
  4096. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  4097. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  4098. pm_runtime_put_sync(sde_kms->dev->dev);
  4099. }
  4100. sde_kms->affinity_notify.notify = sde_kms_irq_affinity_notify;
  4101. sde_kms->affinity_notify.release = sde_kms_irq_affinity_release;
  4102. irq_num = platform_get_irq(to_platform_device(sde_kms->dev->dev), 0);
  4103. SDE_DEBUG("Registering for notification of irq_num: %d\n", irq_num);
  4104. irq_set_affinity_notifier(irq_num, &sde_kms->affinity_notify);
  4105. if (sde_in_trusted_vm(sde_kms)) {
  4106. rc = sde_vm_trusted_init(sde_kms);
  4107. sde_dbg_set_hw_ownership_status(false);
  4108. } else {
  4109. rc = sde_vm_primary_init(sde_kms);
  4110. sde_dbg_set_hw_ownership_status(true);
  4111. }
  4112. if (rc) {
  4113. SDE_ERROR("failed to initialize VM ops, rc: %d\n", rc);
  4114. goto error;
  4115. }
  4116. return 0;
  4117. error:
  4118. _sde_kms_hw_destroy(sde_kms, platformdev);
  4119. end:
  4120. return rc;
  4121. }
  4122. struct msm_kms *sde_kms_init(struct drm_device *dev)
  4123. {
  4124. struct msm_drm_private *priv;
  4125. struct sde_kms *sde_kms;
  4126. if (!dev || !dev->dev_private) {
  4127. SDE_ERROR("drm device node invalid\n");
  4128. return ERR_PTR(-EINVAL);
  4129. }
  4130. priv = dev->dev_private;
  4131. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  4132. if (!sde_kms) {
  4133. SDE_ERROR("failed to allocate sde kms\n");
  4134. return ERR_PTR(-ENOMEM);
  4135. }
  4136. msm_kms_init(&sde_kms->base, &kms_funcs);
  4137. sde_kms->dev = dev;
  4138. return &sde_kms->base;
  4139. }
  4140. void sde_kms_vm_trusted_resource_deinit(struct sde_kms *sde_kms)
  4141. {
  4142. struct dsi_display *display;
  4143. struct sde_splash_display *handoff_display;
  4144. int i;
  4145. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  4146. handoff_display = &sde_kms->splash_data.splash_display[i];
  4147. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  4148. if (handoff_display->cont_splash_enabled)
  4149. _sde_kms_free_splash_display_data(sde_kms,
  4150. handoff_display);
  4151. dsi_display_set_active_state(display, false);
  4152. }
  4153. memset(&sde_kms->splash_data, 0, sizeof(struct sde_splash_data));
  4154. }
  4155. int sde_kms_vm_trusted_resource_init(struct sde_kms *sde_kms,
  4156. struct drm_atomic_state *state)
  4157. {
  4158. struct drm_device *dev;
  4159. struct msm_drm_private *priv;
  4160. struct sde_splash_display *handoff_display;
  4161. struct dsi_display *display;
  4162. int ret, i;
  4163. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  4164. SDE_ERROR("invalid params\n");
  4165. return -EINVAL;
  4166. }
  4167. dev = sde_kms->dev;
  4168. priv = dev->dev_private;
  4169. sde_kms->splash_data.type = SDE_VM_HANDOFF;
  4170. sde_kms->splash_data.num_splash_displays = sde_kms->dsi_display_count;
  4171. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  4172. &sde_kms->splash_data, sde_kms->catalog);
  4173. if (ret) {
  4174. SDE_ERROR("invalid cont splash init, ret:%d\n", ret);
  4175. return -EINVAL;
  4176. }
  4177. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  4178. handoff_display = &sde_kms->splash_data.splash_display[i];
  4179. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  4180. if (!handoff_display->cont_splash_enabled || ret)
  4181. _sde_kms_free_splash_display_data(sde_kms,
  4182. handoff_display);
  4183. else
  4184. dsi_display_set_active_state(display, true);
  4185. }
  4186. if (sde_kms->splash_data.num_splash_displays != 1) {
  4187. SDE_ERROR("no. of displays not supported:%d\n",
  4188. sde_kms->splash_data.num_splash_displays);
  4189. goto error;
  4190. }
  4191. ret = sde_kms_cont_splash_config(&sde_kms->base, state);
  4192. if (ret) {
  4193. SDE_ERROR("error in setting handoff configs\n");
  4194. goto error;
  4195. }
  4196. /**
  4197. * fill-in vote for the continuous splash hanodff path, which will be
  4198. * removed on the successful first commit.
  4199. */
  4200. ret = pm_runtime_resume_and_get(sde_kms->dev->dev);
  4201. if (ret < 0) {
  4202. SDE_ERROR("failed to enable power resource %d\n", ret);
  4203. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  4204. goto error;
  4205. }
  4206. return 0;
  4207. error:
  4208. return ret;
  4209. }
  4210. static int _sde_kms_register_events(struct msm_kms *kms,
  4211. struct drm_mode_object *obj, u32 event, bool en)
  4212. {
  4213. int ret = 0;
  4214. struct drm_crtc *crtc;
  4215. struct drm_connector *conn;
  4216. struct sde_kms *sde_kms;
  4217. if (!kms || !obj) {
  4218. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  4219. return -EINVAL;
  4220. }
  4221. sde_kms = to_sde_kms(kms);
  4222. sde_vm_lock(sde_kms);
  4223. if (!sde_vm_owns_hw(sde_kms)) {
  4224. sde_vm_unlock(sde_kms);
  4225. SDE_DEBUG("HW is owned by other VM\n");
  4226. return -EACCES;
  4227. }
  4228. /* check vm ownership, if event registration requires HW access */
  4229. switch (obj->type) {
  4230. case DRM_MODE_OBJECT_CRTC:
  4231. crtc = obj_to_crtc(obj);
  4232. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  4233. break;
  4234. case DRM_MODE_OBJECT_CONNECTOR:
  4235. conn = obj_to_connector(obj);
  4236. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  4237. en);
  4238. break;
  4239. }
  4240. sde_vm_unlock(sde_kms);
  4241. return ret;
  4242. }
  4243. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  4244. {
  4245. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  4246. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  4247. }
  4248. void sde_kms_add_data_to_minidump_va(struct sde_kms *sde_kms)
  4249. {
  4250. struct msm_drm_private *priv;
  4251. struct sde_crtc *sde_crtc;
  4252. struct sde_crtc_state *cstate;
  4253. struct sde_connector *sde_conn;
  4254. struct sde_connector_state *conn_state;
  4255. u32 i;
  4256. priv = sde_kms->dev->dev_private;
  4257. sde_mini_dump_add_va_region("sde_kms", sizeof(*sde_kms), sde_kms);
  4258. for (i = 0; i < priv->num_crtcs; i++) {
  4259. sde_crtc = to_sde_crtc(priv->crtcs[i]);
  4260. cstate = to_sde_crtc_state(priv->crtcs[i]->state);
  4261. sde_mini_dump_add_va_region("sde_crtc", sizeof(*sde_crtc), sde_crtc);
  4262. sde_mini_dump_add_va_region("crtc_state", sizeof(*cstate), cstate);
  4263. }
  4264. for (i = 0; i < priv->num_planes; i++)
  4265. sde_plane_add_data_to_minidump_va(priv->planes[i]);
  4266. for (i = 0; i < priv->num_encoders; i++)
  4267. sde_encoder_add_data_to_minidump_va(priv->encoders[i]);
  4268. for (i = 0; i < priv->num_connectors; i++) {
  4269. sde_conn = to_sde_connector(priv->connectors[i]);
  4270. conn_state = to_sde_connector_state(priv->connectors[i]->state);
  4271. sde_mini_dump_add_va_region("sde_conn", sizeof(*sde_conn), sde_conn);
  4272. sde_mini_dump_add_va_region("conn_state", sizeof(*conn_state), conn_state);
  4273. }
  4274. }