sde_hw_sspp.c 46 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #include "sde_hwio.h"
  7. #include "sde_hw_catalog.h"
  8. #include "sde_hw_lm.h"
  9. #include "sde_hw_sspp.h"
  10. #include "sde_hw_color_processing.h"
  11. #include "sde_dbg.h"
  12. #include "sde_kms.h"
  13. #include "sde_hw_reg_dma_v1_color_proc.h"
  14. #include "sde_hw_vbif.h"
  15. #define SDE_FETCH_CONFIG_RESET_VALUE 0x00000087
  16. /* SDE_SSPP_SRC */
  17. #define SSPP_SRC_SIZE 0x00
  18. #define SSPP_SRC_XY 0x08
  19. #define SSPP_OUT_SIZE 0x0c
  20. #define SSPP_OUT_XY 0x10
  21. #define SSPP_SRC0_ADDR 0x14
  22. #define SSPP_SRC1_ADDR 0x18
  23. #define SSPP_SRC2_ADDR 0x1C
  24. #define SSPP_SRC3_ADDR 0x20
  25. #define SSPP_SRC_YSTRIDE0 0x24
  26. #define SSPP_SRC_YSTRIDE1 0x28
  27. #define SSPP_SRC_FORMAT 0x30
  28. #define SSPP_SRC_UNPACK_PATTERN 0x34
  29. #define SSPP_SRC_OP_MODE 0x38
  30. /* SSPP_MULTIRECT*/
  31. #define SSPP_SRC_SIZE_REC1 0x16C
  32. #define SSPP_SRC_XY_REC1 0x168
  33. #define SSPP_OUT_SIZE_REC1 0x160
  34. #define SSPP_OUT_XY_REC1 0x164
  35. #define SSPP_SRC_FORMAT_REC1 0x174
  36. #define SSPP_SRC_UNPACK_PATTERN_REC1 0x178
  37. #define SSPP_SRC_OP_MODE_REC1 0x17C
  38. #define SSPP_MULTIRECT_OPMODE 0x170
  39. #define SSPP_SRC_CONSTANT_COLOR_REC1 0x180
  40. #define SSPP_EXCL_REC_SIZE_REC1 0x184
  41. #define SSPP_EXCL_REC_XY_REC1 0x188
  42. #define SSPP_UIDLE_CTRL_VALUE 0x1f0
  43. #define SSPP_UIDLE_CTRL_VALUE_REC1 0x1f4
  44. /* SSPP_DGM */
  45. #define SSPP_DGM_0 0x9F0
  46. #define SSPP_DGM_1 0x19F0
  47. #define SSPP_DGM_SIZE 0x420
  48. #define SSPP_DGM_CSC_0 0x800
  49. #define SSPP_DGM_CSC_1 0x1800
  50. #define SSPP_DGM_CSC_SIZE 0xFC
  51. #define VIG_GAMUT_SIZE 0x1CC
  52. #define MDSS_MDP_OP_DEINTERLACE BIT(22)
  53. #define MDSS_MDP_OP_DEINTERLACE_ODD BIT(23)
  54. #define MDSS_MDP_OP_IGC_ROM_1 BIT(18)
  55. #define MDSS_MDP_OP_IGC_ROM_0 BIT(17)
  56. #define MDSS_MDP_OP_IGC_EN BIT(16)
  57. #define MDSS_MDP_OP_FLIP_UD BIT(14)
  58. #define MDSS_MDP_OP_FLIP_LR BIT(13)
  59. #define MDSS_MDP_OP_SPLIT_ORDER BIT(4)
  60. #define MDSS_MDP_OP_BWC_EN BIT(0)
  61. #define MDSS_MDP_OP_PE_OVERRIDE BIT(31)
  62. #define MDSS_MDP_OP_BWC_LOSSLESS (0 << 1)
  63. #define MDSS_MDP_OP_BWC_Q_HIGH (1 << 1)
  64. #define MDSS_MDP_OP_BWC_Q_MED (2 << 1)
  65. #define SSPP_SRC_CONSTANT_COLOR 0x3c
  66. #define SSPP_EXCL_REC_CTL 0x40
  67. #define SSPP_UBWC_STATIC_CTRL 0x44
  68. #define SSPP_FETCH_CONFIG 0x48
  69. #define SSPP_PRE_DOWN_SCALE 0x50
  70. #define SSPP_DANGER_LUT 0x60
  71. #define SSPP_SAFE_LUT 0x64
  72. #define SSPP_CREQ_LUT 0x68
  73. #define SSPP_QOS_CTRL 0x6C
  74. #define SSPP_DECIMATION_CONFIG 0xB4
  75. #define SSPP_SRC_ADDR_SW_STATUS 0x70
  76. #define SSPP_CREQ_LUT_0 0x74
  77. #define SSPP_CREQ_LUT_1 0x78
  78. #define SSPP_UBWC_STATS_ROI 0x7C
  79. #define SSPP_UBWC_STATS_DATA 0x80
  80. #define SSPP_UBWC_STATS_ROI_REC1 0xB4
  81. #define SSPP_UBWC_STATS_DATA_REC1 0xB8
  82. #define SSPP_SW_PIX_EXT_C0_LR 0x100
  83. #define SSPP_SW_PIX_EXT_C0_TB 0x104
  84. #define SSPP_SW_PIX_EXT_C0_REQ_PIXELS 0x108
  85. #define SSPP_SW_PIX_EXT_C1C2_LR 0x110
  86. #define SSPP_SW_PIX_EXT_C1C2_TB 0x114
  87. #define SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS 0x118
  88. #define SSPP_SW_PIX_EXT_C3_LR 0x120
  89. #define SSPP_SW_PIX_EXT_C3_TB 0x124
  90. #define SSPP_SW_PIX_EXT_C3_REQ_PIXELS 0x128
  91. #define SSPP_META_ERROR_STATUS 0X12C
  92. #define SSPP_TRAFFIC_SHAPER 0x130
  93. #define SSPP_CDP_CNTL 0x134
  94. #define SSPP_UBWC_ERROR_STATUS 0x138
  95. #define SSPP_CDP_CNTL_REC1 0x13c
  96. #define SSPP_TRAFFIC_SHAPER_PREFILL 0x150
  97. #define SSPP_TRAFFIC_SHAPER_REC1_PREFILL 0x154
  98. #define SSPP_TRAFFIC_SHAPER_REC1 0x158
  99. #define SSPP_EXCL_REC_SIZE 0x1B4
  100. #define SSPP_EXCL_REC_XY 0x1B8
  101. #define SSPP_UBWC_STATIC_CTRL_REC1 0x1C0
  102. #define SSPP_UBWC_ERROR_STATUS_REC1 0x1C8
  103. #define SSPP_META_ERROR_STATUS_REC1 0x1C4
  104. #define SSPP_VIG_OP_MODE 0x0
  105. #define SSPP_VIG_CSC_10_OP_MODE 0x0
  106. #define SSPP_TRAFFIC_SHAPER_BPC_MAX 0xFF
  107. #define SSPP_CLK_CTRL 0x330
  108. #define SSPP_CLK_STATUS 0x334
  109. /* SSPP_QOS_CTRL */
  110. #define SSPP_QOS_CTRL_VBLANK_EN BIT(16)
  111. #define SSPP_QOS_CTRL_DANGER_SAFE_EN BIT(0)
  112. #define SSPP_QOS_CTRL_DANGER_VBLANK_MASK 0x3
  113. #define SSPP_QOS_CTRL_DANGER_VBLANK_OFF 4
  114. #define SSPP_QOS_CTRL_CREQ_VBLANK_MASK 0x3
  115. #define SSPP_QOS_CTRL_CREQ_VBLANK_OFF 20
  116. #define SSPP_SYS_CACHE_MODE 0x1BC
  117. #define SSPP_SBUF_STATUS_PLANE0 0x1C0
  118. #define SSPP_SBUF_STATUS_PLANE1 0x1C4
  119. #define SSPP_SBUF_STATUS_PLANE_EMPTY BIT(16)
  120. /* SDE_SSPP_SCALER_QSEED2 */
  121. #define SCALE_CONFIG 0x04
  122. #define COMP0_3_PHASE_STEP_X 0x10
  123. #define COMP0_3_PHASE_STEP_Y 0x14
  124. #define COMP1_2_PHASE_STEP_X 0x18
  125. #define COMP1_2_PHASE_STEP_Y 0x1c
  126. #define COMP0_3_INIT_PHASE_X 0x20
  127. #define COMP0_3_INIT_PHASE_Y 0x24
  128. #define COMP1_2_INIT_PHASE_X 0x28
  129. #define COMP1_2_INIT_PHASE_Y 0x2C
  130. #define VIG_0_QSEED2_SHARP 0x30
  131. /*
  132. * Definitions for ViG op modes
  133. */
  134. #define VIG_OP_CSC_DST_DATAFMT BIT(19)
  135. #define VIG_OP_CSC_SRC_DATAFMT BIT(18)
  136. #define VIG_OP_CSC_EN BIT(17)
  137. #define VIG_OP_MEM_PROT_CONT BIT(15)
  138. #define VIG_OP_MEM_PROT_VAL BIT(14)
  139. #define VIG_OP_MEM_PROT_SAT BIT(13)
  140. #define VIG_OP_MEM_PROT_HUE BIT(12)
  141. #define VIG_OP_HIST BIT(8)
  142. #define VIG_OP_SKY_COL BIT(7)
  143. #define VIG_OP_FOIL BIT(6)
  144. #define VIG_OP_SKIN_COL BIT(5)
  145. #define VIG_OP_PA_EN BIT(4)
  146. #define VIG_OP_PA_SAT_ZERO_EXP BIT(2)
  147. #define VIG_OP_MEM_PROT_BLEND BIT(1)
  148. /*
  149. * Definitions for CSC 10 op modes
  150. */
  151. #define VIG_CSC_10_SRC_DATAFMT BIT(1)
  152. #define VIG_CSC_10_EN BIT(0)
  153. #define CSC_10BIT_OFFSET 4
  154. #define DGM_CSC_MATRIX_SHIFT 0
  155. /* traffic shaper clock in Hz */
  156. #define TS_CLK 19200000
  157. static inline int _sspp_subblk_offset(struct sde_hw_pipe *ctx,
  158. int s_id,
  159. u32 *idx)
  160. {
  161. int rc = 0;
  162. const struct sde_sspp_sub_blks *sblk;
  163. if (!ctx)
  164. return -EINVAL;
  165. sblk = ctx->cap->sblk;
  166. switch (s_id) {
  167. case SDE_SSPP_SRC:
  168. *idx = sblk->src_blk.base;
  169. break;
  170. case SDE_SSPP_SCALER_QSEED2:
  171. case SDE_SSPP_SCALER_QSEED3:
  172. *idx = sblk->scaler_blk.base;
  173. break;
  174. case SDE_SSPP_CSC:
  175. case SDE_SSPP_CSC_10BIT:
  176. *idx = sblk->csc_blk.base;
  177. break;
  178. case SDE_SSPP_HSIC:
  179. *idx = sblk->hsic_blk.base;
  180. break;
  181. case SDE_SSPP_PCC:
  182. *idx = sblk->pcc_blk.base;
  183. break;
  184. case SDE_SSPP_MEMCOLOR:
  185. *idx = sblk->memcolor_blk.base;
  186. break;
  187. default:
  188. rc = -EINVAL;
  189. }
  190. return rc;
  191. }
  192. static void sde_hw_sspp_update_multirect(struct sde_hw_pipe *ctx,
  193. bool enable,
  194. enum sde_sspp_multirect_index index,
  195. enum sde_sspp_multirect_mode mode)
  196. {
  197. u32 mode_mask;
  198. u32 idx;
  199. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  200. return;
  201. if (index == SDE_SSPP_RECT_SOLO) {
  202. /**
  203. * if rect index is RECT_SOLO, we cannot expect a
  204. * virtual plane sharing the same SSPP id. So we go
  205. * and disable multirect
  206. */
  207. mode_mask = 0;
  208. } else {
  209. mode_mask = SDE_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx);
  210. if (enable)
  211. mode_mask |= index;
  212. else
  213. mode_mask &= ~index;
  214. if (enable && (mode == SDE_SSPP_MULTIRECT_TIME_MX))
  215. mode_mask |= BIT(2);
  216. else
  217. mode_mask &= ~BIT(2);
  218. }
  219. SDE_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask);
  220. }
  221. static void _sspp_setup_opmode(struct sde_hw_pipe *ctx,
  222. u32 mask, u8 en)
  223. {
  224. u32 idx;
  225. u32 opmode;
  226. if (!test_bit(SDE_SSPP_SCALER_QSEED2, &ctx->cap->features) ||
  227. _sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED2, &idx) ||
  228. !test_bit(SDE_SSPP_CSC, &ctx->cap->features))
  229. return;
  230. opmode = SDE_REG_READ(&ctx->hw, SSPP_VIG_OP_MODE + idx);
  231. if (en)
  232. opmode |= mask;
  233. else
  234. opmode &= ~mask;
  235. SDE_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode);
  236. }
  237. static void _sspp_setup_csc10_opmode(struct sde_hw_pipe *ctx,
  238. u32 mask, u8 en)
  239. {
  240. u32 idx;
  241. u32 opmode;
  242. if (_sspp_subblk_offset(ctx, SDE_SSPP_CSC_10BIT, &idx))
  243. return;
  244. opmode = SDE_REG_READ(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx);
  245. if (en)
  246. opmode |= mask;
  247. else
  248. opmode &= ~mask;
  249. SDE_REG_WRITE(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx, opmode);
  250. }
  251. static void sde_hw_sspp_set_src_split_order(struct sde_hw_pipe *ctx,
  252. enum sde_sspp_multirect_index rect_mode, bool enable)
  253. {
  254. struct sde_hw_blk_reg_map *c;
  255. u32 opmode, idx, op_mode_off;
  256. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  257. return;
  258. if (rect_mode == SDE_SSPP_RECT_SOLO || rect_mode == SDE_SSPP_RECT_0)
  259. op_mode_off = SSPP_SRC_OP_MODE;
  260. else
  261. op_mode_off = SSPP_SRC_OP_MODE_REC1;
  262. c = &ctx->hw;
  263. opmode = SDE_REG_READ(c, op_mode_off + idx);
  264. if (enable)
  265. opmode |= MDSS_MDP_OP_SPLIT_ORDER;
  266. else
  267. opmode &= ~MDSS_MDP_OP_SPLIT_ORDER;
  268. SDE_REG_WRITE(c, op_mode_off + idx, opmode);
  269. }
  270. static void sde_hw_sspp_setup_ubwc(struct sde_hw_pipe *ctx, struct sde_hw_blk_reg_map *c,
  271. const struct sde_format *fmt, bool const_alpha_en, bool const_color_en,
  272. enum sde_sspp_multirect_index rect_mode)
  273. {
  274. u32 alpha_en_mask = 0, color_en_mask = 0, ubwc_ctrl_off;
  275. SDE_REG_WRITE(c, SSPP_FETCH_CONFIG,
  276. SDE_FETCH_CONFIG_RESET_VALUE |
  277. ctx->mdp->highest_bank_bit << 18);
  278. if ((rect_mode == SDE_SSPP_RECT_SOLO || rect_mode == SDE_SSPP_RECT_0) ||
  279. !test_bit(SDE_SSPP_UBWC_STATS, &ctx->cap->features))
  280. ubwc_ctrl_off = SSPP_UBWC_STATIC_CTRL;
  281. else
  282. ubwc_ctrl_off = SSPP_UBWC_STATIC_CTRL_REC1;
  283. if (IS_UBWC_40_SUPPORTED(ctx->catalog->ubwc_rev)) {
  284. SDE_REG_WRITE(c, ubwc_ctrl_off, SDE_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
  285. } else if (IS_UBWC_30_SUPPORTED(ctx->catalog->ubwc_rev)) {
  286. color_en_mask = const_color_en ? BIT(30) : 0;
  287. SDE_REG_WRITE(c, ubwc_ctrl_off,
  288. color_en_mask | (ctx->mdp->ubwc_swizzle) |
  289. (ctx->mdp->highest_bank_bit << 4));
  290. } else if (IS_UBWC_20_SUPPORTED(ctx->catalog->ubwc_rev)) {
  291. alpha_en_mask = const_alpha_en ? BIT(31) : 0;
  292. SDE_REG_WRITE(c, ubwc_ctrl_off,
  293. alpha_en_mask | (ctx->mdp->ubwc_swizzle) |
  294. (ctx->mdp->highest_bank_bit << 4));
  295. } else if (IS_UBWC_10_SUPPORTED(ctx->catalog->ubwc_rev)) {
  296. alpha_en_mask = const_alpha_en ? BIT(31) : 0;
  297. SDE_REG_WRITE(c, ubwc_ctrl_off,
  298. alpha_en_mask | (ctx->mdp->ubwc_swizzle & 0x1) |
  299. BIT(8) | (ctx->mdp->highest_bank_bit << 4));
  300. }
  301. }
  302. /**
  303. * Setup source pixel format, flip,
  304. */
  305. static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx,
  306. const struct sde_format *fmt,
  307. bool const_alpha_en, u32 flags,
  308. enum sde_sspp_multirect_index rect_mode)
  309. {
  310. struct sde_hw_blk_reg_map *c;
  311. u32 chroma_samp, unpack, src_format;
  312. u32 opmode = 0;
  313. u32 op_mode_off, unpack_pat_off, format_off;
  314. u32 idx;
  315. bool const_color_en = true;
  316. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx) || !fmt)
  317. return;
  318. if (rect_mode == SDE_SSPP_RECT_SOLO || rect_mode == SDE_SSPP_RECT_0) {
  319. op_mode_off = SSPP_SRC_OP_MODE;
  320. unpack_pat_off = SSPP_SRC_UNPACK_PATTERN;
  321. format_off = SSPP_SRC_FORMAT;
  322. } else {
  323. op_mode_off = SSPP_SRC_OP_MODE_REC1;
  324. unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1;
  325. format_off = SSPP_SRC_FORMAT_REC1;
  326. }
  327. c = &ctx->hw;
  328. opmode = SDE_REG_READ(c, op_mode_off + idx);
  329. opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD |
  330. MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE);
  331. if (flags & SDE_SSPP_FLIP_LR)
  332. opmode |= MDSS_MDP_OP_FLIP_LR;
  333. if (flags & SDE_SSPP_FLIP_UD)
  334. opmode |= MDSS_MDP_OP_FLIP_UD;
  335. chroma_samp = fmt->chroma_sample;
  336. if (flags & SDE_SSPP_SOURCE_ROTATED_90) {
  337. if (chroma_samp == SDE_CHROMA_H2V1)
  338. chroma_samp = SDE_CHROMA_H1V2;
  339. else if (chroma_samp == SDE_CHROMA_H1V2)
  340. chroma_samp = SDE_CHROMA_H2V1;
  341. }
  342. src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) |
  343. (fmt->bits[C3_ALPHA] << 6) | (fmt->bits[C2_R_Cr] << 4) |
  344. (fmt->bits[C1_B_Cb] << 2) | (fmt->bits[C0_G_Y] << 0);
  345. if (flags & SDE_SSPP_ROT_90)
  346. src_format |= BIT(11); /* ROT90 */
  347. if (fmt->alpha_enable && fmt->fetch_planes == SDE_PLANE_INTERLEAVED)
  348. src_format |= BIT(8); /* SRCC3_EN */
  349. if (flags & SDE_SSPP_SOLID_FILL)
  350. src_format |= BIT(22);
  351. unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) |
  352. (fmt->element[1] << 8) | (fmt->element[0] << 0);
  353. src_format |= ((fmt->unpack_count - 1) << 12) |
  354. (fmt->unpack_tight << 17) |
  355. (fmt->unpack_align_msb << 18);
  356. if (SDE_FORMAT_IS_FP16(fmt)) {
  357. src_format |= BIT(16) | BIT(10) | BIT(9);
  358. } else if (fmt->bpp <= 4) {
  359. src_format |= ((fmt->bpp - 1) << 9);
  360. } else if (fmt->bpp <= 8) {
  361. src_format |= BIT(16) | ((fmt->bpp - 5) << 9);
  362. }
  363. if ((flags & SDE_SSPP_ROT_90) && test_bit(SDE_SSPP_INLINE_CONST_CLR,
  364. &ctx->cap->features))
  365. const_color_en = false;
  366. if (fmt->fetch_mode != SDE_FETCH_LINEAR) {
  367. if (SDE_FORMAT_IS_UBWC(fmt))
  368. opmode |= MDSS_MDP_OP_BWC_EN;
  369. src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
  370. sde_hw_sspp_setup_ubwc(ctx, c, fmt, const_alpha_en, const_color_en, rect_mode);
  371. }
  372. opmode |= MDSS_MDP_OP_PE_OVERRIDE;
  373. /* if this is YUV pixel format, enable CSC */
  374. if (SDE_FORMAT_IS_YUV(fmt))
  375. src_format |= BIT(15);
  376. if (SDE_FORMAT_IS_DX(fmt))
  377. src_format |= BIT(14);
  378. /* update scaler opmode, if appropriate */
  379. if (test_bit(SDE_SSPP_CSC, &ctx->cap->features))
  380. _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
  381. SDE_FORMAT_IS_YUV(fmt));
  382. else if (test_bit(SDE_SSPP_CSC_10BIT, &ctx->cap->features))
  383. _sspp_setup_csc10_opmode(ctx,
  384. VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
  385. SDE_FORMAT_IS_YUV(fmt));
  386. SDE_REG_WRITE(c, format_off + idx, src_format);
  387. SDE_REG_WRITE(c, unpack_pat_off + idx, unpack);
  388. SDE_REG_WRITE(c, op_mode_off + idx, opmode);
  389. /* clear previous UBWC error */
  390. SDE_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31));
  391. }
  392. static void sde_hw_sspp_clear_ubwc_error(struct sde_hw_pipe *ctx,
  393. enum sde_sspp_multirect_index multirect_index)
  394. {
  395. struct sde_hw_blk_reg_map *c;
  396. c = &ctx->hw;
  397. SDE_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31));
  398. }
  399. static u32 sde_hw_sspp_get_ubwc_error(struct sde_hw_pipe *ctx,
  400. enum sde_sspp_multirect_index multirect_index)
  401. {
  402. struct sde_hw_blk_reg_map *c;
  403. u32 reg_code;
  404. c = &ctx->hw;
  405. reg_code = SDE_REG_READ(c, SSPP_UBWC_ERROR_STATUS);
  406. return reg_code;
  407. }
  408. static void sde_hw_sspp_clear_ubwc_error_v1(struct sde_hw_pipe *ctx,
  409. enum sde_sspp_multirect_index multirect_index)
  410. {
  411. struct sde_hw_blk_reg_map *c;
  412. c = &ctx->hw;
  413. if (multirect_index == SDE_SSPP_RECT_1)
  414. SDE_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS_REC1, BIT(31));
  415. else
  416. SDE_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31));
  417. }
  418. static u32 sde_hw_sspp_get_ubwc_error_v1(struct sde_hw_pipe *ctx,
  419. enum sde_sspp_multirect_index multirect_index)
  420. {
  421. struct sde_hw_blk_reg_map *c;
  422. u32 reg_code;
  423. c = &ctx->hw;
  424. if (multirect_index == SDE_SSPP_RECT_1)
  425. reg_code = SDE_REG_READ(c, SSPP_UBWC_ERROR_STATUS_REC1);
  426. else
  427. reg_code = SDE_REG_READ(c, SSPP_UBWC_ERROR_STATUS);
  428. return reg_code;
  429. }
  430. static void sde_hw_sspp_clear_meta_error(struct sde_hw_pipe *ctx,
  431. enum sde_sspp_multirect_index multirect_index)
  432. {
  433. struct sde_hw_blk_reg_map *c;
  434. c = &ctx->hw;
  435. if (multirect_index == SDE_SSPP_RECT_1)
  436. SDE_REG_WRITE(c, SSPP_META_ERROR_STATUS_REC1, BIT(31));
  437. else
  438. SDE_REG_WRITE(c, SSPP_META_ERROR_STATUS, BIT(31));
  439. }
  440. static u32 sde_hw_sspp_get_meta_error(struct sde_hw_pipe *ctx,
  441. enum sde_sspp_multirect_index multirect_index)
  442. {
  443. struct sde_hw_blk_reg_map *c;
  444. u32 reg_code;
  445. c = &ctx->hw;
  446. if (multirect_index == SDE_SSPP_RECT_1)
  447. reg_code = SDE_REG_READ(c, SSPP_META_ERROR_STATUS_REC1);
  448. else
  449. reg_code = SDE_REG_READ(c, SSPP_META_ERROR_STATUS);
  450. return reg_code;
  451. }
  452. static void sde_hw_sspp_ubwc_stats_set_roi(struct sde_hw_pipe *ctx,
  453. enum sde_sspp_multirect_index multirect_index,
  454. struct sde_drm_ubwc_stats_roi *roi)
  455. {
  456. struct sde_hw_blk_reg_map *c;
  457. u32 idx, ctrl_off, roi_off;
  458. u32 ctrl_val = 0, roi_val = 0;
  459. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  460. return;
  461. if (multirect_index == SDE_SSPP_RECT_SOLO || multirect_index == SDE_SSPP_RECT_0) {
  462. ctrl_off = SSPP_UBWC_STATIC_CTRL + idx;
  463. roi_off = SSPP_UBWC_STATS_ROI + idx;
  464. } else {
  465. ctrl_off = SSPP_UBWC_STATIC_CTRL_REC1 + idx;
  466. roi_off = SSPP_UBWC_STATS_ROI_REC1 + idx;
  467. }
  468. c = &ctx->hw;
  469. ctrl_val = SDE_REG_READ(c, ctrl_off);
  470. if (roi) {
  471. ctrl_val |= BIT(24);
  472. if (roi->y_coord0) {
  473. ctrl_val |= BIT(25);
  474. roi_val |= roi->y_coord0;
  475. if (roi->y_coord1) {
  476. ctrl_val |= BIT(26);
  477. roi_val |= (roi->y_coord1) << 0x10;
  478. }
  479. }
  480. } else {
  481. ctrl_val &= ~(BIT(24) | BIT(25) | BIT(26));
  482. }
  483. SDE_REG_WRITE(c, ctrl_off, ctrl_val);
  484. SDE_REG_WRITE(c, roi_off, roi_val);
  485. }
  486. static void sde_hw_sspp_ubwc_stats_get_data(struct sde_hw_pipe *ctx,
  487. enum sde_sspp_multirect_index multirect_index,
  488. struct sde_drm_ubwc_stats_data *data)
  489. {
  490. struct sde_hw_blk_reg_map *c;
  491. u32 idx, value = 0;
  492. int i;
  493. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  494. return;
  495. if (multirect_index == SDE_SSPP_RECT_SOLO || multirect_index == SDE_SSPP_RECT_0)
  496. idx += SSPP_UBWC_STATS_DATA;
  497. else
  498. idx += SSPP_UBWC_STATS_DATA_REC1;
  499. c = &ctx->hw;
  500. for (i = 0; i < UBWC_STATS_MAX_ROI; i++) {
  501. value = SDE_REG_READ(c, idx);
  502. data->worst_bw[i] = value & 0xFFFF;
  503. data->worst_bw_y_coord[i] = (value >> 0x10) & 0xFFFF;
  504. data->total_bw[i] = SDE_REG_READ(c, idx + 4);
  505. idx += 8;
  506. }
  507. }
  508. static void sde_hw_sspp_setup_secure(struct sde_hw_pipe *ctx,
  509. enum sde_sspp_multirect_index rect_mode,
  510. bool enable)
  511. {
  512. struct sde_hw_blk_reg_map *c;
  513. u32 secure = 0, secure_bit_mask;
  514. u32 idx;
  515. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  516. return;
  517. c = &ctx->hw;
  518. if ((rect_mode == SDE_SSPP_RECT_SOLO)
  519. || (rect_mode == SDE_SSPP_RECT_0))
  520. secure_bit_mask =
  521. (rect_mode == SDE_SSPP_RECT_SOLO) ? 0xF : 0x5;
  522. else
  523. secure_bit_mask = 0xA;
  524. secure = SDE_REG_READ(c, SSPP_SRC_ADDR_SW_STATUS + idx);
  525. if (enable)
  526. secure |= secure_bit_mask;
  527. else
  528. secure &= ~secure_bit_mask;
  529. SDE_REG_WRITE(c, SSPP_SRC_ADDR_SW_STATUS + idx, secure);
  530. /* multiple planes share same sw_status register */
  531. wmb();
  532. }
  533. static void sde_hw_sspp_setup_pe_config(struct sde_hw_pipe *ctx,
  534. struct sde_hw_pixel_ext *pe_ext)
  535. {
  536. struct sde_hw_blk_reg_map *c;
  537. u8 color;
  538. u32 lr_pe[4], tb_pe[4], tot_req_pixels[4];
  539. const u32 bytemask = 0xff;
  540. const u32 shortmask = 0xffff;
  541. u32 idx;
  542. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx) || !pe_ext)
  543. return;
  544. c = &ctx->hw;
  545. /* program SW pixel extension override for all pipes*/
  546. for (color = 0; color < SDE_MAX_PLANES; color++) {
  547. /* color 2 has the same set of registers as color 1 */
  548. if (color == 2)
  549. continue;
  550. lr_pe[color] = ((pe_ext->right_ftch[color] & bytemask) << 24)|
  551. ((pe_ext->right_rpt[color] & bytemask) << 16)|
  552. ((pe_ext->left_ftch[color] & bytemask) << 8)|
  553. (pe_ext->left_rpt[color] & bytemask);
  554. tb_pe[color] = ((pe_ext->btm_ftch[color] & bytemask) << 24)|
  555. ((pe_ext->btm_rpt[color] & bytemask) << 16)|
  556. ((pe_ext->top_ftch[color] & bytemask) << 8)|
  557. (pe_ext->top_rpt[color] & bytemask);
  558. tot_req_pixels[color] = (((pe_ext->roi_h[color] +
  559. pe_ext->num_ext_pxls_top[color] +
  560. pe_ext->num_ext_pxls_btm[color]) & shortmask) << 16) |
  561. ((pe_ext->roi_w[color] +
  562. pe_ext->num_ext_pxls_left[color] +
  563. pe_ext->num_ext_pxls_right[color]) & shortmask);
  564. }
  565. /* color 0 */
  566. SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_LR + idx, lr_pe[0]);
  567. SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_TB + idx, tb_pe[0]);
  568. SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_REQ_PIXELS + idx,
  569. tot_req_pixels[0]);
  570. /* color 1 and color 2 */
  571. SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_LR + idx, lr_pe[1]);
  572. SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_TB + idx, tb_pe[1]);
  573. SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS + idx,
  574. tot_req_pixels[1]);
  575. /* color 3 */
  576. SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_LR + idx, lr_pe[3]);
  577. SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_TB + idx, tb_pe[3]);
  578. SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_REQ_PIXELS + idx,
  579. tot_req_pixels[3]);
  580. }
  581. static void _sde_hw_sspp_setup_scaler(struct sde_hw_pipe *ctx,
  582. struct sde_hw_pipe_cfg *sspp,
  583. struct sde_hw_pixel_ext *pe,
  584. void *scaler_cfg)
  585. {
  586. struct sde_hw_blk_reg_map *c;
  587. int config_h = 0x0;
  588. int config_v = 0x0;
  589. u32 idx;
  590. (void)sspp;
  591. (void)scaler_cfg;
  592. if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED2, &idx) || !pe)
  593. return;
  594. c = &ctx->hw;
  595. /* enable scaler(s) if valid filter set */
  596. if (pe->horz_filter[SDE_SSPP_COMP_0] < SDE_SCALE_FILTER_MAX)
  597. config_h |= pe->horz_filter[SDE_SSPP_COMP_0] << 8;
  598. if (pe->horz_filter[SDE_SSPP_COMP_1_2] < SDE_SCALE_FILTER_MAX)
  599. config_h |= pe->horz_filter[SDE_SSPP_COMP_1_2] << 12;
  600. if (pe->horz_filter[SDE_SSPP_COMP_3] < SDE_SCALE_FILTER_MAX)
  601. config_h |= pe->horz_filter[SDE_SSPP_COMP_3] << 16;
  602. if (config_h)
  603. config_h |= BIT(0);
  604. if (pe->vert_filter[SDE_SSPP_COMP_0] < SDE_SCALE_FILTER_MAX)
  605. config_v |= pe->vert_filter[SDE_SSPP_COMP_0] << 10;
  606. if (pe->vert_filter[SDE_SSPP_COMP_1_2] < SDE_SCALE_FILTER_MAX)
  607. config_v |= pe->vert_filter[SDE_SSPP_COMP_1_2] << 14;
  608. if (pe->vert_filter[SDE_SSPP_COMP_3] < SDE_SCALE_FILTER_MAX)
  609. config_v |= pe->vert_filter[SDE_SSPP_COMP_3] << 18;
  610. if (config_v)
  611. config_v |= BIT(1);
  612. SDE_REG_WRITE(c, SCALE_CONFIG + idx, config_h | config_v);
  613. SDE_REG_WRITE(c, COMP0_3_INIT_PHASE_X + idx,
  614. pe->init_phase_x[SDE_SSPP_COMP_0]);
  615. SDE_REG_WRITE(c, COMP0_3_INIT_PHASE_Y + idx,
  616. pe->init_phase_y[SDE_SSPP_COMP_0]);
  617. SDE_REG_WRITE(c, COMP0_3_PHASE_STEP_X + idx,
  618. pe->phase_step_x[SDE_SSPP_COMP_0]);
  619. SDE_REG_WRITE(c, COMP0_3_PHASE_STEP_Y + idx,
  620. pe->phase_step_y[SDE_SSPP_COMP_0]);
  621. SDE_REG_WRITE(c, COMP1_2_INIT_PHASE_X + idx,
  622. pe->init_phase_x[SDE_SSPP_COMP_1_2]);
  623. SDE_REG_WRITE(c, COMP1_2_INIT_PHASE_Y + idx,
  624. pe->init_phase_y[SDE_SSPP_COMP_1_2]);
  625. SDE_REG_WRITE(c, COMP1_2_PHASE_STEP_X + idx,
  626. pe->phase_step_x[SDE_SSPP_COMP_1_2]);
  627. SDE_REG_WRITE(c, COMP1_2_PHASE_STEP_Y + idx,
  628. pe->phase_step_y[SDE_SSPP_COMP_1_2]);
  629. }
  630. static void _sde_hw_sspp_setup_scaler3(struct sde_hw_pipe *ctx,
  631. struct sde_hw_pipe_cfg *sspp,
  632. struct sde_hw_pixel_ext *pe,
  633. void *scaler_cfg)
  634. {
  635. u32 idx;
  636. bool de_lpf_en = false;
  637. struct sde_hw_scaler3_cfg *scaler3_cfg = scaler_cfg;
  638. (void)pe;
  639. if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED3, &idx) || !sspp
  640. || !scaler3_cfg || !ctx || !ctx->cap || !ctx->cap->sblk)
  641. return;
  642. if (test_bit(SDE_SSPP_SCALER_DE_LPF_BLEND, &ctx->cap->features))
  643. de_lpf_en = true;
  644. sde_hw_setup_scaler3(&ctx->hw, scaler3_cfg,
  645. ctx->cap->sblk->scaler_blk.version, idx, sspp->layout.format, de_lpf_en);
  646. }
  647. static void sde_hw_sspp_setup_pre_downscale(struct sde_hw_pipe *ctx,
  648. struct sde_hw_inline_pre_downscale_cfg *pre_down)
  649. {
  650. u32 idx, val;
  651. if (!ctx || !pre_down || _sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  652. return;
  653. val = pre_down->pre_downscale_x_0 |
  654. (pre_down->pre_downscale_x_1 << 4) |
  655. (pre_down->pre_downscale_y_0 << 8) |
  656. (pre_down->pre_downscale_y_1 << 12);
  657. SDE_REG_WRITE(&ctx->hw, SSPP_PRE_DOWN_SCALE + idx, val);
  658. }
  659. /**
  660. * sde_hw_sspp_setup_rects()
  661. */
  662. static void sde_hw_sspp_setup_rects(struct sde_hw_pipe *ctx,
  663. struct sde_hw_pipe_cfg *cfg,
  664. enum sde_sspp_multirect_index rect_index)
  665. {
  666. struct sde_hw_blk_reg_map *c;
  667. u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
  668. u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
  669. u32 decimation = 0;
  670. u32 idx;
  671. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx) || !cfg)
  672. return;
  673. c = &ctx->hw;
  674. if (rect_index == SDE_SSPP_RECT_SOLO || rect_index == SDE_SSPP_RECT_0) {
  675. src_size_off = SSPP_SRC_SIZE;
  676. src_xy_off = SSPP_SRC_XY;
  677. out_size_off = SSPP_OUT_SIZE;
  678. out_xy_off = SSPP_OUT_XY;
  679. } else {
  680. src_size_off = SSPP_SRC_SIZE_REC1;
  681. src_xy_off = SSPP_SRC_XY_REC1;
  682. out_size_off = SSPP_OUT_SIZE_REC1;
  683. out_xy_off = SSPP_OUT_XY_REC1;
  684. }
  685. /* src and dest rect programming */
  686. src_xy = (cfg->src_rect.y << 16) | (cfg->src_rect.x);
  687. src_size = (cfg->src_rect.h << 16) | (cfg->src_rect.w);
  688. dst_xy = (cfg->dst_rect.y << 16) | (cfg->dst_rect.x);
  689. dst_size = (cfg->dst_rect.h << 16) | (cfg->dst_rect.w);
  690. if (rect_index == SDE_SSPP_RECT_SOLO) {
  691. ystride0 = (cfg->layout.plane_pitch[0]) |
  692. (cfg->layout.plane_pitch[1] << 16);
  693. ystride1 = (cfg->layout.plane_pitch[2]) |
  694. (cfg->layout.plane_pitch[3] << 16);
  695. } else {
  696. ystride0 = SDE_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx);
  697. ystride1 = SDE_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx);
  698. if (rect_index == SDE_SSPP_RECT_0) {
  699. ystride0 = (ystride0 & 0xFFFF0000) |
  700. (cfg->layout.plane_pitch[0] & 0x0000FFFF);
  701. ystride1 = (ystride1 & 0xFFFF0000)|
  702. (cfg->layout.plane_pitch[2] & 0x0000FFFF);
  703. } else {
  704. ystride0 = (ystride0 & 0x0000FFFF) |
  705. ((cfg->layout.plane_pitch[0] << 16) &
  706. 0xFFFF0000);
  707. ystride1 = (ystride1 & 0x0000FFFF) |
  708. ((cfg->layout.plane_pitch[2] << 16) &
  709. 0xFFFF0000);
  710. }
  711. }
  712. /* program scaler, phase registers, if pipes supporting scaling */
  713. if (ctx->cap->features & SDE_SSPP_SCALER) {
  714. /* program decimation */
  715. decimation = ((1 << cfg->horz_decimation) - 1) << 8;
  716. decimation |= ((1 << cfg->vert_decimation) - 1);
  717. }
  718. /* rectangle register programming */
  719. SDE_REG_WRITE(c, src_size_off + idx, src_size);
  720. SDE_REG_WRITE(c, src_xy_off + idx, src_xy);
  721. SDE_REG_WRITE(c, out_size_off + idx, dst_size);
  722. SDE_REG_WRITE(c, out_xy_off + idx, dst_xy);
  723. SDE_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0);
  724. SDE_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
  725. SDE_REG_WRITE(c, SSPP_DECIMATION_CONFIG + idx, decimation);
  726. }
  727. /**
  728. * _sde_hw_sspp_setup_excl_rect() - set exclusion rect configs
  729. * @ctx: Pointer to pipe context
  730. * @excl_rect: Exclusion rect configs
  731. */
  732. static void _sde_hw_sspp_setup_excl_rect(struct sde_hw_pipe *ctx,
  733. struct sde_rect *excl_rect,
  734. enum sde_sspp_multirect_index rect_index)
  735. {
  736. struct sde_hw_blk_reg_map *c;
  737. u32 size, xy;
  738. u32 idx;
  739. u32 reg_xy, reg_size;
  740. u32 excl_ctrl = BIT(0);
  741. u32 enable_bit;
  742. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx) || !excl_rect)
  743. return;
  744. if (rect_index == SDE_SSPP_RECT_0 || rect_index == SDE_SSPP_RECT_SOLO) {
  745. reg_xy = SSPP_EXCL_REC_XY;
  746. reg_size = SSPP_EXCL_REC_SIZE;
  747. enable_bit = BIT(0);
  748. } else {
  749. reg_xy = SSPP_EXCL_REC_XY_REC1;
  750. reg_size = SSPP_EXCL_REC_SIZE_REC1;
  751. enable_bit = BIT(1);
  752. }
  753. c = &ctx->hw;
  754. xy = (excl_rect->y << 16) | (excl_rect->x);
  755. size = (excl_rect->h << 16) | (excl_rect->w);
  756. /* Set if multi-rect disabled, read+modify only if multi-rect enabled */
  757. if (rect_index != SDE_SSPP_RECT_SOLO)
  758. excl_ctrl = SDE_REG_READ(c, SSPP_EXCL_REC_CTL + idx);
  759. if (!size) {
  760. SDE_REG_WRITE(c, SSPP_EXCL_REC_CTL + idx,
  761. excl_ctrl & ~enable_bit);
  762. } else {
  763. SDE_REG_WRITE(c, SSPP_EXCL_REC_CTL + idx,
  764. excl_ctrl | enable_bit);
  765. SDE_REG_WRITE(c, reg_size + idx, size);
  766. SDE_REG_WRITE(c, reg_xy + idx, xy);
  767. }
  768. }
  769. static void sde_hw_sspp_setup_sourceaddress(struct sde_hw_pipe *ctx,
  770. struct sde_hw_pipe_cfg *cfg,
  771. enum sde_sspp_multirect_index rect_mode)
  772. {
  773. int i;
  774. u32 idx;
  775. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  776. return;
  777. if (rect_mode == SDE_SSPP_RECT_SOLO) {
  778. for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
  779. SDE_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4,
  780. cfg->layout.plane_addr[i]);
  781. } else if (rect_mode == SDE_SSPP_RECT_0) {
  782. SDE_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx,
  783. cfg->layout.plane_addr[0]);
  784. SDE_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx,
  785. cfg->layout.plane_addr[2]);
  786. } else {
  787. SDE_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx,
  788. cfg->layout.plane_addr[0]);
  789. SDE_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
  790. cfg->layout.plane_addr[2]);
  791. }
  792. }
  793. u32 sde_hw_sspp_get_source_addr(struct sde_hw_pipe *ctx, bool is_virtual)
  794. {
  795. u32 idx;
  796. u32 offset = 0;
  797. if (!ctx || _sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  798. return 0;
  799. offset = is_virtual ? (SSPP_SRC1_ADDR + idx) : (SSPP_SRC0_ADDR + idx);
  800. return SDE_REG_READ(&ctx->hw, offset);
  801. }
  802. static void sde_hw_sspp_setup_csc(struct sde_hw_pipe *ctx,
  803. struct sde_csc_cfg *data)
  804. {
  805. u32 idx;
  806. bool csc10 = false;
  807. if (_sspp_subblk_offset(ctx, SDE_SSPP_CSC, &idx) || !data)
  808. return;
  809. if (test_bit(SDE_SSPP_CSC_10BIT, &ctx->cap->features)) {
  810. idx += CSC_10BIT_OFFSET;
  811. csc10 = true;
  812. }
  813. sde_hw_csc_setup(&ctx->hw, idx, data, csc10);
  814. }
  815. static void sde_hw_sspp_setup_sharpening(struct sde_hw_pipe *ctx,
  816. struct sde_hw_sharp_cfg *cfg)
  817. {
  818. struct sde_hw_blk_reg_map *c;
  819. u32 idx;
  820. if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED2, &idx) || !cfg ||
  821. !test_bit(SDE_SSPP_SCALER_QSEED2, &ctx->cap->features))
  822. return;
  823. c = &ctx->hw;
  824. SDE_REG_WRITE(c, VIG_0_QSEED2_SHARP + idx, cfg->strength);
  825. SDE_REG_WRITE(c, VIG_0_QSEED2_SHARP + idx + 0x4, cfg->edge_thr);
  826. SDE_REG_WRITE(c, VIG_0_QSEED2_SHARP + idx + 0x8, cfg->smooth_thr);
  827. SDE_REG_WRITE(c, VIG_0_QSEED2_SHARP + idx + 0xC, cfg->noise_thr);
  828. }
  829. static void sde_hw_sspp_setup_solidfill(struct sde_hw_pipe *ctx, u32 color, enum
  830. sde_sspp_multirect_index rect_index)
  831. {
  832. u32 idx;
  833. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  834. return;
  835. if (rect_index == SDE_SSPP_RECT_SOLO || rect_index == SDE_SSPP_RECT_0)
  836. SDE_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color);
  837. else
  838. SDE_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1 + idx,
  839. color);
  840. }
  841. static void sde_hw_sspp_setup_qos_lut(struct sde_hw_pipe *ctx,
  842. struct sde_hw_pipe_qos_cfg *cfg)
  843. {
  844. u32 idx;
  845. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  846. return;
  847. SDE_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, cfg->danger_lut);
  848. SDE_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, cfg->safe_lut);
  849. if (ctx->cap && test_bit(SDE_PERF_SSPP_QOS_8LVL,
  850. &ctx->cap->perf_features)) {
  851. SDE_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, cfg->creq_lut);
  852. SDE_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_1 + idx,
  853. cfg->creq_lut >> 32);
  854. } else {
  855. SDE_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, cfg->creq_lut);
  856. }
  857. }
  858. static void sde_hw_sspp_setup_qos_ctrl(struct sde_hw_pipe *ctx,
  859. struct sde_hw_pipe_qos_cfg *cfg)
  860. {
  861. u32 idx;
  862. u32 qos_ctrl = 0;
  863. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  864. return;
  865. if (cfg->vblank_en) {
  866. qos_ctrl |= ((cfg->creq_vblank &
  867. SSPP_QOS_CTRL_CREQ_VBLANK_MASK) <<
  868. SSPP_QOS_CTRL_CREQ_VBLANK_OFF);
  869. qos_ctrl |= ((cfg->danger_vblank &
  870. SSPP_QOS_CTRL_DANGER_VBLANK_MASK) <<
  871. SSPP_QOS_CTRL_DANGER_VBLANK_OFF);
  872. qos_ctrl |= SSPP_QOS_CTRL_VBLANK_EN;
  873. }
  874. if (cfg->danger_safe_en)
  875. qos_ctrl |= SSPP_QOS_CTRL_DANGER_SAFE_EN;
  876. SDE_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl);
  877. }
  878. static void sde_hw_sspp_setup_ts_prefill(struct sde_hw_pipe *ctx,
  879. struct sde_hw_pipe_ts_cfg *cfg,
  880. enum sde_sspp_multirect_index index)
  881. {
  882. u32 idx;
  883. u32 ts_offset, ts_prefill_offset;
  884. u32 ts_count = 0, ts_bytes = 0;
  885. const struct sde_sspp_cfg *cap;
  886. if (!ctx || !cfg || !ctx->cap)
  887. return;
  888. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  889. return;
  890. cap = ctx->cap;
  891. if ((index == SDE_SSPP_RECT_SOLO || index == SDE_SSPP_RECT_0) &&
  892. test_bit(SDE_PERF_SSPP_TS_PREFILL,
  893. &cap->perf_features)) {
  894. ts_offset = SSPP_TRAFFIC_SHAPER;
  895. ts_prefill_offset = SSPP_TRAFFIC_SHAPER_PREFILL;
  896. } else if (index == SDE_SSPP_RECT_1 &&
  897. test_bit(SDE_PERF_SSPP_TS_PREFILL_REC1,
  898. &cap->perf_features)) {
  899. ts_offset = SSPP_TRAFFIC_SHAPER_REC1;
  900. ts_prefill_offset = SSPP_TRAFFIC_SHAPER_REC1_PREFILL;
  901. } else {
  902. pr_err("%s: unexpected idx:%d\n", __func__, index);
  903. return;
  904. }
  905. if (cfg->time) {
  906. ts_count = DIV_ROUND_UP_ULL(TS_CLK * cfg->time, 1000000ULL);
  907. ts_bytes = DIV_ROUND_UP_ULL(cfg->size, ts_count);
  908. if (ts_bytes > SSPP_TRAFFIC_SHAPER_BPC_MAX)
  909. ts_bytes = SSPP_TRAFFIC_SHAPER_BPC_MAX;
  910. }
  911. if (ts_count)
  912. ts_bytes |= BIT(31) | BIT(27);
  913. SDE_REG_WRITE(&ctx->hw, ts_offset, ts_bytes);
  914. SDE_REG_WRITE(&ctx->hw, ts_prefill_offset, ts_count);
  915. }
  916. static void sde_hw_sspp_setup_cdp(struct sde_hw_pipe *ctx,
  917. struct sde_hw_pipe_cdp_cfg *cfg,
  918. enum sde_sspp_multirect_index index)
  919. {
  920. u32 idx;
  921. u32 cdp_cntl = 0;
  922. u32 cdp_cntl_offset = 0;
  923. if (!ctx || !cfg)
  924. return;
  925. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  926. return;
  927. if (index == SDE_SSPP_RECT_SOLO || index == SDE_SSPP_RECT_0) {
  928. cdp_cntl_offset = SSPP_CDP_CNTL;
  929. } else if (index == SDE_SSPP_RECT_1) {
  930. cdp_cntl_offset = SSPP_CDP_CNTL_REC1;
  931. } else {
  932. pr_err("%s: unexpected idx:%d\n", __func__, index);
  933. return;
  934. }
  935. if (cfg->enable)
  936. cdp_cntl |= BIT(0);
  937. if (cfg->ubwc_meta_enable)
  938. cdp_cntl |= BIT(1);
  939. if (cfg->tile_amortize_enable)
  940. cdp_cntl |= BIT(2);
  941. if (cfg->preload_ahead == SDE_SSPP_CDP_PRELOAD_AHEAD_64)
  942. cdp_cntl |= BIT(3);
  943. SDE_REG_WRITE(&ctx->hw, cdp_cntl_offset, cdp_cntl);
  944. }
  945. static void sde_hw_sspp_setup_sys_cache(struct sde_hw_pipe *ctx,
  946. struct sde_hw_pipe_sc_cfg *cfg)
  947. {
  948. u32 idx, val;
  949. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  950. return;
  951. if (!cfg)
  952. return;
  953. val = SDE_REG_READ(&ctx->hw, SSPP_SYS_CACHE_MODE + idx);
  954. if (cfg->flags & SYS_CACHE_EN_FLAG)
  955. val = (val & ~BIT(15)) | ((cfg->rd_en & 0x1) << 15);
  956. if (cfg->flags & SYS_CACHE_SCID)
  957. val = (val & ~0x1F00) | ((cfg->rd_scid & 0x1f) << 8);
  958. if (cfg->flags & SYS_CACHE_OP_MODE)
  959. val = (val & ~0xC0000) | ((cfg->op_mode & 0x3) << 18);
  960. if (cfg->flags & SYS_CACHE_OP_TYPE)
  961. val = (val & ~0xF) | ((cfg->rd_op_type & 0xf) << 0);
  962. if (cfg->flags & SYS_CACHE_NO_ALLOC)
  963. val = (val & ~0x10) | ((cfg->rd_noallocate & 0x1) << 4);
  964. SDE_REG_WRITE(&ctx->hw, SSPP_SYS_CACHE_MODE + idx, val);
  965. }
  966. static void sde_hw_sspp_setup_uidle(struct sde_hw_pipe *ctx,
  967. struct sde_hw_pipe_uidle_cfg *cfg,
  968. enum sde_sspp_multirect_index index)
  969. {
  970. u32 idx, val;
  971. u32 offset;
  972. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  973. return;
  974. if (index == SDE_SSPP_RECT_1)
  975. offset = SSPP_UIDLE_CTRL_VALUE_REC1;
  976. else
  977. offset = SSPP_UIDLE_CTRL_VALUE;
  978. val = SDE_REG_READ(&ctx->hw, offset + idx);
  979. val = (val & ~BIT(31)) | (cfg->enable ? 0x0 : BIT(31));
  980. val = (val & ~0xFF00000) | (cfg->fal_allowed_threshold << 20);
  981. val = (val & ~0xF0000) | (cfg->fal10_exit_threshold << 16);
  982. val = (val & ~0xF00) | (cfg->fal10_threshold << 8);
  983. val = (val & ~0xF) | (cfg->fal1_threshold << 0);
  984. SDE_REG_WRITE(&ctx->hw, offset + idx, val);
  985. }
  986. static void _setup_layer_ops_colorproc(struct sde_hw_pipe *c,
  987. unsigned long features, bool is_virtual_pipe)
  988. {
  989. int ret = 0;
  990. if (is_virtual_pipe) {
  991. features &=
  992. ~(BIT(SDE_SSPP_VIG_IGC) | BIT(SDE_SSPP_VIG_GAMUT));
  993. c->cap->features = features;
  994. }
  995. if (test_bit(SDE_SSPP_HSIC, &features)) {
  996. if (c->cap->sblk->hsic_blk.version ==
  997. (SDE_COLOR_PROCESS_VER(0x1, 0x7))) {
  998. c->ops.setup_pa_hue = sde_setup_pipe_pa_hue_v1_7;
  999. c->ops.setup_pa_sat = sde_setup_pipe_pa_sat_v1_7;
  1000. c->ops.setup_pa_val = sde_setup_pipe_pa_val_v1_7;
  1001. c->ops.setup_pa_cont = sde_setup_pipe_pa_cont_v1_7;
  1002. }
  1003. }
  1004. if (test_bit(SDE_SSPP_MEMCOLOR, &features)) {
  1005. if (c->cap->sblk->memcolor_blk.version ==
  1006. (SDE_COLOR_PROCESS_VER(0x1, 0x7)))
  1007. c->ops.setup_pa_memcolor =
  1008. sde_setup_pipe_pa_memcol_v1_7;
  1009. }
  1010. if (test_bit(SDE_SSPP_VIG_GAMUT, &features)) {
  1011. if (c->cap->sblk->gamut_blk.version ==
  1012. (SDE_COLOR_PROCESS_VER(0x5, 0x0))) {
  1013. ret = reg_dmav1_init_sspp_op_v4(SDE_SSPP_VIG_GAMUT,
  1014. c->idx);
  1015. if (!ret)
  1016. c->ops.setup_vig_gamut =
  1017. reg_dmav1_setup_vig_gamutv5;
  1018. else
  1019. c->ops.setup_vig_gamut = NULL;
  1020. }
  1021. if (c->cap->sblk->gamut_blk.version ==
  1022. (SDE_COLOR_PROCESS_VER(0x6, 0x0))) {
  1023. ret = reg_dmav1_init_sspp_op_v4(SDE_SSPP_VIG_GAMUT,
  1024. c->idx);
  1025. if (!ret)
  1026. c->ops.setup_vig_gamut =
  1027. reg_dmav1_setup_vig_gamutv6;
  1028. else
  1029. c->ops.setup_vig_gamut = NULL;
  1030. } else if (c->cap->sblk->gamut_blk.version ==
  1031. (SDE_COLOR_PROCESS_VER(0x6, 0x1))) {
  1032. ret = reg_dmav1_init_sspp_op_v4(SDE_SSPP_VIG_GAMUT,
  1033. c->idx);
  1034. if (!ret)
  1035. c->ops.setup_vig_gamut =
  1036. reg_dmav2_setup_vig_gamutv61;
  1037. else
  1038. c->ops.setup_vig_gamut = NULL;
  1039. }
  1040. }
  1041. if (test_bit(SDE_SSPP_VIG_IGC, &features)) {
  1042. if (c->cap->sblk->igc_blk[0].version ==
  1043. (SDE_COLOR_PROCESS_VER(0x5, 0x0))) {
  1044. ret = reg_dmav1_init_sspp_op_v4(SDE_SSPP_VIG_IGC,
  1045. c->idx);
  1046. if (!ret)
  1047. c->ops.setup_vig_igc =
  1048. reg_dmav1_setup_vig_igcv5;
  1049. else
  1050. c->ops.setup_vig_igc = NULL;
  1051. }
  1052. if (c->cap->sblk->igc_blk[0].version ==
  1053. (SDE_COLOR_PROCESS_VER(0x6, 0x0))) {
  1054. ret = reg_dmav1_init_sspp_op_v4(SDE_SSPP_VIG_IGC,
  1055. c->idx);
  1056. if (!ret)
  1057. c->ops.setup_vig_igc =
  1058. reg_dmav1_setup_vig_igcv6;
  1059. else
  1060. c->ops.setup_vig_igc = NULL;
  1061. }
  1062. }
  1063. if (test_bit(SDE_SSPP_DMA_IGC, &features)) {
  1064. if (c->cap->sblk->igc_blk[0].version ==
  1065. (SDE_COLOR_PROCESS_VER(0x5, 0x0))) {
  1066. ret = reg_dmav1_init_sspp_op_v4(SDE_SSPP_DMA_IGC,
  1067. c->idx);
  1068. if (!ret)
  1069. c->ops.setup_dma_igc =
  1070. reg_dmav1_setup_dma_igcv5;
  1071. else
  1072. c->ops.setup_dma_igc = NULL;
  1073. }
  1074. }
  1075. if (test_bit(SDE_SSPP_DMA_GC, &features)) {
  1076. if (c->cap->sblk->gc_blk[0].version ==
  1077. (SDE_COLOR_PROCESS_VER(0x5, 0x0))) {
  1078. ret = reg_dmav1_init_sspp_op_v4(SDE_SSPP_DMA_GC,
  1079. c->idx);
  1080. if (!ret)
  1081. c->ops.setup_dma_gc =
  1082. reg_dmav1_setup_dma_gcv5;
  1083. else
  1084. c->ops.setup_dma_gc = NULL;
  1085. }
  1086. }
  1087. if (test_bit(SDE_SSPP_FP16_IGC, &features) &&
  1088. IS_SDE_CP_VER_1_0(c->cap->sblk->fp16_igc_blk[0].version))
  1089. c->ops.setup_fp16_igc = sde_setup_fp16_igcv1;
  1090. if (test_bit(SDE_SSPP_FP16_GC, &features) &&
  1091. IS_SDE_CP_VER_1_0(c->cap->sblk->fp16_gc_blk[0].version))
  1092. c->ops.setup_fp16_gc = sde_setup_fp16_gcv1;
  1093. if (test_bit(SDE_SSPP_FP16_CSC, &features) &&
  1094. IS_SDE_CP_VER_1_0(c->cap->sblk->fp16_csc_blk[0].version))
  1095. c->ops.setup_fp16_csc = sde_setup_fp16_cscv1;
  1096. if (test_bit(SDE_SSPP_FP16_UNMULT, &features) &&
  1097. IS_SDE_CP_VER_1_0(c->cap->sblk->fp16_unmult_blk[0].version))
  1098. c->ops.setup_fp16_unmult = sde_setup_fp16_unmultv1;
  1099. }
  1100. static void sde_hw_sspp_setup_inverse_pma(struct sde_hw_pipe *ctx,
  1101. enum sde_sspp_multirect_index index, u32 enable)
  1102. {
  1103. u32 op_mode = 0;
  1104. u32 offset;
  1105. if (!ctx || (index == SDE_SSPP_RECT_1))
  1106. return;
  1107. offset = ctx->cap->sblk->unmult_offset[0];
  1108. if (enable)
  1109. op_mode |= BIT(0);
  1110. SDE_REG_WRITE(&ctx->hw, offset, op_mode);
  1111. }
  1112. static void sde_hw_sspp_setup_dgm_inverse_pma(struct sde_hw_pipe *ctx,
  1113. enum sde_sspp_multirect_index index, u32 enable)
  1114. {
  1115. u32 offset;
  1116. u32 op_mode = 0;
  1117. if (!ctx)
  1118. return;
  1119. if (index == SDE_SSPP_RECT_1)
  1120. offset = ctx->cap->sblk->unmult_offset[1];
  1121. else
  1122. offset = ctx->cap->sblk->unmult_offset[0];
  1123. op_mode = SDE_REG_READ(&ctx->hw, offset);
  1124. if (enable)
  1125. op_mode |= BIT(0);
  1126. else
  1127. op_mode &= ~BIT(0);
  1128. SDE_REG_WRITE(&ctx->hw, offset, op_mode);
  1129. }
  1130. static void sde_hw_sspp_setup_dgm_csc(struct sde_hw_pipe *ctx,
  1131. enum sde_sspp_multirect_index index, struct sde_csc_cfg *data)
  1132. {
  1133. u32 idx = 0;
  1134. u32 offset;
  1135. u32 op_mode = 0;
  1136. const struct sde_sspp_sub_blks *sblk;
  1137. if (!ctx || !ctx->cap || !ctx->cap->sblk)
  1138. return;
  1139. sblk = ctx->cap->sblk;
  1140. if (index == SDE_SSPP_RECT_1)
  1141. idx = 1;
  1142. offset = sblk->dgm_csc_blk[idx].base;
  1143. if (data) {
  1144. op_mode |= BIT(0);
  1145. sde_hw_csc_matrix_coeff_setup(&ctx->hw,
  1146. offset + CSC_10BIT_OFFSET, data, DGM_CSC_MATRIX_SHIFT);
  1147. }
  1148. SDE_REG_WRITE(&ctx->hw, offset, op_mode);
  1149. }
  1150. static bool sde_hw_sspp_setup_clk_force_ctrl(struct sde_hw_blk_reg_map *hw,
  1151. enum sde_clk_ctrl_type clk_ctrl, bool enable)
  1152. {
  1153. u32 reg_val, new_val;
  1154. if (!hw)
  1155. return false;
  1156. if (!SDE_CLK_CTRL_SSPP_VALID(clk_ctrl))
  1157. return false;
  1158. reg_val = SDE_REG_READ(hw, SSPP_CLK_CTRL);
  1159. if (enable)
  1160. new_val = reg_val | BIT(0);
  1161. else
  1162. new_val = reg_val & ~BIT(0);
  1163. SDE_REG_WRITE(hw, SSPP_CLK_CTRL, new_val);
  1164. wmb(); /* ensure write finished before progressing */
  1165. return !(reg_val & BIT(0));
  1166. }
  1167. static int sde_hw_sspp_get_clk_ctrl_status(struct sde_hw_blk_reg_map *hw,
  1168. enum sde_clk_ctrl_type clk_ctrl, bool *status)
  1169. {
  1170. if (!hw)
  1171. return -EINVAL;
  1172. if (!SDE_CLK_CTRL_SSPP_VALID(clk_ctrl))
  1173. return -EINVAL;
  1174. *status = SDE_REG_READ(hw, SSPP_CLK_STATUS) & BIT(0);
  1175. return 0;
  1176. }
  1177. static void _setup_layer_ops(struct sde_hw_pipe *c,
  1178. unsigned long features, unsigned long perf_features,
  1179. bool is_virtual_pipe)
  1180. {
  1181. int ret;
  1182. if (test_bit(SDE_SSPP_SRC, &features)) {
  1183. c->ops.setup_format = sde_hw_sspp_setup_format;
  1184. c->ops.setup_rects = sde_hw_sspp_setup_rects;
  1185. c->ops.setup_sourceaddress = sde_hw_sspp_setup_sourceaddress;
  1186. c->ops.get_sourceaddress = sde_hw_sspp_get_source_addr;
  1187. c->ops.setup_solidfill = sde_hw_sspp_setup_solidfill;
  1188. c->ops.setup_pe = sde_hw_sspp_setup_pe_config;
  1189. c->ops.setup_secure_address = sde_hw_sspp_setup_secure;
  1190. c->ops.set_src_split_order = sde_hw_sspp_set_src_split_order;
  1191. }
  1192. if (test_bit(SDE_SSPP_EXCL_RECT, &features))
  1193. c->ops.setup_excl_rect = _sde_hw_sspp_setup_excl_rect;
  1194. if (test_bit(SDE_PERF_SSPP_QOS, &features)) {
  1195. c->ops.setup_qos_lut =
  1196. sde_hw_sspp_setup_qos_lut;
  1197. c->ops.setup_qos_ctrl = sde_hw_sspp_setup_qos_ctrl;
  1198. }
  1199. if (test_bit(SDE_PERF_SSPP_TS_PREFILL, &perf_features))
  1200. c->ops.setup_ts_prefill = sde_hw_sspp_setup_ts_prefill;
  1201. if (test_bit(SDE_SSPP_CSC, &features) ||
  1202. test_bit(SDE_SSPP_CSC_10BIT, &features))
  1203. c->ops.setup_csc = sde_hw_sspp_setup_csc;
  1204. if (test_bit(SDE_SSPP_DGM_CSC, &features))
  1205. c->ops.setup_dgm_csc = sde_hw_sspp_setup_dgm_csc;
  1206. if (test_bit(SDE_SSPP_SCALER_QSEED2, &features)) {
  1207. c->ops.setup_sharpening = sde_hw_sspp_setup_sharpening;
  1208. c->ops.setup_scaler = _sde_hw_sspp_setup_scaler;
  1209. }
  1210. if (sde_hw_sspp_multirect_enabled(c->cap))
  1211. c->ops.update_multirect = sde_hw_sspp_update_multirect;
  1212. if (test_bit(SDE_SSPP_SCALER_QSEED3, &features) ||
  1213. test_bit(SDE_SSPP_SCALER_QSEED3LITE, &features)) {
  1214. c->ops.setup_scaler = _sde_hw_sspp_setup_scaler3;
  1215. c->ops.setup_scaler_lut = is_qseed3_rev_qseed3lite(
  1216. c->catalog) ? reg_dmav1_setup_scaler3lite_lut
  1217. : reg_dmav1_setup_scaler3_lut;
  1218. ret = reg_dmav1_init_sspp_op_v4(is_qseed3_rev_qseed3lite(
  1219. c->catalog) ? SDE_SSPP_SCALER_QSEED3LITE
  1220. : SDE_SSPP_SCALER_QSEED3, c->idx);
  1221. if (!ret)
  1222. c->ops.setup_scaler = reg_dmav1_setup_vig_qseed3;
  1223. }
  1224. if (test_bit(SDE_SSPP_MULTIRECT_ERROR, &features)) {
  1225. c->ops.get_meta_error = sde_hw_sspp_get_meta_error;
  1226. c->ops.clear_meta_error = sde_hw_sspp_clear_meta_error;
  1227. c->ops.get_ubwc_error = sde_hw_sspp_get_ubwc_error_v1;
  1228. c->ops.clear_ubwc_error = sde_hw_sspp_clear_ubwc_error_v1;
  1229. } else {
  1230. c->ops.get_ubwc_error = sde_hw_sspp_get_ubwc_error;
  1231. c->ops.clear_ubwc_error = sde_hw_sspp_clear_ubwc_error;
  1232. }
  1233. if (test_bit(SDE_SSPP_PREDOWNSCALE, &features))
  1234. c->ops.setup_pre_downscale = sde_hw_sspp_setup_pre_downscale;
  1235. if (test_bit(SDE_PERF_SSPP_SYS_CACHE, &perf_features))
  1236. c->ops.setup_sys_cache = sde_hw_sspp_setup_sys_cache;
  1237. if (test_bit(SDE_PERF_SSPP_CDP, &perf_features))
  1238. c->ops.setup_cdp = sde_hw_sspp_setup_cdp;
  1239. if (test_bit(SDE_PERF_SSPP_UIDLE, &perf_features))
  1240. c->ops.setup_uidle = sde_hw_sspp_setup_uidle;
  1241. _setup_layer_ops_colorproc(c, features, is_virtual_pipe);
  1242. if (test_bit(SDE_SSPP_DGM_INVERSE_PMA, &features))
  1243. c->ops.setup_inverse_pma = sde_hw_sspp_setup_dgm_inverse_pma;
  1244. else if (test_bit(SDE_SSPP_INVERSE_PMA, &features))
  1245. c->ops.setup_inverse_pma = sde_hw_sspp_setup_inverse_pma;
  1246. if (test_bit(SDE_SSPP_UBWC_STATS, &features)) {
  1247. c->ops.set_ubwc_stats_roi = sde_hw_sspp_ubwc_stats_set_roi;
  1248. c->ops.get_ubwc_stats_data = sde_hw_sspp_ubwc_stats_get_data;
  1249. }
  1250. }
  1251. static struct sde_sspp_cfg *_sspp_offset(enum sde_sspp sspp,
  1252. void __iomem *addr,
  1253. struct sde_mdss_cfg *catalog,
  1254. struct sde_hw_blk_reg_map *b)
  1255. {
  1256. int i;
  1257. struct sde_sspp_cfg *cfg;
  1258. if ((sspp < SSPP_MAX) && catalog && addr && b) {
  1259. for (i = 0; i < catalog->sspp_count; i++) {
  1260. if (sspp == catalog->sspp[i].id) {
  1261. b->base_off = addr;
  1262. b->blk_off = catalog->sspp[i].base;
  1263. b->length = catalog->sspp[i].len;
  1264. b->hw_rev = catalog->hw_rev;
  1265. b->log_mask = SDE_DBG_MASK_SSPP;
  1266. /* Only shallow copy is needed */
  1267. cfg = kmemdup(&catalog->sspp[i], sizeof(*cfg),
  1268. GFP_KERNEL);
  1269. if (!cfg)
  1270. return ERR_PTR(-ENOMEM);
  1271. return cfg;
  1272. }
  1273. }
  1274. }
  1275. return ERR_PTR(-ENOMEM);
  1276. }
  1277. struct sde_hw_pipe *sde_hw_sspp_init(enum sde_sspp idx,
  1278. void __iomem *addr, struct sde_mdss_cfg *catalog,
  1279. bool is_virtual_pipe, struct sde_vbif_clk_client *clk_client)
  1280. {
  1281. struct sde_hw_pipe *hw_pipe;
  1282. struct sde_sspp_cfg *cfg;
  1283. if (!addr || !catalog)
  1284. return ERR_PTR(-EINVAL);
  1285. hw_pipe = kzalloc(sizeof(*hw_pipe), GFP_KERNEL);
  1286. if (!hw_pipe)
  1287. return ERR_PTR(-ENOMEM);
  1288. cfg = _sspp_offset(idx, addr, catalog, &hw_pipe->hw);
  1289. if (IS_ERR_OR_NULL(cfg)) {
  1290. kfree(hw_pipe);
  1291. return ERR_PTR(-EINVAL);
  1292. }
  1293. /* Assign ops */
  1294. hw_pipe->catalog = catalog;
  1295. hw_pipe->mdp = &catalog->mdp[0];
  1296. hw_pipe->idx = idx;
  1297. hw_pipe->cap = cfg;
  1298. _setup_layer_ops(hw_pipe, hw_pipe->cap->features,
  1299. hw_pipe->cap->perf_features, is_virtual_pipe);
  1300. if (catalog->qseed_hw_rev)
  1301. sde_init_scaler_blk(&hw_pipe->cap->sblk->scaler_blk,
  1302. catalog->qseed_hw_rev);
  1303. if (!is_virtual_pipe) {
  1304. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name,
  1305. hw_pipe->hw.blk_off,
  1306. hw_pipe->hw.blk_off + hw_pipe->hw.length,
  1307. hw_pipe->hw.xin_id);
  1308. if (test_bit(SDE_SSPP_DGM_CSC, &hw_pipe->cap->features)) {
  1309. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, "CSC_0",
  1310. hw_pipe->hw.blk_off + SSPP_DGM_CSC_0,
  1311. hw_pipe->hw.blk_off + SSPP_DGM_CSC_0 + SSPP_DGM_CSC_SIZE,
  1312. hw_pipe->hw.xin_id);
  1313. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, "CSC_1",
  1314. hw_pipe->hw.blk_off + SSPP_DGM_CSC_1,
  1315. hw_pipe->hw.blk_off + SSPP_DGM_CSC_1 + SSPP_DGM_CSC_SIZE,
  1316. hw_pipe->hw.xin_id);
  1317. }
  1318. if (test_bit(SDE_SSPP_DMA_IGC, &hw_pipe->cap->features)) {
  1319. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, "DGM_0",
  1320. hw_pipe->hw.blk_off + SSPP_DGM_0,
  1321. hw_pipe->hw.blk_off + SSPP_DGM_0 + SSPP_DGM_SIZE,
  1322. hw_pipe->hw.xin_id);
  1323. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, "DGM_1",
  1324. hw_pipe->hw.blk_off + SSPP_DGM_1,
  1325. hw_pipe->hw.blk_off + SSPP_DGM_1 + SSPP_DGM_SIZE,
  1326. hw_pipe->hw.xin_id);
  1327. }
  1328. if (test_bit(SDE_SSPP_VIG_GAMUT, &hw_pipe->cap->features)) {
  1329. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->sblk->gamut_blk.name,
  1330. hw_pipe->hw.blk_off + cfg->sblk->gamut_blk.base,
  1331. hw_pipe->hw.blk_off + cfg->sblk->gamut_blk.base + VIG_GAMUT_SIZE,
  1332. hw_pipe->hw.xin_id);
  1333. }
  1334. }
  1335. if (cfg->sblk->scaler_blk.len && !is_virtual_pipe)
  1336. sde_dbg_reg_register_dump_range(SDE_DBG_NAME,
  1337. cfg->sblk->scaler_blk.name,
  1338. hw_pipe->hw.blk_off + cfg->sblk->scaler_blk.base,
  1339. hw_pipe->hw.blk_off + cfg->sblk->scaler_blk.base +
  1340. cfg->sblk->scaler_blk.len,
  1341. hw_pipe->hw.xin_id);
  1342. if (test_bit(SDE_FEATURE_VBIF_CLK_SPLIT, catalog->features)) {
  1343. if (SDE_CLK_CTRL_SSPP_VALID(cfg->clk_ctrl)) {
  1344. clk_client->hw = &hw_pipe->hw;
  1345. clk_client->clk_ctrl = cfg->clk_ctrl;
  1346. clk_client->ops.get_clk_ctrl_status = sde_hw_sspp_get_clk_ctrl_status;
  1347. clk_client->ops.setup_clk_force_ctrl = sde_hw_sspp_setup_clk_force_ctrl;
  1348. } else {
  1349. SDE_ERROR("invalid sspp clk ctrl type %d\n", cfg->clk_ctrl);
  1350. }
  1351. }
  1352. return hw_pipe;
  1353. }
  1354. void sde_hw_sspp_destroy(struct sde_hw_pipe *ctx)
  1355. {
  1356. if (ctx) {
  1357. reg_dmav1_deinit_sspp_ops(ctx->idx);
  1358. kfree(ctx->cap);
  1359. }
  1360. kfree(ctx);
  1361. }