sde_encoder_phys.h 31 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #ifndef __SDE_ENCODER_PHYS_H__
  7. #define __SDE_ENCODER_PHYS_H__
  8. #include <linux/jiffies.h>
  9. #include <linux/sde_rsc.h>
  10. #include "sde_kms.h"
  11. #include "sde_hw_intf.h"
  12. #include "sde_hw_pingpong.h"
  13. #include "sde_hw_ctl.h"
  14. #include "sde_hw_top.h"
  15. #include "sde_hw_wb.h"
  16. #include "sde_hw_cdm.h"
  17. #include "sde_hw_dnsc_blur.h"
  18. #include "sde_encoder.h"
  19. #include "sde_connector.h"
  20. #define SDE_ENCODER_NAME_MAX 16
  21. /* wait for at most 2 vsync for lowest refresh rate (24hz) */
  22. #define DEFAULT_KICKOFF_TIMEOUT_MS 84
  23. #define MAX_TE_PROFILE_COUNT 5
  24. /**
  25. * enum sde_enc_split_role - Role this physical encoder will play in a
  26. * split-panel configuration, where one panel is master, and others slaves.
  27. * Masters have extra responsibilities, like managing the VBLANK IRQ.
  28. * @ENC_ROLE_SOLO: This is the one and only panel. This encoder is master.
  29. * @ENC_ROLE_MASTER: This encoder is the master of a split panel config.
  30. * @ENC_ROLE_SLAVE: This encoder is not the master of a split panel config.
  31. * @ENC_ROLE_SKIP: This encoder is not participating in kickoffs
  32. */
  33. enum sde_enc_split_role {
  34. ENC_ROLE_SOLO,
  35. ENC_ROLE_MASTER,
  36. ENC_ROLE_SLAVE,
  37. ENC_ROLE_SKIP
  38. };
  39. /**
  40. * enum sde_enc_enable_state - current enabled state of the physical encoder
  41. * @SDE_ENC_DISABLING: Encoder transitioning to disable state
  42. * Events bounding transition are encoder type specific
  43. * @SDE_ENC_DISABLED: Encoder is disabled
  44. * @SDE_ENC_ENABLING: Encoder transitioning to enabled
  45. * Events bounding transition are encoder type specific
  46. * @SDE_ENC_ENABLED: Encoder is enabled
  47. * @SDE_ENC_ERR_NEEDS_HW_RESET: Encoder is enabled, but requires a hw_reset
  48. * to recover from a previous error
  49. */
  50. enum sde_enc_enable_state {
  51. SDE_ENC_DISABLING,
  52. SDE_ENC_DISABLED,
  53. SDE_ENC_ENABLING,
  54. SDE_ENC_ENABLED,
  55. SDE_ENC_ERR_NEEDS_HW_RESET
  56. };
  57. struct sde_encoder_phys;
  58. /**
  59. * struct sde_encoder_virt_ops - Interface the containing virtual encoder
  60. * provides for the physical encoders to use to callback.
  61. * @handle_vblank_virt: Notify virtual encoder of vblank IRQ reception
  62. * Note: This is called from IRQ handler context.
  63. * @handle_underrun_virt: Notify virtual encoder of underrun IRQ reception
  64. * Note: This is called from IRQ handler context.
  65. * @handle_frame_done: Notify virtual encoder that this phys encoder
  66. * completes last request frame.
  67. * @get_qsync_fps: Returns the min fps for the qsync feature.
  68. */
  69. struct sde_encoder_virt_ops {
  70. void (*handle_vblank_virt)(struct drm_encoder *parent,
  71. struct sde_encoder_phys *phys);
  72. void (*handle_underrun_virt)(struct drm_encoder *parent,
  73. struct sde_encoder_phys *phys);
  74. void (*handle_frame_done)(struct drm_encoder *parent,
  75. struct sde_encoder_phys *phys, u32 event);
  76. void (*get_qsync_fps)(struct drm_encoder *parent,
  77. u32 *qsync_fps, struct drm_connector_state *conn_state);
  78. };
  79. /**
  80. * struct sde_encoder_phys_ops - Interface the physical encoders provide to
  81. * the containing virtual encoder.
  82. * @late_register: DRM Call. Add Userspace interfaces, debugfs.
  83. * @prepare_commit: MSM Atomic Call, start of atomic commit sequence
  84. * @is_master: Whether this phys_enc is the current master
  85. * encoder. Can be switched at enable time. Based
  86. * on split_role and current mode (CMD/VID).
  87. * @mode_fixup: DRM Call. Fixup a DRM mode.
  88. * @cont_splash_mode_set: mode set with specific HW resources during
  89. * cont splash enabled state.
  90. * @mode_set: DRM Call. Set a DRM mode.
  91. * This likely caches the mode, for use at enable.
  92. * @enable: DRM Call. Enable a DRM mode.
  93. * @disable: DRM Call. Disable mode.
  94. * @atomic_check: DRM Call. Atomic check new DRM state.
  95. * @destroy: DRM Call. Destroy and release resources.
  96. * @get_hw_resources: Populate the structure with the hardware
  97. * resources that this phys_enc is using.
  98. * Expect no overlap between phys_encs.
  99. * @control_vblank_irq Register/Deregister for VBLANK IRQ
  100. * @wait_for_commit_done: Wait for hardware to have flushed the
  101. * current pending frames to hardware
  102. * @wait_for_tx_complete: Wait for hardware to transfer the pixels
  103. * to the panel
  104. * @wait_for_vblank: Wait for VBLANK, for sub-driver internal use
  105. * @prepare_for_kickoff: Do any work necessary prior to a kickoff
  106. * For CMD encoder, may wait for previous tx done
  107. * @handle_post_kickoff: Do any work necessary post-kickoff work
  108. * @trigger_flush: Process flush event on physical encoder
  109. * @trigger_start: Process start event on physical encoder
  110. * @needs_single_flush: Whether encoder slaves need to be flushed
  111. * @setup_misr: Sets up MISR, enable and disables based on sysfs
  112. * @collect_misr: Collects MISR data on frame update
  113. * @hw_reset: Issue HW recovery such as CTL reset and clear
  114. * SDE_ENC_ERR_NEEDS_HW_RESET state
  115. * @irq_control: Handler to enable/disable all the encoder IRQs
  116. * @update_split_role: Update the split role of the phys enc
  117. * @control_te: Interface to control the vsync_enable status
  118. * @restore: Restore all the encoder configs.
  119. * @is_autorefresh_enabled: provides the autorefresh current
  120. * enable/disable state.
  121. * @get_line_count: Obtain current internal vertical line count
  122. * @wait_dma_trigger: Returns true if lut dma has to trigger and wait
  123. * unitl transaction is complete.
  124. * @wait_for_active: Wait for display scan line to be in active area
  125. * @setup_vsync_source: Configure vsync source selection for cmd mode.
  126. * @get_underrun_line_count: Obtain and log current internal vertical line
  127. * count and underrun line count
  128. * @add_to_minidump: Add this phys_enc data to minidumps
  129. */
  130. struct sde_encoder_phys_ops {
  131. int (*late_register)(struct sde_encoder_phys *encoder,
  132. struct dentry *debugfs_root);
  133. void (*prepare_commit)(struct sde_encoder_phys *encoder);
  134. bool (*is_master)(struct sde_encoder_phys *encoder);
  135. bool (*mode_fixup)(struct sde_encoder_phys *encoder,
  136. const struct drm_display_mode *mode,
  137. struct drm_display_mode *adjusted_mode);
  138. void (*mode_set)(struct sde_encoder_phys *encoder,
  139. struct drm_display_mode *mode,
  140. struct drm_display_mode *adjusted_mode);
  141. void (*cont_splash_mode_set)(struct sde_encoder_phys *encoder,
  142. struct drm_display_mode *adjusted_mode);
  143. void (*enable)(struct sde_encoder_phys *encoder);
  144. void (*disable)(struct sde_encoder_phys *encoder);
  145. int (*atomic_check)(struct sde_encoder_phys *encoder,
  146. struct drm_crtc_state *crtc_state,
  147. struct drm_connector_state *conn_state);
  148. void (*destroy)(struct sde_encoder_phys *encoder);
  149. void (*get_hw_resources)(struct sde_encoder_phys *encoder,
  150. struct sde_encoder_hw_resources *hw_res,
  151. struct drm_connector_state *conn_state);
  152. int (*control_vblank_irq)(struct sde_encoder_phys *enc, bool enable);
  153. int (*wait_for_commit_done)(struct sde_encoder_phys *phys_enc);
  154. int (*wait_for_tx_complete)(struct sde_encoder_phys *phys_enc);
  155. int (*wait_for_vblank)(struct sde_encoder_phys *phys_enc);
  156. int (*prepare_for_kickoff)(struct sde_encoder_phys *phys_enc,
  157. struct sde_encoder_kickoff_params *params);
  158. void (*handle_post_kickoff)(struct sde_encoder_phys *phys_enc);
  159. void (*trigger_flush)(struct sde_encoder_phys *phys_enc);
  160. void (*trigger_start)(struct sde_encoder_phys *phys_enc);
  161. bool (*needs_single_flush)(struct sde_encoder_phys *phys_enc);
  162. void (*setup_misr)(struct sde_encoder_phys *phys_encs,
  163. bool enable, u32 frame_count);
  164. int (*collect_misr)(struct sde_encoder_phys *phys_enc, bool nonblock,
  165. u32 *misr_value);
  166. void (*hw_reset)(struct sde_encoder_phys *phys_enc);
  167. void (*irq_control)(struct sde_encoder_phys *phys, bool enable);
  168. void (*update_split_role)(struct sde_encoder_phys *phys_enc,
  169. enum sde_enc_split_role role);
  170. void (*control_te)(struct sde_encoder_phys *phys_enc, bool enable);
  171. void (*restore)(struct sde_encoder_phys *phys);
  172. bool (*is_autorefresh_enabled)(struct sde_encoder_phys *phys);
  173. int (*get_line_count)(struct sde_encoder_phys *phys);
  174. bool (*wait_dma_trigger)(struct sde_encoder_phys *phys);
  175. int (*wait_for_active)(struct sde_encoder_phys *phys);
  176. void (*setup_vsync_source)(struct sde_encoder_phys *phys, u32 vsync_source,
  177. struct msm_display_info *disp_info);
  178. u32 (*get_underrun_line_count)(struct sde_encoder_phys *phys);
  179. void (*add_to_minidump)(struct sde_encoder_phys *phys);
  180. };
  181. /**
  182. * enum sde_intr_idx - sde encoder interrupt index
  183. * @INTR_IDX_VSYNC: Vsync interrupt for video mode panel
  184. * @INTR_IDX_PINGPONG: Pingpong done interrupt for cmd mode panel
  185. * @INTR_IDX_UNDERRUN: Underrun interrupt for video and cmd mode panel
  186. * @INTR_IDX_CTL_START:Control start interrupt to indicate the frame start
  187. * @INTR_IDX_CTL_DONE: Control done interrupt indicating the control path being idle
  188. * @INTR_IDX_RDPTR: Readpointer done interrupt for cmd mode panel
  189. * @INTR_IDX_WB_DONE: Writeback done interrupt for WB
  190. * @INTR_IDX_PP1_OVFL: Pingpong overflow interrupt on PP1 for Concurrent WB
  191. * @INTR_IDX_PP2_OVFL: Pingpong overflow interrupt on PP2 for Concurrent WB
  192. * @INTR_IDX_PP3_OVFL: Pingpong overflow interrupt on PP3 for Concurrent WB
  193. * @INTR_IDX_PP4_OVFL: Pingpong overflow interrupt on PP4 for Concurrent WB
  194. * @INTR_IDX_PP5_OVFL: Pingpong overflow interrupt on PP5 for Concurrent WB
  195. * @INTR_IDX_PP_CWB_OVFL: Pingpong overflow interrupt on PP_CWB0/1 for Concurrent WB
  196. * @INTR_IDX_AUTOREFRESH_DONE: Autorefresh done for cmd mode panel meaning
  197. * autorefresh has triggered a double buffer flip
  198. * @INTR_IDX_WRPTR: Writepointer start interrupt for cmd mode panel
  199. * @INTR_IDX_WB_LINEPTR: Programmable lineptr interrupt for WB
  200. */
  201. enum sde_intr_idx {
  202. INTR_IDX_VSYNC,
  203. INTR_IDX_PINGPONG,
  204. INTR_IDX_UNDERRUN,
  205. INTR_IDX_CTL_START,
  206. INTR_IDX_CTL_DONE,
  207. INTR_IDX_RDPTR,
  208. INTR_IDX_AUTOREFRESH_DONE,
  209. INTR_IDX_WB_DONE,
  210. INTR_IDX_PP1_OVFL,
  211. INTR_IDX_PP2_OVFL,
  212. INTR_IDX_PP3_OVFL,
  213. INTR_IDX_PP4_OVFL,
  214. INTR_IDX_PP5_OVFL,
  215. INTR_IDX_PP_CWB_OVFL,
  216. INTR_IDX_WRPTR,
  217. INTR_IDX_WB_LINEPTR,
  218. INTR_IDX_MAX,
  219. };
  220. /**
  221. * sde_encoder_irq - tracking structure for interrupts
  222. * @name: string name of interrupt
  223. * @intr_type: Encoder interrupt type
  224. * @intr_idx: Encoder interrupt enumeration
  225. * @hw_idx: HW Block ID
  226. * @irq_idx: IRQ interface lookup index from SDE IRQ framework
  227. * will be -EINVAL if IRQ is not registered
  228. * @irq_cb: interrupt callback
  229. */
  230. struct sde_encoder_irq {
  231. const char *name;
  232. enum sde_intr_type intr_type;
  233. enum sde_intr_idx intr_idx;
  234. int hw_idx;
  235. int irq_idx;
  236. struct sde_irq_callback cb;
  237. };
  238. /**
  239. * struct sde_encoder_phys - physical encoder that drives a single INTF block
  240. * tied to a specific panel / sub-panel. Abstract type, sub-classed by
  241. * phys_vid or phys_cmd for video mode or command mode encs respectively.
  242. * @parent: Pointer to the containing virtual encoder
  243. * @connector: If a mode is set, cached pointer to the active connector
  244. * @ops: Operations exposed to the virtual encoder
  245. * @parent_ops: Callbacks exposed by the parent to the phys_enc
  246. * @hw_mdptop: Hardware interface to the top registers
  247. * @hw_ctl: Hardware interface to the ctl registers
  248. * @hw_intf: Hardware interface to INTF registers
  249. * @hw_cdm: Hardware interface to the cdm registers
  250. * @hw_qdss: Hardware interface to the qdss registers
  251. * @cdm_cfg: Chroma-down hardware configuration
  252. * @hw_pp: Hardware interface to the ping pong registers
  253. * @hw_dnsc_blur: Hardware interface to the downscale blur registers
  254. * @sde_kms: Pointer to the sde_kms top level
  255. * @cached_mode: DRM mode cached at mode_set time, acted on in enable
  256. * @enabled: Whether the encoder has enabled and running a mode
  257. * @split_role: Role to play in a split-panel configuration
  258. * @intf_mode: Interface mode
  259. * @intf_idx: Interface index on sde hardware
  260. * @intf_cfg: Interface hardware configuration
  261. * @intf_cfg_v1: Interface hardware configuration to be used if control
  262. * path supports SDE_CTL_ACTIVE_CFG
  263. * @comp_type: Type of compression supported
  264. * @comp_ratio: Compression ratio
  265. * @dsc_extra_pclk_cycle_cnt: Extra pclk cycle count for DSC over DP
  266. * @dsc_extra_disp_width: Additional display width for DSC over DP
  267. * @poms_align_vsync: poms with vsync aligned
  268. * @dce_bytes_per_line: Compressed bytes per line
  269. * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
  270. * @enable_state: Enable state tracking
  271. * @vblank_refcount: Reference count of vblank request
  272. * @wbirq_refcount: Reference count of wb irq request
  273. * @vsync_cnt: Vsync count for the physical encoder
  274. * @last_vsync_timestamp: store last vsync timestamp
  275. * @underrun_cnt: Underrun count for the physical encoder
  276. * @pending_kickoff_cnt: Atomic counter tracking the number of kickoffs
  277. * vs. the number of done/vblank irqs. Should hover
  278. * between 0-2 Incremented when a new kickoff is
  279. * scheduled. Decremented in irq handler
  280. * @pending_retire_fence_cnt: Atomic counter tracking the pending retire
  281. * fences that have to be signalled.
  282. * @pending_ctl_start_cnt: Atomic counter tracking the pending ctl-start-irq,
  283. * used to release commit thread. Currently managed
  284. * only for writeback encoder and the counter keeps
  285. * increasing for other type of encoders.
  286. * @pending_kickoff_wq: Wait queue for blocking until kickoff completes
  287. * @kickoff_timeout_ms: kickoff timeout in mill seconds
  288. * @irq: IRQ tracking structures
  289. * @has_intf_te: Interface TE configuration support
  290. * @cont_splash_enabled: Variable to store continuous splash settings.
  291. * @in_clone_mode Indicates if encoder is in clone mode ref@CWB
  292. * @vfp_cached: cached vertical front porch to be used for
  293. * programming ROT and MDP fetch start
  294. * @frame_trigger_mode: frame trigger mode indication for command
  295. * mode display
  296. * @recovered: flag set to true when recovered from pp timeout
  297. */
  298. struct sde_encoder_phys {
  299. struct drm_encoder *parent;
  300. struct drm_connector *connector;
  301. struct sde_encoder_phys_ops ops;
  302. struct sde_encoder_virt_ops parent_ops;
  303. struct sde_hw_mdp *hw_mdptop;
  304. struct sde_hw_ctl *hw_ctl;
  305. struct sde_hw_intf *hw_intf;
  306. struct sde_hw_cdm *hw_cdm;
  307. struct sde_hw_qdss *hw_qdss;
  308. struct sde_hw_cdm_cfg cdm_cfg;
  309. struct sde_hw_pingpong *hw_pp;
  310. struct sde_hw_dnsc_blur *hw_dnsc_blur;
  311. struct sde_kms *sde_kms;
  312. struct drm_display_mode cached_mode;
  313. enum sde_enc_split_role split_role;
  314. enum sde_intf_mode intf_mode;
  315. enum sde_intf intf_idx;
  316. struct sde_hw_intf_cfg intf_cfg;
  317. struct sde_hw_intf_cfg_v1 intf_cfg_v1;
  318. enum msm_display_compression_type comp_type;
  319. u32 comp_ratio;
  320. u32 dsc_extra_pclk_cycle_cnt;
  321. u32 dsc_extra_disp_width;
  322. bool poms_align_vsync;
  323. u32 dce_bytes_per_line;
  324. spinlock_t *enc_spinlock;
  325. enum sde_enc_enable_state enable_state;
  326. struct mutex *vblank_ctl_lock;
  327. atomic_t vblank_refcount;
  328. atomic_t wbirq_refcount;
  329. atomic_t vsync_cnt;
  330. ktime_t last_vsync_timestamp;
  331. atomic_t underrun_cnt;
  332. atomic_t pending_kickoff_cnt;
  333. atomic_t pending_retire_fence_cnt;
  334. atomic_t pending_ctl_start_cnt;
  335. wait_queue_head_t pending_kickoff_wq;
  336. u32 kickoff_timeout_ms;
  337. struct sde_encoder_irq irq[INTR_IDX_MAX];
  338. bool has_intf_te;
  339. bool cont_splash_enabled;
  340. bool in_clone_mode;
  341. int vfp_cached;
  342. enum frame_trigger_mode_type frame_trigger_mode;
  343. bool recovered;
  344. };
  345. static inline int sde_encoder_phys_inc_pending(struct sde_encoder_phys *phys)
  346. {
  347. return atomic_inc_return(&phys->pending_kickoff_cnt);
  348. }
  349. /**
  350. * struct sde_encoder_phys_vid - sub-class of sde_encoder_phys to handle video
  351. * mode specific operations
  352. * @base: Baseclass physical encoder structure
  353. * @timing_params: Current timing parameter
  354. * @error_count: Number of consecutive kickoffs that experienced an error
  355. */
  356. struct sde_encoder_phys_vid {
  357. struct sde_encoder_phys base;
  358. struct intf_timing_params timing_params;
  359. int error_count;
  360. };
  361. /**
  362. * struct sde_encoder_phys_cmd_autorefresh - autorefresh state tracking
  363. * @cfg: current active autorefresh configuration
  364. * @kickoff_cnt: atomic count tracking autorefresh done irq kickoffs pending
  365. * @kickoff_wq: wait queue for waiting on autorefresh done irq
  366. */
  367. struct sde_encoder_phys_cmd_autorefresh {
  368. struct sde_hw_autorefresh cfg;
  369. atomic_t kickoff_cnt;
  370. wait_queue_head_t kickoff_wq;
  371. };
  372. /**
  373. * struct sde_encoder_phys_cmd_te_timestamp - list node to keep track of
  374. * rd_ptr/TE timestamp
  375. * @list: list node
  376. * @timestamp: TE timestamp
  377. */
  378. struct sde_encoder_phys_cmd_te_timestamp {
  379. struct list_head list;
  380. ktime_t timestamp;
  381. };
  382. /**
  383. * struct sde_encoder_phys_cmd - sub-class of sde_encoder_phys to handle command
  384. * mode specific operations
  385. * @base: Baseclass physical encoder structure
  386. * @stream_sel: Stream selection for multi-stream interfaces
  387. * @frame_tx_timeout_report_cnt: number of pp_done/ctl_done irq timeout errors
  388. * @autorefresh: autorefresh feature state
  389. * @pending_vblank_cnt: Atomic counter tracking pending wait for VBLANK
  390. * @pending_vblank_wq: Wait queue for blocking until VBLANK received
  391. * @wr_ptr_wait_success: log wr_ptr_wait success for release fence trigger
  392. * @te_timestamp_list: List head for the TE timestamp list
  393. * @te_timestamp: Array of size MAX_TE_PROFILE_COUNT te_timestamp_list elements
  394. */
  395. struct sde_encoder_phys_cmd {
  396. struct sde_encoder_phys base;
  397. int stream_sel;
  398. int frame_tx_timeout_report_cnt;
  399. struct sde_encoder_phys_cmd_autorefresh autorefresh;
  400. atomic_t pending_vblank_cnt;
  401. wait_queue_head_t pending_vblank_wq;
  402. bool wr_ptr_wait_success;
  403. struct list_head te_timestamp_list;
  404. struct sde_encoder_phys_cmd_te_timestamp
  405. te_timestamp[MAX_TE_PROFILE_COUNT];
  406. };
  407. /**
  408. * struct sde_encoder_phys_wb - sub-class of sde_encoder_phys to handle
  409. * writeback specific operations
  410. * @base: Baseclass physical encoder structure
  411. * @hw_wb: Hardware interface to the wb registers
  412. * @wbdone_timeout: Timeout value for writeback done in msec
  413. * @wb_cfg: Writeback hardware configuration
  414. * @cdp_cfg: Writeback CDP configuration
  415. * @wb_roi: Writeback region-of-interest
  416. * @wb_fmt: Writeback pixel format
  417. * @wb_fb: Pointer to current writeback framebuffer
  418. * @wb_aspace: Pointer to current writeback address space
  419. * @old_fb: Pointer to old writeback framebuffer
  420. * @old_aspace: Pointer to old writeback address space
  421. * @aspace: address space identifier for non-secure/secure domain
  422. * @wb_dev: Pointer to writeback device
  423. * @bo_disable: Buffer object(s) to use during the disabling state
  424. * @fb_disable: Frame buffer to use during the disabling state
  425. * @sc_cfg: Stores wb system cache config
  426. * @crtc Pointer to drm_crtc
  427. * @prog_line: Cached programmable line value used to trigger early wb-fence
  428. */
  429. struct sde_encoder_phys_wb {
  430. struct sde_encoder_phys base;
  431. struct sde_hw_wb *hw_wb;
  432. u32 wbdone_timeout;
  433. struct sde_hw_wb_cfg wb_cfg;
  434. struct sde_hw_wb_cdp_cfg cdp_cfg;
  435. struct sde_rect wb_roi;
  436. const struct sde_format *wb_fmt;
  437. struct drm_framebuffer *wb_fb;
  438. struct msm_gem_address_space *wb_aspace;
  439. struct drm_framebuffer *old_fb;
  440. struct msm_gem_address_space *old_aspace;
  441. struct msm_gem_address_space *aspace[SDE_IOMMU_DOMAIN_MAX];
  442. struct sde_wb_device *wb_dev;
  443. struct drm_gem_object *bo_disable[SDE_MAX_PLANES];
  444. struct drm_framebuffer *fb_disable;
  445. struct sde_hw_wb_sc_cfg sc_cfg;
  446. struct drm_crtc *crtc;
  447. u32 prog_line;
  448. };
  449. /**
  450. * struct sde_enc_phys_init_params - initialization parameters for phys encs
  451. * @sde_kms: Pointer to the sde_kms top level
  452. * @parent: Pointer to the containing virtual encoder
  453. * @parent_ops: Callbacks exposed by the parent to the phys_enc
  454. * @split_role: Role to play in a split-panel configuration
  455. * @intf_idx: Interface index this phys_enc will control
  456. * @wb_idx: Writeback index this phys_enc will control
  457. * @comp_type: Type of compression supported
  458. * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
  459. */
  460. struct sde_enc_phys_init_params {
  461. struct sde_kms *sde_kms;
  462. struct drm_encoder *parent;
  463. struct sde_encoder_virt_ops parent_ops;
  464. enum sde_enc_split_role split_role;
  465. enum sde_intf intf_idx;
  466. enum sde_wb wb_idx;
  467. enum msm_display_compression_type comp_type;
  468. spinlock_t *enc_spinlock;
  469. struct mutex *vblank_ctl_lock;
  470. };
  471. /**
  472. * sde_encoder_wait_info - container for passing arguments to irq wait functions
  473. * @wq: wait queue structure
  474. * @atomic_cnt: wait until atomic_cnt equals zero
  475. * @count_check: wait for specific atomic_cnt instead of zero.
  476. * @timeout_ms: timeout value in milliseconds
  477. */
  478. struct sde_encoder_wait_info {
  479. wait_queue_head_t *wq;
  480. atomic_t *atomic_cnt;
  481. u32 count_check;
  482. s64 timeout_ms;
  483. };
  484. /**
  485. * sde_encoder_phys_vid_init - Construct a new video mode physical encoder
  486. * @p: Pointer to init params structure
  487. * Return: Error code or newly allocated encoder
  488. */
  489. struct sde_encoder_phys *sde_encoder_phys_vid_init(
  490. struct sde_enc_phys_init_params *p);
  491. /**
  492. * sde_encoder_phys_cmd_init - Construct a new command mode physical encoder
  493. * @p: Pointer to init params structure
  494. * Return: Error code or newly allocated encoder
  495. */
  496. struct sde_encoder_phys *sde_encoder_phys_cmd_init(
  497. struct sde_enc_phys_init_params *p);
  498. /**
  499. * sde_encoder_phys_wb_init - Construct a new writeback physical encoder
  500. * @p: Pointer to init params structure
  501. * Return: Error code or newly allocated encoder
  502. */
  503. #if IS_ENABLED(CONFIG_DRM_SDE_WB)
  504. struct sde_encoder_phys *sde_encoder_phys_wb_init(
  505. struct sde_enc_phys_init_params *p);
  506. #else
  507. static inline
  508. struct sde_encoder_phys *sde_encoder_phys_wb_init(
  509. struct sde_enc_phys_init_params *p)
  510. {
  511. return NULL;
  512. }
  513. #endif /* CONFIG_DRM_SDE_WB */
  514. void sde_encoder_phys_setup_cdm(struct sde_encoder_phys *phys_enc,
  515. struct drm_framebuffer *fb, const struct sde_format *format,
  516. struct sde_rect *wb_roi);
  517. /**
  518. * sde_encoder_helper_get_pp_line_count - pingpong linecount helper function
  519. * @drm_enc: Pointer to drm encoder structure
  520. * @info: structure used to populate the pp line count information
  521. */
  522. void sde_encoder_helper_get_pp_line_count(struct drm_encoder *drm_enc,
  523. struct sde_hw_pp_vsync_info *info);
  524. /**
  525. * sde_encoder_helper_get_kickoff_timeout_ms- get the kickoff timeout value based on fps
  526. * @drm_enc: Pointer to drm encoder structure
  527. * Returns: Kickoff timeout in milli seconds
  528. */
  529. u32 sde_encoder_helper_get_kickoff_timeout_ms(struct drm_encoder *drm_enc);
  530. /**
  531. * sde_encoder_helper_trigger_flush - control flush helper function
  532. * This helper function may be optionally specified by physical
  533. * encoders if they require ctl_flush triggering.
  534. * @phys_enc: Pointer to physical encoder structure
  535. */
  536. void sde_encoder_helper_trigger_flush(struct sde_encoder_phys *phys_enc);
  537. /**
  538. * sde_encoder_helper_trigger_start - control start helper function
  539. * This helper function may be optionally specified by physical
  540. * encoders if they require ctl_start triggering.
  541. * @phys_enc: Pointer to physical encoder structure
  542. */
  543. void sde_encoder_helper_trigger_start(struct sde_encoder_phys *phys_enc);
  544. /**
  545. * sde_encoder_helper_vsync_config - configure vsync source for cmd mode
  546. * @phys_enc: Pointer to physical encoder structure
  547. * @vsync_source: vsync source selection
  548. */
  549. void sde_encoder_helper_vsync_config(struct sde_encoder_phys *phys_enc, u32 vsync_source);
  550. /**
  551. * sde_encoder_helper_wait_event_timeout - wait for event with timeout
  552. * taking into account that jiffies may jump between reads leading to
  553. * incorrectly detected timeouts. Prevent failure in this scenario by
  554. * making sure that elapsed time during wait is valid.
  555. * @drm_id: drm object id for logging
  556. * @hw_id: hw instance id for logging
  557. * @info: wait info structure
  558. */
  559. int sde_encoder_helper_wait_event_timeout(
  560. int32_t drm_id,
  561. int32_t hw_id,
  562. struct sde_encoder_wait_info *info);
  563. /*
  564. * sde_encoder_get_fps - get the allowed panel jitter in nanoseconds
  565. * @encoder: Pointer to drm encoder object
  566. */
  567. void sde_encoder_helper_get_jitter_bounds_ns(struct drm_encoder *encoder,
  568. u64 *l_bound, u64 *u_bound);
  569. /**
  570. * sde_encoder_helper_switch_vsync - switch vsync source to WD or default
  571. * @drm_enc: Pointer to drm encoder structure
  572. * @watchdog_te: switch vsync source to watchdog TE
  573. */
  574. int sde_encoder_helper_switch_vsync(struct drm_encoder *drm_enc,
  575. bool watchdog_te);
  576. /**
  577. * sde_encoder_helper_hw_reset - issue ctl hw reset
  578. * This helper function may be optionally specified by physical
  579. * encoders if they require ctl hw reset. If state is currently
  580. * SDE_ENC_ERR_NEEDS_HW_RESET, it is set back to SDE_ENC_ENABLED.
  581. * @phys_enc: Pointer to physical encoder structure
  582. */
  583. void sde_encoder_helper_hw_reset(struct sde_encoder_phys *phys_enc);
  584. static inline enum sde_3d_blend_mode sde_encoder_helper_get_3d_blend_mode(
  585. struct sde_encoder_phys *phys_enc)
  586. {
  587. struct msm_display_topology def;
  588. enum sde_enc_split_role split_role;
  589. int ret, num_lm;
  590. bool mode_3d;
  591. if (!phys_enc || phys_enc->enable_state == SDE_ENC_DISABLING ||
  592. !phys_enc->connector || !phys_enc->connector->state)
  593. return BLEND_3D_NONE;
  594. ret = sde_connector_state_get_topology
  595. (phys_enc->connector->state, &def);
  596. if (ret)
  597. return BLEND_3D_NONE;
  598. if (phys_enc->hw_intf && phys_enc->hw_intf->cfg.split_link_en)
  599. return BLEND_3D_NONE;
  600. num_lm = def.num_lm;
  601. mode_3d = (num_lm > def.num_enc) ? true : false;
  602. split_role = phys_enc->split_role;
  603. if (split_role == ENC_ROLE_SOLO && num_lm == 2 && mode_3d)
  604. return BLEND_3D_H_ROW_INT;
  605. if ((split_role == ENC_ROLE_MASTER || split_role == ENC_ROLE_SLAVE)
  606. && num_lm == 4 && mode_3d)
  607. return BLEND_3D_H_ROW_INT;
  608. return BLEND_3D_NONE;
  609. }
  610. /**
  611. * sde_encoder_phys_is_cwb_disabling - Check if CWB encoder attached to this
  612. * CRTC and it is in SDE_ENC_DISABLING state.
  613. * @phys_enc: Pointer to physical encoder structure
  614. * @crtc: drm crtc
  615. * @Return: true if cwb encoder is in disabling state
  616. */
  617. static inline bool sde_encoder_phys_is_cwb_disabling(
  618. struct sde_encoder_phys *phys, struct drm_crtc *crtc)
  619. {
  620. struct sde_encoder_phys_wb *wb_enc;
  621. if (!phys || !phys->in_clone_mode ||
  622. phys->enable_state != SDE_ENC_DISABLING)
  623. return false;
  624. wb_enc = container_of(phys, struct sde_encoder_phys_wb, base);
  625. return (wb_enc->crtc == crtc) ? true : false;
  626. }
  627. /**
  628. * sde_encoder_helper_split_config - split display configuration helper function
  629. * This helper function may be used by physical encoders to configure
  630. * the split display related registers.
  631. * @phys_enc: Pointer to physical encoder structure
  632. * @interface: enum sde_intf setting
  633. */
  634. void sde_encoder_helper_split_config(
  635. struct sde_encoder_phys *phys_enc,
  636. enum sde_intf interface);
  637. /**
  638. * sde_encoder_helper_reset_mixers - reset mixers associated with phys enc
  639. * @phys_enc: Pointer to physical encoder structure
  640. * @fb: Optional fb for specifying new mixer output resolution, may be NULL
  641. * Return: Zero on success
  642. */
  643. int sde_encoder_helper_reset_mixers(struct sde_encoder_phys *phys_enc,
  644. struct drm_framebuffer *fb);
  645. /**
  646. * sde_encoder_helper_report_irq_timeout - utility to report error that irq has
  647. * timed out, including reporting frame error event to crtc and debug dump
  648. * @phys_enc: Pointer to physical encoder structure
  649. * @intr_idx: Failing interrupt index
  650. */
  651. void sde_encoder_helper_report_irq_timeout(struct sde_encoder_phys *phys_enc,
  652. enum sde_intr_idx intr_idx);
  653. /**
  654. * sde_encoder_helper_wait_for_irq - utility to wait on an irq.
  655. * note: will call sde_encoder_helper_wait_for_irq on timeout
  656. * @phys_enc: Pointer to physical encoder structure
  657. * @intr_idx: encoder interrupt index
  658. * @wait_info: wait info struct
  659. * @Return: 0 or -ERROR
  660. */
  661. int sde_encoder_helper_wait_for_irq(struct sde_encoder_phys *phys_enc,
  662. enum sde_intr_idx intr_idx,
  663. struct sde_encoder_wait_info *wait_info);
  664. /**
  665. * sde_encoder_helper_register_irq - register and enable an irq
  666. * @phys_enc: Pointer to physical encoder structure
  667. * @intr_idx: encoder interrupt index
  668. * @Return: 0 or -ERROR
  669. */
  670. int sde_encoder_helper_register_irq(struct sde_encoder_phys *phys_enc,
  671. enum sde_intr_idx intr_idx);
  672. /**
  673. * sde_encoder_helper_unregister_irq - unregister and disable an irq
  674. * @phys_enc: Pointer to physical encoder structure
  675. * @intr_idx: encoder interrupt index
  676. * @Return: 0 or -ERROR
  677. */
  678. int sde_encoder_helper_unregister_irq(struct sde_encoder_phys *phys_enc,
  679. enum sde_intr_idx intr_idx);
  680. /**
  681. * sde_encoder_helper_update_intf_cfg - update interface configuration for
  682. * single control path.
  683. * @phys_enc: Pointer to physical encoder structure
  684. */
  685. void sde_encoder_helper_update_intf_cfg(
  686. struct sde_encoder_phys *phys_enc);
  687. /**
  688. * _sde_encoder_phys_is_dual_ctl - check if encoder needs dual ctl path.
  689. * @phys_enc: Pointer to physical encoder structure
  690. * @Return: true if dual ctl paths else false
  691. */
  692. static inline bool _sde_encoder_phys_is_dual_ctl(
  693. struct sde_encoder_phys *phys_enc)
  694. {
  695. struct sde_kms *sde_kms;
  696. enum sde_rm_topology_name topology;
  697. const struct sde_rm_topology_def* def;
  698. if (!phys_enc) {
  699. pr_err("invalid phys_enc\n");
  700. return false;
  701. }
  702. sde_kms = phys_enc->sde_kms;
  703. if (!sde_kms) {
  704. pr_err("invalid kms\n");
  705. return false;
  706. }
  707. topology = sde_connector_get_topology_name(phys_enc->connector);
  708. def = sde_rm_topology_get_topology_def(&sde_kms->rm, topology);
  709. if (IS_ERR_OR_NULL(def)) {
  710. pr_err("invalid topology\n");
  711. return false;
  712. }
  713. return (def->num_ctl == 2) ? true : false;
  714. }
  715. /**
  716. * _sde_encoder_phys_is_ppsplit - check if pp_split is enabled
  717. * @phys_enc: Pointer to physical encoder structure
  718. * @Return: true or false
  719. */
  720. static inline bool _sde_encoder_phys_is_ppsplit(
  721. struct sde_encoder_phys *phys_enc)
  722. {
  723. enum sde_rm_topology_name topology;
  724. if (!phys_enc) {
  725. pr_err("invalid phys_enc\n");
  726. return false;
  727. }
  728. topology = sde_connector_get_topology_name(phys_enc->connector);
  729. if (topology == SDE_RM_TOPOLOGY_PPSPLIT)
  730. return true;
  731. return false;
  732. }
  733. static inline bool sde_encoder_phys_needs_single_flush(
  734. struct sde_encoder_phys *phys_enc)
  735. {
  736. if (!phys_enc)
  737. return false;
  738. return (_sde_encoder_phys_is_ppsplit(phys_enc) ||
  739. !_sde_encoder_phys_is_dual_ctl(phys_enc));
  740. }
  741. /**
  742. * sde_encoder_helper_phys_disable - helper function to disable virt encoder
  743. * @phys_enc: Pointer to physical encoder structure
  744. * @wb_enc: Pointer to writeback encoder structure
  745. */
  746. void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
  747. struct sde_encoder_phys_wb *wb_enc);
  748. /**
  749. * sde_encoder_helper_phys_reset - helper function to reset virt encoder
  750. * if vsync is missing on phys encoder
  751. * @phys_enc: Pointer to physical encoder structure
  752. */
  753. void sde_encoder_helper_phys_reset(struct sde_encoder_phys *phys_enc);
  754. /**
  755. * sde_encoder_helper_setup_misr - helper function to setup misr
  756. * @phys_enc: Pointer to physical encoder structure
  757. * @enable: enable/disable flag
  758. * @frame_count: frame count for misr
  759. */
  760. void sde_encoder_helper_setup_misr(struct sde_encoder_phys *phys_enc,
  761. bool enable, u32 frame_count);
  762. /**
  763. * sde_encoder_helper_collect_misr - helper function to collect misr
  764. * @phys_enc: Pointer to physical encoder structure
  765. * @nonblock: blocking/non-blocking flag
  766. * @misr_value: pointer to misr value
  767. * @Return: zero on success
  768. */
  769. int sde_encoder_helper_collect_misr(struct sde_encoder_phys *phys_enc,
  770. bool nonblock, u32 *misr_value);
  771. #endif /* __sde_encoder_phys_H__ */