dsi_phy_hw.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #ifndef _DSI_PHY_HW_H_
  7. #define _DSI_PHY_HW_H_
  8. #include "dsi_defs.h"
  9. #include "dsi_hw.h"
  10. #define DSI_MAX_SETTINGS 8
  11. #define DSI_PHY_TIMING_V3_SIZE 12
  12. #define DSI_PHY_TIMING_V4_SIZE 14
  13. #define DSI_PHY_DBG(p, fmt, ...) DRM_DEV_DEBUG(NULL, "[msm-dsi-debug]: DSI_%d: "\
  14. fmt, p ? p->index : -1, ##__VA_ARGS__)
  15. #define DSI_PHY_ERR(p, fmt, ...) DRM_DEV_ERROR(NULL, "[msm-dsi-error]: DSI_%d: "\
  16. fmt, p ? p->index : -1, ##__VA_ARGS__)
  17. #define DSI_PHY_INFO(p, fmt, ...) DRM_DEV_INFO(NULL, "[msm-dsi-info]: DSI_%d: "\
  18. fmt, p ? p->index : -1, ##__VA_ARGS__)
  19. #define DSI_PHY_WARN(p, fmt, ...) DRM_WARN("[msm-dsi-warn]: DSI_%d: " fmt,\
  20. p ? p->index : -1, ##__VA_ARGS__)
  21. #define DSI_MISC_R32(dsi_phy_hw, off) DSI_GEN_R32((dsi_phy_hw)->phy_clamp_base, off)
  22. #define DSI_MISC_W32(dsi_phy_hw, off, val) \
  23. DSI_GEN_W32_DEBUG((dsi_phy_hw)->phy_clamp_base, (dsi_phy_hw)->index, off, val)
  24. /**
  25. * enum dsi_phy_version - DSI PHY version enumeration
  26. * @DSI_PHY_VERSION_UNKNOWN: Unknown version.
  27. * @DSI_PHY_VERSION_3_0: 10nm
  28. * @DSI_PHY_VERSION_4_0: 7nm
  29. * @DSI_PHY_VERSION_4_1: 7nm
  30. * @DSI_PHY_VERSION_4_2: 5nm
  31. * @DSI_PHY_VERSION_4_3: 5nm
  32. * @DSI_PHY_VERSION_5_2: 4nm
  33. * @DSI_PHY_VERSION_MAX:
  34. */
  35. enum dsi_phy_version {
  36. DSI_PHY_VERSION_UNKNOWN,
  37. DSI_PHY_VERSION_3_0, /* 10nm */
  38. DSI_PHY_VERSION_4_0, /* 7nm */
  39. DSI_PHY_VERSION_4_1, /* 7nm */
  40. DSI_PHY_VERSION_4_2, /* 5nm */
  41. DSI_PHY_VERSION_4_3, /* 5nm */
  42. DSI_PHY_VERSION_5_2, /* 4nm */
  43. DSI_PHY_VERSION_MAX
  44. };
  45. /**
  46. * enum dsi_pll_version - DSI PHY PLL version enumeration
  47. * @DSI_PLL_VERSION_4NM: 4nm PLL
  48. * @DSI_PLL_VERSION_5NM: 5nm PLL
  49. * @DSI_PLL_VERSION_10NM: 10nm PLL
  50. * @DSI_PLL_VERSION_UNKNOWN: Unknown PLL version
  51. */
  52. enum dsi_pll_version {
  53. DSI_PLL_VERSION_4NM,
  54. DSI_PLL_VERSION_5NM,
  55. DSI_PLL_VERSION_10NM,
  56. DSI_PLL_VERSION_UNKNOWN
  57. };
  58. /**
  59. * enum dsi_phy_hw_features - features supported by DSI PHY hardware
  60. * @DSI_PHY_DPHY: Supports DPHY
  61. * @DSI_PHY_CPHY: Supports CPHY
  62. * @DSI_PHY_SPLIT_LINK: Supports Split Link
  63. * @DSI_PHY_MAX_FEATURES:
  64. */
  65. enum dsi_phy_hw_features {
  66. DSI_PHY_DPHY,
  67. DSI_PHY_CPHY,
  68. DSI_PHY_SPLIT_LINK,
  69. DSI_PHY_MAX_FEATURES
  70. };
  71. /**
  72. * enum dsi_phy_pll_source - pll clock source for PHY.
  73. * @DSI_PLL_SOURCE_STANDALONE: Clock is sourced from native PLL and is not
  74. * shared by other PHYs.
  75. * @DSI_PLL_SOURCE_NATIVE: Clock is sourced from native PLL and is
  76. * shared by other PHYs.
  77. * @DSI_PLL_SOURCE_NON_NATIVE: Clock is sourced from other PHYs.
  78. * @DSI_PLL_SOURCE_MAX:
  79. */
  80. enum dsi_phy_pll_source {
  81. DSI_PLL_SOURCE_STANDALONE = 0,
  82. DSI_PLL_SOURCE_NATIVE,
  83. DSI_PLL_SOURCE_NON_NATIVE,
  84. DSI_PLL_SOURCE_MAX
  85. };
  86. /**
  87. * struct dsi_phy_per_lane_cfgs - Holds register values for PHY parameters
  88. * @lane: A set of maximum 8 values for each lane.
  89. * @lane_v3: A set of maximum 12 values for each lane.
  90. * @count_per_lane: Number of values per each lane.
  91. */
  92. struct dsi_phy_per_lane_cfgs {
  93. u8 lane[DSI_LANE_MAX][DSI_MAX_SETTINGS];
  94. u8 lane_v3[DSI_PHY_TIMING_V3_SIZE];
  95. u8 lane_v4[DSI_PHY_TIMING_V4_SIZE];
  96. u32 count_per_lane;
  97. };
  98. /**
  99. * struct dsi_phy_cfg - DSI PHY configuration
  100. * @lanecfg: Lane configuration settings.
  101. * @strength: Strength settings for lanes.
  102. * @timing: Timing parameters for lanes.
  103. * @is_phy_timing_present: Boolean whether phy timings are defined.
  104. * @regulators: Regulator settings for lanes.
  105. * @pll_source: PLL source.
  106. * @lane_map: DSI logical to PHY lane mapping.
  107. * @force_clk_lane_hs:Boolean whether to force clock lane in HS mode.
  108. * @phy_type: Phy-type (Dphy/Cphy).
  109. * @bit_clk_rate_hz: DSI bit clk rate in HZ.
  110. * @split_link: DSI split link config data.
  111. */
  112. struct dsi_phy_cfg {
  113. struct dsi_phy_per_lane_cfgs lanecfg;
  114. struct dsi_phy_per_lane_cfgs strength;
  115. struct dsi_phy_per_lane_cfgs timing;
  116. bool is_phy_timing_present;
  117. struct dsi_phy_per_lane_cfgs regulators;
  118. enum dsi_phy_pll_source pll_source;
  119. struct dsi_lane_map lane_map;
  120. bool force_clk_lane_hs;
  121. enum dsi_phy_type phy_type;
  122. unsigned long bit_clk_rate_hz;
  123. struct dsi_split_link_config split_link;
  124. };
  125. struct dsi_phy_hw;
  126. struct phy_ulps_config_ops {
  127. /**
  128. * wait_for_lane_idle() - wait for DSI lanes to go to idle state
  129. * @phy: Pointer to DSI PHY hardware instance.
  130. * @lanes: ORed list of lanes (enum dsi_data_lanes) which need
  131. * to be checked to be in idle state.
  132. */
  133. int (*wait_for_lane_idle)(struct dsi_phy_hw *phy, u32 lanes);
  134. /**
  135. * ulps_request() - request ulps entry for specified lanes
  136. * @phy: Pointer to DSI PHY hardware instance.
  137. * @cfg: Per lane configurations for timing, strength and lane
  138. * configurations.
  139. * @lanes: ORed list of lanes (enum dsi_data_lanes) which need
  140. * to enter ULPS.
  141. *
  142. * Caller should check if lanes are in ULPS mode by calling
  143. * get_lanes_in_ulps() operation.
  144. */
  145. void (*ulps_request)(struct dsi_phy_hw *phy,
  146. struct dsi_phy_cfg *cfg, u32 lanes);
  147. /**
  148. * ulps_exit() - exit ULPS on specified lanes
  149. * @phy: Pointer to DSI PHY hardware instance.
  150. * @cfg: Per lane configurations for timing, strength and lane
  151. * configurations.
  152. * @lanes: ORed list of lanes (enum dsi_data_lanes) which need
  153. * to exit ULPS.
  154. *
  155. * Caller should check if lanes are in active mode by calling
  156. * get_lanes_in_ulps() operation.
  157. */
  158. void (*ulps_exit)(struct dsi_phy_hw *phy,
  159. struct dsi_phy_cfg *cfg, u32 lanes);
  160. /**
  161. * get_lanes_in_ulps() - returns the list of lanes in ULPS mode
  162. * @phy: Pointer to DSI PHY hardware instance.
  163. *
  164. * Returns an ORed list of lanes (enum dsi_data_lanes) that are in ULPS
  165. * state.
  166. *
  167. * Return: List of lanes in ULPS state.
  168. */
  169. u32 (*get_lanes_in_ulps)(struct dsi_phy_hw *phy);
  170. /**
  171. * is_lanes_in_ulps() - checks if the given lanes are in ulps
  172. * @lanes: lanes to be checked.
  173. * @ulps_lanes: lanes in ulps currenly.
  174. *
  175. * Return: true if all the given lanes are in ulps; false otherwise.
  176. */
  177. bool (*is_lanes_in_ulps)(u32 ulps, u32 ulps_lanes);
  178. };
  179. struct phy_dyn_refresh_ops {
  180. /**
  181. * dyn_refresh_helper - helper function to config particular registers
  182. * @phy: Pointer to DSI PHY hardware instance.
  183. * @offset: register offset to program.
  184. */
  185. void (*dyn_refresh_helper)(struct dsi_phy_hw *phy, u32 offset);
  186. /**
  187. * dyn_refresh_trigger_sel - configure trigger_sel to frame flush
  188. * @phy: Pointer to DSI PHY hardware instance.
  189. * @is_master: Boolean to indicate whether master or slave.
  190. */
  191. void (*dyn_refresh_trigger_sel)(struct dsi_phy_hw *phy,
  192. bool is_master);
  193. /**
  194. * dyn_refresh_config - configure dynamic refresh ctrl registers
  195. * @phy: Pointer to DSI PHY hardware instance.
  196. * @cfg: Pointer to DSI PHY timings.
  197. * @is_master: Boolean to indicate whether for master or slave.
  198. */
  199. void (*dyn_refresh_config)(struct dsi_phy_hw *phy,
  200. struct dsi_phy_cfg *cfg, bool is_master);
  201. /**
  202. * dyn_refresh_pipe_delay - configure pipe delay registers for dynamic
  203. * refresh.
  204. * @phy: Pointer to DSI PHY hardware instance.
  205. * @delay: structure containing all the delays to be programed.
  206. */
  207. void (*dyn_refresh_pipe_delay)(struct dsi_phy_hw *phy,
  208. struct dsi_dyn_clk_delay *delay);
  209. /**
  210. * cache_phy_timings - cache the phy timings calculated as part of
  211. * dynamic refresh.
  212. * @timings: Pointer to calculated phy timing parameters.
  213. * @dst: Pointer to cache location.
  214. * @size: Number of phy lane settings.
  215. */
  216. int (*cache_phy_timings)(struct dsi_phy_per_lane_cfgs *timings,
  217. u32 *dst, u32 size);
  218. };
  219. /**
  220. * struct dsi_phy_hw_ops - Operations for DSI PHY hardware.
  221. * @regulator_enable: Enable PHY regulators.
  222. * @regulator_disable: Disable PHY regulators.
  223. * @enable: Enable PHY.
  224. * @disable: Disable PHY.
  225. * @calculate_timing_params: Calculate PHY timing params from mode information
  226. */
  227. struct dsi_phy_hw_ops {
  228. /**
  229. * regulator_enable() - enable regulators for DSI PHY
  230. * @phy: Pointer to DSI PHY hardware object.
  231. * @reg_cfg: Regulator configuration for all DSI lanes.
  232. */
  233. void (*regulator_enable)(struct dsi_phy_hw *phy,
  234. struct dsi_phy_per_lane_cfgs *reg_cfg);
  235. /**
  236. * regulator_disable() - disable regulators
  237. * @phy: Pointer to DSI PHY hardware object.
  238. */
  239. void (*regulator_disable)(struct dsi_phy_hw *phy);
  240. /**
  241. * enable() - Enable PHY hardware
  242. * @phy: Pointer to DSI PHY hardware object.
  243. * @cfg: Per lane configurations for timing, strength and lane
  244. * configurations.
  245. */
  246. void (*enable)(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
  247. /**
  248. * disable() - Disable PHY hardware
  249. * @phy: Pointer to DSI PHY hardware object.
  250. * @cfg: Per lane configurations for timing, strength and lane
  251. * configurations.
  252. */
  253. void (*disable)(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
  254. /**
  255. * phy_idle_on() - Enable PHY hardware when entering idle screen
  256. * @phy: Pointer to DSI PHY hardware object.
  257. * @cfg: Per lane configurations for timing, strength and lane
  258. * configurations.
  259. */
  260. void (*phy_idle_on)(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
  261. /**
  262. * phy_idle_off() - Disable PHY hardware when exiting idle screen
  263. * @phy: Pointer to DSI PHY hardware object.
  264. */
  265. void (*phy_idle_off)(struct dsi_phy_hw *phy);
  266. /**
  267. * calculate_timing_params() - calculates timing parameters.
  268. * @phy: Pointer to DSI PHY hardware object.
  269. * @mode: Mode information for which timing has to be calculated.
  270. * @config: DSI host configuration for this mode.
  271. * @timing: Timing parameters for each lane which will be returned.
  272. * @use_mode_bit_clk: Boolean to indicate whether reacalculate dsi
  273. * bitclk or use the existing bitclk(for dynamic clk case).
  274. */
  275. int (*calculate_timing_params)(struct dsi_phy_hw *phy,
  276. struct dsi_mode_info *mode,
  277. struct dsi_host_common_cfg *config,
  278. struct dsi_phy_per_lane_cfgs *timing,
  279. bool use_mode_bit_clk);
  280. /**
  281. * phy_timing_val() - Gets PHY timing values.
  282. * @timing_val: Timing parameters for each lane which will be returned.
  283. * @timing: Array containing PHY timing values
  284. * @size: Size of the array
  285. */
  286. int (*phy_timing_val)(struct dsi_phy_per_lane_cfgs *timing_val,
  287. u32 *timing, u32 size);
  288. /**
  289. * clamp_ctrl() - configure clamps for DSI lanes
  290. * @phy: DSI PHY handle.
  291. * @enable: boolean to specify clamp enable/disable.
  292. * Return: error code.
  293. */
  294. void (*clamp_ctrl)(struct dsi_phy_hw *phy, bool enable);
  295. /**
  296. * phy_lane_reset() - Reset dsi phy lanes in case of error.
  297. * @phy: Pointer to DSI PHY hardware object.
  298. * Return: error code.
  299. */
  300. int (*phy_lane_reset)(struct dsi_phy_hw *phy);
  301. /**
  302. * toggle_resync_fifo() - toggle resync retime FIFO to sync data paths
  303. * @phy: Pointer to DSI PHY hardware object.
  304. * Return: error code.
  305. */
  306. void (*toggle_resync_fifo)(struct dsi_phy_hw *phy);
  307. /**
  308. * reset_clk_en_sel() - reset clk_en_sel on phy cmn_clk_cfg1 register
  309. * @phy: Pointer to DSI PHY hardware object.
  310. */
  311. void (*reset_clk_en_sel)(struct dsi_phy_hw *phy);
  312. /**
  313. * set_continuous_clk() - Set continuous clock
  314. * @phy: Pointer to DSI PHY hardware object
  315. * @enable: Bool to control continuous clock request.
  316. */
  317. void (*set_continuous_clk)(struct dsi_phy_hw *phy, bool enable);
  318. /**
  319. * commit_phy_timing() - Commit PHY timing
  320. * @phy: Pointer to DSI PHY hardware object.
  321. * @timing: Pointer to PHY timing array
  322. */
  323. void (*commit_phy_timing)(struct dsi_phy_hw *phy,
  324. struct dsi_phy_per_lane_cfgs *timing);
  325. void *timing_ops;
  326. struct phy_ulps_config_ops ulps_ops;
  327. struct phy_dyn_refresh_ops dyn_refresh_ops;
  328. /**
  329. * configure() - Configure the DSI PHY PLL
  330. * @pll: Pointer to DSI PLL.
  331. * @commit: boolean to specify if calculated PHY configuration
  332. needs to be committed. Set to false in case of
  333. dynamic clock switch.
  334. */
  335. int (*configure)(void *pll, bool commit);
  336. /**
  337. * pll_toggle() - Toggle the DSI PHY PLL
  338. * @pll: Pointer to DSI PLL.
  339. * @prepare: specify if PLL needs to be turned on or off.
  340. */
  341. int (*pll_toggle)(void *pll, bool prepare);
  342. };
  343. /**
  344. * struct dsi_phy_hw - DSI phy hardware object specific to an instance
  345. * @base: VA for the DSI PHY base address.
  346. * @length: Length of the DSI PHY register base map.
  347. * @dyn_pll_base: VA for the DSI dynamic refresh base address.
  348. * @length: Length of the DSI dynamic refresh register base map.
  349. * @index: Instance ID of the controller.
  350. * @version: DSI PHY version.
  351. * @phy_clamp_base: Base address of phy clamp register map.
  352. * @feature_map: Features supported by DSI PHY.
  353. * @ops: Function pointer to PHY operations.
  354. */
  355. struct dsi_phy_hw {
  356. void __iomem *base;
  357. u32 length;
  358. void __iomem *dyn_pll_base;
  359. u32 dyn_refresh_len;
  360. u32 index;
  361. enum dsi_phy_version version;
  362. void __iomem *phy_clamp_base;
  363. DECLARE_BITMAP(feature_map, DSI_PHY_MAX_FEATURES);
  364. struct dsi_phy_hw_ops ops;
  365. };
  366. /**
  367. * dsi_phy_conv_phy_to_logical_lane() - Convert physical to logical lane
  368. * @lane_map: logical lane
  369. * @phy_lane: physical lane
  370. *
  371. * Return: Error code on failure. Lane number on success.
  372. */
  373. int dsi_phy_conv_phy_to_logical_lane(
  374. struct dsi_lane_map *lane_map, enum dsi_phy_data_lanes phy_lane);
  375. /**
  376. * dsi_phy_conv_logical_to_phy_lane() - Convert logical to physical lane
  377. * @lane_map: physical lane
  378. * @lane: logical lane
  379. *
  380. * Return: Error code on failure. Lane number on success.
  381. */
  382. int dsi_phy_conv_logical_to_phy_lane(
  383. struct dsi_lane_map *lane_map, enum dsi_logical_lane lane);
  384. #endif /* _DSI_PHY_HW_H_ */