dsi_phy.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/of_device.h>
  6. #include <linux/err.h>
  7. #include <linux/regulator/consumer.h>
  8. #include <linux/clk.h>
  9. #include <linux/list.h>
  10. #include "msm_drv.h"
  11. #include "msm_kms.h"
  12. #include "dsi_phy.h"
  13. #include "dsi_phy_hw.h"
  14. #include "dsi_clk.h"
  15. #include "dsi_pwr.h"
  16. #include "dsi_catalog.h"
  17. #include "sde_dbg.h"
  18. #define DSI_PHY_DEFAULT_LABEL "MDSS PHY CTRL"
  19. #define BITS_PER_BYTE 8
  20. struct dsi_phy_list_item {
  21. struct msm_dsi_phy *phy;
  22. struct list_head list;
  23. };
  24. static LIST_HEAD(dsi_phy_list);
  25. static DEFINE_MUTEX(dsi_phy_list_lock);
  26. static const struct dsi_ver_spec_info dsi_phy_v3_0 = {
  27. .version = DSI_PHY_VERSION_3_0,
  28. .lane_cfg_count = 4,
  29. .strength_cfg_count = 2,
  30. .regulator_cfg_count = 0,
  31. .timing_cfg_count = 12,
  32. };
  33. static const struct dsi_ver_spec_info dsi_phy_v4_0 = {
  34. .version = DSI_PHY_VERSION_4_0,
  35. .lane_cfg_count = 4,
  36. .strength_cfg_count = 2,
  37. .regulator_cfg_count = 0,
  38. .timing_cfg_count = 14,
  39. };
  40. static const struct dsi_ver_spec_info dsi_phy_v4_1 = {
  41. .version = DSI_PHY_VERSION_4_1,
  42. .lane_cfg_count = 4,
  43. .strength_cfg_count = 2,
  44. .regulator_cfg_count = 0,
  45. .timing_cfg_count = 14,
  46. };
  47. static const struct dsi_ver_spec_info dsi_phy_v4_2 = {
  48. .version = DSI_PHY_VERSION_4_2,
  49. .lane_cfg_count = 4,
  50. .strength_cfg_count = 2,
  51. .regulator_cfg_count = 0,
  52. .timing_cfg_count = 14,
  53. };
  54. static const struct dsi_ver_spec_info dsi_phy_v4_3 = {
  55. .version = DSI_PHY_VERSION_4_3,
  56. .lane_cfg_count = 4,
  57. .strength_cfg_count = 2,
  58. .regulator_cfg_count = 0,
  59. .timing_cfg_count = 14,
  60. };
  61. static const struct dsi_ver_spec_info dsi_phy_v5_2 = {
  62. .version = DSI_PHY_VERSION_5_2,
  63. .lane_cfg_count = 4,
  64. .strength_cfg_count = 2,
  65. .regulator_cfg_count = 0,
  66. .timing_cfg_count = 14,
  67. };
  68. static const struct of_device_id msm_dsi_phy_of_match[] = {
  69. { .compatible = "qcom,dsi-phy-v3.0",
  70. .data = &dsi_phy_v3_0,},
  71. { .compatible = "qcom,dsi-phy-v4.0",
  72. .data = &dsi_phy_v4_0,},
  73. { .compatible = "qcom,dsi-phy-v4.1",
  74. .data = &dsi_phy_v4_1,},
  75. { .compatible = "qcom,dsi-phy-v4.2",
  76. .data = &dsi_phy_v4_2,},
  77. { .compatible = "qcom,dsi-phy-v4.3",
  78. .data = &dsi_phy_v4_3,},
  79. { .compatible = "qcom,dsi-phy-v5.2",
  80. .data = &dsi_phy_v5_2,},
  81. {}
  82. };
  83. int dsi_phy_get_version(struct msm_dsi_phy *phy)
  84. {
  85. return phy->ver_info->version;
  86. }
  87. int dsi_phy_get_io_resources(struct msm_io_res *io_res)
  88. {
  89. struct dsi_phy_list_item *dsi_phy;
  90. int rc = 0;
  91. mutex_lock(&dsi_phy_list_lock);
  92. list_for_each_entry(dsi_phy, &dsi_phy_list, list) {
  93. rc = msm_dss_get_io_mem(dsi_phy->phy->pdev, &io_res->mem);
  94. if (rc) {
  95. DSI_PHY_ERR(dsi_phy->phy,
  96. "failed to get io mem, rc = %d\n", rc);
  97. return rc;
  98. }
  99. }
  100. mutex_unlock(&dsi_phy_list_lock);
  101. return rc;
  102. }
  103. static int dsi_phy_regmap_init(struct platform_device *pdev,
  104. struct msm_dsi_phy *phy)
  105. {
  106. int rc = 0;
  107. void __iomem *ptr;
  108. ptr = msm_ioremap(pdev, "dsi_phy", phy->name);
  109. if (IS_ERR(ptr)) {
  110. rc = PTR_ERR(ptr);
  111. return rc;
  112. }
  113. phy->hw.base = ptr;
  114. ptr = msm_ioremap(pdev, "dyn_refresh_base", phy->name);
  115. phy->hw.dyn_pll_base = ptr;
  116. DSI_PHY_DBG(phy, "map dsi_phy registers to %pK\n", phy->hw.base);
  117. return rc;
  118. }
  119. static int dsi_phy_regmap_deinit(struct msm_dsi_phy *phy)
  120. {
  121. DSI_PHY_DBG(phy, "unmap registers\n");
  122. return 0;
  123. }
  124. static int dsi_phy_supplies_init(struct platform_device *pdev,
  125. struct msm_dsi_phy *phy)
  126. {
  127. int rc = 0;
  128. int i = 0;
  129. struct dsi_regulator_info *regs;
  130. struct regulator *vreg = NULL;
  131. regs = &phy->pwr_info.digital;
  132. regs->vregs = devm_kzalloc(&pdev->dev, sizeof(struct dsi_vreg),
  133. GFP_KERNEL);
  134. if (!regs->vregs)
  135. goto error;
  136. regs->count = 1;
  137. snprintf(regs->vregs->vreg_name,
  138. ARRAY_SIZE(regs->vregs[i].vreg_name),
  139. "%s", "gdsc");
  140. rc = dsi_pwr_get_dt_vreg_data(&pdev->dev,
  141. &phy->pwr_info.phy_pwr,
  142. "qcom,phy-supply-entries");
  143. if (rc) {
  144. DSI_PHY_ERR(phy, "failed to get host power supplies, rc = %d\n",
  145. rc);
  146. goto error_digital;
  147. }
  148. regs = &phy->pwr_info.digital;
  149. for (i = 0; i < regs->count; i++) {
  150. vreg = devm_regulator_get(&pdev->dev, regs->vregs[i].vreg_name);
  151. rc = PTR_ERR_OR_ZERO(vreg);
  152. if (rc) {
  153. DSI_PHY_ERR(phy, "failed to get %s regulator\n",
  154. regs->vregs[i].vreg_name);
  155. goto error_host_pwr;
  156. }
  157. regs->vregs[i].vreg = vreg;
  158. }
  159. regs = &phy->pwr_info.phy_pwr;
  160. for (i = 0; i < regs->count; i++) {
  161. vreg = devm_regulator_get(&pdev->dev, regs->vregs[i].vreg_name);
  162. rc = PTR_ERR_OR_ZERO(vreg);
  163. if (rc) {
  164. DSI_PHY_ERR(phy, "failed to get %s regulator\n",
  165. regs->vregs[i].vreg_name);
  166. for (--i; i >= 0; i--)
  167. devm_regulator_put(regs->vregs[i].vreg);
  168. goto error_digital_put;
  169. }
  170. regs->vregs[i].vreg = vreg;
  171. }
  172. return rc;
  173. error_digital_put:
  174. regs = &phy->pwr_info.digital;
  175. for (i = 0; i < regs->count; i++)
  176. devm_regulator_put(regs->vregs[i].vreg);
  177. error_host_pwr:
  178. devm_kfree(&pdev->dev, phy->pwr_info.phy_pwr.vregs);
  179. phy->pwr_info.phy_pwr.vregs = NULL;
  180. phy->pwr_info.phy_pwr.count = 0;
  181. error_digital:
  182. devm_kfree(&pdev->dev, phy->pwr_info.digital.vregs);
  183. phy->pwr_info.digital.vregs = NULL;
  184. phy->pwr_info.digital.count = 0;
  185. error:
  186. return rc;
  187. }
  188. static int dsi_phy_supplies_deinit(struct msm_dsi_phy *phy)
  189. {
  190. int i = 0;
  191. int rc = 0;
  192. struct dsi_regulator_info *regs;
  193. regs = &phy->pwr_info.digital;
  194. for (i = 0; i < regs->count; i++) {
  195. if (!regs->vregs[i].vreg)
  196. DSI_PHY_ERR(phy, "vreg is NULL, should not reach here\n");
  197. else
  198. devm_regulator_put(regs->vregs[i].vreg);
  199. }
  200. regs = &phy->pwr_info.phy_pwr;
  201. for (i = 0; i < regs->count; i++) {
  202. if (!regs->vregs[i].vreg)
  203. DSI_PHY_ERR(phy, "vreg is NULL, should not reach here\n");
  204. else
  205. devm_regulator_put(regs->vregs[i].vreg);
  206. }
  207. if (phy->pwr_info.phy_pwr.vregs) {
  208. devm_kfree(&phy->pdev->dev, phy->pwr_info.phy_pwr.vregs);
  209. phy->pwr_info.phy_pwr.vregs = NULL;
  210. phy->pwr_info.phy_pwr.count = 0;
  211. }
  212. if (phy->pwr_info.digital.vregs) {
  213. devm_kfree(&phy->pdev->dev, phy->pwr_info.digital.vregs);
  214. phy->pwr_info.digital.vregs = NULL;
  215. phy->pwr_info.digital.count = 0;
  216. }
  217. return rc;
  218. }
  219. static int dsi_phy_parse_dt_per_lane_cfgs(struct platform_device *pdev,
  220. struct dsi_phy_per_lane_cfgs *cfg,
  221. char *property)
  222. {
  223. int rc = 0, i = 0, j = 0;
  224. const u8 *data;
  225. u32 len = 0;
  226. data = of_get_property(pdev->dev.of_node, property, &len);
  227. if (!data) {
  228. DSI_ERR("Unable to read Phy %s settings\n", property);
  229. return -EINVAL;
  230. }
  231. if (len != DSI_LANE_MAX * cfg->count_per_lane) {
  232. DSI_ERR("incorrect phy %s settings, exp=%d, act=%d\n",
  233. property, (DSI_LANE_MAX * cfg->count_per_lane), len);
  234. return -EINVAL;
  235. }
  236. for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {
  237. for (j = 0; j < cfg->count_per_lane; j++) {
  238. cfg->lane[i][j] = *data;
  239. data++;
  240. }
  241. }
  242. return rc;
  243. }
  244. static int dsi_phy_settings_init(struct platform_device *pdev,
  245. struct msm_dsi_phy *phy)
  246. {
  247. int rc = 0;
  248. struct dsi_phy_per_lane_cfgs *lane = &phy->cfg.lanecfg;
  249. struct dsi_phy_per_lane_cfgs *strength = &phy->cfg.strength;
  250. struct dsi_phy_per_lane_cfgs *timing = &phy->cfg.timing;
  251. struct dsi_phy_per_lane_cfgs *regs = &phy->cfg.regulators;
  252. lane->count_per_lane = phy->ver_info->lane_cfg_count;
  253. rc = dsi_phy_parse_dt_per_lane_cfgs(pdev, lane,
  254. "qcom,platform-lane-config");
  255. if (rc) {
  256. DSI_PHY_ERR(phy, "failed to parse lane cfgs, rc=%d\n", rc);
  257. goto err;
  258. }
  259. strength->count_per_lane = phy->ver_info->strength_cfg_count;
  260. rc = dsi_phy_parse_dt_per_lane_cfgs(pdev, strength,
  261. "qcom,platform-strength-ctrl");
  262. if (rc) {
  263. DSI_PHY_ERR(phy, "failed to parse lane cfgs, rc=%d\n", rc);
  264. goto err;
  265. }
  266. regs->count_per_lane = phy->ver_info->regulator_cfg_count;
  267. if (regs->count_per_lane > 0) {
  268. rc = dsi_phy_parse_dt_per_lane_cfgs(pdev, regs,
  269. "qcom,platform-regulator-settings");
  270. if (rc) {
  271. DSI_PHY_ERR(phy, "failed to parse lane cfgs, rc=%d\n",
  272. rc);
  273. goto err;
  274. }
  275. }
  276. /* Actual timing values are dependent on panel */
  277. timing->count_per_lane = phy->ver_info->timing_cfg_count;
  278. phy->allow_phy_power_off = of_property_read_bool(pdev->dev.of_node,
  279. "qcom,panel-allow-phy-poweroff");
  280. of_property_read_u32(pdev->dev.of_node,
  281. "qcom,dsi-phy-regulator-min-datarate-bps",
  282. &phy->regulator_min_datarate_bps);
  283. return 0;
  284. err:
  285. lane->count_per_lane = 0;
  286. strength->count_per_lane = 0;
  287. regs->count_per_lane = 0;
  288. timing->count_per_lane = 0;
  289. return rc;
  290. }
  291. static int dsi_phy_settings_deinit(struct msm_dsi_phy *phy)
  292. {
  293. memset(&phy->cfg.lanecfg, 0x0, sizeof(phy->cfg.lanecfg));
  294. memset(&phy->cfg.strength, 0x0, sizeof(phy->cfg.strength));
  295. memset(&phy->cfg.timing, 0x0, sizeof(phy->cfg.timing));
  296. memset(&phy->cfg.regulators, 0x0, sizeof(phy->cfg.regulators));
  297. return 0;
  298. }
  299. static int dsi_phy_driver_probe(struct platform_device *pdev)
  300. {
  301. struct msm_dsi_phy *dsi_phy;
  302. struct dsi_phy_list_item *item;
  303. const struct of_device_id *id;
  304. const struct dsi_ver_spec_info *ver_info;
  305. int rc = 0;
  306. u32 index = 0;
  307. if (!pdev || !pdev->dev.of_node) {
  308. DSI_ERR("pdev not found\n");
  309. return -ENODEV;
  310. }
  311. id = of_match_node(msm_dsi_phy_of_match, pdev->dev.of_node);
  312. if (!id)
  313. return -ENODEV;
  314. ver_info = id->data;
  315. item = devm_kzalloc(&pdev->dev, sizeof(*item), GFP_KERNEL);
  316. if (!item)
  317. return -ENOMEM;
  318. dsi_phy = devm_kzalloc(&pdev->dev, sizeof(*dsi_phy), GFP_KERNEL);
  319. if (!dsi_phy) {
  320. devm_kfree(&pdev->dev, item);
  321. return -ENOMEM;
  322. }
  323. rc = of_property_read_u32(pdev->dev.of_node, "cell-index", &index);
  324. if (rc) {
  325. DSI_PHY_DBG(dsi_phy, "cell index not set, default to 0\n");
  326. index = 0;
  327. }
  328. dsi_phy->index = index;
  329. dsi_phy->name = of_get_property(pdev->dev.of_node, "label", NULL);
  330. if (!dsi_phy->name)
  331. dsi_phy->name = DSI_PHY_DEFAULT_LABEL;
  332. DSI_PHY_DBG(dsi_phy, "Probing device\n");
  333. dsi_phy->ver_info = ver_info;
  334. rc = dsi_phy_regmap_init(pdev, dsi_phy);
  335. if (rc) {
  336. DSI_PHY_ERR(dsi_phy, "Failed to parse register information, rc=%d\n",
  337. rc);
  338. goto fail;
  339. }
  340. rc = dsi_phy_supplies_init(pdev, dsi_phy);
  341. if (rc) {
  342. DSI_PHY_ERR(dsi_phy, "failed to parse voltage supplies, rc = %d\n",
  343. rc);
  344. goto fail_regmap;
  345. }
  346. rc = dsi_catalog_phy_setup(&dsi_phy->hw, ver_info->version,
  347. dsi_phy->index);
  348. if (rc) {
  349. DSI_PHY_ERR(dsi_phy, "Catalog does not support version (%d)\n",
  350. ver_info->version);
  351. goto fail_supplies;
  352. }
  353. rc = dsi_phy_settings_init(pdev, dsi_phy);
  354. if (rc) {
  355. DSI_PHY_ERR(dsi_phy, "Failed to parse phy setting, rc=%d\n",
  356. rc);
  357. goto fail_supplies;
  358. }
  359. rc = dsi_pll_init(pdev, &dsi_phy->pll);
  360. if (rc) {
  361. DSI_PHY_ERR(dsi_phy, "Failed to initialize DSI PLL, rc=%d\n", rc);
  362. goto fail_settings;
  363. }
  364. rc = dsi_catalog_phy_pll_setup(&dsi_phy->hw,
  365. dsi_phy->pll->pll_revision);
  366. if (rc) {
  367. DSI_PHY_ERR(dsi_phy, "Catalog does not support PLL version (%d)\n",
  368. dsi_phy->pll->pll_revision);
  369. goto fail_settings;
  370. }
  371. item->phy = dsi_phy;
  372. mutex_lock(&dsi_phy_list_lock);
  373. list_add(&item->list, &dsi_phy_list);
  374. mutex_unlock(&dsi_phy_list_lock);
  375. mutex_init(&dsi_phy->phy_lock);
  376. /** TODO: initialize debugfs */
  377. dsi_phy->pdev = pdev;
  378. platform_set_drvdata(pdev, dsi_phy);
  379. DSI_PHY_INFO(dsi_phy, "Probe successful\n");
  380. return 0;
  381. fail_settings:
  382. (void)dsi_phy_settings_deinit(dsi_phy);
  383. fail_supplies:
  384. (void)dsi_phy_supplies_deinit(dsi_phy);
  385. fail_regmap:
  386. (void)dsi_phy_regmap_deinit(dsi_phy);
  387. fail:
  388. devm_kfree(&pdev->dev, dsi_phy);
  389. devm_kfree(&pdev->dev, item);
  390. return rc;
  391. }
  392. static int dsi_phy_driver_remove(struct platform_device *pdev)
  393. {
  394. int rc = 0;
  395. struct msm_dsi_phy *phy = platform_get_drvdata(pdev);
  396. struct list_head *pos, *tmp;
  397. if (!pdev || !phy) {
  398. DSI_PHY_ERR(phy, "Invalid device\n");
  399. return -EINVAL;
  400. }
  401. mutex_lock(&dsi_phy_list_lock);
  402. list_for_each_safe(pos, tmp, &dsi_phy_list) {
  403. struct dsi_phy_list_item *n;
  404. n = list_entry(pos, struct dsi_phy_list_item, list);
  405. if (n->phy == phy) {
  406. list_del(&n->list);
  407. devm_kfree(&pdev->dev, n);
  408. break;
  409. }
  410. }
  411. mutex_unlock(&dsi_phy_list_lock);
  412. mutex_lock(&phy->phy_lock);
  413. rc = dsi_phy_settings_deinit(phy);
  414. if (rc)
  415. DSI_PHY_ERR(phy, "failed to deinitialize phy settings, rc=%d\n",
  416. rc);
  417. rc = dsi_phy_supplies_deinit(phy);
  418. if (rc)
  419. DSI_PHY_ERR(phy, "failed to deinitialize voltage supplies, rc=%d\n",
  420. rc);
  421. rc = dsi_phy_regmap_deinit(phy);
  422. if (rc)
  423. DSI_PHY_ERR(phy, "failed to deinitialize regmap, rc=%d\n", rc);
  424. mutex_unlock(&phy->phy_lock);
  425. mutex_destroy(&phy->phy_lock);
  426. devm_kfree(&pdev->dev, phy);
  427. platform_set_drvdata(pdev, NULL);
  428. return 0;
  429. }
  430. static struct platform_driver dsi_phy_platform_driver = {
  431. .probe = dsi_phy_driver_probe,
  432. .remove = dsi_phy_driver_remove,
  433. .driver = {
  434. .name = "dsi_phy",
  435. .of_match_table = msm_dsi_phy_of_match,
  436. },
  437. };
  438. static void dsi_phy_enable_hw(struct msm_dsi_phy *phy)
  439. {
  440. if (phy->hw.ops.regulator_enable)
  441. phy->hw.ops.regulator_enable(&phy->hw, &phy->cfg.regulators);
  442. if (phy->hw.ops.enable)
  443. phy->hw.ops.enable(&phy->hw, &phy->cfg);
  444. }
  445. static void dsi_phy_disable_hw(struct msm_dsi_phy *phy)
  446. {
  447. if (phy->hw.ops.disable)
  448. phy->hw.ops.disable(&phy->hw, &phy->cfg);
  449. if (phy->hw.ops.regulator_disable)
  450. phy->hw.ops.regulator_disable(&phy->hw);
  451. }
  452. /**
  453. * dsi_phy_check_resource() - check if DSI PHY is probed
  454. * @of_node: of_node of the DSI PHY.
  455. *
  456. * Checks if the DSI PHY has been probed and is available.
  457. *
  458. * Return: status of DSI PHY
  459. */
  460. bool dsi_phy_check_resource(struct device_node *of_node)
  461. {
  462. struct list_head *pos, *tmp;
  463. struct msm_dsi_phy *phy = NULL;
  464. mutex_lock(&dsi_phy_list_lock);
  465. list_for_each_safe(pos, tmp, &dsi_phy_list) {
  466. struct dsi_phy_list_item *n;
  467. n = list_entry(pos, struct dsi_phy_list_item, list);
  468. if (!n->phy || !n->phy->pdev)
  469. break;
  470. if (n->phy->pdev->dev.of_node == of_node) {
  471. phy = n->phy;
  472. break;
  473. }
  474. }
  475. mutex_unlock(&dsi_phy_list_lock);
  476. return phy ? true : false;
  477. }
  478. /**
  479. * dsi_phy_get() - get a dsi phy handle from device node
  480. * @of_node: device node for dsi phy controller
  481. *
  482. * Gets the DSI PHY handle for the corresponding of_node. The ref count is
  483. * incremented to one all subsequents get will fail until the original client
  484. * calls a put.
  485. *
  486. * Return: DSI PHY handle or an error code.
  487. */
  488. struct msm_dsi_phy *dsi_phy_get(struct device_node *of_node)
  489. {
  490. struct list_head *pos, *tmp;
  491. struct msm_dsi_phy *phy = NULL;
  492. mutex_lock(&dsi_phy_list_lock);
  493. list_for_each_safe(pos, tmp, &dsi_phy_list) {
  494. struct dsi_phy_list_item *n;
  495. n = list_entry(pos, struct dsi_phy_list_item, list);
  496. if (n->phy->pdev->dev.of_node == of_node) {
  497. phy = n->phy;
  498. break;
  499. }
  500. }
  501. mutex_unlock(&dsi_phy_list_lock);
  502. if (!phy) {
  503. DSI_PHY_ERR(phy, "Device with of node not found rc=%d\n",
  504. -EPROBE_DEFER);
  505. phy = ERR_PTR(-EPROBE_DEFER);
  506. return phy;
  507. }
  508. mutex_lock(&phy->phy_lock);
  509. if (phy->refcount > 0) {
  510. DSI_PHY_ERR(phy, "Device under use\n");
  511. phy = ERR_PTR(-EINVAL);
  512. } else {
  513. phy->refcount++;
  514. }
  515. mutex_unlock(&phy->phy_lock);
  516. return phy;
  517. }
  518. /**
  519. * dsi_phy_put() - release dsi phy handle
  520. * @dsi_phy: DSI PHY handle.
  521. *
  522. * Release the DSI PHY hardware. Driver will clean up all resources and puts
  523. * back the DSI PHY into reset state.
  524. */
  525. void dsi_phy_put(struct msm_dsi_phy *dsi_phy)
  526. {
  527. mutex_lock(&dsi_phy->phy_lock);
  528. if (dsi_phy->refcount == 0)
  529. DSI_PHY_ERR(dsi_phy, "Unbalanced %s call\n", __func__);
  530. else
  531. dsi_phy->refcount--;
  532. mutex_unlock(&dsi_phy->phy_lock);
  533. }
  534. /**
  535. * dsi_phy_drv_init() - initialize dsi phy driver
  536. * @dsi_phy: DSI PHY handle.
  537. *
  538. * Initializes DSI PHY driver. Should be called after dsi_phy_get().
  539. *
  540. * Return: error code.
  541. */
  542. int dsi_phy_drv_init(struct msm_dsi_phy *dsi_phy)
  543. {
  544. char dbg_name[DSI_DEBUG_NAME_LEN];
  545. snprintf(dbg_name, DSI_DEBUG_NAME_LEN, "dsi%d_phy", dsi_phy->index);
  546. sde_dbg_reg_register_base(dbg_name, dsi_phy->hw.base,
  547. msm_iomap_size(dsi_phy->pdev, "dsi_phy"),
  548. msm_get_phys_addr(dsi_phy->pdev, "dsi_phy"), SDE_DBG_DSI);
  549. return 0;
  550. }
  551. /**
  552. * dsi_phy_drv_deinit() - de-initialize dsi phy driver
  553. * @dsi_phy: DSI PHY handle.
  554. *
  555. * Release all resources acquired by dsi_phy_drv_init().
  556. *
  557. * Return: error code.
  558. */
  559. int dsi_phy_drv_deinit(struct msm_dsi_phy *dsi_phy)
  560. {
  561. return 0;
  562. }
  563. int dsi_phy_clk_cb_register(struct msm_dsi_phy *dsi_phy,
  564. struct clk_ctrl_cb *clk_cb)
  565. {
  566. if (!dsi_phy || !clk_cb) {
  567. DSI_PHY_ERR(dsi_phy, "Invalid params\n");
  568. return -EINVAL;
  569. }
  570. dsi_phy->clk_cb.priv = clk_cb->priv;
  571. dsi_phy->clk_cb.dsi_clk_cb = clk_cb->dsi_clk_cb;
  572. return 0;
  573. }
  574. /**
  575. * dsi_phy_validate_mode() - validate a display mode
  576. * @dsi_phy: DSI PHY handle.
  577. * @mode: Mode information.
  578. *
  579. * Validation will fail if the mode cannot be supported by the PHY driver or
  580. * hardware.
  581. *
  582. * Return: error code.
  583. */
  584. int dsi_phy_validate_mode(struct msm_dsi_phy *dsi_phy,
  585. struct dsi_mode_info *mode)
  586. {
  587. int rc = 0;
  588. if (!dsi_phy || !mode) {
  589. DSI_PHY_ERR(dsi_phy, "Invalid params\n");
  590. return -EINVAL;
  591. }
  592. DSI_PHY_DBG(dsi_phy, "Skipping validation\n");
  593. return rc;
  594. }
  595. /**
  596. * dsi_phy_set_power_state() - enable/disable dsi phy power supplies
  597. * @dsi_phy: DSI PHY handle.
  598. * @enable: Boolean flag to enable/disable.
  599. *
  600. * Return: error code.
  601. */
  602. int dsi_phy_set_power_state(struct msm_dsi_phy *dsi_phy, bool enable)
  603. {
  604. int rc = 0;
  605. if (!dsi_phy) {
  606. DSI_PHY_ERR(dsi_phy, "Invalid params\n");
  607. return -EINVAL;
  608. }
  609. mutex_lock(&dsi_phy->phy_lock);
  610. if (enable == dsi_phy->power_state) {
  611. DSI_PHY_ERR(dsi_phy, "No state change\n");
  612. goto error;
  613. }
  614. if (enable) {
  615. rc = dsi_pwr_enable_regulator(&dsi_phy->pwr_info.digital, true);
  616. if (rc) {
  617. DSI_PHY_ERR(dsi_phy, "failed to enable digital regulator\n");
  618. goto error;
  619. }
  620. if (dsi_phy->dsi_phy_state == DSI_PHY_ENGINE_OFF &&
  621. dsi_phy->regulator_required) {
  622. rc = dsi_pwr_enable_regulator(
  623. &dsi_phy->pwr_info.phy_pwr, true);
  624. if (rc) {
  625. DSI_PHY_ERR(dsi_phy, "failed to enable phy power\n");
  626. (void)dsi_pwr_enable_regulator(
  627. &dsi_phy->pwr_info.digital, false);
  628. goto error;
  629. }
  630. }
  631. } else {
  632. if (dsi_phy->dsi_phy_state == DSI_PHY_ENGINE_OFF &&
  633. dsi_phy->regulator_required) {
  634. rc = dsi_pwr_enable_regulator(
  635. &dsi_phy->pwr_info.phy_pwr, false);
  636. if (rc) {
  637. DSI_PHY_ERR(dsi_phy, "failed to enable digital regulator\n");
  638. goto error;
  639. }
  640. }
  641. rc = dsi_pwr_enable_regulator(&dsi_phy->pwr_info.digital,
  642. false);
  643. if (rc) {
  644. DSI_PHY_ERR(dsi_phy, "failed to enable phy power\n");
  645. goto error;
  646. }
  647. }
  648. dsi_phy->power_state = enable;
  649. error:
  650. mutex_unlock(&dsi_phy->phy_lock);
  651. return rc;
  652. }
  653. /**
  654. * dsi_phy_get_data_lanes_count() - Count the data lines need to be configured
  655. * @dsi_phy: DSI PHY handle.
  656. *
  657. * Return: Count of data lanes being used
  658. */
  659. static inline int dsi_phy_get_data_lanes_count(struct msm_dsi_phy *phy)
  660. {
  661. int num_of_lanes = 0;
  662. enum dsi_data_lanes dlanes;
  663. dlanes = phy->data_lanes;
  664. /**
  665. * For split link use case effective data lines need to be used
  666. * rather than total lanes on PHY for clock calculation and hence we
  667. * fall back pll->lanes to lanes_per_sublink rather than total
  668. * lanes.
  669. */
  670. if (phy->cfg.split_link.enabled)
  671. return phy->cfg.split_link.lanes_per_sublink;
  672. if (dlanes & DSI_DATA_LANE_0)
  673. num_of_lanes++;
  674. if (dlanes & DSI_DATA_LANE_1)
  675. num_of_lanes++;
  676. if (dlanes & DSI_DATA_LANE_2)
  677. num_of_lanes++;
  678. if (dlanes & DSI_DATA_LANE_3)
  679. num_of_lanes++;
  680. return num_of_lanes;
  681. }
  682. /**
  683. * dsi_phy_configure() - Configure DSI PHY PLL
  684. * @dsi_phy: DSI PHY handle.
  685. * @commit: boolean to specify if calculated PHY configuration
  686. * needs to be committed. Set to false in case of
  687. * dynamic clock switch.
  688. *
  689. * Return: error code.
  690. */
  691. int dsi_phy_configure(struct msm_dsi_phy *phy, bool commit)
  692. {
  693. int rc = 0;
  694. phy->pll->type = phy->cfg.phy_type;
  695. phy->pll->bpp = dsi_pixel_format_to_bpp(phy->dst_format);
  696. phy->pll->lanes = dsi_phy_get_data_lanes_count(phy);
  697. if (phy->hw.ops.configure)
  698. rc = phy->hw.ops.configure(phy->pll, commit);
  699. return rc;
  700. }
  701. /**
  702. * dsi_phy_pll_toggle() - Toggle DSI PHY PLL
  703. * @dsi_phy: DSI PHY handle.
  704. * @prepare: specifies if PLL needs to be turned on or not.
  705. *
  706. * Return: error code.
  707. */
  708. int dsi_phy_pll_toggle(struct msm_dsi_phy *phy, bool prepare)
  709. {
  710. int rc = 0;
  711. if (phy->hw.ops.pll_toggle)
  712. rc = phy->hw.ops.pll_toggle(phy->pll, prepare);
  713. return rc;
  714. }
  715. static int dsi_phy_enable_ulps(struct msm_dsi_phy *phy,
  716. struct dsi_host_config *config, bool clamp_enabled)
  717. {
  718. int rc = 0;
  719. u32 lanes = 0;
  720. u32 ulps_lanes;
  721. lanes = config->common_config.data_lanes;
  722. if (!dsi_is_type_cphy(&config->common_config))
  723. lanes |= DSI_CLOCK_LANE;
  724. /*
  725. * If DSI clamps are enabled, it means that the DSI lanes are
  726. * already in idle state. Checking for lanes to be in idle state
  727. * should be skipped during ULPS entry programming while coming
  728. * out of idle screen.
  729. */
  730. if (!clamp_enabled) {
  731. rc = phy->hw.ops.ulps_ops.wait_for_lane_idle(&phy->hw, lanes);
  732. if (rc) {
  733. DSI_PHY_ERR(phy, "lanes not entering idle, skip ULPS\n");
  734. return rc;
  735. }
  736. }
  737. phy->hw.ops.ulps_ops.ulps_request(&phy->hw, &phy->cfg, lanes);
  738. ulps_lanes = phy->hw.ops.ulps_ops.get_lanes_in_ulps(&phy->hw);
  739. if (!phy->hw.ops.ulps_ops.is_lanes_in_ulps(lanes, ulps_lanes)) {
  740. DSI_PHY_ERR(phy, "Failed to enter ULPS, request=0x%x, actual=0x%x\n",
  741. lanes, ulps_lanes);
  742. rc = -EIO;
  743. }
  744. return rc;
  745. }
  746. static int dsi_phy_disable_ulps(struct msm_dsi_phy *phy,
  747. struct dsi_host_config *config)
  748. {
  749. u32 ulps_lanes, lanes = 0;
  750. lanes = config->common_config.data_lanes;
  751. if (!dsi_is_type_cphy(&config->common_config))
  752. lanes |= DSI_CLOCK_LANE;
  753. ulps_lanes = phy->hw.ops.ulps_ops.get_lanes_in_ulps(&phy->hw);
  754. if (!phy->hw.ops.ulps_ops.is_lanes_in_ulps(lanes, ulps_lanes)) {
  755. DSI_PHY_ERR(phy, "Mismatch in ULPS: lanes:%d, ulps_lanes:%d\n",
  756. lanes, ulps_lanes);
  757. return -EIO;
  758. }
  759. phy->hw.ops.ulps_ops.ulps_exit(&phy->hw, &phy->cfg, lanes);
  760. ulps_lanes = phy->hw.ops.ulps_ops.get_lanes_in_ulps(&phy->hw);
  761. if (phy->hw.ops.ulps_ops.is_lanes_in_ulps(lanes, ulps_lanes)) {
  762. DSI_PHY_ERR(phy, "Lanes (0x%x) stuck in ULPS\n", ulps_lanes);
  763. return -EIO;
  764. }
  765. return 0;
  766. }
  767. void dsi_phy_toggle_resync_fifo(struct msm_dsi_phy *phy)
  768. {
  769. if (!phy)
  770. return;
  771. if (!phy->hw.ops.toggle_resync_fifo)
  772. return;
  773. phy->hw.ops.toggle_resync_fifo(&phy->hw);
  774. }
  775. void dsi_phy_reset_clk_en_sel(struct msm_dsi_phy *phy)
  776. {
  777. if (!phy)
  778. return;
  779. if (!phy->hw.ops.reset_clk_en_sel)
  780. return;
  781. phy->hw.ops.reset_clk_en_sel(&phy->hw);
  782. }
  783. int dsi_phy_set_ulps(struct msm_dsi_phy *phy, struct dsi_host_config *config,
  784. bool enable, bool clamp_enabled)
  785. {
  786. int rc = 0;
  787. if (!phy) {
  788. DSI_PHY_ERR(phy, "Invalid params\n");
  789. return DSI_PHY_ULPS_ERROR;
  790. }
  791. if (!phy->hw.ops.ulps_ops.ulps_request ||
  792. !phy->hw.ops.ulps_ops.ulps_exit ||
  793. !phy->hw.ops.ulps_ops.get_lanes_in_ulps ||
  794. !phy->hw.ops.ulps_ops.is_lanes_in_ulps ||
  795. !phy->hw.ops.ulps_ops.wait_for_lane_idle) {
  796. DSI_PHY_DBG(phy, "DSI PHY ULPS ops not present\n");
  797. return DSI_PHY_ULPS_NOT_HANDLED;
  798. }
  799. mutex_lock(&phy->phy_lock);
  800. if (enable)
  801. rc = dsi_phy_enable_ulps(phy, config, clamp_enabled);
  802. else
  803. rc = dsi_phy_disable_ulps(phy, config);
  804. if (rc) {
  805. DSI_PHY_ERR(phy, "Ulps state change(%d) failed, rc=%d\n",
  806. enable, rc);
  807. rc = DSI_PHY_ULPS_ERROR;
  808. goto error;
  809. }
  810. DSI_PHY_DBG(phy, "ULPS state = %d\n", enable);
  811. error:
  812. mutex_unlock(&phy->phy_lock);
  813. return rc;
  814. }
  815. /**
  816. * dsi_phy_enable() - enable DSI PHY hardware
  817. * @dsi_phy: DSI PHY handle.
  818. * @config: DSI host configuration.
  819. * @pll_source: Source PLL for PHY clock.
  820. * @skip_validation: Validation will not be performed on parameters.
  821. * @skip_op: Skip re-enabling dsi phy hw during usecases like
  822. * cont-splash/trusted-vm if set to true.
  823. *
  824. * Validates and enables DSI PHY.
  825. *
  826. * Return: error code.
  827. */
  828. int dsi_phy_enable(struct msm_dsi_phy *phy,
  829. struct dsi_host_config *config,
  830. enum dsi_phy_pll_source pll_source,
  831. bool skip_validation,
  832. bool skip_op)
  833. {
  834. int rc = 0;
  835. if (!phy || !config) {
  836. DSI_PHY_ERR(phy, "Invalid params\n");
  837. return -EINVAL;
  838. }
  839. mutex_lock(&phy->phy_lock);
  840. if (!skip_validation)
  841. DSI_PHY_DBG(phy, "TODO: perform validation\n");
  842. memcpy(&phy->mode, &config->video_timing, sizeof(phy->mode));
  843. memcpy(&phy->cfg.lane_map, &config->lane_map, sizeof(config->lane_map));
  844. phy->data_lanes = config->common_config.data_lanes;
  845. phy->dst_format = config->common_config.dst_format;
  846. phy->cfg.pll_source = pll_source;
  847. phy->cfg.bit_clk_rate_hz = config->bit_clk_rate_hz;
  848. /**
  849. * If PHY timing parameters are not present in panel dtsi file,
  850. * then calculate them in the driver
  851. */
  852. if (!phy->cfg.is_phy_timing_present)
  853. rc = phy->hw.ops.calculate_timing_params(&phy->hw,
  854. &phy->mode,
  855. &config->common_config,
  856. &phy->cfg.timing, false);
  857. if (rc) {
  858. DSI_PHY_ERR(phy, "failed to set timing, rc=%d\n", rc);
  859. goto error;
  860. }
  861. if (!skip_op) {
  862. dsi_phy_enable_hw(phy);
  863. DSI_PHY_DBG(phy, "cont splash not enabled, phy enable required\n");
  864. }
  865. phy->dsi_phy_state = DSI_PHY_ENGINE_ON;
  866. error:
  867. mutex_unlock(&phy->phy_lock);
  868. return rc;
  869. }
  870. /* update dsi phy timings for dynamic clk switch use case */
  871. int dsi_phy_update_phy_timings(struct msm_dsi_phy *phy,
  872. struct dsi_host_config *config)
  873. {
  874. int rc = 0;
  875. if (!phy || !config) {
  876. DSI_PHY_ERR(phy, "invalid argument\n");
  877. return -EINVAL;
  878. }
  879. memcpy(&phy->mode, &config->video_timing, sizeof(phy->mode));
  880. rc = phy->hw.ops.calculate_timing_params(&phy->hw, &phy->mode,
  881. &config->common_config,
  882. &phy->cfg.timing, true);
  883. if (rc)
  884. DSI_PHY_ERR(phy, "failed to calculate phy timings %d\n", rc);
  885. return rc;
  886. }
  887. int dsi_phy_lane_reset(struct msm_dsi_phy *phy)
  888. {
  889. int ret = 0;
  890. if (!phy)
  891. return ret;
  892. mutex_lock(&phy->phy_lock);
  893. if (phy->hw.ops.phy_lane_reset)
  894. ret = phy->hw.ops.phy_lane_reset(&phy->hw);
  895. mutex_unlock(&phy->phy_lock);
  896. return ret;
  897. }
  898. /**
  899. * dsi_phy_disable() - disable DSI PHY hardware.
  900. * @phy: DSI PHY handle.
  901. * @skip_op: Skip disabling dsi phy hw during usecases like
  902. * trusted-vm if set to true.
  903. *
  904. * Return: error code.
  905. */
  906. int dsi_phy_disable(struct msm_dsi_phy *phy, bool skip_op)
  907. {
  908. int rc = 0;
  909. if (!phy) {
  910. DSI_PHY_ERR(phy, "Invalid params\n");
  911. return -EINVAL;
  912. }
  913. mutex_lock(&phy->phy_lock);
  914. if (!skip_op)
  915. dsi_phy_disable_hw(phy);
  916. phy->dsi_phy_state = DSI_PHY_ENGINE_OFF;
  917. mutex_unlock(&phy->phy_lock);
  918. return rc;
  919. }
  920. /**
  921. * dsi_phy_set_clamp_state() - configure clamps for DSI lanes
  922. * @phy: DSI PHY handle.
  923. * @enable: boolean to specify clamp enable/disable.
  924. *
  925. * Return: error code.
  926. */
  927. int dsi_phy_set_clamp_state(struct msm_dsi_phy *phy, bool enable)
  928. {
  929. if (!phy)
  930. return -EINVAL;
  931. DSI_PHY_DBG(phy, "enable=%d\n", enable);
  932. if (phy->hw.ops.clamp_ctrl)
  933. phy->hw.ops.clamp_ctrl(&phy->hw, enable);
  934. return 0;
  935. }
  936. /**
  937. * dsi_phy_idle_ctrl() - enable/disable DSI PHY during idle screen
  938. * @phy: DSI PHY handle
  939. * @enable: boolean to specify PHY enable/disable.
  940. *
  941. * Return: error code.
  942. */
  943. int dsi_phy_idle_ctrl(struct msm_dsi_phy *phy, bool enable)
  944. {
  945. if (!phy) {
  946. DSI_PHY_ERR(phy, "Invalid params\n");
  947. return -EINVAL;
  948. }
  949. DSI_PHY_DBG(phy, "enable=%d\n", enable);
  950. mutex_lock(&phy->phy_lock);
  951. if (enable) {
  952. if (phy->hw.ops.phy_idle_on)
  953. phy->hw.ops.phy_idle_on(&phy->hw, &phy->cfg);
  954. if (phy->hw.ops.regulator_enable)
  955. phy->hw.ops.regulator_enable(&phy->hw,
  956. &phy->cfg.regulators);
  957. if (phy->hw.ops.enable)
  958. phy->hw.ops.enable(&phy->hw, &phy->cfg);
  959. phy->dsi_phy_state = DSI_PHY_ENGINE_ON;
  960. } else {
  961. phy->dsi_phy_state = DSI_PHY_ENGINE_OFF;
  962. if (phy->hw.ops.disable)
  963. phy->hw.ops.disable(&phy->hw, &phy->cfg);
  964. if (phy->hw.ops.phy_idle_off)
  965. phy->hw.ops.phy_idle_off(&phy->hw);
  966. }
  967. mutex_unlock(&phy->phy_lock);
  968. return 0;
  969. }
  970. /**
  971. * dsi_phy_set_clk_freq() - set DSI PHY clock frequency setting
  972. * @phy: DSI PHY handle
  973. * @clk_freq: link clock frequency
  974. *
  975. * Return: error code.
  976. */
  977. int dsi_phy_set_clk_freq(struct msm_dsi_phy *phy,
  978. struct link_clk_freq *clk_freq)
  979. {
  980. if (!phy || !clk_freq) {
  981. DSI_PHY_ERR(phy, "Invalid params\n");
  982. return -EINVAL;
  983. }
  984. phy->regulator_required = clk_freq->byte_clk_rate >
  985. (phy->regulator_min_datarate_bps / BITS_PER_BYTE);
  986. /*
  987. * DSI PLL needs 0p9 LDO1A for Powering DSI PLL block.
  988. * PLL driver can vote for this regulator in PLL driver file, but for
  989. * the usecase where we come out of idle(static screen), if PLL and
  990. * PHY vote for regulator ,there will be performance delays as both
  991. * votes go through RPM to enable regulators.
  992. */
  993. phy->regulator_required = true;
  994. DSI_PHY_DBG(phy, "lane_datarate=%u min_datarate=%u required=%d\n",
  995. clk_freq->byte_clk_rate * BITS_PER_BYTE,
  996. phy->regulator_min_datarate_bps,
  997. phy->regulator_required);
  998. return 0;
  999. }
  1000. /**
  1001. * dsi_phy_set_timing_params() - timing parameters for the panel
  1002. * @phy: DSI PHY handle
  1003. * @timing: array holding timing params.
  1004. * @size: size of the array.
  1005. * @commit: boolean to indicate if programming PHY HW registers is
  1006. * required
  1007. *
  1008. * When PHY timing calculator is not implemented, this array will be used to
  1009. * pass PHY timing information.
  1010. *
  1011. * Return: error code.
  1012. */
  1013. int dsi_phy_set_timing_params(struct msm_dsi_phy *phy,
  1014. u32 *timing, u32 size, bool commit)
  1015. {
  1016. int rc = 0;
  1017. if (!phy || !timing || !size) {
  1018. DSI_PHY_ERR(phy, "Invalid params\n");
  1019. return -EINVAL;
  1020. }
  1021. mutex_lock(&phy->phy_lock);
  1022. if (phy->hw.ops.phy_timing_val)
  1023. rc = phy->hw.ops.phy_timing_val(&phy->cfg.timing, timing, size);
  1024. if (!rc)
  1025. phy->cfg.is_phy_timing_present = true;
  1026. if (phy->hw.ops.commit_phy_timing && commit)
  1027. phy->hw.ops.commit_phy_timing(&phy->hw, &phy->cfg.timing);
  1028. mutex_unlock(&phy->phy_lock);
  1029. return rc;
  1030. }
  1031. /**
  1032. * dsi_phy_conv_phy_to_logical_lane() - Convert physical to logical lane
  1033. * @lane_map: logical lane
  1034. * @phy_lane: physical lane
  1035. *
  1036. * Return: Error code on failure. Lane number on success.
  1037. */
  1038. int dsi_phy_conv_phy_to_logical_lane(
  1039. struct dsi_lane_map *lane_map, enum dsi_phy_data_lanes phy_lane)
  1040. {
  1041. int i = 0;
  1042. if (phy_lane > DSI_PHYSICAL_LANE_3)
  1043. return -EINVAL;
  1044. for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++) {
  1045. if (lane_map->lane_map_v2[i] == phy_lane)
  1046. break;
  1047. }
  1048. return i;
  1049. }
  1050. /**
  1051. * dsi_phy_conv_logical_to_phy_lane() - Convert logical to physical lane
  1052. * @lane_map: physical lane
  1053. * @lane: logical lane
  1054. *
  1055. * Return: Error code on failure. Lane number on success.
  1056. */
  1057. int dsi_phy_conv_logical_to_phy_lane(
  1058. struct dsi_lane_map *lane_map, enum dsi_logical_lane lane)
  1059. {
  1060. int i = 0;
  1061. if (lane > (DSI_LANE_MAX - 1))
  1062. return -EINVAL;
  1063. for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++) {
  1064. if (BIT(i) == lane_map->lane_map_v2[lane])
  1065. break;
  1066. }
  1067. return i;
  1068. }
  1069. /**
  1070. * dsi_phy_config_dynamic_refresh() - Configure dynamic refresh registers
  1071. * @phy: DSI PHY handle
  1072. * @delay: pipe delays for dynamic refresh
  1073. * @is_master: Boolean to indicate if for master or slave.
  1074. */
  1075. void dsi_phy_config_dynamic_refresh(struct msm_dsi_phy *phy,
  1076. struct dsi_dyn_clk_delay *delay,
  1077. bool is_master)
  1078. {
  1079. struct dsi_phy_cfg *cfg;
  1080. if (!phy)
  1081. return;
  1082. mutex_lock(&phy->phy_lock);
  1083. cfg = &phy->cfg;
  1084. if (phy->hw.ops.dyn_refresh_ops.dyn_refresh_config)
  1085. phy->hw.ops.dyn_refresh_ops.dyn_refresh_config(&phy->hw, cfg,
  1086. is_master);
  1087. if (phy->hw.ops.dyn_refresh_ops.dyn_refresh_pipe_delay)
  1088. phy->hw.ops.dyn_refresh_ops.dyn_refresh_pipe_delay(
  1089. &phy->hw, delay);
  1090. mutex_unlock(&phy->phy_lock);
  1091. }
  1092. /**
  1093. * dsi_phy_dynamic_refresh_trigger_sel() - trigger dynamic refresh and
  1094. * update the video timings at next frame flush call.
  1095. * @phy: DSI PHY handle
  1096. * @is_master: Boolean to indicate if for master or slave.
  1097. */
  1098. void dsi_phy_dynamic_refresh_trigger_sel(struct msm_dsi_phy *phy,
  1099. bool is_master)
  1100. {
  1101. if (!phy)
  1102. return;
  1103. mutex_lock(&phy->phy_lock);
  1104. /*
  1105. * program DYNAMIC_REFRESH_CTRL.TRIGGER_SEL for master.
  1106. */
  1107. if (phy->hw.ops.dyn_refresh_ops.dyn_refresh_trigger_sel)
  1108. phy->hw.ops.dyn_refresh_ops.dyn_refresh_trigger_sel
  1109. (&phy->hw, is_master);
  1110. phy->dfps_trigger_mdpintf_flush = true;
  1111. SDE_EVT32(is_master, phy->index);
  1112. mutex_unlock(&phy->phy_lock);
  1113. }
  1114. /**
  1115. * dsi_phy_dynamic_refresh_trigger() - trigger dynamic refresh
  1116. * @phy: DSI PHY handle
  1117. * @is_master: Boolean to indicate if for master or slave.
  1118. */
  1119. void dsi_phy_dynamic_refresh_trigger(struct msm_dsi_phy *phy, bool is_master)
  1120. {
  1121. u32 off;
  1122. if (!phy)
  1123. return;
  1124. mutex_lock(&phy->phy_lock);
  1125. /*
  1126. * program PLL_SWI_INTF_SEL and SW_TRIGGER bit only for
  1127. * master and program SYNC_MODE bit only for slave.
  1128. */
  1129. if (is_master)
  1130. off = BIT(DYN_REFRESH_INTF_SEL) | BIT(DYN_REFRESH_SWI_CTRL) |
  1131. BIT(DYN_REFRESH_SW_TRIGGER);
  1132. else
  1133. off = BIT(DYN_REFRESH_SYNC_MODE) | BIT(DYN_REFRESH_SWI_CTRL);
  1134. if (phy->hw.ops.dyn_refresh_ops.dyn_refresh_helper)
  1135. phy->hw.ops.dyn_refresh_ops.dyn_refresh_helper(&phy->hw, off);
  1136. mutex_unlock(&phy->phy_lock);
  1137. }
  1138. /**
  1139. * dsi_phy_cache_phy_timings - cache the phy timings calculated as part of
  1140. * dynamic refresh.
  1141. * @phy: DSI PHY Handle.
  1142. * @dst: Pointer to cache location.
  1143. * @size: Number of phy lane settings.
  1144. */
  1145. int dsi_phy_dyn_refresh_cache_phy_timings(struct msm_dsi_phy *phy, u32 *dst,
  1146. u32 size)
  1147. {
  1148. int rc = 0;
  1149. if (!phy || !dst || !size)
  1150. return -EINVAL;
  1151. if (phy->hw.ops.dyn_refresh_ops.cache_phy_timings)
  1152. rc = phy->hw.ops.dyn_refresh_ops.cache_phy_timings(
  1153. &phy->cfg.timing, dst, size);
  1154. if (rc)
  1155. DSI_PHY_ERR(phy, "failed to cache phy timings %d\n", rc);
  1156. return rc;
  1157. }
  1158. /**
  1159. * dsi_phy_dynamic_refresh_clear() - clear dynamic refresh config
  1160. * @phy: DSI PHY handle
  1161. */
  1162. void dsi_phy_dynamic_refresh_clear(struct msm_dsi_phy *phy)
  1163. {
  1164. if (!phy)
  1165. return;
  1166. mutex_lock(&phy->phy_lock);
  1167. if (phy->hw.ops.dyn_refresh_ops.dyn_refresh_helper)
  1168. phy->hw.ops.dyn_refresh_ops.dyn_refresh_helper(&phy->hw, 0);
  1169. mutex_unlock(&phy->phy_lock);
  1170. }
  1171. /**
  1172. * dsi_phy_set_continuous_clk() - set/unset force clock lane HS request
  1173. * @phy: DSI PHY handle
  1174. * @enable: variable to control continuous clock
  1175. */
  1176. void dsi_phy_set_continuous_clk(struct msm_dsi_phy *phy, bool enable)
  1177. {
  1178. if (!phy)
  1179. return;
  1180. mutex_lock(&phy->phy_lock);
  1181. if (phy->hw.ops.set_continuous_clk)
  1182. phy->hw.ops.set_continuous_clk(&phy->hw, enable);
  1183. else
  1184. DSI_PHY_WARN(phy, "set_continuous_clk ops not present\n");
  1185. mutex_unlock(&phy->phy_lock);
  1186. }
  1187. /**
  1188. * dsi_phy_pll_parse_dfps_data() - parse dfps data for PLL
  1189. * @phy: DSI PHY handle
  1190. */
  1191. void dsi_phy_pll_parse_dfps_data(struct msm_dsi_phy *phy)
  1192. {
  1193. dsi_pll_parse_dfps_data(phy->pdev, phy->pll);
  1194. }
  1195. void dsi_phy_drv_register(void)
  1196. {
  1197. platform_driver_register(&dsi_phy_platform_driver);
  1198. }
  1199. void dsi_phy_drv_unregister(void)
  1200. {
  1201. platform_driver_unregister(&dsi_phy_platform_driver);
  1202. }