dsi_drm.c 44 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #include <drm/drm_atomic_helper.h>
  7. #include <drm/drm_atomic.h>
  8. #include "msm_kms.h"
  9. #include "sde_connector.h"
  10. #include "dsi_drm.h"
  11. #include "sde_trace.h"
  12. #include "sde_dbg.h"
  13. #include "msm_drv.h"
  14. #include "sde_encoder.h"
  15. #define to_dsi_bridge(x) container_of((x), struct dsi_bridge, base)
  16. #define to_dsi_state(x) container_of((x), struct dsi_connector_state, base)
  17. #define DEFAULT_PANEL_JITTER_NUMERATOR 2
  18. #define DEFAULT_PANEL_JITTER_DENOMINATOR 1
  19. #define DEFAULT_PANEL_JITTER_ARRAY_SIZE 2
  20. #define DEFAULT_PANEL_PREFILL_LINES 25
  21. static struct dsi_display_mode_priv_info default_priv_info = {
  22. .panel_jitter_numer = DEFAULT_PANEL_JITTER_NUMERATOR,
  23. .panel_jitter_denom = DEFAULT_PANEL_JITTER_DENOMINATOR,
  24. .panel_prefill_lines = DEFAULT_PANEL_PREFILL_LINES,
  25. .dsc_enabled = false,
  26. };
  27. static void convert_to_dsi_mode(const struct drm_display_mode *drm_mode,
  28. struct dsi_display_mode *dsi_mode)
  29. {
  30. memset(dsi_mode, 0, sizeof(*dsi_mode));
  31. dsi_mode->timing.h_active = drm_mode->hdisplay;
  32. dsi_mode->timing.h_back_porch = drm_mode->htotal - drm_mode->hsync_end;
  33. dsi_mode->timing.h_sync_width = drm_mode->htotal -
  34. (drm_mode->hsync_start + dsi_mode->timing.h_back_porch);
  35. dsi_mode->timing.h_front_porch = drm_mode->hsync_start -
  36. drm_mode->hdisplay;
  37. dsi_mode->timing.h_skew = drm_mode->hskew;
  38. dsi_mode->timing.v_active = drm_mode->vdisplay;
  39. dsi_mode->timing.v_back_porch = drm_mode->vtotal - drm_mode->vsync_end;
  40. dsi_mode->timing.v_sync_width = drm_mode->vtotal -
  41. (drm_mode->vsync_start + dsi_mode->timing.v_back_porch);
  42. dsi_mode->timing.v_front_porch = drm_mode->vsync_start -
  43. drm_mode->vdisplay;
  44. dsi_mode->timing.refresh_rate = drm_mode_vrefresh(drm_mode);
  45. dsi_mode->timing.h_sync_polarity =
  46. !!(drm_mode->flags & DRM_MODE_FLAG_PHSYNC);
  47. dsi_mode->timing.v_sync_polarity =
  48. !!(drm_mode->flags & DRM_MODE_FLAG_PVSYNC);
  49. }
  50. static void msm_parse_mode_priv_info(const struct msm_display_mode *msm_mode,
  51. struct dsi_display_mode *dsi_mode)
  52. {
  53. dsi_mode->priv_info =
  54. (struct dsi_display_mode_priv_info *)msm_mode->private;
  55. if (dsi_mode->priv_info) {
  56. dsi_mode->timing.dsc_enabled = dsi_mode->priv_info->dsc_enabled;
  57. dsi_mode->timing.dsc = &dsi_mode->priv_info->dsc;
  58. dsi_mode->timing.vdc_enabled = dsi_mode->priv_info->vdc_enabled;
  59. dsi_mode->timing.vdc = &dsi_mode->priv_info->vdc;
  60. dsi_mode->timing.pclk_scale = dsi_mode->priv_info->pclk_scale;
  61. dsi_mode->timing.clk_rate_hz = dsi_mode->priv_info->clk_rate_hz;
  62. }
  63. if (msm_is_mode_seamless(msm_mode))
  64. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_SEAMLESS;
  65. if (msm_is_mode_dynamic_fps(msm_mode))
  66. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS;
  67. if (msm_needs_vblank_pre_modeset(msm_mode))
  68. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  69. if (msm_is_mode_seamless_dms(msm_mode))
  70. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  71. if (msm_is_mode_seamless_vrr(msm_mode))
  72. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  73. if (msm_is_mode_seamless_poms_to_vid(msm_mode))
  74. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS_TO_VID;
  75. if (msm_is_mode_seamless_poms_to_cmd(msm_mode))
  76. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS_TO_CMD;
  77. if (msm_is_mode_seamless_dyn_clk(msm_mode))
  78. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DYN_CLK;
  79. }
  80. void dsi_convert_to_drm_mode(const struct dsi_display_mode *dsi_mode,
  81. struct drm_display_mode *drm_mode)
  82. {
  83. char *panel_caps = "vid";
  84. if ((dsi_mode->panel_mode_caps & DSI_OP_VIDEO_MODE) &&
  85. (dsi_mode->panel_mode_caps & DSI_OP_CMD_MODE))
  86. panel_caps = "vid_cmd";
  87. else if (dsi_mode->panel_mode_caps & DSI_OP_VIDEO_MODE)
  88. panel_caps = "vid";
  89. else if (dsi_mode->panel_mode_caps & DSI_OP_CMD_MODE)
  90. panel_caps = "cmd";
  91. memset(drm_mode, 0, sizeof(*drm_mode));
  92. drm_mode->hdisplay = dsi_mode->timing.h_active;
  93. drm_mode->hsync_start = drm_mode->hdisplay +
  94. dsi_mode->timing.h_front_porch;
  95. drm_mode->hsync_end = drm_mode->hsync_start +
  96. dsi_mode->timing.h_sync_width;
  97. drm_mode->htotal = drm_mode->hsync_end + dsi_mode->timing.h_back_porch;
  98. drm_mode->hskew = dsi_mode->timing.h_skew;
  99. drm_mode->vdisplay = dsi_mode->timing.v_active;
  100. drm_mode->vsync_start = drm_mode->vdisplay +
  101. dsi_mode->timing.v_front_porch;
  102. drm_mode->vsync_end = drm_mode->vsync_start +
  103. dsi_mode->timing.v_sync_width;
  104. drm_mode->vtotal = drm_mode->vsync_end + dsi_mode->timing.v_back_porch;
  105. drm_mode->clock = drm_mode->htotal * drm_mode->vtotal * dsi_mode->timing.refresh_rate;
  106. drm_mode->clock /= 1000;
  107. if (dsi_mode->timing.h_sync_polarity)
  108. drm_mode->flags |= DRM_MODE_FLAG_PHSYNC;
  109. if (dsi_mode->timing.v_sync_polarity)
  110. drm_mode->flags |= DRM_MODE_FLAG_PVSYNC;
  111. /* set mode name */
  112. snprintf(drm_mode->name, DRM_DISPLAY_MODE_LEN, "%dx%dx%d%s",
  113. drm_mode->hdisplay, drm_mode->vdisplay,
  114. drm_mode_vrefresh(drm_mode), panel_caps);
  115. }
  116. static void dsi_convert_to_msm_mode(const struct dsi_display_mode *dsi_mode,
  117. struct msm_display_mode *msm_mode)
  118. {
  119. msm_mode->private_flags = 0;
  120. msm_mode->private = (int *)dsi_mode->priv_info;
  121. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)
  122. msm_mode->private_flags |= DRM_MODE_FLAG_SEAMLESS;
  123. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DFPS)
  124. msm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYNAMIC_FPS;
  125. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VBLANK_PRE_MODESET)
  126. msm_mode->private_flags |= MSM_MODE_FLAG_VBLANK_PRE_MODESET;
  127. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DMS)
  128. msm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DMS;
  129. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VRR)
  130. msm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_VRR;
  131. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_VID)
  132. msm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_POMS_VID;
  133. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_CMD)
  134. msm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_POMS_CMD;
  135. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)
  136. msm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYN_CLK;
  137. }
  138. static int dsi_bridge_attach(struct drm_bridge *bridge,
  139. enum drm_bridge_attach_flags flags)
  140. {
  141. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  142. if (!bridge) {
  143. DSI_ERR("Invalid params\n");
  144. return -EINVAL;
  145. }
  146. DSI_DEBUG("[%d] attached\n", c_bridge->id);
  147. return 0;
  148. }
  149. static void dsi_bridge_pre_enable(struct drm_bridge *bridge)
  150. {
  151. int rc = 0;
  152. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  153. if (!bridge) {
  154. DSI_ERR("Invalid params\n");
  155. return;
  156. }
  157. if (!c_bridge || !c_bridge->display || !c_bridge->display->panel) {
  158. DSI_ERR("Incorrect bridge details\n");
  159. return;
  160. }
  161. atomic_set(&c_bridge->display->panel->esd_recovery_pending, 0);
  162. /* By this point mode should have been validated through mode_fixup */
  163. rc = dsi_display_set_mode(c_bridge->display,
  164. &(c_bridge->dsi_mode), 0x0);
  165. if (rc) {
  166. DSI_ERR("[%d] failed to perform a mode set, rc=%d\n",
  167. c_bridge->id, rc);
  168. return;
  169. }
  170. if (c_bridge->dsi_mode.dsi_mode_flags &
  171. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  172. DSI_MODE_FLAG_DYN_CLK)) {
  173. DSI_DEBUG("[%d] seamless pre-enable\n", c_bridge->id);
  174. return;
  175. }
  176. SDE_ATRACE_BEGIN("dsi_display_prepare");
  177. rc = dsi_display_prepare(c_bridge->display);
  178. if (rc) {
  179. DSI_ERR("[%d] DSI display prepare failed, rc=%d\n",
  180. c_bridge->id, rc);
  181. SDE_ATRACE_END("dsi_display_prepare");
  182. return;
  183. }
  184. SDE_ATRACE_END("dsi_display_prepare");
  185. SDE_ATRACE_BEGIN("dsi_display_enable");
  186. rc = dsi_display_enable(c_bridge->display);
  187. if (rc) {
  188. DSI_ERR("[%d] DSI display enable failed, rc=%d\n",
  189. c_bridge->id, rc);
  190. (void)dsi_display_unprepare(c_bridge->display);
  191. }
  192. SDE_ATRACE_END("dsi_display_enable");
  193. rc = dsi_display_splash_res_cleanup(c_bridge->display);
  194. if (rc)
  195. DSI_ERR("Continuous splash pipeline cleanup failed, rc=%d\n",
  196. rc);
  197. }
  198. static void dsi_bridge_enable(struct drm_bridge *bridge)
  199. {
  200. int rc = 0;
  201. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  202. struct dsi_display *display;
  203. if (!bridge) {
  204. DSI_ERR("Invalid params\n");
  205. return;
  206. }
  207. if (c_bridge->dsi_mode.dsi_mode_flags &
  208. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  209. DSI_MODE_FLAG_DYN_CLK)) {
  210. DSI_DEBUG("[%d] seamless enable\n", c_bridge->id);
  211. return;
  212. }
  213. display = c_bridge->display;
  214. rc = dsi_display_post_enable(display);
  215. if (rc)
  216. DSI_ERR("[%d] DSI display post enabled failed, rc=%d\n",
  217. c_bridge->id, rc);
  218. if (display)
  219. display->enabled = true;
  220. if (display && display->drm_conn) {
  221. sde_connector_helper_bridge_enable(display->drm_conn);
  222. if (display->poms_pending) {
  223. display->poms_pending = false;
  224. sde_connector_schedule_status_work(display->drm_conn,
  225. true);
  226. }
  227. }
  228. }
  229. static void dsi_bridge_disable(struct drm_bridge *bridge)
  230. {
  231. int rc = 0;
  232. struct dsi_display *display;
  233. struct sde_connector_state *conn_state;
  234. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  235. if (!bridge) {
  236. DSI_ERR("Invalid params\n");
  237. return;
  238. }
  239. display = c_bridge->display;
  240. if (display)
  241. display->enabled = false;
  242. if (display && display->drm_conn) {
  243. conn_state = to_sde_connector_state(display->drm_conn->state);
  244. if (!conn_state) {
  245. DSI_ERR("invalid params\n");
  246. return;
  247. }
  248. display->poms_pending = msm_is_mode_seamless_poms(
  249. &conn_state->msm_mode);
  250. sde_connector_helper_bridge_disable(display->drm_conn);
  251. }
  252. rc = dsi_display_pre_disable(c_bridge->display);
  253. if (rc) {
  254. DSI_ERR("[%d] DSI display pre disable failed, rc=%d\n",
  255. c_bridge->id, rc);
  256. }
  257. }
  258. static void dsi_bridge_post_disable(struct drm_bridge *bridge)
  259. {
  260. int rc = 0;
  261. struct dsi_display *display;
  262. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  263. if (!bridge) {
  264. DSI_ERR("Invalid params\n");
  265. return;
  266. }
  267. display = c_bridge->display;
  268. SDE_ATRACE_BEGIN("dsi_bridge_post_disable");
  269. SDE_ATRACE_BEGIN("dsi_display_disable");
  270. rc = dsi_display_disable(c_bridge->display);
  271. if (rc) {
  272. DSI_ERR("[%d] DSI display disable failed, rc=%d\n",
  273. c_bridge->id, rc);
  274. SDE_ATRACE_END("dsi_display_disable");
  275. return;
  276. }
  277. SDE_ATRACE_END("dsi_display_disable");
  278. if (display && display->drm_conn)
  279. sde_connector_helper_bridge_post_disable(display->drm_conn);
  280. rc = dsi_display_unprepare(c_bridge->display);
  281. if (rc) {
  282. DSI_ERR("[%d] DSI display unprepare failed, rc=%d\n",
  283. c_bridge->id, rc);
  284. SDE_ATRACE_END("dsi_bridge_post_disable");
  285. return;
  286. }
  287. SDE_ATRACE_END("dsi_bridge_post_disable");
  288. }
  289. static void dsi_bridge_mode_set(struct drm_bridge *bridge,
  290. const struct drm_display_mode *mode,
  291. const struct drm_display_mode *adjusted_mode)
  292. {
  293. int rc = 0;
  294. struct dsi_bridge *c_bridge = NULL;
  295. struct dsi_display *display;
  296. struct drm_connector *conn;
  297. struct sde_connector_state *conn_state;
  298. if (!bridge || !mode || !adjusted_mode) {
  299. DSI_ERR("Invalid params\n");
  300. return;
  301. }
  302. c_bridge = to_dsi_bridge(bridge);
  303. if (!c_bridge) {
  304. DSI_ERR("invalid dsi bridge\n");
  305. return;
  306. }
  307. display = c_bridge->display;
  308. if (!display || !display->drm_conn || !display->drm_conn->state) {
  309. DSI_ERR("invalid display\n");
  310. return;
  311. }
  312. memset(&(c_bridge->dsi_mode), 0x0, sizeof(struct dsi_display_mode));
  313. convert_to_dsi_mode(adjusted_mode, &(c_bridge->dsi_mode));
  314. conn = sde_encoder_get_connector(bridge->dev, bridge->encoder);
  315. if (!conn)
  316. return;
  317. conn_state = to_sde_connector_state(conn->state);
  318. if (!conn_state) {
  319. DSI_ERR("invalid connector state\n");
  320. return;
  321. }
  322. msm_parse_mode_priv_info(&conn_state->msm_mode,
  323. &(c_bridge->dsi_mode));
  324. rc = dsi_display_restore_bit_clk(display, &c_bridge->dsi_mode);
  325. if (rc) {
  326. DSI_ERR("[%s] bit clk rate cannot be restored\n", display->name);
  327. return;
  328. }
  329. DSI_DEBUG("clk_rate: %llu\n", c_bridge->dsi_mode.timing.clk_rate_hz);
  330. }
  331. static bool _dsi_bridge_mode_validate_and_fixup(struct drm_bridge *bridge,
  332. struct drm_crtc_state *crtc_state, struct dsi_display *display,
  333. struct dsi_display_mode *adj_mode)
  334. {
  335. int rc = 0;
  336. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  337. struct dsi_display_mode cur_dsi_mode;
  338. struct sde_connector_state *old_conn_state;
  339. struct drm_display_mode *cur_mode;
  340. if (!bridge->encoder || !bridge->encoder->crtc || !crtc_state->crtc)
  341. return 0;
  342. cur_mode = &crtc_state->crtc->state->mode;
  343. old_conn_state = to_sde_connector_state(display->drm_conn->state);
  344. convert_to_dsi_mode(cur_mode, &cur_dsi_mode);
  345. msm_parse_mode_priv_info(&old_conn_state->msm_mode, &cur_dsi_mode);
  346. rc = dsi_display_validate_mode_change(c_bridge->display, &cur_dsi_mode, adj_mode);
  347. if (rc) {
  348. DSI_ERR("[%s] seamless mode mismatch failure rc=%d\n", c_bridge->display->name, rc);
  349. return rc;
  350. }
  351. /*
  352. * DMS Flag if set during active changed condition cannot be
  353. * treated as seamless. Hence, removing DMS flag in such cases.
  354. */
  355. if ((adj_mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) &&
  356. crtc_state->active_changed)
  357. adj_mode->dsi_mode_flags &= ~DSI_MODE_FLAG_DMS;
  358. /* No DMS/VRR when drm pipeline is changing */
  359. if (!dsi_display_mode_match(&cur_dsi_mode, adj_mode,
  360. DSI_MODE_MATCH_FULL_TIMINGS) &&
  361. (!(adj_mode->dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
  362. (!(adj_mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)) &&
  363. (!(adj_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_VID)) &&
  364. (!(adj_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_CMD)) &&
  365. (!crtc_state->active_changed ||
  366. display->is_cont_splash_enabled)) {
  367. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  368. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2,
  369. adj_mode->timing.h_active,
  370. adj_mode->timing.v_active,
  371. adj_mode->timing.refresh_rate,
  372. adj_mode->pixel_clk_khz,
  373. adj_mode->panel_mode_caps);
  374. }
  375. return rc;
  376. }
  377. static bool dsi_bridge_mode_fixup(struct drm_bridge *bridge,
  378. const struct drm_display_mode *mode,
  379. struct drm_display_mode *adjusted_mode)
  380. {
  381. int rc = 0;
  382. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  383. struct dsi_display *display;
  384. struct dsi_display_mode dsi_mode, *panel_dsi_mode;
  385. struct drm_crtc_state *crtc_state;
  386. struct drm_connector_state *drm_conn_state;
  387. struct sde_connector_state *conn_state;
  388. struct msm_sub_mode new_sub_mode;
  389. crtc_state = container_of(mode, struct drm_crtc_state, mode);
  390. if (!bridge || !mode || !adjusted_mode) {
  391. DSI_ERR("invalid params\n");
  392. return false;
  393. }
  394. display = c_bridge->display;
  395. if (!display || !display->drm_conn || !display->drm_conn->state) {
  396. DSI_ERR("invalid params\n");
  397. return false;
  398. }
  399. drm_conn_state = drm_atomic_get_new_connector_state(crtc_state->state,
  400. display->drm_conn);
  401. conn_state = to_sde_connector_state(drm_conn_state);
  402. if (!conn_state) {
  403. DSI_ERR("invalid params\n");
  404. return false;
  405. }
  406. /*
  407. * if no timing defined in panel, it must be external mode
  408. * and we'll use empty priv info to populate the mode
  409. */
  410. if (display->panel && !display->panel->num_timing_nodes) {
  411. *adjusted_mode = *mode;
  412. conn_state->msm_mode.base = adjusted_mode;
  413. conn_state->msm_mode.private = (int *)&default_priv_info;
  414. conn_state->msm_mode.private_flags = 0;
  415. return true;
  416. }
  417. convert_to_dsi_mode(mode, &dsi_mode);
  418. msm_parse_mode_priv_info(&conn_state->msm_mode, &dsi_mode);
  419. new_sub_mode.dsc_mode = sde_connector_get_property(drm_conn_state,
  420. CONNECTOR_PROP_DSC_MODE);
  421. /*
  422. * retrieve dsi mode from dsi driver's cache since not safe to take
  423. * the drm mode config mutex in all paths
  424. */
  425. rc = dsi_display_find_mode(display, &dsi_mode, &new_sub_mode,
  426. &panel_dsi_mode);
  427. if (rc)
  428. return rc;
  429. /* propagate the private info to the adjusted_mode derived dsi mode */
  430. dsi_mode.priv_info = panel_dsi_mode->priv_info;
  431. dsi_mode.dsi_mode_flags = panel_dsi_mode->dsi_mode_flags;
  432. dsi_mode.panel_mode_caps = panel_dsi_mode->panel_mode_caps;
  433. dsi_mode.timing.dsc_enabled = dsi_mode.priv_info->dsc_enabled;
  434. dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;
  435. rc = dsi_display_restore_bit_clk(display, &dsi_mode);
  436. if (rc) {
  437. DSI_ERR("[%s] bit clk rate cannot be restored\n", display->name);
  438. return false;
  439. }
  440. rc = dsi_display_update_dyn_bit_clk(display, &dsi_mode);
  441. if (rc) {
  442. DSI_ERR("[%s] failed to update bit clock\n", display->name);
  443. return false;
  444. }
  445. rc = dsi_display_validate_mode(c_bridge->display, &dsi_mode,
  446. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  447. if (rc) {
  448. DSI_ERR("[%d] mode is not valid, rc=%d\n", c_bridge->id, rc);
  449. return false;
  450. }
  451. rc = _dsi_bridge_mode_validate_and_fixup(bridge, crtc_state, display, &dsi_mode);
  452. if (rc) {
  453. DSI_ERR("[%s] failed to validate dsi bridge mode.\n", display->name);
  454. return false;
  455. }
  456. /* Reject seamless transition when active changed */
  457. if (crtc_state->active_changed &&
  458. ((dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) ||
  459. (dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK) ||
  460. (dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_VID) ||
  461. (dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_CMD))) {
  462. DSI_INFO("seamless upon active changed 0x%x %d\n",
  463. dsi_mode.dsi_mode_flags, crtc_state->active_changed);
  464. return false;
  465. }
  466. /* convert back to drm mode, propagating the private info & flags */
  467. dsi_convert_to_drm_mode(&dsi_mode, adjusted_mode);
  468. dsi_convert_to_msm_mode(&dsi_mode, &conn_state->msm_mode);
  469. return true;
  470. }
  471. u32 dsi_drm_get_dfps_maxfps(void *display)
  472. {
  473. u32 dfps_maxfps = 0;
  474. struct dsi_display *dsi_display = display;
  475. /*
  476. * The time of SDE transmitting one frame active data
  477. * will not be changed, if frame rate is adjusted with
  478. * VFP method.
  479. * So only return max fps of DFPS for UIDLE update, if DFPS
  480. * is enabled with VFP.
  481. */
  482. if (dsi_display && dsi_display->panel &&
  483. dsi_display->panel->panel_mode == DSI_OP_VIDEO_MODE &&
  484. dsi_display->panel->dfps_caps.type ==
  485. DSI_DFPS_IMMEDIATE_VFP)
  486. dfps_maxfps =
  487. dsi_display->panel->dfps_caps.max_refresh_rate;
  488. return dfps_maxfps;
  489. }
  490. int dsi_conn_get_lm_from_mode(void *display, const struct drm_display_mode *drm_mode)
  491. {
  492. struct dsi_display *dsi_display = display;
  493. struct dsi_display_mode dsi_mode, *panel_dsi_mode;
  494. int rc = -EINVAL;
  495. if (!dsi_display || !drm_mode) {
  496. DSI_ERR("Invalid params %d %d\n", !display, !drm_mode);
  497. return rc;
  498. }
  499. convert_to_dsi_mode(drm_mode, &dsi_mode);
  500. rc = dsi_display_find_mode(dsi_display, &dsi_mode, NULL, &panel_dsi_mode);
  501. if (rc) {
  502. DSI_ERR("mode not found %d\n", rc);
  503. drm_mode_debug_printmodeline(drm_mode);
  504. return rc;
  505. }
  506. return panel_dsi_mode->priv_info->topology.num_lm;
  507. }
  508. int dsi_conn_get_mode_info(struct drm_connector *connector,
  509. const struct drm_display_mode *drm_mode,
  510. struct msm_sub_mode *sub_mode,
  511. struct msm_mode_info *mode_info,
  512. void *display, const struct msm_resource_caps_info *avail_res)
  513. {
  514. struct dsi_display_mode partial_dsi_mode, *dsi_mode = NULL;
  515. struct dsi_mode_info *timing;
  516. int src_bpp, tar_bpp, rc = 0;
  517. struct dsi_display *dsi_display = (struct dsi_display *) display;
  518. if (!drm_mode || !mode_info)
  519. return -EINVAL;
  520. convert_to_dsi_mode(drm_mode, &partial_dsi_mode);
  521. rc = dsi_display_find_mode(dsi_display, &partial_dsi_mode, sub_mode, &dsi_mode);
  522. if (rc || !dsi_mode->priv_info)
  523. return -EINVAL;
  524. memset(mode_info, 0, sizeof(*mode_info));
  525. timing = &dsi_mode->timing;
  526. mode_info->frame_rate = dsi_mode->timing.refresh_rate;
  527. mode_info->vtotal = DSI_V_TOTAL(timing);
  528. mode_info->prefill_lines = dsi_mode->priv_info->panel_prefill_lines;
  529. mode_info->jitter_numer = dsi_mode->priv_info->panel_jitter_numer;
  530. mode_info->jitter_denom = dsi_mode->priv_info->panel_jitter_denom;
  531. mode_info->dfps_maxfps = dsi_drm_get_dfps_maxfps(display);
  532. mode_info->panel_mode_caps = dsi_mode->panel_mode_caps;
  533. mode_info->mdp_transfer_time_us =
  534. dsi_mode->priv_info->mdp_transfer_time_us;
  535. mode_info->disable_rsc_solver = dsi_mode->priv_info->disable_rsc_solver;
  536. mode_info->qsync_min_fps = dsi_mode->timing.qsync_min_fps;
  537. memcpy(&mode_info->topology, &dsi_mode->priv_info->topology,
  538. sizeof(struct msm_display_topology));
  539. if (dsi_mode->priv_info->bit_clk_list.count) {
  540. struct msm_dyn_clk_list *dyn_clk_list = &mode_info->dyn_clk_list;
  541. dyn_clk_list->rates = dsi_mode->priv_info->bit_clk_list.rates;
  542. dyn_clk_list->count = dsi_mode->priv_info->bit_clk_list.count;
  543. dyn_clk_list->type = dsi_display->panel->dyn_clk_caps.type;
  544. dyn_clk_list->front_porches = dsi_mode->priv_info->bit_clk_list.front_porches;
  545. dyn_clk_list->pixel_clks_khz = dsi_mode->priv_info->bit_clk_list.pixel_clks_khz;
  546. rc = dsi_display_restore_bit_clk(dsi_display, dsi_mode);
  547. if (rc) {
  548. DSI_ERR("[%s] bit clk rate cannot be restored\n", dsi_display->name);
  549. return rc;
  550. }
  551. }
  552. mode_info->clk_rate = dsi_mode->timing.clk_rate_hz;
  553. if (dsi_mode->priv_info->dsc_enabled) {
  554. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_DSC;
  555. mode_info->topology.comp_type = MSM_DISPLAY_COMPRESSION_DSC;
  556. memcpy(&mode_info->comp_info.dsc_info, &dsi_mode->priv_info->dsc,
  557. sizeof(dsi_mode->priv_info->dsc));
  558. } else if (dsi_mode->priv_info->vdc_enabled) {
  559. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_VDC;
  560. mode_info->topology.comp_type = MSM_DISPLAY_COMPRESSION_VDC;
  561. memcpy(&mode_info->comp_info.vdc_info, &dsi_mode->priv_info->vdc,
  562. sizeof(dsi_mode->priv_info->vdc));
  563. }
  564. if (mode_info->comp_info.comp_type) {
  565. tar_bpp = dsi_mode->priv_info->pclk_scale.numer;
  566. src_bpp = dsi_mode->priv_info->pclk_scale.denom;
  567. mode_info->comp_info.comp_ratio = mult_frac(1, src_bpp,
  568. tar_bpp);
  569. mode_info->wide_bus_en = dsi_mode->priv_info->widebus_support;
  570. }
  571. if (dsi_mode->priv_info->roi_caps.enabled) {
  572. memcpy(&mode_info->roi_caps, &dsi_mode->priv_info->roi_caps,
  573. sizeof(dsi_mode->priv_info->roi_caps));
  574. }
  575. mode_info->allowed_mode_switches =
  576. dsi_mode->priv_info->allowed_mode_switch;
  577. return 0;
  578. }
  579. static const struct drm_bridge_funcs dsi_bridge_ops = {
  580. .attach = dsi_bridge_attach,
  581. .mode_fixup = dsi_bridge_mode_fixup,
  582. .pre_enable = dsi_bridge_pre_enable,
  583. .enable = dsi_bridge_enable,
  584. .disable = dsi_bridge_disable,
  585. .post_disable = dsi_bridge_post_disable,
  586. .mode_set = dsi_bridge_mode_set,
  587. };
  588. int dsi_conn_set_avr_step_info(struct dsi_panel *panel, void *info)
  589. {
  590. u32 i;
  591. int idx = 0;
  592. size_t buff_sz = PAGE_SIZE;
  593. char *buff;
  594. buff = kzalloc(buff_sz, GFP_KERNEL);
  595. if (!buff)
  596. return -ENOMEM;
  597. for (i = 0; i < panel->avr_caps.avr_step_fps_list_len && (idx < (buff_sz - 1)); i++)
  598. idx += scnprintf(&buff[idx], buff_sz - idx, "%u@%u ",
  599. panel->avr_caps.avr_step_fps_list[i],
  600. panel->dfps_caps.dfps_list[i]);
  601. sde_kms_info_add_keystr(info, "avr step requirement", buff);
  602. kfree(buff);
  603. return 0;
  604. }
  605. int dsi_conn_get_qsync_min_fps(struct drm_connector_state *conn_state)
  606. {
  607. struct sde_connector_state *sde_conn_state = to_sde_connector_state(conn_state);
  608. struct msm_display_mode *msm_mode;
  609. struct dsi_display_mode_priv_info *priv_info;
  610. if (!sde_conn_state)
  611. return -EINVAL;
  612. msm_mode = &sde_conn_state->msm_mode;
  613. if (!msm_mode || !msm_mode->private)
  614. return -EINVAL;
  615. priv_info = (struct dsi_display_mode_priv_info *)(msm_mode->private);
  616. return priv_info->qsync_min_fps;
  617. }
  618. int dsi_conn_set_info_blob(struct drm_connector *connector,
  619. void *info, void *display, struct msm_mode_info *mode_info)
  620. {
  621. struct dsi_display *dsi_display = display;
  622. struct dsi_panel *panel;
  623. enum dsi_pixel_format fmt;
  624. u32 bpp;
  625. if (!info || !dsi_display)
  626. return -EINVAL;
  627. dsi_display->drm_conn = connector;
  628. sde_kms_info_add_keystr(info,
  629. "display type", dsi_display->display_type);
  630. switch (dsi_display->type) {
  631. case DSI_DISPLAY_SINGLE:
  632. sde_kms_info_add_keystr(info, "display config",
  633. "single display");
  634. break;
  635. case DSI_DISPLAY_EXT_BRIDGE:
  636. sde_kms_info_add_keystr(info, "display config", "ext bridge");
  637. break;
  638. case DSI_DISPLAY_SPLIT:
  639. sde_kms_info_add_keystr(info, "display config",
  640. "split display");
  641. break;
  642. case DSI_DISPLAY_SPLIT_EXT_BRIDGE:
  643. sde_kms_info_add_keystr(info, "display config",
  644. "split ext bridge");
  645. break;
  646. default:
  647. DSI_DEBUG("invalid display type:%d\n", dsi_display->type);
  648. break;
  649. }
  650. if (!dsi_display->panel) {
  651. DSI_DEBUG("invalid panel data\n");
  652. goto end;
  653. }
  654. panel = dsi_display->panel;
  655. sde_kms_info_add_keystr(info, "panel name", panel->name);
  656. switch (panel->panel_mode) {
  657. case DSI_OP_VIDEO_MODE:
  658. sde_kms_info_add_keystr(info, "panel mode", "video");
  659. if (panel->avr_caps.avr_step_fps_list_len)
  660. dsi_conn_set_avr_step_info(panel, info);
  661. break;
  662. case DSI_OP_CMD_MODE:
  663. sde_kms_info_add_keystr(info, "panel mode", "command");
  664. sde_kms_info_add_keyint(info, "mdp_transfer_time_us",
  665. mode_info->mdp_transfer_time_us);
  666. break;
  667. default:
  668. DSI_DEBUG("invalid panel type:%d\n", panel->panel_mode);
  669. break;
  670. }
  671. sde_kms_info_add_keystr(info, "qsync support",
  672. panel->qsync_caps.qsync_support ?
  673. "true" : "false");
  674. if (panel->qsync_caps.qsync_min_fps)
  675. sde_kms_info_add_keyint(info, "qsync_fps",
  676. panel->qsync_caps.qsync_min_fps);
  677. sde_kms_info_add_keystr(info, "dfps support",
  678. panel->dfps_caps.dfps_support ? "true" : "false");
  679. if (panel->dfps_caps.dfps_support) {
  680. sde_kms_info_add_keyint(info, "min_fps",
  681. panel->dfps_caps.min_refresh_rate);
  682. sde_kms_info_add_keyint(info, "max_fps",
  683. panel->dfps_caps.max_refresh_rate);
  684. }
  685. sde_kms_info_add_keystr(info, "dyn bitclk support",
  686. panel->dyn_clk_caps.dyn_clk_support ? "true" : "false");
  687. switch (panel->phy_props.rotation) {
  688. case DSI_PANEL_ROTATE_NONE:
  689. sde_kms_info_add_keystr(info, "panel orientation", "none");
  690. break;
  691. case DSI_PANEL_ROTATE_H_FLIP:
  692. sde_kms_info_add_keystr(info, "panel orientation", "horz flip");
  693. break;
  694. case DSI_PANEL_ROTATE_V_FLIP:
  695. sde_kms_info_add_keystr(info, "panel orientation", "vert flip");
  696. break;
  697. case DSI_PANEL_ROTATE_HV_FLIP:
  698. sde_kms_info_add_keystr(info, "panel orientation",
  699. "horz & vert flip");
  700. break;
  701. default:
  702. DSI_DEBUG("invalid panel rotation:%d\n",
  703. panel->phy_props.rotation);
  704. break;
  705. }
  706. switch (panel->bl_config.type) {
  707. case DSI_BACKLIGHT_PWM:
  708. sde_kms_info_add_keystr(info, "backlight type", "pwm");
  709. break;
  710. case DSI_BACKLIGHT_WLED:
  711. sde_kms_info_add_keystr(info, "backlight type", "wled");
  712. break;
  713. case DSI_BACKLIGHT_DCS:
  714. sde_kms_info_add_keystr(info, "backlight type", "dcs");
  715. break;
  716. default:
  717. DSI_DEBUG("invalid panel backlight type:%d\n",
  718. panel->bl_config.type);
  719. break;
  720. }
  721. sde_kms_info_add_keyint(info, "max os brightness", panel->bl_config.brightness_max_level);
  722. sde_kms_info_add_keyint(info, "max panel backlight", panel->bl_config.bl_max_level);
  723. if (panel->spr_info.enable)
  724. sde_kms_info_add_keystr(info, "spr_pack_type",
  725. msm_spr_pack_type_str[panel->spr_info.pack_type]);
  726. if (mode_info && mode_info->roi_caps.enabled) {
  727. sde_kms_info_add_keyint(info, "partial_update_num_roi",
  728. mode_info->roi_caps.num_roi);
  729. sde_kms_info_add_keyint(info, "partial_update_xstart",
  730. mode_info->roi_caps.align.xstart_pix_align);
  731. sde_kms_info_add_keyint(info, "partial_update_walign",
  732. mode_info->roi_caps.align.width_pix_align);
  733. sde_kms_info_add_keyint(info, "partial_update_wmin",
  734. mode_info->roi_caps.align.min_width);
  735. sde_kms_info_add_keyint(info, "partial_update_ystart",
  736. mode_info->roi_caps.align.ystart_pix_align);
  737. sde_kms_info_add_keyint(info, "partial_update_halign",
  738. mode_info->roi_caps.align.height_pix_align);
  739. sde_kms_info_add_keyint(info, "partial_update_hmin",
  740. mode_info->roi_caps.align.min_height);
  741. sde_kms_info_add_keyint(info, "partial_update_roimerge",
  742. mode_info->roi_caps.merge_rois);
  743. }
  744. fmt = dsi_display->config.common_config.dst_format;
  745. bpp = dsi_ctrl_pixel_format_to_bpp(fmt);
  746. sde_kms_info_add_keyint(info, "bit_depth", bpp);
  747. end:
  748. return 0;
  749. }
  750. void dsi_conn_set_submode_blob_info(struct drm_connector *conn,
  751. void *info, void *display, struct drm_display_mode *drm_mode)
  752. {
  753. struct dsi_display *dsi_display = display;
  754. struct dsi_display_mode partial_dsi_mode;
  755. int count, i;
  756. int preferred_submode_idx = -EINVAL;
  757. enum dsi_dyn_clk_feature_type dyn_clk_type;
  758. char *dyn_clk_types[DSI_DYN_CLK_TYPE_MAX] = {
  759. [DSI_DYN_CLK_TYPE_LEGACY] = "none",
  760. [DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_HFP] = "hfp",
  761. [DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_VFP] = "vfp",
  762. };
  763. if (!conn || !display || !drm_mode) {
  764. DSI_ERR("Invalid params\n");
  765. return;
  766. }
  767. convert_to_dsi_mode(drm_mode, &partial_dsi_mode);
  768. mutex_lock(&dsi_display->display_lock);
  769. count = dsi_display->panel->num_display_modes;
  770. for (i = 0; i < count; i++) {
  771. struct dsi_display_mode *dsi_mode = &dsi_display->modes[i];
  772. u32 panel_mode_caps = 0;
  773. const char *topo_name = NULL;
  774. if (!dsi_display_mode_match(&partial_dsi_mode, dsi_mode,
  775. DSI_MODE_MATCH_FULL_TIMINGS))
  776. continue;
  777. sde_kms_info_add_keyint(info, "submode_idx", i);
  778. if (dsi_mode->is_preferred)
  779. preferred_submode_idx = i;
  780. if (dsi_mode->panel_mode_caps & DSI_OP_CMD_MODE)
  781. panel_mode_caps |= DRM_MODE_FLAG_CMD_MODE_PANEL;
  782. if (dsi_mode->panel_mode_caps & DSI_OP_VIDEO_MODE)
  783. panel_mode_caps |= DRM_MODE_FLAG_VID_MODE_PANEL;
  784. sde_kms_info_add_keyint(info, "panel_mode_capabilities",
  785. panel_mode_caps);
  786. sde_kms_info_add_keyint(info, "dsc_mode",
  787. dsi_mode->priv_info->dsc_enabled ? MSM_DISPLAY_DSC_MODE_ENABLED :
  788. MSM_DISPLAY_DSC_MODE_DISABLED);
  789. topo_name = sde_conn_get_topology_name(conn,
  790. dsi_mode->priv_info->topology);
  791. if (topo_name)
  792. sde_kms_info_add_keystr(info, "topology", topo_name);
  793. if (!dsi_mode->priv_info->bit_clk_list.count)
  794. continue;
  795. dyn_clk_type = dsi_display->panel->dyn_clk_caps.type;
  796. sde_kms_info_add_list(info, "dyn_bitclk_list",
  797. dsi_mode->priv_info->bit_clk_list.rates,
  798. dsi_mode->priv_info->bit_clk_list.count);
  799. sde_kms_info_add_keystr(info, "dyn_fp_type",
  800. dyn_clk_types[dyn_clk_type]);
  801. sde_kms_info_add_list(info, "dyn_fp_list",
  802. dsi_mode->priv_info->bit_clk_list.front_porches,
  803. dsi_mode->priv_info->bit_clk_list.count);
  804. sde_kms_info_add_list(info, "dyn_pclk_list",
  805. dsi_mode->priv_info->bit_clk_list.pixel_clks_khz,
  806. dsi_mode->priv_info->bit_clk_list.count);
  807. }
  808. if (preferred_submode_idx >= 0)
  809. sde_kms_info_add_keyint(info, "preferred_submode_idx",
  810. preferred_submode_idx);
  811. mutex_unlock(&dsi_display->display_lock);
  812. }
  813. enum drm_connector_status dsi_conn_detect(struct drm_connector *conn,
  814. bool force,
  815. void *display)
  816. {
  817. enum drm_connector_status status = connector_status_unknown;
  818. struct msm_display_info info;
  819. int rc;
  820. if (!conn || !display)
  821. return status;
  822. /* get display dsi_info */
  823. memset(&info, 0x0, sizeof(info));
  824. rc = dsi_display_get_info(conn, &info, display);
  825. if (rc) {
  826. DSI_ERR("failed to get display info, rc=%d\n", rc);
  827. return connector_status_disconnected;
  828. }
  829. if (info.capabilities & MSM_DISPLAY_CAP_HOT_PLUG)
  830. status = (info.is_connected ? connector_status_connected :
  831. connector_status_disconnected);
  832. else
  833. status = connector_status_connected;
  834. conn->display_info.width_mm = info.width_mm;
  835. conn->display_info.height_mm = info.height_mm;
  836. return status;
  837. }
  838. void dsi_connector_put_modes(struct drm_connector *connector,
  839. void *display)
  840. {
  841. struct dsi_display *dsi_display;
  842. int count, i;
  843. if (!connector || !display)
  844. return;
  845. dsi_display = display;
  846. count = dsi_display->panel->num_display_modes;
  847. for (i = 0; i < count; i++) {
  848. struct dsi_display_mode *dsi_mode = &dsi_display->modes[i];
  849. dsi_display_put_mode(dsi_display, dsi_mode);
  850. }
  851. /* free the display structure modes also */
  852. kfree(dsi_display->modes);
  853. dsi_display->modes = NULL;
  854. }
  855. static int dsi_drm_update_edid_name(struct edid *edid, const char *name)
  856. {
  857. u8 *dtd = (u8 *)&edid->detailed_timings[3];
  858. u8 standard_header[] = {0x00, 0x00, 0x00, 0xFE, 0x00};
  859. u32 dtd_size = 18;
  860. u32 header_size = sizeof(standard_header);
  861. if (!name)
  862. return -EINVAL;
  863. /* Fill standard header */
  864. memcpy(dtd, standard_header, header_size);
  865. dtd_size -= header_size;
  866. dtd_size = min_t(u32, dtd_size, strlen(name));
  867. memcpy(dtd + header_size, name, dtd_size);
  868. return 0;
  869. }
  870. static void dsi_drm_update_dtd(struct edid *edid,
  871. struct dsi_display_mode *modes, u32 modes_count)
  872. {
  873. u32 i;
  874. u32 count = min_t(u32, modes_count, 3);
  875. for (i = 0; i < count; i++) {
  876. struct detailed_timing *dtd = &edid->detailed_timings[i];
  877. struct dsi_display_mode *mode = &modes[i];
  878. struct dsi_mode_info *timing = &mode->timing;
  879. struct detailed_pixel_timing *pd = &dtd->data.pixel_data;
  880. u32 h_blank = timing->h_front_porch + timing->h_sync_width +
  881. timing->h_back_porch;
  882. u32 v_blank = timing->v_front_porch + timing->v_sync_width +
  883. timing->v_back_porch;
  884. u32 h_img = 0, v_img = 0;
  885. dtd->pixel_clock = mode->pixel_clk_khz / 10;
  886. pd->hactive_lo = timing->h_active & 0xFF;
  887. pd->hblank_lo = h_blank & 0xFF;
  888. pd->hactive_hblank_hi = ((h_blank >> 8) & 0xF) |
  889. ((timing->h_active >> 8) & 0xF) << 4;
  890. pd->vactive_lo = timing->v_active & 0xFF;
  891. pd->vblank_lo = v_blank & 0xFF;
  892. pd->vactive_vblank_hi = ((v_blank >> 8) & 0xF) |
  893. ((timing->v_active >> 8) & 0xF) << 4;
  894. pd->hsync_offset_lo = timing->h_front_porch & 0xFF;
  895. pd->hsync_pulse_width_lo = timing->h_sync_width & 0xFF;
  896. pd->vsync_offset_pulse_width_lo =
  897. ((timing->v_front_porch & 0xF) << 4) |
  898. (timing->v_sync_width & 0xF);
  899. pd->hsync_vsync_offset_pulse_width_hi =
  900. (((timing->h_front_porch >> 8) & 0x3) << 6) |
  901. (((timing->h_sync_width >> 8) & 0x3) << 4) |
  902. (((timing->v_front_porch >> 4) & 0x3) << 2) |
  903. (((timing->v_sync_width >> 4) & 0x3) << 0);
  904. pd->width_mm_lo = h_img & 0xFF;
  905. pd->height_mm_lo = v_img & 0xFF;
  906. pd->width_height_mm_hi = (((h_img >> 8) & 0xF) << 4) |
  907. ((v_img >> 8) & 0xF);
  908. pd->hborder = 0;
  909. pd->vborder = 0;
  910. pd->misc = 0;
  911. }
  912. }
  913. static void dsi_drm_update_checksum(struct edid *edid)
  914. {
  915. u8 *data = (u8 *)edid;
  916. u32 i, sum = 0;
  917. for (i = 0; i < EDID_LENGTH - 1; i++)
  918. sum += data[i];
  919. edid->checksum = 0x100 - (sum & 0xFF);
  920. }
  921. int dsi_connector_get_modes(struct drm_connector *connector, void *data,
  922. const struct msm_resource_caps_info *avail_res)
  923. {
  924. int rc, i;
  925. u32 count = 0, edid_size;
  926. struct dsi_display_mode *modes = NULL;
  927. struct drm_display_mode drm_mode;
  928. struct dsi_display *display = data;
  929. struct edid edid;
  930. unsigned int width_mm = connector->display_info.width_mm;
  931. unsigned int height_mm = connector->display_info.height_mm;
  932. const u8 edid_buf[EDID_LENGTH] = {
  933. 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x44, 0x6D,
  934. 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1B, 0x10, 0x01, 0x03,
  935. 0x80, 0x00, 0x00, 0x78, 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47,
  936. 0x98, 0x27, 0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
  937. 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
  938. 0x01, 0x01, 0x01, 0x01,
  939. };
  940. edid_size = min_t(u32, sizeof(edid), EDID_LENGTH);
  941. memcpy(&edid, edid_buf, edid_size);
  942. rc = dsi_display_get_mode_count(display, &count);
  943. if (rc) {
  944. DSI_ERR("failed to get num of modes, rc=%d\n", rc);
  945. goto end;
  946. }
  947. rc = dsi_display_get_modes(display, &modes);
  948. if (rc) {
  949. DSI_ERR("failed to get modes, rc=%d\n", rc);
  950. count = 0;
  951. goto end;
  952. }
  953. for (i = 0; i < count; i++) {
  954. struct drm_display_mode *m;
  955. memset(&drm_mode, 0x0, sizeof(drm_mode));
  956. dsi_convert_to_drm_mode(&modes[i], &drm_mode);
  957. m = drm_mode_duplicate(connector->dev, &drm_mode);
  958. if (!m) {
  959. DSI_ERR("failed to add mode %ux%u\n",
  960. drm_mode.hdisplay,
  961. drm_mode.vdisplay);
  962. count = -ENOMEM;
  963. goto end;
  964. }
  965. m->width_mm = connector->display_info.width_mm;
  966. m->height_mm = connector->display_info.height_mm;
  967. if (display->cmdline_timing != NO_OVERRIDE) {
  968. /* get the preferred mode from dsi display mode */
  969. if (modes[i].is_preferred)
  970. m->type |= DRM_MODE_TYPE_PREFERRED;
  971. } else if (modes[i].mode_idx == 0) {
  972. /* set the first mode in device tree list as preferred */
  973. m->type |= DRM_MODE_TYPE_PREFERRED;
  974. }
  975. drm_mode_probed_add(connector, m);
  976. }
  977. rc = dsi_drm_update_edid_name(&edid, display->panel->name);
  978. if (rc) {
  979. count = 0;
  980. goto end;
  981. }
  982. edid.width_cm = (connector->display_info.width_mm) / 10;
  983. edid.height_cm = (connector->display_info.height_mm) / 10;
  984. dsi_drm_update_dtd(&edid, modes, count);
  985. dsi_drm_update_checksum(&edid);
  986. rc = drm_connector_update_edid_property(connector, &edid);
  987. if (rc)
  988. count = 0;
  989. /*
  990. * DRM EDID structure maintains panel physical dimensions in
  991. * centimeters, we will be losing the precision anything below cm.
  992. * Changing DRM framework will effect other clients at this
  993. * moment, overriding the values back to millimeter.
  994. */
  995. connector->display_info.width_mm = width_mm;
  996. connector->display_info.height_mm = height_mm;
  997. end:
  998. DSI_DEBUG("MODE COUNT =%d\n\n", count);
  999. return count;
  1000. }
  1001. enum drm_mode_status dsi_conn_mode_valid(struct drm_connector *connector,
  1002. struct drm_display_mode *mode,
  1003. void *display, const struct msm_resource_caps_info *avail_res)
  1004. {
  1005. struct dsi_display_mode dsi_mode;
  1006. struct dsi_display_mode *full_dsi_mode = NULL;
  1007. struct sde_connector_state *conn_state;
  1008. int rc;
  1009. if (!connector || !mode) {
  1010. DSI_ERR("Invalid params\n");
  1011. return MODE_ERROR;
  1012. }
  1013. convert_to_dsi_mode(mode, &dsi_mode);
  1014. conn_state = to_sde_connector_state(connector->state);
  1015. if (conn_state)
  1016. msm_parse_mode_priv_info(&conn_state->msm_mode, &dsi_mode);
  1017. rc = dsi_display_find_mode(display, &dsi_mode, NULL, &full_dsi_mode);
  1018. if (rc) {
  1019. DSI_ERR("could not find mode %s\n", mode->name);
  1020. return MODE_ERROR;
  1021. }
  1022. rc = dsi_display_validate_mode(display, full_dsi_mode,
  1023. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  1024. if (rc) {
  1025. DSI_ERR("mode not supported, rc=%d\n", rc);
  1026. return MODE_BAD;
  1027. }
  1028. return MODE_OK;
  1029. }
  1030. int dsi_conn_pre_kickoff(struct drm_connector *connector,
  1031. void *display,
  1032. struct msm_display_kickoff_params *params)
  1033. {
  1034. if (!connector || !display || !params) {
  1035. DSI_ERR("Invalid params\n");
  1036. return -EINVAL;
  1037. }
  1038. return dsi_display_pre_kickoff(connector, display, params);
  1039. }
  1040. int dsi_conn_prepare_commit(void *display,
  1041. struct msm_display_conn_params *params)
  1042. {
  1043. if (!display || !params) {
  1044. pr_err("Invalid params\n");
  1045. return -EINVAL;
  1046. }
  1047. return dsi_display_pre_commit(display, params);
  1048. }
  1049. void dsi_conn_enable_event(struct drm_connector *connector,
  1050. uint32_t event_idx, bool enable, void *display)
  1051. {
  1052. struct dsi_event_cb_info event_info;
  1053. memset(&event_info, 0, sizeof(event_info));
  1054. event_info.event_cb = sde_connector_trigger_event;
  1055. event_info.event_usr_ptr = connector;
  1056. dsi_display_enable_event(connector, display,
  1057. event_idx, &event_info, enable);
  1058. }
  1059. int dsi_conn_post_kickoff(struct drm_connector *connector,
  1060. struct msm_display_conn_params *params)
  1061. {
  1062. struct drm_encoder *encoder;
  1063. struct drm_bridge *bridge;
  1064. struct dsi_bridge *c_bridge;
  1065. struct dsi_display_mode adj_mode;
  1066. struct dsi_display *display;
  1067. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1068. int i, rc = 0, ctrl_version;
  1069. bool enable;
  1070. struct dsi_dyn_clk_caps *dyn_clk_caps;
  1071. if (!connector || !connector->state) {
  1072. DSI_ERR("invalid connector or connector state\n");
  1073. return -EINVAL;
  1074. }
  1075. encoder = connector->state->best_encoder;
  1076. if (!encoder) {
  1077. DSI_DEBUG("best encoder is not available\n");
  1078. return 0;
  1079. }
  1080. bridge = drm_bridge_chain_get_first_bridge(encoder);
  1081. if (!bridge) {
  1082. DSI_DEBUG("bridge is not available\n");
  1083. return 0;
  1084. }
  1085. c_bridge = to_dsi_bridge(bridge);
  1086. adj_mode = c_bridge->dsi_mode;
  1087. display = c_bridge->display;
  1088. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  1089. if (adj_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) {
  1090. m_ctrl = &display->ctrl[display->clk_master_idx];
  1091. ctrl_version = m_ctrl->ctrl->version;
  1092. rc = dsi_ctrl_timing_db_update(m_ctrl->ctrl, false);
  1093. if (rc) {
  1094. DSI_ERR("[%s] failed to dfps update rc=%d\n",
  1095. display->name, rc);
  1096. return -EINVAL;
  1097. }
  1098. /*
  1099. * When both DFPS and dynamic clock switch with constant
  1100. * fps features are enabled, wait for dynamic refresh done
  1101. * only in case of clock switch.
  1102. * In case where only fps changes, clock remains same.
  1103. * So, wait for dynamic refresh done is not required.
  1104. */
  1105. if ((ctrl_version >= DSI_CTRL_VERSION_2_5) &&
  1106. (dyn_clk_caps->maintain_const_fps) &&
  1107. (adj_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)) {
  1108. display_for_each_ctrl(i, display) {
  1109. ctrl = &display->ctrl[i];
  1110. rc = dsi_ctrl_wait4dynamic_refresh_done(
  1111. ctrl->ctrl);
  1112. if (rc)
  1113. DSI_ERR("wait4dfps refresh failed\n");
  1114. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  1115. dsi_clk_disable_unprepare(&display->clock_info.pll_clks);
  1116. }
  1117. }
  1118. /* Update the rest of the controllers */
  1119. display_for_each_ctrl(i, display) {
  1120. ctrl = &display->ctrl[i];
  1121. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1122. continue;
  1123. rc = dsi_ctrl_timing_db_update(ctrl->ctrl, false);
  1124. if (rc) {
  1125. DSI_ERR("[%s] failed to dfps update rc=%d\n",
  1126. display->name, rc);
  1127. return -EINVAL;
  1128. }
  1129. }
  1130. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_VRR;
  1131. }
  1132. /* ensure dynamic clk switch flag is reset */
  1133. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_DYN_CLK;
  1134. if (params->qsync_update) {
  1135. enable = (params->qsync_mode > 0) ? true : false;
  1136. display_for_each_ctrl(i, display)
  1137. dsi_ctrl_setup_avr(display->ctrl[i].ctrl, enable);
  1138. }
  1139. return 0;
  1140. }
  1141. struct dsi_bridge *dsi_drm_bridge_init(struct dsi_display *display,
  1142. struct drm_device *dev,
  1143. struct drm_encoder *encoder)
  1144. {
  1145. int rc = 0;
  1146. struct dsi_bridge *bridge;
  1147. bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
  1148. if (!bridge) {
  1149. rc = -ENOMEM;
  1150. goto error;
  1151. }
  1152. bridge->display = display;
  1153. bridge->base.funcs = &dsi_bridge_ops;
  1154. bridge->base.encoder = encoder;
  1155. rc = drm_bridge_attach(encoder, &bridge->base, NULL, 0);
  1156. if (rc) {
  1157. DSI_ERR("failed to attach bridge, rc=%d\n", rc);
  1158. goto error_free_bridge;
  1159. }
  1160. return bridge;
  1161. error_free_bridge:
  1162. kfree(bridge);
  1163. error:
  1164. return ERR_PTR(rc);
  1165. }
  1166. void dsi_drm_bridge_cleanup(struct dsi_bridge *bridge)
  1167. {
  1168. kfree(bridge);
  1169. }
  1170. static bool is_valid_poms_switch(struct dsi_display_mode *mode_a,
  1171. struct dsi_display_mode *mode_b)
  1172. {
  1173. /*
  1174. * POMS cannot happen in conjunction with any other type of mode set.
  1175. * Check to ensure FPS remains same between the modes and also
  1176. * resolution.
  1177. */
  1178. return((mode_a->timing.refresh_rate == mode_b->timing.refresh_rate) &&
  1179. (mode_a->timing.v_active == mode_b->timing.v_active) &&
  1180. (mode_a->timing.h_active == mode_b->timing.h_active));
  1181. }
  1182. void dsi_conn_set_allowed_mode_switch(struct drm_connector *connector,
  1183. void *display)
  1184. {
  1185. u32 mode_idx = 0, cmp_mode_idx = 0;
  1186. u32 common_mode_caps = 0;
  1187. struct drm_display_mode *drm_mode, *cmp_drm_mode;
  1188. struct dsi_display_mode dsi_mode, *panel_dsi_mode, *cmp_panel_dsi_mode;
  1189. struct list_head *mode_list = &connector->modes;
  1190. struct dsi_display *disp = display;
  1191. struct dsi_panel *panel;
  1192. int mode_count = 0, rc = 0;
  1193. struct dsi_display_mode_priv_info *dsi_mode_info, *cmp_dsi_mode_info;
  1194. bool allow_switch = false;
  1195. if (!disp || !disp->panel) {
  1196. DSI_ERR("invalid parameters");
  1197. return;
  1198. }
  1199. panel = disp->panel;
  1200. list_for_each_entry(drm_mode, &connector->modes, head)
  1201. mode_count++;
  1202. list_for_each_entry(drm_mode, &connector->modes, head) {
  1203. convert_to_dsi_mode(drm_mode, &dsi_mode);
  1204. rc = dsi_display_find_mode(display, &dsi_mode, NULL, &panel_dsi_mode);
  1205. if (rc)
  1206. return;
  1207. dsi_mode_info = panel_dsi_mode->priv_info;
  1208. dsi_mode_info->allowed_mode_switch |= BIT(mode_idx);
  1209. if (mode_idx == mode_count - 1)
  1210. break;
  1211. mode_list = mode_list->next;
  1212. cmp_mode_idx = 1;
  1213. list_for_each_entry(cmp_drm_mode, mode_list, head) {
  1214. if (&cmp_drm_mode->head == &connector->modes)
  1215. continue;
  1216. convert_to_dsi_mode(cmp_drm_mode, &dsi_mode);
  1217. rc = dsi_display_find_mode(display, &dsi_mode,
  1218. NULL, &cmp_panel_dsi_mode);
  1219. if (rc)
  1220. return;
  1221. cmp_dsi_mode_info = cmp_panel_dsi_mode->priv_info;
  1222. allow_switch = false;
  1223. common_mode_caps = (panel_dsi_mode->panel_mode_caps &
  1224. cmp_panel_dsi_mode->panel_mode_caps);
  1225. /*
  1226. * FPS switch among video modes, is only supported
  1227. * if DFPS or dynamic clocks are specified.
  1228. * Reject any mode switches between video mode timing
  1229. * nodes if support for those features is not present.
  1230. */
  1231. if (common_mode_caps & DSI_OP_CMD_MODE) {
  1232. allow_switch = true;
  1233. } else if ((common_mode_caps & DSI_OP_VIDEO_MODE) &&
  1234. (panel->dfps_caps.dfps_support ||
  1235. panel->dyn_clk_caps.dyn_clk_support)) {
  1236. allow_switch = true;
  1237. } else {
  1238. if (is_valid_poms_switch(panel_dsi_mode,
  1239. cmp_panel_dsi_mode))
  1240. allow_switch = true;
  1241. }
  1242. if (allow_switch) {
  1243. dsi_mode_info->allowed_mode_switch |=
  1244. BIT(mode_idx + cmp_mode_idx);
  1245. cmp_dsi_mode_info->allowed_mode_switch |=
  1246. BIT(mode_idx);
  1247. }
  1248. if ((mode_idx + cmp_mode_idx) >= mode_count - 1)
  1249. break;
  1250. cmp_mode_idx++;
  1251. }
  1252. mode_idx++;
  1253. }
  1254. }
  1255. int dsi_conn_set_dyn_bit_clk(struct drm_connector *connector, uint64_t value)
  1256. {
  1257. struct sde_connector *c_conn = NULL;
  1258. struct dsi_display *display;
  1259. if (!connector) {
  1260. DSI_ERR("invalid connector\n");
  1261. return -EINVAL;
  1262. }
  1263. c_conn = to_sde_connector(connector);
  1264. display = (struct dsi_display *) c_conn->display;
  1265. display->dyn_bit_clk = value;
  1266. display->dyn_bit_clk_pending = true;
  1267. SDE_EVT32(display->dyn_bit_clk);
  1268. DSI_DEBUG("update dynamic bit clock rate to %llu\n", display->dyn_bit_clk);
  1269. return 0;
  1270. }