dp_pll.h 3.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef __DP_PLL_H
  6. #define __DP_PLL_H
  7. #include <linux/io.h>
  8. #include <linux/clk-provider.h>
  9. #include <linux/of_device.h>
  10. #include "dp_parser.h"
  11. #include "sde_dbg.h"
  12. #define DP_VCO_HSCLK_RATE_1620MHZDIV1000 1620000UL
  13. #define DP_VCO_HSCLK_RATE_2700MHZDIV1000 2700000UL
  14. #define DP_VCO_HSCLK_RATE_5400MHZDIV1000 5400000UL
  15. #define DP_VCO_HSCLK_RATE_8100MHZDIV1000 8100000UL
  16. #define dp_pll_get_base(x) pll->io.x->io.base
  17. #define dp_pll_read(x, offset) ({ \
  18. readl_relaxed((dp_pll_get_base(x)) + (offset)); \
  19. })
  20. #define dp_pll_write(x, offset, data) ({ \
  21. DP_DEBUG(#offset", addr=0x%llx, val=0x%x\n", \
  22. ((u64)(dp_pll_get_base(x)) + (offset)), (data)); \
  23. SDE_EVT32_VERBOSE((dp_pll_get_base(x)) + (offset), (data)); \
  24. writel_relaxed((data), (dp_pll_get_base(x)) + (offset)); \
  25. })
  26. enum dp_pll_revision {
  27. DP_PLL_UNKNOWN,
  28. DP_PLL_5NM_V1,
  29. DP_PLL_5NM_V2,
  30. DP_PLL_4NM_V1,
  31. };
  32. static inline const char *dp_pll_get_revision(enum dp_pll_revision rev)
  33. {
  34. switch (rev) {
  35. case DP_PLL_UNKNOWN: return "DP_PLL_UNKNOWN";
  36. case DP_PLL_5NM_V1: return "DP_PLL_5NM_V1";
  37. case DP_PLL_5NM_V2: return "DP_PLL_5NM_V2";
  38. case DP_PLL_4NM_V1: return "DP_PLL_4NM_V1";
  39. default: return "???";
  40. }
  41. }
  42. struct dp_pll_io {
  43. struct dp_io_data *dp_phy;
  44. struct dp_io_data *dp_pll;
  45. struct dp_io_data *dp_ln_tx0;
  46. struct dp_io_data *dp_ln_tx1;
  47. struct dp_io_data *gdsc;
  48. };
  49. struct dp_pll_vco_clk {
  50. struct clk_hw hw;
  51. void *priv;
  52. };
  53. struct dp_pll {
  54. /* target pll revision information */
  55. u32 revision;
  56. /* save vco current rate */
  57. unsigned long vco_rate;
  58. /*
  59. * PLL index if multiple index are available. Eg. in case of
  60. * DSI we have 2 plls.
  61. */
  62. uint32_t index;
  63. bool ssc_en;
  64. bool bonding_en;
  65. void *priv;
  66. struct platform_device *pdev;
  67. struct dp_parser *parser;
  68. struct dp_power *power;
  69. struct dp_aux *aux;
  70. struct dp_pll_io io;
  71. struct clk_onecell_data *clk_data;
  72. u32 dp_core_revision;
  73. int (*pll_cfg)(struct dp_pll *pll, unsigned long rate);
  74. int (*pll_prepare)(struct dp_pll *pll);
  75. int (*pll_unprepare)(struct dp_pll *pll);
  76. };
  77. struct dp_pll_db {
  78. struct dp_pll *pll;
  79. /* lane and orientation settings */
  80. u8 lane_cnt;
  81. u8 orientation;
  82. /* COM PHY settings */
  83. u32 hsclk_sel;
  84. u32 dec_start_mode0;
  85. u32 div_frac_start1_mode0;
  86. u32 div_frac_start2_mode0;
  87. u32 div_frac_start3_mode0;
  88. u32 integloop_gain0_mode0;
  89. u32 integloop_gain1_mode0;
  90. u32 lock_cmp1_mode0;
  91. u32 lock_cmp2_mode0;
  92. u32 lock_cmp_en;
  93. u32 ssc_step_size1_mode0;
  94. u32 ssc_step_size2_mode0;
  95. u32 ssc_per1;
  96. u32 cmp_code1_mode0;
  97. u32 cmp_code2_mode0;
  98. /* PHY vco divider */
  99. u32 phy_vco_div;
  100. };
  101. static inline struct dp_pll_vco_clk *to_dp_vco_hw(struct clk_hw *hw)
  102. {
  103. return container_of(hw, struct dp_pll_vco_clk, hw);
  104. }
  105. static inline bool is_gdsc_disabled(struct dp_pll *pll)
  106. {
  107. return (dp_pll_read(gdsc, 0x0) & BIT(31)) ? false : true;
  108. }
  109. int dp_pll_clock_register_5nm(struct dp_pll *pll);
  110. void dp_pll_clock_unregister_5nm(struct dp_pll *pll);
  111. int dp_pll_clock_register_4nm(struct dp_pll *pll);
  112. void dp_pll_clock_unregister_4nm(struct dp_pll *pll);
  113. struct dp_pll_in {
  114. struct platform_device *pdev;
  115. struct dp_aux *aux;
  116. struct dp_parser *parser;
  117. u32 dp_core_revision;
  118. };
  119. int dp_pll_clock_register_helper(struct dp_pll *pll, struct dp_pll_vco_clk *clks, int num_clks);
  120. struct dp_pll *dp_pll_get(struct dp_pll_in *in);
  121. void dp_pll_put(struct dp_pll *pll);
  122. #endif /* __DP_PLL_H */