ubwcp_main.c 87 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "%s: %s(): " fmt, KBUILD_MODNAME, __func__
  6. #include <linux/module.h>
  7. #include <linux/kernel.h>
  8. #include <linux/dma-buf.h>
  9. #include <linux/slab.h>
  10. #include <linux/cdev.h>
  11. #include <linux/hashtable.h>
  12. #include <linux/scatterlist.h>
  13. #include <linux/types.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/of.h>
  16. #include <linux/of_platform.h>
  17. #include <linux/of_address.h>
  18. #include <linux/genalloc.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/regulator/consumer.h>
  21. #include <linux/numa.h>
  22. #include <linux/memory_hotplug.h>
  23. #include <asm/page.h>
  24. #include <linux/delay.h>
  25. #include <linux/ubwcp_dma_heap.h>
  26. #include <linux/debugfs.h>
  27. #include <linux/clk.h>
  28. #include <linux/iommu.h>
  29. #include <linux/set_memory.h>
  30. #include <linux/range.h>
  31. MODULE_IMPORT_NS(DMA_BUF);
  32. #include "include/kernel/ubwcp.h"
  33. #include "ubwcp_hw.h"
  34. #include "include/uapi/ubwcp_ioctl.h"
  35. #define CREATE_TRACE_POINTS
  36. #include "ubwcp_trace.h"
  37. #define UBWCP_NUM_DEVICES 1
  38. #define UBWCP_DEVICE_NAME "ubwcp"
  39. #define UBWCP_BUFFER_DESC_OFFSET 64
  40. #define UBWCP_BUFFER_DESC_COUNT 256
  41. #define CACHE_ADDR(x) ((x) >> 6)
  42. #define PAGE_ADDR(x) ((x) >> 12)
  43. #define UBWCP_ALIGN(_x, _y) ((((_x) + (_y) - 1)/(_y))*(_y))
  44. #define DBG_BUF_ATTR(fmt, args...) do { if (unlikely(ubwcp_debug_trace_enable)) \
  45. pr_err(fmt "\n", ##args); \
  46. } while (0)
  47. #define DBG(fmt, args...) do { if (unlikely(ubwcp_debug_trace_enable)) \
  48. pr_err(fmt "\n", ##args); \
  49. } while (0)
  50. #define ERR(fmt, args...) pr_err_ratelimited("%d: ~~~ERROR~~~: " fmt "\n", __LINE__, ##args)
  51. #define META_DATA_PITCH_ALIGN 64
  52. #define META_DATA_HEIGHT_ALIGN 16
  53. #define META_DATA_SIZE_ALIGN 4096
  54. #define PIXEL_DATA_SIZE_ALIGN 4096
  55. #define UBWCP_SYNC_GRANULE 0x4000000L /* 64 MB */
  56. /* Max values for attributes */
  57. #define MAX_ATTR_WIDTH (10*1024)
  58. #define MAX_ATTR_HEIGHT (10*1024)
  59. #define MAX_ATTR_STRIDE (64*1024)
  60. #define MAX_ATTR_PLANAR_PAD 4096
  61. #define MAX_ATTR_SCANLN_HT_DELTA (32*1024)
  62. enum ula_remove_mem_status {
  63. ULA_REMOVE_MEM_SUCCESS = 0,
  64. ULA_REMOVE_MEM_ABORTED = 1
  65. };
  66. struct ubwcp_desc {
  67. int idx;
  68. void *ptr;
  69. };
  70. struct tile_dimension {
  71. u16 width;
  72. u16 height;
  73. };
  74. struct ubwcp_plane_info {
  75. u16 pixel_bytes;
  76. u16 per_pixel;
  77. struct tile_dimension tilesize_p; /* pixels */
  78. struct tile_dimension macrotilesize_p; /* pixels */
  79. };
  80. struct ubwcp_image_format_info {
  81. u16 planes;
  82. struct ubwcp_plane_info p_info[2];
  83. };
  84. enum ubwcp_std_image_format {
  85. RGBA = 0,
  86. NV12 = 1,
  87. NV124R = 2,
  88. P010 = 3,
  89. TP10 = 4,
  90. P016 = 5,
  91. INFO_FORMAT_LIST_SIZE,
  92. };
  93. enum ubwcp_state {
  94. UBWCP_STATE_READY = 0,
  95. UBWCP_STATE_INVALID = -1,
  96. UBWCP_STATE_FAULT = -2,
  97. };
  98. struct ubwcp_driver {
  99. /* cdev related */
  100. dev_t devt;
  101. struct class *dev_class; //sysfs dev class
  102. struct device *dev_sys; //sysfs dev
  103. struct cdev cdev; //char dev
  104. /* debugfs */
  105. struct dentry *debugfs_root;
  106. bool read_err_irq_en;
  107. bool write_err_irq_en;
  108. bool decode_err_irq_en;
  109. bool encode_err_irq_en;
  110. /* ubwcp devices */
  111. struct device *dev; //ubwcp device
  112. struct device *dev_desc_cb; //smmu dev for descriptors
  113. struct device *dev_buf_cb; //smmu dev for ubwcp buffers
  114. void __iomem *base; //ubwcp base address
  115. struct regulator *vdd;
  116. struct clk **clocks;
  117. int num_clocks;
  118. /* interrupts */
  119. int irq_range_ck_rd;
  120. int irq_range_ck_wr;
  121. int irq_encode;
  122. int irq_decode;
  123. /* ula address pool */
  124. u64 ula_pool_base;
  125. u64 ula_pool_size;
  126. struct gen_pool *ula_pool;
  127. configure_mmap mmap_config_fptr;
  128. /* HW version */
  129. u32 hw_ver_major;
  130. u32 hw_ver_minor;
  131. /* keep track of all potential buffers.
  132. * hash table index'ed using dma_buf ptr.
  133. * 2**13 = 8192 hash values
  134. */
  135. DECLARE_HASHTABLE(buf_table, 13);
  136. /* buffer descriptor */
  137. void *buffer_desc_base; /* CPU address */
  138. dma_addr_t buffer_desc_dma_handle; /* dma address */
  139. size_t buffer_desc_size;
  140. struct ubwcp_desc desc_list[UBWCP_BUFFER_DESC_COUNT];
  141. struct ubwcp_image_format_info format_info[INFO_FORMAT_LIST_SIZE];
  142. /* driver state */
  143. enum ubwcp_state state;
  144. atomic_t num_non_lin_buffers;
  145. bool mem_online;
  146. struct mutex desc_lock; /* allocate/free descriptors */
  147. spinlock_t buf_table_lock; /* add/remove dma_buf into list of managed bufffers */
  148. struct mutex mem_hotplug_lock; /* memory hotplug lock */
  149. struct mutex ula_lock; /* allocate/free ula */
  150. struct mutex ubwcp_flush_lock; /* ubwcp flush */
  151. struct mutex hw_range_ck_lock; /* range ck */
  152. struct list_head err_handler_list; /* error handler list */
  153. spinlock_t err_handler_list_lock; /* err_handler_list lock */
  154. struct dev_pagemap pgmap;
  155. };
  156. struct ubwcp_buf {
  157. struct hlist_node hnode;
  158. struct ubwcp_driver *ubwcp;
  159. struct ubwcp_buffer_attrs buf_attr;
  160. bool perm;
  161. struct ubwcp_desc *desc;
  162. bool buf_attr_set;
  163. enum dma_data_direction dma_dir;
  164. int lock_count;
  165. /* dma_buf info */
  166. struct dma_buf *dma_buf;
  167. struct dma_buf_attachment *attachment;
  168. struct sg_table *sgt;
  169. /* ula info */
  170. phys_addr_t ula_pa;
  171. size_t ula_size;
  172. /* meta metadata */
  173. struct ubwcp_hw_meta_metadata mmdata;
  174. struct mutex lock;
  175. };
  176. static struct ubwcp_driver *me;
  177. static u32 ubwcp_debug_trace_enable;
  178. static struct ubwcp_driver *ubwcp_get_driver(void)
  179. {
  180. if (!me)
  181. WARN(1, "ubwcp: driver ptr requested but driver not initialized");
  182. return me;
  183. }
  184. static void image_format_init(struct ubwcp_driver *ubwcp)
  185. { /* planes, bytes/p, Tp , MTp */
  186. ubwcp->format_info[RGBA] = (struct ubwcp_image_format_info)
  187. {1, {{4, 1, {16, 4}, {64, 16}}}};
  188. ubwcp->format_info[NV12] = (struct ubwcp_image_format_info)
  189. {2, {{1, 1, {32, 8}, {128, 32}},
  190. {2, 1, {16, 8}, { 64, 32}}}};
  191. ubwcp->format_info[NV124R] = (struct ubwcp_image_format_info)
  192. {2, {{1, 1, {64, 4}, {256, 16}},
  193. {2, 1, {32, 4}, {128, 16}}}};
  194. ubwcp->format_info[P010] = (struct ubwcp_image_format_info)
  195. {2, {{2, 1, {32, 4}, {128, 16}},
  196. {4, 1, {16, 4}, { 64, 16}}}};
  197. ubwcp->format_info[TP10] = (struct ubwcp_image_format_info)
  198. {2, {{4, 3, {48, 4}, {192, 16}},
  199. {8, 3, {24, 4}, { 96, 16}}}};
  200. ubwcp->format_info[P016] = (struct ubwcp_image_format_info)
  201. {2, {{2, 1, {32, 4}, {128, 16}},
  202. {4, 1, {16, 4}, { 64, 16}}}};
  203. }
  204. static void ubwcp_buf_desc_list_init(struct ubwcp_driver *ubwcp)
  205. {
  206. int idx;
  207. struct ubwcp_desc *desc_list = ubwcp->desc_list;
  208. for (idx = 0; idx < UBWCP_BUFFER_DESC_COUNT; idx++) {
  209. desc_list[idx].idx = -1;
  210. desc_list[idx].ptr = NULL;
  211. }
  212. }
  213. static int ubwcp_init_clocks(struct ubwcp_driver *ubwcp, struct device *dev)
  214. {
  215. const char *cname;
  216. struct property *prop;
  217. int i;
  218. ubwcp->num_clocks =
  219. of_property_count_strings(dev->of_node, "clock-names");
  220. if (ubwcp->num_clocks < 1) {
  221. ubwcp->num_clocks = 0;
  222. return 0;
  223. }
  224. ubwcp->clocks = devm_kzalloc(dev,
  225. sizeof(*ubwcp->clocks) * ubwcp->num_clocks, GFP_KERNEL);
  226. if (!ubwcp->clocks)
  227. return -ENOMEM;
  228. i = 0;
  229. of_property_for_each_string(dev->of_node, "clock-names",
  230. prop, cname) {
  231. struct clk *c = devm_clk_get(dev, cname);
  232. if (IS_ERR(c)) {
  233. ERR("Couldn't get clock: %s\n", cname);
  234. return PTR_ERR(c);
  235. }
  236. ubwcp->clocks[i] = c;
  237. ++i;
  238. }
  239. return 0;
  240. }
  241. static int ubwcp_enable_clocks(struct ubwcp_driver *ubwcp)
  242. {
  243. int i, ret = 0;
  244. for (i = 0; i < ubwcp->num_clocks; ++i) {
  245. ret = clk_prepare_enable(ubwcp->clocks[i]);
  246. if (ret) {
  247. ERR("Couldn't enable clock #%d\n", i);
  248. while (i--)
  249. clk_disable_unprepare(ubwcp->clocks[i]);
  250. break;
  251. }
  252. }
  253. return ret;
  254. }
  255. static void ubwcp_disable_clocks(struct ubwcp_driver *ubwcp)
  256. {
  257. int i;
  258. for (i = ubwcp->num_clocks; i; --i)
  259. clk_disable_unprepare(ubwcp->clocks[i - 1]);
  260. }
  261. /* UBWCP Power control */
  262. static int ubwcp_power(struct ubwcp_driver *ubwcp, bool enable)
  263. {
  264. int ret = 0;
  265. if (enable)
  266. ret = regulator_enable(ubwcp->vdd);
  267. else
  268. ret = regulator_disable(ubwcp->vdd);
  269. if (ret) {
  270. ERR("regulator call (enable: %d) failed: %d", enable, ret);
  271. return ret;
  272. }
  273. if (enable) {
  274. ret = ubwcp_enable_clocks(ubwcp);
  275. if (ret) {
  276. ERR("enable clocks failed: %d", ret);
  277. regulator_disable(ubwcp->vdd);
  278. return ret;
  279. }
  280. } else {
  281. ubwcp_disable_clocks(ubwcp);
  282. }
  283. return ret;
  284. }
  285. /* get ubwcp_buf corresponding to the given dma_buf */
  286. static struct ubwcp_buf *dma_buf_to_ubwcp_buf(struct dma_buf *dmabuf)
  287. {
  288. struct ubwcp_buf *buf = NULL;
  289. struct ubwcp_buf *ret_buf = NULL;
  290. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  291. unsigned long flags;
  292. if (!dmabuf || !ubwcp)
  293. return NULL;
  294. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  295. /* look up ubwcp_buf corresponding to this dma_buf */
  296. hash_for_each_possible(ubwcp->buf_table, buf, hnode, (u64)dmabuf) {
  297. if (buf->dma_buf == dmabuf) {
  298. ret_buf = buf;
  299. break;
  300. }
  301. }
  302. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  303. return ret_buf;
  304. }
  305. /* return ubwcp hardware version */
  306. int ubwcp_get_hw_version(struct ubwcp_ioctl_hw_version *ver)
  307. {
  308. struct ubwcp_driver *ubwcp;
  309. if (!ver) {
  310. ERR("invalid version ptr");
  311. return -EINVAL;
  312. }
  313. ubwcp = ubwcp_get_driver();
  314. if (!ubwcp)
  315. return -1;
  316. if (ubwcp->state == UBWCP_STATE_INVALID)
  317. return -EPERM;
  318. ver->major = ubwcp->hw_ver_major;
  319. ver->minor = ubwcp->hw_ver_minor;
  320. return 0;
  321. }
  322. EXPORT_SYMBOL(ubwcp_get_hw_version);
  323. static int ula_add_mem(struct ubwcp_driver *ubwcp)
  324. {
  325. int ret = 0;
  326. int nid;
  327. void *ptr;
  328. nid = memory_add_physaddr_to_nid(ubwcp->ula_pool_base);
  329. DBG("calling memremap_pages()...");
  330. ubwcp->pgmap.type = MEMORY_DEVICE_GENERIC;
  331. ubwcp->pgmap.nr_range = 1;
  332. ubwcp->pgmap.range.start = ubwcp->ula_pool_base;
  333. ubwcp->pgmap.range.end = ubwcp->ula_pool_base + ubwcp->ula_pool_size - 1;
  334. trace_ubwcp_memremap_pages_start(ubwcp->ula_pool_size);
  335. ptr = memremap_pages(&ubwcp->pgmap, nid);
  336. trace_ubwcp_memremap_pages_end(ubwcp->ula_pool_size);
  337. if (IS_ERR(ptr)) {
  338. ret = IS_ERR(ptr);
  339. ERR("memremap_pages() failed st:0x%lx sz:0x%lx err: %d",
  340. ubwcp->ula_pool_base,
  341. ubwcp->ula_pool_size,
  342. ret);
  343. } else {
  344. DBG("memremap_pages() ula_pool_base:0x%llx, size:0x%zx, kernel addr:0x%p",
  345. ubwcp->ula_pool_base,
  346. ubwcp->ula_pool_size,
  347. page_to_virt(pfn_to_page(PFN_DOWN(ubwcp->ula_pool_base))));
  348. }
  349. return ret;
  350. }
  351. static int ula_map_uncached(u64 base, u64 size)
  352. {
  353. int ret;
  354. trace_ubwcp_set_direct_map_range_uncached_start(size);
  355. ret = set_direct_map_range_uncached((unsigned long)phys_to_virt(base), size >> PAGE_SHIFT);
  356. trace_ubwcp_set_direct_map_range_uncached_end(size);
  357. if (ret)
  358. ERR("set_direct_map_range_uncached failed st:0x%lx num pages:%lu err: %d",
  359. base, size >> PAGE_SHIFT, ret);
  360. return ret;
  361. }
  362. static void ula_unmap(struct ubwcp_driver *ubwcp)
  363. {
  364. DBG("Calling memunmap_pages() for ULA PA pool");
  365. trace_ubwcp_memunmap_pages_start(ubwcp->ula_pool_size);
  366. memunmap_pages(&ubwcp->pgmap);
  367. trace_ubwcp_memunmap_pages_end(ubwcp->ula_pool_size);
  368. }
  369. static void ula_sync_for_cpu(struct device *dev, u64 addr, unsigned long size)
  370. {
  371. trace_ubwcp_dma_sync_single_for_cpu_start(size, DMA_BIDIRECTIONAL);
  372. dma_sync_single_for_cpu(dev, addr, size, DMA_BIDIRECTIONAL);
  373. trace_ubwcp_dma_sync_single_for_cpu_end(size, DMA_BIDIRECTIONAL);
  374. }
  375. /** Remove ula memory in chunks
  376. * Abort if new buffer addition is detected
  377. * If remove succeeds or aborted, return success
  378. * status value indicates if mem was removed or aborted (not removed)
  379. * Otherwise return failure
  380. */
  381. static int ula_remove_mem(struct ubwcp_driver *ubwcp, enum ula_remove_mem_status *status)
  382. {
  383. int ret = 0;
  384. unsigned long sync_remain = ubwcp->ula_pool_size;
  385. unsigned long sync_offset = 0;
  386. unsigned long sync_size = 0;
  387. ret = ula_map_uncached(ubwcp->ula_pool_base, ubwcp->ula_pool_size);
  388. if (ret)
  389. return ret;
  390. trace_ubwcp_offline_sync_start(ubwcp->ula_pool_size);
  391. while (sync_remain > 0) {
  392. if (atomic_read(&ubwcp->num_non_lin_buffers) > 0) {
  393. trace_ubwcp_offline_sync_end(ubwcp->ula_pool_size);
  394. ula_unmap(ubwcp);
  395. if (ula_add_mem(ubwcp)) {
  396. ERR("remove mem: failed to add back during abort");
  397. return -1;
  398. }
  399. *status = ULA_REMOVE_MEM_ABORTED;
  400. return 0;
  401. }
  402. if (UBWCP_SYNC_GRANULE > sync_remain) {
  403. sync_size = sync_remain;
  404. sync_remain = 0;
  405. } else {
  406. sync_size = UBWCP_SYNC_GRANULE;
  407. sync_remain -= UBWCP_SYNC_GRANULE;
  408. }
  409. ula_sync_for_cpu(ubwcp->dev, ubwcp->ula_pool_base + sync_offset, sync_size);
  410. sync_offset += sync_size;
  411. }
  412. trace_ubwcp_offline_sync_end(ubwcp->ula_pool_size);
  413. ula_unmap(ubwcp);
  414. *status = ULA_REMOVE_MEM_SUCCESS;
  415. return 0;
  416. }
  417. static int inc_num_non_lin_buffers(struct ubwcp_driver *ubwcp)
  418. {
  419. atomic_inc(&ubwcp->num_non_lin_buffers);
  420. mutex_lock(&ubwcp->mem_hotplug_lock);
  421. if (!ubwcp->mem_online) {
  422. if (atomic_read(&ubwcp->num_non_lin_buffers) == 0) {
  423. ERR("Bad state: num_non_lin_buffers should not be 0");
  424. goto err;
  425. }
  426. if (ubwcp_power(ubwcp, true))
  427. goto err;
  428. if (ula_add_mem(ubwcp))
  429. goto err_add_memory;
  430. ubwcp->mem_online = true;
  431. }
  432. mutex_unlock(&ubwcp->mem_hotplug_lock);
  433. return 0;
  434. err_add_memory:
  435. ubwcp_power(ubwcp, false);
  436. err:
  437. atomic_dec(&ubwcp->num_non_lin_buffers);
  438. mutex_unlock(&ubwcp->mem_hotplug_lock);
  439. ubwcp->state = UBWCP_STATE_FAULT;
  440. ERR("state set to fault");
  441. return -1;
  442. }
  443. static int dec_num_non_lin_buffers(struct ubwcp_driver *ubwcp)
  444. {
  445. int ret;
  446. enum ula_remove_mem_status remove_status;
  447. atomic_dec(&ubwcp->num_non_lin_buffers);
  448. mutex_lock(&ubwcp->mem_hotplug_lock);
  449. if (atomic_read(&ubwcp->num_non_lin_buffers) == 0) {
  450. DBG("last buffer: ~~~~~~~~~~~");
  451. if (!ubwcp->mem_online) {
  452. ERR("Bad state: mem_online should not be false");
  453. goto err;
  454. }
  455. ret = ula_remove_mem(ubwcp, &remove_status);
  456. if (ret)
  457. goto err;
  458. if (remove_status == ULA_REMOVE_MEM_SUCCESS) {
  459. ubwcp->mem_online = false;
  460. if (ubwcp_power(ubwcp, false))
  461. goto err;
  462. } else if (remove_status == ULA_REMOVE_MEM_ABORTED) {
  463. DBG("ula memory offline aborted");
  464. } else {
  465. ERR("unexpected ula remove status: %d", remove_status);
  466. goto err;
  467. }
  468. }
  469. mutex_unlock(&ubwcp->mem_hotplug_lock);
  470. return 0;
  471. err:
  472. atomic_inc(&ubwcp->num_non_lin_buffers);
  473. mutex_unlock(&ubwcp->mem_hotplug_lock);
  474. ubwcp->state = UBWCP_STATE_FAULT;
  475. ERR("state set to fault");
  476. return -1;
  477. }
  478. /**
  479. *
  480. * Initialize ubwcp buffer for the given dma_buf. This
  481. * initializes ubwcp internal data structures and possibly hw to
  482. * use ubwcp for this buffer.
  483. *
  484. * @param dmabuf : ptr to the buffer to be configured for ubwcp
  485. *
  486. * @return int : 0 on success, otherwise error code
  487. */
  488. static int ubwcp_init_buffer(struct dma_buf *dmabuf)
  489. {
  490. struct ubwcp_buf *buf;
  491. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  492. unsigned long flags;
  493. trace_ubwcp_init_buffer_start(dmabuf);
  494. if (!ubwcp) {
  495. trace_ubwcp_init_buffer_end(dmabuf);
  496. return -1;
  497. }
  498. if (ubwcp->state != UBWCP_STATE_READY) {
  499. ERR("driver in invalid state: %d", ubwcp->state);
  500. trace_ubwcp_init_buffer_end(dmabuf);
  501. return -EPERM;
  502. }
  503. if (!dmabuf) {
  504. ERR("NULL dmabuf input ptr");
  505. trace_ubwcp_init_buffer_end(dmabuf);
  506. return -EINVAL;
  507. }
  508. if (dma_buf_to_ubwcp_buf(dmabuf)) {
  509. ERR("dma_buf already initialized for ubwcp");
  510. trace_ubwcp_init_buffer_end(dmabuf);
  511. return -EEXIST;
  512. }
  513. buf = kzalloc(sizeof(*buf), GFP_KERNEL);
  514. if (!buf) {
  515. ERR("failed to alloc for new ubwcp_buf");
  516. trace_ubwcp_init_buffer_end(dmabuf);
  517. return -ENOMEM;
  518. }
  519. mutex_init(&buf->lock);
  520. buf->dma_buf = dmabuf;
  521. buf->ubwcp = ubwcp;
  522. buf->buf_attr.image_format = UBWCP_LINEAR;
  523. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  524. hash_add(ubwcp->buf_table, &buf->hnode, (u64)buf->dma_buf);
  525. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  526. trace_ubwcp_init_buffer_end(dmabuf);
  527. return 0;
  528. }
  529. static void dump_attributes(struct ubwcp_buffer_attrs *attr)
  530. {
  531. DBG_BUF_ATTR("");
  532. DBG_BUF_ATTR("image_format: %d", attr->image_format);
  533. DBG_BUF_ATTR("major_ubwc_ver: %d", attr->major_ubwc_ver);
  534. DBG_BUF_ATTR("minor_ubwc_ver: %d", attr->minor_ubwc_ver);
  535. DBG_BUF_ATTR("compression_type: %d", attr->compression_type);
  536. DBG_BUF_ATTR("lossy_params: %llu", attr->lossy_params);
  537. DBG_BUF_ATTR("width: %d", attr->width);
  538. DBG_BUF_ATTR("height: %d", attr->height);
  539. DBG_BUF_ATTR("stride: %d", attr->stride);
  540. DBG_BUF_ATTR("scanlines: %d", attr->scanlines);
  541. DBG_BUF_ATTR("planar_padding: %d", attr->planar_padding);
  542. DBG_BUF_ATTR("subsample: %d", attr->subsample);
  543. DBG_BUF_ATTR("sub_system_target: %d", attr->sub_system_target);
  544. DBG_BUF_ATTR("y_offset: %d", attr->y_offset);
  545. DBG_BUF_ATTR("batch_size: %d", attr->batch_size);
  546. DBG_BUF_ATTR("");
  547. }
  548. static int to_std_format(u16 ioctl_image_format, enum ubwcp_std_image_format *format)
  549. {
  550. switch (ioctl_image_format) {
  551. case UBWCP_RGBA8888:
  552. *format = RGBA;
  553. return 0;
  554. case UBWCP_NV12:
  555. case UBWCP_NV12_Y:
  556. case UBWCP_NV12_UV:
  557. *format = NV12;
  558. return 0;
  559. case UBWCP_NV124R:
  560. case UBWCP_NV124R_Y:
  561. case UBWCP_NV124R_UV:
  562. *format = NV124R;
  563. return 0;
  564. case UBWCP_TP10:
  565. case UBWCP_TP10_Y:
  566. case UBWCP_TP10_UV:
  567. *format = TP10;
  568. return 0;
  569. case UBWCP_P010:
  570. case UBWCP_P010_Y:
  571. case UBWCP_P010_UV:
  572. *format = P010;
  573. return 0;
  574. case UBWCP_P016:
  575. case UBWCP_P016_Y:
  576. case UBWCP_P016_UV:
  577. *format = P016;
  578. return 0;
  579. default:
  580. ERR("Failed to convert ioctl image format to std format: %d", ioctl_image_format);
  581. return -1;
  582. }
  583. }
  584. static int std_to_hw_img_fmt(enum ubwcp_std_image_format format, u16 *hw_fmt)
  585. {
  586. switch (format) {
  587. case RGBA:
  588. *hw_fmt = HW_BUFFER_FORMAT_RGBA;
  589. return 0;
  590. case NV12:
  591. *hw_fmt = HW_BUFFER_FORMAT_NV12;
  592. return 0;
  593. case NV124R:
  594. *hw_fmt = HW_BUFFER_FORMAT_NV124R;
  595. return 0;
  596. case P010:
  597. *hw_fmt = HW_BUFFER_FORMAT_P010;
  598. return 0;
  599. case TP10:
  600. *hw_fmt = HW_BUFFER_FORMAT_TP10;
  601. return 0;
  602. case P016:
  603. *hw_fmt = HW_BUFFER_FORMAT_P016;
  604. return 0;
  605. default:
  606. ERR("Failed to convert std image format to hw format: %d", format);
  607. return -1;
  608. }
  609. }
  610. static int get_stride_alignment(enum ubwcp_std_image_format format, u16 *align)
  611. {
  612. switch (format) {
  613. case TP10:
  614. *align = 64;
  615. return 0;
  616. case NV12:
  617. *align = 128;
  618. return 0;
  619. case RGBA:
  620. case NV124R:
  621. case P010:
  622. case P016:
  623. *align = 256;
  624. return 0;
  625. default:
  626. return -1;
  627. }
  628. }
  629. /* returns stride of compressed image */
  630. static u32 get_compressed_stride(struct ubwcp_driver *ubwcp,
  631. enum ubwcp_std_image_format format, u32 width)
  632. {
  633. struct ubwcp_plane_info p_info;
  634. u16 macro_tile_width_p;
  635. u16 pixel_bytes;
  636. u16 per_pixel;
  637. p_info = ubwcp->format_info[format].p_info[0];
  638. macro_tile_width_p = p_info.macrotilesize_p.width;
  639. pixel_bytes = p_info.pixel_bytes;
  640. per_pixel = p_info.per_pixel;
  641. return UBWCP_ALIGN(width, macro_tile_width_p)*pixel_bytes/per_pixel;
  642. }
  643. static void
  644. ubwcp_pixel_to_bytes(struct ubwcp_driver *ubwcp,
  645. enum ubwcp_std_image_format format,
  646. u32 width_p, u32 height_p,
  647. u32 *width_b, u32 *height_b)
  648. {
  649. u16 pixel_bytes;
  650. u16 per_pixel;
  651. struct ubwcp_image_format_info f_info;
  652. struct ubwcp_plane_info p_info;
  653. f_info = ubwcp->format_info[format];
  654. p_info = f_info.p_info[0];
  655. pixel_bytes = p_info.pixel_bytes;
  656. per_pixel = p_info.per_pixel;
  657. *width_b = (width_p*pixel_bytes)/per_pixel;
  658. *height_b = (height_p*pixel_bytes)/per_pixel;
  659. }
  660. /* check if linear stride conforms to hw limitations
  661. * always returns false for linear image
  662. */
  663. static bool stride_is_valid(struct ubwcp_driver *ubwcp,
  664. enum ubwcp_std_image_format format, u32 width, u32 lin_stride)
  665. {
  666. u32 compressed_stride;
  667. u32 width_b;
  668. u32 height_b;
  669. ubwcp_pixel_to_bytes(ubwcp, format, width, 0, &width_b, &height_b);
  670. if ((lin_stride < width_b) || (lin_stride > MAX_ATTR_STRIDE)) {
  671. ERR("Invalid stride: %u width: %u width_b: %u", lin_stride, width, width_b);
  672. return false;
  673. }
  674. if (format == TP10) {
  675. if(!IS_ALIGNED(lin_stride, 64)) {
  676. ERR("stride must be aligned to 64: %d", lin_stride);
  677. return false;
  678. }
  679. } else {
  680. compressed_stride = get_compressed_stride(ubwcp, format, width);
  681. if (lin_stride != compressed_stride) {
  682. ERR("linear stride: %d must be same as compressed stride: %d",
  683. lin_stride, compressed_stride);
  684. return false;
  685. }
  686. }
  687. return true;
  688. }
  689. static bool ioctl_format_is_valid(u16 ioctl_image_format)
  690. {
  691. switch (ioctl_image_format) {
  692. case UBWCP_LINEAR:
  693. case UBWCP_RGBA8888:
  694. case UBWCP_NV12:
  695. case UBWCP_NV12_Y:
  696. case UBWCP_NV12_UV:
  697. case UBWCP_NV124R:
  698. case UBWCP_NV124R_Y:
  699. case UBWCP_NV124R_UV:
  700. case UBWCP_TP10:
  701. case UBWCP_TP10_Y:
  702. case UBWCP_TP10_UV:
  703. case UBWCP_P010:
  704. case UBWCP_P010_Y:
  705. case UBWCP_P010_UV:
  706. case UBWCP_P016:
  707. case UBWCP_P016_Y:
  708. case UBWCP_P016_UV:
  709. return true;
  710. default:
  711. return false;
  712. }
  713. }
  714. /* validate buffer attributes */
  715. static bool ubwcp_buf_attrs_valid(struct ubwcp_driver *ubwcp, struct ubwcp_buffer_attrs *attr)
  716. {
  717. enum ubwcp_std_image_format format;
  718. if (attr->unused1 || attr->unused2 || attr->unused3 || attr->unused4 || attr->unused5 ||
  719. attr->unused6 || attr->unused7 || attr->unused8 || attr->unused9) {
  720. ERR("buf attr unused values must be set to 0");
  721. goto err;
  722. }
  723. if (!ioctl_format_is_valid(attr->image_format)) {
  724. ERR("invalid image format: %d", attr->image_format);
  725. goto err;
  726. }
  727. /* rest of the fields are ignored for linear format */
  728. if (attr->image_format == UBWCP_LINEAR) {
  729. goto valid;
  730. }
  731. if (to_std_format(attr->image_format, &format))
  732. goto err;
  733. if (attr->major_ubwc_ver || attr->minor_ubwc_ver) {
  734. ERR("major/minor ubwc ver must be 0. major: %d minor: %d",
  735. attr->major_ubwc_ver, attr->minor_ubwc_ver);
  736. goto err;
  737. }
  738. if (attr->compression_type != UBWCP_COMPRESSION_LOSSLESS) {
  739. ERR("compression_type is not valid: %d",
  740. attr->compression_type);
  741. goto err;
  742. }
  743. if (attr->lossy_params != 0) {
  744. ERR("lossy_params is not valid: %d", attr->lossy_params);
  745. goto err;
  746. }
  747. if (attr->width > MAX_ATTR_WIDTH) {
  748. ERR("width is invalid (above upper limit): %d", attr->width);
  749. goto err;
  750. }
  751. if (attr->height > MAX_ATTR_HEIGHT) {
  752. ERR("height is invalid (above upper limit): %d", attr->height);
  753. goto err;
  754. }
  755. if(!stride_is_valid(ubwcp, format, attr->width, attr->stride)) {
  756. ERR("stride is invalid: %d", attr->stride);
  757. goto err;
  758. }
  759. if ((attr->scanlines < attr->height) ||
  760. (attr->scanlines > attr->height + MAX_ATTR_SCANLN_HT_DELTA)) {
  761. ERR("scanlines is not valid - height: %d scanlines: %d",
  762. attr->height, attr->scanlines);
  763. goto err;
  764. }
  765. if (attr->planar_padding > MAX_ATTR_PLANAR_PAD) {
  766. ERR("planar_padding is not valid: %d", attr->planar_padding);
  767. goto err;
  768. }
  769. if (attr->subsample != UBWCP_SUBSAMPLE_4_2_0) {
  770. ERR("subsample is not valid: %d", attr->subsample);
  771. goto err;
  772. }
  773. if (attr->sub_system_target & ~UBWCP_SUBSYSTEM_TARGET_CPU) {
  774. ERR("sub_system_target other that CPU is not supported: %d",
  775. attr->sub_system_target);
  776. goto err;
  777. }
  778. if (!(attr->sub_system_target & UBWCP_SUBSYSTEM_TARGET_CPU)) {
  779. ERR("sub_system_target is not set to CPU: %d",
  780. attr->sub_system_target);
  781. goto err;
  782. }
  783. if (attr->y_offset != 0) {
  784. ERR("y_offset is not valid: %d", attr->y_offset);
  785. goto err;
  786. }
  787. if (attr->batch_size != 1) {
  788. ERR("batch_size is not valid: %d", attr->batch_size);
  789. goto err;
  790. }
  791. valid:
  792. dump_attributes(attr);
  793. return true;
  794. err:
  795. dump_attributes(attr);
  796. return false;
  797. }
  798. /* calculate and return metadata buffer size for a given plane
  799. * and buffer attributes
  800. */
  801. static int metadata_buf_sz(struct ubwcp_driver *ubwcp,
  802. enum ubwcp_std_image_format format,
  803. u32 width, u32 height, u8 plane, size_t *size)
  804. {
  805. u64 pitch;
  806. u64 lines;
  807. u64 tile_width;
  808. u32 tile_height;
  809. struct ubwcp_image_format_info f_info;
  810. struct ubwcp_plane_info p_info;
  811. f_info = ubwcp->format_info[format];
  812. DBG_BUF_ATTR("");
  813. DBG_BUF_ATTR("");
  814. DBG_BUF_ATTR("Calculating metadata buffer size: format = %d, plane = %d", format, plane);
  815. if (plane >= f_info.planes) {
  816. ERR("Missing plane info: format: %d, plane: %d", format, plane);
  817. return -1;
  818. }
  819. p_info = f_info.p_info[plane];
  820. /* UV plane */
  821. if (plane == 1) {
  822. width = width/2;
  823. height = height/2;
  824. }
  825. tile_width = p_info.tilesize_p.width;
  826. tile_height = p_info.tilesize_p.height;
  827. /* pitch: # of tiles in a row
  828. * lines: # of tile rows
  829. */
  830. pitch = UBWCP_ALIGN((width + tile_width - 1)/tile_width, META_DATA_PITCH_ALIGN);
  831. lines = UBWCP_ALIGN((height + tile_height - 1)/tile_height, META_DATA_HEIGHT_ALIGN);
  832. DBG_BUF_ATTR("image params : %d x %d (pixels)", width, height);
  833. DBG_BUF_ATTR("tile params : %d x %d (pixels)", tile_width, tile_height);
  834. DBG_BUF_ATTR("pitch : %d (%d)", pitch, width/tile_width);
  835. DBG_BUF_ATTR("lines : %d (%d)", lines, height);
  836. DBG_BUF_ATTR("size (p*l*bytes) : %d", pitch*lines*1);
  837. /* x1 below is only to clarify that we are multiplying by 1 bytes/tile */
  838. *size = UBWCP_ALIGN(pitch*lines*1, META_DATA_SIZE_ALIGN);
  839. DBG_BUF_ATTR("size (aligned 4K): %zu (0x%zx)", *size, *size);
  840. return 0;
  841. }
  842. /* calculate and return size of pixel data buffer for a given plane
  843. * and buffer attributes
  844. */
  845. static int pixeldata_buf_sz(struct ubwcp_driver *ubwcp,
  846. u16 format, u32 width,
  847. u32 height, u8 plane, size_t *size)
  848. {
  849. u64 pitch;
  850. u64 lines;
  851. u16 pixel_bytes;
  852. u16 per_pixel;
  853. u64 macro_tile_width_p;
  854. u64 macro_tile_height_p;
  855. struct ubwcp_image_format_info f_info;
  856. struct ubwcp_plane_info p_info;
  857. f_info = ubwcp->format_info[format];
  858. DBG_BUF_ATTR("");
  859. DBG_BUF_ATTR("");
  860. DBG_BUF_ATTR("Calculating Pixeldata buffer size: format = %d, plane = %d", format, plane);
  861. if (plane >= f_info.planes) {
  862. ERR("Missing plane info: format: %d, plane: %d", format, plane);
  863. return -1;
  864. }
  865. p_info = f_info.p_info[plane];
  866. pixel_bytes = p_info.pixel_bytes;
  867. per_pixel = p_info.per_pixel;
  868. /* UV plane */
  869. if (plane == 1) {
  870. width = width/2;
  871. height = height/2;
  872. }
  873. macro_tile_width_p = p_info.macrotilesize_p.width;
  874. macro_tile_height_p = p_info.macrotilesize_p.height;
  875. /* align pixel width and height macro tile width and height */
  876. pitch = UBWCP_ALIGN(width, macro_tile_width_p);
  877. lines = UBWCP_ALIGN(height, macro_tile_height_p);
  878. DBG_BUF_ATTR("image params : %d x %d (pixels)", width, height);
  879. DBG_BUF_ATTR("macro tile params: %d x %d (pixels)", macro_tile_width_p,
  880. macro_tile_height_p);
  881. DBG_BUF_ATTR("bytes_per_pixel : %d/%d", pixel_bytes, per_pixel);
  882. DBG_BUF_ATTR("pitch : %d", pitch);
  883. DBG_BUF_ATTR("lines : %d", lines);
  884. DBG_BUF_ATTR("size (p*l*bytes) : %d", (pitch*lines*pixel_bytes)/per_pixel);
  885. *size = UBWCP_ALIGN((pitch*lines*pixel_bytes)/per_pixel, PIXEL_DATA_SIZE_ALIGN);
  886. DBG_BUF_ATTR("size (aligned 4K): %zu (0x%zx)", *size, *size);
  887. return 0;
  888. }
  889. static int get_tile_height(struct ubwcp_driver *ubwcp, enum ubwcp_std_image_format format,
  890. u8 plane)
  891. {
  892. struct ubwcp_image_format_info f_info;
  893. struct ubwcp_plane_info p_info;
  894. f_info = ubwcp->format_info[format];
  895. p_info = f_info.p_info[plane];
  896. return p_info.tilesize_p.height;
  897. }
  898. /*
  899. * plane: must be 0 or 1 (1st plane == 0, 2nd plane == 1)
  900. */
  901. static size_t ubwcp_ula_size(struct ubwcp_driver *ubwcp, u16 format,
  902. u32 stride_b, u32 scanlines, u8 plane,
  903. bool add_tile_pad)
  904. {
  905. size_t size;
  906. DBG_BUF_ATTR("%s(format = %d, plane = %d)", __func__, format, plane);
  907. /* UV plane */
  908. if (plane == 1)
  909. scanlines = scanlines/2;
  910. if (add_tile_pad) {
  911. int tile_height = get_tile_height(ubwcp, format, plane);
  912. /* Align plane size to plane tile height */
  913. scanlines = ((scanlines + tile_height - 1) / tile_height) * tile_height;
  914. }
  915. size = stride_b*scanlines;
  916. DBG_BUF_ATTR("Size of plane-%u: (%u * %u) = %zu (0x%zx)",
  917. plane, stride_b, scanlines, size, size);
  918. return size;
  919. }
  920. static int missing_plane_from_format(u16 ioctl_image_format)
  921. {
  922. int missing_plane;
  923. switch (ioctl_image_format) {
  924. case UBWCP_NV12_Y:
  925. missing_plane = 2;
  926. break;
  927. case UBWCP_NV12_UV:
  928. missing_plane = 1;
  929. break;
  930. case UBWCP_NV124R_Y:
  931. missing_plane = 2;
  932. break;
  933. case UBWCP_NV124R_UV:
  934. missing_plane = 1;
  935. break;
  936. case UBWCP_TP10_Y:
  937. missing_plane = 2;
  938. break;
  939. case UBWCP_TP10_UV:
  940. missing_plane = 1;
  941. break;
  942. case UBWCP_P010_Y:
  943. missing_plane = 2;
  944. break;
  945. case UBWCP_P010_UV:
  946. missing_plane = 1;
  947. break;
  948. case UBWCP_P016_Y:
  949. missing_plane = 2;
  950. break;
  951. case UBWCP_P016_UV:
  952. missing_plane = 1;
  953. break;
  954. default:
  955. missing_plane = 0;
  956. }
  957. return missing_plane;
  958. }
  959. static int planes_in_format(enum ubwcp_std_image_format format)
  960. {
  961. if (format == RGBA)
  962. return 1;
  963. else
  964. return 2;
  965. }
  966. static int ubwcp_validate_uv_align(struct ubwcp_driver *ubwcp,
  967. struct ubwcp_buffer_attrs *attr,
  968. size_t ula_y_plane_size,
  969. size_t uv_start_offset)
  970. {
  971. int ret = 0;
  972. size_t ula_y_plane_size_align;
  973. size_t y_tile_align_bytes;
  974. int y_tile_height;
  975. int planes;
  976. enum ubwcp_std_image_format format;
  977. ret = to_std_format(attr->image_format, &format);
  978. if (ret)
  979. goto err;
  980. /* Only validate UV align if there is both a Y and UV plane */
  981. planes = planes_in_format(format);
  982. if (planes != 2)
  983. return 0;
  984. /* Check it is cache line size aligned */
  985. if ((uv_start_offset % 64) != 0) {
  986. ret = -EINVAL;
  987. ERR("uv_start_offset %zu not cache line aligned",
  988. uv_start_offset);
  989. goto err;
  990. }
  991. /*
  992. * Check that UV plane does not overlap with any of the Y plane’s tiles
  993. */
  994. y_tile_height = get_tile_height(ubwcp, format, 0);
  995. y_tile_align_bytes = y_tile_height * attr->stride;
  996. ula_y_plane_size_align = ((ula_y_plane_size + y_tile_align_bytes - 1) /
  997. y_tile_align_bytes) * y_tile_align_bytes;
  998. if (uv_start_offset < ula_y_plane_size_align) {
  999. ret = -EINVAL;
  1000. ERR("uv offset %zu less than y plane align %zu for y plane size %zu",
  1001. uv_start_offset, ula_y_plane_size_align,
  1002. ula_y_plane_size);
  1003. goto err;
  1004. }
  1005. return 0;
  1006. err:
  1007. return ret;
  1008. }
  1009. /* calculate ULA buffer parms */
  1010. static int ubwcp_calc_ula_params(struct ubwcp_driver *ubwcp,
  1011. struct ubwcp_buffer_attrs *attr,
  1012. size_t *ula_size,
  1013. size_t *ula_y_plane_size,
  1014. size_t *uv_start_offset)
  1015. {
  1016. size_t size;
  1017. enum ubwcp_std_image_format format;
  1018. int planes;
  1019. int missing_plane;
  1020. u32 stride;
  1021. u32 scanlines;
  1022. u32 planar_padding;
  1023. int ret;
  1024. ret = to_std_format(attr->image_format, &format);
  1025. if (ret)
  1026. return ret;
  1027. stride = attr->stride;
  1028. scanlines = attr->scanlines;
  1029. planar_padding = attr->planar_padding;
  1030. /* Number of "expected" planes in "the standard defined" image format */
  1031. planes = planes_in_format(format);
  1032. missing_plane = missing_plane_from_format(attr->image_format);
  1033. DBG_BUF_ATTR("ula params -->");
  1034. DBG_BUF_ATTR("ioctl_image_format : %d, std_format: %d", attr->image_format, format);
  1035. DBG_BUF_ATTR("planes_in_format : %d", planes);
  1036. DBG_BUF_ATTR("missing_plane : %d", missing_plane);
  1037. DBG_BUF_ATTR("Planar Padding : %d", planar_padding);
  1038. if (planes == 1) {
  1039. /* uv_start beyond ULA range */
  1040. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 0, true);
  1041. *uv_start_offset = size;
  1042. *ula_y_plane_size = size;
  1043. } else {
  1044. if (!missing_plane) {
  1045. /* size for both planes and padding */
  1046. /* Don't pad out Y plane as client would not expect this padding */
  1047. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 0, false);
  1048. *ula_y_plane_size = size;
  1049. size += planar_padding;
  1050. *uv_start_offset = size;
  1051. size += ubwcp_ula_size(ubwcp, format, stride, scanlines, 1, true);
  1052. } else {
  1053. if (missing_plane == 2) {
  1054. /* Y-only image, set uv_start beyond ULA range */
  1055. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 0, true);
  1056. *uv_start_offset = size;
  1057. *ula_y_plane_size = size;
  1058. } else {
  1059. /* first plane data is not there */
  1060. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 1, true);
  1061. *uv_start_offset = 0; /* uv data is at the beginning */
  1062. *ula_y_plane_size = 0;
  1063. }
  1064. }
  1065. }
  1066. *ula_size = UBWCP_ALIGN(size, 4096);
  1067. DBG_BUF_ATTR("ULA_Size: %zu (0x%x) (before 4K align: %zu)", *ula_size, *ula_size, size);
  1068. return 0;
  1069. }
  1070. /* calculate UBWCP buffer parms */
  1071. static int ubwcp_calc_ubwcp_buf_params(struct ubwcp_driver *ubwcp,
  1072. struct ubwcp_buffer_attrs *attr,
  1073. size_t *md_p0, size_t *pd_p0,
  1074. size_t *md_p1, size_t *pd_p1,
  1075. size_t *stride_tp10_b)
  1076. {
  1077. int planes;
  1078. int missing_plane;
  1079. enum ubwcp_std_image_format format;
  1080. size_t stride_tp10_p;
  1081. int ret;
  1082. ret = to_std_format(attr->image_format, &format);
  1083. if (ret)
  1084. return ret;
  1085. missing_plane = missing_plane_from_format(attr->image_format);
  1086. planes = planes_in_format(format);
  1087. DBG_BUF_ATTR("ubwcp params -->");
  1088. DBG_BUF_ATTR("ioctl_image_format : %d, std_format: %d", attr->image_format, format);
  1089. DBG_BUF_ATTR("planes_in_format : %d", planes);
  1090. DBG_BUF_ATTR("missing_plane : %d", missing_plane);
  1091. *md_p0 = 0;
  1092. *pd_p0 = 0;
  1093. *md_p1 = 0;
  1094. *pd_p1 = 0;
  1095. *stride_tp10_b = 0;
  1096. if (missing_plane != 1) {
  1097. if (metadata_buf_sz(ubwcp, format, attr->width, attr->height, 0, md_p0))
  1098. return -1;
  1099. if (pixeldata_buf_sz(ubwcp, format, attr->width, attr->height, 0, pd_p0))
  1100. return -1;
  1101. }
  1102. if ((planes == 2) && (missing_plane != 2)){
  1103. if (metadata_buf_sz(ubwcp, format, attr->width, attr->height, 1, md_p1))
  1104. return -1;
  1105. if (pixeldata_buf_sz(ubwcp, format, attr->width, attr->height, 1, pd_p1))
  1106. return -1;
  1107. }
  1108. if (format == TP10) {
  1109. stride_tp10_p = UBWCP_ALIGN(attr->width, 192);
  1110. *stride_tp10_b = (stride_tp10_p/3) + stride_tp10_p;
  1111. }
  1112. return 0;
  1113. }
  1114. /* reserve ULA address space of the given size */
  1115. static phys_addr_t ubwcp_ula_alloc(struct ubwcp_driver *ubwcp, size_t size)
  1116. {
  1117. phys_addr_t pa;
  1118. mutex_lock(&ubwcp->ula_lock);
  1119. pa = gen_pool_alloc(ubwcp->ula_pool, size);
  1120. mutex_unlock(&ubwcp->ula_lock);
  1121. return pa;
  1122. }
  1123. /* free ULA address space of the given address and size */
  1124. static void ubwcp_ula_free(struct ubwcp_driver *ubwcp, phys_addr_t pa, size_t size)
  1125. {
  1126. mutex_lock(&ubwcp->ula_lock);
  1127. if (!gen_pool_has_addr(ubwcp->ula_pool, pa, size)) {
  1128. ERR("Attempt to free mem not from gen_pool: pa: %p, size: %zx", pa, size);
  1129. goto err;
  1130. }
  1131. DBG("addr: %p, size: %zx", pa, size);
  1132. gen_pool_free(ubwcp->ula_pool, pa, size);
  1133. mutex_unlock(&ubwcp->ula_lock);
  1134. return;
  1135. err:
  1136. mutex_unlock(&ubwcp->ula_lock);
  1137. }
  1138. /* free up or expand current_pa and return the new pa */
  1139. static phys_addr_t ubwcp_ula_realloc(struct ubwcp_driver *ubwcp,
  1140. phys_addr_t pa,
  1141. size_t size,
  1142. size_t new_size)
  1143. {
  1144. if (size == new_size)
  1145. return pa;
  1146. if (pa)
  1147. ubwcp_ula_free(ubwcp, pa, size);
  1148. return ubwcp_ula_alloc(ubwcp, new_size);
  1149. }
  1150. /* unmap dma buf */
  1151. static void ubwcp_dma_unmap(struct ubwcp_buf *buf)
  1152. {
  1153. if (buf->dma_buf && buf->attachment) {
  1154. DBG("Calling dma_buf_unmap_attachment()");
  1155. dma_buf_unmap_attachment(buf->attachment, buf->sgt, DMA_BIDIRECTIONAL);
  1156. buf->sgt = NULL;
  1157. dma_buf_detach(buf->dma_buf, buf->attachment);
  1158. buf->attachment = NULL;
  1159. }
  1160. }
  1161. static bool verify_dma_buf_size(struct ubwcp_buf *buf, size_t min_size)
  1162. {
  1163. size_t dma_len;
  1164. dma_len = sg_dma_len(buf->sgt->sgl);
  1165. if (dma_len < min_size) {
  1166. ERR("dma len: %zu is less than min ubwcp buffer size: %zu", dma_len, min_size);
  1167. return false;
  1168. } else
  1169. return true;
  1170. }
  1171. /* dma map ubwcp buffer */
  1172. static int ubwcp_dma_map(struct ubwcp_buf *buf,
  1173. struct device *dev,
  1174. dma_addr_t *iova)
  1175. {
  1176. int ret = 0;
  1177. struct dma_buf *dma_buf = buf->dma_buf;
  1178. struct dma_buf_attachment *attachment;
  1179. struct sg_table *sgt;
  1180. /* Map buffer to SMMU and get IOVA */
  1181. attachment = dma_buf_attach(dma_buf, dev);
  1182. if (IS_ERR(attachment)) {
  1183. ret = PTR_ERR(attachment);
  1184. ERR("dma_buf_attach() failed: %d", ret);
  1185. goto err;
  1186. }
  1187. dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
  1188. dma_set_seg_boundary(dev, (unsigned long)DMA_BIT_MASK(64));
  1189. sgt = dma_buf_map_attachment(attachment, DMA_BIDIRECTIONAL);
  1190. if (IS_ERR_OR_NULL(sgt)) {
  1191. ret = PTR_ERR(sgt);
  1192. ERR("dma_buf_map_attachment() failed: %d", ret);
  1193. goto err_detach;
  1194. }
  1195. if (sgt->nents != 1) {
  1196. ERR("nents = %d", sgt->nents);
  1197. goto err_unmap;
  1198. }
  1199. *iova = sg_dma_address(sgt->sgl);
  1200. buf->attachment = attachment;
  1201. buf->sgt = sgt;
  1202. return ret;
  1203. err_unmap:
  1204. dma_buf_unmap_attachment(attachment, sgt, DMA_BIDIRECTIONAL);
  1205. err_detach:
  1206. dma_buf_detach(dma_buf, attachment);
  1207. err:
  1208. if (!ret)
  1209. ret = -1;
  1210. return ret;
  1211. }
  1212. static void reset_buf_attrs(struct ubwcp_buf *buf)
  1213. {
  1214. struct ubwcp_hw_meta_metadata *mmdata;
  1215. struct ubwcp_driver *ubwcp;
  1216. ubwcp = buf->ubwcp;
  1217. mmdata = &buf->mmdata;
  1218. ubwcp_dma_unmap(buf);
  1219. /* reset ula params */
  1220. if (buf->ula_size) {
  1221. ubwcp_ula_free(ubwcp, buf->ula_pa, buf->ula_size);
  1222. buf->ula_size = 0;
  1223. buf->ula_pa = 0;
  1224. }
  1225. /* reset ubwcp params */
  1226. memset(mmdata, 0, sizeof(*mmdata));
  1227. buf->buf_attr_set = false;
  1228. buf->buf_attr.image_format = UBWCP_LINEAR;
  1229. }
  1230. static void print_mmdata_desc(struct ubwcp_hw_meta_metadata *mmdata)
  1231. {
  1232. DBG_BUF_ATTR("");
  1233. DBG_BUF_ATTR("--------MM_DATA DESC ---------");
  1234. DBG_BUF_ATTR("uv_start_addr : 0x%08llx (cache addr) (actual: 0x%llx)",
  1235. mmdata->uv_start_addr, mmdata->uv_start_addr << 6);
  1236. DBG_BUF_ATTR("format : 0x%08x", mmdata->format);
  1237. DBG_BUF_ATTR("stride : 0x%08x (cache addr) (actual: 0x%x)",
  1238. mmdata->stride, mmdata->stride << 6);
  1239. DBG_BUF_ATTR("stride_ubwcp : 0x%08x (cache addr) (actual: 0x%zx)",
  1240. mmdata->stride_ubwcp, mmdata->stride_ubwcp << 6);
  1241. DBG_BUF_ATTR("metadata_base_y : 0x%08x (page addr) (actual: 0x%llx)",
  1242. mmdata->metadata_base_y, mmdata->metadata_base_y << 12);
  1243. DBG_BUF_ATTR("metadata_base_uv: 0x%08x (page addr) (actual: 0x%zx)",
  1244. mmdata->metadata_base_uv, mmdata->metadata_base_uv << 12);
  1245. DBG_BUF_ATTR("buffer_y_offset : 0x%08x (page addr) (actual: 0x%zx)",
  1246. mmdata->buffer_y_offset, mmdata->buffer_y_offset << 12);
  1247. DBG_BUF_ATTR("buffer_uv_offset: 0x%08x (page addr) (actual: 0x%zx)",
  1248. mmdata->buffer_uv_offset, mmdata->buffer_uv_offset << 12);
  1249. DBG_BUF_ATTR("width_height : 0x%08x (width: 0x%x height: 0x%x)",
  1250. mmdata->width_height, mmdata->width_height >> 16, mmdata->width_height & 0xFFFF);
  1251. DBG_BUF_ATTR("");
  1252. }
  1253. /* set buffer attributes:
  1254. * Failure:
  1255. * This call may fail for multiple reasons and it will leave the buffer in an undefined state.
  1256. * In some situations it may leave the buffer in linear mapped state, and in other situations it
  1257. * may leave the buffer in previously set attributes state.
  1258. */
  1259. int ubwcp_set_buf_attrs(struct dma_buf *dmabuf, struct ubwcp_buffer_attrs *attr)
  1260. {
  1261. int ret = 0;
  1262. size_t ula_size = 0;
  1263. size_t uv_start_offset = 0;
  1264. size_t ula_y_plane_size = 0;
  1265. phys_addr_t ula_pa = 0x0;
  1266. struct ubwcp_buf *buf;
  1267. struct ubwcp_driver *ubwcp;
  1268. size_t metadata_p0;
  1269. size_t pixeldata_p0;
  1270. size_t metadata_p1;
  1271. size_t pixeldata_p1;
  1272. size_t iova_min_size;
  1273. size_t stride_tp10_b;
  1274. dma_addr_t iova_base;
  1275. struct ubwcp_hw_meta_metadata *mmdata;
  1276. u64 uv_start;
  1277. u32 stride_b;
  1278. u32 width_b;
  1279. u32 height_b;
  1280. enum ubwcp_std_image_format std_image_format;
  1281. bool is_non_lin_buf;
  1282. u16 hw_img_format;
  1283. trace_ubwcp_set_buf_attrs_start(dmabuf);
  1284. if (!dmabuf) {
  1285. ERR("NULL dmabuf input ptr");
  1286. ret = -EINVAL;
  1287. goto err_validation;
  1288. }
  1289. if (!attr) {
  1290. ERR("NULL attr ptr");
  1291. ret = -EINVAL;
  1292. goto err_validation;
  1293. }
  1294. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1295. if (!buf) {
  1296. ERR("No corresponding ubwcp_buf for the passed in dma_buf");
  1297. ret = -EINVAL;
  1298. goto err_validation;
  1299. }
  1300. ubwcp = buf->ubwcp;
  1301. if (ubwcp->state != UBWCP_STATE_READY) {
  1302. ret = EPERM;
  1303. goto err_validation;
  1304. }
  1305. if (!ubwcp_buf_attrs_valid(ubwcp, attr)) {
  1306. ERR("Invalid buf attrs");
  1307. ret = -EINVAL;
  1308. goto err_validation;
  1309. }
  1310. mutex_lock(&buf->lock);
  1311. if (buf->lock_count) {
  1312. ERR("Cannot set attr when buffer is locked");
  1313. ret = -EBUSY;
  1314. goto unlock;
  1315. }
  1316. mmdata = &buf->mmdata;
  1317. is_non_lin_buf = (buf->buf_attr.image_format != UBWCP_LINEAR);
  1318. /* note: this also checks if buf is mmap'ed */
  1319. ret = ubwcp->mmap_config_fptr(buf->dma_buf, true, 0, 0);
  1320. if (ret) {
  1321. ERR("dma_buf_mmap_config(0,0) failed: %d", ret);
  1322. goto unlock;
  1323. }
  1324. if (attr->image_format == UBWCP_LINEAR) {
  1325. DBG_BUF_ATTR("Linear format requested");
  1326. if (buf->buf_attr_set)
  1327. reset_buf_attrs(buf);
  1328. if (is_non_lin_buf) {
  1329. /*
  1330. * Changing buffer from ubwc to linear so decrement
  1331. * number of ubwc buffers
  1332. */
  1333. ret = dec_num_non_lin_buffers(ubwcp);
  1334. }
  1335. mutex_unlock(&buf->lock);
  1336. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1337. return ret;
  1338. }
  1339. if (to_std_format(attr->image_format, &std_image_format)) {
  1340. ERR("Unable to map ioctl image format to std image format");
  1341. goto unlock;
  1342. }
  1343. if (std_to_hw_img_fmt(std_image_format, &hw_img_format)) {
  1344. ERR("Unable to map std image format to hw image format");
  1345. goto unlock;
  1346. }
  1347. /* Calculate uncompressed-buffer size. */
  1348. ret = ubwcp_calc_ula_params(ubwcp, attr, &ula_size, &ula_y_plane_size, &uv_start_offset);
  1349. if (ret) {
  1350. ERR("ubwcp_calc_ula_params() failed: %d", ret);
  1351. goto unlock;
  1352. }
  1353. ret = ubwcp_validate_uv_align(ubwcp, attr, ula_y_plane_size, uv_start_offset);
  1354. if (ret) {
  1355. ERR("ubwcp_validate_uv_align() failed: %d", ret);
  1356. goto unlock;
  1357. }
  1358. ret = ubwcp_calc_ubwcp_buf_params(ubwcp, attr, &metadata_p0, &pixeldata_p0, &metadata_p1,
  1359. &pixeldata_p1, &stride_tp10_b);
  1360. if (ret) {
  1361. ERR("ubwcp_calc_buf_params() failed: %d", ret);
  1362. goto unlock;
  1363. }
  1364. iova_min_size = metadata_p0 + pixeldata_p0 + metadata_p1 + pixeldata_p1;
  1365. DBG_BUF_ATTR("");
  1366. DBG_BUF_ATTR("");
  1367. DBG_BUF_ATTR("------Summary ULA Calculated Params ------");
  1368. DBG_BUF_ATTR("ULA Size : %8zu (0x%8zx)", ula_size, ula_size);
  1369. DBG_BUF_ATTR("UV Start Offset : %8zu (0x%8zx)", uv_start_offset, uv_start_offset);
  1370. DBG_BUF_ATTR("------Summary UBCP Calculated Params ------");
  1371. DBG_BUF_ATTR("metadata_p0 : %8d (0x%8zx)", metadata_p0, metadata_p0);
  1372. DBG_BUF_ATTR("pixeldata_p0 : %8d (0x%8zx)", pixeldata_p0, pixeldata_p0);
  1373. DBG_BUF_ATTR("metadata_p1 : %8d (0x%8zx)", metadata_p1, metadata_p1);
  1374. DBG_BUF_ATTR("pixeldata_p1 : %8d (0x%8zx)", pixeldata_p1, pixeldata_p1);
  1375. DBG_BUF_ATTR("stride_tp10 : %8d (0x%8zx)", stride_tp10_b, stride_tp10_b);
  1376. DBG_BUF_ATTR("iova_min_size : %8d (0x%8zx)", iova_min_size, iova_min_size);
  1377. DBG_BUF_ATTR("");
  1378. /* assign ULA PA with uncompressed-size range */
  1379. ula_pa = ubwcp_ula_realloc(ubwcp, buf->ula_pa, buf->ula_size, ula_size);
  1380. if (!ula_pa) {
  1381. ERR("ubwcp_ula_alloc/realloc() failed. running out of ULA PA space?");
  1382. goto err;
  1383. }
  1384. buf->ula_size = ula_size;
  1385. buf->ula_pa = ula_pa;
  1386. DBG_BUF_ATTR("Allocated ULA_PA: 0x%p of size: 0x%zx", ula_pa, ula_size);
  1387. DBG_BUF_ATTR("");
  1388. /* dma map only the first time attribute is set */
  1389. if (!buf->buf_attr_set) {
  1390. /* linear -> ubwcp. map ubwcp buffer */
  1391. ret = ubwcp_dma_map(buf, ubwcp->dev_buf_cb, &iova_base);
  1392. if (ret) {
  1393. ERR("ubwcp_dma_map() failed: %d", ret);
  1394. goto err;
  1395. }
  1396. DBG_BUF_ATTR("dma_buf IOVA range: 0x%llx + min_size (0x%zx): 0x%llx",
  1397. iova_base, iova_min_size, iova_base + iova_min_size);
  1398. }
  1399. if(!verify_dma_buf_size(buf, iova_min_size))
  1400. goto err;
  1401. uv_start = ula_pa + uv_start_offset;
  1402. if (!IS_ALIGNED(uv_start, 64)) {
  1403. ERR("ERROR: uv_start is NOT aligned to cache line");
  1404. goto err;
  1405. }
  1406. /* Convert height and width to bytes for writing to mmdata */
  1407. if (std_image_format != TP10) {
  1408. ubwcp_pixel_to_bytes(ubwcp, std_image_format, attr->width,
  1409. attr->height, &width_b, &height_b);
  1410. } else {
  1411. /* for tp10 image compression, we need to program p010 width/height */
  1412. ubwcp_pixel_to_bytes(ubwcp, P010, attr->width,
  1413. attr->height, &width_b, &height_b);
  1414. }
  1415. stride_b = attr->stride;
  1416. /* create the mmdata descriptor */
  1417. memset(mmdata, 0, sizeof(*mmdata));
  1418. mmdata->uv_start_addr = CACHE_ADDR(uv_start);
  1419. mmdata->format = hw_img_format;
  1420. if (std_image_format != TP10) {
  1421. mmdata->stride = CACHE_ADDR(stride_b); /* uncompressed stride */
  1422. } else {
  1423. mmdata->stride = CACHE_ADDR(stride_tp10_b); /* compressed stride */
  1424. mmdata->stride_ubwcp = CACHE_ADDR(stride_b); /* uncompressed stride */
  1425. }
  1426. mmdata->metadata_base_y = PAGE_ADDR(iova_base);
  1427. mmdata->metadata_base_uv = PAGE_ADDR(iova_base + metadata_p0 + pixeldata_p0);
  1428. mmdata->buffer_y_offset = PAGE_ADDR(metadata_p0);
  1429. mmdata->buffer_uv_offset = PAGE_ADDR(metadata_p1);
  1430. /* NOTE: For version 1.1, both width & height needs to be in bytes.
  1431. * For other versions, width in bytes & height in pixels.
  1432. */
  1433. if ((ubwcp->hw_ver_major == 1) && (ubwcp->hw_ver_minor == 1))
  1434. mmdata->width_height = width_b << 16 | height_b;
  1435. else
  1436. mmdata->width_height = width_b << 16 | attr->height;
  1437. print_mmdata_desc(mmdata);
  1438. if (!is_non_lin_buf) {
  1439. /*
  1440. * Changing buffer from linear to ubwc so increment
  1441. * number of ubwc buffers
  1442. */
  1443. ret = inc_num_non_lin_buffers(ubwcp);
  1444. }
  1445. if (ret) {
  1446. ERR("inc_num_non_lin_buffers failed: %d", ret);
  1447. goto err;
  1448. }
  1449. /* inform ULA-PA to dma-heap */
  1450. DBG_BUF_ATTR("Calling mmap_config(): ULA_PA: 0x%p size: 0x%zx", ula_pa, ula_size);
  1451. ret = ubwcp->mmap_config_fptr(buf->dma_buf, false, buf->ula_pa, buf->ula_size);
  1452. if (ret) {
  1453. ERR("dma_buf_mmap_config() failed: %d", ret);
  1454. if (!is_non_lin_buf)
  1455. dec_num_non_lin_buffers(ubwcp);
  1456. goto err;
  1457. }
  1458. buf->buf_attr = *attr;
  1459. buf->buf_attr_set = true;
  1460. mutex_unlock(&buf->lock);
  1461. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1462. return 0;
  1463. err:
  1464. reset_buf_attrs(buf);
  1465. if (is_non_lin_buf) {
  1466. /*
  1467. * Changing buffer from ubwc to linear so decrement
  1468. * number of ubwc buffers
  1469. */
  1470. dec_num_non_lin_buffers(ubwcp);
  1471. }
  1472. unlock:
  1473. mutex_unlock(&buf->lock);
  1474. err_validation:
  1475. if (!ret)
  1476. ret = -1;
  1477. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1478. return ret;
  1479. }
  1480. EXPORT_SYMBOL(ubwcp_set_buf_attrs);
  1481. /* Free up the buffer descriptor */
  1482. static void ubwcp_buf_desc_free(struct ubwcp_driver *ubwcp, struct ubwcp_desc *desc)
  1483. {
  1484. int idx = desc->idx;
  1485. struct ubwcp_desc *desc_list = ubwcp->desc_list;
  1486. mutex_lock(&ubwcp->desc_lock);
  1487. desc_list[idx].idx = -1;
  1488. desc_list[idx].ptr = NULL;
  1489. DBG("freed descriptor_id: %d", idx);
  1490. mutex_unlock(&ubwcp->desc_lock);
  1491. }
  1492. /* Allocate next available buffer descriptor. */
  1493. static struct ubwcp_desc *ubwcp_buf_desc_allocate(struct ubwcp_driver *ubwcp)
  1494. {
  1495. int idx;
  1496. struct ubwcp_desc *desc_list = ubwcp->desc_list;
  1497. mutex_lock(&ubwcp->desc_lock);
  1498. for (idx = 0; idx < UBWCP_BUFFER_DESC_COUNT; idx++) {
  1499. if (desc_list[idx].idx == -1) {
  1500. desc_list[idx].idx = idx;
  1501. desc_list[idx].ptr = ubwcp->buffer_desc_base +
  1502. idx*UBWCP_BUFFER_DESC_OFFSET;
  1503. DBG("allocated descriptor_id: %d", idx);
  1504. mutex_unlock(&ubwcp->desc_lock);
  1505. return &desc_list[idx];
  1506. }
  1507. }
  1508. mutex_unlock(&ubwcp->desc_lock);
  1509. return NULL;
  1510. }
  1511. static int ubwcp_flush(struct ubwcp_driver *ubwcp)
  1512. {
  1513. int ret = 0;
  1514. mutex_lock(&ubwcp->ubwcp_flush_lock);
  1515. trace_ubwcp_hw_flush_start(0);
  1516. ret = ubwcp_hw_flush(ubwcp->base);
  1517. trace_ubwcp_hw_flush_end(0);
  1518. if (ret)
  1519. ERR("ubwcp_hw_flush() failed, ret = %d", ret);
  1520. mutex_unlock(&ubwcp->ubwcp_flush_lock);
  1521. return ret;
  1522. }
  1523. static int range_check_disable(struct ubwcp_driver *ubwcp, int idx)
  1524. {
  1525. int ret;
  1526. mutex_lock(&ubwcp->ubwcp_flush_lock);
  1527. mutex_lock(&ubwcp->hw_range_ck_lock);
  1528. trace_ubwcp_hw_flush_start(0);
  1529. ret = ubwcp_hw_disable_range_check_with_flush(ubwcp->base, idx);
  1530. trace_ubwcp_hw_flush_end(0);
  1531. if (ret)
  1532. ERR("disable_range_check_with_flush() failed: %d", ret);
  1533. mutex_unlock(&ubwcp->hw_range_ck_lock);
  1534. mutex_unlock(&ubwcp->ubwcp_flush_lock);
  1535. return ret;
  1536. }
  1537. static void range_check_enable(struct ubwcp_driver *ubwcp, int idx)
  1538. {
  1539. mutex_lock(&ubwcp->hw_range_ck_lock);
  1540. ubwcp_hw_enable_range_check(ubwcp->base, idx);
  1541. mutex_unlock(&ubwcp->hw_range_ck_lock);
  1542. }
  1543. /**
  1544. * Lock buffer for CPU access. This prepares ubwcp hw to allow
  1545. * CPU access to the compressed buffer. It will perform
  1546. * necessary address translation configuration and cache maintenance ops
  1547. * so that CPU can safely access ubwcp buffer, if this call is
  1548. * successful.
  1549. * Allocate descriptor if not already,
  1550. * perform CMO and then enable range check
  1551. *
  1552. * @param dmabuf : ptr to the dma buf
  1553. * @param direction : direction of access
  1554. *
  1555. * @return int : 0 on success, otherwise error code
  1556. */
  1557. static int ubwcp_lock(struct dma_buf *dmabuf, enum dma_data_direction dir)
  1558. {
  1559. int ret = 0;
  1560. struct ubwcp_buf *buf;
  1561. struct ubwcp_driver *ubwcp;
  1562. trace_ubwcp_lock_start(dmabuf);
  1563. if (!dmabuf) {
  1564. ERR("NULL dmabuf input ptr");
  1565. trace_ubwcp_lock_end(dmabuf);
  1566. return -EINVAL;
  1567. }
  1568. if (!valid_dma_direction(dir)) {
  1569. ERR("invalid direction: %d", dir);
  1570. trace_ubwcp_lock_end(dmabuf);
  1571. return -EINVAL;
  1572. }
  1573. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1574. if (!buf) {
  1575. ERR("ubwcp_buf ptr not found");
  1576. trace_ubwcp_lock_end(dmabuf);
  1577. return -1;
  1578. }
  1579. ubwcp = buf->ubwcp;
  1580. if (ubwcp->state != UBWCP_STATE_READY) {
  1581. ERR("driver in invalid state: %d", ubwcp->state);
  1582. trace_ubwcp_lock_end(dmabuf);
  1583. return -EPERM;
  1584. }
  1585. mutex_lock(&buf->lock);
  1586. if (!buf->buf_attr_set) {
  1587. ERR("lock() called on buffer, but attr not set");
  1588. goto err;
  1589. }
  1590. if (buf->buf_attr.image_format == UBWCP_LINEAR) {
  1591. ERR("lock() called on linear buffer");
  1592. goto err;
  1593. }
  1594. if (!buf->lock_count) {
  1595. DBG("first lock on buffer");
  1596. /* buf->desc could already be allocated because of perm range xlation */
  1597. if (!buf->desc) {
  1598. /* allocate a buffer descriptor */
  1599. buf->desc = ubwcp_buf_desc_allocate(buf->ubwcp);
  1600. if (!buf->desc) {
  1601. ERR("ubwcp_allocate_buf_desc() failed");
  1602. goto err;
  1603. }
  1604. memcpy(buf->desc->ptr, &buf->mmdata, sizeof(buf->mmdata));
  1605. /* Flushing of updated mmdata:
  1606. * mmdata is iocoherent and ubwcp will get it from CPU cache -
  1607. * *as long as* it has not cached that itself during previous
  1608. * access to the same descriptor.
  1609. *
  1610. * During unlock of previous use of this descriptor,
  1611. * we do hw flush, which will get rid of this mmdata from
  1612. * ubwcp cache.
  1613. *
  1614. * In addition, we also do a hw flush after enable_range_ck().
  1615. * That will also get rid of any speculative fetch of mmdata
  1616. * by the ubwcp hw. At this time, the assumption is that ubwcp
  1617. * will cache mmdata only for active descriptor. But if ubwcp
  1618. * is speculatively fetching mmdata for all descriptors
  1619. * (irrespetive of enabled or not), the flush during lock
  1620. * will be necessary to make sure ubwcp sees updated mmdata
  1621. * that we just updated
  1622. */
  1623. /* program ULA range for this buffer */
  1624. DBG("setting range check: descriptor_id: %d, addr: %p, size: %zx",
  1625. buf->desc->idx, buf->ula_pa, buf->ula_size);
  1626. ubwcp_hw_set_range_check(ubwcp->base, buf->desc->idx, buf->ula_pa,
  1627. buf->ula_size);
  1628. }
  1629. /* enable range check */
  1630. DBG("enabling range check, descriptor_id: %d", buf->desc->idx);
  1631. range_check_enable(ubwcp, buf->desc->idx);
  1632. /* Flush/invalidate UBWCP caches */
  1633. /* Why: cpu could have done a speculative fetch before
  1634. * enable_range_ck() and ubwcp in process of returning "default" data
  1635. * we don't want that stashing of default data pending.
  1636. * we force completion of that and then we also cpu invalidate which
  1637. * will get rid of that line.
  1638. */
  1639. ret = ubwcp_flush(ubwcp);
  1640. if (ret) {
  1641. ubwcp->state = UBWCP_STATE_FAULT;
  1642. ERR("state set to fault");
  1643. goto err_flush_failed;
  1644. }
  1645. /* Flush/invalidate ULA PA from CPU caches
  1646. * Always invalidate cache, even when writing.
  1647. * Upgrade direction to force invalidate.
  1648. */
  1649. if (dir == DMA_TO_DEVICE)
  1650. dir = DMA_BIDIRECTIONAL;
  1651. trace_ubwcp_dma_sync_single_for_cpu_start(buf->ula_size, dir);
  1652. dma_sync_single_for_cpu(ubwcp->dev, buf->ula_pa, buf->ula_size, dir);
  1653. trace_ubwcp_dma_sync_single_for_cpu_end(buf->ula_size, dir);
  1654. buf->dma_dir = dir;
  1655. } else {
  1656. DBG("buf already locked");
  1657. /* For write locks, always upgrade direction to bi_directional.
  1658. * A previous read lock will now become write lock.
  1659. * This will ensure a flush when the last unlock comes in.
  1660. */
  1661. if ((dir == DMA_TO_DEVICE) || (dir == DMA_BIDIRECTIONAL))
  1662. buf->dma_dir = DMA_BIDIRECTIONAL;
  1663. }
  1664. buf->lock_count++;
  1665. DBG("new lock_count: %d", buf->lock_count);
  1666. mutex_unlock(&buf->lock);
  1667. trace_ubwcp_lock_end(dmabuf);
  1668. return ret;
  1669. err_flush_failed:
  1670. range_check_disable(ubwcp, buf->desc->idx);
  1671. ubwcp_buf_desc_free(ubwcp, buf->desc);
  1672. buf->desc = NULL;
  1673. err:
  1674. mutex_unlock(&buf->lock);
  1675. if (!ret)
  1676. ret = -1;
  1677. trace_ubwcp_lock_end(dmabuf);
  1678. return ret;
  1679. }
  1680. /* This can be called as a result of external unlock() call or
  1681. * internally if free() is called without unlock().
  1682. */
  1683. static int unlock_internal(struct ubwcp_buf *buf, enum dma_data_direction dir, bool free_buffer)
  1684. {
  1685. int ret = 0;
  1686. struct ubwcp_driver *ubwcp;
  1687. DBG("current lock_count: %d", buf->lock_count);
  1688. if (free_buffer) {
  1689. buf->lock_count = 0;
  1690. DBG("Forced lock_count: %d", buf->lock_count);
  1691. } else {
  1692. /* for write unlocks, remember the direction so we flush on last unlock */
  1693. if ((dir == DMA_TO_DEVICE) || (dir == DMA_BIDIRECTIONAL))
  1694. buf->dma_dir = DMA_BIDIRECTIONAL;
  1695. buf->lock_count--;
  1696. DBG("new lock_count: %d", buf->lock_count);
  1697. if (buf->lock_count) {
  1698. DBG("more than 1 lock on buffer. waiting until last unlock");
  1699. return 0;
  1700. }
  1701. }
  1702. ubwcp = buf->ubwcp;
  1703. /* Only apply CMOs if there were potential CPU writes */
  1704. if (buf->dma_dir == DMA_TO_DEVICE || buf->dma_dir == DMA_BIDIRECTIONAL) {
  1705. /* Flush/invalidate ULA PA from CPU caches */
  1706. trace_ubwcp_dma_sync_single_for_device_start(buf->ula_size, buf->dma_dir);
  1707. dma_sync_single_for_device(ubwcp->dev, buf->ula_pa, buf->ula_size, buf->dma_dir);
  1708. trace_ubwcp_dma_sync_single_for_device_end(buf->ula_size, buf->dma_dir);
  1709. }
  1710. /* disable range check */
  1711. DBG("disabling range check");
  1712. ret = range_check_disable(ubwcp, buf->desc->idx);
  1713. if (ret) {
  1714. ubwcp->state = UBWCP_STATE_FAULT;
  1715. ERR("state set to fault");
  1716. }
  1717. /* release descriptor if perm range xlation is not set */
  1718. if (!buf->perm) {
  1719. ubwcp_buf_desc_free(buf->ubwcp, buf->desc);
  1720. buf->desc = NULL;
  1721. }
  1722. return ret;
  1723. }
  1724. /**
  1725. * Unlock buffer from CPU access. This prepares ubwcp hw to
  1726. * safely allow for device access to the compressed buffer including any
  1727. * necessary cache maintenance ops. It may also free up certain ubwcp
  1728. * resources that could result in error when accessed by CPU in
  1729. * unlocked state.
  1730. *
  1731. * @param dmabuf : ptr to the dma buf
  1732. * @param direction : direction of access
  1733. *
  1734. * @return int : 0 on success, otherwise error code
  1735. */
  1736. static int ubwcp_unlock(struct dma_buf *dmabuf, enum dma_data_direction dir)
  1737. {
  1738. struct ubwcp_buf *buf;
  1739. int ret;
  1740. trace_ubwcp_unlock_start(dmabuf);
  1741. if (!dmabuf) {
  1742. ERR("NULL dmabuf input ptr");
  1743. trace_ubwcp_unlock_end(dmabuf);
  1744. return -EINVAL;
  1745. }
  1746. if (!valid_dma_direction(dir)) {
  1747. ERR("invalid direction: %d", dir);
  1748. trace_ubwcp_unlock_end(dmabuf);
  1749. return -EINVAL;
  1750. }
  1751. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1752. if (!buf) {
  1753. ERR("ubwcp_buf not found");
  1754. trace_ubwcp_unlock_end(dmabuf);
  1755. return -1;
  1756. }
  1757. if (buf->ubwcp->state != UBWCP_STATE_READY) {
  1758. ERR("driver in invalid state: %d", buf->ubwcp->state);
  1759. trace_ubwcp_unlock_end(dmabuf);
  1760. return -EPERM;
  1761. }
  1762. mutex_lock(&buf->lock);
  1763. if (!buf->lock_count) {
  1764. ERR("unlock() called on buffer which not in locked state");
  1765. trace_ubwcp_unlock_end(dmabuf);
  1766. mutex_unlock(&buf->lock);
  1767. return -1;
  1768. }
  1769. ret = unlock_internal(buf, dir, false);
  1770. mutex_unlock(&buf->lock);
  1771. trace_ubwcp_unlock_end(dmabuf);
  1772. return ret;
  1773. }
  1774. /* Return buffer attributes for the given buffer */
  1775. int ubwcp_get_buf_attrs(struct dma_buf *dmabuf, struct ubwcp_buffer_attrs *attr)
  1776. {
  1777. int ret = 0;
  1778. struct ubwcp_buf *buf;
  1779. if (!dmabuf) {
  1780. ERR("NULL dmabuf input ptr");
  1781. return -EINVAL;
  1782. }
  1783. if (!attr) {
  1784. ERR("NULL attr ptr");
  1785. return -EINVAL;
  1786. }
  1787. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1788. if (!buf) {
  1789. ERR("ubwcp_buf ptr not found");
  1790. return -1;
  1791. }
  1792. if (buf->ubwcp->state != UBWCP_STATE_READY) {
  1793. ERR("driver in invalid state: %d", buf->ubwcp->state);
  1794. return -EPERM;
  1795. }
  1796. mutex_lock(&buf->lock);
  1797. if (!buf->buf_attr_set) {
  1798. ERR("buffer attributes not set");
  1799. mutex_unlock(&buf->lock);
  1800. return -1;
  1801. }
  1802. *attr = buf->buf_attr;
  1803. mutex_unlock(&buf->lock);
  1804. return ret;
  1805. }
  1806. EXPORT_SYMBOL(ubwcp_get_buf_attrs);
  1807. /* Set permanent range translation.
  1808. * enable: Descriptor will be reserved for this buffer until disabled,
  1809. * making lock/unlock quicker.
  1810. * disable: Descriptor will not be reserved for this buffer. Instead,
  1811. * descriptor will be allocated and released for each lock/unlock.
  1812. * If currently allocated but not being used, descriptor will be
  1813. * released.
  1814. */
  1815. int ubwcp_set_perm_range_translation(struct dma_buf *dmabuf, bool enable)
  1816. {
  1817. int ret = 0;
  1818. struct ubwcp_buf *buf;
  1819. if (!dmabuf) {
  1820. ERR("NULL dmabuf input ptr");
  1821. return -EINVAL;
  1822. }
  1823. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1824. if (!buf) {
  1825. ERR("ubwcp_buf not found");
  1826. return -1;
  1827. }
  1828. if (buf->ubwcp->state != UBWCP_STATE_READY) {
  1829. ERR("driver in invalid state: %d", buf->ubwcp->state);
  1830. return -EPERM;
  1831. }
  1832. /* not implemented */
  1833. if (1) {
  1834. ERR("API not implemented yet");
  1835. return -1;
  1836. }
  1837. /* TBD: make sure we acquire buf lock while setting this so there is
  1838. * no race condition with attr_set/lock/unlock
  1839. */
  1840. buf->perm = enable;
  1841. /* if "disable" and we have allocated a desc and it is not being
  1842. * used currently, release it
  1843. */
  1844. if (!enable && buf->desc && !buf->lock_count) {
  1845. ubwcp_buf_desc_free(buf->ubwcp, buf->desc);
  1846. buf->desc = NULL;
  1847. /* Flush/invalidate UBWCP caches */
  1848. //TBD: need to do anything?
  1849. }
  1850. return ret;
  1851. }
  1852. EXPORT_SYMBOL(ubwcp_set_perm_range_translation);
  1853. /**
  1854. * Free up ubwcp resources for this buffer.
  1855. *
  1856. * @param dmabuf : ptr to the dma buf
  1857. *
  1858. * @return int : 0 on success, otherwise error code
  1859. */
  1860. static int ubwcp_free_buffer(struct dma_buf *dmabuf)
  1861. {
  1862. int ret = 0;
  1863. struct ubwcp_buf *buf;
  1864. struct ubwcp_driver *ubwcp;
  1865. unsigned long flags;
  1866. bool is_non_lin_buf;
  1867. trace_ubwcp_free_buffer_start(dmabuf);
  1868. if (!dmabuf) {
  1869. ERR("NULL dmabuf input ptr");
  1870. trace_ubwcp_free_buffer_end(dmabuf);
  1871. return -EINVAL;
  1872. }
  1873. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1874. if (!buf) {
  1875. ERR("ubwcp_buf ptr not found");
  1876. trace_ubwcp_free_buffer_end(dmabuf);
  1877. return -1;
  1878. }
  1879. ubwcp = buf->ubwcp;
  1880. if (ubwcp->state != UBWCP_STATE_READY) {
  1881. ERR("driver in invalid state: %d", ubwcp->state);
  1882. trace_ubwcp_free_buffer_end(dmabuf);
  1883. return -EPERM;
  1884. }
  1885. mutex_lock(&buf->lock);
  1886. is_non_lin_buf = (buf->buf_attr.image_format != UBWCP_LINEAR);
  1887. if (buf->lock_count) {
  1888. DBG("free before unlock (lock_count: %d). unlock()'ing first", buf->lock_count);
  1889. ret = unlock_internal(buf, buf->dma_dir, true);
  1890. if (ret)
  1891. ERR("unlock_internal(): failed : %d, but continuing free()", ret);
  1892. }
  1893. /* if we are still holding a desc, release it. this can happen only if perm == true */
  1894. if (buf->desc) {
  1895. if (!buf->perm) {
  1896. ubwcp->state = UBWCP_STATE_FAULT;
  1897. ERR("state set to fault");
  1898. }
  1899. ubwcp_buf_desc_free(buf->ubwcp, buf->desc);
  1900. buf->desc = NULL;
  1901. }
  1902. if (buf->buf_attr_set)
  1903. reset_buf_attrs(buf);
  1904. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  1905. hash_del(&buf->hnode);
  1906. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  1907. mutex_unlock(&buf->lock);
  1908. kfree(buf);
  1909. if (is_non_lin_buf)
  1910. dec_num_non_lin_buffers(ubwcp);
  1911. trace_ubwcp_free_buffer_end(dmabuf);
  1912. return ret;
  1913. }
  1914. /* file open: TBD: increment ref count? */
  1915. static int ubwcp_open(struct inode *i, struct file *f)
  1916. {
  1917. return 0;
  1918. }
  1919. /* file open: TBD: decrement ref count? */
  1920. static int ubwcp_close(struct inode *i, struct file *f)
  1921. {
  1922. return 0;
  1923. }
  1924. static int ioctl_set_buf_attr(struct ubwcp_driver *ubwcp, unsigned long ioctl_param)
  1925. {
  1926. int ret;
  1927. struct dma_buf *dmabuf;
  1928. struct ubwcp_ioctl_buffer_attrs buf_attr_ioctl;
  1929. if (copy_from_user(&buf_attr_ioctl, (const void __user *) ioctl_param,
  1930. sizeof(buf_attr_ioctl))) {
  1931. ERR("copy_from_user() failed");
  1932. return -EFAULT;
  1933. }
  1934. DBG("IOCTL: SET_BUF_ATTR: fd = %d", buf_attr_ioctl.fd);
  1935. dmabuf = dma_buf_get(buf_attr_ioctl.fd);
  1936. if (IS_ERR(dmabuf)) {
  1937. ERR("dmabuf ptr not found for dma_buf_fd = %d", buf_attr_ioctl.fd);
  1938. return PTR_ERR(dmabuf);
  1939. }
  1940. ret = ubwcp_set_buf_attrs(dmabuf, &buf_attr_ioctl.attr);
  1941. dma_buf_put(dmabuf);
  1942. return ret;
  1943. }
  1944. static int ioctl_get_hw_ver(struct ubwcp_driver *ubwcp, unsigned long ioctl_param)
  1945. {
  1946. struct ubwcp_ioctl_hw_version hw_ver;
  1947. DBG("IOCTL: GET_HW_VER");
  1948. if (ubwcp_get_hw_version(&hw_ver))
  1949. return -EINVAL;
  1950. if (copy_to_user((void __user *)ioctl_param, &hw_ver, sizeof(hw_ver))) {
  1951. ERR("copy_to_user() failed");
  1952. return -EFAULT;
  1953. }
  1954. return 0;
  1955. }
  1956. static int ioctl_get_stride_align(struct ubwcp_driver *ubwcp, unsigned long ioctl_param)
  1957. {
  1958. struct ubwcp_ioctl_stride_align stride_align_ioctl;
  1959. enum ubwcp_std_image_format format;
  1960. DBG("IOCTL: GET_STRIDE_ALIGN");
  1961. if (copy_from_user(&stride_align_ioctl, (const void __user *) ioctl_param,
  1962. sizeof(stride_align_ioctl))) {
  1963. ERR("copy_from_user() failed");
  1964. return -EFAULT;
  1965. }
  1966. if (stride_align_ioctl.unused != 0) {
  1967. ERR("unused values must be set to 0");
  1968. return -EINVAL;
  1969. }
  1970. if (!ioctl_format_is_valid(stride_align_ioctl.image_format)) {
  1971. ERR("invalid image format: %d", stride_align_ioctl.image_format);
  1972. return -EINVAL;
  1973. }
  1974. if (stride_align_ioctl.image_format == UBWCP_LINEAR) {
  1975. ERR("not supported for LINEAR format");
  1976. return -EINVAL;
  1977. }
  1978. if (to_std_format(stride_align_ioctl.image_format, &format)) {
  1979. ERR("Unable to map ioctl image format to std image format");
  1980. return -EINVAL;
  1981. }
  1982. if (get_stride_alignment(format, &stride_align_ioctl.stride_align)) {
  1983. ERR("failed for format: %d", format);
  1984. return -EFAULT;
  1985. }
  1986. if (copy_to_user((void __user *)ioctl_param, &stride_align_ioctl,
  1987. sizeof(stride_align_ioctl))) {
  1988. ERR("copy_to_user() failed");
  1989. return -EFAULT;
  1990. }
  1991. return 0;
  1992. }
  1993. static int ioctl_validate_stride(struct ubwcp_driver *ubwcp, unsigned long ioctl_param)
  1994. {
  1995. struct ubwcp_ioctl_validate_stride validate_stride_ioctl;
  1996. enum ubwcp_std_image_format format;
  1997. DBG("IOCTL: VALIDATE_STRIDE");
  1998. if (copy_from_user(&validate_stride_ioctl, (const void __user *) ioctl_param,
  1999. sizeof(validate_stride_ioctl))) {
  2000. ERR("copy_from_user() failed");
  2001. return -EFAULT;
  2002. }
  2003. if (validate_stride_ioctl.unused1 || validate_stride_ioctl.unused2) {
  2004. ERR("unused values must be set to 0");
  2005. return -EINVAL;
  2006. }
  2007. if (!ioctl_format_is_valid(validate_stride_ioctl.image_format)) {
  2008. ERR("not supported for LINEAR format");
  2009. return -EINVAL;
  2010. }
  2011. if (validate_stride_ioctl.image_format == UBWCP_LINEAR) {
  2012. ERR("not supported for LINEAR format");
  2013. return -EINVAL;
  2014. }
  2015. if (to_std_format(validate_stride_ioctl.image_format, &format)) {
  2016. ERR("Unable to map ioctl image format to std image format");
  2017. return -EINVAL;
  2018. }
  2019. validate_stride_ioctl.valid = stride_is_valid(ubwcp, format, validate_stride_ioctl.width,
  2020. validate_stride_ioctl.stride);
  2021. if (copy_to_user((void __user *)ioctl_param, &validate_stride_ioctl,
  2022. sizeof(validate_stride_ioctl))) {
  2023. ERR("copy_to_user() failed");
  2024. return -EFAULT;
  2025. }
  2026. return 0;
  2027. }
  2028. /* handle IOCTLs */
  2029. static long ubwcp_ioctl(struct file *file, unsigned int ioctl_num, unsigned long ioctl_param)
  2030. {
  2031. struct ubwcp_driver *ubwcp;
  2032. ubwcp = ubwcp_get_driver();
  2033. if (!ubwcp)
  2034. return -EINVAL;
  2035. if (ubwcp->state != UBWCP_STATE_READY) {
  2036. ERR("driver in invalid state: %d", ubwcp->state);
  2037. return -EPERM;
  2038. }
  2039. switch (ioctl_num) {
  2040. case UBWCP_IOCTL_SET_BUF_ATTR:
  2041. return ioctl_set_buf_attr(ubwcp, ioctl_param);
  2042. case UBWCP_IOCTL_GET_HW_VER:
  2043. return ioctl_get_hw_ver(ubwcp, ioctl_param);
  2044. case UBWCP_IOCTL_GET_STRIDE_ALIGN:
  2045. return ioctl_get_stride_align(ubwcp, ioctl_param);
  2046. case UBWCP_IOCTL_VALIDATE_STRIDE:
  2047. return ioctl_validate_stride(ubwcp, ioctl_param);
  2048. default:
  2049. ERR("Invalid ioctl_num = %d", ioctl_num);
  2050. return -EINVAL;
  2051. }
  2052. return 0;
  2053. }
  2054. static const struct file_operations ubwcp_fops = {
  2055. .owner = THIS_MODULE,
  2056. .open = ubwcp_open,
  2057. .release = ubwcp_close,
  2058. .unlocked_ioctl = ubwcp_ioctl,
  2059. };
  2060. static int read_err_r_op(void *data, u64 *value)
  2061. {
  2062. struct ubwcp_driver *ubwcp = data;
  2063. *value = ubwcp->read_err_irq_en;
  2064. return 0;
  2065. }
  2066. static int read_err_w_op(void *data, u64 value)
  2067. {
  2068. struct ubwcp_driver *ubwcp = data;
  2069. if (ubwcp->state != UBWCP_STATE_READY)
  2070. return -EPERM;
  2071. if (ubwcp_power(ubwcp, true))
  2072. goto err;
  2073. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, value);
  2074. ubwcp->read_err_irq_en = value;
  2075. if (ubwcp_power(ubwcp, false))
  2076. goto err;
  2077. return 0;
  2078. err:
  2079. ubwcp->state = UBWCP_STATE_FAULT;
  2080. ERR("state set to fault");
  2081. return -1;
  2082. }
  2083. static int write_err_r_op(void *data, u64 *value)
  2084. {
  2085. struct ubwcp_driver *ubwcp = data;
  2086. if (ubwcp->state != UBWCP_STATE_READY)
  2087. return -EPERM;
  2088. *value = ubwcp->write_err_irq_en;
  2089. return 0;
  2090. }
  2091. static int write_err_w_op(void *data, u64 value)
  2092. {
  2093. struct ubwcp_driver *ubwcp = data;
  2094. if (ubwcp->state != UBWCP_STATE_READY)
  2095. return -EPERM;
  2096. if (ubwcp_power(ubwcp, true))
  2097. goto err;
  2098. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, value);
  2099. ubwcp->write_err_irq_en = value;
  2100. if (ubwcp_power(ubwcp, false))
  2101. goto err;
  2102. return 0;
  2103. err:
  2104. ubwcp->state = UBWCP_STATE_FAULT;
  2105. ERR("state set to fault");
  2106. return -1;
  2107. }
  2108. static int decode_err_r_op(void *data, u64 *value)
  2109. {
  2110. struct ubwcp_driver *ubwcp = data;
  2111. if (ubwcp->state != UBWCP_STATE_READY)
  2112. return -EPERM;
  2113. *value = ubwcp->decode_err_irq_en;
  2114. return 0;
  2115. }
  2116. static int decode_err_w_op(void *data, u64 value)
  2117. {
  2118. struct ubwcp_driver *ubwcp = data;
  2119. if (ubwcp->state != UBWCP_STATE_READY)
  2120. return -EPERM;
  2121. if (ubwcp_power(ubwcp, true))
  2122. goto err;
  2123. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, value);
  2124. ubwcp->decode_err_irq_en = value;
  2125. if (ubwcp_power(ubwcp, false))
  2126. goto err;
  2127. return 0;
  2128. err:
  2129. ubwcp->state = UBWCP_STATE_FAULT;
  2130. ERR("state set to fault");
  2131. return -1;
  2132. }
  2133. static int encode_err_r_op(void *data, u64 *value)
  2134. {
  2135. struct ubwcp_driver *ubwcp = data;
  2136. if (ubwcp->state != UBWCP_STATE_READY)
  2137. return -EPERM;
  2138. *value = ubwcp->encode_err_irq_en;
  2139. return 0;
  2140. }
  2141. static int encode_err_w_op(void *data, u64 value)
  2142. {
  2143. struct ubwcp_driver *ubwcp = data;
  2144. if (ubwcp->state != UBWCP_STATE_READY)
  2145. return -EPERM;
  2146. if (ubwcp_power(ubwcp, true))
  2147. goto err;
  2148. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, value);
  2149. ubwcp->encode_err_irq_en = value;
  2150. if (ubwcp_power(ubwcp, false))
  2151. goto err;
  2152. return 0;
  2153. err:
  2154. ubwcp->state = UBWCP_STATE_FAULT;
  2155. ERR("state set to fault");
  2156. return -1;
  2157. }
  2158. static int reg_rw_trace_w_op(void *data, u64 value)
  2159. {
  2160. struct ubwcp_driver *ubwcp = data;
  2161. if (ubwcp->state != UBWCP_STATE_READY)
  2162. return -EPERM;
  2163. ubwcp_hw_trace_set(value);
  2164. return 0;
  2165. }
  2166. static int reg_rw_trace_r_op(void *data, u64 *value)
  2167. {
  2168. struct ubwcp_driver *ubwcp = data;
  2169. bool trace_status;
  2170. if (ubwcp->state != UBWCP_STATE_READY)
  2171. return -EPERM;
  2172. ubwcp_hw_trace_get(&trace_status);
  2173. *value = trace_status;
  2174. return 0;
  2175. }
  2176. DEFINE_DEBUGFS_ATTRIBUTE(read_err_fops, read_err_r_op, read_err_w_op, "%d\n");
  2177. DEFINE_DEBUGFS_ATTRIBUTE(decode_err_fops, decode_err_r_op, decode_err_w_op, "%d\n");
  2178. DEFINE_DEBUGFS_ATTRIBUTE(write_err_fops, write_err_r_op, write_err_w_op, "%d\n");
  2179. DEFINE_DEBUGFS_ATTRIBUTE(encode_err_fops, encode_err_r_op, encode_err_w_op, "%d\n");
  2180. DEFINE_DEBUGFS_ATTRIBUTE(reg_rw_trace_fops, reg_rw_trace_r_op, reg_rw_trace_w_op, "%d\n");
  2181. static void ubwcp_debugfs_init(struct ubwcp_driver *ubwcp)
  2182. {
  2183. struct dentry *debugfs_root;
  2184. struct dentry *dfile;
  2185. debugfs_root = debugfs_create_dir("ubwcp", NULL);
  2186. if (IS_ERR_OR_NULL(debugfs_root)) {
  2187. ERR("Failed to create debugfs for ubwcp\n");
  2188. return;
  2189. }
  2190. debugfs_create_u32("debug_trace_enable", 0644, debugfs_root, &ubwcp_debug_trace_enable);
  2191. dfile = debugfs_create_file("reg_rw_trace_en", 0644, debugfs_root, ubwcp, &reg_rw_trace_fops);
  2192. if (IS_ERR_OR_NULL(dfile)) {
  2193. ERR("failed to create reg_rw_trace_en debugfs file");
  2194. goto err;
  2195. }
  2196. dfile = debugfs_create_file("read_err_irq_en", 0644, debugfs_root, ubwcp, &read_err_fops);
  2197. if (IS_ERR_OR_NULL(dfile)) {
  2198. ERR("failed to create read_err_irq debugfs file");
  2199. goto err;
  2200. }
  2201. dfile = debugfs_create_file("write_err_irq_en", 0644, debugfs_root, ubwcp, &write_err_fops);
  2202. if (IS_ERR_OR_NULL(dfile)) {
  2203. ERR("failed to create write_err_irq debugfs file");
  2204. goto err;
  2205. }
  2206. dfile = debugfs_create_file("decode_err_irq_en", 0644, debugfs_root, ubwcp,
  2207. &decode_err_fops);
  2208. if (IS_ERR_OR_NULL(dfile)) {
  2209. ERR("failed to create decode_err_irq debugfs file");
  2210. goto err;
  2211. }
  2212. dfile = debugfs_create_file("encode_err_irq_en", 0644, debugfs_root, ubwcp,
  2213. &encode_err_fops);
  2214. if (IS_ERR_OR_NULL(dfile)) {
  2215. ERR("failed to create encode_err_irq debugfs file");
  2216. goto err;
  2217. }
  2218. ubwcp->debugfs_root = debugfs_root;
  2219. return;
  2220. err:
  2221. debugfs_remove_recursive(ubwcp->debugfs_root);
  2222. ubwcp->debugfs_root = NULL;
  2223. }
  2224. static void ubwcp_debugfs_deinit(struct ubwcp_driver *ubwcp)
  2225. {
  2226. debugfs_remove_recursive(ubwcp->debugfs_root);
  2227. }
  2228. /* ubwcp char device initialization */
  2229. static int ubwcp_cdev_init(struct ubwcp_driver *ubwcp)
  2230. {
  2231. int ret;
  2232. dev_t devt;
  2233. struct class *dev_class;
  2234. struct device *dev_sys;
  2235. /* allocate major device number (/proc/devices -> major_num ubwcp) */
  2236. ret = alloc_chrdev_region(&devt, 0, UBWCP_NUM_DEVICES, UBWCP_DEVICE_NAME);
  2237. if (ret) {
  2238. ERR("alloc_chrdev_region() failed: %d", ret);
  2239. return ret;
  2240. }
  2241. /* create device class (/sys/class/ubwcp_class) */
  2242. dev_class = class_create(THIS_MODULE, "ubwcp_class");
  2243. if (IS_ERR(dev_class)) {
  2244. ret = PTR_ERR(dev_class);
  2245. ERR("class_create() failed, ret: %d", ret);
  2246. goto err;
  2247. }
  2248. /* Create device and register with sysfs
  2249. * (/sys/class/ubwcp_class/ubwcp/... -> dev/power/subsystem/uevent)
  2250. */
  2251. dev_sys = device_create(dev_class, NULL, devt, NULL,
  2252. UBWCP_DEVICE_NAME);
  2253. if (IS_ERR(dev_sys)) {
  2254. ret = PTR_ERR(dev_sys);
  2255. ERR("device_create() failed, ret: %d", ret);
  2256. goto err_device_create;
  2257. }
  2258. /* register file operations and get cdev */
  2259. cdev_init(&ubwcp->cdev, &ubwcp_fops);
  2260. /* associate cdev and device major/minor with file system
  2261. * can do file ops on /dev/ubwcp after this
  2262. */
  2263. ret = cdev_add(&ubwcp->cdev, devt, 1);
  2264. if (ret) {
  2265. ERR("cdev_add() failed, ret: %d", ret);
  2266. goto err_cdev_add;
  2267. }
  2268. ubwcp->devt = devt;
  2269. ubwcp->dev_class = dev_class;
  2270. ubwcp->dev_sys = dev_sys;
  2271. return 0;
  2272. err_cdev_add:
  2273. device_destroy(dev_class, devt);
  2274. err_device_create:
  2275. class_destroy(dev_class);
  2276. err:
  2277. unregister_chrdev_region(devt, UBWCP_NUM_DEVICES);
  2278. return ret;
  2279. }
  2280. static void ubwcp_cdev_deinit(struct ubwcp_driver *ubwcp)
  2281. {
  2282. device_destroy(ubwcp->dev_class, ubwcp->devt);
  2283. class_destroy(ubwcp->dev_class);
  2284. cdev_del(&ubwcp->cdev);
  2285. unregister_chrdev_region(ubwcp->devt, UBWCP_NUM_DEVICES);
  2286. }
  2287. struct handler_node {
  2288. struct list_head list;
  2289. u32 client_id;
  2290. ubwcp_error_handler_t handler;
  2291. void *data;
  2292. };
  2293. int ubwcp_register_error_handler(u32 client_id, ubwcp_error_handler_t handler,
  2294. void *data)
  2295. {
  2296. struct handler_node *node;
  2297. unsigned long flags;
  2298. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2299. if (!ubwcp)
  2300. return -EINVAL;
  2301. if (client_id != -1)
  2302. return -EINVAL;
  2303. if (!handler)
  2304. return -EINVAL;
  2305. if (ubwcp->state != UBWCP_STATE_READY)
  2306. return -EPERM;
  2307. node = kzalloc(sizeof(*node), GFP_KERNEL);
  2308. if (!node)
  2309. return -ENOMEM;
  2310. node->client_id = client_id;
  2311. node->handler = handler;
  2312. node->data = data;
  2313. spin_lock_irqsave(&ubwcp->err_handler_list_lock, flags);
  2314. list_add_tail(&node->list, &ubwcp->err_handler_list);
  2315. spin_unlock_irqrestore(&ubwcp->err_handler_list_lock, flags);
  2316. return 0;
  2317. }
  2318. EXPORT_SYMBOL(ubwcp_register_error_handler);
  2319. static void ubwcp_notify_error_handlers(struct ubwcp_err_info *err)
  2320. {
  2321. struct handler_node *node;
  2322. unsigned long flags;
  2323. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2324. if (!ubwcp)
  2325. return;
  2326. spin_lock_irqsave(&ubwcp->err_handler_list_lock, flags);
  2327. list_for_each_entry(node, &ubwcp->err_handler_list, list)
  2328. node->handler(err, node->data);
  2329. spin_unlock_irqrestore(&ubwcp->err_handler_list_lock, flags);
  2330. }
  2331. int ubwcp_unregister_error_handler(u32 client_id)
  2332. {
  2333. int ret = -EINVAL;
  2334. struct handler_node *node;
  2335. unsigned long flags;
  2336. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2337. if (!ubwcp)
  2338. return -EINVAL;
  2339. if (ubwcp->state != UBWCP_STATE_INVALID)
  2340. return -EPERM;
  2341. spin_lock_irqsave(&ubwcp->err_handler_list_lock, flags);
  2342. list_for_each_entry(node, &ubwcp->err_handler_list, list)
  2343. if (node->client_id == client_id) {
  2344. list_del(&node->list);
  2345. kfree(node);
  2346. ret = 0;
  2347. break;
  2348. }
  2349. spin_unlock_irqrestore(&ubwcp->err_handler_list_lock, flags);
  2350. return ret;
  2351. }
  2352. EXPORT_SYMBOL(ubwcp_unregister_error_handler);
  2353. /* get ubwcp_buf corresponding to the ULA PA*/
  2354. static struct dma_buf *get_dma_buf_from_ulapa(phys_addr_t addr)
  2355. {
  2356. struct ubwcp_buf *buf = NULL;
  2357. struct dma_buf *ret_buf = NULL;
  2358. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2359. unsigned long flags;
  2360. u32 i;
  2361. if (!ubwcp)
  2362. return NULL;
  2363. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  2364. hash_for_each(ubwcp->buf_table, i, buf, hnode) {
  2365. if (buf->ula_pa <= addr && addr < buf->ula_pa + buf->ula_size) {
  2366. ret_buf = buf->dma_buf;
  2367. break;
  2368. }
  2369. }
  2370. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  2371. return ret_buf;
  2372. }
  2373. /* get ubwcp_buf corresponding to the IOVA*/
  2374. static struct dma_buf *get_dma_buf_from_iova(unsigned long addr)
  2375. {
  2376. struct ubwcp_buf *buf = NULL;
  2377. struct dma_buf *ret_buf = NULL;
  2378. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2379. unsigned long flags;
  2380. u32 i;
  2381. if (!ubwcp)
  2382. return NULL;
  2383. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  2384. hash_for_each(ubwcp->buf_table, i, buf, hnode) {
  2385. unsigned long iova_base;
  2386. unsigned int iova_size;
  2387. if (!buf->sgt)
  2388. continue;
  2389. iova_base = sg_dma_address(buf->sgt->sgl);
  2390. iova_size = sg_dma_len(buf->sgt->sgl);
  2391. if (iova_base <= addr && addr < iova_base + iova_size) {
  2392. ret_buf = buf->dma_buf;
  2393. break;
  2394. }
  2395. }
  2396. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  2397. return ret_buf;
  2398. }
  2399. int ubwcp_iommu_fault_handler(struct iommu_domain *domain, struct device *dev,
  2400. unsigned long iova, int flags, void *data)
  2401. {
  2402. int ret = 0;
  2403. struct ubwcp_err_info err;
  2404. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2405. struct device *cb_dev = (struct device *)data;
  2406. if (!ubwcp) {
  2407. ret = -EINVAL;
  2408. goto err;
  2409. }
  2410. err.err_code = UBWCP_SMMU_FAULT;
  2411. if (cb_dev == ubwcp->dev_desc_cb)
  2412. err.smmu_err.iommu_dev_id = UBWCP_DESC_CB_ID;
  2413. else if (cb_dev == ubwcp->dev_buf_cb)
  2414. err.smmu_err.iommu_dev_id = UBWCP_BUF_CB_ID;
  2415. else
  2416. err.smmu_err.iommu_dev_id = UBWCP_UNKNOWN_CB_ID;
  2417. err.smmu_err.dmabuf = get_dma_buf_from_iova(iova);
  2418. err.smmu_err.iova = iova;
  2419. err.smmu_err.iommu_fault_flags = flags;
  2420. ERR("ubwcp_err: err code: %d (smmu), iommu_dev_id: %d, iova: 0x%llx, flags: 0x%x",
  2421. err.err_code, err.smmu_err.iommu_dev_id, err.smmu_err.iova,
  2422. err.smmu_err.iommu_fault_flags);
  2423. ubwcp_notify_error_handlers(&err);
  2424. err:
  2425. return ret;
  2426. }
  2427. static irqreturn_t ubwcp_irq_handler(int irq, void *ptr)
  2428. {
  2429. struct ubwcp_driver *ubwcp;
  2430. void __iomem *base;
  2431. phys_addr_t addr;
  2432. struct ubwcp_err_info err;
  2433. ubwcp = (struct ubwcp_driver *) ptr;
  2434. base = ubwcp->base;
  2435. if (irq == ubwcp->irq_range_ck_rd) {
  2436. addr = ubwcp_hw_interrupt_src_address(base, 0) << 6;
  2437. err.err_code = UBWCP_RANGE_TRANSLATION_ERROR;
  2438. err.translation_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2439. err.translation_err.ula_pa = addr;
  2440. err.translation_err.read = true;
  2441. ERR("err_code: %d (range read), dmabuf: 0x%llx, read: %d, addr: 0x%llx",
  2442. err.err_code, err.translation_err.dmabuf, err.translation_err.read, addr);
  2443. ubwcp_notify_error_handlers(&err);
  2444. ubwcp_hw_interrupt_clear(ubwcp->base, 0);
  2445. } else if (irq == ubwcp->irq_range_ck_wr) {
  2446. addr = ubwcp_hw_interrupt_src_address(base, 1) << 6;
  2447. err.err_code = UBWCP_RANGE_TRANSLATION_ERROR;
  2448. err.translation_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2449. err.translation_err.ula_pa = addr;
  2450. err.translation_err.read = false;
  2451. ERR("err_code: %d (range write), dmabuf: 0x%llx, read: %d, addr: 0x%llx",
  2452. err.err_code, err.translation_err.dmabuf, err.translation_err.read, addr);
  2453. ubwcp_notify_error_handlers(&err);
  2454. ubwcp_hw_interrupt_clear(ubwcp->base, 1);
  2455. } else if (irq == ubwcp->irq_encode) {
  2456. addr = ubwcp_hw_interrupt_src_address(base, 3) << 6;
  2457. err.err_code = UBWCP_ENCODE_ERROR;
  2458. err.enc_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2459. err.enc_err.ula_pa = addr;
  2460. ERR("err_code: %d (encode), dmabuf: 0x%llx, addr: 0x%llx",
  2461. err.err_code, err.enc_err.dmabuf, addr);
  2462. ubwcp_notify_error_handlers(&err);
  2463. ubwcp_hw_interrupt_clear(ubwcp->base, 3);
  2464. } else if (irq == ubwcp->irq_decode) {
  2465. addr = ubwcp_hw_interrupt_src_address(base, 2) << 6;
  2466. err.err_code = UBWCP_DECODE_ERROR;
  2467. err.dec_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2468. err.dec_err.ula_pa = addr;
  2469. ERR("err_code: %d (decode), dmabuf: 0x%llx, addr: 0x%llx",
  2470. err.err_code, err.enc_err.dmabuf, addr);
  2471. ubwcp_notify_error_handlers(&err);
  2472. ubwcp_hw_interrupt_clear(ubwcp->base, 2);
  2473. } else {
  2474. ERR("unknown irq: %d", irq);
  2475. return IRQ_NONE;
  2476. }
  2477. return IRQ_HANDLED;
  2478. }
  2479. static int ubwcp_interrupt_register(struct platform_device *pdev, struct ubwcp_driver *ubwcp)
  2480. {
  2481. int ret = 0;
  2482. struct device *dev = &pdev->dev;
  2483. ubwcp->irq_range_ck_rd = platform_get_irq(pdev, 0);
  2484. if (ubwcp->irq_range_ck_rd < 0)
  2485. return ubwcp->irq_range_ck_rd;
  2486. ubwcp->irq_range_ck_wr = platform_get_irq(pdev, 1);
  2487. if (ubwcp->irq_range_ck_wr < 0)
  2488. return ubwcp->irq_range_ck_wr;
  2489. ubwcp->irq_encode = platform_get_irq(pdev, 2);
  2490. if (ubwcp->irq_encode < 0)
  2491. return ubwcp->irq_encode;
  2492. ubwcp->irq_decode = platform_get_irq(pdev, 3);
  2493. if (ubwcp->irq_decode < 0)
  2494. return ubwcp->irq_decode;
  2495. DBG("got irqs: %d %d %d %d", ubwcp->irq_range_ck_rd,
  2496. ubwcp->irq_range_ck_wr,
  2497. ubwcp->irq_encode,
  2498. ubwcp->irq_decode);
  2499. ret = devm_request_irq(dev, ubwcp->irq_range_ck_rd, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2500. if (ret) {
  2501. ERR("request_irq() failed. irq: %d ret: %d",
  2502. ubwcp->irq_range_ck_rd, ret);
  2503. return ret;
  2504. }
  2505. ret = devm_request_irq(dev, ubwcp->irq_range_ck_wr, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2506. if (ret) {
  2507. ERR("request_irq() failed. irq: %d ret: %d",
  2508. ubwcp->irq_range_ck_wr, ret);
  2509. return ret;
  2510. }
  2511. ret = devm_request_irq(dev, ubwcp->irq_encode, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2512. if (ret) {
  2513. ERR("request_irq() failed. irq: %d ret: %d",
  2514. ubwcp->irq_encode, ret);
  2515. return ret;
  2516. }
  2517. ret = devm_request_irq(dev, ubwcp->irq_decode, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2518. if (ret) {
  2519. ERR("request_irq() failed. irq: %d ret: %d",
  2520. ubwcp->irq_decode, ret);
  2521. return ret;
  2522. }
  2523. return ret;
  2524. }
  2525. /* ubwcp device probe */
  2526. static int qcom_ubwcp_probe(struct platform_device *pdev)
  2527. {
  2528. int ret = 0;
  2529. struct ubwcp_driver *ubwcp;
  2530. struct device *ubwcp_dev = &pdev->dev;
  2531. ubwcp = devm_kzalloc(ubwcp_dev, sizeof(*ubwcp), GFP_KERNEL);
  2532. if (!ubwcp) {
  2533. ERR("devm_kzalloc() failed");
  2534. return -ENOMEM;
  2535. }
  2536. ubwcp->dev = &pdev->dev;
  2537. ret = dma_set_mask_and_coherent(ubwcp->dev, DMA_BIT_MASK(64));
  2538. ubwcp->base = devm_platform_ioremap_resource(pdev, 0);
  2539. if (IS_ERR(ubwcp->base)) {
  2540. ERR("devm ioremap() failed: %d", PTR_ERR(ubwcp->base));
  2541. return PTR_ERR(ubwcp->base);
  2542. }
  2543. DBG("ubwcp->base: %p", ubwcp->base);
  2544. ret = of_property_read_u64_index(ubwcp_dev->of_node, "ula_range", 0, &ubwcp->ula_pool_base);
  2545. if (ret) {
  2546. ERR("failed reading ula_range (base): %d", ret);
  2547. return ret;
  2548. }
  2549. DBG("ubwcp: ula_range: base = 0x%lx", ubwcp->ula_pool_base);
  2550. ret = of_property_read_u64_index(ubwcp_dev->of_node, "ula_range", 1, &ubwcp->ula_pool_size);
  2551. if (ret) {
  2552. ERR("failed reading ula_range (size): %d", ret);
  2553. return ret;
  2554. }
  2555. DBG("ubwcp: ula_range: size = 0x%lx", ubwcp->ula_pool_size);
  2556. INIT_LIST_HEAD(&ubwcp->err_handler_list);
  2557. /* driver initial state */
  2558. ubwcp->state = UBWCP_STATE_INVALID;
  2559. atomic_set(&ubwcp->num_non_lin_buffers, 0);
  2560. ubwcp->mem_online = false;
  2561. mutex_init(&ubwcp->desc_lock);
  2562. spin_lock_init(&ubwcp->buf_table_lock);
  2563. mutex_init(&ubwcp->mem_hotplug_lock);
  2564. mutex_init(&ubwcp->ula_lock);
  2565. mutex_init(&ubwcp->ubwcp_flush_lock);
  2566. mutex_init(&ubwcp->hw_range_ck_lock);
  2567. spin_lock_init(&ubwcp->err_handler_list_lock);
  2568. /* Regulator */
  2569. ubwcp->vdd = devm_regulator_get(ubwcp_dev, "vdd");
  2570. if (IS_ERR_OR_NULL(ubwcp->vdd)) {
  2571. ret = PTR_ERR(ubwcp->vdd);
  2572. ERR("devm_regulator_get() failed: %d", ret);
  2573. return ret;
  2574. }
  2575. ret = ubwcp_init_clocks(ubwcp, ubwcp_dev);
  2576. if (ret) {
  2577. ERR("failed to initialize ubwcp clocks err: %d", ret);
  2578. return ret;
  2579. }
  2580. if (ubwcp_power(ubwcp, true))
  2581. return -1;
  2582. if (ubwcp_cdev_init(ubwcp))
  2583. return -1;
  2584. /* disable all interrupts (reset value has some interrupts enabled by default) */
  2585. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, false);
  2586. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, false);
  2587. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, false);
  2588. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, false);
  2589. if (ubwcp_interrupt_register(pdev, ubwcp))
  2590. return -1;
  2591. ubwcp_debugfs_init(ubwcp);
  2592. /* create ULA pool */
  2593. ubwcp->ula_pool = gen_pool_create(PAGE_SHIFT, -1);
  2594. if (!ubwcp->ula_pool) {
  2595. ERR("failed gen_pool_create()");
  2596. ret = -1;
  2597. goto err_pool_create;
  2598. }
  2599. ret = gen_pool_add(ubwcp->ula_pool, ubwcp->ula_pool_base, ubwcp->ula_pool_size, -1);
  2600. if (ret) {
  2601. ERR("failed gen_pool_add(): %d", ret);
  2602. ret = -1;
  2603. goto err_pool_add;
  2604. }
  2605. /* register the default config mmap function. */
  2606. ubwcp->mmap_config_fptr = msm_ubwcp_dma_buf_configure_mmap;
  2607. hash_init(ubwcp->buf_table);
  2608. ubwcp_buf_desc_list_init(ubwcp);
  2609. image_format_init(ubwcp);
  2610. /* one time hw init */
  2611. ubwcp_hw_one_time_init(ubwcp->base);
  2612. ubwcp_hw_version(ubwcp->base, &ubwcp->hw_ver_major, &ubwcp->hw_ver_minor);
  2613. pr_err("ubwcp: hw version: major %d, minor %d\n", ubwcp->hw_ver_major, ubwcp->hw_ver_minor);
  2614. if (ubwcp->hw_ver_major == 0) {
  2615. ERR("Failed to read HW version");
  2616. ret = -1;
  2617. goto err_pool_add;
  2618. }
  2619. /* set pdev->dev->driver_data = ubwcp */
  2620. platform_set_drvdata(pdev, ubwcp);
  2621. /* enable interrupts */
  2622. if (ubwcp->read_err_irq_en)
  2623. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, true);
  2624. if (ubwcp->write_err_irq_en)
  2625. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, true);
  2626. if (ubwcp->decode_err_irq_en)
  2627. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, true);
  2628. if (ubwcp->encode_err_irq_en)
  2629. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, true);
  2630. /* Turn OFF until buffers are allocated */
  2631. if (ubwcp_power(ubwcp, false)) {
  2632. ret = -1;
  2633. goto err_power_off;
  2634. }
  2635. ret = msm_ubwcp_set_ops(ubwcp_init_buffer, ubwcp_free_buffer, ubwcp_lock, ubwcp_unlock);
  2636. if (ret) {
  2637. ERR("msm_ubwcp_set_ops() failed: %d", ret);
  2638. goto err_power_off;
  2639. } else {
  2640. DBG("msm_ubwcp_set_ops(): success"); }
  2641. me = ubwcp;
  2642. return ret;
  2643. err_power_off:
  2644. if (!ubwcp_power(ubwcp, true)) {
  2645. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, false);
  2646. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, false);
  2647. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, false);
  2648. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, false);
  2649. ubwcp_power(ubwcp, false);
  2650. }
  2651. err_pool_add:
  2652. gen_pool_destroy(ubwcp->ula_pool);
  2653. err_pool_create:
  2654. ubwcp_debugfs_deinit(ubwcp);
  2655. ubwcp_cdev_deinit(ubwcp);
  2656. return ret;
  2657. }
  2658. /* buffer context bank device probe */
  2659. static int ubwcp_probe_cb_buf(struct platform_device *pdev)
  2660. {
  2661. struct ubwcp_driver *ubwcp;
  2662. struct iommu_domain *domain = NULL;
  2663. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2664. if (!ubwcp) {
  2665. ERR("failed to get ubwcp ptr");
  2666. return -EINVAL;
  2667. }
  2668. ubwcp->dev_buf_cb = &pdev->dev;
  2669. domain = iommu_get_domain_for_dev(ubwcp->dev_buf_cb);
  2670. if (domain)
  2671. iommu_set_fault_handler(domain, ubwcp_iommu_fault_handler, ubwcp->dev_buf_cb);
  2672. if (ubwcp->dev_desc_cb)
  2673. ubwcp->state = UBWCP_STATE_READY;
  2674. return 0;
  2675. }
  2676. /* descriptor context bank device probe */
  2677. static int ubwcp_probe_cb_desc(struct platform_device *pdev)
  2678. {
  2679. int ret = 0;
  2680. struct ubwcp_driver *ubwcp;
  2681. struct iommu_domain *domain = NULL;
  2682. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2683. if (!ubwcp) {
  2684. ERR("failed to get ubwcp ptr");
  2685. return -EINVAL;
  2686. }
  2687. ubwcp->buffer_desc_size = UBWCP_BUFFER_DESC_OFFSET *
  2688. UBWCP_BUFFER_DESC_COUNT;
  2689. ubwcp->dev_desc_cb = &pdev->dev;
  2690. dma_set_max_seg_size(ubwcp->dev_desc_cb, DMA_BIT_MASK(32));
  2691. dma_set_seg_boundary(ubwcp->dev_desc_cb, (unsigned long)DMA_BIT_MASK(64));
  2692. /* Allocate buffer descriptors. UBWCP is iocoherent device.
  2693. * Thus we don't need to flush after updates to buffer descriptors.
  2694. */
  2695. ubwcp->buffer_desc_base = dma_alloc_coherent(ubwcp->dev_desc_cb,
  2696. ubwcp->buffer_desc_size,
  2697. &ubwcp->buffer_desc_dma_handle,
  2698. GFP_KERNEL);
  2699. if (!ubwcp->buffer_desc_base) {
  2700. ERR("failed to allocate desc buffer");
  2701. return -ENOMEM;
  2702. }
  2703. DBG("desc_base = %p size = %zu", ubwcp->buffer_desc_base,
  2704. ubwcp->buffer_desc_size);
  2705. ret = ubwcp_power(ubwcp, true);
  2706. if (ret) {
  2707. ERR("failed to power on");
  2708. goto err;
  2709. }
  2710. ubwcp_hw_set_buf_desc(ubwcp->base, (u64) ubwcp->buffer_desc_dma_handle,
  2711. UBWCP_BUFFER_DESC_OFFSET);
  2712. ret = ubwcp_power(ubwcp, false);
  2713. if (ret) {
  2714. ERR("failed to power off");
  2715. goto err;
  2716. }
  2717. domain = iommu_get_domain_for_dev(ubwcp->dev_desc_cb);
  2718. if (domain)
  2719. iommu_set_fault_handler(domain, ubwcp_iommu_fault_handler, ubwcp->dev_desc_cb);
  2720. if (ubwcp->dev_buf_cb)
  2721. ubwcp->state = UBWCP_STATE_READY;
  2722. return ret;
  2723. err:
  2724. dma_free_coherent(ubwcp->dev_desc_cb,
  2725. ubwcp->buffer_desc_size,
  2726. ubwcp->buffer_desc_base,
  2727. ubwcp->buffer_desc_dma_handle);
  2728. ubwcp->buffer_desc_base = NULL;
  2729. ubwcp->buffer_desc_dma_handle = 0;
  2730. ubwcp->dev_desc_cb = NULL;
  2731. return -1;
  2732. }
  2733. /* buffer context bank device remove */
  2734. static int ubwcp_remove_cb_buf(struct platform_device *pdev)
  2735. {
  2736. struct ubwcp_driver *ubwcp;
  2737. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2738. if (!ubwcp) {
  2739. ERR("failed to get ubwcp ptr");
  2740. return -EINVAL;
  2741. }
  2742. ubwcp->state = UBWCP_STATE_INVALID;
  2743. ubwcp->dev_buf_cb = NULL;
  2744. return 0;
  2745. }
  2746. /* descriptor context bank device remove */
  2747. static int ubwcp_remove_cb_desc(struct platform_device *pdev)
  2748. {
  2749. struct ubwcp_driver *ubwcp;
  2750. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2751. if (!ubwcp) {
  2752. ERR("failed to get ubwcp ptr");
  2753. return -EINVAL;
  2754. }
  2755. if (!ubwcp->dev_desc_cb) {
  2756. ERR("ubwcp->dev_desc_cb == NULL");
  2757. return -1;
  2758. }
  2759. if (!ubwcp_power(ubwcp, true)) {
  2760. ubwcp_hw_set_buf_desc(ubwcp->base, 0x0, 0x0);
  2761. ubwcp_power(ubwcp, false);
  2762. }
  2763. ubwcp->state = UBWCP_STATE_INVALID;
  2764. dma_free_coherent(ubwcp->dev_desc_cb,
  2765. ubwcp->buffer_desc_size,
  2766. ubwcp->buffer_desc_base,
  2767. ubwcp->buffer_desc_dma_handle);
  2768. ubwcp->buffer_desc_base = NULL;
  2769. ubwcp->buffer_desc_dma_handle = 0;
  2770. return 0;
  2771. }
  2772. /* ubwcp device remove */
  2773. static int qcom_ubwcp_remove(struct platform_device *pdev)
  2774. {
  2775. size_t avail;
  2776. size_t psize;
  2777. struct ubwcp_driver *ubwcp;
  2778. /* get pdev->dev->driver_data = ubwcp */
  2779. ubwcp = platform_get_drvdata(pdev);
  2780. if (!ubwcp) {
  2781. ERR("ubwcp == NULL");
  2782. return -1;
  2783. }
  2784. if (!ubwcp_power(ubwcp, true)) {
  2785. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, false);
  2786. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, false);
  2787. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, false);
  2788. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, false);
  2789. ubwcp_power(ubwcp, false);
  2790. }
  2791. ubwcp->state = UBWCP_STATE_INVALID;
  2792. /* before destroying, make sure pool is empty. otherwise pool_destroy() panics. */
  2793. avail = gen_pool_avail(ubwcp->ula_pool);
  2794. psize = gen_pool_size(ubwcp->ula_pool);
  2795. if (psize != avail) {
  2796. ERR("gen_pool is not empty! avail: %zx size: %zx", avail, psize);
  2797. ERR("skipping pool destroy....cause it will PANIC. Fix this!!!!");
  2798. } else {
  2799. gen_pool_destroy(ubwcp->ula_pool);
  2800. }
  2801. ubwcp_debugfs_deinit(ubwcp);
  2802. ubwcp_cdev_deinit(ubwcp);
  2803. return 0;
  2804. }
  2805. /* top level ubwcp device probe function */
  2806. static int ubwcp_probe(struct platform_device *pdev)
  2807. {
  2808. const char *compatible = "";
  2809. trace_ubwcp_probe(pdev);
  2810. if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp"))
  2811. return qcom_ubwcp_probe(pdev);
  2812. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-desc"))
  2813. return ubwcp_probe_cb_desc(pdev);
  2814. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-buf"))
  2815. return ubwcp_probe_cb_buf(pdev);
  2816. of_property_read_string(pdev->dev.of_node, "compatible", &compatible);
  2817. ERR("unknown device: %s", compatible);
  2818. return -EINVAL;
  2819. }
  2820. /* top level ubwcp device remove function */
  2821. static int ubwcp_remove(struct platform_device *pdev)
  2822. {
  2823. const char *compatible = "";
  2824. trace_ubwcp_remove(pdev);
  2825. /* TBD: what if buffers are still allocated? locked? etc.
  2826. * also should turn off power?
  2827. */
  2828. if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp"))
  2829. return qcom_ubwcp_remove(pdev);
  2830. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-desc"))
  2831. return ubwcp_remove_cb_desc(pdev);
  2832. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-buf"))
  2833. return ubwcp_remove_cb_buf(pdev);
  2834. of_property_read_string(pdev->dev.of_node, "compatible", &compatible);
  2835. ERR("unknown device: %s", compatible);
  2836. return -EINVAL;
  2837. }
  2838. static const struct of_device_id ubwcp_dt_match[] = {
  2839. {.compatible = "qcom,ubwcp"},
  2840. {.compatible = "qcom,ubwcp-context-bank-desc"},
  2841. {.compatible = "qcom,ubwcp-context-bank-buf"},
  2842. {}
  2843. };
  2844. struct platform_driver ubwcp_platform_driver = {
  2845. .probe = ubwcp_probe,
  2846. .remove = ubwcp_remove,
  2847. .driver = {
  2848. .name = "qcom,ubwcp",
  2849. .of_match_table = ubwcp_dt_match,
  2850. },
  2851. };
  2852. int ubwcp_init(void)
  2853. {
  2854. int ret = 0;
  2855. DBG("+++++++++++");
  2856. ret = platform_driver_register(&ubwcp_platform_driver);
  2857. if (ret)
  2858. ERR("platform_driver_register() failed: %d", ret);
  2859. return ret;
  2860. }
  2861. void ubwcp_exit(void)
  2862. {
  2863. platform_driver_unregister(&ubwcp_platform_driver);
  2864. DBG("-----------");
  2865. }
  2866. module_init(ubwcp_init);
  2867. module_exit(ubwcp_exit);
  2868. MODULE_LICENSE("GPL");