a0b168f7b3
This change enables display drivers code compilation for lahaina target and current location of header files is replacing the header files in usr/include/drm directory before installing display specific header files. This change ensures both the drm and msm_drv header files are exported to user mode clients. Change-Id: If6fc347598b902e670b7206dbcb82fe0740b3984 Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org> Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org> Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
663 řádky
21 KiB
C
663 řádky
21 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
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/*
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* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef _SDE_DRM_H_
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#define _SDE_DRM_H_
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#include <drm/drm.h>
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/* Total number of supported color planes */
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#define SDE_MAX_PLANES 4
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/* Total number of parameterized detail enhancer mapping curves */
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#define SDE_MAX_DE_CURVES 3
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/* Y/RGB and UV filter configuration */
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#define FILTER_EDGE_DIRECTED_2D 0x0
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#define FILTER_CIRCULAR_2D 0x1
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#define FILTER_SEPARABLE_1D 0x2
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#define FILTER_BILINEAR 0x3
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/* Alpha filters */
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#define FILTER_ALPHA_DROP_REPEAT 0x0
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#define FILTER_ALPHA_BILINEAR 0x1
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#define FILTER_ALPHA_2D 0x3
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/* Blend filters */
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#define FILTER_BLEND_CIRCULAR_2D 0x0
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#define FILTER_BLEND_SEPARABLE_1D 0x1
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/* LUT configuration flags */
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#define SCALER_LUT_SWAP 0x1
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#define SCALER_LUT_DIR_WR 0x2
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#define SCALER_LUT_Y_CIR_WR 0x4
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#define SCALER_LUT_UV_CIR_WR 0x8
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#define SCALER_LUT_Y_SEP_WR 0x10
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#define SCALER_LUT_UV_SEP_WR 0x20
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/**
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* Blend operations for "blend_op" property
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*
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* @SDE_DRM_BLEND_OP_NOT_DEFINED: No blend operation defined for the layer.
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* @SDE_DRM_BLEND_OP_OPAQUE: Apply a constant blend operation. The layer
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* would appear opaque in case fg plane alpha
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* is 0xff.
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* @SDE_DRM_BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already
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* has alpha pre-multiplication done. If the fg
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* plane alpha is less than 0xff, apply
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* modulation as well. This operation is
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* intended on layers having alpha channel.
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* @SDE_DRM_BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not
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* alpha pre-multiplied. Apply
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* pre-multiplication. If fg plane alpha is
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* less than 0xff, apply modulation as well.
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* @SDE_DRM_BLEND_OP_MAX: Used to track maximum blend operation
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* possible by mdp.
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*/
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#define SDE_DRM_BLEND_OP_NOT_DEFINED 0
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#define SDE_DRM_BLEND_OP_OPAQUE 1
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#define SDE_DRM_BLEND_OP_PREMULTIPLIED 2
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#define SDE_DRM_BLEND_OP_COVERAGE 3
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#define SDE_DRM_BLEND_OP_MAX 4
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/**
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* Bit masks for "src_config" property
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* construct bitmask via (1UL << SDE_DRM_<flag>)
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*/
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#define SDE_DRM_DEINTERLACE 0 /* Specifies interlaced input */
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/* DRM bitmasks are restricted to 0..63 */
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#define SDE_DRM_BITMASK_COUNT 64
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/**
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* Framebuffer modes for "fb_translation_mode" PLANE and CONNECTOR property
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*
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* @SDE_DRM_FB_NON_SEC: IOMMU configuration for this framebuffer mode
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* is non-secure domain and requires
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* both stage I and stage II translations when
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* this buffer is accessed by the display HW.
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* This is the default mode of all frambuffers.
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* @SDE_DRM_FB_SEC: IOMMU configuration for this framebuffer mode
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* is secure domain and requires
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* both stage I and stage II translations when
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* this buffer is accessed by the display HW.
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* @SDE_DRM_FB_NON_SEC_DIR_TRANS: IOMMU configuration for this framebuffer mode
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* is non-secure domain and requires
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* only stage II translation when
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* this buffer is accessed by the display HW.
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* @SDE_DRM_FB_SEC_DIR_TRANS: IOMMU configuration for this framebuffer mode
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* is secure domain and requires
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* only stage II translation when
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* this buffer is accessed by the display HW.
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*/
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#define SDE_DRM_FB_NON_SEC 0
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#define SDE_DRM_FB_SEC 1
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#define SDE_DRM_FB_NON_SEC_DIR_TRANS 2
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#define SDE_DRM_FB_SEC_DIR_TRANS 3
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/**
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* Secure levels for "security_level" CRTC property.
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* CRTC property which specifies what plane types
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* can be attached to this CRTC. Plane component
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* derives the plane type based on the FB_MODE.
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* @ SDE_DRM_SEC_NON_SEC: Both Secure and non-secure plane types can be
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* attached to this CRTC. This is the default state of
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* the CRTC.
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* @ SDE_DRM_SEC_ONLY: Only secure planes can be added to this CRTC. If a
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* CRTC is instructed to be in this mode it follows the
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* platform dependent restrictions.
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*/
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#define SDE_DRM_SEC_NON_SEC 0
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#define SDE_DRM_SEC_ONLY 1
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/**
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* struct sde_drm_pix_ext_v1 - version 1 of pixel ext structure
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* @num_ext_pxls_lr: Number of total horizontal pixels
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* @num_ext_pxls_tb: Number of total vertical lines
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* @left_ftch: Number of extra pixels to overfetch from left
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* @right_ftch: Number of extra pixels to overfetch from right
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* @top_ftch: Number of extra lines to overfetch from top
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* @btm_ftch: Number of extra lines to overfetch from bottom
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* @left_rpt: Number of extra pixels to repeat from left
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* @right_rpt: Number of extra pixels to repeat from right
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* @top_rpt: Number of extra lines to repeat from top
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* @btm_rpt: Number of extra lines to repeat from bottom
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*/
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struct sde_drm_pix_ext_v1 {
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/*
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* Number of pixels ext in left, right, top and bottom direction
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* for all color components.
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*/
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int32_t num_ext_pxls_lr[SDE_MAX_PLANES];
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int32_t num_ext_pxls_tb[SDE_MAX_PLANES];
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/*
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* Number of pixels needs to be overfetched in left, right, top
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* and bottom directions from source image for scaling.
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*/
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int32_t left_ftch[SDE_MAX_PLANES];
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int32_t right_ftch[SDE_MAX_PLANES];
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int32_t top_ftch[SDE_MAX_PLANES];
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int32_t btm_ftch[SDE_MAX_PLANES];
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/*
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* Number of pixels needs to be repeated in left, right, top and
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* bottom directions for scaling.
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*/
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int32_t left_rpt[SDE_MAX_PLANES];
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int32_t right_rpt[SDE_MAX_PLANES];
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int32_t top_rpt[SDE_MAX_PLANES];
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int32_t btm_rpt[SDE_MAX_PLANES];
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};
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/**
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* struct sde_drm_scaler_v1 - version 1 of struct sde_drm_scaler
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* @lr: Pixel extension settings for left/right
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* @tb: Pixel extension settings for top/botton
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* @init_phase_x: Initial scaler phase values for x
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* @phase_step_x: Phase step values for x
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* @init_phase_y: Initial scaler phase values for y
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* @phase_step_y: Phase step values for y
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* @horz_filter: Horizontal filter array
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* @vert_filter: Vertical filter array
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*/
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struct sde_drm_scaler_v1 {
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/*
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* Pix ext settings
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*/
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struct sde_drm_pix_ext_v1 pe;
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/*
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* Phase settings
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*/
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int32_t init_phase_x[SDE_MAX_PLANES];
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int32_t phase_step_x[SDE_MAX_PLANES];
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int32_t init_phase_y[SDE_MAX_PLANES];
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int32_t phase_step_y[SDE_MAX_PLANES];
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/*
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* Filter type to be used for scaling in horizontal and vertical
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* directions
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*/
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uint32_t horz_filter[SDE_MAX_PLANES];
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uint32_t vert_filter[SDE_MAX_PLANES];
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};
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/**
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* struct sde_drm_de_v1 - version 1 of detail enhancer structure
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* @enable: Enables/disables detail enhancer
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* @sharpen_level1: Sharpening strength for noise
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* @sharpen_level2: Sharpening strength for context
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* @clip: Clip coefficient
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* @limit: Detail enhancer limit factor
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* @thr_quiet: Quite zone threshold
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* @thr_dieout: Die-out zone threshold
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* @thr_low: Linear zone left threshold
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* @thr_high: Linear zone right threshold
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* @prec_shift: Detail enhancer precision
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* @adjust_a: Mapping curves A coefficients
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* @adjust_b: Mapping curves B coefficients
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* @adjust_c: Mapping curves C coefficients
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*/
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struct sde_drm_de_v1 {
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uint32_t enable;
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int16_t sharpen_level1;
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int16_t sharpen_level2;
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uint16_t clip;
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uint16_t limit;
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uint16_t thr_quiet;
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uint16_t thr_dieout;
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uint16_t thr_low;
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uint16_t thr_high;
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uint16_t prec_shift;
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int16_t adjust_a[SDE_MAX_DE_CURVES];
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int16_t adjust_b[SDE_MAX_DE_CURVES];
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int16_t adjust_c[SDE_MAX_DE_CURVES];
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};
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/*
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* Scaler configuration flags
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*/
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/* Disable dynamic expansion */
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#define SDE_DYN_EXP_DISABLE 0x1
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#define SDE_DRM_QSEED3LITE
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#define SDE_DRM_QSEED4
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#define SDE_DRM_INLINE_PREDOWNSCALE
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/**
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* struct sde_drm_scaler_v2 - version 2 of struct sde_drm_scaler
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* @enable: Scaler enable
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* @dir_en: Detail enhancer enable
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* @pe: Pixel extension settings
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* @horz_decimate: Horizontal decimation factor
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* @vert_decimate: Vertical decimation factor
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* @init_phase_x: Initial scaler phase values for x
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* @phase_step_x: Phase step values for x
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* @init_phase_y: Initial scaler phase values for y
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* @phase_step_y: Phase step values for y
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* @preload_x: Horizontal preload value
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* @preload_y: Vertical preload value
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* @src_width: Source width
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* @src_height: Source height
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* @dst_width: Destination width
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* @dst_height: Destination height
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* @y_rgb_filter_cfg: Y/RGB plane filter configuration
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* @uv_filter_cfg: UV plane filter configuration
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* @alpha_filter_cfg: Alpha filter configuration
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* @blend_cfg: Selection of blend coefficients
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* @lut_flag: LUT configuration flags
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* @dir_lut_idx: 2d 4x4 LUT index
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* @y_rgb_cir_lut_idx: Y/RGB circular LUT index
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* @uv_cir_lut_idx: UV circular LUT index
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* @y_rgb_sep_lut_idx: Y/RGB separable LUT index
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* @uv_sep_lut_idx: UV separable LUT index
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* @de: Detail enhancer settings
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* @dir_weight: Directional Weight
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* @unsharp_mask_blend: Unsharp Blend Filter Ratio
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* @de_blend: Ratio of two unsharp mask filters
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* @flags: Scaler configuration flags
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* @pre_downscale_x_0 Pre-downscale ratio, x-direction, plane 0(Y/RGB)
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* @pre_downscale_x_1 Pre-downscale ratio, x-direction, plane 1(UV)
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* @pre_downscale_y_0 Pre-downscale ratio, y-direction, plane 0(Y/RGB)
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* @pre_downscale_y_1 Pre-downscale ratio, y-direction, plane 1(UV)
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*/
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struct sde_drm_scaler_v2 {
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/*
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* General definitions
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*/
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uint32_t enable;
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uint32_t dir_en;
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/*
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* Pix ext settings
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*/
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struct sde_drm_pix_ext_v1 pe;
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/*
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* Decimation settings
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*/
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uint32_t horz_decimate;
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uint32_t vert_decimate;
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/*
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* Phase settings
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*/
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int32_t init_phase_x[SDE_MAX_PLANES];
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int32_t phase_step_x[SDE_MAX_PLANES];
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int32_t init_phase_y[SDE_MAX_PLANES];
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int32_t phase_step_y[SDE_MAX_PLANES];
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uint32_t preload_x[SDE_MAX_PLANES];
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uint32_t preload_y[SDE_MAX_PLANES];
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uint32_t src_width[SDE_MAX_PLANES];
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uint32_t src_height[SDE_MAX_PLANES];
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uint32_t dst_width;
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uint32_t dst_height;
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uint32_t y_rgb_filter_cfg;
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uint32_t uv_filter_cfg;
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uint32_t alpha_filter_cfg;
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uint32_t blend_cfg;
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uint32_t lut_flag;
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uint32_t dir_lut_idx;
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/* for Y(RGB) and UV planes*/
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uint32_t y_rgb_cir_lut_idx;
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uint32_t uv_cir_lut_idx;
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uint32_t y_rgb_sep_lut_idx;
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uint32_t uv_sep_lut_idx;
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/*
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* Detail enhancer settings
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*/
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struct sde_drm_de_v1 de;
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uint32_t dir_weight;
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uint32_t unsharp_mask_blend;
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uint32_t de_blend;
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uint32_t flags;
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/*
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* Inline pre-downscale settings
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*/
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uint32_t pre_downscale_x_0;
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uint32_t pre_downscale_x_1;
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uint32_t pre_downscale_y_0;
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uint32_t pre_downscale_y_1;
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};
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/* Number of dest scalers supported */
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#define SDE_MAX_DS_COUNT 2
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/*
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* Destination scaler flag config
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*/
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#define SDE_DRM_DESTSCALER_ENABLE 0x1
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#define SDE_DRM_DESTSCALER_SCALE_UPDATE 0x2
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#define SDE_DRM_DESTSCALER_ENHANCER_UPDATE 0x4
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#define SDE_DRM_DESTSCALER_PU_ENABLE 0x8
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/**
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* struct sde_drm_dest_scaler_cfg - destination scaler config structure
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* @flags: Flag to switch between mode for destination scaler
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* refer to destination scaler flag config
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* @index: Destination scaler selection index
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* @lm_width: Layer mixer width configuration
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* @lm_height: Layer mixer height configuration
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* @scaler_cfg: The scaling parameters for all the mode except disable
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* Userspace pointer to struct sde_drm_scaler_v2
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*/
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struct sde_drm_dest_scaler_cfg {
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uint32_t flags;
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uint32_t index;
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uint32_t lm_width;
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uint32_t lm_height;
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uint64_t scaler_cfg;
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};
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/**
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* struct sde_drm_dest_scaler_data - destination scaler data struct
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* @num_dest_scaler: Number of dest scalers to be configured
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* @ds_cfg: Destination scaler block configuration
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*/
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struct sde_drm_dest_scaler_data {
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uint32_t num_dest_scaler;
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struct sde_drm_dest_scaler_cfg ds_cfg[SDE_MAX_DS_COUNT];
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};
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/*
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* Define constants for struct sde_drm_csc
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*/
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#define SDE_CSC_MATRIX_COEFF_SIZE 9
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#define SDE_CSC_CLAMP_SIZE 6
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#define SDE_CSC_BIAS_SIZE 3
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/**
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* struct sde_drm_csc_v1 - version 1 of struct sde_drm_csc
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* @ctm_coeff: Matrix coefficients, in S31.32 format
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* @pre_bias: Pre-bias array values
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* @post_bias: Post-bias array values
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* @pre_clamp: Pre-clamp array values
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* @post_clamp: Post-clamp array values
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*/
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struct sde_drm_csc_v1 {
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int64_t ctm_coeff[SDE_CSC_MATRIX_COEFF_SIZE];
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uint32_t pre_bias[SDE_CSC_BIAS_SIZE];
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uint32_t post_bias[SDE_CSC_BIAS_SIZE];
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uint32_t pre_clamp[SDE_CSC_CLAMP_SIZE];
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uint32_t post_clamp[SDE_CSC_CLAMP_SIZE];
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};
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/**
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* struct sde_drm_color - struct to store the color and alpha values
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* @color_0: Color 0 value
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* @color_1: Color 1 value
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* @color_2: Color 2 value
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* @color_3: Color 3 value
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*/
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struct sde_drm_color {
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uint32_t color_0;
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uint32_t color_1;
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uint32_t color_2;
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uint32_t color_3;
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};
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/* Total number of supported dim layers */
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#define SDE_MAX_DIM_LAYERS 7
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/* SDE_DRM_DIM_LAYER_CONFIG_FLAG - flags for Dim Layer */
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/* Color fill inside of the rect, including border */
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#define SDE_DRM_DIM_LAYER_INCLUSIVE 0x1
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/* Color fill outside of the rect, excluding border */
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#define SDE_DRM_DIM_LAYER_EXCLUSIVE 0x2
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/**
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* struct sde_drm_dim_layer - dim layer cfg struct
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* @flags: Refer SDE_DRM_DIM_LAYER_CONFIG_FLAG for possible values
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* @stage: Blending stage of the dim layer
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* @color_fill: Color fill for dim layer
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* @rect: Dim layer coordinates
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*/
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struct sde_drm_dim_layer_cfg {
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uint32_t flags;
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uint32_t stage;
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struct sde_drm_color color_fill;
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struct drm_clip_rect rect;
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};
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/**
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* struct sde_drm_dim_layer_v1 - version 1 of dim layer struct
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* @num_layers: Numer of Dim Layers
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* @layer: Dim layer user cfgs ptr for the num_layers
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*/
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struct sde_drm_dim_layer_v1 {
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uint32_t num_layers;
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struct sde_drm_dim_layer_cfg layer_cfg[SDE_MAX_DIM_LAYERS];
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};
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/* Writeback Config version definition */
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#define SDE_DRM_WB_CFG 0x1
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/* SDE_DRM_WB_CONFIG_FLAGS - Writeback configuration flags */
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#define SDE_DRM_WB_CFG_FLAGS_CONNECTED (1<<0)
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/**
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* struct sde_drm_wb_cfg - Writeback configuration structure
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* @flags: see DRM_MSM_WB_CONFIG_FLAGS
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* @connector_id: writeback connector identifier
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* @count_modes: Count of modes in modes_ptr
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* @modes: Pointer to struct drm_mode_modeinfo
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|
*/
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struct sde_drm_wb_cfg {
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uint32_t flags;
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uint32_t connector_id;
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uint32_t count_modes;
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uint64_t modes;
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};
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|
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#define SDE_MAX_ROI_V1 4
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|
|
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/**
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|
* struct sde_drm_roi_v1 - list of regions of interest for a drm object
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|
* @num_rects: number of valid rectangles in the roi array
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|
* @roi: list of roi rectangles
|
|
*/
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struct sde_drm_roi_v1 {
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|
uint32_t num_rects;
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struct drm_clip_rect roi[SDE_MAX_ROI_V1];
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|
};
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|
|
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/**
|
|
* Define extended power modes supported by the SDE connectors.
|
|
*/
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|
#define SDE_MODE_DPMS_ON 0
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#define SDE_MODE_DPMS_LP1 1
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#define SDE_MODE_DPMS_LP2 2
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|
#define SDE_MODE_DPMS_STANDBY 3
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|
#define SDE_MODE_DPMS_SUSPEND 4
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|
#define SDE_MODE_DPMS_OFF 5
|
|
|
|
/**
|
|
* sde recovery events for notifying client
|
|
*/
|
|
#define SDE_RECOVERY_SUCCESS 0
|
|
#define SDE_RECOVERY_CAPTURE 1
|
|
#define SDE_RECOVERY_HARD_RESET 2
|
|
|
|
/*
|
|
* Colorimetry Data Block values
|
|
* These bit nums are defined as per the CTA spec
|
|
* and indicate the colorspaces supported by the sink
|
|
*/
|
|
#define DRM_EDID_CLRMETRY_xvYCC_601 (1 << 0)
|
|
#define DRM_EDID_CLRMETRY_xvYCC_709 (1 << 1)
|
|
#define DRM_EDID_CLRMETRY_sYCC_601 (1 << 2)
|
|
#define DRM_EDID_CLRMETRY_ADOBE_YCC_601 (1 << 3)
|
|
#define DRM_EDID_CLRMETRY_ADOBE_RGB (1 << 4)
|
|
#define DRM_EDID_CLRMETRY_BT2020_CYCC (1 << 5)
|
|
#define DRM_EDID_CLRMETRY_BT2020_YCC (1 << 6)
|
|
#define DRM_EDID_CLRMETRY_BT2020_RGB (1 << 7)
|
|
#define DRM_EDID_CLRMETRY_DCI_P3 (1 << 15)
|
|
|
|
/*
|
|
* HDR Metadata
|
|
* These are defined as per EDID spec and shall be used by the sink
|
|
* to set the HDR metadata for playback from userspace.
|
|
*/
|
|
|
|
#define HDR_PRIMARIES_COUNT 3
|
|
|
|
/* HDR EOTF */
|
|
#define HDR_EOTF_SDR_LUM_RANGE 0x0
|
|
#define HDR_EOTF_HDR_LUM_RANGE 0x1
|
|
#define HDR_EOTF_SMTPE_ST2084 0x2
|
|
#define HDR_EOTF_HLG 0x3
|
|
|
|
#define DRM_MSM_EXT_HDR_METADATA
|
|
#define DRM_MSM_EXT_HDR_PLUS_METADATA
|
|
struct drm_msm_ext_hdr_metadata {
|
|
__u32 hdr_state; /* HDR state */
|
|
__u32 eotf; /* electro optical transfer function */
|
|
__u32 hdr_supported; /* HDR supported */
|
|
__u32 display_primaries_x[HDR_PRIMARIES_COUNT]; /* Primaries x */
|
|
__u32 display_primaries_y[HDR_PRIMARIES_COUNT]; /* Primaries y */
|
|
__u32 white_point_x; /* white_point_x */
|
|
__u32 white_point_y; /* white_point_y */
|
|
__u32 max_luminance; /* Max luminance */
|
|
__u32 min_luminance; /* Min Luminance */
|
|
__u32 max_content_light_level; /* max content light level */
|
|
__u32 max_average_light_level; /* max average light level */
|
|
|
|
__u64 hdr_plus_payload; /* user pointer to dynamic HDR payload */
|
|
__u32 hdr_plus_payload_size;/* size of dynamic HDR payload data */
|
|
};
|
|
|
|
/**
|
|
* HDR sink properties
|
|
* These are defined as per EDID spec and shall be used by the userspace
|
|
* to determine the HDR properties to be set to the sink.
|
|
*/
|
|
#define DRM_MSM_EXT_HDR_PROPERTIES
|
|
#define DRM_MSM_EXT_HDR_PLUS_PROPERTIES
|
|
struct drm_msm_ext_hdr_properties {
|
|
__u8 hdr_metadata_type_one; /* static metadata type one */
|
|
__u32 hdr_supported; /* HDR supported */
|
|
__u32 hdr_eotf; /* electro optical transfer function */
|
|
__u32 hdr_max_luminance; /* Max luminance */
|
|
__u32 hdr_avg_luminance; /* Avg luminance */
|
|
__u32 hdr_min_luminance; /* Min Luminance */
|
|
|
|
__u32 hdr_plus_supported; /* HDR10+ supported */
|
|
};
|
|
|
|
/* HDR WRGB x and y index */
|
|
#define DISPLAY_PRIMARIES_WX 0
|
|
#define DISPLAY_PRIMARIES_WY 1
|
|
#define DISPLAY_PRIMARIES_RX 2
|
|
#define DISPLAY_PRIMARIES_RY 3
|
|
#define DISPLAY_PRIMARIES_GX 4
|
|
#define DISPLAY_PRIMARIES_GY 5
|
|
#define DISPLAY_PRIMARIES_BX 6
|
|
#define DISPLAY_PRIMARIES_BY 7
|
|
#define DISPLAY_PRIMARIES_MAX 8
|
|
|
|
struct drm_panel_hdr_properties {
|
|
__u32 hdr_enabled;
|
|
|
|
/* WRGB X and y values arrayed in format */
|
|
/* [WX, WY, RX, RY, GX, GY, BX, BY] */
|
|
__u32 display_primaries[DISPLAY_PRIMARIES_MAX];
|
|
|
|
/* peak brightness supported by panel */
|
|
__u32 peak_brightness;
|
|
/* Blackness level supported by panel */
|
|
__u32 blackness_level;
|
|
};
|
|
|
|
/**
|
|
* struct drm_msm_event_req - Payload to event enable/disable ioctls.
|
|
* @object_id: DRM object id. e.g.: for crtc pass crtc id.
|
|
* @object_type: DRM object type. e.g.: for crtc set it to DRM_MODE_OBJECT_CRTC.
|
|
* @event: Event for which notification is being enabled/disabled.
|
|
* e.g.: for Histogram set - DRM_EVENT_HISTOGRAM.
|
|
* @client_context: Opaque pointer that will be returned during event response
|
|
* notification.
|
|
* @index: Object index(e.g.: crtc index), optional for user-space to set.
|
|
* Driver will override value based on object_id and object_type.
|
|
*/
|
|
struct drm_msm_event_req {
|
|
__u32 object_id;
|
|
__u32 object_type;
|
|
__u32 event;
|
|
__u64 client_context;
|
|
__u32 index;
|
|
};
|
|
|
|
/**
|
|
* struct drm_msm_event_resp - payload returned when read is called for
|
|
* custom notifications.
|
|
* @base: Event type and length of complete notification payload.
|
|
* @info: Contains information about DRM that which raised this event.
|
|
* @data: Custom payload that driver returns for event type.
|
|
* size of data = base.length - (sizeof(base) + sizeof(info))
|
|
*/
|
|
struct drm_msm_event_resp {
|
|
struct drm_event base;
|
|
struct drm_msm_event_req info;
|
|
__u8 data[];
|
|
};
|
|
|
|
/**
|
|
* struct drm_msm_power_ctrl: Payload to enable/disable the power vote
|
|
* @enable: enable/disable the power vote
|
|
* @flags: operation control flags, for future use
|
|
*/
|
|
struct drm_msm_power_ctrl {
|
|
__u32 enable;
|
|
__u32 flags;
|
|
};
|
|
#define DRM_SDE_WB_CONFIG 0x40
|
|
#define DRM_MSM_REGISTER_EVENT 0x41
|
|
#define DRM_MSM_DEREGISTER_EVENT 0x42
|
|
#define DRM_MSM_RMFB2 0x43
|
|
#define DRM_MSM_POWER_CTRL 0x44
|
|
|
|
/* sde custom events */
|
|
#define DRM_EVENT_HISTOGRAM 0x80000000
|
|
#define DRM_EVENT_AD_BACKLIGHT 0x80000001
|
|
#define DRM_EVENT_CRTC_POWER 0x80000002
|
|
#define DRM_EVENT_SYS_BACKLIGHT 0x80000003
|
|
#define DRM_EVENT_SDE_POWER 0x80000004
|
|
#define DRM_EVENT_IDLE_NOTIFY 0x80000005
|
|
#define DRM_EVENT_PANEL_DEAD 0x80000006 /* ESD event */
|
|
#define DRM_EVENT_SDE_HW_RECOVERY 0X80000007
|
|
#define DRM_EVENT_LTM_HIST 0X80000008
|
|
#define DRM_EVENT_LTM_WB_PB 0X80000009
|
|
#define DRM_EVENT_LTM_OFF 0X8000000A
|
|
|
|
#define DRM_IOCTL_SDE_WB_CONFIG \
|
|
DRM_IOW((DRM_COMMAND_BASE + DRM_SDE_WB_CONFIG), struct sde_drm_wb_cfg)
|
|
#define DRM_IOCTL_MSM_REGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + \
|
|
DRM_MSM_REGISTER_EVENT), struct drm_msm_event_req)
|
|
#define DRM_IOCTL_MSM_DEREGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + \
|
|
DRM_MSM_DEREGISTER_EVENT), struct drm_msm_event_req)
|
|
#define DRM_IOCTL_MSM_RMFB2 DRM_IOW((DRM_COMMAND_BASE + \
|
|
DRM_MSM_RMFB2), unsigned int)
|
|
#define DRM_IOCTL_MSM_POWER_CTRL DRM_IOW((DRM_COMMAND_BASE + \
|
|
DRM_MSM_POWER_CTRL), struct drm_msm_power_ctrl)
|
|
|
|
#if defined(__cplusplus)
|
|
}
|
|
#endif
|
|
|
|
#endif /* _SDE_DRM_H_ */
|