dp_main.c 158 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <qdf_net_types.h>
  21. #include <qdf_lro.h>
  22. #include <qdf_module.h>
  23. #include <hal_api.h>
  24. #include <hif.h>
  25. #include <htt.h>
  26. #include <wdi_event.h>
  27. #include <queue.h>
  28. #include "dp_htt.h"
  29. #include "dp_types.h"
  30. #include "dp_internal.h"
  31. #include "dp_tx.h"
  32. #include "dp_tx_desc.h"
  33. #include "dp_rx.h"
  34. #include <cdp_txrx_handle.h>
  35. #include <wlan_cfg.h>
  36. #include "cdp_txrx_cmn_struct.h"
  37. #include <qdf_util.h>
  38. #include "dp_peer.h"
  39. #include "dp_rx_mon.h"
  40. #include "htt_stats.h"
  41. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  42. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  43. #include "cdp_txrx_flow_ctrl_v2.h"
  44. #else
  45. static inline void
  46. cdp_dump_flow_pool_info(struct cdp_soc_t *soc)
  47. {
  48. return;
  49. }
  50. #endif
  51. #include <ol_cfg.h>
  52. #include "dp_ipa.h"
  53. #define DP_INTR_POLL_TIMER_MS 10
  54. #define DP_WDS_AGING_TIMER_DEFAULT_MS 120000
  55. #define DP_MCS_LENGTH (6*MAX_MCS)
  56. #define DP_NSS_LENGTH (6*SS_COUNT)
  57. #define DP_RXDMA_ERR_LENGTH (6*HAL_RXDMA_ERR_MAX)
  58. #define DP_REO_ERR_LENGTH (6*HAL_REO_ERR_MAX)
  59. #define DP_MAX_MCS_STRING_LEN 30
  60. #define DP_CURR_FW_STATS_AVAIL 19
  61. #define DP_HTT_DBG_EXT_STATS_MAX 256
  62. #ifdef IPA_OFFLOAD
  63. /* Exclude IPA rings from the interrupt context */
  64. #define TX_RING_MASK_VAL 0x7
  65. #define RX_RING_MASK_VAL 0x7
  66. #else
  67. #define TX_RING_MASK_VAL 0xF
  68. #define RX_RING_MASK_VAL 0xF
  69. #endif
  70. bool rx_hash = 1;
  71. qdf_declare_param(rx_hash, bool);
  72. #define STR_MAXLEN 64
  73. /**
  74. * default_dscp_tid_map - Default DSCP-TID mapping
  75. *
  76. * DSCP TID AC
  77. * 000000 0 WME_AC_BE
  78. * 001000 1 WME_AC_BK
  79. * 010000 1 WME_AC_BK
  80. * 011000 0 WME_AC_BE
  81. * 100000 5 WME_AC_VI
  82. * 101000 5 WME_AC_VI
  83. * 110000 6 WME_AC_VO
  84. * 111000 6 WME_AC_VO
  85. */
  86. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  87. 0, 0, 0, 0, 0, 0, 0, 0,
  88. 1, 1, 1, 1, 1, 1, 1, 1,
  89. 1, 1, 1, 1, 1, 1, 1, 1,
  90. 0, 0, 0, 0, 0, 0, 0, 0,
  91. 5, 5, 5, 5, 5, 5, 5, 5,
  92. 5, 5, 5, 5, 5, 5, 5, 5,
  93. 6, 6, 6, 6, 6, 6, 6, 6,
  94. 6, 6, 6, 6, 6, 6, 6, 6,
  95. };
  96. /*
  97. * struct dp_rate_debug
  98. *
  99. * @mcs_type: print string for a given mcs
  100. * @valid: valid mcs rate?
  101. */
  102. struct dp_rate_debug {
  103. char mcs_type[DP_MAX_MCS_STRING_LEN];
  104. uint8_t valid;
  105. };
  106. #define MCS_VALID 1
  107. #define MCS_INVALID 0
  108. static const struct dp_rate_debug dp_rate_string[DOT11_MAX][MAX_MCS] = {
  109. {
  110. {"CCK 11 Mbps Long ", MCS_VALID},
  111. {"CCK 5.5 Mbps Long ", MCS_VALID},
  112. {"CCK 2 Mbps Long ", MCS_VALID},
  113. {"CCK 1 Mbps Long ", MCS_VALID},
  114. {"CCK 11 Mbps Short ", MCS_VALID},
  115. {"CCK 5.5 Mbps Short", MCS_VALID},
  116. {"CCK 2 Mbps Short ", MCS_VALID},
  117. {"INVALID ", MCS_INVALID},
  118. {"INVALID ", MCS_INVALID},
  119. {"INVALID ", MCS_INVALID},
  120. {"INVALID ", MCS_INVALID},
  121. {"INVALID ", MCS_INVALID},
  122. {"INVALID ", MCS_VALID},
  123. },
  124. {
  125. {"OFDM 48 Mbps", MCS_VALID},
  126. {"OFDM 24 Mbps", MCS_VALID},
  127. {"OFDM 12 Mbps", MCS_VALID},
  128. {"OFDM 6 Mbps ", MCS_VALID},
  129. {"OFDM 54 Mbps", MCS_VALID},
  130. {"OFDM 36 Mbps", MCS_VALID},
  131. {"OFDM 18 Mbps", MCS_VALID},
  132. {"OFDM 9 Mbps ", MCS_VALID},
  133. {"INVALID ", MCS_INVALID},
  134. {"INVALID ", MCS_INVALID},
  135. {"INVALID ", MCS_INVALID},
  136. {"INVALID ", MCS_INVALID},
  137. {"INVALID ", MCS_VALID},
  138. },
  139. {
  140. {"HT MCS 0 (BPSK 1/2) ", MCS_VALID},
  141. {"HT MCS 1 (QPSK 1/2) ", MCS_VALID},
  142. {"HT MCS 2 (QPSK 3/4) ", MCS_VALID},
  143. {"HT MCS 3 (16-QAM 1/2)", MCS_VALID},
  144. {"HT MCS 4 (16-QAM 3/4)", MCS_VALID},
  145. {"HT MCS 5 (64-QAM 2/3)", MCS_VALID},
  146. {"HT MCS 6 (64-QAM 3/4)", MCS_VALID},
  147. {"HT MCS 7 (64-QAM 5/6)", MCS_VALID},
  148. {"INVALID ", MCS_INVALID},
  149. {"INVALID ", MCS_INVALID},
  150. {"INVALID ", MCS_INVALID},
  151. {"INVALID ", MCS_INVALID},
  152. {"INVALID ", MCS_VALID},
  153. },
  154. {
  155. {"VHT MCS 0 (BPSK 1/2) ", MCS_VALID},
  156. {"VHT MCS 1 (QPSK 1/2) ", MCS_VALID},
  157. {"VHT MCS 2 (QPSK 3/4) ", MCS_VALID},
  158. {"VHT MCS 3 (16-QAM 1/2) ", MCS_VALID},
  159. {"VHT MCS 4 (16-QAM 3/4) ", MCS_VALID},
  160. {"VHT MCS 5 (64-QAM 2/3) ", MCS_VALID},
  161. {"VHT MCS 6 (64-QAM 3/4) ", MCS_VALID},
  162. {"VHT MCS 7 (64-QAM 5/6) ", MCS_VALID},
  163. {"VHT MCS 8 (256-QAM 3/4) ", MCS_VALID},
  164. {"VHT MCS 9 (256-QAM 5/6) ", MCS_VALID},
  165. {"VHT MCS 10 (1024-QAM 3/4)", MCS_VALID},
  166. {"VHT MCS 10 (1024-QAM 5/6)", MCS_VALID},
  167. {"INVALID ", MCS_VALID},
  168. },
  169. {
  170. {"HE MCS 0 (BPSK 1/2) ", MCS_VALID},
  171. {"HE MCS 1 (QPSK 1/2) ", MCS_VALID},
  172. {"HE MCS 2 (QPSK 3/4) ", MCS_VALID},
  173. {"HE MCS 3 (16-QAM 1/2) ", MCS_VALID},
  174. {"HE MCS 4 (16-QAM 3/4) ", MCS_VALID},
  175. {"HE MCS 5 (64-QAM 2/3) ", MCS_VALID},
  176. {"HE MCS 6 (64-QAM 3/4) ", MCS_VALID},
  177. {"HE MCS 7 (64-QAM 5/6) ", MCS_VALID},
  178. {"HE MCS 8 (256-QAM 3/4) ", MCS_VALID},
  179. {"HE MCS 9 (256-QAM 5/6) ", MCS_VALID},
  180. {"HE MCS 10 (1024-QAM 3/4)", MCS_VALID},
  181. {"HE MCS 10 (1024-QAM 5/6)", MCS_VALID},
  182. {"INVALID ", MCS_VALID},
  183. }
  184. };
  185. /**
  186. * @brief Cpu ring map types
  187. */
  188. enum dp_cpu_ring_map_types {
  189. DP_DEFAULT_MAP,
  190. DP_NSS_FIRST_RADIO_OFFLOADED_MAP,
  191. DP_NSS_SECOND_RADIO_OFFLOADED_MAP,
  192. DP_NSS_ALL_RADIO_OFFLOADED_MAP,
  193. DP_CPU_RING_MAP_MAX
  194. };
  195. /**
  196. * @brief Cpu to tx ring map
  197. */
  198. static uint8_t dp_cpu_ring_map[DP_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS] = {
  199. {0x0, 0x1, 0x2, 0x0},
  200. {0x1, 0x2, 0x1, 0x2},
  201. {0x0, 0x2, 0x0, 0x2},
  202. {0x2, 0x2, 0x2, 0x2}
  203. };
  204. /**
  205. * @brief Select the type of statistics
  206. */
  207. enum dp_stats_type {
  208. STATS_FW = 0,
  209. STATS_HOST = 1,
  210. STATS_TYPE_MAX = 2,
  211. };
  212. /**
  213. * @brief General Firmware statistics options
  214. *
  215. */
  216. enum dp_fw_stats {
  217. TXRX_FW_STATS_INVALID = -1,
  218. };
  219. /**
  220. * dp_stats_mapping_table - Firmware and Host statistics
  221. * currently supported
  222. */
  223. const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
  224. {HTT_DBG_EXT_STATS_RESET, TXRX_HOST_STATS_INVALID},
  225. {HTT_DBG_EXT_STATS_PDEV_TX, TXRX_HOST_STATS_INVALID},
  226. {HTT_DBG_EXT_STATS_PDEV_RX, TXRX_HOST_STATS_INVALID},
  227. {HTT_DBG_EXT_STATS_PDEV_TX_HWQ, TXRX_HOST_STATS_INVALID},
  228. {HTT_DBG_EXT_STATS_PDEV_TX_SCHED, TXRX_HOST_STATS_INVALID},
  229. {HTT_DBG_EXT_STATS_PDEV_ERROR, TXRX_HOST_STATS_INVALID},
  230. {HTT_DBG_EXT_STATS_PDEV_TQM, TXRX_HOST_STATS_INVALID},
  231. {HTT_DBG_EXT_STATS_TQM_CMDQ, TXRX_HOST_STATS_INVALID},
  232. {HTT_DBG_EXT_STATS_TX_DE_INFO, TXRX_HOST_STATS_INVALID},
  233. {HTT_DBG_EXT_STATS_PDEV_TX_RATE, TXRX_HOST_STATS_INVALID},
  234. {HTT_DBG_EXT_STATS_PDEV_RX_RATE, TXRX_HOST_STATS_INVALID},
  235. {TXRX_FW_STATS_INVALID, TXRX_HOST_STATS_INVALID},
  236. {HTT_DBG_EXT_STATS_TX_SELFGEN_INFO, TXRX_HOST_STATS_INVALID},
  237. {HTT_DBG_EXT_STATS_TX_MU_HWQ, TXRX_HOST_STATS_INVALID},
  238. {HTT_DBG_EXT_STATS_RING_IF_INFO, TXRX_HOST_STATS_INVALID},
  239. {HTT_DBG_EXT_STATS_SRNG_INFO, TXRX_HOST_STATS_INVALID},
  240. {HTT_DBG_EXT_STATS_SFM_INFO, TXRX_HOST_STATS_INVALID},
  241. {HTT_DBG_EXT_STATS_PDEV_TX_MU, TXRX_HOST_STATS_INVALID},
  242. {HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST, TXRX_HOST_STATS_INVALID},
  243. /* Last ENUM for HTT FW STATS */
  244. {DP_HTT_DBG_EXT_STATS_MAX, TXRX_HOST_STATS_INVALID},
  245. {TXRX_FW_STATS_INVALID, TXRX_CLEAR_STATS},
  246. {TXRX_FW_STATS_INVALID, TXRX_RX_RATE_STATS},
  247. {TXRX_FW_STATS_INVALID, TXRX_TX_RATE_STATS},
  248. {TXRX_FW_STATS_INVALID, TXRX_TX_HOST_STATS},
  249. {TXRX_FW_STATS_INVALID, TXRX_RX_HOST_STATS},
  250. {TXRX_FW_STATS_INVALID, TXRX_AST_STATS},
  251. {TXRX_FW_STATS_INVALID, TXRX_SRNG_PTR_STATS},
  252. };
  253. /**
  254. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  255. * @ring_num: ring num of the ring being queried
  256. * @grp_mask: the grp_mask array for the ring type in question.
  257. *
  258. * The grp_mask array is indexed by group number and the bit fields correspond
  259. * to ring numbers. We are finding which interrupt group a ring belongs to.
  260. *
  261. * Return: the index in the grp_mask array with the ring number.
  262. * -QDF_STATUS_E_NOENT if no entry is found
  263. */
  264. static int dp_srng_find_ring_in_mask(int ring_num, int *grp_mask)
  265. {
  266. int ext_group_num;
  267. int mask = 1 << ring_num;
  268. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  269. ext_group_num++) {
  270. if (mask & grp_mask[ext_group_num])
  271. return ext_group_num;
  272. }
  273. return -QDF_STATUS_E_NOENT;
  274. }
  275. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  276. enum hal_ring_type ring_type,
  277. int ring_num)
  278. {
  279. int *grp_mask;
  280. switch (ring_type) {
  281. case WBM2SW_RELEASE:
  282. /* dp_tx_comp_handler - soc->tx_comp_ring */
  283. if (ring_num < 3)
  284. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  285. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  286. else if (ring_num == 3) {
  287. /* sw treats this as a separate ring type */
  288. grp_mask = &soc->wlan_cfg_ctx->
  289. int_rx_wbm_rel_ring_mask[0];
  290. ring_num = 0;
  291. } else {
  292. qdf_assert(0);
  293. return -QDF_STATUS_E_NOENT;
  294. }
  295. break;
  296. case REO_EXCEPTION:
  297. /* dp_rx_err_process - &soc->reo_exception_ring */
  298. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  299. break;
  300. case REO_DST:
  301. /* dp_rx_process - soc->reo_dest_ring */
  302. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  303. break;
  304. case REO_STATUS:
  305. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  306. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  307. break;
  308. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  309. case RXDMA_MONITOR_STATUS:
  310. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  311. case RXDMA_MONITOR_DST:
  312. /* dp_mon_process */
  313. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  314. break;
  315. case RXDMA_DST:
  316. /* dp_rxdma_err_process */
  317. grp_mask = &soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[0];
  318. break;
  319. case RXDMA_MONITOR_BUF:
  320. case RXDMA_BUF:
  321. /* TODO: support low_thresh interrupt */
  322. return -QDF_STATUS_E_NOENT;
  323. break;
  324. case TCL_DATA:
  325. case TCL_CMD:
  326. case REO_CMD:
  327. case SW2WBM_RELEASE:
  328. case WBM_IDLE_LINK:
  329. /* normally empty SW_TO_HW rings */
  330. return -QDF_STATUS_E_NOENT;
  331. break;
  332. case TCL_STATUS:
  333. case REO_REINJECT:
  334. /* misc unused rings */
  335. return -QDF_STATUS_E_NOENT;
  336. break;
  337. case CE_SRC:
  338. case CE_DST:
  339. case CE_DST_STATUS:
  340. /* CE_rings - currently handled by hif */
  341. default:
  342. return -QDF_STATUS_E_NOENT;
  343. break;
  344. }
  345. return dp_srng_find_ring_in_mask(ring_num, grp_mask);
  346. }
  347. static void dp_srng_msi_setup(struct dp_soc *soc, struct hal_srng_params
  348. *ring_params, int ring_type, int ring_num)
  349. {
  350. int msi_group_number;
  351. int msi_data_count;
  352. int ret;
  353. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  354. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  355. &msi_data_count, &msi_data_start,
  356. &msi_irq_start);
  357. if (ret)
  358. return;
  359. msi_group_number = dp_srng_calculate_msi_group(soc, ring_type,
  360. ring_num);
  361. if (msi_group_number < 0) {
  362. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  363. FL("ring not part of an ext_group; ring_type: %d,ring_num %d"),
  364. ring_type, ring_num);
  365. ring_params->msi_addr = 0;
  366. ring_params->msi_data = 0;
  367. return;
  368. }
  369. if (msi_group_number > msi_data_count) {
  370. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  371. FL("2 msi_groups will share an msi; msi_group_num %d"),
  372. msi_group_number);
  373. QDF_ASSERT(0);
  374. }
  375. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  376. ring_params->msi_addr = addr_low;
  377. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  378. ring_params->msi_data = (msi_group_number % msi_data_count)
  379. + msi_data_start;
  380. ring_params->flags |= HAL_SRNG_MSI_INTR;
  381. }
  382. /**
  383. * dp_print_ast_stats() - Dump AST table contents
  384. * @soc: Datapath soc handle
  385. *
  386. * return void
  387. */
  388. #ifdef FEATURE_WDS
  389. static void dp_print_ast_stats(struct dp_soc *soc)
  390. {
  391. uint8_t i;
  392. uint8_t num_entries = 0;
  393. struct dp_vdev *vdev;
  394. struct dp_pdev *pdev;
  395. struct dp_peer *peer;
  396. struct dp_ast_entry *ase, *tmp_ase;
  397. DP_PRINT_STATS("AST Stats:");
  398. DP_PRINT_STATS(" Entries Added = %d", soc->stats.ast.added);
  399. DP_PRINT_STATS(" Entries Deleted = %d", soc->stats.ast.deleted);
  400. DP_PRINT_STATS(" Entries Agedout = %d", soc->stats.ast.aged_out);
  401. DP_PRINT_STATS("AST Table:");
  402. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  403. pdev = soc->pdev_list[i];
  404. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  405. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  406. DP_PEER_ITERATE_ASE_LIST(peer, ase, tmp_ase) {
  407. DP_PRINT_STATS("%6d mac_addr = %pM"
  408. " peer_mac_addr = %pM"
  409. " type = %d"
  410. " next_hop = %d"
  411. " is_active = %d"
  412. " is_bss = %d",
  413. ++num_entries,
  414. ase->mac_addr.raw,
  415. ase->peer->mac_addr.raw,
  416. ase->type,
  417. ase->next_hop,
  418. ase->is_active,
  419. ase->is_bss);
  420. }
  421. }
  422. }
  423. }
  424. }
  425. #else
  426. static void dp_print_ast_stats(struct dp_soc *soc)
  427. {
  428. DP_PRINT_STATS("AST Stats not available.Enable FEATURE_WDS");
  429. return;
  430. }
  431. #endif
  432. /*
  433. * dp_setup_srng - Internal function to setup SRNG rings used by data path
  434. */
  435. static int dp_srng_setup(struct dp_soc *soc, struct dp_srng *srng,
  436. int ring_type, int ring_num, int mac_id, uint32_t num_entries)
  437. {
  438. void *hal_soc = soc->hal_soc;
  439. uint32_t entry_size = hal_srng_get_entrysize(hal_soc, ring_type);
  440. /* TODO: See if we should get align size from hal */
  441. uint32_t ring_base_align = 8;
  442. struct hal_srng_params ring_params;
  443. uint32_t max_entries = hal_srng_max_entries(hal_soc, ring_type);
  444. /* TODO: Currently hal layer takes care of endianness related settings.
  445. * See if these settings need to passed from DP layer
  446. */
  447. ring_params.flags = 0;
  448. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  449. FL("Ring type: %d, num:%d"), ring_type, ring_num);
  450. num_entries = (num_entries > max_entries) ? max_entries : num_entries;
  451. srng->hal_srng = NULL;
  452. srng->alloc_size = (num_entries * entry_size) + ring_base_align - 1;
  453. srng->base_vaddr_unaligned = qdf_mem_alloc_consistent(
  454. soc->osdev, soc->osdev->dev, srng->alloc_size,
  455. &(srng->base_paddr_unaligned));
  456. if (!srng->base_vaddr_unaligned) {
  457. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  458. FL("alloc failed - ring_type: %d, ring_num %d"),
  459. ring_type, ring_num);
  460. return QDF_STATUS_E_NOMEM;
  461. }
  462. ring_params.ring_base_vaddr = srng->base_vaddr_unaligned +
  463. ((unsigned long)srng->base_vaddr_unaligned % ring_base_align);
  464. ring_params.ring_base_paddr = srng->base_paddr_unaligned +
  465. ((unsigned long)(ring_params.ring_base_vaddr) -
  466. (unsigned long)srng->base_vaddr_unaligned);
  467. ring_params.num_entries = num_entries;
  468. if (soc->intr_mode == DP_INTR_MSI) {
  469. dp_srng_msi_setup(soc, &ring_params, ring_type, ring_num);
  470. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  471. FL("Using MSI for ring_type: %d, ring_num %d"),
  472. ring_type, ring_num);
  473. } else {
  474. ring_params.msi_data = 0;
  475. ring_params.msi_addr = 0;
  476. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  477. FL("Skipping MSI for ring_type: %d, ring_num %d"),
  478. ring_type, ring_num);
  479. }
  480. /*
  481. * Setup interrupt timer and batch counter thresholds for
  482. * interrupt mitigation based on ring type
  483. */
  484. if (ring_type == REO_DST) {
  485. ring_params.intr_timer_thres_us =
  486. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  487. ring_params.intr_batch_cntr_thres_entries =
  488. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  489. } else if (ring_type == WBM2SW_RELEASE && (ring_num < 3)) {
  490. ring_params.intr_timer_thres_us =
  491. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  492. ring_params.intr_batch_cntr_thres_entries =
  493. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  494. } else {
  495. ring_params.intr_timer_thres_us =
  496. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  497. ring_params.intr_batch_cntr_thres_entries =
  498. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  499. }
  500. /* Enable low threshold interrupts for rx buffer rings (regular and
  501. * monitor buffer rings.
  502. * TODO: See if this is required for any other ring
  503. */
  504. if ((ring_type == RXDMA_BUF) || (ring_type == RXDMA_MONITOR_BUF)) {
  505. /* TODO: Setting low threshold to 1/8th of ring size
  506. * see if this needs to be configurable
  507. */
  508. ring_params.low_threshold = num_entries >> 3;
  509. ring_params.flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  510. ring_params.intr_timer_thres_us = 0x1000;
  511. }
  512. srng->hal_srng = hal_srng_setup(hal_soc, ring_type, ring_num,
  513. mac_id, &ring_params);
  514. return 0;
  515. }
  516. /**
  517. * dp_srng_cleanup - Internal function to cleanup SRNG rings used by data path
  518. * Any buffers allocated and attached to ring entries are expected to be freed
  519. * before calling this function.
  520. */
  521. static void dp_srng_cleanup(struct dp_soc *soc, struct dp_srng *srng,
  522. int ring_type, int ring_num)
  523. {
  524. if (!srng->hal_srng) {
  525. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  526. FL("Ring type: %d, num:%d not setup"),
  527. ring_type, ring_num);
  528. return;
  529. }
  530. hal_srng_cleanup(soc->hal_soc, srng->hal_srng);
  531. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  532. srng->alloc_size,
  533. srng->base_vaddr_unaligned,
  534. srng->base_paddr_unaligned, 0);
  535. srng->hal_srng = NULL;
  536. }
  537. #ifdef IPA_OFFLOAD
  538. /**
  539. * dp_tx_ipa_uc_detach - Free autonomy TX resources
  540. * @soc: data path instance
  541. * @pdev: core txrx pdev context
  542. *
  543. * Free allocated TX buffers with WBM SRNG
  544. *
  545. * Return: none
  546. */
  547. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  548. {
  549. int idx;
  550. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  551. if (soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx])
  552. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx]);
  553. }
  554. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  555. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = NULL;
  556. }
  557. /**
  558. * dp_rx_ipa_uc_detach - free autonomy RX resources
  559. * @soc: data path instance
  560. * @pdev: core txrx pdev context
  561. *
  562. * This function will detach DP RX into main device context
  563. * will free DP Rx resources.
  564. *
  565. * Return: none
  566. */
  567. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  568. {
  569. }
  570. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  571. {
  572. /* TX resource detach */
  573. dp_tx_ipa_uc_detach(soc, pdev);
  574. /* RX resource detach */
  575. dp_rx_ipa_uc_detach(soc, pdev);
  576. dp_srng_cleanup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2);
  577. return QDF_STATUS_SUCCESS; /* success */
  578. }
  579. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  580. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  581. /**
  582. * dp_tx_ipa_uc_attach - Allocate autonomy TX resources
  583. * @soc: data path instance
  584. * @pdev: Physical device handle
  585. *
  586. * Allocate TX buffer from non-cacheable memory
  587. * Attache allocated TX buffers with WBM SRNG
  588. *
  589. * Return: int
  590. */
  591. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  592. {
  593. uint32_t tx_buffer_count;
  594. uint32_t ring_base_align = 8;
  595. void *buffer_vaddr_unaligned;
  596. void *buffer_vaddr;
  597. qdf_dma_addr_t buffer_paddr_unaligned;
  598. qdf_dma_addr_t buffer_paddr;
  599. void *wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  600. uint32_t paddr_lo;
  601. uint32_t paddr_hi;
  602. void *ring_entry;
  603. int ring_size = ((struct hal_srng *)wbm_srng)->ring_size;
  604. int retval = QDF_STATUS_SUCCESS;
  605. /*
  606. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  607. * unsigned int uc_tx_buf_sz =
  608. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  609. */
  610. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  611. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  612. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  613. "requested %d buffers to be posted to wbm ring",
  614. ring_size);
  615. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = qdf_mem_malloc(ring_size *
  616. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr));
  617. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr) {
  618. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  619. "%s: IPA WBM Ring mem_info alloc fail", __func__);
  620. return -ENOMEM;
  621. }
  622. hal_srng_access_start(soc->hal_soc, wbm_srng);
  623. /* Allocate TX buffers as many as possible */
  624. for (tx_buffer_count = 0;
  625. tx_buffer_count < ring_size; tx_buffer_count++) {
  626. ring_entry = hal_srng_src_get_next(soc->hal_soc, wbm_srng);
  627. if (!ring_entry) {
  628. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  629. "Failed to get WBM ring entry\n");
  630. goto fail;
  631. }
  632. buffer_vaddr_unaligned = qdf_mem_alloc_consistent(soc->osdev,
  633. soc->osdev->dev, alloc_size, &buffer_paddr_unaligned);
  634. if (!buffer_vaddr_unaligned) {
  635. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  636. "IPA WDI TX buffer alloc fail %d allocated\n",
  637. tx_buffer_count);
  638. break;
  639. }
  640. buffer_vaddr = buffer_vaddr_unaligned +
  641. ((unsigned long)buffer_vaddr_unaligned %
  642. ring_base_align);
  643. buffer_paddr = buffer_paddr_unaligned +
  644. ((unsigned long)(buffer_vaddr) -
  645. (unsigned long)buffer_vaddr_unaligned);
  646. paddr_lo = ((u64)buffer_paddr & 0x00000000ffffffff);
  647. paddr_hi = ((u64)buffer_paddr & 0x0000001f00000000) >> 32;
  648. HAL_WBM_PADDR_LO_SET(ring_entry, paddr_lo);
  649. HAL_WBM_PADDR_HI_SET(ring_entry, paddr_hi);
  650. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[tx_buffer_count] =
  651. buffer_vaddr;
  652. }
  653. hal_srng_access_end(soc->hal_soc, wbm_srng);
  654. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  655. return retval;
  656. fail:
  657. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  658. return retval;
  659. }
  660. /**
  661. * dp_rx_ipa_uc_attach - Allocate autonomy RX resources
  662. * @soc: data path instance
  663. * @pdev: core txrx pdev context
  664. *
  665. * This function will attach a DP RX instance into the main
  666. * device (SOC) context.
  667. *
  668. * Return: QDF_STATUS_SUCCESS: success
  669. * QDF_STATUS_E_RESOURCES: Error return
  670. */
  671. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  672. {
  673. return QDF_STATUS_SUCCESS;
  674. }
  675. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  676. {
  677. int error;
  678. /* TX resource attach */
  679. error = dp_tx_ipa_uc_attach(soc, pdev);
  680. if (error) {
  681. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  682. "DP IPA UC TX attach fail code %d\n", error);
  683. return error;
  684. }
  685. /* RX resource attach */
  686. error = dp_rx_ipa_uc_attach(soc, pdev);
  687. if (error) {
  688. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  689. "DP IPA UC RX attach fail code %d\n", error);
  690. dp_tx_ipa_uc_detach(soc, pdev);
  691. return error;
  692. }
  693. return QDF_STATUS_SUCCESS; /* success */
  694. }
  695. #else
  696. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  697. {
  698. return QDF_STATUS_SUCCESS;
  699. }
  700. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  701. {
  702. return QDF_STATUS_SUCCESS;
  703. }
  704. #endif
  705. /* TODO: Need this interface from HIF */
  706. void *hif_get_hal_handle(void *hif_handle);
  707. /*
  708. * dp_service_srngs() - Top level interrupt handler for DP Ring interrupts
  709. * @dp_ctx: DP SOC handle
  710. * @budget: Number of frames/descriptors that can be processed in one shot
  711. *
  712. * Return: remaining budget/quota for the soc device
  713. */
  714. static uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget)
  715. {
  716. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  717. struct dp_soc *soc = int_ctx->soc;
  718. int ring = 0;
  719. uint32_t work_done = 0;
  720. int budget = dp_budget;
  721. uint8_t tx_mask = int_ctx->tx_ring_mask;
  722. uint8_t rx_mask = int_ctx->rx_ring_mask;
  723. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  724. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  725. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  726. uint32_t remaining_quota = dp_budget;
  727. /* Process Tx completion interrupts first to return back buffers */
  728. while (tx_mask) {
  729. if (tx_mask & 0x1) {
  730. work_done = dp_tx_comp_handler(soc,
  731. soc->tx_comp_ring[ring].hal_srng,
  732. remaining_quota);
  733. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  734. "tx mask 0x%x ring %d, budget %d, work_done %d",
  735. tx_mask, ring, budget, work_done);
  736. budget -= work_done;
  737. if (budget <= 0)
  738. goto budget_done;
  739. remaining_quota = budget;
  740. }
  741. tx_mask = tx_mask >> 1;
  742. ring++;
  743. }
  744. /* Process REO Exception ring interrupt */
  745. if (rx_err_mask) {
  746. work_done = dp_rx_err_process(soc,
  747. soc->reo_exception_ring.hal_srng,
  748. remaining_quota);
  749. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  750. "REO Exception Ring: work_done %d budget %d",
  751. work_done, budget);
  752. budget -= work_done;
  753. if (budget <= 0) {
  754. goto budget_done;
  755. }
  756. remaining_quota = budget;
  757. }
  758. /* Process Rx WBM release ring interrupt */
  759. if (rx_wbm_rel_mask) {
  760. work_done = dp_rx_wbm_err_process(soc,
  761. soc->rx_rel_ring.hal_srng, remaining_quota);
  762. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  763. "WBM Release Ring: work_done %d budget %d",
  764. work_done, budget);
  765. budget -= work_done;
  766. if (budget <= 0) {
  767. goto budget_done;
  768. }
  769. remaining_quota = budget;
  770. }
  771. /* Process Rx interrupts */
  772. if (rx_mask) {
  773. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  774. if (rx_mask & (1 << ring)) {
  775. work_done = dp_rx_process(int_ctx,
  776. soc->reo_dest_ring[ring].hal_srng,
  777. remaining_quota);
  778. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  779. "rx mask 0x%x ring %d, work_done %d budget %d",
  780. rx_mask, ring, work_done, budget);
  781. budget -= work_done;
  782. if (budget <= 0)
  783. goto budget_done;
  784. remaining_quota = budget;
  785. }
  786. }
  787. }
  788. if (reo_status_mask)
  789. dp_reo_status_ring_handler(soc);
  790. /* Process LMAC interrupts */
  791. for (ring = 0 ; ring < MAX_PDEV_CNT; ring++) {
  792. if (soc->pdev_list[ring] == NULL)
  793. continue;
  794. if (int_ctx->rx_mon_ring_mask & (1 << ring)) {
  795. work_done = dp_mon_process(soc, ring, remaining_quota);
  796. budget -= work_done;
  797. remaining_quota = budget;
  798. }
  799. if (int_ctx->rxdma2host_ring_mask & (1 << ring)) {
  800. work_done = dp_rxdma_err_process(soc, ring,
  801. remaining_quota);
  802. budget -= work_done;
  803. }
  804. }
  805. qdf_lro_flush(int_ctx->lro_ctx);
  806. budget_done:
  807. return dp_budget - budget;
  808. }
  809. #ifdef DP_INTR_POLL_BASED
  810. /* dp_interrupt_timer()- timer poll for interrupts
  811. *
  812. * @arg: SoC Handle
  813. *
  814. * Return:
  815. *
  816. */
  817. static void dp_interrupt_timer(void *arg)
  818. {
  819. struct dp_soc *soc = (struct dp_soc *) arg;
  820. int i;
  821. if (qdf_atomic_read(&soc->cmn_init_done)) {
  822. for (i = 0;
  823. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  824. dp_service_srngs(&soc->intr_ctx[i], 0xffff);
  825. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  826. }
  827. }
  828. /*
  829. * dp_soc_interrupt_attach_poll() - Register handlers for DP interrupts
  830. * @txrx_soc: DP SOC handle
  831. *
  832. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  833. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  834. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  835. *
  836. * Return: 0 for success. nonzero for failure.
  837. */
  838. static QDF_STATUS dp_soc_interrupt_attach_poll(void *txrx_soc)
  839. {
  840. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  841. int i;
  842. soc->intr_mode = DP_INTR_POLL;
  843. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  844. soc->intr_ctx[i].dp_intr_id = i;
  845. soc->intr_ctx[i].tx_ring_mask = TX_RING_MASK_VAL;
  846. soc->intr_ctx[i].rx_ring_mask = RX_RING_MASK_VAL;
  847. soc->intr_ctx[i].rx_mon_ring_mask = 0x1;
  848. soc->intr_ctx[i].rx_err_ring_mask = 0x1;
  849. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0x1;
  850. soc->intr_ctx[i].reo_status_ring_mask = 0x1;
  851. soc->intr_ctx[i].rxdma2host_ring_mask = 0x1;
  852. soc->intr_ctx[i].soc = soc;
  853. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  854. }
  855. qdf_timer_init(soc->osdev, &soc->int_timer,
  856. dp_interrupt_timer, (void *)soc,
  857. QDF_TIMER_TYPE_WAKE_APPS);
  858. return QDF_STATUS_SUCCESS;
  859. }
  860. #ifdef CONFIG_MCL
  861. extern int con_mode_monitor;
  862. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc);
  863. /*
  864. * dp_soc_interrupt_attach_wrapper() - Register handlers for DP interrupts
  865. * @txrx_soc: DP SOC handle
  866. *
  867. * Call the appropriate attach function based on the mode of operation.
  868. * This is a WAR for enabling monitor mode.
  869. *
  870. * Return: 0 for success. nonzero for failure.
  871. */
  872. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  873. {
  874. if (con_mode_monitor == QDF_GLOBAL_MONITOR_MODE) {
  875. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  876. FL("Attach interrupts in Poll mode"));
  877. return dp_soc_interrupt_attach_poll(txrx_soc);
  878. } else {
  879. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  880. FL("Attach interrupts in MSI mode"));
  881. return dp_soc_interrupt_attach(txrx_soc);
  882. }
  883. }
  884. #else
  885. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  886. {
  887. return dp_soc_interrupt_attach_poll(txrx_soc);
  888. }
  889. #endif
  890. #endif
  891. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  892. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  893. {
  894. int j;
  895. int num_irq = 0;
  896. int tx_mask =
  897. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  898. int rx_mask =
  899. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  900. int rx_mon_mask =
  901. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  902. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  903. soc->wlan_cfg_ctx, intr_ctx_num);
  904. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  905. soc->wlan_cfg_ctx, intr_ctx_num);
  906. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  907. soc->wlan_cfg_ctx, intr_ctx_num);
  908. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  909. soc->wlan_cfg_ctx, intr_ctx_num);
  910. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  911. if (tx_mask & (1 << j)) {
  912. irq_id_map[num_irq++] =
  913. (wbm2host_tx_completions_ring1 - j);
  914. }
  915. if (rx_mask & (1 << j)) {
  916. irq_id_map[num_irq++] =
  917. (reo2host_destination_ring1 - j);
  918. }
  919. if (rxdma2host_ring_mask & (1 << j)) {
  920. irq_id_map[num_irq++] =
  921. rxdma2host_destination_ring_mac1 -
  922. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  923. }
  924. if (rx_mon_mask & (1 << j)) {
  925. irq_id_map[num_irq++] =
  926. ppdu_end_interrupts_mac1 -
  927. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  928. }
  929. if (rx_wbm_rel_ring_mask & (1 << j))
  930. irq_id_map[num_irq++] = wbm2host_rx_release;
  931. if (rx_err_ring_mask & (1 << j))
  932. irq_id_map[num_irq++] = reo2host_exception;
  933. if (reo_status_ring_mask & (1 << j))
  934. irq_id_map[num_irq++] = reo2host_status;
  935. }
  936. *num_irq_r = num_irq;
  937. }
  938. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  939. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  940. int msi_vector_count, int msi_vector_start)
  941. {
  942. int tx_mask = wlan_cfg_get_tx_ring_mask(
  943. soc->wlan_cfg_ctx, intr_ctx_num);
  944. int rx_mask = wlan_cfg_get_rx_ring_mask(
  945. soc->wlan_cfg_ctx, intr_ctx_num);
  946. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  947. soc->wlan_cfg_ctx, intr_ctx_num);
  948. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  949. soc->wlan_cfg_ctx, intr_ctx_num);
  950. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  951. soc->wlan_cfg_ctx, intr_ctx_num);
  952. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  953. soc->wlan_cfg_ctx, intr_ctx_num);
  954. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  955. soc->wlan_cfg_ctx, intr_ctx_num);
  956. unsigned int vector =
  957. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  958. int num_irq = 0;
  959. soc->intr_mode = DP_INTR_MSI;
  960. if (tx_mask | rx_mask | rx_mon_mask | rx_err_ring_mask |
  961. rx_wbm_rel_ring_mask | reo_status_ring_mask | rxdma2host_ring_mask)
  962. irq_id_map[num_irq++] =
  963. pld_get_msi_irq(soc->osdev->dev, vector);
  964. *num_irq_r = num_irq;
  965. }
  966. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  967. int *irq_id_map, int *num_irq)
  968. {
  969. int msi_vector_count, ret;
  970. uint32_t msi_base_data, msi_vector_start;
  971. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  972. &msi_vector_count,
  973. &msi_base_data,
  974. &msi_vector_start);
  975. if (ret)
  976. return dp_soc_interrupt_map_calculate_integrated(soc,
  977. intr_ctx_num, irq_id_map, num_irq);
  978. else
  979. dp_soc_interrupt_map_calculate_msi(soc,
  980. intr_ctx_num, irq_id_map, num_irq,
  981. msi_vector_count, msi_vector_start);
  982. }
  983. /*
  984. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  985. * @txrx_soc: DP SOC handle
  986. *
  987. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  988. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  989. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  990. *
  991. * Return: 0 for success. nonzero for failure.
  992. */
  993. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  994. {
  995. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  996. int i = 0;
  997. int num_irq = 0;
  998. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  999. int ret = 0;
  1000. /* Map of IRQ ids registered with one interrupt context */
  1001. int irq_id_map[HIF_MAX_GRP_IRQ];
  1002. int tx_mask =
  1003. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  1004. int rx_mask =
  1005. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  1006. int rx_mon_mask =
  1007. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  1008. int rx_err_ring_mask =
  1009. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  1010. int rx_wbm_rel_ring_mask =
  1011. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  1012. int reo_status_ring_mask =
  1013. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  1014. int rxdma2host_ring_mask =
  1015. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  1016. soc->intr_ctx[i].dp_intr_id = i;
  1017. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  1018. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  1019. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  1020. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  1021. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  1022. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  1023. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  1024. soc->intr_ctx[i].soc = soc;
  1025. num_irq = 0;
  1026. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  1027. &num_irq);
  1028. ret = hif_register_ext_group(soc->hif_handle,
  1029. num_irq, irq_id_map, dp_service_srngs,
  1030. &soc->intr_ctx[i], "dp_intr",
  1031. HIF_EXEC_NAPI_TYPE, 2);
  1032. if (ret) {
  1033. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1034. FL("failed, ret = %d"), ret);
  1035. return QDF_STATUS_E_FAILURE;
  1036. }
  1037. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  1038. }
  1039. hif_configure_ext_group_interrupts(soc->hif_handle);
  1040. return QDF_STATUS_SUCCESS;
  1041. }
  1042. /*
  1043. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  1044. * @txrx_soc: DP SOC handle
  1045. *
  1046. * Return: void
  1047. */
  1048. static void dp_soc_interrupt_detach(void *txrx_soc)
  1049. {
  1050. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1051. int i;
  1052. if (soc->intr_mode == DP_INTR_POLL) {
  1053. qdf_timer_stop(&soc->int_timer);
  1054. qdf_timer_free(&soc->int_timer);
  1055. } else {
  1056. hif_deregister_exec_group(soc->hif_handle, "dp_intr");
  1057. }
  1058. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1059. soc->intr_ctx[i].tx_ring_mask = 0;
  1060. soc->intr_ctx[i].rx_ring_mask = 0;
  1061. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  1062. soc->intr_ctx[i].rx_err_ring_mask = 0;
  1063. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  1064. soc->intr_ctx[i].reo_status_ring_mask = 0;
  1065. soc->intr_ctx[i].rxdma2host_ring_mask = 0;
  1066. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  1067. }
  1068. }
  1069. #define AVG_MAX_MPDUS_PER_TID 128
  1070. #define AVG_TIDS_PER_CLIENT 2
  1071. #define AVG_FLOWS_PER_TID 2
  1072. #define AVG_MSDUS_PER_FLOW 128
  1073. #define AVG_MSDUS_PER_MPDU 4
  1074. /*
  1075. * Allocate and setup link descriptor pool that will be used by HW for
  1076. * various link and queue descriptors and managed by WBM
  1077. */
  1078. static int dp_hw_link_desc_pool_setup(struct dp_soc *soc)
  1079. {
  1080. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  1081. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  1082. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  1083. uint32_t num_mpdus_per_link_desc =
  1084. hal_num_mpdus_per_link_desc(soc->hal_soc);
  1085. uint32_t num_msdus_per_link_desc =
  1086. hal_num_msdus_per_link_desc(soc->hal_soc);
  1087. uint32_t num_mpdu_links_per_queue_desc =
  1088. hal_num_mpdu_links_per_queue_desc(soc->hal_soc);
  1089. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1090. uint32_t total_link_descs, total_mem_size;
  1091. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  1092. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  1093. uint32_t num_link_desc_banks;
  1094. uint32_t last_bank_size = 0;
  1095. uint32_t entry_size, num_entries;
  1096. int i;
  1097. uint32_t desc_id = 0;
  1098. /* Only Tx queue descriptors are allocated from common link descriptor
  1099. * pool Rx queue descriptors are not included in this because (REO queue
  1100. * extension descriptors) they are expected to be allocated contiguously
  1101. * with REO queue descriptors
  1102. */
  1103. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1104. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  1105. num_mpdu_queue_descs = num_mpdu_link_descs /
  1106. num_mpdu_links_per_queue_desc;
  1107. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1108. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  1109. num_msdus_per_link_desc;
  1110. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1111. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  1112. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  1113. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  1114. /* Round up to power of 2 */
  1115. total_link_descs = 1;
  1116. while (total_link_descs < num_entries)
  1117. total_link_descs <<= 1;
  1118. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1119. FL("total_link_descs: %u, link_desc_size: %d"),
  1120. total_link_descs, link_desc_size);
  1121. total_mem_size = total_link_descs * link_desc_size;
  1122. total_mem_size += link_desc_align;
  1123. if (total_mem_size <= max_alloc_size) {
  1124. num_link_desc_banks = 0;
  1125. last_bank_size = total_mem_size;
  1126. } else {
  1127. num_link_desc_banks = (total_mem_size) /
  1128. (max_alloc_size - link_desc_align);
  1129. last_bank_size = total_mem_size %
  1130. (max_alloc_size - link_desc_align);
  1131. }
  1132. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1133. FL("total_mem_size: %d, num_link_desc_banks: %u"),
  1134. total_mem_size, num_link_desc_banks);
  1135. for (i = 0; i < num_link_desc_banks; i++) {
  1136. soc->link_desc_banks[i].base_vaddr_unaligned =
  1137. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1138. max_alloc_size,
  1139. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1140. soc->link_desc_banks[i].size = max_alloc_size;
  1141. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)(
  1142. soc->link_desc_banks[i].base_vaddr_unaligned) +
  1143. ((unsigned long)(
  1144. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1145. link_desc_align));
  1146. soc->link_desc_banks[i].base_paddr = (unsigned long)(
  1147. soc->link_desc_banks[i].base_paddr_unaligned) +
  1148. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1149. (unsigned long)(
  1150. soc->link_desc_banks[i].base_vaddr_unaligned));
  1151. if (!soc->link_desc_banks[i].base_vaddr_unaligned) {
  1152. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1153. FL("Link descriptor memory alloc failed"));
  1154. goto fail;
  1155. }
  1156. }
  1157. if (last_bank_size) {
  1158. /* Allocate last bank in case total memory required is not exact
  1159. * multiple of max_alloc_size
  1160. */
  1161. soc->link_desc_banks[i].base_vaddr_unaligned =
  1162. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1163. last_bank_size,
  1164. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1165. soc->link_desc_banks[i].size = last_bank_size;
  1166. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)
  1167. (soc->link_desc_banks[i].base_vaddr_unaligned) +
  1168. ((unsigned long)(
  1169. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1170. link_desc_align));
  1171. soc->link_desc_banks[i].base_paddr =
  1172. (unsigned long)(
  1173. soc->link_desc_banks[i].base_paddr_unaligned) +
  1174. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1175. (unsigned long)(
  1176. soc->link_desc_banks[i].base_vaddr_unaligned));
  1177. }
  1178. /* Allocate and setup link descriptor idle list for HW internal use */
  1179. entry_size = hal_srng_get_entrysize(soc->hal_soc, WBM_IDLE_LINK);
  1180. total_mem_size = entry_size * total_link_descs;
  1181. if (total_mem_size <= max_alloc_size) {
  1182. void *desc;
  1183. if (dp_srng_setup(soc, &soc->wbm_idle_link_ring,
  1184. WBM_IDLE_LINK, 0, 0, total_link_descs)) {
  1185. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1186. FL("Link desc idle ring setup failed"));
  1187. goto fail;
  1188. }
  1189. hal_srng_access_start_unlocked(soc->hal_soc,
  1190. soc->wbm_idle_link_ring.hal_srng);
  1191. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1192. soc->link_desc_banks[i].base_paddr; i++) {
  1193. uint32_t num_entries = (soc->link_desc_banks[i].size -
  1194. ((unsigned long)(
  1195. soc->link_desc_banks[i].base_vaddr) -
  1196. (unsigned long)(
  1197. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1198. / link_desc_size;
  1199. unsigned long paddr = (unsigned long)(
  1200. soc->link_desc_banks[i].base_paddr);
  1201. while (num_entries && (desc = hal_srng_src_get_next(
  1202. soc->hal_soc,
  1203. soc->wbm_idle_link_ring.hal_srng))) {
  1204. hal_set_link_desc_addr(desc,
  1205. LINK_DESC_COOKIE(desc_id, i), paddr);
  1206. num_entries--;
  1207. desc_id++;
  1208. paddr += link_desc_size;
  1209. }
  1210. }
  1211. hal_srng_access_end_unlocked(soc->hal_soc,
  1212. soc->wbm_idle_link_ring.hal_srng);
  1213. } else {
  1214. uint32_t num_scatter_bufs;
  1215. uint32_t num_entries_per_buf;
  1216. uint32_t rem_entries;
  1217. uint8_t *scatter_buf_ptr;
  1218. uint16_t scatter_buf_num;
  1219. soc->wbm_idle_scatter_buf_size =
  1220. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1221. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  1222. soc->hal_soc, soc->wbm_idle_scatter_buf_size);
  1223. num_scatter_bufs = hal_idle_list_num_scatter_bufs(
  1224. soc->hal_soc, total_mem_size,
  1225. soc->wbm_idle_scatter_buf_size);
  1226. for (i = 0; i < num_scatter_bufs; i++) {
  1227. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1228. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1229. soc->wbm_idle_scatter_buf_size,
  1230. &(soc->wbm_idle_scatter_buf_base_paddr[i]));
  1231. if (soc->wbm_idle_scatter_buf_base_vaddr[i] == NULL) {
  1232. QDF_TRACE(QDF_MODULE_ID_DP,
  1233. QDF_TRACE_LEVEL_ERROR,
  1234. FL("Scatter list memory alloc failed"));
  1235. goto fail;
  1236. }
  1237. }
  1238. /* Populate idle list scatter buffers with link descriptor
  1239. * pointers
  1240. */
  1241. scatter_buf_num = 0;
  1242. scatter_buf_ptr = (uint8_t *)(
  1243. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  1244. rem_entries = num_entries_per_buf;
  1245. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1246. soc->link_desc_banks[i].base_paddr; i++) {
  1247. uint32_t num_link_descs =
  1248. (soc->link_desc_banks[i].size -
  1249. ((unsigned long)(
  1250. soc->link_desc_banks[i].base_vaddr) -
  1251. (unsigned long)(
  1252. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1253. / link_desc_size;
  1254. unsigned long paddr = (unsigned long)(
  1255. soc->link_desc_banks[i].base_paddr);
  1256. while (num_link_descs) {
  1257. hal_set_link_desc_addr((void *)scatter_buf_ptr,
  1258. LINK_DESC_COOKIE(desc_id, i), paddr);
  1259. num_link_descs--;
  1260. desc_id++;
  1261. paddr += link_desc_size;
  1262. rem_entries--;
  1263. if (rem_entries) {
  1264. scatter_buf_ptr += entry_size;
  1265. } else {
  1266. rem_entries = num_entries_per_buf;
  1267. scatter_buf_num++;
  1268. if (scatter_buf_num >= num_scatter_bufs)
  1269. break;
  1270. scatter_buf_ptr = (uint8_t *)(
  1271. soc->wbm_idle_scatter_buf_base_vaddr[
  1272. scatter_buf_num]);
  1273. }
  1274. }
  1275. }
  1276. /* Setup link descriptor idle list in HW */
  1277. hal_setup_link_idle_list(soc->hal_soc,
  1278. soc->wbm_idle_scatter_buf_base_paddr,
  1279. soc->wbm_idle_scatter_buf_base_vaddr,
  1280. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  1281. (uint32_t)(scatter_buf_ptr -
  1282. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  1283. scatter_buf_num-1])), total_link_descs);
  1284. }
  1285. return 0;
  1286. fail:
  1287. if (soc->wbm_idle_link_ring.hal_srng) {
  1288. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  1289. WBM_IDLE_LINK, 0);
  1290. }
  1291. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1292. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1293. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1294. soc->wbm_idle_scatter_buf_size,
  1295. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1296. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1297. }
  1298. }
  1299. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1300. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1301. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1302. soc->link_desc_banks[i].size,
  1303. soc->link_desc_banks[i].base_vaddr_unaligned,
  1304. soc->link_desc_banks[i].base_paddr_unaligned,
  1305. 0);
  1306. }
  1307. }
  1308. return QDF_STATUS_E_FAILURE;
  1309. }
  1310. /*
  1311. * Free link descriptor pool that was setup HW
  1312. */
  1313. static void dp_hw_link_desc_pool_cleanup(struct dp_soc *soc)
  1314. {
  1315. int i;
  1316. if (soc->wbm_idle_link_ring.hal_srng) {
  1317. dp_srng_cleanup(soc, &soc->wbm_idle_link_ring,
  1318. WBM_IDLE_LINK, 0);
  1319. }
  1320. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1321. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1322. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1323. soc->wbm_idle_scatter_buf_size,
  1324. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1325. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1326. }
  1327. }
  1328. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1329. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1330. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1331. soc->link_desc_banks[i].size,
  1332. soc->link_desc_banks[i].base_vaddr_unaligned,
  1333. soc->link_desc_banks[i].base_paddr_unaligned,
  1334. 0);
  1335. }
  1336. }
  1337. }
  1338. /* TODO: Following should be configurable */
  1339. #define WBM_RELEASE_RING_SIZE 64
  1340. #define TCL_CMD_RING_SIZE 32
  1341. #define TCL_STATUS_RING_SIZE 32
  1342. #if defined(QCA_WIFI_QCA6290)
  1343. #define REO_DST_RING_SIZE 1024
  1344. #else
  1345. #define REO_DST_RING_SIZE 2048
  1346. #endif
  1347. #define REO_REINJECT_RING_SIZE 32
  1348. #define RX_RELEASE_RING_SIZE 1024
  1349. #define REO_EXCEPTION_RING_SIZE 128
  1350. #define REO_CMD_RING_SIZE 32
  1351. #define REO_STATUS_RING_SIZE 32
  1352. #define RXDMA_BUF_RING_SIZE 1024
  1353. #define RXDMA_REFILL_RING_SIZE 2048
  1354. #define RXDMA_MONITOR_BUF_RING_SIZE 4096
  1355. #define RXDMA_MONITOR_DST_RING_SIZE 2048
  1356. #define RXDMA_MONITOR_STATUS_RING_SIZE 1024
  1357. #define RXDMA_MONITOR_DESC_RING_SIZE 2048
  1358. #define RXDMA_ERR_DST_RING_SIZE 1024
  1359. /*
  1360. * dp_wds_aging_timer_fn() - Timer callback function for WDS aging
  1361. * @soc: Datapath SOC handle
  1362. *
  1363. * This is a timer function used to age out stale WDS nodes from
  1364. * AST table
  1365. */
  1366. #ifdef FEATURE_WDS
  1367. static void dp_wds_aging_timer_fn(void *soc_hdl)
  1368. {
  1369. struct dp_soc *soc = (struct dp_soc *) soc_hdl;
  1370. struct dp_pdev *pdev;
  1371. struct dp_vdev *vdev;
  1372. struct dp_peer *peer;
  1373. struct dp_ast_entry *ase, *temp_ase;
  1374. int i;
  1375. qdf_spin_lock_bh(&soc->ast_lock);
  1376. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  1377. pdev = soc->pdev_list[i];
  1378. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  1379. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  1380. DP_PEER_ITERATE_ASE_LIST(peer, ase, temp_ase) {
  1381. /*
  1382. * Do not expire static ast entries
  1383. */
  1384. if (ase->type == CDP_TXRX_AST_TYPE_STATIC)
  1385. continue;
  1386. if (ase->is_active) {
  1387. ase->is_active = FALSE;
  1388. continue;
  1389. }
  1390. DP_STATS_INC(soc, ast.aged_out, 1);
  1391. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  1392. pdev->osif_pdev,
  1393. ase->mac_addr.raw);
  1394. dp_peer_del_ast(soc, ase);
  1395. }
  1396. }
  1397. }
  1398. }
  1399. qdf_spin_unlock_bh(&soc->ast_lock);
  1400. if (qdf_atomic_read(&soc->cmn_init_done))
  1401. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1402. }
  1403. /*
  1404. * dp_soc_wds_attach() - Setup WDS timer and AST table
  1405. * @soc: Datapath SOC handle
  1406. *
  1407. * Return: None
  1408. */
  1409. static void dp_soc_wds_attach(struct dp_soc *soc)
  1410. {
  1411. qdf_timer_init(soc->osdev, &soc->wds_aging_timer,
  1412. dp_wds_aging_timer_fn, (void *)soc,
  1413. QDF_TIMER_TYPE_WAKE_APPS);
  1414. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1415. }
  1416. /*
  1417. * dp_soc_wds_detach() - Detach WDS data structures and timers
  1418. * @txrx_soc: DP SOC handle
  1419. *
  1420. * Return: None
  1421. */
  1422. static void dp_soc_wds_detach(struct dp_soc *soc)
  1423. {
  1424. qdf_timer_stop(&soc->wds_aging_timer);
  1425. qdf_timer_free(&soc->wds_aging_timer);
  1426. }
  1427. #else
  1428. static void dp_soc_wds_attach(struct dp_soc *soc)
  1429. {
  1430. }
  1431. static void dp_soc_wds_detach(struct dp_soc *soc)
  1432. {
  1433. }
  1434. #endif
  1435. /*
  1436. * dp_soc_reset_ring_map() - Reset cpu ring map
  1437. * @soc: Datapath soc handler
  1438. *
  1439. * This api resets the default cpu ring map
  1440. */
  1441. static void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  1442. {
  1443. uint8_t i;
  1444. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1445. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  1446. if (nss_config == 1) {
  1447. /*
  1448. * Setting Tx ring map for one nss offloaded radio
  1449. */
  1450. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  1451. } else if (nss_config == 2) {
  1452. /*
  1453. * Setting Tx ring for two nss offloaded radios
  1454. */
  1455. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  1456. } else {
  1457. /*
  1458. * Setting Tx ring map for all nss offloaded radios
  1459. */
  1460. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_ALL_RADIO_OFFLOADED_MAP][i];
  1461. }
  1462. }
  1463. }
  1464. /*
  1465. * dp_soc_ring_if_nss_offloaded() - find if ring is offloaded to NSS
  1466. * @dp_soc - DP soc handle
  1467. * @ring_type - ring type
  1468. * @ring_num - ring_num
  1469. *
  1470. * return 0 or 1
  1471. */
  1472. static uint8_t dp_soc_ring_if_nss_offloaded(struct dp_soc *soc, enum hal_ring_type ring_type, int ring_num)
  1473. {
  1474. uint8_t nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1475. uint8_t status = 0;
  1476. switch (ring_type) {
  1477. case WBM2SW_RELEASE:
  1478. case REO_DST:
  1479. status = ((nss_config) & (1 << ring_num));
  1480. break;
  1481. default:
  1482. break;
  1483. }
  1484. return status;
  1485. }
  1486. /*
  1487. * dp_soc_reset_intr_mask() - reset interrupt mask
  1488. * @dp_soc - DP Soc handle
  1489. *
  1490. * Return: Return void
  1491. */
  1492. static void dp_soc_reset_intr_mask(struct dp_soc *soc)
  1493. {
  1494. uint8_t j;
  1495. int *grp_mask = NULL;
  1496. int group_number, mask, num_ring;
  1497. /* number of tx ring */
  1498. num_ring = wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1499. /*
  1500. * group mask for tx completion ring.
  1501. */
  1502. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  1503. /* loop and reset the mask for only offloaded ring */
  1504. for (j = 0; j < num_ring; j++) {
  1505. if (!dp_soc_ring_if_nss_offloaded(soc, WBM2SW_RELEASE, j)) {
  1506. continue;
  1507. }
  1508. /*
  1509. * Group number corresponding to tx offloaded ring.
  1510. */
  1511. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  1512. if (group_number < 0) {
  1513. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1514. FL("ring not part of an group; ring_type: %d,ring_num %d"),
  1515. WBM2SW_RELEASE, j);
  1516. return;
  1517. }
  1518. /* reset the tx mask for offloaded ring */
  1519. mask = wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, group_number);
  1520. mask &= (~(1 << j));
  1521. /*
  1522. * reset the interrupt mask for offloaded ring.
  1523. */
  1524. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  1525. }
  1526. /* number of rx rings */
  1527. num_ring = wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1528. /*
  1529. * group mask for reo destination ring.
  1530. */
  1531. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  1532. /* loop and reset the mask for only offloaded ring */
  1533. for (j = 0; j < num_ring; j++) {
  1534. if (!dp_soc_ring_if_nss_offloaded(soc, REO_DST, j)) {
  1535. continue;
  1536. }
  1537. /*
  1538. * Group number corresponding to rx offloaded ring.
  1539. */
  1540. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  1541. if (group_number < 0) {
  1542. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1543. FL("ring not part of an group; ring_type: %d,ring_num %d"),
  1544. REO_DST, j);
  1545. return;
  1546. }
  1547. /* set the interrupt mask for offloaded ring */
  1548. mask = wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, group_number);
  1549. mask &= (~(1 << j));
  1550. /*
  1551. * set the interrupt mask to zero for rx offloaded radio.
  1552. */
  1553. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  1554. }
  1555. }
  1556. #ifdef IPA_OFFLOAD
  1557. /**
  1558. * dp_reo_remap_config() - configure reo remap register value based
  1559. * nss configuration.
  1560. * based on offload_radio value below remap configuration
  1561. * get applied.
  1562. * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4)
  1563. * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4)
  1564. * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4)
  1565. * 3 - both Radios handled by NSS (remap not required)
  1566. * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3)
  1567. *
  1568. * @remap1: output parameter indicates reo remap 1 register value
  1569. * @remap2: output parameter indicates reo remap 2 register value
  1570. * Return: bool type, true if remap is configured else false.
  1571. */
  1572. static bool dp_reo_remap_config(struct dp_soc *soc,
  1573. uint32_t *remap1,
  1574. uint32_t *remap2)
  1575. {
  1576. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) | (0x1 << 9) |
  1577. (0x2 << 12) | (0x3 << 15) | (0x1 << 18) | (0x2 << 21)) << 8;
  1578. *remap2 = ((0x3 << 0) | (0x1 << 3) | (0x2 << 6) | (0x3 << 9) |
  1579. (0x1 << 12) | (0x2 << 15) | (0x3 << 18) | (0x1 << 21)) << 8;
  1580. return true;
  1581. }
  1582. #else
  1583. static bool dp_reo_remap_config(struct dp_soc *soc,
  1584. uint32_t *remap1,
  1585. uint32_t *remap2)
  1586. {
  1587. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1588. switch (offload_radio) {
  1589. case 0:
  1590. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1591. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1592. (0x3 << 18) | (0x4 << 21)) << 8;
  1593. *remap2 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1594. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1595. (0x3 << 18) | (0x4 << 21)) << 8;
  1596. break;
  1597. case 1:
  1598. *remap1 = ((0x2 << 0) | (0x3 << 3) | (0x4 << 6) |
  1599. (0x2 << 9) | (0x3 << 12) | (0x4 << 15) |
  1600. (0x2 << 18) | (0x3 << 21)) << 8;
  1601. *remap2 = ((0x4 << 0) | (0x2 << 3) | (0x3 << 6) |
  1602. (0x4 << 9) | (0x2 << 12) | (0x3 << 15) |
  1603. (0x4 << 18) | (0x2 << 21)) << 8;
  1604. break;
  1605. case 2:
  1606. *remap1 = ((0x1 << 0) | (0x3 << 3) | (0x4 << 6) |
  1607. (0x1 << 9) | (0x3 << 12) | (0x4 << 15) |
  1608. (0x1 << 18) | (0x3 << 21)) << 8;
  1609. *remap2 = ((0x4 << 0) | (0x1 << 3) | (0x3 << 6) |
  1610. (0x4 << 9) | (0x1 << 12) | (0x3 << 15) |
  1611. (0x4 << 18) | (0x1 << 21)) << 8;
  1612. break;
  1613. case 3:
  1614. /* return false if both radios are offloaded to NSS */
  1615. return false;
  1616. }
  1617. return true;
  1618. }
  1619. #endif
  1620. /*
  1621. * dp_soc_cmn_setup() - Common SoC level initializion
  1622. * @soc: Datapath SOC handle
  1623. *
  1624. * This is an internal function used to setup common SOC data structures,
  1625. * to be called from PDEV attach after receiving HW mode capabilities from FW
  1626. */
  1627. static int dp_soc_cmn_setup(struct dp_soc *soc)
  1628. {
  1629. int i;
  1630. struct hal_reo_params reo_params;
  1631. int tx_ring_size;
  1632. int tx_comp_ring_size;
  1633. if (qdf_atomic_read(&soc->cmn_init_done))
  1634. return 0;
  1635. if (dp_peer_find_attach(soc))
  1636. goto fail0;
  1637. if (dp_hw_link_desc_pool_setup(soc))
  1638. goto fail1;
  1639. /* Setup SRNG rings */
  1640. /* Common rings */
  1641. if (dp_srng_setup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0,
  1642. WBM_RELEASE_RING_SIZE)) {
  1643. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1644. FL("dp_srng_setup failed for wbm_desc_rel_ring"));
  1645. goto fail1;
  1646. }
  1647. soc->num_tcl_data_rings = 0;
  1648. /* Tx data rings */
  1649. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1650. soc->num_tcl_data_rings =
  1651. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1652. tx_comp_ring_size =
  1653. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1654. tx_ring_size =
  1655. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1656. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  1657. if (dp_srng_setup(soc, &soc->tcl_data_ring[i],
  1658. TCL_DATA, i, 0, tx_ring_size)) {
  1659. QDF_TRACE(QDF_MODULE_ID_DP,
  1660. QDF_TRACE_LEVEL_ERROR,
  1661. FL("dp_srng_setup failed for tcl_data_ring[%d]"), i);
  1662. goto fail1;
  1663. }
  1664. /*
  1665. * TBD: Set IPA WBM ring size with ini IPA UC tx buffer
  1666. * count
  1667. */
  1668. if (dp_srng_setup(soc, &soc->tx_comp_ring[i],
  1669. WBM2SW_RELEASE, i, 0, tx_comp_ring_size)) {
  1670. QDF_TRACE(QDF_MODULE_ID_DP,
  1671. QDF_TRACE_LEVEL_ERROR,
  1672. FL("dp_srng_setup failed for tx_comp_ring[%d]"), i);
  1673. goto fail1;
  1674. }
  1675. }
  1676. } else {
  1677. /* This will be incremented during per pdev ring setup */
  1678. soc->num_tcl_data_rings = 0;
  1679. }
  1680. if (dp_tx_soc_attach(soc)) {
  1681. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1682. FL("dp_tx_soc_attach failed"));
  1683. goto fail1;
  1684. }
  1685. /* TCL command and status rings */
  1686. if (dp_srng_setup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0, 0,
  1687. TCL_CMD_RING_SIZE)) {
  1688. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1689. FL("dp_srng_setup failed for tcl_cmd_ring"));
  1690. goto fail1;
  1691. }
  1692. if (dp_srng_setup(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0,
  1693. TCL_STATUS_RING_SIZE)) {
  1694. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1695. FL("dp_srng_setup failed for tcl_status_ring"));
  1696. goto fail1;
  1697. }
  1698. /* TBD: call dp_tx_init to setup Tx SW descriptors and MSDU extension
  1699. * descriptors
  1700. */
  1701. /* Rx data rings */
  1702. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1703. soc->num_reo_dest_rings =
  1704. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1705. QDF_TRACE(QDF_MODULE_ID_DP,
  1706. QDF_TRACE_LEVEL_ERROR,
  1707. FL("num_reo_dest_rings %d\n"), soc->num_reo_dest_rings);
  1708. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  1709. if (dp_srng_setup(soc, &soc->reo_dest_ring[i], REO_DST,
  1710. i, 0, REO_DST_RING_SIZE)) {
  1711. QDF_TRACE(QDF_MODULE_ID_DP,
  1712. QDF_TRACE_LEVEL_ERROR,
  1713. FL("dp_srng_setup failed for reo_dest_ring[%d]"), i);
  1714. goto fail1;
  1715. }
  1716. }
  1717. } else {
  1718. /* This will be incremented during per pdev ring setup */
  1719. soc->num_reo_dest_rings = 0;
  1720. }
  1721. /* TBD: call dp_rx_init to setup Rx SW descriptors */
  1722. /* REO reinjection ring */
  1723. if (dp_srng_setup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0,
  1724. REO_REINJECT_RING_SIZE)) {
  1725. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1726. FL("dp_srng_setup failed for reo_reinject_ring"));
  1727. goto fail1;
  1728. }
  1729. /* Rx release ring */
  1730. if (dp_srng_setup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 3, 0,
  1731. RX_RELEASE_RING_SIZE)) {
  1732. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1733. FL("dp_srng_setup failed for rx_rel_ring"));
  1734. goto fail1;
  1735. }
  1736. /* Rx exception ring */
  1737. if (dp_srng_setup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0,
  1738. MAX_REO_DEST_RINGS, REO_EXCEPTION_RING_SIZE)) {
  1739. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1740. FL("dp_srng_setup failed for reo_exception_ring"));
  1741. goto fail1;
  1742. }
  1743. /* REO command and status rings */
  1744. if (dp_srng_setup(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0,
  1745. REO_CMD_RING_SIZE)) {
  1746. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1747. FL("dp_srng_setup failed for reo_cmd_ring"));
  1748. goto fail1;
  1749. }
  1750. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  1751. TAILQ_INIT(&soc->rx.reo_cmd_list);
  1752. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  1753. if (dp_srng_setup(soc, &soc->reo_status_ring, REO_STATUS, 0, 0,
  1754. REO_STATUS_RING_SIZE)) {
  1755. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1756. FL("dp_srng_setup failed for reo_status_ring"));
  1757. goto fail1;
  1758. }
  1759. qdf_spinlock_create(&soc->ast_lock);
  1760. dp_soc_wds_attach(soc);
  1761. /* Reset the cpu ring map if radio is NSS offloaded */
  1762. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  1763. dp_soc_reset_cpu_ring_map(soc);
  1764. dp_soc_reset_intr_mask(soc);
  1765. }
  1766. /* Setup HW REO */
  1767. qdf_mem_zero(&reo_params, sizeof(reo_params));
  1768. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1769. /*
  1770. * Reo ring remap is not required if both radios
  1771. * are offloaded to NSS
  1772. */
  1773. if (!dp_reo_remap_config(soc,
  1774. &reo_params.remap1,
  1775. &reo_params.remap2))
  1776. goto out;
  1777. reo_params.rx_hash_enabled = true;
  1778. }
  1779. out:
  1780. hal_reo_setup(soc->hal_soc, &reo_params);
  1781. qdf_atomic_set(&soc->cmn_init_done, 1);
  1782. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  1783. return 0;
  1784. fail1:
  1785. /*
  1786. * Cleanup will be done as part of soc_detach, which will
  1787. * be called on pdev attach failure
  1788. */
  1789. fail0:
  1790. return QDF_STATUS_E_FAILURE;
  1791. }
  1792. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force);
  1793. static void dp_lro_hash_setup(struct dp_soc *soc)
  1794. {
  1795. struct cdp_lro_hash_config lro_hash;
  1796. if (!wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  1797. !wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1798. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1799. FL("LRO disabled RX hash disabled"));
  1800. return;
  1801. }
  1802. qdf_mem_zero(&lro_hash, sizeof(lro_hash));
  1803. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx)) {
  1804. lro_hash.lro_enable = 1;
  1805. lro_hash.tcp_flag = QDF_TCPHDR_ACK;
  1806. lro_hash.tcp_flag_mask = QDF_TCPHDR_FIN | QDF_TCPHDR_SYN |
  1807. QDF_TCPHDR_RST | QDF_TCPHDR_ACK | QDF_TCPHDR_URG |
  1808. QDF_TCPHDR_ECE | QDF_TCPHDR_CWR;
  1809. }
  1810. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, FL("enabled"));
  1811. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv4,
  1812. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1813. LRO_IPV4_SEED_ARR_SZ));
  1814. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv6,
  1815. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1816. LRO_IPV6_SEED_ARR_SZ));
  1817. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1818. "lro_hash: lro_enable: 0x%x"
  1819. "lro_hash: tcp_flag 0x%x tcp_flag_mask 0x%x",
  1820. lro_hash.lro_enable, lro_hash.tcp_flag,
  1821. lro_hash.tcp_flag_mask);
  1822. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1823. FL("lro_hash: toeplitz_hash_ipv4:"));
  1824. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1825. QDF_TRACE_LEVEL_ERROR,
  1826. (void *)lro_hash.toeplitz_hash_ipv4,
  1827. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1828. LRO_IPV4_SEED_ARR_SZ));
  1829. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1830. FL("lro_hash: toeplitz_hash_ipv6:"));
  1831. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1832. QDF_TRACE_LEVEL_ERROR,
  1833. (void *)lro_hash.toeplitz_hash_ipv6,
  1834. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1835. LRO_IPV6_SEED_ARR_SZ));
  1836. qdf_assert(soc->cdp_soc.ol_ops->lro_hash_config);
  1837. if (soc->cdp_soc.ol_ops->lro_hash_config)
  1838. (void)soc->cdp_soc.ol_ops->lro_hash_config
  1839. (soc->osif_soc, &lro_hash);
  1840. }
  1841. /*
  1842. * dp_rxdma_ring_setup() - configure the RX DMA rings
  1843. * @soc: data path SoC handle
  1844. * @pdev: Physical device handle
  1845. *
  1846. * Return: 0 - success, > 0 - failure
  1847. */
  1848. #ifdef QCA_HOST2FW_RXBUF_RING
  1849. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1850. struct dp_pdev *pdev)
  1851. {
  1852. int max_mac_rings =
  1853. wlan_cfg_get_num_mac_rings
  1854. (pdev->wlan_cfg_ctx);
  1855. int i;
  1856. for (i = 0; i < max_mac_rings; i++) {
  1857. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1858. "%s: pdev_id %d mac_id %d\n",
  1859. __func__, pdev->pdev_id, i);
  1860. if (dp_srng_setup(soc, &pdev->rx_mac_buf_ring[i],
  1861. RXDMA_BUF, 1, i, RXDMA_BUF_RING_SIZE)) {
  1862. QDF_TRACE(QDF_MODULE_ID_DP,
  1863. QDF_TRACE_LEVEL_ERROR,
  1864. FL("failed rx mac ring setup"));
  1865. return QDF_STATUS_E_FAILURE;
  1866. }
  1867. }
  1868. return QDF_STATUS_SUCCESS;
  1869. }
  1870. #else
  1871. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1872. struct dp_pdev *pdev)
  1873. {
  1874. return QDF_STATUS_SUCCESS;
  1875. }
  1876. #endif
  1877. /**
  1878. * dp_dscp_tid_map_setup(): Initialize the dscp-tid maps
  1879. * @pdev - DP_PDEV handle
  1880. *
  1881. * Return: void
  1882. */
  1883. static inline void
  1884. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  1885. {
  1886. uint8_t map_id;
  1887. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  1888. qdf_mem_copy(pdev->dscp_tid_map[map_id], default_dscp_tid_map,
  1889. sizeof(default_dscp_tid_map));
  1890. }
  1891. for (map_id = 0; map_id < HAL_MAX_HW_DSCP_TID_MAPS; map_id++) {
  1892. hal_tx_set_dscp_tid_map(pdev->soc->hal_soc,
  1893. pdev->dscp_tid_map[map_id],
  1894. map_id);
  1895. }
  1896. }
  1897. /*
  1898. * dp_ipa_ring_resource_setup() - setup IPA ring resources
  1899. * @soc: data path SoC handle
  1900. *
  1901. * Return: none
  1902. */
  1903. #ifdef IPA_OFFLOAD
  1904. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1905. struct dp_pdev *pdev)
  1906. {
  1907. void *hal_srng;
  1908. struct hal_srng_params srng_params;
  1909. qdf_dma_addr_t hp_addr, tp_addr;
  1910. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL4 */
  1911. hal_srng = soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  1912. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1913. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  1914. srng_params.ring_base_paddr;
  1915. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  1916. srng_params.ring_base_vaddr;
  1917. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  1918. srng_params.num_entries * srng_params.entry_size;
  1919. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1920. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr = hp_addr;
  1921. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW3_RELEASE */
  1922. hal_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1923. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1924. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  1925. srng_params.ring_base_paddr;
  1926. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  1927. srng_params.ring_base_vaddr;
  1928. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  1929. srng_params.num_entries * srng_params.entry_size;
  1930. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1931. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr = tp_addr;
  1932. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  1933. hal_srng = soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1934. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1935. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  1936. srng_params.ring_base_paddr;
  1937. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  1938. srng_params.ring_base_vaddr;
  1939. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  1940. srng_params.num_entries * srng_params.entry_size;
  1941. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1942. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr = tp_addr;
  1943. /* IPA RX_REFILL_BUF Ring - ipa_rx_refill_buf_ring */
  1944. if (dp_srng_setup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2,
  1945. pdev->pdev_id, RXDMA_BUF_RING_SIZE)) {
  1946. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1947. "%s: dp_srng_setup failed IPA rx refill ring\n",
  1948. __func__);
  1949. return -EFAULT;
  1950. }
  1951. hal_srng = pdev->ipa_rx_refill_buf_ring.hal_srng;
  1952. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1953. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  1954. srng_params.ring_base_paddr;
  1955. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  1956. srng_params.ring_base_vaddr;
  1957. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  1958. srng_params.num_entries * srng_params.entry_size;
  1959. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1960. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr = hp_addr;
  1961. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1962. "%s: ring_base_paddr:%pK, ring_base_vaddr:%pK"
  1963. "_entries:%d, hp_addr:%pK\n",
  1964. __func__,
  1965. (void *)srng_params.ring_base_paddr,
  1966. (void *)srng_params.ring_base_vaddr,
  1967. srng_params.num_entries,
  1968. (void *)hp_addr);
  1969. return 0;
  1970. }
  1971. #else
  1972. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1973. struct dp_pdev *pdev)
  1974. {
  1975. return 0;
  1976. }
  1977. #endif
  1978. /*
  1979. * dp_pdev_attach_wifi3() - attach txrx pdev
  1980. * @osif_pdev: Opaque PDEV handle from OSIF/HDD
  1981. * @txrx_soc: Datapath SOC handle
  1982. * @htc_handle: HTC handle for host-target interface
  1983. * @qdf_osdev: QDF OS device
  1984. * @pdev_id: PDEV ID
  1985. *
  1986. * Return: DP PDEV handle on success, NULL on failure
  1987. */
  1988. static struct cdp_pdev *dp_pdev_attach_wifi3(struct cdp_soc_t *txrx_soc,
  1989. struct cdp_cfg *ctrl_pdev,
  1990. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev, uint8_t pdev_id)
  1991. {
  1992. int tx_ring_size;
  1993. int tx_comp_ring_size;
  1994. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1995. struct dp_pdev *pdev = qdf_mem_malloc(sizeof(*pdev));
  1996. if (!pdev) {
  1997. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1998. FL("DP PDEV memory allocation failed"));
  1999. goto fail0;
  2000. }
  2001. pdev->wlan_cfg_ctx = wlan_cfg_pdev_attach();
  2002. if (!pdev->wlan_cfg_ctx) {
  2003. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2004. FL("pdev cfg_attach failed"));
  2005. qdf_mem_free(pdev);
  2006. goto fail0;
  2007. }
  2008. /*
  2009. * set nss pdev config based on soc config
  2010. */
  2011. wlan_cfg_set_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx,
  2012. (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx) & (1 << pdev_id)));
  2013. pdev->soc = soc;
  2014. pdev->osif_pdev = ctrl_pdev;
  2015. pdev->pdev_id = pdev_id;
  2016. soc->pdev_list[pdev_id] = pdev;
  2017. soc->pdev_count++;
  2018. TAILQ_INIT(&pdev->vdev_list);
  2019. pdev->vdev_count = 0;
  2020. qdf_spinlock_create(&pdev->tx_mutex);
  2021. qdf_spinlock_create(&pdev->neighbour_peer_mutex);
  2022. TAILQ_INIT(&pdev->neighbour_peers_list);
  2023. if (dp_soc_cmn_setup(soc)) {
  2024. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2025. FL("dp_soc_cmn_setup failed"));
  2026. goto fail1;
  2027. }
  2028. /* Setup per PDEV TCL rings if configured */
  2029. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2030. tx_ring_size =
  2031. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2032. tx_comp_ring_size =
  2033. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  2034. if (dp_srng_setup(soc, &soc->tcl_data_ring[pdev_id], TCL_DATA,
  2035. pdev_id, pdev_id, tx_ring_size)) {
  2036. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2037. FL("dp_srng_setup failed for tcl_data_ring"));
  2038. goto fail1;
  2039. }
  2040. if (dp_srng_setup(soc, &soc->tx_comp_ring[pdev_id],
  2041. WBM2SW_RELEASE, pdev_id, pdev_id, tx_comp_ring_size)) {
  2042. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2043. FL("dp_srng_setup failed for tx_comp_ring"));
  2044. goto fail1;
  2045. }
  2046. soc->num_tcl_data_rings++;
  2047. }
  2048. /* Tx specific init */
  2049. if (dp_tx_pdev_attach(pdev)) {
  2050. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2051. FL("dp_tx_pdev_attach failed"));
  2052. goto fail1;
  2053. }
  2054. /* Setup per PDEV REO rings if configured */
  2055. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2056. if (dp_srng_setup(soc, &soc->reo_dest_ring[pdev_id], REO_DST,
  2057. pdev_id, pdev_id, REO_DST_RING_SIZE)) {
  2058. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2059. FL("dp_srng_setup failed for reo_dest_ringn"));
  2060. goto fail1;
  2061. }
  2062. soc->num_reo_dest_rings++;
  2063. }
  2064. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0, pdev_id,
  2065. RXDMA_REFILL_RING_SIZE)) {
  2066. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2067. FL("dp_srng_setup failed rx refill ring"));
  2068. goto fail1;
  2069. }
  2070. if (dp_rxdma_ring_setup(soc, pdev)) {
  2071. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2072. FL("RXDMA ring config failed"));
  2073. goto fail1;
  2074. }
  2075. if (dp_srng_setup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0,
  2076. pdev_id, RXDMA_MONITOR_BUF_RING_SIZE)) {
  2077. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2078. FL("dp_srng_setup failed for rxdma_mon_buf_ring"));
  2079. goto fail1;
  2080. }
  2081. if (dp_srng_setup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0,
  2082. pdev_id, RXDMA_MONITOR_DST_RING_SIZE)) {
  2083. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2084. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  2085. goto fail1;
  2086. }
  2087. if (dp_srng_setup(soc, &pdev->rxdma_mon_status_ring,
  2088. RXDMA_MONITOR_STATUS, 0, pdev_id,
  2089. RXDMA_MONITOR_STATUS_RING_SIZE)) {
  2090. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2091. FL("dp_srng_setup failed for rxdma_mon_status_ring"));
  2092. goto fail1;
  2093. }
  2094. if (dp_srng_setup(soc, &pdev->rxdma_mon_desc_ring,
  2095. RXDMA_MONITOR_DESC, 0, pdev_id, RXDMA_MONITOR_DESC_RING_SIZE)) {
  2096. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2097. "dp_srng_setup failed for rxdma_mon_desc_ring\n");
  2098. goto fail1;
  2099. }
  2100. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0,
  2101. pdev_id, RXDMA_ERR_DST_RING_SIZE)) {
  2102. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2103. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  2104. goto fail1;
  2105. }
  2106. if (dp_ipa_ring_resource_setup(soc, pdev))
  2107. goto fail1;
  2108. if (dp_ipa_uc_attach(soc, pdev) != QDF_STATUS_SUCCESS) {
  2109. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2110. "%s: dp_ipa_uc_attach failed\n", __func__);
  2111. goto fail1;
  2112. }
  2113. /* Rx specific init */
  2114. if (dp_rx_pdev_attach(pdev)) {
  2115. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2116. FL("dp_rx_pdev_attach failed "));
  2117. goto fail0;
  2118. }
  2119. DP_STATS_INIT(pdev);
  2120. #ifndef CONFIG_WIN
  2121. /* MCL */
  2122. dp_local_peer_id_pool_init(pdev);
  2123. #endif
  2124. dp_dscp_tid_map_setup(pdev);
  2125. /* Rx monitor mode specific init */
  2126. if (dp_rx_pdev_mon_attach(pdev)) {
  2127. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2128. "dp_rx_pdev_attach failed\n");
  2129. goto fail1;
  2130. }
  2131. if (dp_wdi_event_attach(pdev)) {
  2132. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2133. "dp_wdi_evet_attach failed\n");
  2134. goto fail1;
  2135. }
  2136. /* set the reo destination during initialization */
  2137. pdev->reo_dest = pdev->pdev_id + 1;
  2138. return (struct cdp_pdev *)pdev;
  2139. fail1:
  2140. dp_pdev_detach_wifi3((struct cdp_pdev *)pdev, 0);
  2141. fail0:
  2142. return NULL;
  2143. }
  2144. /*
  2145. * dp_rxdma_ring_cleanup() - configure the RX DMA rings
  2146. * @soc: data path SoC handle
  2147. * @pdev: Physical device handle
  2148. *
  2149. * Return: void
  2150. */
  2151. #ifdef QCA_HOST2FW_RXBUF_RING
  2152. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2153. struct dp_pdev *pdev)
  2154. {
  2155. int max_mac_rings =
  2156. wlan_cfg_get_num_mac_rings(pdev->wlan_cfg_ctx);
  2157. int i;
  2158. max_mac_rings = max_mac_rings < MAX_RX_MAC_RINGS ?
  2159. max_mac_rings : MAX_RX_MAC_RINGS;
  2160. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  2161. dp_srng_cleanup(soc, &pdev->rx_mac_buf_ring[i],
  2162. RXDMA_BUF, 1);
  2163. }
  2164. #else
  2165. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2166. struct dp_pdev *pdev)
  2167. {
  2168. }
  2169. #endif
  2170. /*
  2171. * dp_neighbour_peers_detach() - Detach neighbour peers(nac clients)
  2172. * @pdev: device object
  2173. *
  2174. * Return: void
  2175. */
  2176. static void dp_neighbour_peers_detach(struct dp_pdev *pdev)
  2177. {
  2178. struct dp_neighbour_peer *peer = NULL;
  2179. struct dp_neighbour_peer *temp_peer = NULL;
  2180. TAILQ_FOREACH_SAFE(peer, &pdev->neighbour_peers_list,
  2181. neighbour_peer_list_elem, temp_peer) {
  2182. /* delete this peer from the list */
  2183. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2184. peer, neighbour_peer_list_elem);
  2185. qdf_mem_free(peer);
  2186. }
  2187. qdf_spinlock_destroy(&pdev->neighbour_peer_mutex);
  2188. }
  2189. /*
  2190. * dp_pdev_detach_wifi3() - detach txrx pdev
  2191. * @txrx_pdev: Datapath PDEV handle
  2192. * @force: Force detach
  2193. *
  2194. */
  2195. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force)
  2196. {
  2197. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2198. struct dp_soc *soc = pdev->soc;
  2199. dp_wdi_event_detach(pdev);
  2200. dp_tx_pdev_detach(pdev);
  2201. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2202. dp_srng_cleanup(soc, &soc->tcl_data_ring[pdev->pdev_id],
  2203. TCL_DATA, pdev->pdev_id);
  2204. dp_srng_cleanup(soc, &soc->tx_comp_ring[pdev->pdev_id],
  2205. WBM2SW_RELEASE, pdev->pdev_id);
  2206. }
  2207. dp_rx_pdev_detach(pdev);
  2208. dp_rx_pdev_mon_detach(pdev);
  2209. dp_neighbour_peers_detach(pdev);
  2210. qdf_spinlock_destroy(&pdev->tx_mutex);
  2211. dp_ipa_uc_detach(soc, pdev);
  2212. /* Cleanup per PDEV REO rings if configured */
  2213. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2214. dp_srng_cleanup(soc, &soc->reo_dest_ring[pdev->pdev_id],
  2215. REO_DST, pdev->pdev_id);
  2216. }
  2217. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0);
  2218. dp_rxdma_ring_cleanup(soc, pdev);
  2219. dp_srng_cleanup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0);
  2220. dp_srng_cleanup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0);
  2221. dp_srng_cleanup(soc, &pdev->rxdma_mon_status_ring,
  2222. RXDMA_MONITOR_STATUS, 0);
  2223. dp_srng_cleanup(soc, &pdev->rxdma_mon_desc_ring,
  2224. RXDMA_MONITOR_DESC, 0);
  2225. dp_srng_cleanup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0);
  2226. soc->pdev_list[pdev->pdev_id] = NULL;
  2227. soc->pdev_count--;
  2228. wlan_cfg_pdev_detach(pdev->wlan_cfg_ctx);
  2229. qdf_mem_free(pdev);
  2230. }
  2231. /*
  2232. * dp_reo_desc_freelist_destroy() - Flush REO descriptors from deferred freelist
  2233. * @soc: DP SOC handle
  2234. */
  2235. static inline void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  2236. {
  2237. struct reo_desc_list_node *desc;
  2238. struct dp_rx_tid *rx_tid;
  2239. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  2240. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  2241. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2242. rx_tid = &desc->rx_tid;
  2243. qdf_mem_unmap_nbytes_single(soc->osdev,
  2244. rx_tid->hw_qdesc_paddr,
  2245. QDF_DMA_BIDIRECTIONAL,
  2246. rx_tid->hw_qdesc_alloc_size);
  2247. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  2248. qdf_mem_free(desc);
  2249. }
  2250. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  2251. qdf_list_destroy(&soc->reo_desc_freelist);
  2252. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  2253. }
  2254. /*
  2255. * dp_soc_detach_wifi3() - Detach txrx SOC
  2256. * @txrx_soc: DP SOC handle, struct cdp_soc_t is first element of struct dp_soc.
  2257. */
  2258. static void dp_soc_detach_wifi3(void *txrx_soc)
  2259. {
  2260. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2261. int i;
  2262. qdf_atomic_set(&soc->cmn_init_done, 0);
  2263. qdf_flush_work(&soc->htt_stats.work);
  2264. qdf_disable_work(&soc->htt_stats.work);
  2265. /* Free pending htt stats messages */
  2266. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  2267. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2268. if (soc->pdev_list[i])
  2269. dp_pdev_detach_wifi3(
  2270. (struct cdp_pdev *)soc->pdev_list[i], 1);
  2271. }
  2272. dp_peer_find_detach(soc);
  2273. /* TBD: Call Tx and Rx cleanup functions to free buffers and
  2274. * SW descriptors
  2275. */
  2276. /* Free the ring memories */
  2277. /* Common rings */
  2278. dp_srng_cleanup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  2279. dp_tx_soc_detach(soc);
  2280. /* Tx data rings */
  2281. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2282. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2283. dp_srng_cleanup(soc, &soc->tcl_data_ring[i],
  2284. TCL_DATA, i);
  2285. dp_srng_cleanup(soc, &soc->tx_comp_ring[i],
  2286. WBM2SW_RELEASE, i);
  2287. }
  2288. }
  2289. /* TCL command and status rings */
  2290. dp_srng_cleanup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0);
  2291. dp_srng_cleanup(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  2292. /* Rx data rings */
  2293. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2294. soc->num_reo_dest_rings =
  2295. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  2296. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  2297. /* TODO: Get number of rings and ring sizes
  2298. * from wlan_cfg
  2299. */
  2300. dp_srng_cleanup(soc, &soc->reo_dest_ring[i],
  2301. REO_DST, i);
  2302. }
  2303. }
  2304. /* REO reinjection ring */
  2305. dp_srng_cleanup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  2306. /* Rx release ring */
  2307. dp_srng_cleanup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  2308. /* Rx exception ring */
  2309. /* TODO: Better to store ring_type and ring_num in
  2310. * dp_srng during setup
  2311. */
  2312. dp_srng_cleanup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  2313. /* REO command and status rings */
  2314. dp_srng_cleanup(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  2315. dp_srng_cleanup(soc, &soc->reo_status_ring, REO_STATUS, 0);
  2316. dp_hw_link_desc_pool_cleanup(soc);
  2317. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2318. qdf_spinlock_destroy(&soc->peer_ref_mutex);
  2319. qdf_spinlock_destroy(&soc->htt_stats.lock);
  2320. htt_soc_detach(soc->htt_handle);
  2321. dp_reo_cmdlist_destroy(soc);
  2322. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2323. dp_reo_desc_freelist_destroy(soc);
  2324. wlan_cfg_soc_detach(soc->wlan_cfg_ctx);
  2325. dp_soc_wds_detach(soc);
  2326. qdf_spinlock_destroy(&soc->ast_lock);
  2327. qdf_mem_free(soc);
  2328. }
  2329. /*
  2330. * dp_setup_ipa_rx_refill_buf_ring() - setup IPA RX Refill buffer ring
  2331. * @soc: data path SoC handle
  2332. * @pdev: physical device handle
  2333. *
  2334. * Return: void
  2335. */
  2336. #ifdef IPA_OFFLOAD
  2337. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2338. struct dp_pdev *pdev)
  2339. {
  2340. htt_srng_setup(soc->htt_handle, 0,
  2341. pdev->ipa_rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2342. }
  2343. #else
  2344. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2345. struct dp_pdev *pdev)
  2346. {
  2347. }
  2348. #endif
  2349. /*
  2350. * dp_rxdma_ring_config() - configure the RX DMA rings
  2351. *
  2352. * This function is used to configure the MAC rings.
  2353. * On MCL host provides buffers in Host2FW ring
  2354. * FW refills (copies) buffers to the ring and updates
  2355. * ring_idx in register
  2356. *
  2357. * @soc: data path SoC handle
  2358. *
  2359. * Return: void
  2360. */
  2361. #ifdef QCA_HOST2FW_RXBUF_RING
  2362. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2363. {
  2364. int i;
  2365. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2366. struct dp_pdev *pdev = soc->pdev_list[i];
  2367. if (pdev) {
  2368. int mac_id = 0;
  2369. int j;
  2370. bool dbs_enable = 0;
  2371. int max_mac_rings =
  2372. wlan_cfg_get_num_mac_rings
  2373. (pdev->wlan_cfg_ctx);
  2374. htt_srng_setup(soc->htt_handle, 0,
  2375. pdev->rx_refill_buf_ring.hal_srng,
  2376. RXDMA_BUF);
  2377. dp_config_ipa_rx_refill_buf_ring(soc, pdev);
  2378. if (soc->cdp_soc.ol_ops->
  2379. is_hw_dbs_2x2_capable) {
  2380. dbs_enable = soc->cdp_soc.ol_ops->
  2381. is_hw_dbs_2x2_capable(soc->psoc);
  2382. }
  2383. if (dbs_enable) {
  2384. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2385. QDF_TRACE_LEVEL_ERROR,
  2386. FL("DBS enabled max_mac_rings %d\n"),
  2387. max_mac_rings);
  2388. } else {
  2389. max_mac_rings = 1;
  2390. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2391. QDF_TRACE_LEVEL_ERROR,
  2392. FL("DBS disabled, max_mac_rings %d\n"),
  2393. max_mac_rings);
  2394. }
  2395. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2396. FL("pdev_id %d max_mac_rings %d\n"),
  2397. pdev->pdev_id, max_mac_rings);
  2398. for (j = 0; j < max_mac_rings; j++) {
  2399. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2400. QDF_TRACE_LEVEL_ERROR,
  2401. FL("mac_id %d\n"), mac_id);
  2402. htt_srng_setup(soc->htt_handle, mac_id,
  2403. pdev->rx_mac_buf_ring[j]
  2404. .hal_srng,
  2405. RXDMA_BUF);
  2406. mac_id++;
  2407. }
  2408. /* Configure monitor mode rings */
  2409. htt_srng_setup(soc->htt_handle, i,
  2410. pdev->rxdma_mon_buf_ring.hal_srng,
  2411. RXDMA_MONITOR_BUF);
  2412. htt_srng_setup(soc->htt_handle, i,
  2413. pdev->rxdma_mon_dst_ring.hal_srng,
  2414. RXDMA_MONITOR_DST);
  2415. htt_srng_setup(soc->htt_handle, i,
  2416. pdev->rxdma_mon_status_ring.hal_srng,
  2417. RXDMA_MONITOR_STATUS);
  2418. htt_srng_setup(soc->htt_handle, i,
  2419. pdev->rxdma_mon_desc_ring.hal_srng,
  2420. RXDMA_MONITOR_DESC);
  2421. htt_srng_setup(soc->htt_handle, i,
  2422. pdev->rxdma_err_dst_ring.hal_srng,
  2423. RXDMA_DST);
  2424. }
  2425. }
  2426. }
  2427. #else
  2428. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2429. {
  2430. int i;
  2431. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2432. struct dp_pdev *pdev = soc->pdev_list[i];
  2433. if (pdev) {
  2434. htt_srng_setup(soc->htt_handle, i,
  2435. pdev->rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2436. htt_srng_setup(soc->htt_handle, i,
  2437. pdev->rxdma_mon_buf_ring.hal_srng,
  2438. RXDMA_MONITOR_BUF);
  2439. htt_srng_setup(soc->htt_handle, i,
  2440. pdev->rxdma_mon_dst_ring.hal_srng,
  2441. RXDMA_MONITOR_DST);
  2442. htt_srng_setup(soc->htt_handle, i,
  2443. pdev->rxdma_mon_status_ring.hal_srng,
  2444. RXDMA_MONITOR_STATUS);
  2445. htt_srng_setup(soc->htt_handle, i,
  2446. pdev->rxdma_mon_desc_ring.hal_srng,
  2447. RXDMA_MONITOR_DESC);
  2448. htt_srng_setup(soc->htt_handle, i,
  2449. pdev->rxdma_err_dst_ring.hal_srng,
  2450. RXDMA_DST);
  2451. }
  2452. }
  2453. }
  2454. #endif
  2455. /*
  2456. * dp_soc_attach_target_wifi3() - SOC initialization in the target
  2457. * @txrx_soc: Datapath SOC handle
  2458. */
  2459. static int dp_soc_attach_target_wifi3(struct cdp_soc_t *cdp_soc)
  2460. {
  2461. struct dp_soc *soc = (struct dp_soc *)cdp_soc;
  2462. htt_soc_attach_target(soc->htt_handle);
  2463. dp_rxdma_ring_config(soc);
  2464. DP_STATS_INIT(soc);
  2465. /* initialize work queue for stats processing */
  2466. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  2467. return 0;
  2468. }
  2469. /*
  2470. * dp_soc_get_nss_cfg_wifi3() - SOC get nss config
  2471. * @txrx_soc: Datapath SOC handle
  2472. */
  2473. static int dp_soc_get_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc)
  2474. {
  2475. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2476. return wlan_cfg_get_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx);
  2477. }
  2478. /*
  2479. * dp_soc_set_nss_cfg_wifi3() - SOC set nss config
  2480. * @txrx_soc: Datapath SOC handle
  2481. * @nss_cfg: nss config
  2482. */
  2483. static void dp_soc_set_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc, int config)
  2484. {
  2485. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2486. wlan_cfg_set_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx, config);
  2487. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2488. FL("nss-wifi<0> nss config is enabled"));
  2489. }
  2490. /*
  2491. * dp_vdev_attach_wifi3() - attach txrx vdev
  2492. * @txrx_pdev: Datapath PDEV handle
  2493. * @vdev_mac_addr: MAC address of the virtual interface
  2494. * @vdev_id: VDEV Id
  2495. * @wlan_op_mode: VDEV operating mode
  2496. *
  2497. * Return: DP VDEV handle on success, NULL on failure
  2498. */
  2499. static struct cdp_vdev *dp_vdev_attach_wifi3(struct cdp_pdev *txrx_pdev,
  2500. uint8_t *vdev_mac_addr, uint8_t vdev_id, enum wlan_op_mode op_mode)
  2501. {
  2502. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2503. struct dp_soc *soc = pdev->soc;
  2504. struct dp_vdev *vdev = qdf_mem_malloc(sizeof(*vdev));
  2505. int tx_ring_size;
  2506. if (!vdev) {
  2507. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2508. FL("DP VDEV memory allocation failed"));
  2509. goto fail0;
  2510. }
  2511. vdev->pdev = pdev;
  2512. vdev->vdev_id = vdev_id;
  2513. vdev->opmode = op_mode;
  2514. vdev->osdev = soc->osdev;
  2515. vdev->osif_rx = NULL;
  2516. vdev->osif_rsim_rx_decap = NULL;
  2517. vdev->osif_get_key = NULL;
  2518. vdev->osif_rx_mon = NULL;
  2519. vdev->osif_tx_free_ext = NULL;
  2520. vdev->osif_vdev = NULL;
  2521. vdev->delete.pending = 0;
  2522. vdev->safemode = 0;
  2523. vdev->drop_unenc = 1;
  2524. #ifdef notyet
  2525. vdev->filters_num = 0;
  2526. #endif
  2527. qdf_mem_copy(
  2528. &vdev->mac_addr.raw[0], vdev_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2529. vdev->tx_encap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2530. vdev->rx_decap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2531. vdev->dscp_tid_map_id = 0;
  2532. vdev->mcast_enhancement_en = 0;
  2533. tx_ring_size = wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2534. /* TODO: Initialize default HTT meta data that will be used in
  2535. * TCL descriptors for packets transmitted from this VDEV
  2536. */
  2537. TAILQ_INIT(&vdev->peer_list);
  2538. /* add this vdev into the pdev's list */
  2539. TAILQ_INSERT_TAIL(&pdev->vdev_list, vdev, vdev_list_elem);
  2540. pdev->vdev_count++;
  2541. dp_tx_vdev_attach(vdev);
  2542. if (QDF_STATUS_SUCCESS != dp_tx_flow_pool_map_handler(pdev, vdev_id,
  2543. FLOW_TYPE_VDEV, vdev_id, tx_ring_size))
  2544. goto fail1;
  2545. if ((soc->intr_mode == DP_INTR_POLL) &&
  2546. wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx) != 0) {
  2547. if (pdev->vdev_count == 1)
  2548. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  2549. }
  2550. dp_lro_hash_setup(soc);
  2551. /* LRO */
  2552. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  2553. wlan_op_mode_sta == vdev->opmode)
  2554. vdev->lro_enable = true;
  2555. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2556. "LRO: vdev_id %d lro_enable %d", vdev_id, vdev->lro_enable);
  2557. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2558. "Created vdev %pK (%pM)", vdev, vdev->mac_addr.raw);
  2559. DP_STATS_INIT(vdev);
  2560. return (struct cdp_vdev *)vdev;
  2561. fail1:
  2562. dp_tx_vdev_detach(vdev);
  2563. qdf_mem_free(vdev);
  2564. fail0:
  2565. return NULL;
  2566. }
  2567. /**
  2568. * dp_vdev_register_wifi3() - Register VDEV operations from osif layer
  2569. * @vdev: Datapath VDEV handle
  2570. * @osif_vdev: OSIF vdev handle
  2571. * @txrx_ops: Tx and Rx operations
  2572. *
  2573. * Return: DP VDEV handle on success, NULL on failure
  2574. */
  2575. static void dp_vdev_register_wifi3(struct cdp_vdev *vdev_handle,
  2576. void *osif_vdev,
  2577. struct ol_txrx_ops *txrx_ops)
  2578. {
  2579. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2580. vdev->osif_vdev = osif_vdev;
  2581. vdev->osif_rx = txrx_ops->rx.rx;
  2582. vdev->osif_rsim_rx_decap = txrx_ops->rx.rsim_rx_decap;
  2583. vdev->osif_get_key = txrx_ops->get_key;
  2584. vdev->osif_rx_mon = txrx_ops->rx.mon;
  2585. vdev->osif_tx_free_ext = txrx_ops->tx.tx_free_ext;
  2586. #ifdef notyet
  2587. #if ATH_SUPPORT_WAPI
  2588. vdev->osif_check_wai = txrx_ops->rx.wai_check;
  2589. #endif
  2590. #endif
  2591. #ifdef UMAC_SUPPORT_PROXY_ARP
  2592. vdev->osif_proxy_arp = txrx_ops->proxy_arp;
  2593. #endif
  2594. vdev->me_convert = txrx_ops->me_convert;
  2595. /* TODO: Enable the following once Tx code is integrated */
  2596. txrx_ops->tx.tx = dp_tx_send;
  2597. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2598. "DP Vdev Register success");
  2599. }
  2600. /*
  2601. * dp_vdev_detach_wifi3() - Detach txrx vdev
  2602. * @txrx_vdev: Datapath VDEV handle
  2603. * @callback: Callback OL_IF on completion of detach
  2604. * @cb_context: Callback context
  2605. *
  2606. */
  2607. static void dp_vdev_detach_wifi3(struct cdp_vdev *vdev_handle,
  2608. ol_txrx_vdev_delete_cb callback, void *cb_context)
  2609. {
  2610. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2611. struct dp_pdev *pdev = vdev->pdev;
  2612. struct dp_soc *soc = pdev->soc;
  2613. /* preconditions */
  2614. qdf_assert(vdev);
  2615. /* remove the vdev from its parent pdev's list */
  2616. TAILQ_REMOVE(&pdev->vdev_list, vdev, vdev_list_elem);
  2617. /*
  2618. * Use peer_ref_mutex while accessing peer_list, in case
  2619. * a peer is in the process of being removed from the list.
  2620. */
  2621. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2622. /* check that the vdev has no peers allocated */
  2623. if (!TAILQ_EMPTY(&vdev->peer_list)) {
  2624. /* debug print - will be removed later */
  2625. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2626. FL("not deleting vdev object %pK (%pM)"
  2627. "until deletion finishes for all its peers"),
  2628. vdev, vdev->mac_addr.raw);
  2629. /* indicate that the vdev needs to be deleted */
  2630. vdev->delete.pending = 1;
  2631. vdev->delete.callback = callback;
  2632. vdev->delete.context = cb_context;
  2633. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2634. return;
  2635. }
  2636. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2637. dp_tx_flow_pool_unmap_handler(pdev, vdev->vdev_id, FLOW_TYPE_VDEV,
  2638. vdev->vdev_id);
  2639. dp_tx_vdev_detach(vdev);
  2640. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2641. FL("deleting vdev object %pK (%pM)"), vdev, vdev->mac_addr.raw);
  2642. qdf_mem_free(vdev);
  2643. if (callback)
  2644. callback(cb_context);
  2645. }
  2646. /*
  2647. * dp_peer_create_wifi3() - attach txrx peer
  2648. * @txrx_vdev: Datapath VDEV handle
  2649. * @peer_mac_addr: Peer MAC address
  2650. *
  2651. * Return: DP peeer handle on success, NULL on failure
  2652. */
  2653. static void *dp_peer_create_wifi3(struct cdp_vdev *vdev_handle,
  2654. uint8_t *peer_mac_addr)
  2655. {
  2656. struct dp_peer *peer;
  2657. int i;
  2658. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2659. struct dp_pdev *pdev;
  2660. struct dp_soc *soc;
  2661. /* preconditions */
  2662. qdf_assert(vdev);
  2663. qdf_assert(peer_mac_addr);
  2664. pdev = vdev->pdev;
  2665. soc = pdev->soc;
  2666. #ifdef notyet
  2667. peer = (struct dp_peer *)qdf_mempool_alloc(soc->osdev,
  2668. soc->mempool_ol_ath_peer);
  2669. #else
  2670. peer = (struct dp_peer *)qdf_mem_malloc(sizeof(*peer));
  2671. #endif
  2672. if (!peer)
  2673. return NULL; /* failure */
  2674. qdf_mem_zero(peer, sizeof(struct dp_peer));
  2675. TAILQ_INIT(&peer->ast_entry_list);
  2676. /* store provided params */
  2677. peer->vdev = vdev;
  2678. dp_peer_add_ast(soc, peer, peer_mac_addr, 1);
  2679. qdf_spinlock_create(&peer->peer_info_lock);
  2680. qdf_mem_copy(
  2681. &peer->mac_addr.raw[0], peer_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2682. /* TODO: See of rx_opt_proc is really required */
  2683. peer->rx_opt_proc = soc->rx_opt_proc;
  2684. /* initialize the peer_id */
  2685. for (i = 0; i < MAX_NUM_PEER_ID_PER_PEER; i++)
  2686. peer->peer_ids[i] = HTT_INVALID_PEER;
  2687. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2688. qdf_atomic_init(&peer->ref_cnt);
  2689. /* keep one reference for attach */
  2690. qdf_atomic_inc(&peer->ref_cnt);
  2691. /* add this peer into the vdev's list */
  2692. TAILQ_INSERT_TAIL(&vdev->peer_list, peer, peer_list_elem);
  2693. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2694. /* TODO: See if hash based search is required */
  2695. dp_peer_find_hash_add(soc, peer);
  2696. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2697. "vdev %pK created peer %pK (%pM) ref_cnt: %d",
  2698. vdev, peer, peer->mac_addr.raw,
  2699. qdf_atomic_read(&peer->ref_cnt));
  2700. /*
  2701. * For every peer MAp message search and set if bss_peer
  2702. */
  2703. if (memcmp(peer->mac_addr.raw, vdev->mac_addr.raw, 6) == 0) {
  2704. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2705. "vdev bss_peer!!!!");
  2706. peer->bss_peer = 1;
  2707. vdev->vap_bss_peer = peer;
  2708. }
  2709. #ifndef CONFIG_WIN
  2710. dp_local_peer_id_alloc(pdev, peer);
  2711. #endif
  2712. DP_STATS_INIT(peer);
  2713. return (void *)peer;
  2714. }
  2715. /*
  2716. * dp_peer_setup_wifi3() - initialize the peer
  2717. * @vdev_hdl: virtual device object
  2718. * @peer: Peer object
  2719. *
  2720. * Return: void
  2721. */
  2722. static void dp_peer_setup_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  2723. {
  2724. struct dp_peer *peer = (struct dp_peer *)peer_hdl;
  2725. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2726. struct dp_pdev *pdev;
  2727. struct dp_soc *soc;
  2728. bool hash_based = 0;
  2729. enum cdp_host_reo_dest_ring reo_dest;
  2730. /* preconditions */
  2731. qdf_assert(vdev);
  2732. qdf_assert(peer);
  2733. pdev = vdev->pdev;
  2734. soc = pdev->soc;
  2735. dp_peer_rx_init(pdev, peer);
  2736. peer->last_assoc_rcvd = 0;
  2737. peer->last_disassoc_rcvd = 0;
  2738. peer->last_deauth_rcvd = 0;
  2739. /*
  2740. * hash based steering is disabled for Radios which are offloaded
  2741. * to NSS
  2742. */
  2743. if (!wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx))
  2744. hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2745. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2746. FL("hash based steering for pdev: %d is %d\n"),
  2747. pdev->pdev_id, hash_based);
  2748. /*
  2749. * Below line of code will ensure the proper reo_dest ring is choosen
  2750. * for cases where toeplitz hash cannot be generated (ex: non TCP/UDP)
  2751. */
  2752. reo_dest = pdev->reo_dest;
  2753. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  2754. /* TODO: Check the destination ring number to be passed to FW */
  2755. soc->cdp_soc.ol_ops->peer_set_default_routing(
  2756. pdev->osif_pdev, peer->mac_addr.raw,
  2757. peer->vdev->vdev_id, hash_based, reo_dest);
  2758. }
  2759. return;
  2760. }
  2761. /*
  2762. * dp_set_vdev_tx_encap_type() - set the encap type of the vdev
  2763. * @vdev_handle: virtual device object
  2764. * @htt_pkt_type: type of pkt
  2765. *
  2766. * Return: void
  2767. */
  2768. static void dp_set_vdev_tx_encap_type(struct cdp_vdev *vdev_handle,
  2769. enum htt_cmn_pkt_type val)
  2770. {
  2771. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2772. vdev->tx_encap_type = val;
  2773. }
  2774. /*
  2775. * dp_set_vdev_rx_decap_type() - set the decap type of the vdev
  2776. * @vdev_handle: virtual device object
  2777. * @htt_pkt_type: type of pkt
  2778. *
  2779. * Return: void
  2780. */
  2781. static void dp_set_vdev_rx_decap_type(struct cdp_vdev *vdev_handle,
  2782. enum htt_cmn_pkt_type val)
  2783. {
  2784. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2785. vdev->rx_decap_type = val;
  2786. }
  2787. /*
  2788. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  2789. * @pdev_handle: physical device object
  2790. * @val: reo destination ring index (1 - 4)
  2791. *
  2792. * Return: void
  2793. */
  2794. static void dp_set_pdev_reo_dest(struct cdp_pdev *pdev_handle,
  2795. enum cdp_host_reo_dest_ring val)
  2796. {
  2797. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2798. if (pdev)
  2799. pdev->reo_dest = val;
  2800. }
  2801. /*
  2802. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  2803. * @pdev_handle: physical device object
  2804. *
  2805. * Return: reo destination ring index
  2806. */
  2807. static enum cdp_host_reo_dest_ring
  2808. dp_get_pdev_reo_dest(struct cdp_pdev *pdev_handle)
  2809. {
  2810. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2811. if (pdev)
  2812. return pdev->reo_dest;
  2813. else
  2814. return cdp_host_reo_dest_ring_unknown;
  2815. }
  2816. #ifdef QCA_SUPPORT_SON
  2817. static void dp_son_peer_authorize(struct dp_peer *peer)
  2818. {
  2819. struct dp_soc *soc;
  2820. soc = peer->vdev->pdev->soc;
  2821. peer->peer_bs_inact_flag = 0;
  2822. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  2823. return;
  2824. }
  2825. #else
  2826. static void dp_son_peer_authorize(struct dp_peer *peer)
  2827. {
  2828. return;
  2829. }
  2830. #endif
  2831. /*
  2832. * dp_set_filter_neighbour_peers() - set filter neighbour peers for smart mesh
  2833. * @pdev_handle: device object
  2834. * @val: value to be set
  2835. *
  2836. * Return: void
  2837. */
  2838. static int dp_set_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2839. uint32_t val)
  2840. {
  2841. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2842. /* Enable/Disable smart mesh filtering. This flag will be checked
  2843. * during rx processing to check if packets are from NAC clients.
  2844. */
  2845. pdev->filter_neighbour_peers = val;
  2846. return 0;
  2847. }
  2848. /*
  2849. * dp_update_filter_neighbour_peers() - set neighbour peers(nac clients)
  2850. * address for smart mesh filtering
  2851. * @pdev_handle: device object
  2852. * @cmd: Add/Del command
  2853. * @macaddr: nac client mac address
  2854. *
  2855. * Return: void
  2856. */
  2857. static int dp_update_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2858. uint32_t cmd, uint8_t *macaddr)
  2859. {
  2860. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2861. struct dp_neighbour_peer *peer = NULL;
  2862. if (!macaddr)
  2863. goto fail0;
  2864. /* Store address of NAC (neighbour peer) which will be checked
  2865. * against TA of received packets.
  2866. */
  2867. if (cmd == DP_NAC_PARAM_ADD) {
  2868. peer = (struct dp_neighbour_peer *) qdf_mem_malloc(
  2869. sizeof(*peer));
  2870. if (!peer) {
  2871. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2872. FL("DP neighbour peer node memory allocation failed"));
  2873. goto fail0;
  2874. }
  2875. qdf_mem_copy(&peer->neighbour_peers_macaddr.raw[0],
  2876. macaddr, DP_MAC_ADDR_LEN);
  2877. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2878. /* add this neighbour peer into the list */
  2879. TAILQ_INSERT_TAIL(&pdev->neighbour_peers_list, peer,
  2880. neighbour_peer_list_elem);
  2881. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2882. return 1;
  2883. } else if (cmd == DP_NAC_PARAM_DEL) {
  2884. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2885. TAILQ_FOREACH(peer, &pdev->neighbour_peers_list,
  2886. neighbour_peer_list_elem) {
  2887. if (!qdf_mem_cmp(&peer->neighbour_peers_macaddr.raw[0],
  2888. macaddr, DP_MAC_ADDR_LEN)) {
  2889. /* delete this peer from the list */
  2890. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2891. peer, neighbour_peer_list_elem);
  2892. qdf_mem_free(peer);
  2893. break;
  2894. }
  2895. }
  2896. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2897. return 1;
  2898. }
  2899. fail0:
  2900. return 0;
  2901. }
  2902. /*
  2903. * dp_get_sec_type() - Get the security type
  2904. * @peer: Datapath peer handle
  2905. * @sec_idx: Security id (mcast, ucast)
  2906. *
  2907. * return sec_type: Security type
  2908. */
  2909. static int dp_get_sec_type(struct cdp_peer *peer, uint8_t sec_idx)
  2910. {
  2911. struct dp_peer *dpeer = (struct dp_peer *)peer;
  2912. return dpeer->security[sec_idx].sec_type;
  2913. }
  2914. /*
  2915. * dp_peer_authorize() - authorize txrx peer
  2916. * @peer_handle: Datapath peer handle
  2917. * @authorize
  2918. *
  2919. */
  2920. static void dp_peer_authorize(struct cdp_peer *peer_handle, uint32_t authorize)
  2921. {
  2922. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2923. struct dp_soc *soc;
  2924. if (peer != NULL) {
  2925. soc = peer->vdev->pdev->soc;
  2926. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2927. dp_son_peer_authorize(peer);
  2928. peer->authorize = authorize ? 1 : 0;
  2929. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2930. }
  2931. }
  2932. /*
  2933. * dp_peer_unref_delete() - unref and delete peer
  2934. * @peer_handle: Datapath peer handle
  2935. *
  2936. */
  2937. void dp_peer_unref_delete(void *peer_handle)
  2938. {
  2939. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2940. struct dp_vdev *vdev = peer->vdev;
  2941. struct dp_pdev *pdev = vdev->pdev;
  2942. struct dp_soc *soc = pdev->soc;
  2943. struct dp_peer *tmppeer;
  2944. int found = 0;
  2945. uint16_t peer_id;
  2946. /*
  2947. * Hold the lock all the way from checking if the peer ref count
  2948. * is zero until the peer references are removed from the hash
  2949. * table and vdev list (if the peer ref count is zero).
  2950. * This protects against a new HL tx operation starting to use the
  2951. * peer object just after this function concludes it's done being used.
  2952. * Furthermore, the lock needs to be held while checking whether the
  2953. * vdev's list of peers is empty, to make sure that list is not modified
  2954. * concurrently with the empty check.
  2955. */
  2956. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2957. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2958. "%s: peer %pK ref_cnt(before decrement): %d\n", __func__,
  2959. peer, qdf_atomic_read(&peer->ref_cnt));
  2960. if (qdf_atomic_dec_and_test(&peer->ref_cnt)) {
  2961. peer_id = peer->peer_ids[0];
  2962. /*
  2963. * Make sure that the reference to the peer in
  2964. * peer object map is removed
  2965. */
  2966. if (peer_id != HTT_INVALID_PEER)
  2967. soc->peer_id_to_obj_map[peer_id] = NULL;
  2968. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2969. "Deleting peer %pK (%pM)", peer, peer->mac_addr.raw);
  2970. /* remove the reference to the peer from the hash table */
  2971. dp_peer_find_hash_remove(soc, peer);
  2972. TAILQ_FOREACH(tmppeer, &peer->vdev->peer_list, peer_list_elem) {
  2973. if (tmppeer == peer) {
  2974. found = 1;
  2975. break;
  2976. }
  2977. }
  2978. if (found) {
  2979. TAILQ_REMOVE(&peer->vdev->peer_list, peer,
  2980. peer_list_elem);
  2981. } else {
  2982. /*Ignoring the remove operation as peer not found*/
  2983. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2984. "peer %pK not found in vdev (%pK)->peer_list:%pK",
  2985. peer, vdev, &peer->vdev->peer_list);
  2986. }
  2987. /* cleanup the peer data */
  2988. dp_peer_cleanup(vdev, peer);
  2989. /* check whether the parent vdev has no peers left */
  2990. if (TAILQ_EMPTY(&vdev->peer_list)) {
  2991. /*
  2992. * Now that there are no references to the peer, we can
  2993. * release the peer reference lock.
  2994. */
  2995. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2996. /*
  2997. * Check if the parent vdev was waiting for its peers
  2998. * to be deleted, in order for it to be deleted too.
  2999. */
  3000. if (vdev->delete.pending) {
  3001. ol_txrx_vdev_delete_cb vdev_delete_cb =
  3002. vdev->delete.callback;
  3003. void *vdev_delete_context =
  3004. vdev->delete.context;
  3005. QDF_TRACE(QDF_MODULE_ID_DP,
  3006. QDF_TRACE_LEVEL_INFO_HIGH,
  3007. FL("deleting vdev object %pK (%pM)"
  3008. " - its last peer is done"),
  3009. vdev, vdev->mac_addr.raw);
  3010. /* all peers are gone, go ahead and delete it */
  3011. qdf_mem_free(vdev);
  3012. if (vdev_delete_cb)
  3013. vdev_delete_cb(vdev_delete_context);
  3014. }
  3015. } else {
  3016. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  3017. }
  3018. #ifdef notyet
  3019. qdf_mempool_free(soc->osdev, soc->mempool_ol_ath_peer, peer);
  3020. #else
  3021. qdf_mem_free(peer);
  3022. #endif
  3023. if (soc->cdp_soc.ol_ops->peer_unref_delete) {
  3024. soc->cdp_soc.ol_ops->peer_unref_delete(pdev->osif_pdev,
  3025. vdev->vdev_id, peer->mac_addr.raw);
  3026. }
  3027. } else {
  3028. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  3029. }
  3030. }
  3031. /*
  3032. * dp_peer_detach_wifi3() – Detach txrx peer
  3033. * @peer_handle: Datapath peer handle
  3034. *
  3035. */
  3036. static void dp_peer_delete_wifi3(void *peer_handle)
  3037. {
  3038. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  3039. /* redirect the peer's rx delivery function to point to a
  3040. * discard func
  3041. */
  3042. peer->rx_opt_proc = dp_rx_discard;
  3043. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  3044. FL("peer %pK (%pM)"), peer, peer->mac_addr.raw);
  3045. #ifndef CONFIG_WIN
  3046. dp_local_peer_id_free(peer->vdev->pdev, peer);
  3047. #endif
  3048. qdf_spinlock_destroy(&peer->peer_info_lock);
  3049. /*
  3050. * Remove the reference added during peer_attach.
  3051. * The peer will still be left allocated until the
  3052. * PEER_UNMAP message arrives to remove the other
  3053. * reference, added by the PEER_MAP message.
  3054. */
  3055. dp_peer_unref_delete(peer_handle);
  3056. }
  3057. /*
  3058. * dp_get_vdev_mac_addr_wifi3() – Detach txrx peer
  3059. * @peer_handle: Datapath peer handle
  3060. *
  3061. */
  3062. static uint8 *dp_get_vdev_mac_addr_wifi3(struct cdp_vdev *pvdev)
  3063. {
  3064. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  3065. return vdev->mac_addr.raw;
  3066. }
  3067. /*
  3068. * dp_vdev_set_wds() - Enable per packet stats
  3069. * @vdev_handle: DP VDEV handle
  3070. * @val: value
  3071. *
  3072. * Return: none
  3073. */
  3074. static int dp_vdev_set_wds(void *vdev_handle, uint32_t val)
  3075. {
  3076. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3077. vdev->wds_enabled = val;
  3078. return 0;
  3079. }
  3080. /*
  3081. * dp_get_vdev_from_vdev_id_wifi3() – Detach txrx peer
  3082. * @peer_handle: Datapath peer handle
  3083. *
  3084. */
  3085. static struct cdp_vdev *dp_get_vdev_from_vdev_id_wifi3(struct cdp_pdev *dev,
  3086. uint8_t vdev_id)
  3087. {
  3088. struct dp_pdev *pdev = (struct dp_pdev *)dev;
  3089. struct dp_vdev *vdev = NULL;
  3090. if (qdf_unlikely(!pdev))
  3091. return NULL;
  3092. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3093. if (vdev->vdev_id == vdev_id)
  3094. break;
  3095. }
  3096. return (struct cdp_vdev *)vdev;
  3097. }
  3098. static int dp_get_opmode(struct cdp_vdev *vdev_handle)
  3099. {
  3100. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3101. return vdev->opmode;
  3102. }
  3103. static struct cdp_cfg *dp_get_ctrl_pdev_from_vdev_wifi3(struct cdp_vdev *pvdev)
  3104. {
  3105. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  3106. struct dp_pdev *pdev = vdev->pdev;
  3107. return (struct cdp_cfg *)pdev->wlan_cfg_ctx;
  3108. }
  3109. /**
  3110. * dp_reset_monitor_mode() - Disable monitor mode
  3111. * @pdev_handle: Datapath PDEV handle
  3112. *
  3113. * Return: 0 on success, not 0 on failure
  3114. */
  3115. static int dp_reset_monitor_mode(struct cdp_pdev *pdev_handle)
  3116. {
  3117. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3118. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3119. struct dp_soc *soc;
  3120. uint8_t pdev_id;
  3121. pdev_id = pdev->pdev_id;
  3122. soc = pdev->soc;
  3123. pdev->monitor_vdev = NULL;
  3124. qdf_mem_set(&(htt_tlv_filter), sizeof(htt_tlv_filter), 0x0);
  3125. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3126. pdev->rxdma_mon_buf_ring.hal_srng,
  3127. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3128. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3129. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3130. RX_BUFFER_SIZE, &htt_tlv_filter);
  3131. return 0;
  3132. }
  3133. /**
  3134. * dp_vdev_set_monitor_mode() - Set DP VDEV to monitor mode
  3135. * @vdev_handle: Datapath VDEV handle
  3136. * @smart_monitor: Flag to denote if its smart monitor mode
  3137. *
  3138. * Return: 0 on success, not 0 on failure
  3139. */
  3140. static int dp_vdev_set_monitor_mode(struct cdp_vdev *vdev_handle,
  3141. uint8_t smart_monitor)
  3142. {
  3143. /* Many monitor VAPs can exists in a system but only one can be up at
  3144. * anytime
  3145. */
  3146. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3147. struct dp_pdev *pdev;
  3148. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3149. struct dp_soc *soc;
  3150. uint8_t pdev_id;
  3151. qdf_assert(vdev);
  3152. pdev = vdev->pdev;
  3153. pdev_id = pdev->pdev_id;
  3154. soc = pdev->soc;
  3155. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  3156. "pdev=%pK, pdev_id=%d, soc=%pK vdev=%pK\n",
  3157. pdev, pdev_id, soc, vdev);
  3158. /*Check if current pdev's monitor_vdev exists */
  3159. if (pdev->monitor_vdev) {
  3160. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3161. "vdev=%pK\n", vdev);
  3162. qdf_assert(vdev);
  3163. }
  3164. pdev->monitor_vdev = vdev;
  3165. /* If smart monitor mode, do not configure monitor ring */
  3166. if (smart_monitor)
  3167. return QDF_STATUS_SUCCESS;
  3168. htt_tlv_filter.mpdu_start = 1;
  3169. htt_tlv_filter.msdu_start = 1;
  3170. htt_tlv_filter.packet = 1;
  3171. htt_tlv_filter.msdu_end = 1;
  3172. htt_tlv_filter.mpdu_end = 1;
  3173. htt_tlv_filter.packet_header = 1;
  3174. htt_tlv_filter.attention = 1;
  3175. htt_tlv_filter.ppdu_start = 0;
  3176. htt_tlv_filter.ppdu_end = 0;
  3177. htt_tlv_filter.ppdu_end_user_stats = 0;
  3178. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  3179. htt_tlv_filter.ppdu_end_status_done = 0;
  3180. htt_tlv_filter.header_per_msdu = 1;
  3181. htt_tlv_filter.enable_fp = 1;
  3182. htt_tlv_filter.enable_md = 0;
  3183. htt_tlv_filter.enable_mo = 1;
  3184. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3185. pdev->rxdma_mon_buf_ring.hal_srng,
  3186. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3187. htt_tlv_filter.mpdu_start = 1;
  3188. htt_tlv_filter.msdu_start = 1;
  3189. htt_tlv_filter.packet = 0;
  3190. htt_tlv_filter.msdu_end = 1;
  3191. htt_tlv_filter.mpdu_end = 1;
  3192. htt_tlv_filter.packet_header = 1;
  3193. htt_tlv_filter.attention = 1;
  3194. htt_tlv_filter.ppdu_start = 1;
  3195. htt_tlv_filter.ppdu_end = 1;
  3196. htt_tlv_filter.ppdu_end_user_stats = 1;
  3197. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3198. htt_tlv_filter.ppdu_end_status_done = 1;
  3199. htt_tlv_filter.header_per_msdu = 0;
  3200. htt_tlv_filter.enable_fp = 1;
  3201. htt_tlv_filter.enable_md = 0;
  3202. htt_tlv_filter.enable_mo = 1;
  3203. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3204. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3205. RX_BUFFER_SIZE, &htt_tlv_filter);
  3206. return QDF_STATUS_SUCCESS;
  3207. }
  3208. #ifdef MESH_MODE_SUPPORT
  3209. void dp_peer_set_mesh_mode(struct cdp_vdev *vdev_hdl, uint32_t val)
  3210. {
  3211. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3212. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3213. FL("val %d"), val);
  3214. vdev->mesh_vdev = val;
  3215. }
  3216. /*
  3217. * dp_peer_set_mesh_rx_filter() - to set the mesh rx filter
  3218. * @vdev_hdl: virtual device object
  3219. * @val: value to be set
  3220. *
  3221. * Return: void
  3222. */
  3223. void dp_peer_set_mesh_rx_filter(struct cdp_vdev *vdev_hdl, uint32_t val)
  3224. {
  3225. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3226. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3227. FL("val %d"), val);
  3228. vdev->mesh_rx_filter = val;
  3229. }
  3230. #endif
  3231. /**
  3232. * dp_aggregate_vdev_stats(): Consolidate stats at VDEV level
  3233. * @vdev: DP VDEV handle
  3234. *
  3235. * return: void
  3236. */
  3237. void dp_aggregate_vdev_stats(struct dp_vdev *vdev)
  3238. {
  3239. struct dp_peer *peer = NULL;
  3240. struct dp_soc *soc = vdev->pdev->soc;
  3241. int i;
  3242. uint8_t pream_type;
  3243. qdf_mem_set(&(vdev->stats.tx), sizeof(vdev->stats.tx), 0x0);
  3244. qdf_mem_set(&(vdev->stats.rx), sizeof(vdev->stats.rx), 0x0);
  3245. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3246. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3247. for (i = 0; i < MAX_MCS; i++) {
  3248. DP_STATS_AGGR(vdev, peer,
  3249. tx.pkt_type[pream_type].mcs_count[i]);
  3250. DP_STATS_AGGR(vdev, peer,
  3251. rx.pkt_type[pream_type].mcs_count[i]);
  3252. }
  3253. }
  3254. for (i = 0; i < MAX_BW; i++) {
  3255. DP_STATS_AGGR(vdev, peer, tx.bw[i]);
  3256. DP_STATS_AGGR(vdev, peer, rx.bw[i]);
  3257. }
  3258. for (i = 0; i < SS_COUNT; i++)
  3259. DP_STATS_AGGR(vdev, peer, rx.nss[i]);
  3260. for (i = 0; i < WME_AC_MAX; i++) {
  3261. DP_STATS_AGGR(vdev, peer, tx.wme_ac_type[i]);
  3262. DP_STATS_AGGR(vdev, peer, rx.wme_ac_type[i]);
  3263. DP_STATS_AGGR(vdev, peer, tx.excess_retries_ac[i]);
  3264. }
  3265. for (i = 0; i < MAX_GI; i++) {
  3266. DP_STATS_AGGR(vdev, peer, tx.sgi_count[i]);
  3267. DP_STATS_AGGR(vdev, peer, rx.sgi_count[i]);
  3268. }
  3269. DP_STATS_AGGR_PKT(vdev, peer, tx.comp_pkt);
  3270. DP_STATS_AGGR_PKT(vdev, peer, tx.ucast);
  3271. DP_STATS_AGGR_PKT(vdev, peer, tx.mcast);
  3272. DP_STATS_AGGR_PKT(vdev, peer, tx.tx_success);
  3273. DP_STATS_AGGR(vdev, peer, tx.tx_failed);
  3274. DP_STATS_AGGR(vdev, peer, tx.ofdma);
  3275. DP_STATS_AGGR(vdev, peer, tx.stbc);
  3276. DP_STATS_AGGR(vdev, peer, tx.ldpc);
  3277. DP_STATS_AGGR(vdev, peer, tx.retries);
  3278. DP_STATS_AGGR(vdev, peer, tx.non_amsdu_cnt);
  3279. DP_STATS_AGGR(vdev, peer, tx.amsdu_cnt);
  3280. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem);
  3281. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_tx);
  3282. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_notx);
  3283. DP_STATS_AGGR(vdev, peer, tx.dropped.age_out);
  3284. DP_STATS_AGGR(vdev, peer, rx.err.mic_err);
  3285. DP_STATS_AGGR(vdev, peer, rx.err.decrypt_err);
  3286. DP_STATS_AGGR(vdev, peer, rx.non_ampdu_cnt);
  3287. DP_STATS_AGGR(vdev, peer, rx.ampdu_cnt);
  3288. DP_STATS_AGGR(vdev, peer, rx.non_amsdu_cnt);
  3289. DP_STATS_AGGR(vdev, peer, rx.amsdu_cnt);
  3290. DP_STATS_AGGR_PKT(vdev, peer, rx.to_stack);
  3291. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  3292. DP_STATS_AGGR_PKT(vdev, peer, rx.rcvd_reo[i]);
  3293. peer->stats.rx.unicast.num = peer->stats.rx.to_stack.num -
  3294. peer->stats.rx.multicast.num;
  3295. peer->stats.rx.unicast.bytes = peer->stats.rx.to_stack.bytes -
  3296. peer->stats.rx.multicast.bytes;
  3297. DP_STATS_AGGR_PKT(vdev, peer, rx.unicast);
  3298. DP_STATS_AGGR_PKT(vdev, peer, rx.multicast);
  3299. DP_STATS_AGGR_PKT(vdev, peer, rx.wds);
  3300. DP_STATS_AGGR_PKT(vdev, peer, rx.raw);
  3301. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.pkts);
  3302. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.fail);
  3303. vdev->stats.tx.last_ack_rssi =
  3304. peer->stats.tx.last_ack_rssi;
  3305. }
  3306. if (soc->cdp_soc.ol_ops->update_dp_stats)
  3307. soc->cdp_soc.ol_ops->update_dp_stats(vdev->pdev->osif_pdev,
  3308. &vdev->stats, vdev->vdev_id, UPDATE_VDEV_STATS);
  3309. }
  3310. /**
  3311. * dp_aggregate_pdev_stats(): Consolidate stats at PDEV level
  3312. * @pdev: DP PDEV handle
  3313. *
  3314. * return: void
  3315. */
  3316. static inline void dp_aggregate_pdev_stats(struct dp_pdev *pdev)
  3317. {
  3318. struct dp_vdev *vdev = NULL;
  3319. uint8_t i;
  3320. uint8_t pream_type;
  3321. qdf_mem_set(&(pdev->stats.tx), sizeof(pdev->stats.tx), 0x0);
  3322. qdf_mem_set(&(pdev->stats.rx), sizeof(pdev->stats.rx), 0x0);
  3323. qdf_mem_set(&(pdev->stats.tx_i), sizeof(pdev->stats.tx_i), 0x0);
  3324. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3325. dp_aggregate_vdev_stats(vdev);
  3326. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3327. for (i = 0; i < MAX_MCS; i++) {
  3328. DP_STATS_AGGR(pdev, vdev,
  3329. tx.pkt_type[pream_type].mcs_count[i]);
  3330. DP_STATS_AGGR(pdev, vdev,
  3331. rx.pkt_type[pream_type].mcs_count[i]);
  3332. }
  3333. }
  3334. for (i = 0; i < MAX_BW; i++) {
  3335. DP_STATS_AGGR(pdev, vdev, tx.bw[i]);
  3336. DP_STATS_AGGR(pdev, vdev, rx.bw[i]);
  3337. }
  3338. for (i = 0; i < SS_COUNT; i++)
  3339. DP_STATS_AGGR(pdev, vdev, rx.nss[i]);
  3340. for (i = 0; i < WME_AC_MAX; i++) {
  3341. DP_STATS_AGGR(pdev, vdev, tx.wme_ac_type[i]);
  3342. DP_STATS_AGGR(pdev, vdev, rx.wme_ac_type[i]);
  3343. DP_STATS_AGGR(pdev, vdev,
  3344. tx.excess_retries_ac[i]);
  3345. }
  3346. for (i = 0; i < MAX_GI; i++) {
  3347. DP_STATS_AGGR(pdev, vdev, tx.sgi_count[i]);
  3348. DP_STATS_AGGR(pdev, vdev, rx.sgi_count[i]);
  3349. }
  3350. DP_STATS_AGGR_PKT(pdev, vdev, tx.comp_pkt);
  3351. DP_STATS_AGGR_PKT(pdev, vdev, tx.ucast);
  3352. DP_STATS_AGGR_PKT(pdev, vdev, tx.mcast);
  3353. DP_STATS_AGGR_PKT(pdev, vdev, tx.tx_success);
  3354. DP_STATS_AGGR(pdev, vdev, tx.tx_failed);
  3355. DP_STATS_AGGR(pdev, vdev, tx.ofdma);
  3356. DP_STATS_AGGR(pdev, vdev, tx.stbc);
  3357. DP_STATS_AGGR(pdev, vdev, tx.ldpc);
  3358. DP_STATS_AGGR(pdev, vdev, tx.retries);
  3359. DP_STATS_AGGR(pdev, vdev, tx.non_amsdu_cnt);
  3360. DP_STATS_AGGR(pdev, vdev, tx.amsdu_cnt);
  3361. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem);
  3362. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_tx);
  3363. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_notx);
  3364. DP_STATS_AGGR(pdev, vdev, tx.dropped.age_out);
  3365. DP_STATS_AGGR(pdev, vdev, rx.err.mic_err);
  3366. DP_STATS_AGGR(pdev, vdev, rx.err.decrypt_err);
  3367. DP_STATS_AGGR(pdev, vdev, rx.non_ampdu_cnt);
  3368. DP_STATS_AGGR(pdev, vdev, rx.ampdu_cnt);
  3369. DP_STATS_AGGR(pdev, vdev, rx.non_amsdu_cnt);
  3370. DP_STATS_AGGR(pdev, vdev, rx.amsdu_cnt);
  3371. DP_STATS_AGGR_PKT(pdev, vdev, rx.to_stack);
  3372. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[0]);
  3373. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[1]);
  3374. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[2]);
  3375. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[3]);
  3376. DP_STATS_AGGR_PKT(pdev, vdev, rx.unicast);
  3377. DP_STATS_AGGR_PKT(pdev, vdev, rx.multicast);
  3378. DP_STATS_AGGR_PKT(pdev, vdev, rx.wds);
  3379. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.pkts);
  3380. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.fail);
  3381. DP_STATS_AGGR_PKT(pdev, vdev, rx.raw);
  3382. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.rcvd);
  3383. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.processed);
  3384. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.reinject_pkts);
  3385. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.inspect_pkts);
  3386. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.raw.raw_pkt);
  3387. DP_STATS_AGGR(pdev, vdev, tx_i.raw.dma_map_error);
  3388. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.tso.tso_pkt);
  3389. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_host);
  3390. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_target);
  3391. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_host);
  3392. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_target);
  3393. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.sg.sg_pkt);
  3394. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.mcast_en.mcast_pkt);
  3395. DP_STATS_AGGR(pdev, vdev,
  3396. tx_i.mcast_en.dropped_map_error);
  3397. DP_STATS_AGGR(pdev, vdev,
  3398. tx_i.mcast_en.dropped_self_mac);
  3399. DP_STATS_AGGR(pdev, vdev,
  3400. tx_i.mcast_en.dropped_send_fail);
  3401. DP_STATS_AGGR(pdev, vdev, tx_i.mcast_en.ucast);
  3402. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.dma_error);
  3403. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.ring_full);
  3404. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.enqueue_fail);
  3405. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.desc_na);
  3406. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.res_full);
  3407. pdev->stats.tx_i.dropped.dropped_pkt.num =
  3408. pdev->stats.tx_i.dropped.dma_error +
  3409. pdev->stats.tx_i.dropped.ring_full +
  3410. pdev->stats.tx_i.dropped.enqueue_fail +
  3411. pdev->stats.tx_i.dropped.desc_na +
  3412. pdev->stats.tx_i.dropped.res_full;
  3413. pdev->stats.tx.last_ack_rssi =
  3414. vdev->stats.tx.last_ack_rssi;
  3415. pdev->stats.tx_i.tso.num_seg =
  3416. vdev->stats.tx_i.tso.num_seg;
  3417. }
  3418. }
  3419. /**
  3420. * dp_print_pdev_tx_stats(): Print Pdev level TX stats
  3421. * @pdev: DP_PDEV Handle
  3422. *
  3423. * Return:void
  3424. */
  3425. static inline void
  3426. dp_print_pdev_tx_stats(struct dp_pdev *pdev)
  3427. {
  3428. DP_PRINT_STATS("PDEV Tx Stats:\n");
  3429. DP_PRINT_STATS("Received From Stack:");
  3430. DP_PRINT_STATS(" Packets = %d",
  3431. pdev->stats.tx_i.rcvd.num);
  3432. DP_PRINT_STATS(" Bytes = %d",
  3433. pdev->stats.tx_i.rcvd.bytes);
  3434. DP_PRINT_STATS("Processed:");
  3435. DP_PRINT_STATS(" Packets = %d",
  3436. pdev->stats.tx_i.processed.num);
  3437. DP_PRINT_STATS(" Bytes = %d",
  3438. pdev->stats.tx_i.processed.bytes);
  3439. DP_PRINT_STATS("Completions:");
  3440. DP_PRINT_STATS(" Packets = %d",
  3441. pdev->stats.tx.comp_pkt.num);
  3442. DP_PRINT_STATS(" Bytes = %d",
  3443. pdev->stats.tx.comp_pkt.bytes);
  3444. DP_PRINT_STATS("Dropped:");
  3445. DP_PRINT_STATS(" Total = %d",
  3446. pdev->stats.tx_i.dropped.dropped_pkt.num);
  3447. DP_PRINT_STATS(" Dma_map_error = %d",
  3448. pdev->stats.tx_i.dropped.dma_error);
  3449. DP_PRINT_STATS(" Ring Full = %d",
  3450. pdev->stats.tx_i.dropped.ring_full);
  3451. DP_PRINT_STATS(" Descriptor Not available = %d",
  3452. pdev->stats.tx_i.dropped.desc_na);
  3453. DP_PRINT_STATS(" HW enqueue failed= %d",
  3454. pdev->stats.tx_i.dropped.enqueue_fail);
  3455. DP_PRINT_STATS(" Resources Full = %d",
  3456. pdev->stats.tx_i.dropped.res_full);
  3457. DP_PRINT_STATS(" FW removed = %d",
  3458. pdev->stats.tx.dropped.fw_rem);
  3459. DP_PRINT_STATS(" FW removed transmitted = %d",
  3460. pdev->stats.tx.dropped.fw_rem_tx);
  3461. DP_PRINT_STATS(" FW removed untransmitted = %d",
  3462. pdev->stats.tx.dropped.fw_rem_notx);
  3463. DP_PRINT_STATS(" Aged Out from msdu/mpdu queues = %d",
  3464. pdev->stats.tx.dropped.age_out);
  3465. DP_PRINT_STATS("Scatter Gather:");
  3466. DP_PRINT_STATS(" Packets = %d",
  3467. pdev->stats.tx_i.sg.sg_pkt.num);
  3468. DP_PRINT_STATS(" Bytes = %d",
  3469. pdev->stats.tx_i.sg.sg_pkt.bytes);
  3470. DP_PRINT_STATS(" Dropped By Host = %d",
  3471. pdev->stats.tx_i.sg.dropped_host);
  3472. DP_PRINT_STATS(" Dropped By Target = %d",
  3473. pdev->stats.tx_i.sg.dropped_target);
  3474. DP_PRINT_STATS("TSO:");
  3475. DP_PRINT_STATS(" Number of Segments = %d",
  3476. pdev->stats.tx_i.tso.num_seg);
  3477. DP_PRINT_STATS(" Packets = %d",
  3478. pdev->stats.tx_i.tso.tso_pkt.num);
  3479. DP_PRINT_STATS(" Bytes = %d",
  3480. pdev->stats.tx_i.tso.tso_pkt.bytes);
  3481. DP_PRINT_STATS(" Dropped By Host = %d",
  3482. pdev->stats.tx_i.tso.dropped_host);
  3483. DP_PRINT_STATS("Mcast Enhancement:");
  3484. DP_PRINT_STATS(" Packets = %d",
  3485. pdev->stats.tx_i.mcast_en.mcast_pkt.num);
  3486. DP_PRINT_STATS(" Bytes = %d",
  3487. pdev->stats.tx_i.mcast_en.mcast_pkt.bytes);
  3488. DP_PRINT_STATS(" Dropped: Map Errors = %d",
  3489. pdev->stats.tx_i.mcast_en.dropped_map_error);
  3490. DP_PRINT_STATS(" Dropped: Self Mac = %d",
  3491. pdev->stats.tx_i.mcast_en.dropped_self_mac);
  3492. DP_PRINT_STATS(" Dropped: Send Fail = %d",
  3493. pdev->stats.tx_i.mcast_en.dropped_send_fail);
  3494. DP_PRINT_STATS(" Unicast sent = %d",
  3495. pdev->stats.tx_i.mcast_en.ucast);
  3496. DP_PRINT_STATS("Raw:");
  3497. DP_PRINT_STATS(" Packets = %d",
  3498. pdev->stats.tx_i.raw.raw_pkt.num);
  3499. DP_PRINT_STATS(" Bytes = %d",
  3500. pdev->stats.tx_i.raw.raw_pkt.bytes);
  3501. DP_PRINT_STATS(" DMA map error = %d",
  3502. pdev->stats.tx_i.raw.dma_map_error);
  3503. DP_PRINT_STATS("Reinjected:");
  3504. DP_PRINT_STATS(" Packets = %d",
  3505. pdev->stats.tx_i.reinject_pkts.num);
  3506. DP_PRINT_STATS("Bytes = %d\n",
  3507. pdev->stats.tx_i.reinject_pkts.bytes);
  3508. DP_PRINT_STATS("Inspected:");
  3509. DP_PRINT_STATS(" Packets = %d",
  3510. pdev->stats.tx_i.inspect_pkts.num);
  3511. DP_PRINT_STATS(" Bytes = %d",
  3512. pdev->stats.tx_i.inspect_pkts.bytes);
  3513. }
  3514. /**
  3515. * dp_print_pdev_rx_stats(): Print Pdev level RX stats
  3516. * @pdev: DP_PDEV Handle
  3517. *
  3518. * Return: void
  3519. */
  3520. static inline void
  3521. dp_print_pdev_rx_stats(struct dp_pdev *pdev)
  3522. {
  3523. DP_PRINT_STATS("PDEV Rx Stats:\n");
  3524. DP_PRINT_STATS("Received From HW (Per Rx Ring):");
  3525. DP_PRINT_STATS(" Packets = %d %d %d %d",
  3526. pdev->stats.rx.rcvd_reo[0].num,
  3527. pdev->stats.rx.rcvd_reo[1].num,
  3528. pdev->stats.rx.rcvd_reo[2].num,
  3529. pdev->stats.rx.rcvd_reo[3].num);
  3530. DP_PRINT_STATS(" Bytes = %d %d %d %d",
  3531. pdev->stats.rx.rcvd_reo[0].bytes,
  3532. pdev->stats.rx.rcvd_reo[1].bytes,
  3533. pdev->stats.rx.rcvd_reo[2].bytes,
  3534. pdev->stats.rx.rcvd_reo[3].bytes);
  3535. DP_PRINT_STATS("Replenished:");
  3536. DP_PRINT_STATS(" Packets = %d",
  3537. pdev->stats.replenish.pkts.num);
  3538. DP_PRINT_STATS(" Bytes = %d",
  3539. pdev->stats.replenish.pkts.bytes);
  3540. DP_PRINT_STATS(" Buffers Added To Freelist = %d",
  3541. pdev->stats.buf_freelist);
  3542. DP_PRINT_STATS("Dropped:");
  3543. DP_PRINT_STATS(" msdu_not_done = %d",
  3544. pdev->stats.dropped.msdu_not_done);
  3545. DP_PRINT_STATS("Sent To Stack:");
  3546. DP_PRINT_STATS(" Packets = %d",
  3547. pdev->stats.rx.to_stack.num);
  3548. DP_PRINT_STATS(" Bytes = %d",
  3549. pdev->stats.rx.to_stack.bytes);
  3550. DP_PRINT_STATS("Multicast/Broadcast:");
  3551. DP_PRINT_STATS(" Packets = %d",
  3552. pdev->stats.rx.multicast.num);
  3553. DP_PRINT_STATS(" Bytes = %d",
  3554. pdev->stats.rx.multicast.bytes);
  3555. DP_PRINT_STATS("Errors:");
  3556. DP_PRINT_STATS(" Rxdma Ring Un-inititalized = %d",
  3557. pdev->stats.replenish.rxdma_err);
  3558. DP_PRINT_STATS(" Desc Alloc Failed: = %d",
  3559. pdev->stats.err.desc_alloc_fail);
  3560. }
  3561. /**
  3562. * dp_print_soc_tx_stats(): Print SOC level stats
  3563. * @soc DP_SOC Handle
  3564. *
  3565. * Return: void
  3566. */
  3567. static inline void
  3568. dp_print_soc_tx_stats(struct dp_soc *soc)
  3569. {
  3570. DP_PRINT_STATS("SOC Tx Stats:\n");
  3571. DP_PRINT_STATS("Tx Descriptors In Use = %d",
  3572. soc->stats.tx.desc_in_use);
  3573. DP_PRINT_STATS("Invalid peer:");
  3574. DP_PRINT_STATS(" Packets = %d",
  3575. soc->stats.tx.tx_invalid_peer.num);
  3576. DP_PRINT_STATS(" Bytes = %d",
  3577. soc->stats.tx.tx_invalid_peer.bytes);
  3578. DP_PRINT_STATS("Packets dropped due to TCL ring full = %d %d %d",
  3579. soc->stats.tx.tcl_ring_full[0],
  3580. soc->stats.tx.tcl_ring_full[1],
  3581. soc->stats.tx.tcl_ring_full[2]);
  3582. }
  3583. /**
  3584. * dp_print_soc_rx_stats: Print SOC level Rx stats
  3585. * @soc: DP_SOC Handle
  3586. *
  3587. * Return:void
  3588. */
  3589. static inline void
  3590. dp_print_soc_rx_stats(struct dp_soc *soc)
  3591. {
  3592. uint32_t i;
  3593. char reo_error[DP_REO_ERR_LENGTH];
  3594. char rxdma_error[DP_RXDMA_ERR_LENGTH];
  3595. uint8_t index = 0;
  3596. DP_PRINT_STATS("SOC Rx Stats:\n");
  3597. DP_PRINT_STATS("Errors:\n");
  3598. DP_PRINT_STATS("Rx Decrypt Errors = %d",
  3599. (soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_DECRYPT] +
  3600. soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_TKIP_MIC]));
  3601. DP_PRINT_STATS("Invalid RBM = %d",
  3602. soc->stats.rx.err.invalid_rbm);
  3603. DP_PRINT_STATS("Invalid Vdev = %d",
  3604. soc->stats.rx.err.invalid_vdev);
  3605. DP_PRINT_STATS("Invalid Pdev = %d",
  3606. soc->stats.rx.err.invalid_pdev);
  3607. DP_PRINT_STATS("Invalid Peer = %d",
  3608. soc->stats.rx.err.rx_invalid_peer.num);
  3609. DP_PRINT_STATS("HAL Ring Access Fail = %d",
  3610. soc->stats.rx.err.hal_ring_access_fail);
  3611. for (i = 0; i < HAL_RXDMA_ERR_MAX; i++) {
  3612. index += qdf_snprint(&rxdma_error[index],
  3613. DP_RXDMA_ERR_LENGTH - index,
  3614. " %d", soc->stats.rx.err.rxdma_error[i]);
  3615. }
  3616. DP_PRINT_STATS("RXDMA Error (0-31):%s",
  3617. rxdma_error);
  3618. index = 0;
  3619. for (i = 0; i < HAL_REO_ERR_MAX; i++) {
  3620. index += qdf_snprint(&reo_error[index],
  3621. DP_REO_ERR_LENGTH - index,
  3622. " %d", soc->stats.rx.err.reo_error[i]);
  3623. }
  3624. DP_PRINT_STATS("REO Error(0-14):%s",
  3625. reo_error);
  3626. }
  3627. /**
  3628. * dp_print_ring_stat_from_hal(): Print hal level ring stats
  3629. * @soc: DP_SOC handle
  3630. * @srng: DP_SRNG handle
  3631. * @ring_name: SRNG name
  3632. *
  3633. * Return: void
  3634. */
  3635. static inline void
  3636. dp_print_ring_stat_from_hal(struct dp_soc *soc, struct dp_srng *srng,
  3637. char *ring_name)
  3638. {
  3639. uint32_t tailp;
  3640. uint32_t headp;
  3641. if (srng->hal_srng != NULL) {
  3642. hal_api_get_tphp(soc->hal_soc, srng->hal_srng, &tailp, &headp);
  3643. DP_PRINT_STATS("%s : Head pointer = %d Tail Pointer = %d\n",
  3644. ring_name, headp, tailp);
  3645. }
  3646. }
  3647. /**
  3648. * dp_print_ring_stats(): Print tail and head pointer
  3649. * @pdev: DP_PDEV handle
  3650. *
  3651. * Return:void
  3652. */
  3653. static inline void
  3654. dp_print_ring_stats(struct dp_pdev *pdev)
  3655. {
  3656. uint32_t i;
  3657. char ring_name[STR_MAXLEN + 1];
  3658. dp_print_ring_stat_from_hal(pdev->soc,
  3659. &pdev->soc->reo_exception_ring,
  3660. "Reo Exception Ring");
  3661. dp_print_ring_stat_from_hal(pdev->soc,
  3662. &pdev->soc->reo_reinject_ring,
  3663. "Reo Inject Ring");
  3664. dp_print_ring_stat_from_hal(pdev->soc,
  3665. &pdev->soc->reo_cmd_ring,
  3666. "Reo Command Ring");
  3667. dp_print_ring_stat_from_hal(pdev->soc,
  3668. &pdev->soc->reo_status_ring,
  3669. "Reo Status Ring");
  3670. dp_print_ring_stat_from_hal(pdev->soc,
  3671. &pdev->soc->rx_rel_ring,
  3672. "Rx Release ring");
  3673. dp_print_ring_stat_from_hal(pdev->soc,
  3674. &pdev->soc->tcl_cmd_ring,
  3675. "Tcl command Ring");
  3676. dp_print_ring_stat_from_hal(pdev->soc,
  3677. &pdev->soc->tcl_status_ring,
  3678. "Tcl Status Ring");
  3679. dp_print_ring_stat_from_hal(pdev->soc,
  3680. &pdev->soc->wbm_desc_rel_ring,
  3681. "Wbm Desc Rel Ring");
  3682. for (i = 0; i < MAX_REO_DEST_RINGS; i++) {
  3683. snprintf(ring_name, STR_MAXLEN, "Reo Dest Ring %d", i);
  3684. dp_print_ring_stat_from_hal(pdev->soc,
  3685. &pdev->soc->reo_dest_ring[i],
  3686. ring_name);
  3687. }
  3688. for (i = 0; i < pdev->soc->num_tcl_data_rings; i++) {
  3689. snprintf(ring_name, STR_MAXLEN, "Tcl Data Ring %d", i);
  3690. dp_print_ring_stat_from_hal(pdev->soc,
  3691. &pdev->soc->tcl_data_ring[i],
  3692. ring_name);
  3693. }
  3694. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  3695. snprintf(ring_name, STR_MAXLEN, "Tx Comp Ring %d", i);
  3696. dp_print_ring_stat_from_hal(pdev->soc,
  3697. &pdev->soc->tx_comp_ring[i],
  3698. ring_name);
  3699. }
  3700. dp_print_ring_stat_from_hal(pdev->soc,
  3701. &pdev->rx_refill_buf_ring,
  3702. "Rx Refill Buf Ring");
  3703. #ifdef IPA_OFFLOAD
  3704. dp_print_ring_stat_from_hal(pdev->soc,
  3705. &pdev->ipa_rx_refill_buf_ring,
  3706. "IPA Rx Refill Buf Ring");
  3707. #endif
  3708. dp_print_ring_stat_from_hal(pdev->soc,
  3709. &pdev->rxdma_mon_buf_ring,
  3710. "Rxdma Mon Buf Ring");
  3711. dp_print_ring_stat_from_hal(pdev->soc,
  3712. &pdev->rxdma_mon_dst_ring,
  3713. "Rxdma Mon Dst Ring");
  3714. dp_print_ring_stat_from_hal(pdev->soc,
  3715. &pdev->rxdma_mon_status_ring,
  3716. "Rxdma Mon Status Ring");
  3717. dp_print_ring_stat_from_hal(pdev->soc,
  3718. &pdev->rxdma_mon_desc_ring,
  3719. "Rxdma mon desc Ring");
  3720. dp_print_ring_stat_from_hal(pdev->soc,
  3721. &pdev->rxdma_err_dst_ring,
  3722. "Rxdma err dst ring");
  3723. for (i = 0; i < MAX_RX_MAC_RINGS; i++) {
  3724. snprintf(ring_name, STR_MAXLEN, "Rx mac buf ring %d", i);
  3725. dp_print_ring_stat_from_hal(pdev->soc,
  3726. &pdev->rx_mac_buf_ring[i],
  3727. ring_name);
  3728. }
  3729. }
  3730. /**
  3731. * dp_txrx_host_stats_clr(): Reinitialize the txrx stats
  3732. * @vdev: DP_VDEV handle
  3733. *
  3734. * Return:void
  3735. */
  3736. static inline void
  3737. dp_txrx_host_stats_clr(struct dp_vdev *vdev)
  3738. {
  3739. struct dp_peer *peer = NULL;
  3740. DP_STATS_CLR(vdev->pdev);
  3741. DP_STATS_CLR(vdev->pdev->soc);
  3742. DP_STATS_CLR(vdev);
  3743. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3744. if (!peer)
  3745. return;
  3746. DP_STATS_CLR(peer);
  3747. }
  3748. }
  3749. /**
  3750. * dp_print_rx_rates(): Print Rx rate stats
  3751. * @vdev: DP_VDEV handle
  3752. *
  3753. * Return:void
  3754. */
  3755. static inline void
  3756. dp_print_rx_rates(struct dp_vdev *vdev)
  3757. {
  3758. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3759. uint8_t i, mcs, pkt_type;
  3760. uint8_t index = 0;
  3761. char nss[DP_NSS_LENGTH];
  3762. DP_PRINT_STATS("Rx Rate Info:\n");
  3763. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3764. index = 0;
  3765. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3766. if (!dp_rate_string[pkt_type][mcs].valid)
  3767. continue;
  3768. DP_PRINT_STATS(" %s = %d",
  3769. dp_rate_string[pkt_type][mcs].mcs_type,
  3770. pdev->stats.rx.pkt_type[pkt_type].
  3771. mcs_count[mcs]);
  3772. }
  3773. DP_PRINT_STATS("\n");
  3774. }
  3775. index = 0;
  3776. for (i = 0; i < SS_COUNT; i++) {
  3777. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3778. " %d", pdev->stats.rx.nss[i]);
  3779. }
  3780. DP_PRINT_STATS("NSS(0-7) = %s",
  3781. nss);
  3782. DP_PRINT_STATS("SGI ="
  3783. " 0.8us %d,"
  3784. " 0.4us %d,"
  3785. " 1.6us %d,"
  3786. " 3.2us %d,",
  3787. pdev->stats.rx.sgi_count[0],
  3788. pdev->stats.rx.sgi_count[1],
  3789. pdev->stats.rx.sgi_count[2],
  3790. pdev->stats.rx.sgi_count[3]);
  3791. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3792. pdev->stats.rx.bw[0], pdev->stats.rx.bw[1],
  3793. pdev->stats.rx.bw[2], pdev->stats.rx.bw[3]);
  3794. DP_PRINT_STATS("Reception Type ="
  3795. " SU: %d,"
  3796. " MU_MIMO:%d,"
  3797. " MU_OFDMA:%d,"
  3798. " MU_OFDMA_MIMO:%d\n",
  3799. pdev->stats.rx.reception_type[0],
  3800. pdev->stats.rx.reception_type[1],
  3801. pdev->stats.rx.reception_type[2],
  3802. pdev->stats.rx.reception_type[3]);
  3803. DP_PRINT_STATS("Aggregation:\n");
  3804. DP_PRINT_STATS("Number of Msdu's Part of Ampdus = %d",
  3805. pdev->stats.rx.ampdu_cnt);
  3806. DP_PRINT_STATS("Number of Msdu's With No Mpdu Level Aggregation : %d",
  3807. pdev->stats.rx.non_ampdu_cnt);
  3808. DP_PRINT_STATS("Number of Msdu's Part of Amsdu: %d",
  3809. pdev->stats.rx.amsdu_cnt);
  3810. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation: %d",
  3811. pdev->stats.rx.non_amsdu_cnt);
  3812. }
  3813. /**
  3814. * dp_print_tx_rates(): Print tx rates
  3815. * @vdev: DP_VDEV handle
  3816. *
  3817. * Return:void
  3818. */
  3819. static inline void
  3820. dp_print_tx_rates(struct dp_vdev *vdev)
  3821. {
  3822. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3823. uint8_t mcs, pkt_type;
  3824. uint32_t index;
  3825. DP_PRINT_STATS("Tx Rate Info:\n");
  3826. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3827. index = 0;
  3828. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3829. if (!dp_rate_string[pkt_type][mcs].valid)
  3830. continue;
  3831. DP_PRINT_STATS(" %s = %d",
  3832. dp_rate_string[pkt_type][mcs].mcs_type,
  3833. pdev->stats.tx.pkt_type[pkt_type].
  3834. mcs_count[mcs]);
  3835. }
  3836. DP_PRINT_STATS("\n");
  3837. }
  3838. DP_PRINT_STATS("SGI ="
  3839. " 0.8us %d"
  3840. " 0.4us %d"
  3841. " 1.6us %d"
  3842. " 3.2us %d",
  3843. pdev->stats.tx.sgi_count[0],
  3844. pdev->stats.tx.sgi_count[1],
  3845. pdev->stats.tx.sgi_count[2],
  3846. pdev->stats.tx.sgi_count[3]);
  3847. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3848. pdev->stats.tx.bw[0], pdev->stats.tx.bw[1],
  3849. pdev->stats.tx.bw[2], pdev->stats.tx.bw[3]);
  3850. DP_PRINT_STATS("OFDMA = %d", pdev->stats.tx.ofdma);
  3851. DP_PRINT_STATS("STBC = %d", pdev->stats.tx.stbc);
  3852. DP_PRINT_STATS("LDPC = %d", pdev->stats.tx.ldpc);
  3853. DP_PRINT_STATS("Retries = %d", pdev->stats.tx.retries);
  3854. DP_PRINT_STATS("Last ack rssi = %d\n", pdev->stats.tx.last_ack_rssi);
  3855. DP_PRINT_STATS("Aggregation:\n");
  3856. DP_PRINT_STATS("Number of Msdu's Part of Amsdu = %d",
  3857. pdev->stats.tx.amsdu_cnt);
  3858. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation = %d",
  3859. pdev->stats.tx.non_amsdu_cnt);
  3860. }
  3861. /**
  3862. * dp_print_peer_stats():print peer stats
  3863. * @peer: DP_PEER handle
  3864. *
  3865. * return void
  3866. */
  3867. static inline void dp_print_peer_stats(struct dp_peer *peer)
  3868. {
  3869. uint8_t i, mcs, pkt_type;
  3870. uint32_t index;
  3871. char nss[DP_NSS_LENGTH];
  3872. DP_PRINT_STATS("Node Tx Stats:\n");
  3873. DP_PRINT_STATS("Total Packet Completions = %d",
  3874. peer->stats.tx.comp_pkt.num);
  3875. DP_PRINT_STATS("Total Bytes Completions = %d",
  3876. peer->stats.tx.comp_pkt.bytes);
  3877. DP_PRINT_STATS("Success Packets = %d",
  3878. peer->stats.tx.tx_success.num);
  3879. DP_PRINT_STATS("Success Bytes = %d",
  3880. peer->stats.tx.tx_success.bytes);
  3881. DP_PRINT_STATS("Packets Failed = %d",
  3882. peer->stats.tx.tx_failed);
  3883. DP_PRINT_STATS("Packets In OFDMA = %d",
  3884. peer->stats.tx.ofdma);
  3885. DP_PRINT_STATS("Packets In STBC = %d",
  3886. peer->stats.tx.stbc);
  3887. DP_PRINT_STATS("Packets In LDPC = %d",
  3888. peer->stats.tx.ldpc);
  3889. DP_PRINT_STATS("Packet Retries = %d",
  3890. peer->stats.tx.retries);
  3891. DP_PRINT_STATS("MSDU's Part of AMSDU = %d",
  3892. peer->stats.tx.amsdu_cnt);
  3893. DP_PRINT_STATS("Last Packet RSSI = %d",
  3894. peer->stats.tx.last_ack_rssi);
  3895. DP_PRINT_STATS("Dropped At FW: Removed = %d",
  3896. peer->stats.tx.dropped.fw_rem);
  3897. DP_PRINT_STATS("Dropped At FW: Removed transmitted = %d",
  3898. peer->stats.tx.dropped.fw_rem_tx);
  3899. DP_PRINT_STATS("Dropped At FW: Removed Untransmitted = %d",
  3900. peer->stats.tx.dropped.fw_rem_notx);
  3901. DP_PRINT_STATS("Dropped : Age Out = %d",
  3902. peer->stats.tx.dropped.age_out);
  3903. DP_PRINT_STATS("Rate Info:");
  3904. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3905. index = 0;
  3906. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3907. if (!dp_rate_string[pkt_type][mcs].valid)
  3908. continue;
  3909. DP_PRINT_STATS(" %s = %d",
  3910. dp_rate_string[pkt_type][mcs].mcs_type,
  3911. peer->stats.tx.pkt_type[pkt_type].
  3912. mcs_count[mcs]);
  3913. }
  3914. DP_PRINT_STATS("\n");
  3915. }
  3916. DP_PRINT_STATS("SGI = "
  3917. " 0.8us %d"
  3918. " 0.4us %d"
  3919. " 1.6us %d"
  3920. " 3.2us %d",
  3921. peer->stats.tx.sgi_count[0],
  3922. peer->stats.tx.sgi_count[1],
  3923. peer->stats.tx.sgi_count[2],
  3924. peer->stats.tx.sgi_count[3]);
  3925. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d\n",
  3926. peer->stats.tx.bw[0], peer->stats.tx.bw[1],
  3927. peer->stats.tx.bw[2], peer->stats.tx.bw[3]);
  3928. DP_PRINT_STATS("Aggregation:");
  3929. DP_PRINT_STATS(" Number of Msdu's Part of Amsdu = %d",
  3930. peer->stats.tx.amsdu_cnt);
  3931. DP_PRINT_STATS(" Number of Msdu's With No Msdu Level Aggregation = %d\n",
  3932. peer->stats.tx.non_amsdu_cnt);
  3933. DP_PRINT_STATS("Node Rx Stats:");
  3934. DP_PRINT_STATS("Packets Sent To Stack = %d",
  3935. peer->stats.rx.to_stack.num);
  3936. DP_PRINT_STATS("Bytes Sent To Stack = %d",
  3937. peer->stats.rx.to_stack.bytes);
  3938. for (i = 0; i < CDP_MAX_RX_RINGS; i++) {
  3939. DP_PRINT_STATS("Packets Received = %d",
  3940. peer->stats.rx.rcvd_reo[i].num);
  3941. DP_PRINT_STATS("Bytes Received = %d",
  3942. peer->stats.rx.rcvd_reo[i].bytes);
  3943. }
  3944. DP_PRINT_STATS("Multicast Packets Received = %d",
  3945. peer->stats.rx.multicast.num);
  3946. DP_PRINT_STATS("Multicast Bytes Received = %d",
  3947. peer->stats.rx.multicast.bytes);
  3948. DP_PRINT_STATS("WDS Packets Received = %d",
  3949. peer->stats.rx.wds.num);
  3950. DP_PRINT_STATS("WDS Bytes Received = %d",
  3951. peer->stats.rx.wds.bytes);
  3952. DP_PRINT_STATS("Intra BSS Packets Received = %d",
  3953. peer->stats.rx.intra_bss.pkts.num);
  3954. DP_PRINT_STATS("Intra BSS Bytes Received = %d",
  3955. peer->stats.rx.intra_bss.pkts.bytes);
  3956. DP_PRINT_STATS("Raw Packets Received = %d",
  3957. peer->stats.rx.raw.num);
  3958. DP_PRINT_STATS("Raw Bytes Received = %d",
  3959. peer->stats.rx.raw.bytes);
  3960. DP_PRINT_STATS("Errors: MIC Errors = %d",
  3961. peer->stats.rx.err.mic_err);
  3962. DP_PRINT_STATS("Erros: Decryption Errors = %d",
  3963. peer->stats.rx.err.decrypt_err);
  3964. DP_PRINT_STATS("Msdu's Received As Part of Ampdu = %d",
  3965. peer->stats.rx.non_ampdu_cnt);
  3966. DP_PRINT_STATS("Msdu's Recived As Ampdu = %d",
  3967. peer->stats.rx.ampdu_cnt);
  3968. DP_PRINT_STATS("Msdu's Received Not Part of Amsdu's = %d",
  3969. peer->stats.rx.non_amsdu_cnt);
  3970. DP_PRINT_STATS("MSDUs Received As Part of Amsdu = %d",
  3971. peer->stats.rx.amsdu_cnt);
  3972. DP_PRINT_STATS("SGI ="
  3973. " 0.8us %d"
  3974. " 0.4us %d"
  3975. " 1.6us %d"
  3976. " 3.2us %d",
  3977. peer->stats.rx.sgi_count[0],
  3978. peer->stats.rx.sgi_count[1],
  3979. peer->stats.rx.sgi_count[2],
  3980. peer->stats.rx.sgi_count[3]);
  3981. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d",
  3982. peer->stats.rx.bw[0], peer->stats.rx.bw[1],
  3983. peer->stats.rx.bw[2], peer->stats.rx.bw[3]);
  3984. DP_PRINT_STATS("Reception Type ="
  3985. " SU %d,"
  3986. " MU_MIMO %d,"
  3987. " MU_OFDMA %d,"
  3988. " MU_OFDMA_MIMO %d",
  3989. peer->stats.rx.reception_type[0],
  3990. peer->stats.rx.reception_type[1],
  3991. peer->stats.rx.reception_type[2],
  3992. peer->stats.rx.reception_type[3]);
  3993. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3994. index = 0;
  3995. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3996. if (!dp_rate_string[pkt_type][mcs].valid)
  3997. continue;
  3998. DP_PRINT_STATS(" %s = %d",
  3999. dp_rate_string[pkt_type][mcs].mcs_type,
  4000. peer->stats.rx.pkt_type[pkt_type].
  4001. mcs_count[mcs]);
  4002. }
  4003. DP_PRINT_STATS("\n");
  4004. }
  4005. index = 0;
  4006. for (i = 0; i < SS_COUNT; i++) {
  4007. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  4008. " %d", peer->stats.rx.nss[i]);
  4009. }
  4010. DP_PRINT_STATS("NSS(0-7) = %s",
  4011. nss);
  4012. DP_PRINT_STATS("Aggregation:");
  4013. DP_PRINT_STATS(" Msdu's Part of Ampdu = %d",
  4014. peer->stats.rx.ampdu_cnt);
  4015. DP_PRINT_STATS(" Msdu's With No Mpdu Level Aggregation = %d",
  4016. peer->stats.rx.non_ampdu_cnt);
  4017. DP_PRINT_STATS(" Msdu's Part of Amsdu = %d",
  4018. peer->stats.rx.amsdu_cnt);
  4019. DP_PRINT_STATS(" Msdu's With No Msdu Level Aggregation = %d",
  4020. peer->stats.rx.non_amsdu_cnt);
  4021. }
  4022. /**
  4023. * dp_print_host_stats()- Function to print the stats aggregated at host
  4024. * @vdev_handle: DP_VDEV handle
  4025. * @type: host stats type
  4026. *
  4027. * Available Stat types
  4028. * TXRX_CLEAR_STATS : Clear the stats
  4029. * TXRX_RX_RATE_STATS: Print Rx Rate Info
  4030. * TXRX_TX_RATE_STATS: Print Tx Rate Info
  4031. * TXRX_TX_HOST_STATS: Print Tx Stats
  4032. * TXRX_RX_HOST_STATS: Print Rx Stats
  4033. * TXRX_AST_STATS: Print AST Stats
  4034. * TXRX_SRNG_PTR_STATS: Print SRNG ring pointer stats
  4035. *
  4036. * Return: 0 on success, print error message in case of failure
  4037. */
  4038. static int
  4039. dp_print_host_stats(struct cdp_vdev *vdev_handle, enum cdp_host_txrx_stats type)
  4040. {
  4041. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4042. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  4043. dp_aggregate_pdev_stats(pdev);
  4044. switch (type) {
  4045. case TXRX_CLEAR_STATS:
  4046. dp_txrx_host_stats_clr(vdev);
  4047. break;
  4048. case TXRX_RX_RATE_STATS:
  4049. dp_print_rx_rates(vdev);
  4050. break;
  4051. case TXRX_TX_RATE_STATS:
  4052. dp_print_tx_rates(vdev);
  4053. break;
  4054. case TXRX_TX_HOST_STATS:
  4055. dp_print_pdev_tx_stats(pdev);
  4056. dp_print_soc_tx_stats(pdev->soc);
  4057. break;
  4058. case TXRX_RX_HOST_STATS:
  4059. dp_print_pdev_rx_stats(pdev);
  4060. dp_print_soc_rx_stats(pdev->soc);
  4061. break;
  4062. case TXRX_AST_STATS:
  4063. dp_print_ast_stats(pdev->soc);
  4064. break;
  4065. case TXRX_SRNG_PTR_STATS:
  4066. dp_print_ring_stats(pdev);
  4067. break;
  4068. default:
  4069. DP_TRACE(FATAL, "Wrong Input For TxRx Host Stats");
  4070. break;
  4071. }
  4072. return 0;
  4073. }
  4074. /*
  4075. * dp_get_host_peer_stats()- function to print peer stats
  4076. * @pdev_handle: DP_PDEV handle
  4077. * @mac_addr: mac address of the peer
  4078. *
  4079. * Return: void
  4080. */
  4081. static void
  4082. dp_get_host_peer_stats(struct cdp_pdev *pdev_handle, char *mac_addr)
  4083. {
  4084. struct dp_peer *peer;
  4085. uint8_t local_id;
  4086. peer = (struct dp_peer *)dp_find_peer_by_addr(pdev_handle, mac_addr,
  4087. &local_id);
  4088. if (!peer) {
  4089. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  4090. "%s: Invalid peer\n", __func__);
  4091. return;
  4092. }
  4093. dp_print_peer_stats(peer);
  4094. dp_peer_rxtid_stats(peer);
  4095. return;
  4096. }
  4097. /*
  4098. * dp_ppdu_ring_cfg()- Configure PPDU Stats ring
  4099. * @pdev: DP_PDEV handle
  4100. *
  4101. * Return: void
  4102. */
  4103. static void
  4104. dp_ppdu_ring_cfg(struct dp_pdev *pdev)
  4105. {
  4106. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4107. htt_tlv_filter.mpdu_start = 0;
  4108. htt_tlv_filter.msdu_start = 0;
  4109. htt_tlv_filter.packet = 0;
  4110. htt_tlv_filter.msdu_end = 0;
  4111. htt_tlv_filter.mpdu_end = 0;
  4112. htt_tlv_filter.packet_header = 1;
  4113. htt_tlv_filter.attention = 1;
  4114. htt_tlv_filter.ppdu_start = 1;
  4115. htt_tlv_filter.ppdu_end = 1;
  4116. htt_tlv_filter.ppdu_end_user_stats = 1;
  4117. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4118. htt_tlv_filter.ppdu_end_status_done = 1;
  4119. htt_tlv_filter.enable_fp = 1;
  4120. htt_tlv_filter.enable_md = 0;
  4121. htt_tlv_filter.enable_mo = 0;
  4122. htt_h2t_rx_ring_cfg(pdev->soc->htt_handle, pdev->pdev_id,
  4123. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  4124. RX_BUFFER_SIZE, &htt_tlv_filter);
  4125. }
  4126. /*
  4127. * dp_enable_enhanced_stats()- API to enable enhanced statistcs
  4128. * @pdev_handle: DP_PDEV handle
  4129. *
  4130. * Return: void
  4131. */
  4132. static void
  4133. dp_enable_enhanced_stats(struct cdp_pdev *pdev_handle)
  4134. {
  4135. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4136. pdev->enhanced_stats_en = 1;
  4137. dp_ppdu_ring_cfg(pdev);
  4138. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4139. }
  4140. /*
  4141. * dp_disable_enhanced_stats()- API to disable enhanced statistcs
  4142. * @pdev_handle: DP_PDEV handle
  4143. *
  4144. * Return: void
  4145. */
  4146. static void
  4147. dp_disable_enhanced_stats(struct cdp_pdev *pdev_handle)
  4148. {
  4149. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4150. pdev->enhanced_stats_en = 0;
  4151. }
  4152. /*
  4153. * dp_get_fw_peer_stats()- function to print peer stats
  4154. * @pdev_handle: DP_PDEV handle
  4155. * @mac_addr: mac address of the peer
  4156. * @cap: Type of htt stats requested
  4157. *
  4158. * Currently Supporting only MAC ID based requests Only
  4159. * 1: HTT_PEER_STATS_REQ_MODE_NO_QUERY
  4160. * 2: HTT_PEER_STATS_REQ_MODE_QUERY_TQM
  4161. * 3: HTT_PEER_STATS_REQ_MODE_FLUSH_TQM
  4162. *
  4163. * Return: void
  4164. */
  4165. static void
  4166. dp_get_fw_peer_stats(struct cdp_pdev *pdev_handle, uint8_t *mac_addr,
  4167. uint32_t cap)
  4168. {
  4169. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4170. uint32_t config_param0 = 0;
  4171. uint32_t config_param1 = 0;
  4172. uint32_t config_param2 = 0;
  4173. uint32_t config_param3 = 0;
  4174. HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(config_param0, 1);
  4175. config_param0 |= (1 << (cap + 1));
  4176. config_param1 = 0x8f;
  4177. config_param2 |= (mac_addr[0] & 0x000000ff);
  4178. config_param2 |= ((mac_addr[1] << 8) & 0x0000ff00);
  4179. config_param2 |= ((mac_addr[2] << 16) & 0x00ff0000);
  4180. config_param2 |= ((mac_addr[3] << 24) & 0xff000000);
  4181. config_param3 |= (mac_addr[4] & 0x000000ff);
  4182. config_param3 |= ((mac_addr[5] << 8) & 0x0000ff00);
  4183. dp_h2t_ext_stats_msg_send(pdev, HTT_DBG_EXT_STATS_PEER_INFO,
  4184. config_param0, config_param1, config_param2,
  4185. config_param3);
  4186. }
  4187. /*
  4188. * dp_set_vdev_param: function to set parameters in vdev
  4189. * @param: parameter type to be set
  4190. * @val: value of parameter to be set
  4191. *
  4192. * return: void
  4193. */
  4194. static void dp_set_vdev_param(struct cdp_vdev *vdev_handle,
  4195. enum cdp_vdev_param_type param, uint32_t val)
  4196. {
  4197. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4198. switch (param) {
  4199. case CDP_ENABLE_WDS:
  4200. vdev->wds_enabled = val;
  4201. break;
  4202. case CDP_ENABLE_NAWDS:
  4203. vdev->nawds_enabled = val;
  4204. break;
  4205. case CDP_ENABLE_MCAST_EN:
  4206. vdev->mcast_enhancement_en = val;
  4207. break;
  4208. case CDP_ENABLE_PROXYSTA:
  4209. vdev->proxysta_vdev = val;
  4210. break;
  4211. case CDP_UPDATE_TDLS_FLAGS:
  4212. vdev->tdls_link_connected = val;
  4213. break;
  4214. case CDP_CFG_WDS_AGING_TIMER:
  4215. if (val == 0)
  4216. qdf_timer_stop(&vdev->pdev->soc->wds_aging_timer);
  4217. else if (val != vdev->wds_aging_timer_val)
  4218. qdf_timer_mod(&vdev->pdev->soc->wds_aging_timer, val);
  4219. vdev->wds_aging_timer_val = val;
  4220. break;
  4221. case CDP_ENABLE_AP_BRIDGE:
  4222. if (wlan_op_mode_sta != vdev->opmode)
  4223. vdev->ap_bridge_enabled = val;
  4224. else
  4225. vdev->ap_bridge_enabled = false;
  4226. break;
  4227. default:
  4228. break;
  4229. }
  4230. dp_tx_vdev_update_search_flags(vdev);
  4231. }
  4232. /**
  4233. * dp_peer_set_nawds: set nawds bit in peer
  4234. * @peer_handle: pointer to peer
  4235. * @value: enable/disable nawds
  4236. *
  4237. * return: void
  4238. */
  4239. static void dp_peer_set_nawds(struct cdp_peer *peer_handle, uint8_t value)
  4240. {
  4241. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  4242. peer->nawds_enabled = value;
  4243. }
  4244. /*
  4245. * dp_set_vdev_dscp_tid_map_wifi3(): Update Map ID selected for particular vdev
  4246. * @vdev_handle: DP_VDEV handle
  4247. * @map_id:ID of map that needs to be updated
  4248. *
  4249. * Return: void
  4250. */
  4251. static void dp_set_vdev_dscp_tid_map_wifi3(struct cdp_vdev *vdev_handle,
  4252. uint8_t map_id)
  4253. {
  4254. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4255. vdev->dscp_tid_map_id = map_id;
  4256. return;
  4257. }
  4258. /**
  4259. * dp_set_pdev_dscp_tid_map_wifi3(): update dscp tid map in pdev
  4260. * @pdev: DP_PDEV handle
  4261. * @map_id: ID of map that needs to be updated
  4262. * @tos: index value in map
  4263. * @tid: tid value passed by the user
  4264. *
  4265. * Return: void
  4266. */
  4267. static void dp_set_pdev_dscp_tid_map_wifi3(struct cdp_pdev *pdev_handle,
  4268. uint8_t map_id, uint8_t tos, uint8_t tid)
  4269. {
  4270. uint8_t dscp;
  4271. struct dp_pdev *pdev = (struct dp_pdev *) pdev_handle;
  4272. dscp = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  4273. pdev->dscp_tid_map[map_id][dscp] = tid;
  4274. if (map_id < HAL_MAX_HW_DSCP_TID_MAPS)
  4275. hal_tx_update_dscp_tid(pdev->soc->hal_soc, tid,
  4276. map_id, dscp);
  4277. return;
  4278. }
  4279. /**
  4280. * dp_fw_stats_process(): Process TxRX FW stats request
  4281. * @vdev_handle: DP VDEV handle
  4282. * @val: value passed by user
  4283. *
  4284. * return: int
  4285. */
  4286. static int dp_fw_stats_process(struct cdp_vdev *vdev_handle, uint32_t val)
  4287. {
  4288. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4289. struct dp_pdev *pdev = NULL;
  4290. if (!vdev) {
  4291. DP_TRACE(NONE, "VDEV not found");
  4292. return 1;
  4293. }
  4294. pdev = vdev->pdev;
  4295. return dp_h2t_ext_stats_msg_send(pdev, val, 0, 0, 0, 0);
  4296. }
  4297. /*
  4298. * dp_txrx_stats() - function to map to firmware and host stats
  4299. * @vdev: virtual handle
  4300. * @stats: type of statistics requested
  4301. *
  4302. * Return: integer
  4303. */
  4304. static int dp_txrx_stats(struct cdp_vdev *vdev, enum cdp_stats stats)
  4305. {
  4306. int host_stats;
  4307. int fw_stats;
  4308. if (stats >= CDP_TXRX_MAX_STATS)
  4309. return 0;
  4310. /*
  4311. * DP_CURR_FW_STATS_AVAIL: no of FW stats currently available
  4312. * has to be updated if new FW HTT stats added
  4313. */
  4314. if (stats > CDP_TXRX_STATS_HTT_MAX)
  4315. stats = stats + DP_CURR_FW_STATS_AVAIL - DP_HTT_DBG_EXT_STATS_MAX;
  4316. fw_stats = dp_stats_mapping_table[stats][STATS_FW];
  4317. host_stats = dp_stats_mapping_table[stats][STATS_HOST];
  4318. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4319. "stats: %u fw_stats_type: %d host_stats_type: %d",
  4320. stats, fw_stats, host_stats);
  4321. if (fw_stats != TXRX_FW_STATS_INVALID)
  4322. return dp_fw_stats_process(vdev, fw_stats);
  4323. if ((host_stats != TXRX_HOST_STATS_INVALID) &&
  4324. (host_stats <= TXRX_HOST_STATS_MAX))
  4325. return dp_print_host_stats(vdev, host_stats);
  4326. else
  4327. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4328. "Wrong Input for TxRx Stats");
  4329. return 0;
  4330. }
  4331. /*
  4332. * dp_print_napi_stats(): NAPI stats
  4333. * @soc - soc handle
  4334. */
  4335. static void dp_print_napi_stats(struct dp_soc *soc)
  4336. {
  4337. hif_print_napi_stats(soc->hif_handle);
  4338. }
  4339. /*
  4340. * dp_print_per_ring_stats(): Packet count per ring
  4341. * @soc - soc handle
  4342. */
  4343. static void dp_print_per_ring_stats(struct dp_soc *soc)
  4344. {
  4345. uint8_t core, ring;
  4346. uint64_t total_packets;
  4347. DP_TRACE(FATAL, "Reo packets per ring:");
  4348. for (ring = 0; ring < MAX_REO_DEST_RINGS; ring++) {
  4349. total_packets = 0;
  4350. DP_TRACE(FATAL, "Packets on ring %u:", ring);
  4351. for (core = 0; core < NR_CPUS; core++) {
  4352. DP_TRACE(FATAL, "Packets arriving on core %u: %llu",
  4353. core, soc->stats.rx.ring_packets[core][ring]);
  4354. total_packets += soc->stats.rx.ring_packets[core][ring];
  4355. }
  4356. DP_TRACE(FATAL, "Total packets on ring %u: %llu",
  4357. ring, total_packets);
  4358. }
  4359. }
  4360. /*
  4361. * dp_txrx_path_stats() - Function to display dump stats
  4362. * @soc - soc handle
  4363. *
  4364. * return: none
  4365. */
  4366. static void dp_txrx_path_stats(struct dp_soc *soc)
  4367. {
  4368. uint8_t error_code;
  4369. uint8_t loop_pdev;
  4370. struct dp_pdev *pdev;
  4371. uint8_t i;
  4372. for (loop_pdev = 0; loop_pdev < soc->pdev_count; loop_pdev++) {
  4373. pdev = soc->pdev_list[loop_pdev];
  4374. dp_aggregate_pdev_stats(pdev);
  4375. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4376. "Tx path Statistics:");
  4377. DP_TRACE(FATAL, "from stack: %u msdus (%u bytes)",
  4378. pdev->stats.tx_i.rcvd.num,
  4379. pdev->stats.tx_i.rcvd.bytes);
  4380. DP_TRACE(FATAL, "processed from host: %u msdus (%u bytes)",
  4381. pdev->stats.tx_i.processed.num,
  4382. pdev->stats.tx_i.processed.bytes);
  4383. DP_TRACE(FATAL, "successfully transmitted: %u msdus (%u bytes)",
  4384. pdev->stats.tx.tx_success.num,
  4385. pdev->stats.tx.tx_success.bytes);
  4386. DP_TRACE(FATAL, "Dropped in host:");
  4387. DP_TRACE(FATAL, "Total packets dropped: %u,",
  4388. pdev->stats.tx_i.dropped.dropped_pkt.num);
  4389. DP_TRACE(FATAL, "Descriptor not available: %u",
  4390. pdev->stats.tx_i.dropped.desc_na);
  4391. DP_TRACE(FATAL, "Ring full: %u",
  4392. pdev->stats.tx_i.dropped.ring_full);
  4393. DP_TRACE(FATAL, "Enqueue fail: %u",
  4394. pdev->stats.tx_i.dropped.enqueue_fail);
  4395. DP_TRACE(FATAL, "DMA Error: %u",
  4396. pdev->stats.tx_i.dropped.dma_error);
  4397. DP_TRACE(FATAL, "Dropped in hardware:");
  4398. DP_TRACE(FATAL, "total packets dropped: %u",
  4399. pdev->stats.tx.tx_failed);
  4400. DP_TRACE(FATAL, "mpdu age out: %u",
  4401. pdev->stats.tx.dropped.age_out);
  4402. DP_TRACE(FATAL, "firmware removed: %u",
  4403. pdev->stats.tx.dropped.fw_rem);
  4404. DP_TRACE(FATAL, "firmware removed tx: %u",
  4405. pdev->stats.tx.dropped.fw_rem_tx);
  4406. DP_TRACE(FATAL, "firmware removed notx %u",
  4407. pdev->stats.tx.dropped.fw_rem_notx);
  4408. DP_TRACE(FATAL, "peer_invalid: %u",
  4409. pdev->soc->stats.tx.tx_invalid_peer.num);
  4410. DP_TRACE(FATAL, "Tx packets sent per interrupt:");
  4411. DP_TRACE(FATAL, "Single Packet: %u",
  4412. pdev->stats.tx_comp_histogram.pkts_1);
  4413. DP_TRACE(FATAL, "2-20 Packets: %u",
  4414. pdev->stats.tx_comp_histogram.pkts_2_20);
  4415. DP_TRACE(FATAL, "21-40 Packets: %u",
  4416. pdev->stats.tx_comp_histogram.pkts_21_40);
  4417. DP_TRACE(FATAL, "41-60 Packets: %u",
  4418. pdev->stats.tx_comp_histogram.pkts_41_60);
  4419. DP_TRACE(FATAL, "61-80 Packets: %u",
  4420. pdev->stats.tx_comp_histogram.pkts_61_80);
  4421. DP_TRACE(FATAL, "81-100 Packets: %u",
  4422. pdev->stats.tx_comp_histogram.pkts_81_100);
  4423. DP_TRACE(FATAL, "101-200 Packets: %u",
  4424. pdev->stats.tx_comp_histogram.pkts_101_200);
  4425. DP_TRACE(FATAL, " 201+ Packets: %u",
  4426. pdev->stats.tx_comp_histogram.pkts_201_plus);
  4427. DP_TRACE(FATAL, "Rx path statistics");
  4428. DP_TRACE(FATAL, "delivered %u msdus ( %u bytes),",
  4429. pdev->stats.rx.to_stack.num,
  4430. pdev->stats.rx.to_stack.bytes);
  4431. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  4432. DP_TRACE(FATAL, "received on reo[%d] %u msdus ( %u bytes),",
  4433. i, pdev->stats.rx.rcvd_reo[i].num,
  4434. pdev->stats.rx.rcvd_reo[i].bytes);
  4435. DP_TRACE(FATAL, "intra-bss packets %u msdus ( %u bytes),",
  4436. pdev->stats.rx.intra_bss.pkts.num,
  4437. pdev->stats.rx.intra_bss.pkts.bytes);
  4438. DP_TRACE(FATAL, "intra-bss fails %u msdus ( %u bytes),",
  4439. pdev->stats.rx.intra_bss.fail.num,
  4440. pdev->stats.rx.intra_bss.fail.bytes);
  4441. DP_TRACE(FATAL, "raw packets %u msdus ( %u bytes),",
  4442. pdev->stats.rx.raw.num,
  4443. pdev->stats.rx.raw.bytes);
  4444. DP_TRACE(FATAL, "dropped: error %u msdus",
  4445. pdev->stats.rx.err.mic_err);
  4446. DP_TRACE(FATAL, "peer invalid %u",
  4447. pdev->soc->stats.rx.err.rx_invalid_peer.num);
  4448. DP_TRACE(FATAL, "Reo Statistics");
  4449. DP_TRACE(FATAL, "rbm error: %u msdus",
  4450. pdev->soc->stats.rx.err.invalid_rbm);
  4451. DP_TRACE(FATAL, "hal ring access fail: %u msdus",
  4452. pdev->soc->stats.rx.err.hal_ring_access_fail);
  4453. DP_TRACE(FATAL, "Reo errors");
  4454. for (error_code = 0; error_code < HAL_REO_ERR_MAX;
  4455. error_code++) {
  4456. DP_TRACE(FATAL, "Reo error number (%u): %u msdus",
  4457. error_code,
  4458. pdev->soc->stats.rx.err.reo_error[error_code]);
  4459. }
  4460. for (error_code = 0; error_code < HAL_RXDMA_ERR_MAX;
  4461. error_code++) {
  4462. DP_TRACE(FATAL, "Rxdma error number (%u): %u msdus",
  4463. error_code,
  4464. pdev->soc->stats.rx.err
  4465. .rxdma_error[error_code]);
  4466. }
  4467. DP_TRACE(FATAL, "Rx packets reaped per interrupt:");
  4468. DP_TRACE(FATAL, "Single Packet: %u",
  4469. pdev->stats.rx_ind_histogram.pkts_1);
  4470. DP_TRACE(FATAL, "2-20 Packets: %u",
  4471. pdev->stats.rx_ind_histogram.pkts_2_20);
  4472. DP_TRACE(FATAL, "21-40 Packets: %u",
  4473. pdev->stats.rx_ind_histogram.pkts_21_40);
  4474. DP_TRACE(FATAL, "41-60 Packets: %u",
  4475. pdev->stats.rx_ind_histogram.pkts_41_60);
  4476. DP_TRACE(FATAL, "61-80 Packets: %u",
  4477. pdev->stats.rx_ind_histogram.pkts_61_80);
  4478. DP_TRACE(FATAL, "81-100 Packets: %u",
  4479. pdev->stats.rx_ind_histogram.pkts_81_100);
  4480. DP_TRACE(FATAL, "101-200 Packets: %u",
  4481. pdev->stats.rx_ind_histogram.pkts_101_200);
  4482. DP_TRACE(FATAL, " 201+ Packets: %u",
  4483. pdev->stats.rx_ind_histogram.pkts_201_plus);
  4484. }
  4485. }
  4486. /*
  4487. * dp_txrx_dump_stats() - Dump statistics
  4488. * @value - Statistics option
  4489. */
  4490. static QDF_STATUS dp_txrx_dump_stats(void *psoc, uint16_t value)
  4491. {
  4492. struct dp_soc *soc =
  4493. (struct dp_soc *)psoc;
  4494. QDF_STATUS status = QDF_STATUS_SUCCESS;
  4495. if (!soc) {
  4496. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4497. "%s: soc is NULL", __func__);
  4498. return QDF_STATUS_E_INVAL;
  4499. }
  4500. switch (value) {
  4501. case CDP_TXRX_PATH_STATS:
  4502. dp_txrx_path_stats(soc);
  4503. break;
  4504. case CDP_RX_RING_STATS:
  4505. dp_print_per_ring_stats(soc);
  4506. break;
  4507. case CDP_TXRX_TSO_STATS:
  4508. /* TODO: NOT IMPLEMENTED */
  4509. break;
  4510. case CDP_DUMP_TX_FLOW_POOL_INFO:
  4511. cdp_dump_flow_pool_info((struct cdp_soc_t *)soc);
  4512. break;
  4513. case CDP_DP_NAPI_STATS:
  4514. dp_print_napi_stats(soc);
  4515. break;
  4516. case CDP_TXRX_DESC_STATS:
  4517. /* TODO: NOT IMPLEMENTED */
  4518. break;
  4519. default:
  4520. status = QDF_STATUS_E_INVAL;
  4521. break;
  4522. }
  4523. return status;
  4524. }
  4525. static struct cdp_wds_ops dp_ops_wds = {
  4526. .vdev_set_wds = dp_vdev_set_wds,
  4527. };
  4528. /*
  4529. * dp_peer_delete_ast_entries(): Delete all AST entries for a peer
  4530. * @soc - datapath soc handle
  4531. * @peer - datapath peer handle
  4532. *
  4533. * Delete the AST entries belonging to a peer
  4534. */
  4535. #ifdef FEATURE_WDS
  4536. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4537. struct dp_peer *peer)
  4538. {
  4539. struct dp_ast_entry *ast_entry, *temp_ast_entry;
  4540. qdf_spin_lock_bh(&soc->ast_lock);
  4541. DP_PEER_ITERATE_ASE_LIST(peer, ast_entry, temp_ast_entry) {
  4542. if (ast_entry->next_hop) {
  4543. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  4544. peer->vdev->pdev->osif_pdev,
  4545. ast_entry->mac_addr.raw);
  4546. }
  4547. dp_peer_del_ast(soc, ast_entry);
  4548. }
  4549. qdf_spin_unlock_bh(&soc->ast_lock);
  4550. }
  4551. #else
  4552. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4553. struct dp_peer *peer)
  4554. {
  4555. }
  4556. #endif
  4557. /*
  4558. * dp_txrx_data_tx_cb_set(): set the callback for non standard tx
  4559. * @vdev_handle - datapath vdev handle
  4560. * @callback - callback function
  4561. * @ctxt: callback context
  4562. *
  4563. */
  4564. static void
  4565. dp_txrx_data_tx_cb_set(struct cdp_vdev *vdev_handle,
  4566. ol_txrx_data_tx_cb callback, void *ctxt)
  4567. {
  4568. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4569. vdev->tx_non_std_data_callback.func = callback;
  4570. vdev->tx_non_std_data_callback.ctxt = ctxt;
  4571. }
  4572. #ifdef CONFIG_WIN
  4573. static void dp_peer_teardown_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  4574. {
  4575. struct dp_vdev *vdev = (struct dp_vdev *) vdev_hdl;
  4576. struct dp_peer *peer = (struct dp_peer *) peer_hdl;
  4577. struct dp_soc *soc = (struct dp_soc *) vdev->pdev->soc;
  4578. dp_peer_delete_ast_entries(soc, peer);
  4579. }
  4580. #endif
  4581. static struct cdp_cmn_ops dp_ops_cmn = {
  4582. .txrx_soc_attach_target = dp_soc_attach_target_wifi3,
  4583. .txrx_vdev_attach = dp_vdev_attach_wifi3,
  4584. .txrx_vdev_detach = dp_vdev_detach_wifi3,
  4585. .txrx_pdev_attach = dp_pdev_attach_wifi3,
  4586. .txrx_pdev_detach = dp_pdev_detach_wifi3,
  4587. .txrx_peer_create = dp_peer_create_wifi3,
  4588. .txrx_peer_setup = dp_peer_setup_wifi3,
  4589. #ifdef CONFIG_WIN
  4590. .txrx_peer_teardown = dp_peer_teardown_wifi3,
  4591. #else
  4592. .txrx_peer_teardown = NULL,
  4593. #endif
  4594. .txrx_peer_delete = dp_peer_delete_wifi3,
  4595. .txrx_vdev_register = dp_vdev_register_wifi3,
  4596. .txrx_soc_detach = dp_soc_detach_wifi3,
  4597. .txrx_get_vdev_mac_addr = dp_get_vdev_mac_addr_wifi3,
  4598. .txrx_get_vdev_from_vdev_id = dp_get_vdev_from_vdev_id_wifi3,
  4599. .txrx_get_ctrl_pdev_from_vdev = dp_get_ctrl_pdev_from_vdev_wifi3,
  4600. .addba_requestprocess = dp_addba_requestprocess_wifi3,
  4601. .addba_responsesetup = dp_addba_responsesetup_wifi3,
  4602. .delba_process = dp_delba_process_wifi3,
  4603. .get_peer_mac_addr_frm_id = dp_get_peer_mac_addr_frm_id,
  4604. .flush_cache_rx_queue = NULL,
  4605. /* TODO: get API's for dscp-tid need to be added*/
  4606. .set_vdev_dscp_tid_map = dp_set_vdev_dscp_tid_map_wifi3,
  4607. .set_pdev_dscp_tid_map = dp_set_pdev_dscp_tid_map_wifi3,
  4608. .txrx_stats = dp_txrx_stats,
  4609. .txrx_set_monitor_mode = dp_vdev_set_monitor_mode,
  4610. .display_stats = dp_txrx_dump_stats,
  4611. .txrx_soc_set_nss_cfg = dp_soc_set_nss_cfg_wifi3,
  4612. .txrx_soc_get_nss_cfg = dp_soc_get_nss_cfg_wifi3,
  4613. #ifdef DP_INTR_POLL_BASED
  4614. .txrx_intr_attach = dp_soc_interrupt_attach_wrapper,
  4615. #else
  4616. .txrx_intr_attach = dp_soc_interrupt_attach,
  4617. #endif
  4618. .txrx_intr_detach = dp_soc_interrupt_detach,
  4619. .set_pn_check = dp_set_pn_check_wifi3,
  4620. /* TODO: Add other functions */
  4621. .txrx_data_tx_cb_set = dp_txrx_data_tx_cb_set
  4622. };
  4623. static struct cdp_ctrl_ops dp_ops_ctrl = {
  4624. .txrx_peer_authorize = dp_peer_authorize,
  4625. .txrx_set_vdev_rx_decap_type = dp_set_vdev_rx_decap_type,
  4626. .txrx_set_tx_encap_type = dp_set_vdev_tx_encap_type,
  4627. #ifdef MESH_MODE_SUPPORT
  4628. .txrx_set_mesh_mode = dp_peer_set_mesh_mode,
  4629. .txrx_set_mesh_rx_filter = dp_peer_set_mesh_rx_filter,
  4630. #endif
  4631. .txrx_set_vdev_param = dp_set_vdev_param,
  4632. .txrx_peer_set_nawds = dp_peer_set_nawds,
  4633. .txrx_set_pdev_reo_dest = dp_set_pdev_reo_dest,
  4634. .txrx_get_pdev_reo_dest = dp_get_pdev_reo_dest,
  4635. .txrx_set_filter_neighbour_peers = dp_set_filter_neighbour_peers,
  4636. .txrx_update_filter_neighbour_peers =
  4637. dp_update_filter_neighbour_peers,
  4638. .txrx_get_sec_type = dp_get_sec_type,
  4639. /* TODO: Add other functions */
  4640. .txrx_wdi_event_sub = dp_wdi_event_sub,
  4641. .txrx_wdi_event_unsub = dp_wdi_event_unsub,
  4642. };
  4643. static struct cdp_me_ops dp_ops_me = {
  4644. #ifdef ATH_SUPPORT_IQUE
  4645. .tx_me_alloc_descriptor = dp_tx_me_alloc_descriptor,
  4646. .tx_me_free_descriptor = dp_tx_me_free_descriptor,
  4647. .tx_me_convert_ucast = dp_tx_me_send_convert_ucast,
  4648. #endif
  4649. };
  4650. static struct cdp_mon_ops dp_ops_mon = {
  4651. .txrx_monitor_set_filter_ucast_data = NULL,
  4652. .txrx_monitor_set_filter_mcast_data = NULL,
  4653. .txrx_monitor_set_filter_non_data = NULL,
  4654. .txrx_monitor_get_filter_ucast_data = NULL,
  4655. .txrx_monitor_get_filter_mcast_data = NULL,
  4656. .txrx_monitor_get_filter_non_data = NULL,
  4657. .txrx_reset_monitor_mode = dp_reset_monitor_mode,
  4658. };
  4659. static struct cdp_host_stats_ops dp_ops_host_stats = {
  4660. .txrx_per_peer_stats = dp_get_host_peer_stats,
  4661. .get_fw_peer_stats = dp_get_fw_peer_stats,
  4662. .txrx_enable_enhanced_stats = dp_enable_enhanced_stats,
  4663. .txrx_disable_enhanced_stats = dp_disable_enhanced_stats,
  4664. /* TODO */
  4665. };
  4666. static struct cdp_raw_ops dp_ops_raw = {
  4667. /* TODO */
  4668. };
  4669. #ifdef CONFIG_WIN
  4670. static struct cdp_pflow_ops dp_ops_pflow = {
  4671. /* TODO */
  4672. };
  4673. #endif /* CONFIG_WIN */
  4674. #ifdef FEATURE_RUNTIME_PM
  4675. /**
  4676. * dp_runtime_suspend() - ensure DP is ready to runtime suspend
  4677. * @opaque_pdev: DP pdev context
  4678. *
  4679. * DP is ready to runtime suspend if there are no pending TX packets.
  4680. *
  4681. * Return: QDF_STATUS
  4682. */
  4683. static QDF_STATUS dp_runtime_suspend(struct cdp_pdev *opaque_pdev)
  4684. {
  4685. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4686. struct dp_soc *soc = pdev->soc;
  4687. /* Call DP TX flow control API to check if there is any
  4688. pending packets */
  4689. if (soc->intr_mode == DP_INTR_POLL)
  4690. qdf_timer_stop(&soc->int_timer);
  4691. return QDF_STATUS_SUCCESS;
  4692. }
  4693. /**
  4694. * dp_runtime_resume() - ensure DP is ready to runtime resume
  4695. * @opaque_pdev: DP pdev context
  4696. *
  4697. * Resume DP for runtime PM.
  4698. *
  4699. * Return: QDF_STATUS
  4700. */
  4701. static QDF_STATUS dp_runtime_resume(struct cdp_pdev *opaque_pdev)
  4702. {
  4703. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4704. struct dp_soc *soc = pdev->soc;
  4705. void *hal_srng;
  4706. int i;
  4707. if (soc->intr_mode == DP_INTR_POLL)
  4708. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4709. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  4710. hal_srng = soc->tcl_data_ring[i].hal_srng;
  4711. if (hal_srng) {
  4712. /* We actually only need to acquire the lock */
  4713. hal_srng_access_start(soc->hal_soc, hal_srng);
  4714. /* Update SRC ring head pointer for HW to send
  4715. all pending packets */
  4716. hal_srng_access_end(soc->hal_soc, hal_srng);
  4717. }
  4718. }
  4719. return QDF_STATUS_SUCCESS;
  4720. }
  4721. #endif /* FEATURE_RUNTIME_PM */
  4722. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  4723. {
  4724. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4725. struct dp_soc *soc = pdev->soc;
  4726. if (soc->intr_mode == DP_INTR_POLL)
  4727. qdf_timer_stop(&soc->int_timer);
  4728. return QDF_STATUS_SUCCESS;
  4729. }
  4730. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  4731. {
  4732. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4733. struct dp_soc *soc = pdev->soc;
  4734. if (soc->intr_mode == DP_INTR_POLL)
  4735. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4736. return QDF_STATUS_SUCCESS;
  4737. }
  4738. #ifndef CONFIG_WIN
  4739. static struct cdp_misc_ops dp_ops_misc = {
  4740. .tx_non_std = dp_tx_non_std,
  4741. .get_opmode = dp_get_opmode,
  4742. #ifdef FEATURE_RUNTIME_PM
  4743. .runtime_suspend = dp_runtime_suspend,
  4744. .runtime_resume = dp_runtime_resume,
  4745. #endif /* FEATURE_RUNTIME_PM */
  4746. };
  4747. static struct cdp_flowctl_ops dp_ops_flowctl = {
  4748. /* WIFI 3.0 DP implement as required. */
  4749. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4750. .register_pause_cb = dp_txrx_register_pause_cb,
  4751. .dump_flow_pool_info = dp_tx_dump_flow_pool_info,
  4752. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  4753. };
  4754. static struct cdp_lflowctl_ops dp_ops_l_flowctl = {
  4755. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4756. };
  4757. #ifdef IPA_OFFLOAD
  4758. static struct cdp_ipa_ops dp_ops_ipa = {
  4759. .ipa_get_resource = dp_ipa_get_resource,
  4760. .ipa_set_doorbell_paddr = dp_ipa_set_doorbell_paddr,
  4761. .ipa_op_response = dp_ipa_op_response,
  4762. .ipa_register_op_cb = dp_ipa_register_op_cb,
  4763. .ipa_get_stat = dp_ipa_get_stat,
  4764. .ipa_tx_data_frame = dp_tx_send_ipa_data_frame,
  4765. .ipa_enable_autonomy = dp_ipa_enable_autonomy,
  4766. .ipa_disable_autonomy = dp_ipa_disable_autonomy,
  4767. .ipa_setup = dp_ipa_setup,
  4768. .ipa_cleanup = dp_ipa_cleanup,
  4769. .ipa_setup_iface = dp_ipa_setup_iface,
  4770. .ipa_cleanup_iface = dp_ipa_cleanup_iface,
  4771. .ipa_enable_pipes = dp_ipa_enable_pipes,
  4772. .ipa_disable_pipes = dp_ipa_disable_pipes,
  4773. .ipa_set_perf_level = dp_ipa_set_perf_level
  4774. };
  4775. #endif
  4776. static struct cdp_bus_ops dp_ops_bus = {
  4777. .bus_suspend = dp_bus_suspend,
  4778. .bus_resume = dp_bus_resume
  4779. };
  4780. static struct cdp_ocb_ops dp_ops_ocb = {
  4781. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4782. };
  4783. static struct cdp_throttle_ops dp_ops_throttle = {
  4784. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4785. };
  4786. static struct cdp_mob_stats_ops dp_ops_mob_stats = {
  4787. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4788. };
  4789. static struct cdp_cfg_ops dp_ops_cfg = {
  4790. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4791. };
  4792. static struct cdp_peer_ops dp_ops_peer = {
  4793. .register_peer = dp_register_peer,
  4794. .clear_peer = dp_clear_peer,
  4795. .find_peer_by_addr = dp_find_peer_by_addr,
  4796. .find_peer_by_addr_and_vdev = dp_find_peer_by_addr_and_vdev,
  4797. .local_peer_id = dp_local_peer_id,
  4798. .peer_find_by_local_id = dp_peer_find_by_local_id,
  4799. .peer_state_update = dp_peer_state_update,
  4800. .get_vdevid = dp_get_vdevid,
  4801. .get_vdev_by_sta_id = dp_get_vdev_by_sta_id,
  4802. .peer_get_peer_mac_addr = dp_peer_get_peer_mac_addr,
  4803. .get_vdev_for_peer = dp_get_vdev_for_peer,
  4804. .get_peer_state = dp_get_peer_state,
  4805. .last_assoc_received = dp_get_last_assoc_received,
  4806. .last_disassoc_received = dp_get_last_disassoc_received,
  4807. .last_deauth_received = dp_get_last_deauth_received,
  4808. };
  4809. #endif
  4810. static struct cdp_ops dp_txrx_ops = {
  4811. .cmn_drv_ops = &dp_ops_cmn,
  4812. .ctrl_ops = &dp_ops_ctrl,
  4813. .me_ops = &dp_ops_me,
  4814. .mon_ops = &dp_ops_mon,
  4815. .host_stats_ops = &dp_ops_host_stats,
  4816. .wds_ops = &dp_ops_wds,
  4817. .raw_ops = &dp_ops_raw,
  4818. #ifdef CONFIG_WIN
  4819. .pflow_ops = &dp_ops_pflow,
  4820. #endif /* CONFIG_WIN */
  4821. #ifndef CONFIG_WIN
  4822. .misc_ops = &dp_ops_misc,
  4823. .cfg_ops = &dp_ops_cfg,
  4824. .flowctl_ops = &dp_ops_flowctl,
  4825. .l_flowctl_ops = &dp_ops_l_flowctl,
  4826. #ifdef IPA_OFFLOAD
  4827. .ipa_ops = &dp_ops_ipa,
  4828. #endif
  4829. .bus_ops = &dp_ops_bus,
  4830. .ocb_ops = &dp_ops_ocb,
  4831. .peer_ops = &dp_ops_peer,
  4832. .throttle_ops = &dp_ops_throttle,
  4833. .mob_stats_ops = &dp_ops_mob_stats,
  4834. #endif
  4835. };
  4836. /*
  4837. * dp_soc_set_txrx_ring_map()
  4838. * @dp_soc: DP handler for soc
  4839. *
  4840. * Return: Void
  4841. */
  4842. static void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  4843. {
  4844. uint32_t i;
  4845. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  4846. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_DEFAULT_MAP][i];
  4847. }
  4848. }
  4849. /*
  4850. * dp_soc_attach_wifi3() - Attach txrx SOC
  4851. * @osif_soc: Opaque SOC handle from OSIF/HDD
  4852. * @htc_handle: Opaque HTC handle
  4853. * @hif_handle: Opaque HIF handle
  4854. * @qdf_osdev: QDF device
  4855. *
  4856. * Return: DP SOC handle on success, NULL on failure
  4857. */
  4858. /*
  4859. * Local prototype added to temporarily address warning caused by
  4860. * -Wmissing-prototypes. A more correct solution, namely to expose
  4861. * a prototype in an appropriate header file, will come later.
  4862. */
  4863. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4864. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4865. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc);
  4866. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4867. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4868. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc)
  4869. {
  4870. struct dp_soc *soc = qdf_mem_malloc(sizeof(*soc));
  4871. if (!soc) {
  4872. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4873. FL("DP SOC memory allocation failed"));
  4874. goto fail0;
  4875. }
  4876. soc->cdp_soc.ops = &dp_txrx_ops;
  4877. soc->cdp_soc.ol_ops = ol_ops;
  4878. soc->osif_soc = osif_soc;
  4879. soc->osdev = qdf_osdev;
  4880. soc->hif_handle = hif_handle;
  4881. soc->psoc = psoc;
  4882. soc->hal_soc = hif_get_hal_handle(hif_handle);
  4883. soc->htt_handle = htt_soc_attach(soc, osif_soc, htc_handle,
  4884. soc->hal_soc, qdf_osdev);
  4885. if (!soc->htt_handle) {
  4886. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4887. FL("HTT attach failed"));
  4888. goto fail1;
  4889. }
  4890. soc->wlan_cfg_ctx = wlan_cfg_soc_attach();
  4891. if (!soc->wlan_cfg_ctx) {
  4892. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4893. FL("wlan_cfg_soc_attach failed"));
  4894. goto fail2;
  4895. }
  4896. wlan_cfg_set_rx_hash(soc->wlan_cfg_ctx, rx_hash);
  4897. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  4898. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc,
  4899. CDP_CFG_MAX_PEER_ID);
  4900. if (ret != -EINVAL) {
  4901. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  4902. }
  4903. }
  4904. qdf_spinlock_create(&soc->peer_ref_mutex);
  4905. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  4906. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  4907. /* fill the tx/rx cpu ring map*/
  4908. dp_soc_set_txrx_ring_map(soc);
  4909. qdf_spinlock_create(&soc->htt_stats.lock);
  4910. /* initialize work queue for stats processing */
  4911. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  4912. return (void *)soc;
  4913. fail2:
  4914. htt_soc_detach(soc->htt_handle);
  4915. fail1:
  4916. qdf_mem_free(soc);
  4917. fail0:
  4918. return NULL;
  4919. }
  4920. #if defined(CONFIG_WIN) && WDI_EVENT_ENABLE
  4921. /*
  4922. * dp_set_pktlog_wifi3() - attach txrx vdev
  4923. * @pdev: Datapath PDEV handle
  4924. * @event: which event's notifications are being subscribed to
  4925. * @enable: WDI event subscribe or not. (True or False)
  4926. *
  4927. * Return: Success, NULL on failure
  4928. */
  4929. int dp_set_pktlog_wifi3(struct dp_pdev *pdev, uint32_t event,
  4930. bool enable)
  4931. {
  4932. struct dp_soc *soc = pdev->soc;
  4933. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4934. if (enable) {
  4935. switch (event) {
  4936. case WDI_EVENT_RX_DESC:
  4937. if (pdev->monitor_vdev) {
  4938. /* Nothing needs to be done if monitor mode is
  4939. * enabled
  4940. */
  4941. return 0;
  4942. }
  4943. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_FULL) {
  4944. pdev->rx_pktlog_mode = DP_RX_PKTLOG_FULL;
  4945. htt_tlv_filter.mpdu_start = 1;
  4946. htt_tlv_filter.msdu_start = 1;
  4947. htt_tlv_filter.msdu_end = 1;
  4948. htt_tlv_filter.mpdu_end = 1;
  4949. htt_tlv_filter.packet_header = 1;
  4950. htt_tlv_filter.attention = 1;
  4951. htt_tlv_filter.ppdu_start = 1;
  4952. htt_tlv_filter.ppdu_end = 1;
  4953. htt_tlv_filter.ppdu_end_user_stats = 1;
  4954. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4955. htt_tlv_filter.ppdu_end_status_done = 1;
  4956. htt_tlv_filter.enable_fp = 1;
  4957. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4958. pdev->pdev_id,
  4959. pdev->rxdma_mon_status_ring.hal_srng,
  4960. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4961. &htt_tlv_filter);
  4962. }
  4963. break;
  4964. case WDI_EVENT_LITE_RX:
  4965. if (pdev->monitor_vdev) {
  4966. /* Nothing needs to be done if monitor mode is
  4967. * enabled
  4968. */
  4969. return 0;
  4970. }
  4971. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_LITE) {
  4972. pdev->rx_pktlog_mode = DP_RX_PKTLOG_LITE;
  4973. htt_tlv_filter.ppdu_start = 1;
  4974. htt_tlv_filter.ppdu_end = 1;
  4975. htt_tlv_filter.ppdu_end_user_stats = 1;
  4976. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4977. htt_tlv_filter.ppdu_end_status_done = 1;
  4978. htt_tlv_filter.enable_fp = 1;
  4979. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4980. pdev->pdev_id,
  4981. pdev->rxdma_mon_status_ring.hal_srng,
  4982. RXDMA_MONITOR_STATUS,
  4983. RX_BUFFER_SIZE_PKTLOG_LITE,
  4984. &htt_tlv_filter);
  4985. }
  4986. break;
  4987. case WDI_EVENT_LITE_T2H:
  4988. if (pdev->monitor_vdev) {
  4989. /* Nothing needs to be done if monitor mode is
  4990. * enabled
  4991. */
  4992. return 0;
  4993. }
  4994. /* To enable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4995. * passing value 0xffff. Once these macros will define in htt
  4996. * header file will use proper macros
  4997. */
  4998. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4999. break;
  5000. default:
  5001. /* Nothing needs to be done for other pktlog types */
  5002. break;
  5003. }
  5004. } else {
  5005. switch (event) {
  5006. case WDI_EVENT_RX_DESC:
  5007. case WDI_EVENT_LITE_RX:
  5008. if (pdev->monitor_vdev) {
  5009. /* Nothing needs to be done if monitor mode is
  5010. * enabled
  5011. */
  5012. return 0;
  5013. }
  5014. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_DISABLED) {
  5015. pdev->rx_pktlog_mode = DP_RX_PKTLOG_DISABLED;
  5016. /* htt_tlv_filter is initialized to 0 */
  5017. htt_h2t_rx_ring_cfg(soc->htt_handle,
  5018. pdev->pdev_id,
  5019. pdev->rxdma_mon_status_ring.hal_srng,
  5020. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  5021. &htt_tlv_filter);
  5022. }
  5023. break;
  5024. case WDI_EVENT_LITE_T2H:
  5025. if (pdev->monitor_vdev) {
  5026. /* Nothing needs to be done if monitor mode is
  5027. * enabled
  5028. */
  5029. return 0;
  5030. }
  5031. /* To disable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  5032. * passing value 0. Once these macros will define in htt
  5033. * header file will use proper macros
  5034. */
  5035. dp_h2t_cfg_stats_msg_send(pdev, 0);
  5036. break;
  5037. default:
  5038. /* Nothing needs to be done for other pktlog types */
  5039. break;
  5040. }
  5041. }
  5042. return 0;
  5043. }
  5044. #endif