qcs405.c 232 KB

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  1. /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/gpio.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/i2c.h>
  19. #include <linux/io.h>
  20. #include <linux/module.h>
  21. #include <linux/input.h>
  22. #include <linux/of_device.h>
  23. #include <linux/pm_qos.h>
  24. #include <sound/core.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/pcm.h>
  28. #include <sound/pcm_params.h>
  29. #include <sound/info.h>
  30. #include <dsp/audio_notifier.h>
  31. #include <dsp/q6afe-v2.h>
  32. #include <dsp/q6core.h>
  33. #include <dsp/msm_mdf.h>
  34. #include "device_event.h"
  35. #include "msm-pcm-routing-v2.h"
  36. #include "codecs/msm-cdc-pinctrl.h"
  37. #include "codecs/wcd9335.h"
  38. #include "codecs/wsa881x.h"
  39. #include "codecs/csra66x0/csra66x0.h"
  40. #include <dt-bindings/sound/audio-codec-port-types.h>
  41. #include "codecs/bolero/bolero-cdc.h"
  42. #include "codecs/bolero/wsa-macro.h"
  43. #define DRV_NAME "qcs405-asoc-snd"
  44. #define __CHIPSET__ "QCS405 "
  45. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  46. #define DEV_NAME_STR_LEN 32
  47. #define SAMPLING_RATE_8KHZ 8000
  48. #define SAMPLING_RATE_11P025KHZ 11025
  49. #define SAMPLING_RATE_16KHZ 16000
  50. #define SAMPLING_RATE_22P05KHZ 22050
  51. #define SAMPLING_RATE_32KHZ 32000
  52. #define SAMPLING_RATE_44P1KHZ 44100
  53. #define SAMPLING_RATE_48KHZ 48000
  54. #define SAMPLING_RATE_88P2KHZ 88200
  55. #define SAMPLING_RATE_96KHZ 96000
  56. #define SAMPLING_RATE_176P4KHZ 176400
  57. #define SAMPLING_RATE_192KHZ 192000
  58. #define SAMPLING_RATE_352P8KHZ 352800
  59. #define SAMPLING_RATE_384KHZ 384000
  60. #define SPDIF_TX_CORE_CLK_204_P8_MHZ 204800000
  61. #define TLMM_EAST_SPARE 0x07BA0000
  62. #define TLMM_SPDIF_HDMI_ARC_CTL 0x07BA2000
  63. #define WSA8810_NAME_1 "wsa881x.20170211"
  64. #define WSA8810_NAME_2 "wsa881x.20170212"
  65. #define WCN_CDC_SLIM_RX_CH_MAX 2
  66. #define WCN_CDC_SLIM_TX_CH_MAX 3
  67. #define TDM_CHANNEL_MAX 8
  68. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  69. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  70. enum {
  71. SLIM_RX_0 = 0,
  72. SLIM_RX_1,
  73. SLIM_RX_2,
  74. SLIM_RX_3,
  75. SLIM_RX_4,
  76. SLIM_RX_5,
  77. SLIM_RX_6,
  78. SLIM_RX_7,
  79. SLIM_RX_MAX,
  80. };
  81. enum {
  82. SLIM_TX_0 = 0,
  83. SLIM_TX_1,
  84. SLIM_TX_2,
  85. SLIM_TX_3,
  86. SLIM_TX_4,
  87. SLIM_TX_5,
  88. SLIM_TX_6,
  89. SLIM_TX_7,
  90. SLIM_TX_8,
  91. SLIM_TX_MAX,
  92. };
  93. enum {
  94. PRIM_MI2S = 0,
  95. SEC_MI2S,
  96. TERT_MI2S,
  97. QUAT_MI2S,
  98. QUIN_MI2S,
  99. MI2S_MAX,
  100. };
  101. enum {
  102. PRIM_AUX_PCM = 0,
  103. SEC_AUX_PCM,
  104. TERT_AUX_PCM,
  105. QUAT_AUX_PCM,
  106. QUIN_AUX_PCM,
  107. AUX_PCM_MAX,
  108. };
  109. enum {
  110. WSA_CDC_DMA_RX_0 = 0,
  111. WSA_CDC_DMA_RX_1,
  112. CDC_DMA_RX_MAX,
  113. };
  114. enum {
  115. WSA_CDC_DMA_TX_0 = 0,
  116. WSA_CDC_DMA_TX_1,
  117. WSA_CDC_DMA_TX_2,
  118. VA_CDC_DMA_TX_0,
  119. VA_CDC_DMA_TX_1,
  120. CDC_DMA_TX_MAX,
  121. };
  122. enum {
  123. PRIM_SPDIF_RX = 0,
  124. SEC_SPDIF_RX,
  125. SPDIF_RX_MAX,
  126. };
  127. enum {
  128. PRIM_SPDIF_TX = 0,
  129. SEC_SPDIF_TX,
  130. SPDIF_TX_MAX,
  131. };
  132. struct mi2s_conf {
  133. struct mutex lock;
  134. u32 ref_cnt;
  135. u32 msm_is_mi2s_master;
  136. };
  137. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  138. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  139. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  140. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  141. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  142. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
  143. };
  144. struct dev_config {
  145. u32 sample_rate;
  146. u32 bit_format;
  147. u32 channels;
  148. };
  149. struct msm_wsa881x_dev_info {
  150. struct device_node *of_node;
  151. u32 index;
  152. };
  153. struct msm_csra66x0_dev_info {
  154. struct device_node *of_node;
  155. u32 index;
  156. };
  157. enum pinctrl_pin_state {
  158. STATE_DISABLE = 0, /* All pins are in sleep state */
  159. STATE_MI2S_ACTIVE, /* I2S = active, TDM = sleep */
  160. STATE_TDM_ACTIVE, /* I2S = sleep, TDM = active */
  161. };
  162. struct msm_pinctrl_info {
  163. struct pinctrl *pinctrl;
  164. struct pinctrl_state *mi2s_disable;
  165. struct pinctrl_state *tdm_disable;
  166. struct pinctrl_state *mi2s_active;
  167. struct pinctrl_state *tdm_active;
  168. enum pinctrl_pin_state curr_state;
  169. };
  170. struct msm_asoc_mach_data {
  171. struct snd_info_entry *codec_root;
  172. struct msm_pinctrl_info pinctrl_info;
  173. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  174. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  175. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  176. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  177. int dmic_01_gpio_cnt;
  178. int dmic_23_gpio_cnt;
  179. int dmic_45_gpio_cnt;
  180. int dmic_67_gpio_cnt;
  181. };
  182. struct msm_asoc_wcd93xx_codec {
  183. void* (*get_afe_config_fn)(struct snd_soc_codec *codec,
  184. enum afe_config_type config_type);
  185. };
  186. static const char *const pin_states[] = {"sleep", "i2s-active",
  187. "tdm-active"};
  188. enum {
  189. TDM_0 = 0,
  190. TDM_1,
  191. TDM_2,
  192. TDM_3,
  193. TDM_4,
  194. TDM_5,
  195. TDM_6,
  196. TDM_7,
  197. TDM_PORT_MAX,
  198. };
  199. enum {
  200. TDM_PRI = 0,
  201. TDM_SEC,
  202. TDM_TERT,
  203. TDM_QUAT,
  204. TDM_QUIN,
  205. TDM_INTERFACE_MAX,
  206. };
  207. struct tdm_port {
  208. u32 mode;
  209. u32 channel;
  210. };
  211. /* TDM default config */
  212. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  213. { /* PRI TDM */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  215. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  216. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  217. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  218. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  219. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  220. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  221. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  222. },
  223. { /* SEC TDM */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  225. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  226. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  228. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  229. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  230. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  231. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  232. },
  233. { /* TERT TDM */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  240. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  241. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  242. },
  243. { /* QUAT TDM */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  252. },
  253. { /* QUIN TDM */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  262. }
  263. };
  264. /* TDM default config */
  265. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  266. { /* PRI TDM */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  275. },
  276. { /* SEC TDM */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  285. },
  286. { /* TERT TDM */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  295. },
  296. { /* QUAT TDM */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  305. },
  306. { /* QUIN TDM */
  307. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  308. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  309. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  310. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  311. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  312. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  313. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  314. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  315. }
  316. };
  317. /* Default configuration of slimbus channels */
  318. static struct dev_config slim_rx_cfg[] = {
  319. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  320. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  321. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  322. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  323. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  324. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  325. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  326. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  327. };
  328. static struct dev_config slim_tx_cfg[] = {
  329. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  330. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  331. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  332. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  333. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  334. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  335. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  336. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  337. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  338. };
  339. /* Default configuration of Codec DMA Interface Tx */
  340. static struct dev_config cdc_dma_rx_cfg[] = {
  341. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  342. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  343. };
  344. /* Default configuration of Codec DMA Interface Rx */
  345. static struct dev_config cdc_dma_tx_cfg[] = {
  346. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  347. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  348. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  349. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  350. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  351. };
  352. static struct dev_config usb_rx_cfg = {
  353. .sample_rate = SAMPLING_RATE_48KHZ,
  354. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  355. .channels = 2,
  356. };
  357. static struct dev_config usb_tx_cfg = {
  358. .sample_rate = SAMPLING_RATE_48KHZ,
  359. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  360. .channels = 1,
  361. };
  362. static struct dev_config proxy_rx_cfg = {
  363. .sample_rate = SAMPLING_RATE_48KHZ,
  364. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  365. .channels = 2,
  366. };
  367. /* Default configuration of MI2S channels */
  368. static struct dev_config mi2s_rx_cfg[] = {
  369. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  370. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  371. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  372. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  373. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  374. };
  375. /* Default configuration of SPDIF channels */
  376. static struct dev_config spdif_rx_cfg[] = {
  377. [PRIM_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  378. [SEC_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  379. };
  380. static struct dev_config spdif_tx_cfg[] = {
  381. [PRIM_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  382. [SEC_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  383. };
  384. static struct dev_config mi2s_tx_cfg[] = {
  385. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  386. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  387. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  388. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  389. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  390. };
  391. static struct dev_config aux_pcm_rx_cfg[] = {
  392. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  393. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  394. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  395. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  396. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  397. };
  398. static struct dev_config aux_pcm_tx_cfg[] = {
  399. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  400. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  401. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  402. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  403. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  404. };
  405. static int msm_vi_feed_tx_ch = 2;
  406. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  407. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  408. "Five", "Six", "Seven",
  409. "Eight"};
  410. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  411. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  412. "S32_LE"};
  413. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  414. "KHZ_32", "KHZ_44P1", "KHZ_48",
  415. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  416. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  417. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  418. "KHZ_44P1", "KHZ_48",
  419. "KHZ_88P2", "KHZ_96"};
  420. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  421. "Five", "Six", "Seven",
  422. "Eight"};
  423. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  424. "Six", "Seven", "Eight"};
  425. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  426. "KHZ_16", "KHZ_22P05",
  427. "KHZ_32", "KHZ_44P1", "KHZ_48",
  428. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  429. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  430. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  431. "Five", "Six", "Seven", "Eight"};
  432. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  433. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  434. "KHZ_48", "KHZ_176P4",
  435. "KHZ_352P8"};
  436. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  437. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  438. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  439. "KHZ_48", "KHZ_96", "KHZ_192"};
  440. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  441. "Five", "Six", "Seven",
  442. "Eight"};
  443. static const char *const qos_text[] = {"Disable", "Enable"};
  444. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  445. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  446. "Five", "Six", "Seven",
  447. "Eight"};
  448. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  449. "KHZ_16", "KHZ_22P05",
  450. "KHZ_32", "KHZ_44P1", "KHZ_48",
  451. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  452. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  453. static const char *spdif_rate_text[] = {"KHZ_32", "KHZ_44P1", "KHZ_48",
  454. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  455. "KHZ_192"};
  456. static const char *spdif_ch_text[] = {"One", "Two"};
  457. static const char *spdif_bit_format_text[] = {"S16_LE", "S24_LE"};
  458. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  511. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  517. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  518. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  519. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  520. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  521. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  522. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  523. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  524. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  525. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  526. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  527. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  535. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  536. cdc_dma_sample_rate_text);
  537. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  538. cdc_dma_sample_rate_text);
  539. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  540. cdc_dma_sample_rate_text);
  541. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  542. cdc_dma_sample_rate_text);
  543. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  544. cdc_dma_sample_rate_text);
  545. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  546. cdc_dma_sample_rate_text);
  547. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  548. cdc_dma_sample_rate_text);
  549. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_sample_rate, spdif_rate_text);
  550. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_sample_rate, spdif_rate_text);
  551. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_chs, spdif_ch_text);
  552. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_chs, spdif_ch_text);
  553. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_format, spdif_bit_format_text);
  554. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_format, spdif_bit_format_text);
  555. static struct platform_device *spdev;
  556. static bool is_initial_boot;
  557. static bool codec_reg_done;
  558. static struct snd_soc_aux_dev *msm_aux_dev;
  559. static struct snd_soc_codec_conf *msm_codec_conf;
  560. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  561. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  562. int enable, bool dapm);
  563. static int msm_wsa881x_init(struct snd_soc_component *component);
  564. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  565. struct snd_ctl_elem_value *ucontrol);
  566. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  567. {"MIC BIAS1", NULL, "MCLK TX"},
  568. {"MIC BIAS2", NULL, "MCLK TX"},
  569. {"MIC BIAS3", NULL, "MCLK TX"},
  570. {"MIC BIAS4", NULL, "MCLK TX"},
  571. };
  572. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  573. {
  574. AFE_API_VERSION_I2S_CONFIG,
  575. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  576. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  577. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  578. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  579. 0,
  580. },
  581. {
  582. AFE_API_VERSION_I2S_CONFIG,
  583. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  584. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  585. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  586. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  587. 0,
  588. },
  589. {
  590. AFE_API_VERSION_I2S_CONFIG,
  591. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  592. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  593. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  594. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  595. 0,
  596. },
  597. {
  598. AFE_API_VERSION_I2S_CONFIG,
  599. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  600. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  601. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  602. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  603. 0,
  604. },
  605. {
  606. AFE_API_VERSION_I2S_CONFIG,
  607. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  608. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  609. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  610. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  611. 0,
  612. }
  613. };
  614. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  615. static int slim_get_sample_rate_val(int sample_rate)
  616. {
  617. int sample_rate_val = 0;
  618. switch (sample_rate) {
  619. case SAMPLING_RATE_8KHZ:
  620. sample_rate_val = 0;
  621. break;
  622. case SAMPLING_RATE_16KHZ:
  623. sample_rate_val = 1;
  624. break;
  625. case SAMPLING_RATE_32KHZ:
  626. sample_rate_val = 2;
  627. break;
  628. case SAMPLING_RATE_44P1KHZ:
  629. sample_rate_val = 3;
  630. break;
  631. case SAMPLING_RATE_48KHZ:
  632. sample_rate_val = 4;
  633. break;
  634. case SAMPLING_RATE_88P2KHZ:
  635. sample_rate_val = 5;
  636. break;
  637. case SAMPLING_RATE_96KHZ:
  638. sample_rate_val = 6;
  639. break;
  640. case SAMPLING_RATE_176P4KHZ:
  641. sample_rate_val = 7;
  642. break;
  643. case SAMPLING_RATE_192KHZ:
  644. sample_rate_val = 8;
  645. break;
  646. case SAMPLING_RATE_352P8KHZ:
  647. sample_rate_val = 9;
  648. break;
  649. case SAMPLING_RATE_384KHZ:
  650. sample_rate_val = 10;
  651. break;
  652. default:
  653. sample_rate_val = 4;
  654. break;
  655. }
  656. return sample_rate_val;
  657. }
  658. static int slim_get_sample_rate(int value)
  659. {
  660. int sample_rate = 0;
  661. switch (value) {
  662. case 0:
  663. sample_rate = SAMPLING_RATE_8KHZ;
  664. break;
  665. case 1:
  666. sample_rate = SAMPLING_RATE_16KHZ;
  667. break;
  668. case 2:
  669. sample_rate = SAMPLING_RATE_32KHZ;
  670. break;
  671. case 3:
  672. sample_rate = SAMPLING_RATE_44P1KHZ;
  673. break;
  674. case 4:
  675. sample_rate = SAMPLING_RATE_48KHZ;
  676. break;
  677. case 5:
  678. sample_rate = SAMPLING_RATE_88P2KHZ;
  679. break;
  680. case 6:
  681. sample_rate = SAMPLING_RATE_96KHZ;
  682. break;
  683. case 7:
  684. sample_rate = SAMPLING_RATE_176P4KHZ;
  685. break;
  686. case 8:
  687. sample_rate = SAMPLING_RATE_192KHZ;
  688. break;
  689. case 9:
  690. sample_rate = SAMPLING_RATE_352P8KHZ;
  691. break;
  692. case 10:
  693. sample_rate = SAMPLING_RATE_384KHZ;
  694. break;
  695. default:
  696. sample_rate = SAMPLING_RATE_48KHZ;
  697. break;
  698. }
  699. return sample_rate;
  700. }
  701. static int slim_get_bit_format_val(int bit_format)
  702. {
  703. int val = 0;
  704. switch (bit_format) {
  705. case SNDRV_PCM_FORMAT_S32_LE:
  706. val = 3;
  707. break;
  708. case SNDRV_PCM_FORMAT_S24_3LE:
  709. val = 2;
  710. break;
  711. case SNDRV_PCM_FORMAT_S24_LE:
  712. val = 1;
  713. break;
  714. case SNDRV_PCM_FORMAT_S16_LE:
  715. default:
  716. val = 0;
  717. break;
  718. }
  719. return val;
  720. }
  721. static int slim_get_bit_format(int val)
  722. {
  723. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  724. switch (val) {
  725. case 0:
  726. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  727. break;
  728. case 1:
  729. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  730. break;
  731. case 2:
  732. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  733. break;
  734. case 3:
  735. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  736. break;
  737. default:
  738. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  739. break;
  740. }
  741. return bit_fmt;
  742. }
  743. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  744. {
  745. int port_id = 0;
  746. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  747. port_id = SLIM_RX_0;
  748. } else if (strnstr(kcontrol->id.name,
  749. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  750. port_id = SLIM_RX_2;
  751. } else if (strnstr(kcontrol->id.name,
  752. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  753. port_id = SLIM_RX_5;
  754. } else if (strnstr(kcontrol->id.name,
  755. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  756. port_id = SLIM_RX_6;
  757. } else if (strnstr(kcontrol->id.name,
  758. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  759. port_id = SLIM_TX_0;
  760. } else if (strnstr(kcontrol->id.name,
  761. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  762. port_id = SLIM_TX_1;
  763. } else {
  764. pr_err("%s: unsupported channel: %s",
  765. __func__, kcontrol->id.name);
  766. return -EINVAL;
  767. }
  768. return port_id;
  769. }
  770. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  771. struct snd_ctl_elem_value *ucontrol)
  772. {
  773. int ch_num = slim_get_port_idx(kcontrol);
  774. if (ch_num < 0)
  775. return ch_num;
  776. ucontrol->value.enumerated.item[0] =
  777. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  778. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  779. ch_num, slim_rx_cfg[ch_num].sample_rate,
  780. ucontrol->value.enumerated.item[0]);
  781. return 0;
  782. }
  783. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  784. struct snd_ctl_elem_value *ucontrol)
  785. {
  786. int ch_num = slim_get_port_idx(kcontrol);
  787. if (ch_num < 0)
  788. return ch_num;
  789. slim_rx_cfg[ch_num].sample_rate =
  790. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  791. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  792. ch_num, slim_rx_cfg[ch_num].sample_rate,
  793. ucontrol->value.enumerated.item[0]);
  794. return 0;
  795. }
  796. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  797. struct snd_ctl_elem_value *ucontrol)
  798. {
  799. int ch_num = slim_get_port_idx(kcontrol);
  800. if (ch_num < 0)
  801. return ch_num;
  802. ucontrol->value.enumerated.item[0] =
  803. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  804. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  805. ch_num, slim_tx_cfg[ch_num].sample_rate,
  806. ucontrol->value.enumerated.item[0]);
  807. return 0;
  808. }
  809. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  810. struct snd_ctl_elem_value *ucontrol)
  811. {
  812. int sample_rate = 0;
  813. int ch_num = slim_get_port_idx(kcontrol);
  814. if (ch_num < 0)
  815. return ch_num;
  816. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  817. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  818. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  819. __func__, sample_rate);
  820. return -EINVAL;
  821. }
  822. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  823. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  824. ch_num, slim_tx_cfg[ch_num].sample_rate,
  825. ucontrol->value.enumerated.item[0]);
  826. return 0;
  827. }
  828. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  829. struct snd_ctl_elem_value *ucontrol)
  830. {
  831. int ch_num = slim_get_port_idx(kcontrol);
  832. if (ch_num < 0)
  833. return ch_num;
  834. ucontrol->value.enumerated.item[0] =
  835. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  836. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  837. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  838. ucontrol->value.enumerated.item[0]);
  839. return 0;
  840. }
  841. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  842. struct snd_ctl_elem_value *ucontrol)
  843. {
  844. int ch_num = slim_get_port_idx(kcontrol);
  845. if (ch_num < 0)
  846. return ch_num;
  847. slim_rx_cfg[ch_num].bit_format =
  848. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  849. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  850. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  851. ucontrol->value.enumerated.item[0]);
  852. return 0;
  853. }
  854. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  855. struct snd_ctl_elem_value *ucontrol)
  856. {
  857. int ch_num = slim_get_port_idx(kcontrol);
  858. if (ch_num < 0)
  859. return ch_num;
  860. ucontrol->value.enumerated.item[0] =
  861. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  862. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  863. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  864. ucontrol->value.enumerated.item[0]);
  865. return 0;
  866. }
  867. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  868. struct snd_ctl_elem_value *ucontrol)
  869. {
  870. int ch_num = slim_get_port_idx(kcontrol);
  871. if (ch_num < 0)
  872. return ch_num;
  873. slim_tx_cfg[ch_num].bit_format =
  874. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  875. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  876. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  877. ucontrol->value.enumerated.item[0]);
  878. return 0;
  879. }
  880. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  881. struct snd_ctl_elem_value *ucontrol)
  882. {
  883. int ch_num = slim_get_port_idx(kcontrol);
  884. if (ch_num < 0)
  885. return ch_num;
  886. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  887. ch_num, slim_rx_cfg[ch_num].channels);
  888. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  889. return 0;
  890. }
  891. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  892. struct snd_ctl_elem_value *ucontrol)
  893. {
  894. int ch_num = slim_get_port_idx(kcontrol);
  895. if (ch_num < 0)
  896. return ch_num;
  897. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  898. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  899. ch_num, slim_rx_cfg[ch_num].channels);
  900. return 1;
  901. }
  902. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  903. struct snd_ctl_elem_value *ucontrol)
  904. {
  905. int ch_num = slim_get_port_idx(kcontrol);
  906. if (ch_num < 0)
  907. return ch_num;
  908. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  909. ch_num, slim_tx_cfg[ch_num].channels);
  910. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  911. return 0;
  912. }
  913. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  914. struct snd_ctl_elem_value *ucontrol)
  915. {
  916. int ch_num = slim_get_port_idx(kcontrol);
  917. if (ch_num < 0)
  918. return ch_num;
  919. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  920. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  921. ch_num, slim_tx_cfg[ch_num].channels);
  922. return 1;
  923. }
  924. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  925. struct snd_ctl_elem_value *ucontrol)
  926. {
  927. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  928. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  929. ucontrol->value.integer.value[0]);
  930. return 0;
  931. }
  932. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  933. struct snd_ctl_elem_value *ucontrol)
  934. {
  935. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  936. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  937. return 1;
  938. }
  939. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  940. struct snd_ctl_elem_value *ucontrol)
  941. {
  942. /*
  943. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  944. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  945. * value.
  946. */
  947. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  948. case SAMPLING_RATE_96KHZ:
  949. ucontrol->value.integer.value[0] = 5;
  950. break;
  951. case SAMPLING_RATE_88P2KHZ:
  952. ucontrol->value.integer.value[0] = 4;
  953. break;
  954. case SAMPLING_RATE_48KHZ:
  955. ucontrol->value.integer.value[0] = 3;
  956. break;
  957. case SAMPLING_RATE_44P1KHZ:
  958. ucontrol->value.integer.value[0] = 2;
  959. break;
  960. case SAMPLING_RATE_16KHZ:
  961. ucontrol->value.integer.value[0] = 1;
  962. break;
  963. case SAMPLING_RATE_8KHZ:
  964. default:
  965. ucontrol->value.integer.value[0] = 0;
  966. break;
  967. }
  968. pr_debug("%s: sample rate = %d", __func__,
  969. slim_rx_cfg[SLIM_RX_7].sample_rate);
  970. return 0;
  971. }
  972. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  973. struct snd_ctl_elem_value *ucontrol)
  974. {
  975. switch (ucontrol->value.integer.value[0]) {
  976. case 1:
  977. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  978. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  979. break;
  980. case 2:
  981. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  982. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  983. break;
  984. case 3:
  985. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  986. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  987. break;
  988. case 4:
  989. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  990. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  991. break;
  992. case 5:
  993. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  994. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  995. break;
  996. case 0:
  997. default:
  998. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  999. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1000. break;
  1001. }
  1002. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  1003. __func__,
  1004. slim_rx_cfg[SLIM_RX_7].sample_rate,
  1005. slim_tx_cfg[SLIM_TX_7].sample_rate,
  1006. ucontrol->value.enumerated.item[0]);
  1007. return 0;
  1008. }
  1009. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  1010. {
  1011. int idx = 0;
  1012. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  1013. sizeof("WSA_CDC_DMA_RX_0")))
  1014. idx = WSA_CDC_DMA_RX_0;
  1015. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  1016. sizeof("WSA_CDC_DMA_RX_0")))
  1017. idx = WSA_CDC_DMA_RX_1;
  1018. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  1019. sizeof("WSA_CDC_DMA_TX_0")))
  1020. idx = WSA_CDC_DMA_TX_0;
  1021. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  1022. sizeof("WSA_CDC_DMA_TX_1")))
  1023. idx = WSA_CDC_DMA_TX_1;
  1024. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  1025. sizeof("WSA_CDC_DMA_TX_2")))
  1026. idx = WSA_CDC_DMA_TX_2;
  1027. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  1028. sizeof("VA_CDC_DMA_TX_0")))
  1029. idx = VA_CDC_DMA_TX_0;
  1030. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  1031. sizeof("VA_CDC_DMA_TX_1")))
  1032. idx = VA_CDC_DMA_TX_1;
  1033. else {
  1034. pr_err("%s: unsupported port: %s\n",
  1035. __func__, kcontrol->id.name);
  1036. return -EINVAL;
  1037. }
  1038. return idx;
  1039. }
  1040. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1041. struct snd_ctl_elem_value *ucontrol)
  1042. {
  1043. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1044. if (ch_num < 0)
  1045. return ch_num;
  1046. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1047. cdc_dma_rx_cfg[ch_num].channels - 1);
  1048. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1049. return 0;
  1050. }
  1051. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1052. struct snd_ctl_elem_value *ucontrol)
  1053. {
  1054. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1055. if (ch_num < 0)
  1056. return ch_num;
  1057. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1058. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1059. cdc_dma_rx_cfg[ch_num].channels);
  1060. return 1;
  1061. }
  1062. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1063. struct snd_ctl_elem_value *ucontrol)
  1064. {
  1065. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1066. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1067. case SNDRV_PCM_FORMAT_S32_LE:
  1068. ucontrol->value.integer.value[0] = 3;
  1069. break;
  1070. case SNDRV_PCM_FORMAT_S24_3LE:
  1071. ucontrol->value.integer.value[0] = 2;
  1072. break;
  1073. case SNDRV_PCM_FORMAT_S24_LE:
  1074. ucontrol->value.integer.value[0] = 1;
  1075. break;
  1076. case SNDRV_PCM_FORMAT_S16_LE:
  1077. default:
  1078. ucontrol->value.integer.value[0] = 0;
  1079. break;
  1080. }
  1081. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1082. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1083. ucontrol->value.integer.value[0]);
  1084. return 0;
  1085. }
  1086. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1087. struct snd_ctl_elem_value *ucontrol)
  1088. {
  1089. int rc = 0;
  1090. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1091. switch (ucontrol->value.integer.value[0]) {
  1092. case 3:
  1093. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1094. break;
  1095. case 2:
  1096. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1097. break;
  1098. case 1:
  1099. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1100. break;
  1101. case 0:
  1102. default:
  1103. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1104. break;
  1105. }
  1106. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1107. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1108. ucontrol->value.integer.value[0]);
  1109. return rc;
  1110. }
  1111. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1112. {
  1113. int sample_rate_val = 0;
  1114. switch (sample_rate) {
  1115. case SAMPLING_RATE_8KHZ:
  1116. sample_rate_val = 0;
  1117. break;
  1118. case SAMPLING_RATE_16KHZ:
  1119. sample_rate_val = 1;
  1120. break;
  1121. case SAMPLING_RATE_32KHZ:
  1122. sample_rate_val = 2;
  1123. break;
  1124. case SAMPLING_RATE_44P1KHZ:
  1125. sample_rate_val = 3;
  1126. break;
  1127. case SAMPLING_RATE_48KHZ:
  1128. sample_rate_val = 4;
  1129. break;
  1130. case SAMPLING_RATE_88P2KHZ:
  1131. sample_rate_val = 5;
  1132. break;
  1133. case SAMPLING_RATE_96KHZ:
  1134. sample_rate_val = 6;
  1135. break;
  1136. case SAMPLING_RATE_176P4KHZ:
  1137. sample_rate_val = 7;
  1138. break;
  1139. case SAMPLING_RATE_192KHZ:
  1140. sample_rate_val = 8;
  1141. break;
  1142. case SAMPLING_RATE_352P8KHZ:
  1143. sample_rate_val = 9;
  1144. break;
  1145. case SAMPLING_RATE_384KHZ:
  1146. sample_rate_val = 10;
  1147. break;
  1148. default:
  1149. sample_rate_val = 4;
  1150. break;
  1151. }
  1152. return sample_rate_val;
  1153. }
  1154. static int cdc_dma_get_sample_rate(int value)
  1155. {
  1156. int sample_rate = 0;
  1157. switch (value) {
  1158. case 0:
  1159. sample_rate = SAMPLING_RATE_8KHZ;
  1160. break;
  1161. case 1:
  1162. sample_rate = SAMPLING_RATE_16KHZ;
  1163. break;
  1164. case 2:
  1165. sample_rate = SAMPLING_RATE_32KHZ;
  1166. break;
  1167. case 3:
  1168. sample_rate = SAMPLING_RATE_44P1KHZ;
  1169. break;
  1170. case 4:
  1171. sample_rate = SAMPLING_RATE_48KHZ;
  1172. break;
  1173. case 5:
  1174. sample_rate = SAMPLING_RATE_88P2KHZ;
  1175. break;
  1176. case 6:
  1177. sample_rate = SAMPLING_RATE_96KHZ;
  1178. break;
  1179. case 7:
  1180. sample_rate = SAMPLING_RATE_176P4KHZ;
  1181. break;
  1182. case 8:
  1183. sample_rate = SAMPLING_RATE_192KHZ;
  1184. break;
  1185. case 9:
  1186. sample_rate = SAMPLING_RATE_352P8KHZ;
  1187. break;
  1188. case 10:
  1189. sample_rate = SAMPLING_RATE_384KHZ;
  1190. break;
  1191. default:
  1192. sample_rate = SAMPLING_RATE_48KHZ;
  1193. break;
  1194. }
  1195. return sample_rate;
  1196. }
  1197. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1198. struct snd_ctl_elem_value *ucontrol)
  1199. {
  1200. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1201. if (ch_num < 0)
  1202. return ch_num;
  1203. ucontrol->value.enumerated.item[0] =
  1204. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1205. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1206. cdc_dma_rx_cfg[ch_num].sample_rate);
  1207. return 0;
  1208. }
  1209. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1210. struct snd_ctl_elem_value *ucontrol)
  1211. {
  1212. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1213. if (ch_num < 0)
  1214. return ch_num;
  1215. cdc_dma_rx_cfg[ch_num].sample_rate =
  1216. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1217. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1218. __func__, ucontrol->value.enumerated.item[0],
  1219. cdc_dma_rx_cfg[ch_num].sample_rate);
  1220. return 0;
  1221. }
  1222. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1223. struct snd_ctl_elem_value *ucontrol)
  1224. {
  1225. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1226. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1227. cdc_dma_tx_cfg[ch_num].channels);
  1228. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1229. return 0;
  1230. }
  1231. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1232. struct snd_ctl_elem_value *ucontrol)
  1233. {
  1234. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1235. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1236. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1237. cdc_dma_tx_cfg[ch_num].channels);
  1238. return 1;
  1239. }
  1240. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1241. struct snd_ctl_elem_value *ucontrol)
  1242. {
  1243. int sample_rate_val;
  1244. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1245. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1246. case SAMPLING_RATE_384KHZ:
  1247. sample_rate_val = 12;
  1248. break;
  1249. case SAMPLING_RATE_352P8KHZ:
  1250. sample_rate_val = 11;
  1251. break;
  1252. case SAMPLING_RATE_192KHZ:
  1253. sample_rate_val = 10;
  1254. break;
  1255. case SAMPLING_RATE_176P4KHZ:
  1256. sample_rate_val = 9;
  1257. break;
  1258. case SAMPLING_RATE_96KHZ:
  1259. sample_rate_val = 8;
  1260. break;
  1261. case SAMPLING_RATE_88P2KHZ:
  1262. sample_rate_val = 7;
  1263. break;
  1264. case SAMPLING_RATE_48KHZ:
  1265. sample_rate_val = 6;
  1266. break;
  1267. case SAMPLING_RATE_44P1KHZ:
  1268. sample_rate_val = 5;
  1269. break;
  1270. case SAMPLING_RATE_32KHZ:
  1271. sample_rate_val = 4;
  1272. break;
  1273. case SAMPLING_RATE_22P05KHZ:
  1274. sample_rate_val = 3;
  1275. break;
  1276. case SAMPLING_RATE_16KHZ:
  1277. sample_rate_val = 2;
  1278. break;
  1279. case SAMPLING_RATE_11P025KHZ:
  1280. sample_rate_val = 1;
  1281. break;
  1282. case SAMPLING_RATE_8KHZ:
  1283. sample_rate_val = 0;
  1284. break;
  1285. default:
  1286. sample_rate_val = 6;
  1287. break;
  1288. }
  1289. ucontrol->value.integer.value[0] = sample_rate_val;
  1290. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1291. cdc_dma_tx_cfg[ch_num].sample_rate);
  1292. return 0;
  1293. }
  1294. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1295. struct snd_ctl_elem_value *ucontrol)
  1296. {
  1297. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1298. switch (ucontrol->value.integer.value[0]) {
  1299. case 12:
  1300. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1301. break;
  1302. case 11:
  1303. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1304. break;
  1305. case 10:
  1306. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1307. break;
  1308. case 9:
  1309. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1310. break;
  1311. case 8:
  1312. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1313. break;
  1314. case 7:
  1315. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1316. break;
  1317. case 6:
  1318. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1319. break;
  1320. case 5:
  1321. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1322. break;
  1323. case 4:
  1324. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1325. break;
  1326. case 3:
  1327. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1328. break;
  1329. case 2:
  1330. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1331. break;
  1332. case 1:
  1333. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1334. break;
  1335. case 0:
  1336. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1337. break;
  1338. default:
  1339. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1340. break;
  1341. }
  1342. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1343. __func__, ucontrol->value.integer.value[0],
  1344. cdc_dma_tx_cfg[ch_num].sample_rate);
  1345. return 0;
  1346. }
  1347. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1348. struct snd_ctl_elem_value *ucontrol)
  1349. {
  1350. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1351. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1352. case SNDRV_PCM_FORMAT_S32_LE:
  1353. ucontrol->value.integer.value[0] = 3;
  1354. break;
  1355. case SNDRV_PCM_FORMAT_S24_3LE:
  1356. ucontrol->value.integer.value[0] = 2;
  1357. break;
  1358. case SNDRV_PCM_FORMAT_S24_LE:
  1359. ucontrol->value.integer.value[0] = 1;
  1360. break;
  1361. case SNDRV_PCM_FORMAT_S16_LE:
  1362. default:
  1363. ucontrol->value.integer.value[0] = 0;
  1364. break;
  1365. }
  1366. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1367. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1368. ucontrol->value.integer.value[0]);
  1369. return 0;
  1370. }
  1371. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1372. struct snd_ctl_elem_value *ucontrol)
  1373. {
  1374. int rc = 0;
  1375. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1376. switch (ucontrol->value.integer.value[0]) {
  1377. case 3:
  1378. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1379. break;
  1380. case 2:
  1381. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1382. break;
  1383. case 1:
  1384. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1385. break;
  1386. case 0:
  1387. default:
  1388. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1389. break;
  1390. }
  1391. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1392. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1393. ucontrol->value.integer.value[0]);
  1394. return rc;
  1395. }
  1396. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1397. struct snd_ctl_elem_value *ucontrol)
  1398. {
  1399. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1400. usb_rx_cfg.channels);
  1401. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1402. return 0;
  1403. }
  1404. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1405. struct snd_ctl_elem_value *ucontrol)
  1406. {
  1407. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1408. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1409. return 1;
  1410. }
  1411. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1412. struct snd_ctl_elem_value *ucontrol)
  1413. {
  1414. int sample_rate_val;
  1415. switch (usb_rx_cfg.sample_rate) {
  1416. case SAMPLING_RATE_384KHZ:
  1417. sample_rate_val = 12;
  1418. break;
  1419. case SAMPLING_RATE_352P8KHZ:
  1420. sample_rate_val = 11;
  1421. break;
  1422. case SAMPLING_RATE_192KHZ:
  1423. sample_rate_val = 10;
  1424. break;
  1425. case SAMPLING_RATE_176P4KHZ:
  1426. sample_rate_val = 9;
  1427. break;
  1428. case SAMPLING_RATE_96KHZ:
  1429. sample_rate_val = 8;
  1430. break;
  1431. case SAMPLING_RATE_88P2KHZ:
  1432. sample_rate_val = 7;
  1433. break;
  1434. case SAMPLING_RATE_48KHZ:
  1435. sample_rate_val = 6;
  1436. break;
  1437. case SAMPLING_RATE_44P1KHZ:
  1438. sample_rate_val = 5;
  1439. break;
  1440. case SAMPLING_RATE_32KHZ:
  1441. sample_rate_val = 4;
  1442. break;
  1443. case SAMPLING_RATE_22P05KHZ:
  1444. sample_rate_val = 3;
  1445. break;
  1446. case SAMPLING_RATE_16KHZ:
  1447. sample_rate_val = 2;
  1448. break;
  1449. case SAMPLING_RATE_11P025KHZ:
  1450. sample_rate_val = 1;
  1451. break;
  1452. case SAMPLING_RATE_8KHZ:
  1453. default:
  1454. sample_rate_val = 0;
  1455. break;
  1456. }
  1457. ucontrol->value.integer.value[0] = sample_rate_val;
  1458. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1459. usb_rx_cfg.sample_rate);
  1460. return 0;
  1461. }
  1462. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1463. struct snd_ctl_elem_value *ucontrol)
  1464. {
  1465. switch (ucontrol->value.integer.value[0]) {
  1466. case 12:
  1467. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1468. break;
  1469. case 11:
  1470. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1471. break;
  1472. case 10:
  1473. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1474. break;
  1475. case 9:
  1476. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1477. break;
  1478. case 8:
  1479. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1480. break;
  1481. case 7:
  1482. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1483. break;
  1484. case 6:
  1485. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1486. break;
  1487. case 5:
  1488. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1489. break;
  1490. case 4:
  1491. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1492. break;
  1493. case 3:
  1494. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1495. break;
  1496. case 2:
  1497. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1498. break;
  1499. case 1:
  1500. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1501. break;
  1502. case 0:
  1503. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1504. break;
  1505. default:
  1506. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1507. break;
  1508. }
  1509. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1510. __func__, ucontrol->value.integer.value[0],
  1511. usb_rx_cfg.sample_rate);
  1512. return 0;
  1513. }
  1514. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1515. struct snd_ctl_elem_value *ucontrol)
  1516. {
  1517. switch (usb_rx_cfg.bit_format) {
  1518. case SNDRV_PCM_FORMAT_S32_LE:
  1519. ucontrol->value.integer.value[0] = 3;
  1520. break;
  1521. case SNDRV_PCM_FORMAT_S24_3LE:
  1522. ucontrol->value.integer.value[0] = 2;
  1523. break;
  1524. case SNDRV_PCM_FORMAT_S24_LE:
  1525. ucontrol->value.integer.value[0] = 1;
  1526. break;
  1527. case SNDRV_PCM_FORMAT_S16_LE:
  1528. default:
  1529. ucontrol->value.integer.value[0] = 0;
  1530. break;
  1531. }
  1532. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1533. __func__, usb_rx_cfg.bit_format,
  1534. ucontrol->value.integer.value[0]);
  1535. return 0;
  1536. }
  1537. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1538. struct snd_ctl_elem_value *ucontrol)
  1539. {
  1540. int rc = 0;
  1541. switch (ucontrol->value.integer.value[0]) {
  1542. case 3:
  1543. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1544. break;
  1545. case 2:
  1546. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1547. break;
  1548. case 1:
  1549. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1550. break;
  1551. case 0:
  1552. default:
  1553. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1554. break;
  1555. }
  1556. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1557. __func__, usb_rx_cfg.bit_format,
  1558. ucontrol->value.integer.value[0]);
  1559. return rc;
  1560. }
  1561. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1562. struct snd_ctl_elem_value *ucontrol)
  1563. {
  1564. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1565. usb_tx_cfg.channels);
  1566. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1567. return 0;
  1568. }
  1569. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1570. struct snd_ctl_elem_value *ucontrol)
  1571. {
  1572. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1573. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1574. return 1;
  1575. }
  1576. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1577. struct snd_ctl_elem_value *ucontrol)
  1578. {
  1579. int sample_rate_val;
  1580. switch (usb_tx_cfg.sample_rate) {
  1581. case SAMPLING_RATE_384KHZ:
  1582. sample_rate_val = 12;
  1583. break;
  1584. case SAMPLING_RATE_352P8KHZ:
  1585. sample_rate_val = 11;
  1586. break;
  1587. case SAMPLING_RATE_192KHZ:
  1588. sample_rate_val = 10;
  1589. break;
  1590. case SAMPLING_RATE_176P4KHZ:
  1591. sample_rate_val = 9;
  1592. break;
  1593. case SAMPLING_RATE_96KHZ:
  1594. sample_rate_val = 8;
  1595. break;
  1596. case SAMPLING_RATE_88P2KHZ:
  1597. sample_rate_val = 7;
  1598. break;
  1599. case SAMPLING_RATE_48KHZ:
  1600. sample_rate_val = 6;
  1601. break;
  1602. case SAMPLING_RATE_44P1KHZ:
  1603. sample_rate_val = 5;
  1604. break;
  1605. case SAMPLING_RATE_32KHZ:
  1606. sample_rate_val = 4;
  1607. break;
  1608. case SAMPLING_RATE_22P05KHZ:
  1609. sample_rate_val = 3;
  1610. break;
  1611. case SAMPLING_RATE_16KHZ:
  1612. sample_rate_val = 2;
  1613. break;
  1614. case SAMPLING_RATE_11P025KHZ:
  1615. sample_rate_val = 1;
  1616. break;
  1617. case SAMPLING_RATE_8KHZ:
  1618. sample_rate_val = 0;
  1619. break;
  1620. default:
  1621. sample_rate_val = 6;
  1622. break;
  1623. }
  1624. ucontrol->value.integer.value[0] = sample_rate_val;
  1625. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1626. usb_tx_cfg.sample_rate);
  1627. return 0;
  1628. }
  1629. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1630. struct snd_ctl_elem_value *ucontrol)
  1631. {
  1632. switch (ucontrol->value.integer.value[0]) {
  1633. case 12:
  1634. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1635. break;
  1636. case 11:
  1637. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1638. break;
  1639. case 10:
  1640. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1641. break;
  1642. case 9:
  1643. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1644. break;
  1645. case 8:
  1646. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1647. break;
  1648. case 7:
  1649. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1650. break;
  1651. case 6:
  1652. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1653. break;
  1654. case 5:
  1655. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1656. break;
  1657. case 4:
  1658. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1659. break;
  1660. case 3:
  1661. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1662. break;
  1663. case 2:
  1664. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1665. break;
  1666. case 1:
  1667. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1668. break;
  1669. case 0:
  1670. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1671. break;
  1672. default:
  1673. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1674. break;
  1675. }
  1676. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1677. __func__, ucontrol->value.integer.value[0],
  1678. usb_tx_cfg.sample_rate);
  1679. return 0;
  1680. }
  1681. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1682. struct snd_ctl_elem_value *ucontrol)
  1683. {
  1684. switch (usb_tx_cfg.bit_format) {
  1685. case SNDRV_PCM_FORMAT_S32_LE:
  1686. ucontrol->value.integer.value[0] = 3;
  1687. break;
  1688. case SNDRV_PCM_FORMAT_S24_3LE:
  1689. ucontrol->value.integer.value[0] = 2;
  1690. break;
  1691. case SNDRV_PCM_FORMAT_S24_LE:
  1692. ucontrol->value.integer.value[0] = 1;
  1693. break;
  1694. case SNDRV_PCM_FORMAT_S16_LE:
  1695. default:
  1696. ucontrol->value.integer.value[0] = 0;
  1697. break;
  1698. }
  1699. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1700. __func__, usb_tx_cfg.bit_format,
  1701. ucontrol->value.integer.value[0]);
  1702. return 0;
  1703. }
  1704. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1705. struct snd_ctl_elem_value *ucontrol)
  1706. {
  1707. int rc = 0;
  1708. switch (ucontrol->value.integer.value[0]) {
  1709. case 3:
  1710. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1711. break;
  1712. case 2:
  1713. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1714. break;
  1715. case 1:
  1716. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1717. break;
  1718. case 0:
  1719. default:
  1720. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1721. break;
  1722. }
  1723. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1724. __func__, usb_tx_cfg.bit_format,
  1725. ucontrol->value.integer.value[0]);
  1726. return rc;
  1727. }
  1728. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1729. struct snd_ctl_elem_value *ucontrol)
  1730. {
  1731. pr_debug("%s: proxy_rx channels = %d\n",
  1732. __func__, proxy_rx_cfg.channels);
  1733. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1734. return 0;
  1735. }
  1736. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1737. struct snd_ctl_elem_value *ucontrol)
  1738. {
  1739. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1740. pr_debug("%s: proxy_rx channels = %d\n",
  1741. __func__, proxy_rx_cfg.channels);
  1742. return 1;
  1743. }
  1744. static int tdm_get_sample_rate(int value)
  1745. {
  1746. int sample_rate = 0;
  1747. switch (value) {
  1748. case 0:
  1749. sample_rate = SAMPLING_RATE_8KHZ;
  1750. break;
  1751. case 1:
  1752. sample_rate = SAMPLING_RATE_16KHZ;
  1753. break;
  1754. case 2:
  1755. sample_rate = SAMPLING_RATE_32KHZ;
  1756. break;
  1757. case 3:
  1758. sample_rate = SAMPLING_RATE_48KHZ;
  1759. break;
  1760. case 4:
  1761. sample_rate = SAMPLING_RATE_176P4KHZ;
  1762. break;
  1763. case 5:
  1764. sample_rate = SAMPLING_RATE_352P8KHZ;
  1765. break;
  1766. default:
  1767. sample_rate = SAMPLING_RATE_48KHZ;
  1768. break;
  1769. }
  1770. return sample_rate;
  1771. }
  1772. static int aux_pcm_get_sample_rate(int value)
  1773. {
  1774. int sample_rate;
  1775. switch (value) {
  1776. case 1:
  1777. sample_rate = SAMPLING_RATE_16KHZ;
  1778. break;
  1779. case 0:
  1780. default:
  1781. sample_rate = SAMPLING_RATE_8KHZ;
  1782. break;
  1783. }
  1784. return sample_rate;
  1785. }
  1786. static int tdm_get_sample_rate_val(int sample_rate)
  1787. {
  1788. int sample_rate_val = 0;
  1789. switch (sample_rate) {
  1790. case SAMPLING_RATE_8KHZ:
  1791. sample_rate_val = 0;
  1792. break;
  1793. case SAMPLING_RATE_16KHZ:
  1794. sample_rate_val = 1;
  1795. break;
  1796. case SAMPLING_RATE_32KHZ:
  1797. sample_rate_val = 2;
  1798. break;
  1799. case SAMPLING_RATE_48KHZ:
  1800. sample_rate_val = 3;
  1801. break;
  1802. case SAMPLING_RATE_176P4KHZ:
  1803. sample_rate_val = 4;
  1804. break;
  1805. case SAMPLING_RATE_352P8KHZ:
  1806. sample_rate_val = 5;
  1807. break;
  1808. default:
  1809. sample_rate_val = 3;
  1810. break;
  1811. }
  1812. return sample_rate_val;
  1813. }
  1814. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1815. {
  1816. int sample_rate_val;
  1817. switch (sample_rate) {
  1818. case SAMPLING_RATE_16KHZ:
  1819. sample_rate_val = 1;
  1820. break;
  1821. case SAMPLING_RATE_8KHZ:
  1822. default:
  1823. sample_rate_val = 0;
  1824. break;
  1825. }
  1826. return sample_rate_val;
  1827. }
  1828. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1829. struct tdm_port *port)
  1830. {
  1831. if (port) {
  1832. if (strnstr(kcontrol->id.name, "PRI",
  1833. sizeof(kcontrol->id.name))) {
  1834. port->mode = TDM_PRI;
  1835. } else if (strnstr(kcontrol->id.name, "SEC",
  1836. sizeof(kcontrol->id.name))) {
  1837. port->mode = TDM_SEC;
  1838. } else if (strnstr(kcontrol->id.name, "TERT",
  1839. sizeof(kcontrol->id.name))) {
  1840. port->mode = TDM_TERT;
  1841. } else if (strnstr(kcontrol->id.name, "QUAT",
  1842. sizeof(kcontrol->id.name))) {
  1843. port->mode = TDM_QUAT;
  1844. } else if (strnstr(kcontrol->id.name, "QUIN",
  1845. sizeof(kcontrol->id.name))) {
  1846. port->mode = TDM_QUIN;
  1847. } else {
  1848. pr_err("%s: unsupported mode in: %s",
  1849. __func__, kcontrol->id.name);
  1850. return -EINVAL;
  1851. }
  1852. if (strnstr(kcontrol->id.name, "RX_0",
  1853. sizeof(kcontrol->id.name)) ||
  1854. strnstr(kcontrol->id.name, "TX_0",
  1855. sizeof(kcontrol->id.name))) {
  1856. port->channel = TDM_0;
  1857. } else if (strnstr(kcontrol->id.name, "RX_1",
  1858. sizeof(kcontrol->id.name)) ||
  1859. strnstr(kcontrol->id.name, "TX_1",
  1860. sizeof(kcontrol->id.name))) {
  1861. port->channel = TDM_1;
  1862. } else if (strnstr(kcontrol->id.name, "RX_2",
  1863. sizeof(kcontrol->id.name)) ||
  1864. strnstr(kcontrol->id.name, "TX_2",
  1865. sizeof(kcontrol->id.name))) {
  1866. port->channel = TDM_2;
  1867. } else if (strnstr(kcontrol->id.name, "RX_3",
  1868. sizeof(kcontrol->id.name)) ||
  1869. strnstr(kcontrol->id.name, "TX_3",
  1870. sizeof(kcontrol->id.name))) {
  1871. port->channel = TDM_3;
  1872. } else if (strnstr(kcontrol->id.name, "RX_4",
  1873. sizeof(kcontrol->id.name)) ||
  1874. strnstr(kcontrol->id.name, "TX_4",
  1875. sizeof(kcontrol->id.name))) {
  1876. port->channel = TDM_4;
  1877. } else if (strnstr(kcontrol->id.name, "RX_5",
  1878. sizeof(kcontrol->id.name)) ||
  1879. strnstr(kcontrol->id.name, "TX_5",
  1880. sizeof(kcontrol->id.name))) {
  1881. port->channel = TDM_5;
  1882. } else if (strnstr(kcontrol->id.name, "RX_6",
  1883. sizeof(kcontrol->id.name)) ||
  1884. strnstr(kcontrol->id.name, "TX_6",
  1885. sizeof(kcontrol->id.name))) {
  1886. port->channel = TDM_6;
  1887. } else if (strnstr(kcontrol->id.name, "RX_7",
  1888. sizeof(kcontrol->id.name)) ||
  1889. strnstr(kcontrol->id.name, "TX_7",
  1890. sizeof(kcontrol->id.name))) {
  1891. port->channel = TDM_7;
  1892. } else {
  1893. pr_err("%s: unsupported channel in: %s",
  1894. __func__, kcontrol->id.name);
  1895. return -EINVAL;
  1896. }
  1897. } else
  1898. return -EINVAL;
  1899. return 0;
  1900. }
  1901. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1902. struct snd_ctl_elem_value *ucontrol)
  1903. {
  1904. struct tdm_port port;
  1905. int ret = tdm_get_port_idx(kcontrol, &port);
  1906. if (ret) {
  1907. pr_err("%s: unsupported control: %s",
  1908. __func__, kcontrol->id.name);
  1909. } else {
  1910. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1911. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1912. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1913. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1914. ucontrol->value.enumerated.item[0]);
  1915. }
  1916. return ret;
  1917. }
  1918. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1919. struct snd_ctl_elem_value *ucontrol)
  1920. {
  1921. struct tdm_port port;
  1922. int ret = tdm_get_port_idx(kcontrol, &port);
  1923. if (ret) {
  1924. pr_err("%s: unsupported control: %s",
  1925. __func__, kcontrol->id.name);
  1926. } else {
  1927. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1928. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1929. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1930. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1931. ucontrol->value.enumerated.item[0]);
  1932. }
  1933. return ret;
  1934. }
  1935. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1936. struct snd_ctl_elem_value *ucontrol)
  1937. {
  1938. struct tdm_port port;
  1939. int ret = tdm_get_port_idx(kcontrol, &port);
  1940. if (ret) {
  1941. pr_err("%s: unsupported control: %s",
  1942. __func__, kcontrol->id.name);
  1943. } else {
  1944. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1945. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1946. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1947. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1948. ucontrol->value.enumerated.item[0]);
  1949. }
  1950. return ret;
  1951. }
  1952. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1953. struct snd_ctl_elem_value *ucontrol)
  1954. {
  1955. struct tdm_port port;
  1956. int ret = tdm_get_port_idx(kcontrol, &port);
  1957. if (ret) {
  1958. pr_err("%s: unsupported control: %s",
  1959. __func__, kcontrol->id.name);
  1960. } else {
  1961. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1962. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1963. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1964. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1965. ucontrol->value.enumerated.item[0]);
  1966. }
  1967. return ret;
  1968. }
  1969. static int tdm_get_format(int value)
  1970. {
  1971. int format = 0;
  1972. switch (value) {
  1973. case 0:
  1974. format = SNDRV_PCM_FORMAT_S16_LE;
  1975. break;
  1976. case 1:
  1977. format = SNDRV_PCM_FORMAT_S24_LE;
  1978. break;
  1979. case 2:
  1980. format = SNDRV_PCM_FORMAT_S32_LE;
  1981. break;
  1982. default:
  1983. format = SNDRV_PCM_FORMAT_S16_LE;
  1984. break;
  1985. }
  1986. return format;
  1987. }
  1988. static int tdm_get_format_val(int format)
  1989. {
  1990. int value = 0;
  1991. switch (format) {
  1992. case SNDRV_PCM_FORMAT_S16_LE:
  1993. value = 0;
  1994. break;
  1995. case SNDRV_PCM_FORMAT_S24_LE:
  1996. value = 1;
  1997. break;
  1998. case SNDRV_PCM_FORMAT_S32_LE:
  1999. value = 2;
  2000. break;
  2001. default:
  2002. value = 0;
  2003. break;
  2004. }
  2005. return value;
  2006. }
  2007. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  2008. struct snd_ctl_elem_value *ucontrol)
  2009. {
  2010. struct tdm_port port;
  2011. int ret = tdm_get_port_idx(kcontrol, &port);
  2012. if (ret) {
  2013. pr_err("%s: unsupported control: %s",
  2014. __func__, kcontrol->id.name);
  2015. } else {
  2016. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2017. tdm_rx_cfg[port.mode][port.channel].bit_format);
  2018. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2019. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2020. ucontrol->value.enumerated.item[0]);
  2021. }
  2022. return ret;
  2023. }
  2024. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  2025. struct snd_ctl_elem_value *ucontrol)
  2026. {
  2027. struct tdm_port port;
  2028. int ret = tdm_get_port_idx(kcontrol, &port);
  2029. if (ret) {
  2030. pr_err("%s: unsupported control: %s",
  2031. __func__, kcontrol->id.name);
  2032. } else {
  2033. tdm_rx_cfg[port.mode][port.channel].bit_format =
  2034. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2035. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2036. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2037. ucontrol->value.enumerated.item[0]);
  2038. }
  2039. return ret;
  2040. }
  2041. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  2042. struct snd_ctl_elem_value *ucontrol)
  2043. {
  2044. struct tdm_port port;
  2045. int ret = tdm_get_port_idx(kcontrol, &port);
  2046. if (ret) {
  2047. pr_err("%s: unsupported control: %s",
  2048. __func__, kcontrol->id.name);
  2049. } else {
  2050. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2051. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2052. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2053. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2054. ucontrol->value.enumerated.item[0]);
  2055. }
  2056. return ret;
  2057. }
  2058. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2059. struct snd_ctl_elem_value *ucontrol)
  2060. {
  2061. struct tdm_port port;
  2062. int ret = tdm_get_port_idx(kcontrol, &port);
  2063. if (ret) {
  2064. pr_err("%s: unsupported control: %s",
  2065. __func__, kcontrol->id.name);
  2066. } else {
  2067. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2068. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2069. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2070. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2071. ucontrol->value.enumerated.item[0]);
  2072. }
  2073. return ret;
  2074. }
  2075. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2076. struct snd_ctl_elem_value *ucontrol)
  2077. {
  2078. struct tdm_port port;
  2079. int ret = tdm_get_port_idx(kcontrol, &port);
  2080. if (ret) {
  2081. pr_err("%s: unsupported control: %s",
  2082. __func__, kcontrol->id.name);
  2083. } else {
  2084. ucontrol->value.enumerated.item[0] =
  2085. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2086. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2087. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2088. ucontrol->value.enumerated.item[0]);
  2089. }
  2090. return ret;
  2091. }
  2092. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2093. struct snd_ctl_elem_value *ucontrol)
  2094. {
  2095. struct tdm_port port;
  2096. int ret = tdm_get_port_idx(kcontrol, &port);
  2097. if (ret) {
  2098. pr_err("%s: unsupported control: %s",
  2099. __func__, kcontrol->id.name);
  2100. } else {
  2101. tdm_rx_cfg[port.mode][port.channel].channels =
  2102. ucontrol->value.enumerated.item[0] + 1;
  2103. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2104. tdm_rx_cfg[port.mode][port.channel].channels,
  2105. ucontrol->value.enumerated.item[0] + 1);
  2106. }
  2107. return ret;
  2108. }
  2109. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2110. struct snd_ctl_elem_value *ucontrol)
  2111. {
  2112. struct tdm_port port;
  2113. int ret = tdm_get_port_idx(kcontrol, &port);
  2114. if (ret) {
  2115. pr_err("%s: unsupported control: %s",
  2116. __func__, kcontrol->id.name);
  2117. } else {
  2118. ucontrol->value.enumerated.item[0] =
  2119. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2120. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2121. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2122. ucontrol->value.enumerated.item[0]);
  2123. }
  2124. return ret;
  2125. }
  2126. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2127. struct snd_ctl_elem_value *ucontrol)
  2128. {
  2129. struct tdm_port port;
  2130. int ret = tdm_get_port_idx(kcontrol, &port);
  2131. if (ret) {
  2132. pr_err("%s: unsupported control: %s",
  2133. __func__, kcontrol->id.name);
  2134. } else {
  2135. tdm_tx_cfg[port.mode][port.channel].channels =
  2136. ucontrol->value.enumerated.item[0] + 1;
  2137. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2138. tdm_tx_cfg[port.mode][port.channel].channels,
  2139. ucontrol->value.enumerated.item[0] + 1);
  2140. }
  2141. return ret;
  2142. }
  2143. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2144. {
  2145. int idx;
  2146. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2147. sizeof("PRIM_AUX_PCM")))
  2148. idx = PRIM_AUX_PCM;
  2149. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2150. sizeof("SEC_AUX_PCM")))
  2151. idx = SEC_AUX_PCM;
  2152. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2153. sizeof("TERT_AUX_PCM")))
  2154. idx = TERT_AUX_PCM;
  2155. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2156. sizeof("QUAT_AUX_PCM")))
  2157. idx = QUAT_AUX_PCM;
  2158. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2159. sizeof("QUIN_AUX_PCM")))
  2160. idx = QUIN_AUX_PCM;
  2161. else {
  2162. pr_err("%s: unsupported port: %s",
  2163. __func__, kcontrol->id.name);
  2164. idx = -EINVAL;
  2165. }
  2166. return idx;
  2167. }
  2168. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2169. struct snd_ctl_elem_value *ucontrol)
  2170. {
  2171. int idx = aux_pcm_get_port_idx(kcontrol);
  2172. if (idx < 0)
  2173. return idx;
  2174. aux_pcm_rx_cfg[idx].sample_rate =
  2175. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2176. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2177. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2178. ucontrol->value.enumerated.item[0]);
  2179. return 0;
  2180. }
  2181. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2182. struct snd_ctl_elem_value *ucontrol)
  2183. {
  2184. int idx = aux_pcm_get_port_idx(kcontrol);
  2185. if (idx < 0)
  2186. return idx;
  2187. ucontrol->value.enumerated.item[0] =
  2188. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2189. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2190. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2191. ucontrol->value.enumerated.item[0]);
  2192. return 0;
  2193. }
  2194. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2195. struct snd_ctl_elem_value *ucontrol)
  2196. {
  2197. int idx = aux_pcm_get_port_idx(kcontrol);
  2198. if (idx < 0)
  2199. return idx;
  2200. aux_pcm_tx_cfg[idx].sample_rate =
  2201. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2202. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2203. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2204. ucontrol->value.enumerated.item[0]);
  2205. return 0;
  2206. }
  2207. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2208. struct snd_ctl_elem_value *ucontrol)
  2209. {
  2210. int idx = aux_pcm_get_port_idx(kcontrol);
  2211. if (idx < 0)
  2212. return idx;
  2213. ucontrol->value.enumerated.item[0] =
  2214. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2215. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2216. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2217. ucontrol->value.enumerated.item[0]);
  2218. return 0;
  2219. }
  2220. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2221. {
  2222. int idx;
  2223. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2224. sizeof("PRIM_MI2S_RX")))
  2225. idx = PRIM_MI2S;
  2226. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2227. sizeof("SEC_MI2S_RX")))
  2228. idx = SEC_MI2S;
  2229. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2230. sizeof("TERT_MI2S_RX")))
  2231. idx = TERT_MI2S;
  2232. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2233. sizeof("QUAT_MI2S_RX")))
  2234. idx = QUAT_MI2S;
  2235. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2236. sizeof("QUIN_MI2S_RX")))
  2237. idx = QUIN_MI2S;
  2238. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2239. sizeof("PRIM_MI2S_TX")))
  2240. idx = PRIM_MI2S;
  2241. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2242. sizeof("SEC_MI2S_TX")))
  2243. idx = SEC_MI2S;
  2244. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2245. sizeof("TERT_MI2S_TX")))
  2246. idx = TERT_MI2S;
  2247. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2248. sizeof("QUAT_MI2S_TX")))
  2249. idx = QUAT_MI2S;
  2250. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2251. sizeof("QUIN_MI2S_TX")))
  2252. idx = QUIN_MI2S;
  2253. else {
  2254. pr_err("%s: unsupported channel: %s",
  2255. __func__, kcontrol->id.name);
  2256. idx = -EINVAL;
  2257. }
  2258. return idx;
  2259. }
  2260. static int mi2s_get_sample_rate_val(int sample_rate)
  2261. {
  2262. int sample_rate_val;
  2263. switch (sample_rate) {
  2264. case SAMPLING_RATE_8KHZ:
  2265. sample_rate_val = 0;
  2266. break;
  2267. case SAMPLING_RATE_11P025KHZ:
  2268. sample_rate_val = 1;
  2269. break;
  2270. case SAMPLING_RATE_16KHZ:
  2271. sample_rate_val = 2;
  2272. break;
  2273. case SAMPLING_RATE_22P05KHZ:
  2274. sample_rate_val = 3;
  2275. break;
  2276. case SAMPLING_RATE_32KHZ:
  2277. sample_rate_val = 4;
  2278. break;
  2279. case SAMPLING_RATE_44P1KHZ:
  2280. sample_rate_val = 5;
  2281. break;
  2282. case SAMPLING_RATE_48KHZ:
  2283. sample_rate_val = 6;
  2284. break;
  2285. case SAMPLING_RATE_96KHZ:
  2286. sample_rate_val = 7;
  2287. break;
  2288. case SAMPLING_RATE_192KHZ:
  2289. sample_rate_val = 8;
  2290. break;
  2291. default:
  2292. sample_rate_val = 6;
  2293. break;
  2294. }
  2295. return sample_rate_val;
  2296. }
  2297. static int mi2s_get_sample_rate(int value)
  2298. {
  2299. int sample_rate;
  2300. switch (value) {
  2301. case 0:
  2302. sample_rate = SAMPLING_RATE_8KHZ;
  2303. break;
  2304. case 1:
  2305. sample_rate = SAMPLING_RATE_11P025KHZ;
  2306. break;
  2307. case 2:
  2308. sample_rate = SAMPLING_RATE_16KHZ;
  2309. break;
  2310. case 3:
  2311. sample_rate = SAMPLING_RATE_22P05KHZ;
  2312. break;
  2313. case 4:
  2314. sample_rate = SAMPLING_RATE_32KHZ;
  2315. break;
  2316. case 5:
  2317. sample_rate = SAMPLING_RATE_44P1KHZ;
  2318. break;
  2319. case 6:
  2320. sample_rate = SAMPLING_RATE_48KHZ;
  2321. break;
  2322. case 7:
  2323. sample_rate = SAMPLING_RATE_96KHZ;
  2324. break;
  2325. case 8:
  2326. sample_rate = SAMPLING_RATE_192KHZ;
  2327. break;
  2328. default:
  2329. sample_rate = SAMPLING_RATE_48KHZ;
  2330. break;
  2331. }
  2332. return sample_rate;
  2333. }
  2334. static int mi2s_auxpcm_get_format(int value)
  2335. {
  2336. int format;
  2337. switch (value) {
  2338. case 0:
  2339. format = SNDRV_PCM_FORMAT_S16_LE;
  2340. break;
  2341. case 1:
  2342. format = SNDRV_PCM_FORMAT_S24_LE;
  2343. break;
  2344. case 2:
  2345. format = SNDRV_PCM_FORMAT_S24_3LE;
  2346. break;
  2347. case 3:
  2348. format = SNDRV_PCM_FORMAT_S32_LE;
  2349. break;
  2350. default:
  2351. format = SNDRV_PCM_FORMAT_S16_LE;
  2352. break;
  2353. }
  2354. return format;
  2355. }
  2356. static int mi2s_auxpcm_get_format_value(int format)
  2357. {
  2358. int value;
  2359. switch (format) {
  2360. case SNDRV_PCM_FORMAT_S16_LE:
  2361. value = 0;
  2362. break;
  2363. case SNDRV_PCM_FORMAT_S24_LE:
  2364. value = 1;
  2365. break;
  2366. case SNDRV_PCM_FORMAT_S24_3LE:
  2367. value = 2;
  2368. break;
  2369. case SNDRV_PCM_FORMAT_S32_LE:
  2370. value = 3;
  2371. break;
  2372. default:
  2373. value = 0;
  2374. break;
  2375. }
  2376. return value;
  2377. }
  2378. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2379. struct snd_ctl_elem_value *ucontrol)
  2380. {
  2381. int idx = mi2s_get_port_idx(kcontrol);
  2382. if (idx < 0)
  2383. return idx;
  2384. mi2s_rx_cfg[idx].sample_rate =
  2385. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2386. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2387. idx, mi2s_rx_cfg[idx].sample_rate,
  2388. ucontrol->value.enumerated.item[0]);
  2389. return 0;
  2390. }
  2391. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2392. struct snd_ctl_elem_value *ucontrol)
  2393. {
  2394. int idx = mi2s_get_port_idx(kcontrol);
  2395. if (idx < 0)
  2396. return idx;
  2397. ucontrol->value.enumerated.item[0] =
  2398. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2399. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2400. idx, mi2s_rx_cfg[idx].sample_rate,
  2401. ucontrol->value.enumerated.item[0]);
  2402. return 0;
  2403. }
  2404. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2405. struct snd_ctl_elem_value *ucontrol)
  2406. {
  2407. int idx = mi2s_get_port_idx(kcontrol);
  2408. if (idx < 0)
  2409. return idx;
  2410. mi2s_tx_cfg[idx].sample_rate =
  2411. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2412. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2413. idx, mi2s_tx_cfg[idx].sample_rate,
  2414. ucontrol->value.enumerated.item[0]);
  2415. return 0;
  2416. }
  2417. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2418. struct snd_ctl_elem_value *ucontrol)
  2419. {
  2420. int idx = mi2s_get_port_idx(kcontrol);
  2421. if (idx < 0)
  2422. return idx;
  2423. ucontrol->value.enumerated.item[0] =
  2424. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2425. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2426. idx, mi2s_tx_cfg[idx].sample_rate,
  2427. ucontrol->value.enumerated.item[0]);
  2428. return 0;
  2429. }
  2430. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2431. struct snd_ctl_elem_value *ucontrol)
  2432. {
  2433. int idx = mi2s_get_port_idx(kcontrol);
  2434. if (idx < 0)
  2435. return idx;
  2436. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2437. idx, mi2s_rx_cfg[idx].channels);
  2438. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2439. return 0;
  2440. }
  2441. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2442. struct snd_ctl_elem_value *ucontrol)
  2443. {
  2444. int idx = mi2s_get_port_idx(kcontrol);
  2445. if (idx < 0)
  2446. return idx;
  2447. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2448. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2449. idx, mi2s_rx_cfg[idx].channels);
  2450. return 1;
  2451. }
  2452. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2453. struct snd_ctl_elem_value *ucontrol)
  2454. {
  2455. int idx = mi2s_get_port_idx(kcontrol);
  2456. if (idx < 0)
  2457. return idx;
  2458. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2459. idx, mi2s_tx_cfg[idx].channels);
  2460. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2461. return 0;
  2462. }
  2463. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2464. struct snd_ctl_elem_value *ucontrol)
  2465. {
  2466. int idx = mi2s_get_port_idx(kcontrol);
  2467. if (idx < 0)
  2468. return idx;
  2469. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2470. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2471. idx, mi2s_tx_cfg[idx].channels);
  2472. return 1;
  2473. }
  2474. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2475. struct snd_ctl_elem_value *ucontrol)
  2476. {
  2477. int idx = mi2s_get_port_idx(kcontrol);
  2478. if (idx < 0)
  2479. return idx;
  2480. ucontrol->value.enumerated.item[0] =
  2481. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2482. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2483. idx, mi2s_rx_cfg[idx].bit_format,
  2484. ucontrol->value.enumerated.item[0]);
  2485. return 0;
  2486. }
  2487. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2488. struct snd_ctl_elem_value *ucontrol)
  2489. {
  2490. int idx = mi2s_get_port_idx(kcontrol);
  2491. if (idx < 0)
  2492. return idx;
  2493. mi2s_rx_cfg[idx].bit_format =
  2494. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2495. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2496. idx, mi2s_rx_cfg[idx].bit_format,
  2497. ucontrol->value.enumerated.item[0]);
  2498. return 0;
  2499. }
  2500. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2501. struct snd_ctl_elem_value *ucontrol)
  2502. {
  2503. int idx = mi2s_get_port_idx(kcontrol);
  2504. if (idx < 0)
  2505. return idx;
  2506. ucontrol->value.enumerated.item[0] =
  2507. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2508. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2509. idx, mi2s_tx_cfg[idx].bit_format,
  2510. ucontrol->value.enumerated.item[0]);
  2511. return 0;
  2512. }
  2513. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2514. struct snd_ctl_elem_value *ucontrol)
  2515. {
  2516. int idx = mi2s_get_port_idx(kcontrol);
  2517. if (idx < 0)
  2518. return idx;
  2519. mi2s_tx_cfg[idx].bit_format =
  2520. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2521. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2522. idx, mi2s_tx_cfg[idx].bit_format,
  2523. ucontrol->value.enumerated.item[0]);
  2524. return 0;
  2525. }
  2526. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2527. struct snd_ctl_elem_value *ucontrol)
  2528. {
  2529. int idx = aux_pcm_get_port_idx(kcontrol);
  2530. if (idx < 0)
  2531. return idx;
  2532. ucontrol->value.enumerated.item[0] =
  2533. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2534. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2535. idx, aux_pcm_rx_cfg[idx].bit_format,
  2536. ucontrol->value.enumerated.item[0]);
  2537. return 0;
  2538. }
  2539. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2540. struct snd_ctl_elem_value *ucontrol)
  2541. {
  2542. int idx = aux_pcm_get_port_idx(kcontrol);
  2543. if (idx < 0)
  2544. return idx;
  2545. aux_pcm_rx_cfg[idx].bit_format =
  2546. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2547. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2548. idx, aux_pcm_rx_cfg[idx].bit_format,
  2549. ucontrol->value.enumerated.item[0]);
  2550. return 0;
  2551. }
  2552. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2553. struct snd_ctl_elem_value *ucontrol)
  2554. {
  2555. int idx = aux_pcm_get_port_idx(kcontrol);
  2556. if (idx < 0)
  2557. return idx;
  2558. ucontrol->value.enumerated.item[0] =
  2559. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2560. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2561. idx, aux_pcm_tx_cfg[idx].bit_format,
  2562. ucontrol->value.enumerated.item[0]);
  2563. return 0;
  2564. }
  2565. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2566. struct snd_ctl_elem_value *ucontrol)
  2567. {
  2568. int idx = aux_pcm_get_port_idx(kcontrol);
  2569. if (idx < 0)
  2570. return idx;
  2571. aux_pcm_tx_cfg[idx].bit_format =
  2572. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2573. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2574. idx, aux_pcm_tx_cfg[idx].bit_format,
  2575. ucontrol->value.enumerated.item[0]);
  2576. return 0;
  2577. }
  2578. static int spdif_get_port_idx(struct snd_kcontrol *kcontrol)
  2579. {
  2580. int idx;
  2581. if (strnstr(kcontrol->id.name, "PRIM_SPDIF_RX",
  2582. sizeof("PRIM_SPDIF_RX")))
  2583. idx = PRIM_SPDIF_RX;
  2584. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_RX",
  2585. sizeof("SEC_SPDIF_RX")))
  2586. idx = SEC_SPDIF_RX;
  2587. else if (strnstr(kcontrol->id.name, "PRIM_SPDIF_TX",
  2588. sizeof("PRIM_SPDIF_TX")))
  2589. idx = PRIM_SPDIF_TX;
  2590. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_TX",
  2591. sizeof("SEC_SPDIF_TX")))
  2592. idx = SEC_SPDIF_TX;
  2593. else {
  2594. pr_err("%s: unsupported channel: %s",
  2595. __func__, kcontrol->id.name);
  2596. idx = -EINVAL;
  2597. }
  2598. return idx;
  2599. }
  2600. static int spdif_get_sample_rate_val(int sample_rate)
  2601. {
  2602. int sample_rate_val;
  2603. switch (sample_rate) {
  2604. case SAMPLING_RATE_32KHZ:
  2605. sample_rate_val = 0;
  2606. break;
  2607. case SAMPLING_RATE_44P1KHZ:
  2608. sample_rate_val = 1;
  2609. break;
  2610. case SAMPLING_RATE_48KHZ:
  2611. sample_rate_val = 2;
  2612. break;
  2613. case SAMPLING_RATE_88P2KHZ:
  2614. sample_rate_val = 3;
  2615. break;
  2616. case SAMPLING_RATE_96KHZ:
  2617. sample_rate_val = 4;
  2618. break;
  2619. case SAMPLING_RATE_176P4KHZ:
  2620. sample_rate_val = 5;
  2621. break;
  2622. case SAMPLING_RATE_192KHZ:
  2623. sample_rate_val = 6;
  2624. break;
  2625. default:
  2626. sample_rate_val = 2;
  2627. break;
  2628. }
  2629. return sample_rate_val;
  2630. }
  2631. static int spdif_get_sample_rate(int value)
  2632. {
  2633. int sample_rate;
  2634. switch (value) {
  2635. case 0:
  2636. sample_rate = SAMPLING_RATE_32KHZ;
  2637. break;
  2638. case 1:
  2639. sample_rate = SAMPLING_RATE_44P1KHZ;
  2640. break;
  2641. case 2:
  2642. sample_rate = SAMPLING_RATE_48KHZ;
  2643. break;
  2644. case 3:
  2645. sample_rate = SAMPLING_RATE_88P2KHZ;
  2646. break;
  2647. case 4:
  2648. sample_rate = SAMPLING_RATE_96KHZ;
  2649. break;
  2650. case 5:
  2651. sample_rate = SAMPLING_RATE_176P4KHZ;
  2652. break;
  2653. case 6:
  2654. sample_rate = SAMPLING_RATE_192KHZ;
  2655. break;
  2656. default:
  2657. sample_rate = SAMPLING_RATE_48KHZ;
  2658. break;
  2659. }
  2660. return sample_rate;
  2661. }
  2662. static int spdif_get_format(int value)
  2663. {
  2664. int format;
  2665. switch (value) {
  2666. case 0:
  2667. format = SNDRV_PCM_FORMAT_S16_LE;
  2668. break;
  2669. case 1:
  2670. format = SNDRV_PCM_FORMAT_S24_LE;
  2671. break;
  2672. default:
  2673. format = SNDRV_PCM_FORMAT_S16_LE;
  2674. break;
  2675. }
  2676. return format;
  2677. }
  2678. static int spdif_get_format_value(int format)
  2679. {
  2680. int value;
  2681. switch (format) {
  2682. case SNDRV_PCM_FORMAT_S16_LE:
  2683. value = 0;
  2684. break;
  2685. case SNDRV_PCM_FORMAT_S24_LE:
  2686. value = 1;
  2687. break;
  2688. default:
  2689. value = 0;
  2690. break;
  2691. }
  2692. return value;
  2693. }
  2694. static int msm_spdif_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2695. struct snd_ctl_elem_value *ucontrol)
  2696. {
  2697. int idx = spdif_get_port_idx(kcontrol);
  2698. if (idx < 0)
  2699. return idx;
  2700. spdif_rx_cfg[idx].sample_rate =
  2701. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2702. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2703. idx, spdif_rx_cfg[idx].sample_rate,
  2704. ucontrol->value.enumerated.item[0]);
  2705. return 0;
  2706. }
  2707. static int msm_spdif_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2708. struct snd_ctl_elem_value *ucontrol)
  2709. {
  2710. int idx = spdif_get_port_idx(kcontrol);
  2711. if (idx < 0)
  2712. return idx;
  2713. ucontrol->value.enumerated.item[0] =
  2714. spdif_get_sample_rate_val(spdif_rx_cfg[idx].sample_rate);
  2715. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2716. idx, spdif_rx_cfg[idx].sample_rate,
  2717. ucontrol->value.enumerated.item[0]);
  2718. return 0;
  2719. }
  2720. static int msm_spdif_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2721. struct snd_ctl_elem_value *ucontrol)
  2722. {
  2723. int idx = spdif_get_port_idx(kcontrol);
  2724. if (idx < 0)
  2725. return idx;
  2726. spdif_tx_cfg[idx].sample_rate =
  2727. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2728. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2729. idx, spdif_tx_cfg[idx].sample_rate,
  2730. ucontrol->value.enumerated.item[0]);
  2731. return 0;
  2732. }
  2733. static int msm_spdif_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2734. struct snd_ctl_elem_value *ucontrol)
  2735. {
  2736. int idx = spdif_get_port_idx(kcontrol);
  2737. if (idx < 0)
  2738. return idx;
  2739. ucontrol->value.enumerated.item[0] =
  2740. spdif_get_sample_rate_val(spdif_tx_cfg[idx].sample_rate);
  2741. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2742. idx, spdif_tx_cfg[idx].sample_rate,
  2743. ucontrol->value.enumerated.item[0]);
  2744. return 0;
  2745. }
  2746. static int msm_spdif_rx_ch_get(struct snd_kcontrol *kcontrol,
  2747. struct snd_ctl_elem_value *ucontrol)
  2748. {
  2749. int idx = spdif_get_port_idx(kcontrol);
  2750. if (idx < 0)
  2751. return idx;
  2752. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2753. idx, spdif_rx_cfg[idx].channels);
  2754. ucontrol->value.enumerated.item[0] = spdif_rx_cfg[idx].channels - 1;
  2755. return 0;
  2756. }
  2757. static int msm_spdif_rx_ch_put(struct snd_kcontrol *kcontrol,
  2758. struct snd_ctl_elem_value *ucontrol)
  2759. {
  2760. int idx = spdif_get_port_idx(kcontrol);
  2761. if (idx < 0)
  2762. return idx;
  2763. spdif_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2764. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2765. idx, spdif_rx_cfg[idx].channels);
  2766. return 1;
  2767. }
  2768. static int msm_spdif_tx_ch_get(struct snd_kcontrol *kcontrol,
  2769. struct snd_ctl_elem_value *ucontrol)
  2770. {
  2771. int idx = spdif_get_port_idx(kcontrol);
  2772. if (idx < 0)
  2773. return idx;
  2774. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2775. idx, spdif_tx_cfg[idx].channels);
  2776. ucontrol->value.enumerated.item[0] = spdif_tx_cfg[idx].channels - 1;
  2777. return 0;
  2778. }
  2779. static int msm_spdif_tx_ch_put(struct snd_kcontrol *kcontrol,
  2780. struct snd_ctl_elem_value *ucontrol)
  2781. {
  2782. int idx = spdif_get_port_idx(kcontrol);
  2783. if (idx < 0)
  2784. return idx;
  2785. spdif_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2786. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2787. idx, spdif_tx_cfg[idx].channels);
  2788. return 1;
  2789. }
  2790. static int msm_spdif_rx_format_get(struct snd_kcontrol *kcontrol,
  2791. struct snd_ctl_elem_value *ucontrol)
  2792. {
  2793. int idx = spdif_get_port_idx(kcontrol);
  2794. if (idx < 0)
  2795. return idx;
  2796. ucontrol->value.enumerated.item[0] =
  2797. spdif_get_format_value(spdif_rx_cfg[idx].bit_format);
  2798. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2799. idx, spdif_rx_cfg[idx].bit_format,
  2800. ucontrol->value.enumerated.item[0]);
  2801. return 0;
  2802. }
  2803. static int msm_spdif_rx_format_put(struct snd_kcontrol *kcontrol,
  2804. struct snd_ctl_elem_value *ucontrol)
  2805. {
  2806. int idx = spdif_get_port_idx(kcontrol);
  2807. if (idx < 0)
  2808. return idx;
  2809. spdif_rx_cfg[idx].bit_format =
  2810. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2811. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2812. idx, spdif_rx_cfg[idx].bit_format,
  2813. ucontrol->value.enumerated.item[0]);
  2814. return 0;
  2815. }
  2816. static int msm_spdif_tx_format_get(struct snd_kcontrol *kcontrol,
  2817. struct snd_ctl_elem_value *ucontrol)
  2818. {
  2819. int idx = spdif_get_port_idx(kcontrol);
  2820. if (idx < 0)
  2821. return idx;
  2822. ucontrol->value.enumerated.item[0] =
  2823. spdif_get_format_value(spdif_tx_cfg[idx].bit_format);
  2824. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2825. idx, spdif_tx_cfg[idx].bit_format,
  2826. ucontrol->value.enumerated.item[0]);
  2827. return 0;
  2828. }
  2829. static int msm_spdif_tx_format_put(struct snd_kcontrol *kcontrol,
  2830. struct snd_ctl_elem_value *ucontrol)
  2831. {
  2832. int idx = spdif_get_port_idx(kcontrol);
  2833. if (idx < 0)
  2834. return idx;
  2835. spdif_tx_cfg[idx].bit_format =
  2836. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2837. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2838. idx, spdif_tx_cfg[idx].bit_format,
  2839. ucontrol->value.enumerated.item[0]);
  2840. return 0;
  2841. }
  2842. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  2843. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  2844. slim_rx_ch_get, slim_rx_ch_put),
  2845. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  2846. slim_rx_ch_get, slim_rx_ch_put),
  2847. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  2848. slim_tx_ch_get, slim_tx_ch_put),
  2849. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  2850. slim_tx_ch_get, slim_tx_ch_put),
  2851. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  2852. slim_rx_ch_get, slim_rx_ch_put),
  2853. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  2854. slim_rx_ch_get, slim_rx_ch_put),
  2855. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  2856. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2857. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  2858. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2859. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  2860. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2861. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  2862. slim_tx_bit_format_get, slim_tx_bit_format_put),
  2863. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  2864. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2865. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  2866. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2867. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  2868. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  2869. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  2870. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2871. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  2872. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2873. };
  2874. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  2875. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2876. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2877. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2878. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2879. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2880. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2881. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2882. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2883. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2884. va_cdc_dma_tx_0_sample_rate,
  2885. cdc_dma_tx_sample_rate_get,
  2886. cdc_dma_tx_sample_rate_put),
  2887. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2888. va_cdc_dma_tx_1_sample_rate,
  2889. cdc_dma_tx_sample_rate_get,
  2890. cdc_dma_tx_sample_rate_put),
  2891. };
  2892. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  2893. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  2894. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  2895. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  2896. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2897. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  2898. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2899. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  2900. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2901. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  2902. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2903. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  2904. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2905. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  2906. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2907. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  2908. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2909. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  2910. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2911. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  2912. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2913. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  2914. wsa_cdc_dma_rx_0_sample_rate,
  2915. cdc_dma_rx_sample_rate_get,
  2916. cdc_dma_rx_sample_rate_put),
  2917. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  2918. wsa_cdc_dma_rx_1_sample_rate,
  2919. cdc_dma_rx_sample_rate_get,
  2920. cdc_dma_rx_sample_rate_put),
  2921. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  2922. wsa_cdc_dma_tx_0_sample_rate,
  2923. cdc_dma_tx_sample_rate_get,
  2924. cdc_dma_tx_sample_rate_put),
  2925. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  2926. wsa_cdc_dma_tx_1_sample_rate,
  2927. cdc_dma_tx_sample_rate_get,
  2928. cdc_dma_tx_sample_rate_put),
  2929. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  2930. wsa_cdc_dma_tx_2_sample_rate,
  2931. cdc_dma_tx_sample_rate_get,
  2932. cdc_dma_tx_sample_rate_put),
  2933. };
  2934. static const struct snd_kcontrol_new msm_snd_controls[] = {
  2935. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  2936. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  2937. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  2938. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  2939. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  2940. proxy_rx_ch_get, proxy_rx_ch_put),
  2941. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  2942. usb_audio_rx_format_get, usb_audio_rx_format_put),
  2943. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  2944. usb_audio_tx_format_get, usb_audio_tx_format_put),
  2945. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  2946. msm_bt_sample_rate_get,
  2947. msm_bt_sample_rate_put),
  2948. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  2949. usb_audio_rx_sample_rate_get,
  2950. usb_audio_rx_sample_rate_put),
  2951. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  2952. usb_audio_tx_sample_rate_get,
  2953. usb_audio_tx_sample_rate_put),
  2954. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2955. tdm_rx_sample_rate_get,
  2956. tdm_rx_sample_rate_put),
  2957. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2958. tdm_tx_sample_rate_get,
  2959. tdm_tx_sample_rate_put),
  2960. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  2961. tdm_rx_format_get,
  2962. tdm_rx_format_put),
  2963. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  2964. tdm_tx_format_get,
  2965. tdm_tx_format_put),
  2966. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  2967. tdm_rx_ch_get,
  2968. tdm_rx_ch_put),
  2969. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  2970. tdm_tx_ch_get,
  2971. tdm_tx_ch_put),
  2972. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2973. tdm_rx_sample_rate_get,
  2974. tdm_rx_sample_rate_put),
  2975. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2976. tdm_tx_sample_rate_get,
  2977. tdm_tx_sample_rate_put),
  2978. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  2979. tdm_rx_format_get,
  2980. tdm_rx_format_put),
  2981. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  2982. tdm_tx_format_get,
  2983. tdm_tx_format_put),
  2984. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  2985. tdm_rx_ch_get,
  2986. tdm_rx_ch_put),
  2987. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  2988. tdm_tx_ch_get,
  2989. tdm_tx_ch_put),
  2990. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2991. tdm_rx_sample_rate_get,
  2992. tdm_rx_sample_rate_put),
  2993. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2994. tdm_tx_sample_rate_get,
  2995. tdm_tx_sample_rate_put),
  2996. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  2997. tdm_rx_format_get,
  2998. tdm_rx_format_put),
  2999. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3000. tdm_tx_format_get,
  3001. tdm_tx_format_put),
  3002. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3003. tdm_rx_ch_get,
  3004. tdm_rx_ch_put),
  3005. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3006. tdm_tx_ch_get,
  3007. tdm_tx_ch_put),
  3008. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3009. tdm_rx_sample_rate_get,
  3010. tdm_rx_sample_rate_put),
  3011. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3012. tdm_tx_sample_rate_get,
  3013. tdm_tx_sample_rate_put),
  3014. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3015. tdm_rx_format_get,
  3016. tdm_rx_format_put),
  3017. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3018. tdm_tx_format_get,
  3019. tdm_tx_format_put),
  3020. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3021. tdm_rx_ch_get,
  3022. tdm_rx_ch_put),
  3023. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3024. tdm_tx_ch_get,
  3025. tdm_tx_ch_put),
  3026. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3027. tdm_rx_sample_rate_get,
  3028. tdm_rx_sample_rate_put),
  3029. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3030. tdm_tx_sample_rate_get,
  3031. tdm_tx_sample_rate_put),
  3032. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3033. tdm_rx_format_get,
  3034. tdm_rx_format_put),
  3035. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3036. tdm_tx_format_get,
  3037. tdm_tx_format_put),
  3038. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3039. tdm_rx_ch_get,
  3040. tdm_rx_ch_put),
  3041. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3042. tdm_tx_ch_get,
  3043. tdm_tx_ch_put),
  3044. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3045. aux_pcm_rx_sample_rate_get,
  3046. aux_pcm_rx_sample_rate_put),
  3047. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3048. aux_pcm_rx_sample_rate_get,
  3049. aux_pcm_rx_sample_rate_put),
  3050. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3051. aux_pcm_rx_sample_rate_get,
  3052. aux_pcm_rx_sample_rate_put),
  3053. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3054. aux_pcm_rx_sample_rate_get,
  3055. aux_pcm_rx_sample_rate_put),
  3056. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3057. aux_pcm_rx_sample_rate_get,
  3058. aux_pcm_rx_sample_rate_put),
  3059. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3060. aux_pcm_tx_sample_rate_get,
  3061. aux_pcm_tx_sample_rate_put),
  3062. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3063. aux_pcm_tx_sample_rate_get,
  3064. aux_pcm_tx_sample_rate_put),
  3065. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3066. aux_pcm_tx_sample_rate_get,
  3067. aux_pcm_tx_sample_rate_put),
  3068. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3069. aux_pcm_tx_sample_rate_get,
  3070. aux_pcm_tx_sample_rate_put),
  3071. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3072. aux_pcm_tx_sample_rate_get,
  3073. aux_pcm_tx_sample_rate_put),
  3074. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3075. mi2s_rx_sample_rate_get,
  3076. mi2s_rx_sample_rate_put),
  3077. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3078. mi2s_rx_sample_rate_get,
  3079. mi2s_rx_sample_rate_put),
  3080. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3081. mi2s_rx_sample_rate_get,
  3082. mi2s_rx_sample_rate_put),
  3083. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3084. mi2s_rx_sample_rate_get,
  3085. mi2s_rx_sample_rate_put),
  3086. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3087. mi2s_rx_sample_rate_get,
  3088. mi2s_rx_sample_rate_put),
  3089. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3090. mi2s_tx_sample_rate_get,
  3091. mi2s_tx_sample_rate_put),
  3092. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3093. mi2s_tx_sample_rate_get,
  3094. mi2s_tx_sample_rate_put),
  3095. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3096. mi2s_tx_sample_rate_get,
  3097. mi2s_tx_sample_rate_put),
  3098. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3099. mi2s_tx_sample_rate_get,
  3100. mi2s_tx_sample_rate_put),
  3101. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3102. mi2s_tx_sample_rate_get,
  3103. mi2s_tx_sample_rate_put),
  3104. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3105. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3106. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3107. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3108. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3109. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3110. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3111. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3112. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3113. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3114. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3115. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3116. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3117. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3118. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3119. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3120. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3121. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3122. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3123. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3124. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3125. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3126. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3127. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3128. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3129. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3130. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3131. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3132. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3133. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3134. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3135. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3136. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3137. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3138. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3139. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3140. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3141. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3142. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3143. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3144. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3145. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3146. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3147. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3148. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3149. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3150. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3151. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3152. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3153. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3154. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3155. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3156. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3157. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3158. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3159. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3160. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3161. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3162. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3163. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3164. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  3165. msm_snd_vad_cfg_put),
  3166. SOC_ENUM_EXT("PRIM_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3167. msm_spdif_rx_sample_rate_get,
  3168. msm_spdif_rx_sample_rate_put),
  3169. SOC_ENUM_EXT("PRIM_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3170. msm_spdif_tx_sample_rate_get,
  3171. msm_spdif_tx_sample_rate_put),
  3172. SOC_ENUM_EXT("SEC_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3173. msm_spdif_rx_sample_rate_get,
  3174. msm_spdif_rx_sample_rate_put),
  3175. SOC_ENUM_EXT("SEC_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3176. msm_spdif_tx_sample_rate_get,
  3177. msm_spdif_tx_sample_rate_put),
  3178. SOC_ENUM_EXT("PRIM_SPDIF_RX Channels", spdif_rx_chs,
  3179. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3180. SOC_ENUM_EXT("PRIM_SPDIF_TX Channels", spdif_tx_chs,
  3181. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3182. SOC_ENUM_EXT("SEC_SPDIF_RX Channels", spdif_rx_chs,
  3183. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3184. SOC_ENUM_EXT("SEC_SPDIF_TX Channels", spdif_tx_chs,
  3185. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3186. SOC_ENUM_EXT("PRIM_SPDIF_RX Format", spdif_rx_format,
  3187. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3188. SOC_ENUM_EXT("PRIM_SPDIF_TX Format", spdif_tx_format,
  3189. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3190. SOC_ENUM_EXT("SEC_SPDIF_RX Format", spdif_rx_format,
  3191. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3192. SOC_ENUM_EXT("SEC_SPDIF_TX Format", spdif_tx_format,
  3193. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3194. };
  3195. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  3196. int enable, bool dapm)
  3197. {
  3198. int ret = 0;
  3199. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  3200. ret = tasha_cdc_mclk_enable(codec, enable, dapm);
  3201. } else {
  3202. dev_err(codec->dev, "%s: unknown codec to enable ext clk\n",
  3203. __func__);
  3204. ret = -EINVAL;
  3205. }
  3206. return ret;
  3207. }
  3208. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_codec *codec,
  3209. int enable, bool dapm)
  3210. {
  3211. int ret = 0;
  3212. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  3213. ret = tasha_cdc_mclk_tx_enable(codec, enable, dapm);
  3214. } else {
  3215. dev_err(codec->dev, "%s: unknown codec to enable TX ext clk\n",
  3216. __func__);
  3217. ret = -EINVAL;
  3218. }
  3219. return ret;
  3220. }
  3221. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  3222. struct snd_kcontrol *kcontrol, int event)
  3223. {
  3224. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3225. pr_debug("%s: event = %d\n", __func__, event);
  3226. switch (event) {
  3227. case SND_SOC_DAPM_PRE_PMU:
  3228. return msm_snd_enable_codec_ext_tx_clk(codec, 1, true);
  3229. case SND_SOC_DAPM_POST_PMD:
  3230. return msm_snd_enable_codec_ext_tx_clk(codec, 0, true);
  3231. }
  3232. return 0;
  3233. }
  3234. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  3235. struct snd_kcontrol *kcontrol, int event)
  3236. {
  3237. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3238. pr_debug("%s: event = %d\n", __func__, event);
  3239. switch (event) {
  3240. case SND_SOC_DAPM_PRE_PMU:
  3241. return msm_snd_enable_codec_ext_clk(codec, 1, true);
  3242. case SND_SOC_DAPM_POST_PMD:
  3243. return msm_snd_enable_codec_ext_clk(codec, 0, true);
  3244. }
  3245. return 0;
  3246. }
  3247. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  3248. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  3249. msm_mclk_event,
  3250. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3251. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  3252. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3253. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  3254. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  3255. };
  3256. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  3257. struct snd_kcontrol *kcontrol, int event)
  3258. {
  3259. struct msm_asoc_mach_data *pdata = NULL;
  3260. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3261. int ret = 0;
  3262. uint32_t dmic_idx;
  3263. int *dmic_gpio_cnt;
  3264. struct device_node *dmic_gpio;
  3265. char *wname;
  3266. wname = strpbrk(w->name, "01234567");
  3267. if (!wname) {
  3268. dev_err(codec->dev, "%s: widget not found\n", __func__);
  3269. return -EINVAL;
  3270. }
  3271. ret = kstrtouint(wname, 10, &dmic_idx);
  3272. if (ret < 0) {
  3273. dev_err(codec->dev, "%s: Invalid DMIC line on the codec\n",
  3274. __func__);
  3275. return -EINVAL;
  3276. }
  3277. pdata = snd_soc_card_get_drvdata(codec->component.card);
  3278. switch (dmic_idx) {
  3279. case 0:
  3280. case 1:
  3281. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  3282. dmic_gpio = pdata->dmic_01_gpio_p;
  3283. break;
  3284. case 2:
  3285. case 3:
  3286. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  3287. dmic_gpio = pdata->dmic_23_gpio_p;
  3288. break;
  3289. case 4:
  3290. case 5:
  3291. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  3292. dmic_gpio = pdata->dmic_45_gpio_p;
  3293. break;
  3294. case 6:
  3295. case 7:
  3296. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  3297. dmic_gpio = pdata->dmic_67_gpio_p;
  3298. break;
  3299. default:
  3300. dev_err(codec->dev, "%s: Invalid DMIC Selection\n",
  3301. __func__);
  3302. return -EINVAL;
  3303. }
  3304. dev_dbg(codec->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  3305. __func__, event, dmic_idx, *dmic_gpio_cnt);
  3306. switch (event) {
  3307. case SND_SOC_DAPM_PRE_PMU:
  3308. (*dmic_gpio_cnt)++;
  3309. if (*dmic_gpio_cnt == 1) {
  3310. ret = msm_cdc_pinctrl_select_active_state(
  3311. dmic_gpio);
  3312. if (ret < 0) {
  3313. dev_err(codec->dev, "%s: gpio set cannot be activated %sd\n",
  3314. __func__, "dmic_gpio");
  3315. return ret;
  3316. }
  3317. }
  3318. break;
  3319. case SND_SOC_DAPM_POST_PMD:
  3320. (*dmic_gpio_cnt)--;
  3321. if (*dmic_gpio_cnt == 0) {
  3322. ret = msm_cdc_pinctrl_select_sleep_state(
  3323. dmic_gpio);
  3324. if (ret < 0) {
  3325. dev_err(codec->dev, "%s: gpio set cannot be de-activated %sd\n",
  3326. __func__, "dmic_gpio");
  3327. return ret;
  3328. }
  3329. }
  3330. break;
  3331. default:
  3332. dev_err(codec->dev, "%s: invalid DAPM event %d\n",
  3333. __func__, event);
  3334. return -EINVAL;
  3335. }
  3336. return 0;
  3337. }
  3338. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3339. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3340. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3341. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3342. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3343. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3344. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3345. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3346. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3347. };
  3348. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3349. };
  3350. static inline int param_is_mask(int p)
  3351. {
  3352. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3353. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3354. }
  3355. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3356. int n)
  3357. {
  3358. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3359. }
  3360. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3361. unsigned int bit)
  3362. {
  3363. if (bit >= SNDRV_MASK_MAX)
  3364. return;
  3365. if (param_is_mask(n)) {
  3366. struct snd_mask *m = param_to_mask(p, n);
  3367. m->bits[0] = 0;
  3368. m->bits[1] = 0;
  3369. m->bits[bit >> 5] |= (1 << (bit & 31));
  3370. }
  3371. }
  3372. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3373. {
  3374. int ch_id = 0;
  3375. switch (be_id) {
  3376. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3377. ch_id = SLIM_RX_0;
  3378. break;
  3379. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3380. ch_id = SLIM_RX_1;
  3381. break;
  3382. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3383. ch_id = SLIM_RX_2;
  3384. break;
  3385. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3386. ch_id = SLIM_RX_3;
  3387. break;
  3388. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3389. ch_id = SLIM_RX_4;
  3390. break;
  3391. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3392. ch_id = SLIM_RX_6;
  3393. break;
  3394. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3395. ch_id = SLIM_TX_0;
  3396. break;
  3397. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3398. ch_id = SLIM_TX_3;
  3399. break;
  3400. default:
  3401. ch_id = SLIM_RX_0;
  3402. break;
  3403. }
  3404. return ch_id;
  3405. }
  3406. static int msm_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  3407. {
  3408. *port_id = 0xFFFF;
  3409. switch (be_id) {
  3410. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3411. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  3412. break;
  3413. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3414. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  3415. break;
  3416. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3417. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  3418. break;
  3419. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3420. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  3421. break;
  3422. default:
  3423. return -EINVAL;
  3424. }
  3425. return 0;
  3426. }
  3427. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3428. {
  3429. int idx = 0;
  3430. switch (be_id) {
  3431. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3432. idx = WSA_CDC_DMA_RX_0;
  3433. break;
  3434. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3435. idx = WSA_CDC_DMA_TX_0;
  3436. break;
  3437. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3438. idx = WSA_CDC_DMA_RX_1;
  3439. break;
  3440. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3441. idx = WSA_CDC_DMA_TX_1;
  3442. break;
  3443. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3444. idx = WSA_CDC_DMA_TX_2;
  3445. break;
  3446. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3447. idx = VA_CDC_DMA_TX_0;
  3448. break;
  3449. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3450. idx = VA_CDC_DMA_TX_1;
  3451. break;
  3452. default:
  3453. idx = VA_CDC_DMA_TX_0;
  3454. break;
  3455. }
  3456. return idx;
  3457. }
  3458. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3459. struct snd_pcm_hw_params *params)
  3460. {
  3461. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3462. struct snd_interval *rate = hw_param_interval(params,
  3463. SNDRV_PCM_HW_PARAM_RATE);
  3464. struct snd_interval *channels = hw_param_interval(params,
  3465. SNDRV_PCM_HW_PARAM_CHANNELS);
  3466. int rc = 0;
  3467. int idx;
  3468. void *config = NULL;
  3469. struct snd_soc_codec *codec = NULL;
  3470. pr_debug("%s: format = %d, rate = %d\n",
  3471. __func__, params_format(params), params_rate(params));
  3472. switch (dai_link->id) {
  3473. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3474. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3475. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3476. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3477. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3478. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3479. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3480. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3481. slim_rx_cfg[idx].bit_format);
  3482. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3483. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3484. break;
  3485. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3486. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3487. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3488. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3489. slim_tx_cfg[idx].bit_format);
  3490. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3491. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3492. break;
  3493. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3494. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3495. slim_tx_cfg[1].bit_format);
  3496. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3497. channels->min = channels->max = slim_tx_cfg[1].channels;
  3498. break;
  3499. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3500. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3501. SNDRV_PCM_FORMAT_S32_LE);
  3502. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3503. channels->min = channels->max = msm_vi_feed_tx_ch;
  3504. break;
  3505. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3506. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3507. slim_rx_cfg[5].bit_format);
  3508. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3509. channels->min = channels->max = slim_rx_cfg[5].channels;
  3510. break;
  3511. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3512. codec = rtd->codec;
  3513. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3514. channels->min = channels->max = 1;
  3515. config = msm_codec_fn.get_afe_config_fn(codec,
  3516. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3517. if (config) {
  3518. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3519. config, SLIMBUS_5_TX);
  3520. if (rc)
  3521. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3522. __func__, rc);
  3523. }
  3524. break;
  3525. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3526. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3527. slim_rx_cfg[SLIM_RX_7].bit_format);
  3528. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3529. channels->min = channels->max =
  3530. slim_rx_cfg[SLIM_RX_7].channels;
  3531. break;
  3532. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3533. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3534. channels->min = channels->max =
  3535. slim_tx_cfg[SLIM_TX_7].channels;
  3536. break;
  3537. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3538. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3539. channels->min = channels->max =
  3540. slim_tx_cfg[SLIM_TX_8].channels;
  3541. break;
  3542. case MSM_BACKEND_DAI_USB_RX:
  3543. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3544. usb_rx_cfg.bit_format);
  3545. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3546. channels->min = channels->max = usb_rx_cfg.channels;
  3547. break;
  3548. case MSM_BACKEND_DAI_USB_TX:
  3549. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3550. usb_tx_cfg.bit_format);
  3551. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3552. channels->min = channels->max = usb_tx_cfg.channels;
  3553. break;
  3554. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3555. channels->min = channels->max = proxy_rx_cfg.channels;
  3556. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3557. break;
  3558. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3559. channels->min = channels->max =
  3560. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3561. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3562. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3563. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3564. break;
  3565. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3566. channels->min = channels->max =
  3567. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3568. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3569. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3570. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3571. break;
  3572. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3573. channels->min = channels->max =
  3574. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3575. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3576. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3577. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3578. break;
  3579. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3580. channels->min = channels->max =
  3581. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3582. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3583. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3584. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3585. break;
  3586. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3587. channels->min = channels->max =
  3588. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3589. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3590. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3591. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3592. break;
  3593. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3594. channels->min = channels->max =
  3595. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3596. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3597. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3598. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3599. break;
  3600. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3601. channels->min = channels->max =
  3602. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3603. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3604. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3605. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3606. break;
  3607. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3608. channels->min = channels->max =
  3609. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3610. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3611. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3612. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3613. break;
  3614. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3615. channels->min = channels->max =
  3616. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3617. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3618. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3619. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3620. break;
  3621. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3622. channels->min = channels->max =
  3623. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3624. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3625. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3626. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3627. break;
  3628. case MSM_BACKEND_DAI_AUXPCM_RX:
  3629. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3630. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3631. rate->min = rate->max =
  3632. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3633. channels->min = channels->max =
  3634. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3635. break;
  3636. case MSM_BACKEND_DAI_AUXPCM_TX:
  3637. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3638. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3639. rate->min = rate->max =
  3640. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3641. channels->min = channels->max =
  3642. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3643. break;
  3644. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3645. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3646. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3647. rate->min = rate->max =
  3648. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3649. channels->min = channels->max =
  3650. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3651. break;
  3652. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3653. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3654. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3655. rate->min = rate->max =
  3656. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3657. channels->min = channels->max =
  3658. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3659. break;
  3660. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3661. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3662. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3663. rate->min = rate->max =
  3664. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3665. channels->min = channels->max =
  3666. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3667. break;
  3668. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3669. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3670. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3671. rate->min = rate->max =
  3672. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3673. channels->min = channels->max =
  3674. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3675. break;
  3676. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3677. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3678. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3679. rate->min = rate->max =
  3680. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3681. channels->min = channels->max =
  3682. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3683. break;
  3684. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3685. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3686. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3687. rate->min = rate->max =
  3688. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3689. channels->min = channels->max =
  3690. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3691. break;
  3692. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3693. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3694. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3695. rate->min = rate->max =
  3696. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3697. channels->min = channels->max =
  3698. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3699. break;
  3700. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3701. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3702. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3703. rate->min = rate->max =
  3704. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3705. channels->min = channels->max =
  3706. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3707. break;
  3708. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3709. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3710. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3711. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3712. channels->min = channels->max =
  3713. mi2s_rx_cfg[PRIM_MI2S].channels;
  3714. break;
  3715. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3716. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3717. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3718. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3719. channels->min = channels->max =
  3720. mi2s_tx_cfg[PRIM_MI2S].channels;
  3721. break;
  3722. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3723. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3724. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3725. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3726. channels->min = channels->max =
  3727. mi2s_rx_cfg[SEC_MI2S].channels;
  3728. break;
  3729. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3730. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3731. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3732. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3733. channels->min = channels->max =
  3734. mi2s_tx_cfg[SEC_MI2S].channels;
  3735. break;
  3736. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3737. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3738. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3739. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3740. channels->min = channels->max =
  3741. mi2s_rx_cfg[TERT_MI2S].channels;
  3742. break;
  3743. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3744. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3745. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3746. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3747. channels->min = channels->max =
  3748. mi2s_tx_cfg[TERT_MI2S].channels;
  3749. break;
  3750. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3751. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3752. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3753. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3754. channels->min = channels->max =
  3755. mi2s_rx_cfg[QUAT_MI2S].channels;
  3756. break;
  3757. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3758. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3759. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3760. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3761. channels->min = channels->max =
  3762. mi2s_tx_cfg[QUAT_MI2S].channels;
  3763. break;
  3764. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3765. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3766. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3767. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3768. channels->min = channels->max =
  3769. mi2s_rx_cfg[QUIN_MI2S].channels;
  3770. break;
  3771. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3772. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3773. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3774. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3775. channels->min = channels->max =
  3776. mi2s_tx_cfg[QUIN_MI2S].channels;
  3777. break;
  3778. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3779. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3780. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3781. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3782. cdc_dma_rx_cfg[idx].bit_format);
  3783. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3784. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3785. break;
  3786. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3787. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3788. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3789. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3790. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3791. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3792. cdc_dma_tx_cfg[idx].bit_format);
  3793. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3794. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3795. break;
  3796. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3797. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3798. SNDRV_PCM_FORMAT_S32_LE);
  3799. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3800. channels->min = channels->max = msm_vi_feed_tx_ch;
  3801. break;
  3802. case MSM_BACKEND_DAI_PRI_SPDIF_RX:
  3803. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3804. spdif_rx_cfg[PRIM_SPDIF_RX].bit_format);
  3805. rate->min = rate->max =
  3806. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate;
  3807. channels->min = channels->max =
  3808. spdif_rx_cfg[PRIM_SPDIF_RX].channels;
  3809. break;
  3810. case MSM_BACKEND_DAI_PRI_SPDIF_TX:
  3811. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3812. spdif_tx_cfg[PRIM_SPDIF_TX].bit_format);
  3813. rate->min = rate->max =
  3814. spdif_tx_cfg[PRIM_SPDIF_TX].sample_rate;
  3815. channels->min = channels->max =
  3816. spdif_tx_cfg[PRIM_SPDIF_TX].channels;
  3817. break;
  3818. case MSM_BACKEND_DAI_SEC_SPDIF_RX:
  3819. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3820. spdif_rx_cfg[SEC_SPDIF_RX].bit_format);
  3821. rate->min = rate->max =
  3822. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate;
  3823. channels->min = channels->max =
  3824. spdif_rx_cfg[SEC_SPDIF_RX].channels;
  3825. break;
  3826. case MSM_BACKEND_DAI_SEC_SPDIF_TX:
  3827. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3828. spdif_tx_cfg[SEC_SPDIF_TX].bit_format);
  3829. rate->min = rate->max =
  3830. spdif_tx_cfg[SEC_SPDIF_TX].sample_rate;
  3831. channels->min = channels->max =
  3832. spdif_tx_cfg[SEC_SPDIF_TX].channels;
  3833. break;
  3834. default:
  3835. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3836. break;
  3837. }
  3838. return rc;
  3839. }
  3840. static int msm_afe_set_config(struct snd_soc_codec *codec)
  3841. {
  3842. int ret = 0;
  3843. void *config_data = NULL;
  3844. if (!msm_codec_fn.get_afe_config_fn) {
  3845. dev_err(codec->dev, "%s: codec get afe config not init'ed\n",
  3846. __func__);
  3847. return -EINVAL;
  3848. }
  3849. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3850. AFE_CDC_REGISTERS_CONFIG);
  3851. if (config_data) {
  3852. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  3853. if (ret) {
  3854. dev_err(codec->dev,
  3855. "%s: Failed to set codec registers config %d\n",
  3856. __func__, ret);
  3857. return ret;
  3858. }
  3859. }
  3860. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3861. AFE_CDC_REGISTER_PAGE_CONFIG);
  3862. if (config_data) {
  3863. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  3864. 0);
  3865. if (ret)
  3866. dev_err(codec->dev,
  3867. "%s: Failed to set cdc register page config\n",
  3868. __func__);
  3869. }
  3870. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3871. AFE_SLIMBUS_SLAVE_CONFIG);
  3872. if (config_data) {
  3873. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  3874. if (ret) {
  3875. dev_err(codec->dev,
  3876. "%s: Failed to set slimbus slave config %d\n",
  3877. __func__, ret);
  3878. return ret;
  3879. }
  3880. }
  3881. return 0;
  3882. }
  3883. static void msm_afe_clear_config(void)
  3884. {
  3885. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  3886. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  3887. }
  3888. static int msm_adsp_power_up_config(struct snd_soc_codec *codec,
  3889. struct snd_card *card)
  3890. {
  3891. int ret = 0;
  3892. unsigned long timeout;
  3893. int adsp_ready = 0;
  3894. bool snd_card_online = 0;
  3895. timeout = jiffies +
  3896. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  3897. do {
  3898. if (!snd_card_online) {
  3899. snd_card_online = snd_card_is_online_state(card);
  3900. pr_debug("%s: Sound card is %s\n", __func__,
  3901. snd_card_online ? "Online" : "Offline");
  3902. }
  3903. if (!adsp_ready) {
  3904. adsp_ready = q6core_is_adsp_ready();
  3905. pr_debug("%s: ADSP Audio is %s\n", __func__,
  3906. adsp_ready ? "ready" : "not ready");
  3907. }
  3908. if (snd_card_online && adsp_ready)
  3909. break;
  3910. /*
  3911. * Sound card/ADSP will be coming up after subsystem restart and
  3912. * it might not be fully up when the control reaches
  3913. * here. So, wait for 50msec before checking ADSP state
  3914. */
  3915. msleep(50);
  3916. } while (time_after(timeout, jiffies));
  3917. if (!snd_card_online || !adsp_ready) {
  3918. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  3919. __func__,
  3920. snd_card_online ? "Online" : "Offline",
  3921. adsp_ready ? "ready" : "not ready");
  3922. ret = -ETIMEDOUT;
  3923. goto err;
  3924. }
  3925. ret = msm_afe_set_config(codec);
  3926. if (ret)
  3927. pr_err("%s: Failed to set AFE config. err %d\n",
  3928. __func__, ret);
  3929. return 0;
  3930. err:
  3931. return ret;
  3932. }
  3933. static int qcs405_notifier_service_cb(struct notifier_block *this,
  3934. unsigned long opcode, void *ptr)
  3935. {
  3936. int ret;
  3937. struct snd_soc_card *card = NULL;
  3938. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  3939. struct snd_soc_pcm_runtime *rtd;
  3940. struct snd_soc_codec *codec;
  3941. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  3942. switch (opcode) {
  3943. case AUDIO_NOTIFIER_SERVICE_DOWN:
  3944. /*
  3945. * Use flag to ignore initial boot notifications
  3946. * On initial boot msm_adsp_power_up_config is
  3947. * called on init. There is no need to clear
  3948. * and set the config again on initial boot.
  3949. */
  3950. if (is_initial_boot)
  3951. break;
  3952. msm_afe_clear_config();
  3953. break;
  3954. case AUDIO_NOTIFIER_SERVICE_UP:
  3955. if (is_initial_boot) {
  3956. is_initial_boot = false;
  3957. break;
  3958. }
  3959. if (!spdev)
  3960. return -EINVAL;
  3961. card = platform_get_drvdata(spdev);
  3962. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  3963. if (!rtd) {
  3964. dev_err(card->dev,
  3965. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  3966. __func__, be_dl_name);
  3967. ret = -EINVAL;
  3968. goto err;
  3969. }
  3970. codec = rtd->codec;
  3971. ret = msm_adsp_power_up_config(codec, card->snd_card);
  3972. if (ret < 0) {
  3973. dev_err(card->dev,
  3974. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  3975. __func__, ret);
  3976. goto err;
  3977. }
  3978. break;
  3979. default:
  3980. break;
  3981. }
  3982. err:
  3983. return NOTIFY_OK;
  3984. }
  3985. static struct notifier_block service_nb = {
  3986. .notifier_call = qcs405_notifier_service_cb,
  3987. .priority = -INT_MAX,
  3988. };
  3989. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  3990. {
  3991. int ret = 0;
  3992. void *config_data;
  3993. struct snd_soc_codec *codec = rtd->codec;
  3994. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3995. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3996. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3997. struct snd_card *card;
  3998. struct msm_asoc_mach_data *pdata =
  3999. snd_soc_card_get_drvdata(rtd->card);
  4000. /*
  4001. * Codec SLIMBUS configuration
  4002. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  4003. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  4004. * TX14, TX15, TX16
  4005. */
  4006. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  4007. 151, 152, 153, 154, 155, 156};
  4008. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  4009. 134, 135, 136, 137, 138, 139,
  4010. 140, 141, 142, 143};
  4011. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  4012. rtd->pmdown_time = 0;
  4013. ret = snd_soc_add_codec_controls(codec, msm_snd_sb_controls,
  4014. ARRAY_SIZE(msm_snd_sb_controls));
  4015. if (ret < 0) {
  4016. pr_err("%s: add_codec_controls failed, err %d\n",
  4017. __func__, ret);
  4018. return ret;
  4019. }
  4020. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  4021. ARRAY_SIZE(msm_dapm_widgets));
  4022. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  4023. ARRAY_SIZE(wcd_audio_paths));
  4024. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  4025. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  4026. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4027. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4028. snd_soc_dapm_sync(dapm);
  4029. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4030. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4031. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  4032. ret = msm_adsp_power_up_config(codec, rtd->card->snd_card);
  4033. if (ret) {
  4034. dev_err(codec->dev, "%s: Failed to set AFE config %d\n",
  4035. __func__, ret);
  4036. goto err;
  4037. }
  4038. config_data = msm_codec_fn.get_afe_config_fn(codec,
  4039. AFE_AANC_VERSION);
  4040. if (config_data) {
  4041. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  4042. if (ret) {
  4043. dev_err(codec->dev, "%s: Failed to set aanc version %d\n",
  4044. __func__, ret);
  4045. goto err;
  4046. }
  4047. }
  4048. card = rtd->card->snd_card;
  4049. if (!pdata->codec_root)
  4050. pdata->codec_root = snd_info_create_subdir(card->module,
  4051. "codecs", card->proc_root);
  4052. if (!pdata->codec_root) {
  4053. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4054. __func__);
  4055. ret = 0;
  4056. goto err;
  4057. }
  4058. tasha_codec_info_create_codec_entry(pdata->codec_root, codec);
  4059. codec_reg_done = true;
  4060. return 0;
  4061. err:
  4062. return ret;
  4063. }
  4064. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4065. {
  4066. int ret = 0;
  4067. struct snd_soc_codec *codec = rtd->codec;
  4068. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  4069. struct snd_card *card;
  4070. struct msm_asoc_mach_data *pdata =
  4071. snd_soc_card_get_drvdata(rtd->card);
  4072. ret = snd_soc_add_codec_controls(codec, msm_snd_va_controls,
  4073. ARRAY_SIZE(msm_snd_va_controls));
  4074. if (ret < 0) {
  4075. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  4076. __func__, ret);
  4077. return ret;
  4078. }
  4079. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  4080. ARRAY_SIZE(msm_va_dapm_widgets));
  4081. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4082. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4083. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4084. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4085. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4086. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4087. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  4088. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  4089. snd_soc_dapm_sync(dapm);
  4090. card = rtd->card->snd_card;
  4091. if (!pdata->codec_root)
  4092. pdata->codec_root = snd_info_create_subdir(card->module,
  4093. "codecs", card->proc_root);
  4094. if (!pdata->codec_root) {
  4095. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4096. __func__);
  4097. ret = 0;
  4098. goto done;
  4099. }
  4100. bolero_info_create_codec_entry(pdata->codec_root, codec);
  4101. done:
  4102. return ret;
  4103. }
  4104. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4105. {
  4106. int ret = 0;
  4107. struct snd_soc_codec *codec = rtd->codec;
  4108. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  4109. struct snd_soc_component *aux_comp;
  4110. struct snd_card *card;
  4111. struct msm_asoc_mach_data *pdata =
  4112. snd_soc_card_get_drvdata(rtd->card);
  4113. ret = snd_soc_add_codec_controls(codec, msm_snd_wsa_controls,
  4114. ARRAY_SIZE(msm_snd_wsa_controls));
  4115. if (ret < 0) {
  4116. dev_err(codec->dev, "%s: add_codec_controls for wsa failed, err %d\n",
  4117. __func__, ret);
  4118. return ret;
  4119. }
  4120. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  4121. ARRAY_SIZE(msm_wsa_dapm_widgets));
  4122. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4123. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4124. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4125. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4126. snd_soc_dapm_sync(dapm);
  4127. /*
  4128. * Send speaker configuration only for WSA8810.
  4129. * Default configuration is for WSA8815.
  4130. */
  4131. dev_dbg(codec->dev, "%s: Number of aux devices: %d\n",
  4132. __func__, rtd->card->num_aux_devs);
  4133. if (rtd->card->num_aux_devs &&
  4134. !list_empty(&rtd->card->component_dev_list)) {
  4135. aux_comp = list_first_entry(
  4136. &rtd->card->component_dev_list,
  4137. struct snd_soc_component,
  4138. card_aux_list);
  4139. if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4140. !strcmp(aux_comp->name, WSA8810_NAME_2)) {
  4141. wsa_macro_set_spkr_mode(rtd->codec,
  4142. WSA_MACRO_SPKR_MODE_1);
  4143. wsa_macro_set_spkr_gain_offset(rtd->codec,
  4144. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4145. }
  4146. }
  4147. card = rtd->card->snd_card;
  4148. if (!pdata->codec_root)
  4149. pdata->codec_root = snd_info_create_subdir(card->module,
  4150. "codecs", card->proc_root);
  4151. if (!pdata->codec_root) {
  4152. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4153. __func__);
  4154. ret = 0;
  4155. goto done;
  4156. }
  4157. bolero_info_create_codec_entry(pdata->codec_root, codec);
  4158. done:
  4159. return ret;
  4160. }
  4161. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4162. {
  4163. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4164. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161};
  4165. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4166. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4167. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4168. }
  4169. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  4170. struct snd_pcm_hw_params *params)
  4171. {
  4172. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4173. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4174. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4175. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4176. int ret = 0;
  4177. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  4178. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4179. u32 user_set_tx_ch = 0;
  4180. u32 rx_ch_count;
  4181. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4182. ret = snd_soc_dai_get_channel_map(codec_dai,
  4183. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4184. if (ret < 0) {
  4185. pr_err("%s: failed to get codec chan map, err:%d\n",
  4186. __func__, ret);
  4187. goto err;
  4188. }
  4189. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  4190. pr_debug("%s: rx_5_ch=%d\n", __func__,
  4191. slim_rx_cfg[5].channels);
  4192. rx_ch_count = slim_rx_cfg[5].channels;
  4193. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  4194. pr_debug("%s: rx_2_ch=%d\n", __func__,
  4195. slim_rx_cfg[2].channels);
  4196. rx_ch_count = slim_rx_cfg[2].channels;
  4197. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  4198. pr_debug("%s: rx_6_ch=%d\n", __func__,
  4199. slim_rx_cfg[6].channels);
  4200. rx_ch_count = slim_rx_cfg[6].channels;
  4201. } else {
  4202. pr_debug("%s: rx_0_ch=%d\n", __func__,
  4203. slim_rx_cfg[0].channels);
  4204. rx_ch_count = slim_rx_cfg[0].channels;
  4205. }
  4206. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4207. rx_ch_count, rx_ch);
  4208. if (ret < 0) {
  4209. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4210. __func__, ret);
  4211. goto err;
  4212. }
  4213. } else {
  4214. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  4215. codec_dai->name, codec_dai->id, user_set_tx_ch);
  4216. ret = snd_soc_dai_get_channel_map(codec_dai,
  4217. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4218. if (ret < 0) {
  4219. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  4220. __func__, ret);
  4221. goto err;
  4222. }
  4223. /* For <codec>_tx1 case */
  4224. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  4225. user_set_tx_ch = slim_tx_cfg[0].channels;
  4226. /* For <codec>_tx3 case */
  4227. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  4228. user_set_tx_ch = slim_tx_cfg[1].channels;
  4229. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  4230. user_set_tx_ch = msm_vi_feed_tx_ch;
  4231. else
  4232. user_set_tx_ch = tx_ch_cnt;
  4233. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  4234. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  4235. tx_ch_cnt, dai_link->id);
  4236. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4237. user_set_tx_ch, tx_ch, 0, 0);
  4238. if (ret < 0)
  4239. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  4240. __func__, ret);
  4241. }
  4242. err:
  4243. return ret;
  4244. }
  4245. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4246. struct snd_pcm_hw_params *params)
  4247. {
  4248. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4249. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4250. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4251. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4252. int ret = 0;
  4253. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4254. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4255. u32 user_set_tx_ch = 0;
  4256. u32 user_set_rx_ch = 0;
  4257. u32 ch_id;
  4258. ret = snd_soc_dai_get_channel_map(codec_dai,
  4259. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4260. &rx_ch_cdc_dma);
  4261. if (ret < 0) {
  4262. pr_err("%s: failed to get codec chan map, err:%d\n",
  4263. __func__, ret);
  4264. goto err;
  4265. }
  4266. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4267. switch (dai_link->id) {
  4268. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4269. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4270. {
  4271. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4272. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4273. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4274. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4275. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4276. user_set_rx_ch, &rx_ch_cdc_dma);
  4277. if (ret < 0) {
  4278. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4279. __func__, ret);
  4280. goto err;
  4281. }
  4282. }
  4283. break;
  4284. }
  4285. } else {
  4286. switch (dai_link->id) {
  4287. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4288. {
  4289. user_set_tx_ch = msm_vi_feed_tx_ch;
  4290. }
  4291. break;
  4292. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4293. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4294. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4295. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4296. {
  4297. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4298. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4299. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4300. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4301. }
  4302. break;
  4303. }
  4304. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4305. &tx_ch_cdc_dma, 0, 0);
  4306. if (ret < 0) {
  4307. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4308. __func__, ret);
  4309. goto err;
  4310. }
  4311. }
  4312. err:
  4313. return ret;
  4314. }
  4315. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4316. struct snd_pcm_hw_params *params)
  4317. {
  4318. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4319. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4320. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4321. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4322. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4323. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4324. int ret;
  4325. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4326. codec_dai->name, codec_dai->id);
  4327. ret = snd_soc_dai_get_channel_map(codec_dai,
  4328. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4329. if (ret) {
  4330. dev_err(rtd->dev,
  4331. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4332. __func__, ret);
  4333. goto err;
  4334. }
  4335. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4336. __func__, tx_ch_cnt, dai_link->id);
  4337. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4338. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4339. if (ret)
  4340. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4341. __func__, ret);
  4342. err:
  4343. return ret;
  4344. }
  4345. static int msm_get_port_id(int be_id)
  4346. {
  4347. int afe_port_id;
  4348. switch (be_id) {
  4349. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  4350. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  4351. break;
  4352. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  4353. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  4354. break;
  4355. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  4356. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  4357. break;
  4358. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  4359. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  4360. break;
  4361. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4362. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  4363. break;
  4364. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4365. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  4366. break;
  4367. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4368. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  4369. break;
  4370. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4371. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  4372. break;
  4373. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4374. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  4375. break;
  4376. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4377. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  4378. break;
  4379. default:
  4380. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  4381. afe_port_id = -EINVAL;
  4382. }
  4383. return afe_port_id;
  4384. }
  4385. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  4386. {
  4387. u32 bit_per_sample;
  4388. switch (bit_format) {
  4389. case SNDRV_PCM_FORMAT_S32_LE:
  4390. case SNDRV_PCM_FORMAT_S24_3LE:
  4391. case SNDRV_PCM_FORMAT_S24_LE:
  4392. bit_per_sample = 32;
  4393. break;
  4394. case SNDRV_PCM_FORMAT_S16_LE:
  4395. default:
  4396. bit_per_sample = 16;
  4397. break;
  4398. }
  4399. return bit_per_sample;
  4400. }
  4401. static void update_mi2s_clk_val(int dai_id, int stream)
  4402. {
  4403. u32 bit_per_sample;
  4404. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4405. bit_per_sample =
  4406. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  4407. mi2s_clk[dai_id].clk_freq_in_hz =
  4408. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4409. } else {
  4410. bit_per_sample =
  4411. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4412. mi2s_clk[dai_id].clk_freq_in_hz =
  4413. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4414. }
  4415. }
  4416. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4417. {
  4418. int ret = 0;
  4419. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4420. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4421. int port_id = 0;
  4422. int index = cpu_dai->id;
  4423. port_id = msm_get_port_id(rtd->dai_link->id);
  4424. if (port_id < 0) {
  4425. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4426. ret = port_id;
  4427. goto err;
  4428. }
  4429. if (enable) {
  4430. update_mi2s_clk_val(index, substream->stream);
  4431. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4432. mi2s_clk[index].clk_freq_in_hz);
  4433. }
  4434. mi2s_clk[index].enable = enable;
  4435. ret = afe_set_lpass_clock_v2(port_id,
  4436. &mi2s_clk[index]);
  4437. if (ret < 0) {
  4438. dev_err(rtd->card->dev,
  4439. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4440. __func__, port_id, ret);
  4441. goto err;
  4442. }
  4443. err:
  4444. return ret;
  4445. }
  4446. static int msm_set_pinctrl(struct msm_pinctrl_info *pinctrl_info,
  4447. enum pinctrl_pin_state new_state)
  4448. {
  4449. int ret = 0;
  4450. int curr_state = 0;
  4451. if (pinctrl_info == NULL) {
  4452. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4453. ret = -EINVAL;
  4454. goto err;
  4455. }
  4456. if (pinctrl_info->pinctrl == NULL) {
  4457. pr_err("%s: pinctrl_info->pinctrl is NULL\n", __func__);
  4458. ret = -EINVAL;
  4459. goto err;
  4460. }
  4461. curr_state = pinctrl_info->curr_state;
  4462. pinctrl_info->curr_state = new_state;
  4463. pr_debug("%s: curr_state = %s new_state = %s\n", __func__,
  4464. pin_states[curr_state], pin_states[pinctrl_info->curr_state]);
  4465. if (curr_state == pinctrl_info->curr_state) {
  4466. pr_debug("%s: Already in same state\n", __func__);
  4467. goto err;
  4468. }
  4469. if (curr_state != STATE_DISABLE &&
  4470. pinctrl_info->curr_state != STATE_DISABLE) {
  4471. pr_debug("%s: state already active cannot switch\n", __func__);
  4472. ret = -EIO;
  4473. goto err;
  4474. }
  4475. switch (pinctrl_info->curr_state) {
  4476. case STATE_MI2S_ACTIVE:
  4477. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4478. pinctrl_info->mi2s_active);
  4479. if (ret) {
  4480. pr_err("%s: MI2S state select failed with %d\n",
  4481. __func__, ret);
  4482. ret = -EIO;
  4483. goto err;
  4484. }
  4485. break;
  4486. case STATE_TDM_ACTIVE:
  4487. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4488. pinctrl_info->tdm_active);
  4489. if (ret) {
  4490. pr_err("%s: TDM state select failed with %d\n",
  4491. __func__, ret);
  4492. ret = -EIO;
  4493. goto err;
  4494. }
  4495. break;
  4496. case STATE_DISABLE:
  4497. if (curr_state == STATE_MI2S_ACTIVE) {
  4498. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4499. pinctrl_info->mi2s_disable);
  4500. } else {
  4501. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4502. pinctrl_info->tdm_disable);
  4503. }
  4504. if (ret) {
  4505. pr_err("%s: state disable failed with %d\n",
  4506. __func__, ret);
  4507. ret = -EIO;
  4508. goto err;
  4509. }
  4510. break;
  4511. default:
  4512. pr_err("%s: TLMM pin state is invalid\n", __func__);
  4513. return -EINVAL;
  4514. }
  4515. err:
  4516. return ret;
  4517. }
  4518. static void msm_release_pinctrl(struct platform_device *pdev)
  4519. {
  4520. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4521. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4522. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4523. if (pinctrl_info->pinctrl) {
  4524. devm_pinctrl_put(pinctrl_info->pinctrl);
  4525. pinctrl_info->pinctrl = NULL;
  4526. }
  4527. }
  4528. static int msm_get_pinctrl(struct platform_device *pdev)
  4529. {
  4530. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4531. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4532. struct msm_pinctrl_info *pinctrl_info = NULL;
  4533. struct pinctrl *pinctrl;
  4534. int ret;
  4535. pinctrl_info = &pdata->pinctrl_info;
  4536. if (pinctrl_info == NULL) {
  4537. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4538. return -EINVAL;
  4539. }
  4540. pinctrl = devm_pinctrl_get(&pdev->dev);
  4541. if (IS_ERR_OR_NULL(pinctrl)) {
  4542. pr_err("%s: Unable to get pinctrl handle\n", __func__);
  4543. return -EINVAL;
  4544. }
  4545. pinctrl_info->pinctrl = pinctrl;
  4546. /* get all the states handles from Device Tree */
  4547. pinctrl_info->mi2s_disable = pinctrl_lookup_state(pinctrl,
  4548. "quat-mi2s-sleep");
  4549. if (IS_ERR(pinctrl_info->mi2s_disable)) {
  4550. pr_err("%s: could not get mi2s_disable pinstate\n", __func__);
  4551. goto err;
  4552. }
  4553. pinctrl_info->mi2s_active = pinctrl_lookup_state(pinctrl,
  4554. "quat-mi2s-active");
  4555. if (IS_ERR(pinctrl_info->mi2s_active)) {
  4556. pr_err("%s: could not get mi2s_active pinstate\n", __func__);
  4557. goto err;
  4558. }
  4559. pinctrl_info->tdm_disable = pinctrl_lookup_state(pinctrl,
  4560. "quat-tdm-sleep");
  4561. if (IS_ERR(pinctrl_info->tdm_disable)) {
  4562. pr_err("%s: could not get tdm_disable pinstate\n", __func__);
  4563. goto err;
  4564. }
  4565. pinctrl_info->tdm_active = pinctrl_lookup_state(pinctrl,
  4566. "quat-tdm-active");
  4567. if (IS_ERR(pinctrl_info->tdm_active)) {
  4568. pr_err("%s: could not get tdm_active pinstate\n",
  4569. __func__);
  4570. goto err;
  4571. }
  4572. /* Reset the TLMM pins to a default state */
  4573. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4574. pinctrl_info->mi2s_disable);
  4575. if (ret != 0) {
  4576. pr_err("%s: Disable TLMM pins failed with %d\n",
  4577. __func__, ret);
  4578. ret = -EIO;
  4579. goto err;
  4580. }
  4581. pinctrl_info->curr_state = STATE_DISABLE;
  4582. return 0;
  4583. err:
  4584. devm_pinctrl_put(pinctrl);
  4585. pinctrl_info->pinctrl = NULL;
  4586. return -EINVAL;
  4587. }
  4588. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4589. struct snd_pcm_hw_params *params)
  4590. {
  4591. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4592. struct snd_interval *rate = hw_param_interval(params,
  4593. SNDRV_PCM_HW_PARAM_RATE);
  4594. struct snd_interval *channels = hw_param_interval(params,
  4595. SNDRV_PCM_HW_PARAM_CHANNELS);
  4596. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4597. channels->min = channels->max =
  4598. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4599. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4600. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4601. rate->min = rate->max =
  4602. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4603. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4604. channels->min = channels->max =
  4605. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4606. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4607. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4608. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4609. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4610. channels->min = channels->max =
  4611. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4612. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4613. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4614. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4615. } else {
  4616. pr_err("%s: dai id 0x%x not supported\n",
  4617. __func__, cpu_dai->id);
  4618. return -EINVAL;
  4619. }
  4620. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4621. __func__, cpu_dai->id, channels->max, rate->max,
  4622. params_format(params));
  4623. return 0;
  4624. }
  4625. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4626. struct snd_pcm_hw_params *params)
  4627. {
  4628. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4629. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4630. int ret = 0;
  4631. int slot_width = 32;
  4632. int channels, slots;
  4633. unsigned int slot_mask, rate, clk_freq;
  4634. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4635. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4636. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4637. switch (cpu_dai->id) {
  4638. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4639. slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4640. break;
  4641. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4642. slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4643. break;
  4644. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4645. slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4646. break;
  4647. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4648. slots = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4649. break;
  4650. case AFE_PORT_ID_QUINARY_TDM_RX:
  4651. slots = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4652. break;
  4653. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4654. slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4655. break;
  4656. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4657. slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4658. break;
  4659. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4660. slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4661. break;
  4662. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4663. slots = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4664. break;
  4665. case AFE_PORT_ID_QUINARY_TDM_TX:
  4666. slots = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4667. break;
  4668. default:
  4669. pr_err("%s: dai id 0x%x not supported\n",
  4670. __func__, cpu_dai->id);
  4671. return -EINVAL;
  4672. }
  4673. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4674. /*2 slot config - bits 0 and 1 set for the first two slots */
  4675. slot_mask = 0x0000FFFF >> (16-slots);
  4676. channels = slots;
  4677. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  4678. __func__, slot_width, slots);
  4679. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4680. slots, slot_width);
  4681. if (ret < 0) {
  4682. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4683. __func__, ret);
  4684. goto end;
  4685. }
  4686. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4687. 0, NULL, channels, slot_offset);
  4688. if (ret < 0) {
  4689. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4690. __func__, ret);
  4691. goto end;
  4692. }
  4693. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4694. /*2 slot config - bits 0 and 1 set for the first two slots */
  4695. slot_mask = 0x0000FFFF >> (16-slots);
  4696. channels = slots;
  4697. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  4698. __func__, slot_width, slots);
  4699. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4700. slots, slot_width);
  4701. if (ret < 0) {
  4702. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4703. __func__, ret);
  4704. goto end;
  4705. }
  4706. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4707. channels, slot_offset, 0, NULL);
  4708. if (ret < 0) {
  4709. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4710. __func__, ret);
  4711. goto end;
  4712. }
  4713. } else {
  4714. ret = -EINVAL;
  4715. pr_err("%s: invalid use case, err:%d\n",
  4716. __func__, ret);
  4717. goto end;
  4718. }
  4719. rate = params_rate(params);
  4720. clk_freq = rate * slot_width * slots;
  4721. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4722. if (ret < 0)
  4723. pr_err("%s: failed to set tdm clk, err:%d\n",
  4724. __func__, ret);
  4725. end:
  4726. return ret;
  4727. }
  4728. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  4729. {
  4730. int ret = 0;
  4731. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4732. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4733. struct snd_soc_card *card = rtd->card;
  4734. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4735. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4736. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4737. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4738. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4739. ret = msm_set_pinctrl(pinctrl_info, STATE_TDM_ACTIVE);
  4740. if (ret)
  4741. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4742. __func__, ret);
  4743. }
  4744. return ret;
  4745. }
  4746. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4747. {
  4748. int ret = 0;
  4749. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4750. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4751. struct snd_soc_card *card = rtd->card;
  4752. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4753. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4754. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4755. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4756. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4757. ret = msm_set_pinctrl(pinctrl_info, STATE_DISABLE);
  4758. if (ret)
  4759. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4760. __func__, ret);
  4761. }
  4762. }
  4763. static struct snd_soc_ops qcs405_tdm_be_ops = {
  4764. .hw_params = qcs405_tdm_snd_hw_params,
  4765. .startup = qcs405_tdm_snd_startup,
  4766. .shutdown = qcs405_tdm_snd_shutdown
  4767. };
  4768. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4769. {
  4770. cpumask_t mask;
  4771. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4772. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4773. cpumask_clear(&mask);
  4774. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4775. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4776. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4777. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4778. pm_qos_add_request(&substream->latency_pm_qos_req,
  4779. PM_QOS_CPU_DMA_LATENCY,
  4780. MSM_LL_QOS_VALUE);
  4781. return 0;
  4782. }
  4783. static struct snd_soc_ops msm_fe_qos_ops = {
  4784. .prepare = msm_fe_qos_prepare,
  4785. };
  4786. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4787. {
  4788. int ret = 0;
  4789. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4790. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4791. int index = cpu_dai->id;
  4792. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4793. struct snd_soc_card *card = rtd->card;
  4794. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4795. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4796. int ret_pinctrl = 0;
  4797. dev_dbg(rtd->card->dev,
  4798. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4799. __func__, substream->name, substream->stream,
  4800. cpu_dai->name, cpu_dai->id);
  4801. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4802. ret = -EINVAL;
  4803. dev_err(rtd->card->dev,
  4804. "%s: CPU DAI id (%d) out of range\n",
  4805. __func__, cpu_dai->id);
  4806. goto err;
  4807. }
  4808. /*
  4809. * Mutex protection in case the same MI2S
  4810. * interface using for both TX and RX so
  4811. * that the same clock won't be enable twice.
  4812. */
  4813. mutex_lock(&mi2s_intf_conf[index].lock);
  4814. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4815. /* Check if msm needs to provide the clock to the interface */
  4816. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4817. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4818. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4819. }
  4820. ret = msm_mi2s_set_sclk(substream, true);
  4821. if (ret < 0) {
  4822. dev_err(rtd->card->dev,
  4823. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4824. __func__, ret);
  4825. goto clean_up;
  4826. }
  4827. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4828. if (ret < 0) {
  4829. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4830. __func__, index, ret);
  4831. goto clk_off;
  4832. }
  4833. if (index == QUAT_MI2S) {
  4834. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4835. STATE_MI2S_ACTIVE);
  4836. if (ret_pinctrl)
  4837. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4838. __func__, ret_pinctrl);
  4839. }
  4840. }
  4841. clk_off:
  4842. if (ret < 0)
  4843. msm_mi2s_set_sclk(substream, false);
  4844. clean_up:
  4845. if (ret < 0)
  4846. mi2s_intf_conf[index].ref_cnt--;
  4847. mutex_unlock(&mi2s_intf_conf[index].lock);
  4848. err:
  4849. return ret;
  4850. }
  4851. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4852. {
  4853. int ret;
  4854. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4855. int index = rtd->cpu_dai->id;
  4856. struct snd_soc_card *card = rtd->card;
  4857. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4858. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4859. int ret_pinctrl = 0;
  4860. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4861. substream->name, substream->stream);
  4862. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4863. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4864. return;
  4865. }
  4866. mutex_lock(&mi2s_intf_conf[index].lock);
  4867. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4868. ret = msm_mi2s_set_sclk(substream, false);
  4869. if (ret < 0)
  4870. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4871. __func__, index, ret);
  4872. if (index == QUAT_MI2S) {
  4873. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4874. STATE_DISABLE);
  4875. if (ret_pinctrl)
  4876. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4877. __func__, ret_pinctrl);
  4878. }
  4879. }
  4880. mutex_unlock(&mi2s_intf_conf[index].lock);
  4881. }
  4882. static int msm_spdif_set_clk(struct snd_pcm_substream *substream, bool enable)
  4883. {
  4884. int ret = 0;
  4885. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4886. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4887. int port_id = cpu_dai->id;
  4888. struct afe_clk_set clk_cfg;
  4889. clk_cfg.clk_set_minor_version = Q6AFE_LPASS_CLK_CONFIG_API_VERSION;
  4890. clk_cfg.clk_attri = Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO;
  4891. clk_cfg.clk_root = Q6AFE_LPASS_CLK_ROOT_DEFAULT;
  4892. clk_cfg.enable = enable;
  4893. /* Set core clock (based on sample rate for RX, fixed for TX) */
  4894. switch (port_id) {
  4895. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  4896. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_CORE;
  4897. /* rate x 2ch x 2_for_biphase_coding x 32_bits_per_sample */
  4898. clk_cfg.clk_freq_in_hz =
  4899. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate * 2 * 2 * 32;
  4900. break;
  4901. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  4902. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_CORE;
  4903. clk_cfg.clk_freq_in_hz =
  4904. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate * 2 * 2 * 32;
  4905. break;
  4906. case AFE_PORT_ID_PRIMARY_SPDIF_TX:
  4907. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_INPUT_CORE;
  4908. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_204_P8_MHZ;
  4909. break;
  4910. case AFE_PORT_ID_SECONDARY_SPDIF_TX:
  4911. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_INPUT_CORE;
  4912. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_204_P8_MHZ;
  4913. break;
  4914. }
  4915. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  4916. if (ret < 0) {
  4917. dev_err(rtd->card->dev,
  4918. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4919. __func__, port_id, ret);
  4920. goto err;
  4921. }
  4922. /* Set NPL clock for RX in addition */
  4923. switch (port_id) {
  4924. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  4925. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_NPL;
  4926. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  4927. if (ret < 0) {
  4928. dev_err(rtd->card->dev,
  4929. "%s: afe NPL failed port 0x%x, err:%d\n",
  4930. __func__, port_id, ret);
  4931. goto err;
  4932. }
  4933. break;
  4934. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  4935. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_NPL;
  4936. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  4937. if (ret < 0) {
  4938. dev_err(rtd->card->dev,
  4939. "%s: afe NPL failed for port 0x%x, err:%d\n",
  4940. __func__, port_id, ret);
  4941. goto err;
  4942. }
  4943. break;
  4944. }
  4945. if (enable) {
  4946. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4947. clk_cfg.clk_freq_in_hz);
  4948. }
  4949. err:
  4950. return ret;
  4951. }
  4952. static int msm_spdif_snd_startup(struct snd_pcm_substream *substream)
  4953. {
  4954. int ret = 0;
  4955. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4956. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4957. int port_id = cpu_dai->id;
  4958. dev_dbg(rtd->card->dev,
  4959. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4960. __func__, substream->name, substream->stream,
  4961. cpu_dai->name, cpu_dai->id);
  4962. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  4963. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  4964. ret = -EINVAL;
  4965. dev_err(rtd->card->dev,
  4966. "%s: CPU DAI id (%d) out of range\n",
  4967. __func__, cpu_dai->id);
  4968. goto err;
  4969. }
  4970. ret = msm_spdif_set_clk(substream, true);
  4971. if (ret < 0) {
  4972. dev_err(rtd->card->dev,
  4973. "%s: afe lpass clock failed to enable (%d), err:%d\n",
  4974. __func__, port_id, ret);
  4975. }
  4976. err:
  4977. return ret;
  4978. }
  4979. static void msm_spdif_snd_shutdown(struct snd_pcm_substream *substream)
  4980. {
  4981. int ret;
  4982. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4983. int port_id = rtd->cpu_dai->id;
  4984. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4985. substream->name, substream->stream);
  4986. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  4987. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  4988. pr_err("%s:invalid SPDIF DAI(%d)\n", __func__, port_id);
  4989. return;
  4990. }
  4991. ret = msm_spdif_set_clk(substream, false);
  4992. if (ret < 0)
  4993. pr_err("%s:clock disable failed for SPDIF (%d); ret=%d\n",
  4994. __func__, port_id, ret);
  4995. }
  4996. static struct snd_soc_ops msm_mi2s_be_ops = {
  4997. .startup = msm_mi2s_snd_startup,
  4998. .shutdown = msm_mi2s_snd_shutdown,
  4999. };
  5000. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  5001. .hw_params = msm_snd_cdc_dma_hw_params,
  5002. };
  5003. static struct snd_soc_ops msm_be_ops = {
  5004. .hw_params = msm_snd_hw_params,
  5005. };
  5006. static struct snd_soc_ops msm_wcn_ops = {
  5007. .hw_params = msm_wcn_hw_params,
  5008. };
  5009. static struct snd_soc_ops msm_spdif_be_ops = {
  5010. .startup = msm_spdif_snd_startup,
  5011. .shutdown = msm_spdif_snd_shutdown,
  5012. };
  5013. /* Digital audio interface glue - connects codec <---> CPU */
  5014. static struct snd_soc_dai_link msm_common_dai_links[] = {
  5015. /* FrontEnd DAI Links */
  5016. {
  5017. .name = MSM_DAILINK_NAME(Media1),
  5018. .stream_name = "MultiMedia1",
  5019. .cpu_dai_name = "MultiMedia1",
  5020. .platform_name = "msm-pcm-dsp.0",
  5021. .dynamic = 1,
  5022. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5023. .dpcm_playback = 1,
  5024. .dpcm_capture = 1,
  5025. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5026. SND_SOC_DPCM_TRIGGER_POST},
  5027. .codec_dai_name = "snd-soc-dummy-dai",
  5028. .codec_name = "snd-soc-dummy",
  5029. .ignore_suspend = 1,
  5030. /* this dainlink has playback support */
  5031. .ignore_pmdown_time = 1,
  5032. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  5033. },
  5034. {
  5035. .name = MSM_DAILINK_NAME(Media2),
  5036. .stream_name = "MultiMedia2",
  5037. .cpu_dai_name = "MultiMedia2",
  5038. .platform_name = "msm-pcm-dsp.0",
  5039. .dynamic = 1,
  5040. .dpcm_playback = 1,
  5041. .dpcm_capture = 1,
  5042. .codec_dai_name = "snd-soc-dummy-dai",
  5043. .codec_name = "snd-soc-dummy",
  5044. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5045. SND_SOC_DPCM_TRIGGER_POST},
  5046. .ignore_suspend = 1,
  5047. /* this dainlink has playback support */
  5048. .ignore_pmdown_time = 1,
  5049. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  5050. },
  5051. {
  5052. .name = "VoiceMMode1",
  5053. .stream_name = "VoiceMMode1",
  5054. .cpu_dai_name = "VoiceMMode1",
  5055. .platform_name = "msm-pcm-voice",
  5056. .dynamic = 1,
  5057. .dpcm_playback = 1,
  5058. .dpcm_capture = 1,
  5059. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5060. SND_SOC_DPCM_TRIGGER_POST},
  5061. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5062. .ignore_suspend = 1,
  5063. .ignore_pmdown_time = 1,
  5064. .codec_dai_name = "snd-soc-dummy-dai",
  5065. .codec_name = "snd-soc-dummy",
  5066. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  5067. },
  5068. {
  5069. .name = "MSM VoIP",
  5070. .stream_name = "VoIP",
  5071. .cpu_dai_name = "VoIP",
  5072. .platform_name = "msm-voip-dsp",
  5073. .dynamic = 1,
  5074. .dpcm_playback = 1,
  5075. .dpcm_capture = 1,
  5076. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5077. SND_SOC_DPCM_TRIGGER_POST},
  5078. .codec_dai_name = "snd-soc-dummy-dai",
  5079. .codec_name = "snd-soc-dummy",
  5080. .ignore_suspend = 1,
  5081. /* this dainlink has playback support */
  5082. .ignore_pmdown_time = 1,
  5083. .id = MSM_FRONTEND_DAI_VOIP,
  5084. },
  5085. {
  5086. .name = MSM_DAILINK_NAME(ULL),
  5087. .stream_name = "MultiMedia3",
  5088. .cpu_dai_name = "MultiMedia3",
  5089. .platform_name = "msm-pcm-dsp.2",
  5090. .dynamic = 1,
  5091. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5092. .dpcm_playback = 1,
  5093. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5094. SND_SOC_DPCM_TRIGGER_POST},
  5095. .codec_dai_name = "snd-soc-dummy-dai",
  5096. .codec_name = "snd-soc-dummy",
  5097. .ignore_suspend = 1,
  5098. /* this dainlink has playback support */
  5099. .ignore_pmdown_time = 1,
  5100. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  5101. },
  5102. /* Hostless PCM purpose */
  5103. {
  5104. .name = "SLIMBUS_0 Hostless",
  5105. .stream_name = "SLIMBUS_0 Hostless",
  5106. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  5107. .platform_name = "msm-pcm-hostless",
  5108. .dynamic = 1,
  5109. .dpcm_playback = 1,
  5110. .dpcm_capture = 1,
  5111. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5112. SND_SOC_DPCM_TRIGGER_POST},
  5113. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5114. .ignore_suspend = 1,
  5115. /* this dailink has playback support */
  5116. .ignore_pmdown_time = 1,
  5117. .codec_dai_name = "snd-soc-dummy-dai",
  5118. .codec_name = "snd-soc-dummy",
  5119. },
  5120. {
  5121. .name = "MSM AFE-PCM RX",
  5122. .stream_name = "AFE-PROXY RX",
  5123. .cpu_dai_name = "msm-dai-q6-dev.241",
  5124. .codec_name = "msm-stub-codec.1",
  5125. .codec_dai_name = "msm-stub-rx",
  5126. .platform_name = "msm-pcm-afe",
  5127. .dpcm_playback = 1,
  5128. .ignore_suspend = 1,
  5129. /* this dainlink has playback support */
  5130. .ignore_pmdown_time = 1,
  5131. },
  5132. {
  5133. .name = "MSM AFE-PCM TX",
  5134. .stream_name = "AFE-PROXY TX",
  5135. .cpu_dai_name = "msm-dai-q6-dev.240",
  5136. .codec_name = "msm-stub-codec.1",
  5137. .codec_dai_name = "msm-stub-tx",
  5138. .platform_name = "msm-pcm-afe",
  5139. .dpcm_capture = 1,
  5140. .ignore_suspend = 1,
  5141. },
  5142. {
  5143. .name = MSM_DAILINK_NAME(Compress1),
  5144. .stream_name = "Compress1",
  5145. .cpu_dai_name = "MultiMedia4",
  5146. .platform_name = "msm-compress-dsp",
  5147. .dynamic = 1,
  5148. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5149. .dpcm_playback = 1,
  5150. .dpcm_capture = 1,
  5151. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5152. SND_SOC_DPCM_TRIGGER_POST},
  5153. .codec_dai_name = "snd-soc-dummy-dai",
  5154. .codec_name = "snd-soc-dummy",
  5155. .ignore_suspend = 1,
  5156. .ignore_pmdown_time = 1,
  5157. /* this dainlink has playback support */
  5158. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  5159. },
  5160. {
  5161. .name = "AUXPCM Hostless",
  5162. .stream_name = "AUXPCM Hostless",
  5163. .cpu_dai_name = "AUXPCM_HOSTLESS",
  5164. .platform_name = "msm-pcm-hostless",
  5165. .dynamic = 1,
  5166. .dpcm_playback = 1,
  5167. .dpcm_capture = 1,
  5168. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5169. SND_SOC_DPCM_TRIGGER_POST},
  5170. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5171. .ignore_suspend = 1,
  5172. /* this dainlink has playback support */
  5173. .ignore_pmdown_time = 1,
  5174. .codec_dai_name = "snd-soc-dummy-dai",
  5175. .codec_name = "snd-soc-dummy",
  5176. },
  5177. {
  5178. .name = "SLIMBUS_1 Hostless",
  5179. .stream_name = "SLIMBUS_1 Hostless",
  5180. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  5181. .platform_name = "msm-pcm-hostless",
  5182. .dynamic = 1,
  5183. .dpcm_playback = 1,
  5184. .dpcm_capture = 1,
  5185. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5186. SND_SOC_DPCM_TRIGGER_POST},
  5187. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5188. .ignore_suspend = 1,
  5189. /* this dailink has playback support */
  5190. .ignore_pmdown_time = 1,
  5191. .codec_dai_name = "snd-soc-dummy-dai",
  5192. .codec_name = "snd-soc-dummy",
  5193. },
  5194. {
  5195. .name = "SLIMBUS_3 Hostless",
  5196. .stream_name = "SLIMBUS_3 Hostless",
  5197. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  5198. .platform_name = "msm-pcm-hostless",
  5199. .dynamic = 1,
  5200. .dpcm_playback = 1,
  5201. .dpcm_capture = 1,
  5202. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5203. SND_SOC_DPCM_TRIGGER_POST},
  5204. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5205. .ignore_suspend = 1,
  5206. /* this dailink has playback support */
  5207. .ignore_pmdown_time = 1,
  5208. .codec_dai_name = "snd-soc-dummy-dai",
  5209. .codec_name = "snd-soc-dummy",
  5210. },
  5211. {
  5212. .name = "SLIMBUS_4 Hostless",
  5213. .stream_name = "SLIMBUS_4 Hostless",
  5214. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  5215. .platform_name = "msm-pcm-hostless",
  5216. .dynamic = 1,
  5217. .dpcm_playback = 1,
  5218. .dpcm_capture = 1,
  5219. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5220. SND_SOC_DPCM_TRIGGER_POST},
  5221. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5222. .ignore_suspend = 1,
  5223. /* this dailink has playback support */
  5224. .ignore_pmdown_time = 1,
  5225. .codec_dai_name = "snd-soc-dummy-dai",
  5226. .codec_name = "snd-soc-dummy",
  5227. },
  5228. {
  5229. .name = MSM_DAILINK_NAME(LowLatency),
  5230. .stream_name = "MultiMedia5",
  5231. .cpu_dai_name = "MultiMedia5",
  5232. .platform_name = "msm-pcm-dsp.1",
  5233. .dynamic = 1,
  5234. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5235. .dpcm_playback = 1,
  5236. .dpcm_capture = 1,
  5237. .codec_dai_name = "snd-soc-dummy-dai",
  5238. .codec_name = "snd-soc-dummy",
  5239. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5240. SND_SOC_DPCM_TRIGGER_POST},
  5241. .ignore_suspend = 1,
  5242. /* this dainlink has playback support */
  5243. .ignore_pmdown_time = 1,
  5244. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  5245. .ops = &msm_fe_qos_ops,
  5246. },
  5247. {
  5248. .name = "Listen 1 Audio Service",
  5249. .stream_name = "Listen 1 Audio Service",
  5250. .cpu_dai_name = "LSM1",
  5251. .platform_name = "msm-lsm-client",
  5252. .dynamic = 1,
  5253. .dpcm_capture = 1,
  5254. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5255. SND_SOC_DPCM_TRIGGER_POST },
  5256. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5257. .ignore_suspend = 1,
  5258. .codec_dai_name = "snd-soc-dummy-dai",
  5259. .codec_name = "snd-soc-dummy",
  5260. .id = MSM_FRONTEND_DAI_LSM1,
  5261. },
  5262. /* Multiple Tunnel instances */
  5263. {
  5264. .name = MSM_DAILINK_NAME(Compress2),
  5265. .stream_name = "Compress2",
  5266. .cpu_dai_name = "MultiMedia7",
  5267. .platform_name = "msm-compress-dsp",
  5268. .dynamic = 1,
  5269. .dpcm_playback = 1,
  5270. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5271. SND_SOC_DPCM_TRIGGER_POST},
  5272. .codec_dai_name = "snd-soc-dummy-dai",
  5273. .codec_name = "snd-soc-dummy",
  5274. .ignore_suspend = 1,
  5275. .ignore_pmdown_time = 1,
  5276. /* this dainlink has playback support */
  5277. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  5278. },
  5279. {
  5280. .name = MSM_DAILINK_NAME(MultiMedia10),
  5281. .stream_name = "MultiMedia10",
  5282. .cpu_dai_name = "MultiMedia10",
  5283. .platform_name = "msm-pcm-dsp.1",
  5284. .dynamic = 1,
  5285. .dpcm_playback = 1,
  5286. .dpcm_capture = 1,
  5287. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5288. SND_SOC_DPCM_TRIGGER_POST},
  5289. .codec_dai_name = "snd-soc-dummy-dai",
  5290. .codec_name = "snd-soc-dummy",
  5291. .ignore_suspend = 1,
  5292. .ignore_pmdown_time = 1,
  5293. /* this dainlink has playback support */
  5294. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  5295. },
  5296. {
  5297. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  5298. .stream_name = "MM_NOIRQ",
  5299. .cpu_dai_name = "MultiMedia8",
  5300. .platform_name = "msm-pcm-dsp-noirq",
  5301. .dynamic = 1,
  5302. .dpcm_playback = 1,
  5303. .dpcm_capture = 1,
  5304. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5305. SND_SOC_DPCM_TRIGGER_POST},
  5306. .codec_dai_name = "snd-soc-dummy-dai",
  5307. .codec_name = "snd-soc-dummy",
  5308. .ignore_suspend = 1,
  5309. .ignore_pmdown_time = 1,
  5310. /* this dainlink has playback support */
  5311. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  5312. .ops = &msm_fe_qos_ops,
  5313. },
  5314. /* HDMI Hostless */
  5315. {
  5316. .name = "HDMI_RX_HOSTLESS",
  5317. .stream_name = "HDMI_RX_HOSTLESS",
  5318. .cpu_dai_name = "HDMI_HOSTLESS",
  5319. .platform_name = "msm-pcm-hostless",
  5320. .dynamic = 1,
  5321. .dpcm_playback = 1,
  5322. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5323. SND_SOC_DPCM_TRIGGER_POST},
  5324. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5325. .ignore_suspend = 1,
  5326. .ignore_pmdown_time = 1,
  5327. .codec_dai_name = "snd-soc-dummy-dai",
  5328. .codec_name = "snd-soc-dummy",
  5329. },
  5330. {
  5331. .name = "VoiceMMode2",
  5332. .stream_name = "VoiceMMode2",
  5333. .cpu_dai_name = "VoiceMMode2",
  5334. .platform_name = "msm-pcm-voice",
  5335. .dynamic = 1,
  5336. .dpcm_playback = 1,
  5337. .dpcm_capture = 1,
  5338. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5339. SND_SOC_DPCM_TRIGGER_POST},
  5340. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5341. .ignore_suspend = 1,
  5342. .ignore_pmdown_time = 1,
  5343. .codec_dai_name = "snd-soc-dummy-dai",
  5344. .codec_name = "snd-soc-dummy",
  5345. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  5346. },
  5347. /* LSM FE */
  5348. {
  5349. .name = "Listen 2 Audio Service",
  5350. .stream_name = "Listen 2 Audio Service",
  5351. .cpu_dai_name = "LSM2",
  5352. .platform_name = "msm-lsm-client",
  5353. .dynamic = 1,
  5354. .dpcm_capture = 1,
  5355. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5356. SND_SOC_DPCM_TRIGGER_POST },
  5357. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5358. .ignore_suspend = 1,
  5359. .codec_dai_name = "snd-soc-dummy-dai",
  5360. .codec_name = "snd-soc-dummy",
  5361. .id = MSM_FRONTEND_DAI_LSM2,
  5362. },
  5363. {
  5364. .name = "Listen 3 Audio Service",
  5365. .stream_name = "Listen 3 Audio Service",
  5366. .cpu_dai_name = "LSM3",
  5367. .platform_name = "msm-lsm-client",
  5368. .dynamic = 1,
  5369. .dpcm_capture = 1,
  5370. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5371. SND_SOC_DPCM_TRIGGER_POST },
  5372. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5373. .ignore_suspend = 1,
  5374. .codec_dai_name = "snd-soc-dummy-dai",
  5375. .codec_name = "snd-soc-dummy",
  5376. .id = MSM_FRONTEND_DAI_LSM3,
  5377. },
  5378. {
  5379. .name = "Listen 4 Audio Service",
  5380. .stream_name = "Listen 4 Audio Service",
  5381. .cpu_dai_name = "LSM4",
  5382. .platform_name = "msm-lsm-client",
  5383. .dynamic = 1,
  5384. .dpcm_capture = 1,
  5385. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5386. SND_SOC_DPCM_TRIGGER_POST },
  5387. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5388. .ignore_suspend = 1,
  5389. .codec_dai_name = "snd-soc-dummy-dai",
  5390. .codec_name = "snd-soc-dummy",
  5391. .id = MSM_FRONTEND_DAI_LSM4,
  5392. },
  5393. {
  5394. .name = "Listen 5 Audio Service",
  5395. .stream_name = "Listen 5 Audio Service",
  5396. .cpu_dai_name = "LSM5",
  5397. .platform_name = "msm-lsm-client",
  5398. .dynamic = 1,
  5399. .dpcm_capture = 1,
  5400. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5401. SND_SOC_DPCM_TRIGGER_POST },
  5402. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5403. .ignore_suspend = 1,
  5404. .codec_dai_name = "snd-soc-dummy-dai",
  5405. .codec_name = "snd-soc-dummy",
  5406. .id = MSM_FRONTEND_DAI_LSM5,
  5407. },
  5408. {
  5409. .name = "Listen 6 Audio Service",
  5410. .stream_name = "Listen 6 Audio Service",
  5411. .cpu_dai_name = "LSM6",
  5412. .platform_name = "msm-lsm-client",
  5413. .dynamic = 1,
  5414. .dpcm_capture = 1,
  5415. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5416. SND_SOC_DPCM_TRIGGER_POST },
  5417. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5418. .ignore_suspend = 1,
  5419. .codec_dai_name = "snd-soc-dummy-dai",
  5420. .codec_name = "snd-soc-dummy",
  5421. .id = MSM_FRONTEND_DAI_LSM6,
  5422. },
  5423. {
  5424. .name = "Listen 7 Audio Service",
  5425. .stream_name = "Listen 7 Audio Service",
  5426. .cpu_dai_name = "LSM7",
  5427. .platform_name = "msm-lsm-client",
  5428. .dynamic = 1,
  5429. .dpcm_capture = 1,
  5430. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5431. SND_SOC_DPCM_TRIGGER_POST },
  5432. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5433. .ignore_suspend = 1,
  5434. .codec_dai_name = "snd-soc-dummy-dai",
  5435. .codec_name = "snd-soc-dummy",
  5436. .id = MSM_FRONTEND_DAI_LSM7,
  5437. },
  5438. {
  5439. .name = "Listen 8 Audio Service",
  5440. .stream_name = "Listen 8 Audio Service",
  5441. .cpu_dai_name = "LSM8",
  5442. .platform_name = "msm-lsm-client",
  5443. .dynamic = 1,
  5444. .dpcm_capture = 1,
  5445. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5446. SND_SOC_DPCM_TRIGGER_POST },
  5447. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5448. .ignore_suspend = 1,
  5449. .codec_dai_name = "snd-soc-dummy-dai",
  5450. .codec_name = "snd-soc-dummy",
  5451. .id = MSM_FRONTEND_DAI_LSM8,
  5452. },
  5453. {
  5454. .name = MSM_DAILINK_NAME(Media9),
  5455. .stream_name = "MultiMedia9",
  5456. .cpu_dai_name = "MultiMedia9",
  5457. .platform_name = "msm-pcm-dsp.0",
  5458. .dynamic = 1,
  5459. .dpcm_playback = 1,
  5460. .dpcm_capture = 1,
  5461. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5462. SND_SOC_DPCM_TRIGGER_POST},
  5463. .codec_dai_name = "snd-soc-dummy-dai",
  5464. .codec_name = "snd-soc-dummy",
  5465. .ignore_suspend = 1,
  5466. /* this dainlink has playback support */
  5467. .ignore_pmdown_time = 1,
  5468. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  5469. },
  5470. {
  5471. .name = MSM_DAILINK_NAME(Compress4),
  5472. .stream_name = "Compress4",
  5473. .cpu_dai_name = "MultiMedia11",
  5474. .platform_name = "msm-compress-dsp",
  5475. .dynamic = 1,
  5476. .dpcm_playback = 1,
  5477. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5478. SND_SOC_DPCM_TRIGGER_POST},
  5479. .codec_dai_name = "snd-soc-dummy-dai",
  5480. .codec_name = "snd-soc-dummy",
  5481. .ignore_suspend = 1,
  5482. .ignore_pmdown_time = 1,
  5483. /* this dainlink has playback support */
  5484. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5485. },
  5486. {
  5487. .name = MSM_DAILINK_NAME(Compress5),
  5488. .stream_name = "Compress5",
  5489. .cpu_dai_name = "MultiMedia12",
  5490. .platform_name = "msm-compress-dsp",
  5491. .dynamic = 1,
  5492. .dpcm_playback = 1,
  5493. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5494. SND_SOC_DPCM_TRIGGER_POST},
  5495. .codec_dai_name = "snd-soc-dummy-dai",
  5496. .codec_name = "snd-soc-dummy",
  5497. .ignore_suspend = 1,
  5498. .ignore_pmdown_time = 1,
  5499. /* this dainlink has playback support */
  5500. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5501. },
  5502. {
  5503. .name = MSM_DAILINK_NAME(Compress6),
  5504. .stream_name = "Compress6",
  5505. .cpu_dai_name = "MultiMedia13",
  5506. .platform_name = "msm-compress-dsp",
  5507. .dynamic = 1,
  5508. .dpcm_playback = 1,
  5509. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5510. SND_SOC_DPCM_TRIGGER_POST},
  5511. .codec_dai_name = "snd-soc-dummy-dai",
  5512. .codec_name = "snd-soc-dummy",
  5513. .ignore_suspend = 1,
  5514. .ignore_pmdown_time = 1,
  5515. /* this dainlink has playback support */
  5516. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5517. },
  5518. {
  5519. .name = MSM_DAILINK_NAME(Compress7),
  5520. .stream_name = "Compress7",
  5521. .cpu_dai_name = "MultiMedia14",
  5522. .platform_name = "msm-compress-dsp",
  5523. .dynamic = 1,
  5524. .dpcm_playback = 1,
  5525. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5526. SND_SOC_DPCM_TRIGGER_POST},
  5527. .codec_dai_name = "snd-soc-dummy-dai",
  5528. .codec_name = "snd-soc-dummy",
  5529. .ignore_suspend = 1,
  5530. .ignore_pmdown_time = 1,
  5531. /* this dainlink has playback support */
  5532. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5533. },
  5534. {
  5535. .name = MSM_DAILINK_NAME(Compress8),
  5536. .stream_name = "Compress8",
  5537. .cpu_dai_name = "MultiMedia15",
  5538. .platform_name = "msm-compress-dsp",
  5539. .dynamic = 1,
  5540. .dpcm_playback = 1,
  5541. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5542. SND_SOC_DPCM_TRIGGER_POST},
  5543. .codec_dai_name = "snd-soc-dummy-dai",
  5544. .codec_name = "snd-soc-dummy",
  5545. .ignore_suspend = 1,
  5546. .ignore_pmdown_time = 1,
  5547. /* this dainlink has playback support */
  5548. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5549. },
  5550. {
  5551. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5552. .stream_name = "MM_NOIRQ_2",
  5553. .cpu_dai_name = "MultiMedia16",
  5554. .platform_name = "msm-pcm-dsp-noirq",
  5555. .dynamic = 1,
  5556. .dpcm_playback = 1,
  5557. .dpcm_capture = 1,
  5558. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5559. SND_SOC_DPCM_TRIGGER_POST},
  5560. .codec_dai_name = "snd-soc-dummy-dai",
  5561. .codec_name = "snd-soc-dummy",
  5562. .ignore_suspend = 1,
  5563. .ignore_pmdown_time = 1,
  5564. /* this dainlink has playback support */
  5565. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5566. },
  5567. {
  5568. .name = "SLIMBUS_8 Hostless",
  5569. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5570. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5571. .platform_name = "msm-pcm-hostless",
  5572. .dynamic = 1,
  5573. .dpcm_capture = 1,
  5574. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5575. SND_SOC_DPCM_TRIGGER_POST},
  5576. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5577. .ignore_suspend = 1,
  5578. .codec_dai_name = "snd-soc-dummy-dai",
  5579. .codec_name = "snd-soc-dummy",
  5580. },
  5581. /* Hostless PCM purpose */
  5582. {
  5583. .name = "CDC_DMA Hostless",
  5584. .stream_name = "CDC_DMA Hostless",
  5585. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5586. .platform_name = "msm-pcm-hostless",
  5587. .dynamic = 1,
  5588. .dpcm_playback = 1,
  5589. .dpcm_capture = 1,
  5590. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5591. SND_SOC_DPCM_TRIGGER_POST},
  5592. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5593. .ignore_suspend = 1,
  5594. /* this dailink has playback support */
  5595. .ignore_pmdown_time = 1,
  5596. .codec_dai_name = "snd-soc-dummy-dai",
  5597. .codec_name = "snd-soc-dummy",
  5598. },
  5599. };
  5600. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5601. {
  5602. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5603. .stream_name = "WSA CDC DMA0 Capture",
  5604. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  5605. .platform_name = "msm-pcm-hostless",
  5606. .codec_name = "bolero_codec",
  5607. .codec_dai_name = "wsa_macro_vifeedback",
  5608. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5609. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5610. .ignore_suspend = 1,
  5611. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5612. .ops = &msm_cdc_dma_be_ops,
  5613. },
  5614. };
  5615. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5616. {
  5617. .name = MSM_DAILINK_NAME(ASM Loopback),
  5618. .stream_name = "MultiMedia6",
  5619. .cpu_dai_name = "MultiMedia6",
  5620. .platform_name = "msm-pcm-loopback",
  5621. .dynamic = 1,
  5622. .dpcm_playback = 1,
  5623. .dpcm_capture = 1,
  5624. .codec_dai_name = "snd-soc-dummy-dai",
  5625. .codec_name = "snd-soc-dummy",
  5626. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5627. SND_SOC_DPCM_TRIGGER_POST},
  5628. .ignore_suspend = 1,
  5629. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5630. .ignore_pmdown_time = 1,
  5631. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5632. },
  5633. {
  5634. .name = "USB Audio Hostless",
  5635. .stream_name = "USB Audio Hostless",
  5636. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5637. .platform_name = "msm-pcm-hostless",
  5638. .dynamic = 1,
  5639. .dpcm_playback = 1,
  5640. .dpcm_capture = 1,
  5641. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5642. SND_SOC_DPCM_TRIGGER_POST},
  5643. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5644. .ignore_suspend = 1,
  5645. .ignore_pmdown_time = 1,
  5646. .codec_dai_name = "snd-soc-dummy-dai",
  5647. .codec_name = "snd-soc-dummy",
  5648. },
  5649. {
  5650. .name = "SLIMBUS_7 Hostless",
  5651. .stream_name = "SLIMBUS_7 Hostless",
  5652. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5653. .platform_name = "msm-pcm-hostless",
  5654. .dynamic = 1,
  5655. .dpcm_capture = 1,
  5656. .dpcm_playback = 1,
  5657. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5658. SND_SOC_DPCM_TRIGGER_POST},
  5659. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5660. .ignore_suspend = 1,
  5661. .ignore_pmdown_time = 1,
  5662. .codec_dai_name = "snd-soc-dummy-dai",
  5663. .codec_name = "snd-soc-dummy",
  5664. },
  5665. {
  5666. .name = MSM_DAILINK_NAME(Compr Capture),
  5667. .stream_name = "Compr Capture",
  5668. .cpu_dai_name = "MultiMedia18",
  5669. .platform_name = "msm-compress-dsp",
  5670. .dynamic = 1,
  5671. .dpcm_capture = 1,
  5672. .codec_dai_name = "snd-soc-dummy-dai",
  5673. .codec_name = "snd-soc-dummy",
  5674. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5675. SND_SOC_DPCM_TRIGGER_POST},
  5676. .ignore_pmdown_time = 1,
  5677. .id = MSM_FRONTEND_DAI_MULTIMEDIA18,
  5678. },
  5679. };
  5680. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5681. /* Backend AFE DAI Links */
  5682. {
  5683. .name = LPASS_BE_AFE_PCM_RX,
  5684. .stream_name = "AFE Playback",
  5685. .cpu_dai_name = "msm-dai-q6-dev.224",
  5686. .platform_name = "msm-pcm-routing",
  5687. .codec_name = "msm-stub-codec.1",
  5688. .codec_dai_name = "msm-stub-rx",
  5689. .no_pcm = 1,
  5690. .dpcm_playback = 1,
  5691. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5692. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5693. /* this dainlink has playback support */
  5694. .ignore_pmdown_time = 1,
  5695. .ignore_suspend = 1,
  5696. },
  5697. {
  5698. .name = LPASS_BE_AFE_PCM_TX,
  5699. .stream_name = "AFE Capture",
  5700. .cpu_dai_name = "msm-dai-q6-dev.225",
  5701. .platform_name = "msm-pcm-routing",
  5702. .codec_name = "msm-stub-codec.1",
  5703. .codec_dai_name = "msm-stub-tx",
  5704. .no_pcm = 1,
  5705. .dpcm_capture = 1,
  5706. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5707. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5708. .ignore_suspend = 1,
  5709. },
  5710. /* Incall Record Uplink BACK END DAI Link */
  5711. {
  5712. .name = LPASS_BE_INCALL_RECORD_TX,
  5713. .stream_name = "Voice Uplink Capture",
  5714. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5715. .platform_name = "msm-pcm-routing",
  5716. .codec_name = "msm-stub-codec.1",
  5717. .codec_dai_name = "msm-stub-tx",
  5718. .no_pcm = 1,
  5719. .dpcm_capture = 1,
  5720. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5721. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5722. .ignore_suspend = 1,
  5723. },
  5724. /* Incall Record Downlink BACK END DAI Link */
  5725. {
  5726. .name = LPASS_BE_INCALL_RECORD_RX,
  5727. .stream_name = "Voice Downlink Capture",
  5728. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5729. .platform_name = "msm-pcm-routing",
  5730. .codec_name = "msm-stub-codec.1",
  5731. .codec_dai_name = "msm-stub-tx",
  5732. .no_pcm = 1,
  5733. .dpcm_capture = 1,
  5734. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5735. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5736. .ignore_suspend = 1,
  5737. },
  5738. /* Incall Music BACK END DAI Link */
  5739. {
  5740. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5741. .stream_name = "Voice Farend Playback",
  5742. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5743. .platform_name = "msm-pcm-routing",
  5744. .codec_name = "msm-stub-codec.1",
  5745. .codec_dai_name = "msm-stub-rx",
  5746. .no_pcm = 1,
  5747. .dpcm_playback = 1,
  5748. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5749. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5750. .ignore_suspend = 1,
  5751. .ignore_pmdown_time = 1,
  5752. },
  5753. /* Incall Music 2 BACK END DAI Link */
  5754. {
  5755. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5756. .stream_name = "Voice2 Farend Playback",
  5757. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5758. .platform_name = "msm-pcm-routing",
  5759. .codec_name = "msm-stub-codec.1",
  5760. .codec_dai_name = "msm-stub-rx",
  5761. .no_pcm = 1,
  5762. .dpcm_playback = 1,
  5763. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5764. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5765. .ignore_suspend = 1,
  5766. .ignore_pmdown_time = 1,
  5767. },
  5768. {
  5769. .name = LPASS_BE_USB_AUDIO_RX,
  5770. .stream_name = "USB Audio Playback",
  5771. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5772. .platform_name = "msm-pcm-routing",
  5773. .codec_name = "msm-stub-codec.1",
  5774. .codec_dai_name = "msm-stub-rx",
  5775. .no_pcm = 1,
  5776. .dpcm_playback = 1,
  5777. .id = MSM_BACKEND_DAI_USB_RX,
  5778. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5779. .ignore_pmdown_time = 1,
  5780. .ignore_suspend = 1,
  5781. },
  5782. {
  5783. .name = LPASS_BE_USB_AUDIO_TX,
  5784. .stream_name = "USB Audio Capture",
  5785. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5786. .platform_name = "msm-pcm-routing",
  5787. .codec_name = "msm-stub-codec.1",
  5788. .codec_dai_name = "msm-stub-tx",
  5789. .no_pcm = 1,
  5790. .dpcm_capture = 1,
  5791. .id = MSM_BACKEND_DAI_USB_TX,
  5792. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5793. .ignore_suspend = 1,
  5794. },
  5795. {
  5796. .name = LPASS_BE_PRI_TDM_RX_0,
  5797. .stream_name = "Primary TDM0 Playback",
  5798. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5799. .platform_name = "msm-pcm-routing",
  5800. .codec_name = "msm-stub-codec.1",
  5801. .codec_dai_name = "msm-stub-rx",
  5802. .no_pcm = 1,
  5803. .dpcm_playback = 1,
  5804. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5805. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5806. .ops = &qcs405_tdm_be_ops,
  5807. .ignore_suspend = 1,
  5808. .ignore_pmdown_time = 1,
  5809. },
  5810. {
  5811. .name = LPASS_BE_PRI_TDM_TX_0,
  5812. .stream_name = "Primary TDM0 Capture",
  5813. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5814. .platform_name = "msm-pcm-routing",
  5815. .codec_name = "msm-stub-codec.1",
  5816. .codec_dai_name = "msm-stub-tx",
  5817. .no_pcm = 1,
  5818. .dpcm_capture = 1,
  5819. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5820. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5821. .ops = &qcs405_tdm_be_ops,
  5822. .ignore_suspend = 1,
  5823. },
  5824. {
  5825. .name = LPASS_BE_SEC_TDM_RX_0,
  5826. .stream_name = "Secondary TDM0 Playback",
  5827. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5828. .platform_name = "msm-pcm-routing",
  5829. .codec_name = "msm-stub-codec.1",
  5830. .codec_dai_name = "msm-stub-rx",
  5831. .no_pcm = 1,
  5832. .dpcm_playback = 1,
  5833. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5834. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5835. .ops = &qcs405_tdm_be_ops,
  5836. .ignore_suspend = 1,
  5837. .ignore_pmdown_time = 1,
  5838. },
  5839. {
  5840. .name = LPASS_BE_SEC_TDM_TX_0,
  5841. .stream_name = "Secondary TDM0 Capture",
  5842. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5843. .platform_name = "msm-pcm-routing",
  5844. .codec_name = "msm-stub-codec.1",
  5845. .codec_dai_name = "msm-stub-tx",
  5846. .no_pcm = 1,
  5847. .dpcm_capture = 1,
  5848. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5849. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5850. .ops = &qcs405_tdm_be_ops,
  5851. .ignore_suspend = 1,
  5852. },
  5853. {
  5854. .name = LPASS_BE_TERT_TDM_RX_0,
  5855. .stream_name = "Tertiary TDM0 Playback",
  5856. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5857. .platform_name = "msm-pcm-routing",
  5858. .codec_name = "msm-stub-codec.1",
  5859. .codec_dai_name = "msm-stub-rx",
  5860. .no_pcm = 1,
  5861. .dpcm_playback = 1,
  5862. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5863. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5864. .ops = &qcs405_tdm_be_ops,
  5865. .ignore_suspend = 1,
  5866. .ignore_pmdown_time = 1,
  5867. },
  5868. {
  5869. .name = LPASS_BE_TERT_TDM_TX_0,
  5870. .stream_name = "Tertiary TDM0 Capture",
  5871. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5872. .platform_name = "msm-pcm-routing",
  5873. .codec_name = "msm-stub-codec.1",
  5874. .codec_dai_name = "msm-stub-tx",
  5875. .no_pcm = 1,
  5876. .dpcm_capture = 1,
  5877. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5878. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5879. .ops = &qcs405_tdm_be_ops,
  5880. .ignore_suspend = 1,
  5881. },
  5882. {
  5883. .name = LPASS_BE_QUAT_TDM_RX_0,
  5884. .stream_name = "Quaternary TDM0 Playback",
  5885. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5886. .platform_name = "msm-pcm-routing",
  5887. .codec_name = "msm-stub-codec.1",
  5888. .codec_dai_name = "msm-stub-rx",
  5889. .no_pcm = 1,
  5890. .dpcm_playback = 1,
  5891. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5892. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5893. .ops = &qcs405_tdm_be_ops,
  5894. .ignore_suspend = 1,
  5895. .ignore_pmdown_time = 1,
  5896. },
  5897. {
  5898. .name = LPASS_BE_QUAT_TDM_TX_0,
  5899. .stream_name = "Quaternary TDM0 Capture",
  5900. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5901. .platform_name = "msm-pcm-routing",
  5902. .codec_name = "msm-stub-codec.1",
  5903. .codec_dai_name = "msm-stub-tx",
  5904. .no_pcm = 1,
  5905. .dpcm_capture = 1,
  5906. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5907. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5908. .ops = &qcs405_tdm_be_ops,
  5909. .ignore_suspend = 1,
  5910. },
  5911. {
  5912. .name = LPASS_BE_QUIN_TDM_RX_0,
  5913. .stream_name = "Quinary TDM0 Playback",
  5914. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  5915. .platform_name = "msm-pcm-routing",
  5916. .codec_name = "msm-stub-codec.1",
  5917. .codec_dai_name = "msm-stub-rx",
  5918. .no_pcm = 1,
  5919. .dpcm_playback = 1,
  5920. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  5921. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5922. .ops = &qcs405_tdm_be_ops,
  5923. .ignore_suspend = 1,
  5924. .ignore_pmdown_time = 1,
  5925. },
  5926. {
  5927. .name = LPASS_BE_QUIN_TDM_TX_0,
  5928. .stream_name = "Quinary TDM0 Capture",
  5929. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  5930. .platform_name = "msm-pcm-routing",
  5931. .codec_name = "msm-stub-codec.1",
  5932. .codec_dai_name = "msm-stub-tx",
  5933. .no_pcm = 1,
  5934. .dpcm_capture = 1,
  5935. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  5936. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5937. .ops = &qcs405_tdm_be_ops,
  5938. .ignore_suspend = 1,
  5939. },
  5940. };
  5941. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  5942. {
  5943. .name = LPASS_BE_SLIMBUS_0_RX,
  5944. .stream_name = "Slimbus Playback",
  5945. .cpu_dai_name = "msm-dai-q6-dev.16384",
  5946. .platform_name = "msm-pcm-routing",
  5947. .codec_name = "tasha_codec",
  5948. .codec_dai_name = "tasha_mix_rx1",
  5949. .no_pcm = 1,
  5950. .dpcm_playback = 1,
  5951. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  5952. .init = &msm_audrx_init,
  5953. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5954. /* this dainlink has playback support */
  5955. .ignore_pmdown_time = 1,
  5956. .ignore_suspend = 1,
  5957. .ops = &msm_be_ops,
  5958. },
  5959. {
  5960. .name = LPASS_BE_SLIMBUS_0_TX,
  5961. .stream_name = "Slimbus Capture",
  5962. .cpu_dai_name = "msm-dai-q6-dev.16385",
  5963. .platform_name = "msm-pcm-routing",
  5964. .codec_name = "tasha_codec",
  5965. .codec_dai_name = "tasha_tx1",
  5966. .no_pcm = 1,
  5967. .dpcm_capture = 1,
  5968. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  5969. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5970. .ignore_suspend = 1,
  5971. .ops = &msm_be_ops,
  5972. },
  5973. {
  5974. .name = LPASS_BE_SLIMBUS_1_RX,
  5975. .stream_name = "Slimbus1 Playback",
  5976. .cpu_dai_name = "msm-dai-q6-dev.16386",
  5977. .platform_name = "msm-pcm-routing",
  5978. .codec_name = "tasha_codec",
  5979. .codec_dai_name = "tasha_mix_rx1",
  5980. .no_pcm = 1,
  5981. .dpcm_playback = 1,
  5982. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  5983. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5984. .ops = &msm_be_ops,
  5985. /* dai link has playback support */
  5986. .ignore_pmdown_time = 1,
  5987. .ignore_suspend = 1,
  5988. },
  5989. {
  5990. .name = LPASS_BE_SLIMBUS_1_TX,
  5991. .stream_name = "Slimbus1 Capture",
  5992. .cpu_dai_name = "msm-dai-q6-dev.16387",
  5993. .platform_name = "msm-pcm-routing",
  5994. .codec_name = "tasha_codec",
  5995. .codec_dai_name = "tasha_tx3",
  5996. .no_pcm = 1,
  5997. .dpcm_capture = 1,
  5998. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  5999. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6000. .ops = &msm_be_ops,
  6001. .ignore_suspend = 1,
  6002. },
  6003. {
  6004. .name = LPASS_BE_SLIMBUS_2_RX,
  6005. .stream_name = "Slimbus2 Playback",
  6006. .cpu_dai_name = "msm-dai-q6-dev.16388",
  6007. .platform_name = "msm-pcm-routing",
  6008. .codec_name = "tasha_codec",
  6009. .codec_dai_name = "tasha_rx2",
  6010. .no_pcm = 1,
  6011. .dpcm_playback = 1,
  6012. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  6013. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6014. .ops = &msm_be_ops,
  6015. .ignore_pmdown_time = 1,
  6016. .ignore_suspend = 1,
  6017. },
  6018. {
  6019. .name = LPASS_BE_SLIMBUS_3_RX,
  6020. .stream_name = "Slimbus3 Playback",
  6021. .cpu_dai_name = "msm-dai-q6-dev.16390",
  6022. .platform_name = "msm-pcm-routing",
  6023. .codec_name = "tasha_codec",
  6024. .codec_dai_name = "tasha_mix_rx1",
  6025. .no_pcm = 1,
  6026. .dpcm_playback = 1,
  6027. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  6028. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6029. .ops = &msm_be_ops,
  6030. /* dai link has playback support */
  6031. .ignore_pmdown_time = 1,
  6032. .ignore_suspend = 1,
  6033. },
  6034. {
  6035. .name = LPASS_BE_SLIMBUS_3_TX,
  6036. .stream_name = "Slimbus3 Capture",
  6037. .cpu_dai_name = "msm-dai-q6-dev.16391",
  6038. .platform_name = "msm-pcm-routing",
  6039. .codec_name = "tasha_codec",
  6040. .codec_dai_name = "tasha_tx1",
  6041. .no_pcm = 1,
  6042. .dpcm_capture = 1,
  6043. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  6044. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6045. .ops = &msm_be_ops,
  6046. .ignore_suspend = 1,
  6047. },
  6048. {
  6049. .name = LPASS_BE_SLIMBUS_4_RX,
  6050. .stream_name = "Slimbus4 Playback",
  6051. .cpu_dai_name = "msm-dai-q6-dev.16392",
  6052. .platform_name = "msm-pcm-routing",
  6053. .codec_name = "tasha_codec",
  6054. .codec_dai_name = "tasha_mix_rx1",
  6055. .no_pcm = 1,
  6056. .dpcm_playback = 1,
  6057. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  6058. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6059. .ops = &msm_be_ops,
  6060. /* dai link has playback support */
  6061. .ignore_pmdown_time = 1,
  6062. .ignore_suspend = 1,
  6063. },
  6064. {
  6065. .name = LPASS_BE_SLIMBUS_5_RX,
  6066. .stream_name = "Slimbus5 Playback",
  6067. .cpu_dai_name = "msm-dai-q6-dev.16394",
  6068. .platform_name = "msm-pcm-routing",
  6069. .codec_name = "tasha_codec",
  6070. .codec_dai_name = "tasha_rx3",
  6071. .no_pcm = 1,
  6072. .dpcm_playback = 1,
  6073. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  6074. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6075. .ops = &msm_be_ops,
  6076. /* dai link has playback support */
  6077. .ignore_pmdown_time = 1,
  6078. .ignore_suspend = 1,
  6079. },
  6080. {
  6081. .name = LPASS_BE_SLIMBUS_6_RX,
  6082. .stream_name = "Slimbus6 Playback",
  6083. .cpu_dai_name = "msm-dai-q6-dev.16396",
  6084. .platform_name = "msm-pcm-routing",
  6085. .codec_name = "tasha_codec",
  6086. .codec_dai_name = "tasha_rx4",
  6087. .no_pcm = 1,
  6088. .dpcm_playback = 1,
  6089. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  6090. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6091. .ops = &msm_be_ops,
  6092. /* dai link has playback support */
  6093. .ignore_pmdown_time = 1,
  6094. .ignore_suspend = 1,
  6095. },
  6096. /* Slimbus VI Recording */
  6097. {
  6098. .name = LPASS_BE_SLIMBUS_TX_VI,
  6099. .stream_name = "Slimbus4 Capture",
  6100. .cpu_dai_name = "msm-dai-q6-dev.16393",
  6101. .platform_name = "msm-pcm-routing",
  6102. .codec_name = "tasha_codec",
  6103. .codec_dai_name = "tasha_vifeedback",
  6104. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  6105. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6106. .ops = &msm_be_ops,
  6107. .ignore_suspend = 1,
  6108. .no_pcm = 1,
  6109. .dpcm_capture = 1,
  6110. .ignore_pmdown_time = 1,
  6111. },
  6112. };
  6113. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  6114. {
  6115. .name = LPASS_BE_SLIMBUS_7_RX,
  6116. .stream_name = "Slimbus7 Playback",
  6117. .cpu_dai_name = "msm-dai-q6-dev.16398",
  6118. .platform_name = "msm-pcm-routing",
  6119. .codec_name = "btfmslim_slave",
  6120. /* BT codec driver determines capabilities based on
  6121. * dai name, bt codecdai name should always contains
  6122. * supported usecase information
  6123. */
  6124. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  6125. .no_pcm = 1,
  6126. .dpcm_playback = 1,
  6127. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  6128. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6129. .ops = &msm_wcn_ops,
  6130. /* dai link has playback support */
  6131. .ignore_pmdown_time = 1,
  6132. .ignore_suspend = 1,
  6133. },
  6134. {
  6135. .name = LPASS_BE_SLIMBUS_7_TX,
  6136. .stream_name = "Slimbus7 Capture",
  6137. .cpu_dai_name = "msm-dai-q6-dev.16399",
  6138. .platform_name = "msm-pcm-routing",
  6139. .codec_name = "btfmslim_slave",
  6140. .codec_dai_name = "btfm_bt_sco_slim_tx",
  6141. .no_pcm = 1,
  6142. .dpcm_capture = 1,
  6143. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  6144. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6145. .ops = &msm_wcn_ops,
  6146. .ignore_suspend = 1,
  6147. },
  6148. {
  6149. .name = LPASS_BE_SLIMBUS_8_TX,
  6150. .stream_name = "Slimbus8 Capture",
  6151. .cpu_dai_name = "msm-dai-q6-dev.16401",
  6152. .platform_name = "msm-pcm-routing",
  6153. .codec_name = "btfmslim_slave",
  6154. .codec_dai_name = "btfm_fm_slim_tx",
  6155. .no_pcm = 1,
  6156. .dpcm_capture = 1,
  6157. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  6158. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6159. .init = &msm_wcn_init,
  6160. .ops = &msm_wcn_ops,
  6161. .ignore_suspend = 1,
  6162. },
  6163. };
  6164. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  6165. {
  6166. .name = LPASS_BE_PRI_MI2S_RX,
  6167. .stream_name = "Primary MI2S Playback",
  6168. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6169. .platform_name = "msm-pcm-routing",
  6170. .codec_name = "msm-stub-codec.1",
  6171. .codec_dai_name = "msm-stub-rx",
  6172. .no_pcm = 1,
  6173. .dpcm_playback = 1,
  6174. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  6175. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6176. .ops = &msm_mi2s_be_ops,
  6177. .ignore_suspend = 1,
  6178. .ignore_pmdown_time = 1,
  6179. },
  6180. {
  6181. .name = LPASS_BE_PRI_MI2S_TX,
  6182. .stream_name = "Primary MI2S Capture",
  6183. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6184. .platform_name = "msm-pcm-routing",
  6185. .codec_name = "msm-stub-codec.1",
  6186. .codec_dai_name = "msm-stub-tx",
  6187. .no_pcm = 1,
  6188. .dpcm_capture = 1,
  6189. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  6190. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6191. .ops = &msm_mi2s_be_ops,
  6192. .ignore_suspend = 1,
  6193. },
  6194. {
  6195. .name = LPASS_BE_SEC_MI2S_RX,
  6196. .stream_name = "Secondary MI2S Playback",
  6197. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6198. .platform_name = "msm-pcm-routing",
  6199. .codec_name = "msm-stub-codec.1",
  6200. .codec_dai_name = "msm-stub-rx",
  6201. .no_pcm = 1,
  6202. .dpcm_playback = 1,
  6203. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  6204. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6205. .ops = &msm_mi2s_be_ops,
  6206. .ignore_suspend = 1,
  6207. .ignore_pmdown_time = 1,
  6208. },
  6209. {
  6210. .name = LPASS_BE_SEC_MI2S_TX,
  6211. .stream_name = "Secondary MI2S Capture",
  6212. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6213. .platform_name = "msm-pcm-routing",
  6214. .codec_name = "msm-stub-codec.1",
  6215. .codec_dai_name = "msm-stub-tx",
  6216. .no_pcm = 1,
  6217. .dpcm_capture = 1,
  6218. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  6219. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6220. .ops = &msm_mi2s_be_ops,
  6221. .ignore_suspend = 1,
  6222. },
  6223. {
  6224. .name = LPASS_BE_TERT_MI2S_RX,
  6225. .stream_name = "Tertiary MI2S Playback",
  6226. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6227. .platform_name = "msm-pcm-routing",
  6228. .codec_name = "msm-stub-codec.1",
  6229. .codec_dai_name = "msm-stub-rx",
  6230. .no_pcm = 1,
  6231. .dpcm_playback = 1,
  6232. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  6233. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6234. .ops = &msm_mi2s_be_ops,
  6235. .ignore_suspend = 1,
  6236. .ignore_pmdown_time = 1,
  6237. },
  6238. {
  6239. .name = LPASS_BE_TERT_MI2S_TX,
  6240. .stream_name = "Tertiary MI2S Capture",
  6241. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6242. .platform_name = "msm-pcm-routing",
  6243. .codec_name = "msm-stub-codec.1",
  6244. .codec_dai_name = "msm-stub-tx",
  6245. .no_pcm = 1,
  6246. .dpcm_capture = 1,
  6247. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  6248. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6249. .ops = &msm_mi2s_be_ops,
  6250. .ignore_suspend = 1,
  6251. },
  6252. {
  6253. .name = LPASS_BE_QUAT_MI2S_RX,
  6254. .stream_name = "Quaternary MI2S Playback",
  6255. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6256. .platform_name = "msm-pcm-routing",
  6257. .codec_name = "msm-stub-codec.1",
  6258. .codec_dai_name = "msm-stub-rx",
  6259. .no_pcm = 1,
  6260. .dpcm_playback = 1,
  6261. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  6262. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6263. .ops = &msm_mi2s_be_ops,
  6264. .ignore_suspend = 1,
  6265. .ignore_pmdown_time = 1,
  6266. },
  6267. {
  6268. .name = LPASS_BE_QUAT_MI2S_TX,
  6269. .stream_name = "Quaternary MI2S Capture",
  6270. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6271. .platform_name = "msm-pcm-routing",
  6272. .codec_name = "msm-stub-codec.1",
  6273. .codec_dai_name = "msm-stub-tx",
  6274. .no_pcm = 1,
  6275. .dpcm_capture = 1,
  6276. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  6277. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6278. .ops = &msm_mi2s_be_ops,
  6279. .ignore_suspend = 1,
  6280. },
  6281. {
  6282. .name = LPASS_BE_QUIN_MI2S_RX,
  6283. .stream_name = "Quinary MI2S Playback",
  6284. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6285. .platform_name = "msm-pcm-routing",
  6286. .codec_name = "msm-stub-codec.1",
  6287. .codec_dai_name = "msm-stub-rx",
  6288. .no_pcm = 1,
  6289. .dpcm_playback = 1,
  6290. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  6291. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6292. .ops = &msm_mi2s_be_ops,
  6293. .ignore_suspend = 1,
  6294. .ignore_pmdown_time = 1,
  6295. },
  6296. {
  6297. .name = LPASS_BE_QUIN_MI2S_TX,
  6298. .stream_name = "Quinary MI2S Capture",
  6299. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6300. .platform_name = "msm-pcm-routing",
  6301. .codec_name = "msm-stub-codec.1",
  6302. .codec_dai_name = "msm-stub-tx",
  6303. .no_pcm = 1,
  6304. .dpcm_capture = 1,
  6305. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  6306. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6307. .ops = &msm_mi2s_be_ops,
  6308. .ignore_suspend = 1,
  6309. },
  6310. };
  6311. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  6312. /* Primary AUX PCM Backend DAI Links */
  6313. {
  6314. .name = LPASS_BE_AUXPCM_RX,
  6315. .stream_name = "AUX PCM Playback",
  6316. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6317. .platform_name = "msm-pcm-routing",
  6318. .codec_name = "msm-stub-codec.1",
  6319. .codec_dai_name = "msm-stub-rx",
  6320. .no_pcm = 1,
  6321. .dpcm_playback = 1,
  6322. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6323. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6324. .ignore_pmdown_time = 1,
  6325. .ignore_suspend = 1,
  6326. },
  6327. {
  6328. .name = LPASS_BE_AUXPCM_TX,
  6329. .stream_name = "AUX PCM Capture",
  6330. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6331. .platform_name = "msm-pcm-routing",
  6332. .codec_name = "msm-stub-codec.1",
  6333. .codec_dai_name = "msm-stub-tx",
  6334. .no_pcm = 1,
  6335. .dpcm_capture = 1,
  6336. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6337. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6338. .ignore_suspend = 1,
  6339. },
  6340. /* Secondary AUX PCM Backend DAI Links */
  6341. {
  6342. .name = LPASS_BE_SEC_AUXPCM_RX,
  6343. .stream_name = "Sec AUX PCM Playback",
  6344. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6345. .platform_name = "msm-pcm-routing",
  6346. .codec_name = "msm-stub-codec.1",
  6347. .codec_dai_name = "msm-stub-rx",
  6348. .no_pcm = 1,
  6349. .dpcm_playback = 1,
  6350. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  6351. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6352. .ignore_pmdown_time = 1,
  6353. .ignore_suspend = 1,
  6354. },
  6355. {
  6356. .name = LPASS_BE_SEC_AUXPCM_TX,
  6357. .stream_name = "Sec AUX PCM Capture",
  6358. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6359. .platform_name = "msm-pcm-routing",
  6360. .codec_name = "msm-stub-codec.1",
  6361. .codec_dai_name = "msm-stub-tx",
  6362. .no_pcm = 1,
  6363. .dpcm_capture = 1,
  6364. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  6365. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6366. .ignore_suspend = 1,
  6367. },
  6368. /* Tertiary AUX PCM Backend DAI Links */
  6369. {
  6370. .name = LPASS_BE_TERT_AUXPCM_RX,
  6371. .stream_name = "Tert AUX PCM Playback",
  6372. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6373. .platform_name = "msm-pcm-routing",
  6374. .codec_name = "msm-stub-codec.1",
  6375. .codec_dai_name = "msm-stub-rx",
  6376. .no_pcm = 1,
  6377. .dpcm_playback = 1,
  6378. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  6379. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6380. .ignore_suspend = 1,
  6381. },
  6382. {
  6383. .name = LPASS_BE_TERT_AUXPCM_TX,
  6384. .stream_name = "Tert AUX PCM Capture",
  6385. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6386. .platform_name = "msm-pcm-routing",
  6387. .codec_name = "msm-stub-codec.1",
  6388. .codec_dai_name = "msm-stub-tx",
  6389. .no_pcm = 1,
  6390. .dpcm_capture = 1,
  6391. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  6392. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6393. .ignore_suspend = 1,
  6394. },
  6395. /* Quaternary AUX PCM Backend DAI Links */
  6396. {
  6397. .name = LPASS_BE_QUAT_AUXPCM_RX,
  6398. .stream_name = "Quat AUX PCM Playback",
  6399. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6400. .platform_name = "msm-pcm-routing",
  6401. .codec_name = "msm-stub-codec.1",
  6402. .codec_dai_name = "msm-stub-rx",
  6403. .no_pcm = 1,
  6404. .dpcm_playback = 1,
  6405. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  6406. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6407. .ignore_pmdown_time = 1,
  6408. .ignore_suspend = 1,
  6409. },
  6410. {
  6411. .name = LPASS_BE_QUAT_AUXPCM_TX,
  6412. .stream_name = "Quat AUX PCM Capture",
  6413. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6414. .platform_name = "msm-pcm-routing",
  6415. .codec_name = "msm-stub-codec.1",
  6416. .codec_dai_name = "msm-stub-tx",
  6417. .no_pcm = 1,
  6418. .dpcm_capture = 1,
  6419. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  6420. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6421. .ignore_suspend = 1,
  6422. },
  6423. /* Quinary AUX PCM Backend DAI Links */
  6424. {
  6425. .name = LPASS_BE_QUIN_AUXPCM_RX,
  6426. .stream_name = "Quin AUX PCM Playback",
  6427. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6428. .platform_name = "msm-pcm-routing",
  6429. .codec_name = "msm-stub-codec.1",
  6430. .codec_dai_name = "msm-stub-rx",
  6431. .no_pcm = 1,
  6432. .dpcm_playback = 1,
  6433. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  6434. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6435. .ignore_pmdown_time = 1,
  6436. .ignore_suspend = 1,
  6437. },
  6438. {
  6439. .name = LPASS_BE_QUIN_AUXPCM_TX,
  6440. .stream_name = "Quin AUX PCM Capture",
  6441. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6442. .platform_name = "msm-pcm-routing",
  6443. .codec_name = "msm-stub-codec.1",
  6444. .codec_dai_name = "msm-stub-tx",
  6445. .no_pcm = 1,
  6446. .dpcm_capture = 1,
  6447. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  6448. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6449. .ignore_suspend = 1,
  6450. },
  6451. };
  6452. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  6453. /* WSA CDC DMA Backend DAI Links */
  6454. {
  6455. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  6456. .stream_name = "WSA CDC DMA0 Playback",
  6457. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  6458. .platform_name = "msm-pcm-routing",
  6459. .codec_name = "bolero_codec",
  6460. .codec_dai_name = "wsa_macro_rx1",
  6461. .no_pcm = 1,
  6462. .dpcm_playback = 1,
  6463. .init = &msm_wsa_cdc_dma_init,
  6464. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  6465. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6466. .ignore_pmdown_time = 1,
  6467. .ignore_suspend = 1,
  6468. .ops = &msm_cdc_dma_be_ops,
  6469. },
  6470. {
  6471. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  6472. .stream_name = "WSA CDC DMA1 Playback",
  6473. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  6474. .platform_name = "msm-pcm-routing",
  6475. .codec_name = "bolero_codec",
  6476. .codec_dai_name = "wsa_macro_rx_mix",
  6477. .no_pcm = 1,
  6478. .dpcm_playback = 1,
  6479. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  6480. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6481. .ignore_pmdown_time = 1,
  6482. .ignore_suspend = 1,
  6483. .ops = &msm_cdc_dma_be_ops,
  6484. },
  6485. {
  6486. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  6487. .stream_name = "WSA CDC DMA1 Capture",
  6488. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  6489. .platform_name = "msm-pcm-routing",
  6490. .codec_name = "bolero_codec",
  6491. .codec_dai_name = "wsa_macro_echo",
  6492. .no_pcm = 1,
  6493. .dpcm_capture = 1,
  6494. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  6495. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6496. .ignore_suspend = 1,
  6497. .ops = &msm_cdc_dma_be_ops,
  6498. },
  6499. };
  6500. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6501. {
  6502. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6503. .stream_name = "VA CDC DMA0 Capture",
  6504. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6505. .platform_name = "msm-pcm-routing",
  6506. .codec_name = "bolero_codec",
  6507. .codec_dai_name = "va_macro_tx1",
  6508. .no_pcm = 1,
  6509. .dpcm_capture = 1,
  6510. .init = &msm_va_cdc_dma_init,
  6511. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6512. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6513. .ignore_suspend = 1,
  6514. .ops = &msm_cdc_dma_be_ops,
  6515. },
  6516. {
  6517. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6518. .stream_name = "VA CDC DMA1 Capture",
  6519. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6520. .platform_name = "msm-pcm-routing",
  6521. .codec_name = "bolero_codec",
  6522. .codec_dai_name = "va_macro_tx2",
  6523. .no_pcm = 1,
  6524. .dpcm_capture = 1,
  6525. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6526. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6527. .ignore_suspend = 1,
  6528. .ops = &msm_cdc_dma_be_ops,
  6529. },
  6530. };
  6531. static struct snd_soc_dai_link msm_spdif_be_dai_links[] = {
  6532. {
  6533. .name = LPASS_BE_PRI_SPDIF_RX,
  6534. .stream_name = "Primary SPDIF Playback",
  6535. .cpu_dai_name = "msm-dai-q6-spdif.20480",
  6536. .platform_name = "msm-pcm-routing",
  6537. .codec_name = "msm-stub-codec.1",
  6538. .codec_dai_name = "msm-stub-rx",
  6539. .no_pcm = 1,
  6540. .dpcm_playback = 1,
  6541. .id = MSM_BACKEND_DAI_PRI_SPDIF_RX,
  6542. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6543. .ops = &msm_spdif_be_ops,
  6544. .ignore_suspend = 1,
  6545. .ignore_pmdown_time = 1,
  6546. },
  6547. {
  6548. .name = LPASS_BE_PRI_SPDIF_TX,
  6549. .stream_name = "Primary SPDIF Capture",
  6550. .cpu_dai_name = "msm-dai-q6-spdif.20481",
  6551. .platform_name = "msm-pcm-routing",
  6552. .codec_name = "msm-stub-codec.1",
  6553. .codec_dai_name = "msm-stub-tx",
  6554. .no_pcm = 1,
  6555. .dpcm_capture = 1,
  6556. .id = MSM_BACKEND_DAI_PRI_SPDIF_TX,
  6557. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6558. .ops = &msm_spdif_be_ops,
  6559. .ignore_suspend = 1,
  6560. },
  6561. {
  6562. .name = LPASS_BE_SEC_SPDIF_RX,
  6563. .stream_name = "Secondary SPDIF Playback",
  6564. .cpu_dai_name = "msm-dai-q6-spdif.20482",
  6565. .platform_name = "msm-pcm-routing",
  6566. .codec_name = "msm-stub-codec.1",
  6567. .codec_dai_name = "msm-stub-rx",
  6568. .no_pcm = 1,
  6569. .dpcm_playback = 1,
  6570. .id = MSM_BACKEND_DAI_SEC_SPDIF_RX,
  6571. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6572. .ops = &msm_spdif_be_ops,
  6573. .ignore_suspend = 1,
  6574. .ignore_pmdown_time = 1,
  6575. },
  6576. {
  6577. .name = LPASS_BE_SEC_SPDIF_TX,
  6578. .stream_name = "Secondary SPDIF Capture",
  6579. .cpu_dai_name = "msm-dai-q6-spdif.20483",
  6580. .platform_name = "msm-pcm-routing",
  6581. .codec_name = "msm-stub-codec.1",
  6582. .codec_dai_name = "msm-stub-tx",
  6583. .no_pcm = 1,
  6584. .dpcm_capture = 1,
  6585. .id = MSM_BACKEND_DAI_SEC_SPDIF_TX,
  6586. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6587. .ops = &msm_spdif_be_ops,
  6588. .ignore_suspend = 1,
  6589. },
  6590. };
  6591. static struct snd_soc_dai_link msm_qcs405_dai_links[
  6592. ARRAY_SIZE(msm_common_dai_links) +
  6593. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6594. ARRAY_SIZE(msm_common_be_dai_links) +
  6595. ARRAY_SIZE(msm_tasha_be_dai_links) +
  6596. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6597. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6598. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6599. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6600. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  6601. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  6602. ARRAY_SIZE(msm_spdif_be_dai_links)];
  6603. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  6604. {
  6605. int ret = 0;
  6606. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  6607. &service_nb);
  6608. if (ret < 0)
  6609. pr_err("%s: Audio notifier register failed ret = %d\n",
  6610. __func__, ret);
  6611. return ret;
  6612. }
  6613. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  6614. struct snd_ctl_elem_value *ucontrol)
  6615. {
  6616. int ret = 0;
  6617. int port_id;
  6618. uint32_t vad_enable = ucontrol->value.integer.value[0];
  6619. uint32_t preroll_config = ucontrol->value.integer.value[1];
  6620. uint32_t vad_intf = ucontrol->value.integer.value[2];
  6621. if ((preroll_config < 0) || (preroll_config > 1000) ||
  6622. (vad_enable < 0) || (vad_enable > 1) ||
  6623. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  6624. pr_err("%s: Invalid arguments\n", __func__);
  6625. ret = -EINVAL;
  6626. goto done;
  6627. }
  6628. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  6629. vad_enable, preroll_config, vad_intf);
  6630. ret = msm_vad_get_portid_from_beid(vad_intf, &port_id);
  6631. if (ret) {
  6632. pr_err("%s: Invalid vad interface\n", __func__);
  6633. goto done;
  6634. }
  6635. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  6636. done:
  6637. return ret;
  6638. }
  6639. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  6640. {
  6641. int ret = 0;
  6642. uint32_t tasha_codec = 0;
  6643. ret = afe_cal_init_hwdep(card);
  6644. if (ret) {
  6645. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  6646. ret = 0;
  6647. }
  6648. /* tasha late probe when it is present */
  6649. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  6650. &tasha_codec);
  6651. if (ret) {
  6652. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  6653. ret = 0;
  6654. } else {
  6655. if (tasha_codec) {
  6656. ret = msm_snd_card_tasha_late_probe(card);
  6657. if (ret)
  6658. dev_err(card->dev, "%s: tasha late probe err\n",
  6659. __func__);
  6660. }
  6661. }
  6662. return ret;
  6663. }
  6664. struct snd_soc_card snd_soc_card_qcs405_msm = {
  6665. .name = "qcs405-snd-card",
  6666. .controls = msm_snd_controls,
  6667. .num_controls = ARRAY_SIZE(msm_snd_controls),
  6668. .late_probe = msm_snd_card_codec_late_probe,
  6669. };
  6670. static int msm_populate_dai_link_component_of_node(
  6671. struct snd_soc_card *card)
  6672. {
  6673. int i, index, ret = 0;
  6674. struct device *cdev = card->dev;
  6675. struct snd_soc_dai_link *dai_link = card->dai_link;
  6676. struct device_node *np;
  6677. if (!cdev) {
  6678. pr_err("%s: Sound card device memory NULL\n", __func__);
  6679. return -ENODEV;
  6680. }
  6681. for (i = 0; i < card->num_links; i++) {
  6682. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6683. continue;
  6684. /* populate platform_of_node for snd card dai links */
  6685. if (dai_link[i].platform_name &&
  6686. !dai_link[i].platform_of_node) {
  6687. index = of_property_match_string(cdev->of_node,
  6688. "asoc-platform-names",
  6689. dai_link[i].platform_name);
  6690. if (index < 0) {
  6691. pr_err("%s: No match found for platform name: %s\n",
  6692. __func__, dai_link[i].platform_name);
  6693. ret = index;
  6694. goto err;
  6695. }
  6696. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6697. index);
  6698. if (!np) {
  6699. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  6700. __func__, dai_link[i].platform_name,
  6701. index);
  6702. ret = -ENODEV;
  6703. goto err;
  6704. }
  6705. dai_link[i].platform_of_node = np;
  6706. dai_link[i].platform_name = NULL;
  6707. }
  6708. /* populate cpu_of_node for snd card dai links */
  6709. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6710. index = of_property_match_string(cdev->of_node,
  6711. "asoc-cpu-names",
  6712. dai_link[i].cpu_dai_name);
  6713. if (index >= 0) {
  6714. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6715. index);
  6716. if (!np) {
  6717. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  6718. __func__,
  6719. dai_link[i].cpu_dai_name);
  6720. ret = -ENODEV;
  6721. goto err;
  6722. }
  6723. dai_link[i].cpu_of_node = np;
  6724. dai_link[i].cpu_dai_name = NULL;
  6725. }
  6726. }
  6727. /* populate codec_of_node for snd card dai links */
  6728. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6729. index = of_property_match_string(cdev->of_node,
  6730. "asoc-codec-names",
  6731. dai_link[i].codec_name);
  6732. if (index < 0)
  6733. continue;
  6734. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6735. index);
  6736. if (!np) {
  6737. pr_err("%s: retrieving phandle for codec %s failed\n",
  6738. __func__, dai_link[i].codec_name);
  6739. ret = -ENODEV;
  6740. goto err;
  6741. }
  6742. dai_link[i].codec_of_node = np;
  6743. dai_link[i].codec_name = NULL;
  6744. }
  6745. }
  6746. err:
  6747. return ret;
  6748. }
  6749. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6750. /* FrontEnd DAI Links */
  6751. {
  6752. .name = "MSMSTUB Media1",
  6753. .stream_name = "MultiMedia1",
  6754. .cpu_dai_name = "MultiMedia1",
  6755. .platform_name = "msm-pcm-dsp.0",
  6756. .dynamic = 1,
  6757. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6758. .dpcm_playback = 1,
  6759. .dpcm_capture = 1,
  6760. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6761. SND_SOC_DPCM_TRIGGER_POST},
  6762. .codec_dai_name = "snd-soc-dummy-dai",
  6763. .codec_name = "snd-soc-dummy",
  6764. .ignore_suspend = 1,
  6765. /* this dainlink has playback support */
  6766. .ignore_pmdown_time = 1,
  6767. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6768. },
  6769. };
  6770. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6771. /* Backend DAI Links */
  6772. {
  6773. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6774. .stream_name = "VA CDC DMA0 Capture",
  6775. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6776. .platform_name = "msm-pcm-routing",
  6777. .codec_name = "bolero_codec",
  6778. .codec_dai_name = "va_macro_tx1",
  6779. .no_pcm = 1,
  6780. .dpcm_capture = 1,
  6781. .init = &msm_va_cdc_dma_init,
  6782. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6783. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6784. .ignore_suspend = 1,
  6785. .ops = &msm_cdc_dma_be_ops,
  6786. },
  6787. {
  6788. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6789. .stream_name = "VA CDC DMA1 Capture",
  6790. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6791. .platform_name = "msm-pcm-routing",
  6792. .codec_name = "bolero_codec",
  6793. .codec_dai_name = "va_macro_tx2",
  6794. .no_pcm = 1,
  6795. .dpcm_capture = 1,
  6796. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6797. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6798. .ignore_suspend = 1,
  6799. .ops = &msm_cdc_dma_be_ops,
  6800. },
  6801. };
  6802. static struct snd_soc_dai_link msm_stub_dai_links[
  6803. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6804. ARRAY_SIZE(msm_stub_be_dai_links)];
  6805. struct snd_soc_card snd_soc_card_stub_msm = {
  6806. .name = "qcs405-stub-snd-card",
  6807. };
  6808. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  6809. { .compatible = "qcom,qcs405-asoc-snd",
  6810. .data = "codec"},
  6811. { .compatible = "qcom,qcs405-asoc-snd-stub",
  6812. .data = "stub_codec"},
  6813. {},
  6814. };
  6815. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6816. {
  6817. struct snd_soc_card *card = NULL;
  6818. struct snd_soc_dai_link *dailink;
  6819. int total_links = 0;
  6820. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  6821. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  6822. uint32_t spdif_audio_intf = 0;
  6823. const struct of_device_id *match;
  6824. char __iomem *spdif_cfg, *spdif_pin_ctl;
  6825. int rc = 0;
  6826. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  6827. if (!match) {
  6828. dev_err(dev, "%s: No DT match found for sound card\n",
  6829. __func__);
  6830. return NULL;
  6831. }
  6832. if (!strcmp(match->data, "codec")) {
  6833. card = &snd_soc_card_qcs405_msm;
  6834. memcpy(msm_qcs405_dai_links + total_links,
  6835. msm_common_dai_links,
  6836. sizeof(msm_common_dai_links));
  6837. total_links += ARRAY_SIZE(msm_common_dai_links);
  6838. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  6839. &wsa_bolero_codec);
  6840. if (rc) {
  6841. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  6842. __func__);
  6843. } else {
  6844. if (wsa_bolero_codec) {
  6845. dev_dbg(dev, "%s(): WSA macro in bolero codec present\n",
  6846. __func__);
  6847. memcpy(msm_qcs405_dai_links + total_links,
  6848. msm_bolero_fe_dai_links,
  6849. sizeof(msm_bolero_fe_dai_links));
  6850. total_links +=
  6851. ARRAY_SIZE(msm_bolero_fe_dai_links);
  6852. }
  6853. }
  6854. memcpy(msm_qcs405_dai_links + total_links,
  6855. msm_common_misc_fe_dai_links,
  6856. sizeof(msm_common_misc_fe_dai_links));
  6857. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6858. memcpy(msm_qcs405_dai_links + total_links,
  6859. msm_common_be_dai_links,
  6860. sizeof(msm_common_be_dai_links));
  6861. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6862. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  6863. &tasha_codec);
  6864. if (rc) {
  6865. dev_dbg(dev, "%s: No DT match tasha codec\n",
  6866. __func__);
  6867. } else {
  6868. if (tasha_codec) {
  6869. memcpy(msm_qcs405_dai_links + total_links,
  6870. msm_tasha_be_dai_links,
  6871. sizeof(msm_tasha_be_dai_links));
  6872. total_links +=
  6873. ARRAY_SIZE(msm_tasha_be_dai_links);
  6874. }
  6875. }
  6876. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  6877. &va_bolero_codec);
  6878. if (rc) {
  6879. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  6880. __func__);
  6881. } else {
  6882. if (va_bolero_codec) {
  6883. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  6884. __func__);
  6885. memcpy(msm_qcs405_dai_links + total_links,
  6886. msm_va_cdc_dma_be_dai_links,
  6887. sizeof(msm_va_cdc_dma_be_dai_links));
  6888. total_links +=
  6889. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6890. }
  6891. }
  6892. if (wsa_bolero_codec) {
  6893. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  6894. __func__);
  6895. memcpy(msm_qcs405_dai_links + total_links,
  6896. msm_wsa_cdc_dma_be_dai_links,
  6897. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6898. total_links +=
  6899. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6900. }
  6901. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6902. &mi2s_audio_intf);
  6903. if (rc) {
  6904. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6905. __func__);
  6906. } else {
  6907. if (mi2s_audio_intf) {
  6908. memcpy(msm_qcs405_dai_links + total_links,
  6909. msm_mi2s_be_dai_links,
  6910. sizeof(msm_mi2s_be_dai_links));
  6911. total_links +=
  6912. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6913. }
  6914. }
  6915. rc = of_property_read_u32(dev->of_node,
  6916. "qcom,auxpcm-audio-intf",
  6917. &auxpcm_audio_intf);
  6918. if (rc) {
  6919. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6920. __func__);
  6921. } else {
  6922. if (auxpcm_audio_intf) {
  6923. memcpy(msm_qcs405_dai_links + total_links,
  6924. msm_auxpcm_be_dai_links,
  6925. sizeof(msm_auxpcm_be_dai_links));
  6926. total_links +=
  6927. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6928. }
  6929. }
  6930. rc = of_property_read_u32(dev->of_node, "qcom,spdif-audio-intf",
  6931. &spdif_audio_intf);
  6932. if (rc) {
  6933. dev_dbg(dev, "%s: No DT match SPDIF audio interface\n",
  6934. __func__);
  6935. } else {
  6936. if (spdif_audio_intf) {
  6937. memcpy(msm_qcs405_dai_links + total_links,
  6938. msm_spdif_be_dai_links,
  6939. sizeof(msm_spdif_be_dai_links));
  6940. total_links +=
  6941. ARRAY_SIZE(msm_spdif_be_dai_links);
  6942. /* enable spdif coax pins */
  6943. spdif_cfg = ioremap(TLMM_EAST_SPARE, 0x4);
  6944. spdif_pin_ctl =
  6945. ioremap(TLMM_SPDIF_HDMI_ARC_CTL, 0x4);
  6946. iowrite32(0xc0, spdif_cfg);
  6947. iowrite32(0x2220, spdif_pin_ctl);
  6948. }
  6949. }
  6950. dailink = msm_qcs405_dai_links;
  6951. } else if (!strcmp(match->data, "stub_codec")) {
  6952. card = &snd_soc_card_stub_msm;
  6953. memcpy(msm_stub_dai_links + total_links,
  6954. msm_stub_fe_dai_links,
  6955. sizeof(msm_stub_fe_dai_links));
  6956. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  6957. memcpy(msm_stub_dai_links + total_links,
  6958. msm_stub_be_dai_links,
  6959. sizeof(msm_stub_be_dai_links));
  6960. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  6961. dailink = msm_stub_dai_links;
  6962. }
  6963. if (card) {
  6964. card->dai_link = dailink;
  6965. card->num_links = total_links;
  6966. }
  6967. return card;
  6968. }
  6969. static int msm_wsa881x_init(struct snd_soc_component *component)
  6970. {
  6971. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6972. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6973. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  6974. SPKR_L_BOOST, SPKR_L_VI};
  6975. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  6976. SPKR_R_BOOST, SPKR_R_VI};
  6977. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  6978. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  6979. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  6980. struct msm_asoc_mach_data *pdata;
  6981. struct snd_soc_dapm_context *dapm;
  6982. int ret = 0;
  6983. if (!codec) {
  6984. pr_err("%s codec is NULL\n", __func__);
  6985. return -EINVAL;
  6986. }
  6987. dapm = snd_soc_codec_get_dapm(codec);
  6988. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  6989. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  6990. __func__, codec->component.name);
  6991. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  6992. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6993. &ch_rate[0], &spkleft_port_types[0]);
  6994. if (dapm->component) {
  6995. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  6996. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  6997. }
  6998. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  6999. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  7000. __func__, codec->component.name);
  7001. wsa881x_set_channel_map(codec, &spkright_ports[0],
  7002. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7003. &ch_rate[0], &spkright_port_types[0]);
  7004. if (dapm->component) {
  7005. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  7006. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  7007. }
  7008. } else {
  7009. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  7010. codec->component.name);
  7011. ret = -EINVAL;
  7012. goto err;
  7013. }
  7014. pdata = snd_soc_card_get_drvdata(component->card);
  7015. if (pdata && pdata->codec_root)
  7016. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  7017. codec);
  7018. err:
  7019. return ret;
  7020. }
  7021. static int msm_init_wsa_dev(struct platform_device *pdev,
  7022. struct snd_soc_card *card)
  7023. {
  7024. struct device_node *wsa_of_node;
  7025. u32 wsa_max_devs;
  7026. u32 wsa_dev_cnt;
  7027. int i;
  7028. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  7029. const char *wsa_auxdev_name_prefix[1];
  7030. char *dev_name_str = NULL;
  7031. int found = 0;
  7032. int ret = 0;
  7033. /* Get maximum WSA device count for this platform */
  7034. ret = of_property_read_u32(pdev->dev.of_node,
  7035. "qcom,wsa-max-devs", &wsa_max_devs);
  7036. if (ret) {
  7037. dev_info(&pdev->dev,
  7038. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  7039. __func__, pdev->dev.of_node->full_name, ret);
  7040. card->num_aux_devs = 0;
  7041. return 0;
  7042. }
  7043. if (wsa_max_devs == 0) {
  7044. dev_warn(&pdev->dev,
  7045. "%s: Max WSA devices is 0 for this target?\n",
  7046. __func__);
  7047. card->num_aux_devs = 0;
  7048. return 0;
  7049. }
  7050. /* Get count of WSA device phandles for this platform */
  7051. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7052. "qcom,wsa-devs", NULL);
  7053. if (wsa_dev_cnt == -ENOENT) {
  7054. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  7055. __func__);
  7056. goto err;
  7057. } else if (wsa_dev_cnt <= 0) {
  7058. dev_err(&pdev->dev,
  7059. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  7060. __func__, wsa_dev_cnt);
  7061. ret = -EINVAL;
  7062. goto err;
  7063. }
  7064. /*
  7065. * Expect total phandles count to be NOT less than maximum possible
  7066. * WSA count. However, if it is less, then assign same value to
  7067. * max count as well.
  7068. */
  7069. if (wsa_dev_cnt < wsa_max_devs) {
  7070. dev_dbg(&pdev->dev,
  7071. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  7072. __func__, wsa_max_devs, wsa_dev_cnt);
  7073. wsa_max_devs = wsa_dev_cnt;
  7074. }
  7075. /* Make sure prefix string passed for each WSA device */
  7076. ret = of_property_count_strings(pdev->dev.of_node,
  7077. "qcom,wsa-aux-dev-prefix");
  7078. if (ret != wsa_dev_cnt) {
  7079. dev_err(&pdev->dev,
  7080. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  7081. __func__, wsa_dev_cnt, ret);
  7082. ret = -EINVAL;
  7083. goto err;
  7084. }
  7085. /*
  7086. * Alloc mem to store phandle and index info of WSA device, if already
  7087. * registered with ALSA core
  7088. */
  7089. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  7090. sizeof(struct msm_wsa881x_dev_info),
  7091. GFP_KERNEL);
  7092. if (!wsa881x_dev_info) {
  7093. ret = -ENOMEM;
  7094. goto err;
  7095. }
  7096. /*
  7097. * search and check whether all WSA devices are already
  7098. * registered with ALSA core or not. If found a node, store
  7099. * the node and the index in a local array of struct for later
  7100. * use.
  7101. */
  7102. for (i = 0; i < wsa_dev_cnt; i++) {
  7103. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  7104. "qcom,wsa-devs", i);
  7105. if (unlikely(!wsa_of_node)) {
  7106. /* we should not be here */
  7107. dev_err(&pdev->dev,
  7108. "%s: wsa dev node is not present\n",
  7109. __func__);
  7110. ret = -EINVAL;
  7111. goto err_free_dev_info;
  7112. }
  7113. if (soc_find_component(wsa_of_node, NULL)) {
  7114. /* WSA device registered with ALSA core */
  7115. wsa881x_dev_info[found].of_node = wsa_of_node;
  7116. wsa881x_dev_info[found].index = i;
  7117. found++;
  7118. if (found == wsa_max_devs)
  7119. break;
  7120. }
  7121. }
  7122. if (found < wsa_max_devs) {
  7123. dev_err(&pdev->dev,
  7124. "%s: failed to find %d components. Found only %d\n",
  7125. __func__, wsa_max_devs, found);
  7126. return -EPROBE_DEFER;
  7127. }
  7128. dev_info(&pdev->dev,
  7129. "%s: found %d wsa881x devices registered with ALSA core\n",
  7130. __func__, found);
  7131. card->num_aux_devs = wsa_max_devs;
  7132. card->num_configs = wsa_max_devs;
  7133. /* Alloc array of AUX devs struct */
  7134. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7135. sizeof(struct snd_soc_aux_dev),
  7136. GFP_KERNEL);
  7137. if (!msm_aux_dev) {
  7138. ret = -ENOMEM;
  7139. goto err_free_dev_info;
  7140. }
  7141. /* Alloc array of codec conf struct */
  7142. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7143. sizeof(struct snd_soc_codec_conf),
  7144. GFP_KERNEL);
  7145. if (!msm_codec_conf) {
  7146. ret = -ENOMEM;
  7147. goto err_free_aux_dev;
  7148. }
  7149. for (i = 0; i < card->num_aux_devs; i++) {
  7150. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7151. GFP_KERNEL);
  7152. if (!dev_name_str) {
  7153. ret = -ENOMEM;
  7154. goto err_free_cdc_conf;
  7155. }
  7156. ret = of_property_read_string_index(pdev->dev.of_node,
  7157. "qcom,wsa-aux-dev-prefix",
  7158. wsa881x_dev_info[i].index,
  7159. wsa_auxdev_name_prefix);
  7160. if (ret) {
  7161. dev_err(&pdev->dev,
  7162. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  7163. __func__, ret);
  7164. ret = -EINVAL;
  7165. goto err_free_dev_name_str;
  7166. }
  7167. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  7168. msm_aux_dev[i].name = dev_name_str;
  7169. msm_aux_dev[i].codec_name = NULL;
  7170. msm_aux_dev[i].codec_of_node =
  7171. wsa881x_dev_info[i].of_node;
  7172. msm_aux_dev[i].init = msm_wsa881x_init;
  7173. msm_codec_conf[i].dev_name = NULL;
  7174. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  7175. msm_codec_conf[i].of_node =
  7176. wsa881x_dev_info[i].of_node;
  7177. }
  7178. card->codec_conf = msm_codec_conf;
  7179. card->aux_dev = msm_aux_dev;
  7180. return 0;
  7181. err_free_dev_name_str:
  7182. devm_kfree(&pdev->dev, dev_name_str);
  7183. err_free_cdc_conf:
  7184. devm_kfree(&pdev->dev, msm_codec_conf);
  7185. err_free_aux_dev:
  7186. devm_kfree(&pdev->dev, msm_aux_dev);
  7187. err_free_dev_info:
  7188. devm_kfree(&pdev->dev, wsa881x_dev_info);
  7189. err:
  7190. return ret;
  7191. }
  7192. static int msm_csra66x0_init(struct snd_soc_component *component)
  7193. {
  7194. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  7195. if (!codec) {
  7196. pr_err("%s codec is NULL\n", __func__);
  7197. return -EINVAL;
  7198. }
  7199. return 0;
  7200. }
  7201. static int msm_init_csra_dev(struct platform_device *pdev,
  7202. struct snd_soc_card *card)
  7203. {
  7204. struct device_node *csra_of_node;
  7205. u32 csra_max_devs;
  7206. u32 csra_dev_cnt;
  7207. char *dev_name_str = NULL;
  7208. struct msm_csra66x0_dev_info *csra66x0_dev_info;
  7209. const char *csra_auxdev_name_prefix[1];
  7210. int i;
  7211. int found = 0;
  7212. int ret = 0;
  7213. /* Get maximum CSRA device count for this platform */
  7214. ret = of_property_read_u32(pdev->dev.of_node,
  7215. "qcom,csra-max-devs", &csra_max_devs);
  7216. if (ret) {
  7217. dev_info(&pdev->dev,
  7218. "%s: csra-max-devs property missing in DT %s, ret = %d\n",
  7219. __func__, pdev->dev.of_node->full_name, ret);
  7220. card->num_aux_devs = 0;
  7221. return 0;
  7222. }
  7223. if (csra_max_devs == 0) {
  7224. dev_warn(&pdev->dev,
  7225. "%s: Max CSRA devices is 0 for this target?\n",
  7226. __func__);
  7227. return 0;
  7228. }
  7229. /* Get count of CSRA device phandles for this platform */
  7230. csra_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7231. "qcom,csra-devs", NULL);
  7232. if (csra_dev_cnt == -ENOENT) {
  7233. dev_warn(&pdev->dev, "%s: No csra device defined in DT.\n",
  7234. __func__);
  7235. goto err;
  7236. } else if (csra_dev_cnt <= 0) {
  7237. dev_err(&pdev->dev,
  7238. "%s: Error reading csra device from DT. csra_dev_cnt = %d\n",
  7239. __func__, csra_dev_cnt);
  7240. ret = -EINVAL;
  7241. goto err;
  7242. }
  7243. /*
  7244. * Expect total phandles count to be NOT less than maximum possible
  7245. * CSRA count. However, if it is less, then assign same value to
  7246. * max count as well.
  7247. */
  7248. if (csra_dev_cnt < csra_max_devs) {
  7249. dev_dbg(&pdev->dev,
  7250. "%s: csra_max_devs = %d cannot exceed csra_dev_cnt = %d\n",
  7251. __func__, csra_max_devs, csra_dev_cnt);
  7252. csra_max_devs = csra_dev_cnt;
  7253. }
  7254. /* Make sure prefix string passed for each CSRA device */
  7255. ret = of_property_count_strings(pdev->dev.of_node,
  7256. "qcom,csra-aux-dev-prefix");
  7257. if (ret != csra_dev_cnt) {
  7258. dev_err(&pdev->dev,
  7259. "%s: expecting %d csra prefix. Defined only %d in DT\n",
  7260. __func__, csra_dev_cnt, ret);
  7261. ret = -EINVAL;
  7262. goto err;
  7263. }
  7264. /*
  7265. * Alloc mem to store phandle and index info of CSRA device, if already
  7266. * registered with ALSA core
  7267. */
  7268. csra66x0_dev_info = devm_kcalloc(&pdev->dev, csra_max_devs,
  7269. sizeof(struct msm_csra66x0_dev_info),
  7270. GFP_KERNEL);
  7271. if (!csra66x0_dev_info) {
  7272. ret = -ENOMEM;
  7273. goto err;
  7274. }
  7275. /*
  7276. * search and check whether all CSRA devices are already
  7277. * registered with ALSA core or not. If found a node, store
  7278. * the node and the index in a local array of struct for later
  7279. * use.
  7280. */
  7281. for (i = 0; i < csra_dev_cnt; i++) {
  7282. csra_of_node = of_parse_phandle(pdev->dev.of_node,
  7283. "qcom,csra-devs", i);
  7284. if (unlikely(!csra_of_node)) {
  7285. /* we should not be here */
  7286. dev_err(&pdev->dev,
  7287. "%s: csra dev node is not present\n",
  7288. __func__);
  7289. ret = -EINVAL;
  7290. goto err_free_dev_info;
  7291. }
  7292. if (soc_find_component(csra_of_node, NULL)) {
  7293. /* CSRA device registered with ALSA core */
  7294. csra66x0_dev_info[found].of_node = csra_of_node;
  7295. csra66x0_dev_info[found].index = i;
  7296. found++;
  7297. if (found == csra_max_devs)
  7298. break;
  7299. }
  7300. }
  7301. if (found < csra_max_devs) {
  7302. dev_dbg(&pdev->dev,
  7303. "%s: failed to find %d components. Found only %d\n",
  7304. __func__, csra_max_devs, found);
  7305. return -EPROBE_DEFER;
  7306. }
  7307. dev_info(&pdev->dev,
  7308. "%s: found %d csra66x0 devices registered with ALSA core\n",
  7309. __func__, found);
  7310. card->num_aux_devs = csra_max_devs;
  7311. card->num_configs = csra_max_devs;
  7312. /* Alloc array of AUX devs struct */
  7313. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7314. sizeof(struct snd_soc_aux_dev), GFP_KERNEL);
  7315. if (!msm_aux_dev) {
  7316. ret = -ENOMEM;
  7317. goto err_free_dev_info;
  7318. }
  7319. /* Alloc array of codec conf struct */
  7320. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7321. sizeof(struct snd_soc_codec_conf), GFP_KERNEL);
  7322. if (!msm_codec_conf) {
  7323. ret = -ENOMEM;
  7324. goto err_free_aux_dev;
  7325. }
  7326. for (i = 0; i < card->num_aux_devs; i++) {
  7327. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7328. GFP_KERNEL);
  7329. if (!dev_name_str) {
  7330. ret = -ENOMEM;
  7331. goto err_free_cdc_conf;
  7332. }
  7333. ret = of_property_read_string_index(pdev->dev.of_node,
  7334. "qcom,csra-aux-dev-prefix",
  7335. csra66x0_dev_info[i].index,
  7336. csra_auxdev_name_prefix);
  7337. if (ret) {
  7338. dev_err(&pdev->dev,
  7339. "%s: failed to read csra aux dev prefix, ret = %d\n",
  7340. __func__, ret);
  7341. ret = -EINVAL;
  7342. goto err_free_dev_name_str;
  7343. }
  7344. snprintf(dev_name_str, strlen("csra66x0.%d"), "csra66x0.%d", i);
  7345. msm_aux_dev[i].name = dev_name_str;
  7346. msm_aux_dev[i].codec_name = NULL;
  7347. msm_aux_dev[i].codec_of_node =
  7348. csra66x0_dev_info[i].of_node;
  7349. msm_aux_dev[i].init = msm_csra66x0_init; /* codec specific init */
  7350. msm_codec_conf[i].dev_name = NULL;
  7351. msm_codec_conf[i].name_prefix = csra_auxdev_name_prefix[0];
  7352. msm_codec_conf[i].of_node = csra66x0_dev_info[i].of_node;
  7353. }
  7354. card->codec_conf = msm_codec_conf;
  7355. card->aux_dev = msm_aux_dev;
  7356. return 0;
  7357. err_free_dev_name_str:
  7358. devm_kfree(&pdev->dev, dev_name_str);
  7359. err_free_cdc_conf:
  7360. devm_kfree(&pdev->dev, msm_codec_conf);
  7361. err_free_aux_dev:
  7362. devm_kfree(&pdev->dev, msm_aux_dev);
  7363. err_free_dev_info:
  7364. devm_kfree(&pdev->dev, csra66x0_dev_info);
  7365. err:
  7366. return ret;
  7367. }
  7368. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  7369. {
  7370. int count;
  7371. u32 mi2s_master_slave[MI2S_MAX];
  7372. int ret;
  7373. for (count = 0; count < MI2S_MAX; count++) {
  7374. mutex_init(&mi2s_intf_conf[count].lock);
  7375. mi2s_intf_conf[count].ref_cnt = 0;
  7376. }
  7377. ret = of_property_read_u32_array(pdev->dev.of_node,
  7378. "qcom,msm-mi2s-master",
  7379. mi2s_master_slave, MI2S_MAX);
  7380. if (ret) {
  7381. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  7382. __func__);
  7383. } else {
  7384. for (count = 0; count < MI2S_MAX; count++) {
  7385. mi2s_intf_conf[count].msm_is_mi2s_master =
  7386. mi2s_master_slave[count];
  7387. }
  7388. }
  7389. }
  7390. static void msm_i2s_auxpcm_deinit(void)
  7391. {
  7392. int count;
  7393. for (count = 0; count < MI2S_MAX; count++) {
  7394. mutex_destroy(&mi2s_intf_conf[count].lock);
  7395. mi2s_intf_conf[count].ref_cnt = 0;
  7396. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  7397. }
  7398. }
  7399. static int msm_scan_i2c_addr(struct platform_device *pdev,
  7400. uint32_t busnum, uint32_t addr)
  7401. {
  7402. struct i2c_adapter *adap;
  7403. u8 rbuf;
  7404. struct i2c_msg msg;
  7405. int status = 0;
  7406. adap = i2c_get_adapter(busnum);
  7407. if (!adap) {
  7408. dev_err(&pdev->dev, "%s: Cannot get I2C adapter %d\n",
  7409. __func__, busnum);
  7410. return -EBUSY;
  7411. }
  7412. /* to test presence, read one byte from device */
  7413. msg.addr = addr;
  7414. msg.flags = I2C_M_RD;
  7415. msg.len = 1;
  7416. msg.buf = &rbuf;
  7417. status = i2c_transfer(adap, &msg, 1);
  7418. i2c_put_adapter(adap);
  7419. if (status != 1) {
  7420. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x failed\n",
  7421. __func__, addr);
  7422. return -ENODEV;
  7423. }
  7424. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x successful\n",
  7425. __func__, addr);
  7426. return 0;
  7427. }
  7428. static int msm_detect_ep92_dev(struct platform_device *pdev,
  7429. struct snd_soc_card *card)
  7430. {
  7431. int i;
  7432. uint32_t ep92_busnum = 0;
  7433. uint32_t ep92_reg = 0;
  7434. const char *ep92_name = NULL;
  7435. struct snd_soc_dai_link *dai;
  7436. int rc = 0;
  7437. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-busnum",
  7438. &ep92_busnum);
  7439. if (rc) {
  7440. dev_info(&pdev->dev, "%s: No DT match ep92-reg\n", __func__);
  7441. return 0;
  7442. }
  7443. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-reg",
  7444. &ep92_reg);
  7445. if (rc) {
  7446. dev_info(&pdev->dev, "%s: No DT match ep92-busnum\n", __func__);
  7447. return 0;
  7448. }
  7449. rc = of_property_read_string(pdev->dev.of_node, "qcom,ep92-name",
  7450. &ep92_name);
  7451. if (rc) {
  7452. dev_info(&pdev->dev, "%s: No DT match ep92-name\n", __func__);
  7453. return 0;
  7454. }
  7455. /* check I2C bus for connected ep92 chip */
  7456. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  7457. /* check a second time after a short delay */
  7458. msleep(20);
  7459. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  7460. dev_info(&pdev->dev, "%s: No ep92 device found\n",
  7461. __func__);
  7462. /* continue with snd_card registration without ep92 */
  7463. return 0;
  7464. }
  7465. }
  7466. dev_info(&pdev->dev, "%s: ep92 device found\n", __func__);
  7467. /* update codec info in MI2S dai link */
  7468. dai = &msm_mi2s_be_dai_links[0];
  7469. for (i=0; i<ARRAY_SIZE(msm_mi2s_be_dai_links); i++) {
  7470. if (strcmp(dai->name, LPASS_BE_SEC_MI2S_TX) == 0) {
  7471. dev_dbg(&pdev->dev,
  7472. "%s: Set Sec MI2S dai to ep92 codec\n",
  7473. __func__);
  7474. dai->codec_name = ep92_name;
  7475. dai->codec_dai_name = "ep92-hdmi";
  7476. break;
  7477. }
  7478. dai++;
  7479. }
  7480. /* update codec info in SPDIF dai link */
  7481. dai = &msm_spdif_be_dai_links[0];
  7482. for (i=0; i<ARRAY_SIZE(msm_spdif_be_dai_links); i++) {
  7483. if (strcmp(dai->name, LPASS_BE_SEC_SPDIF_TX) == 0) {
  7484. dev_dbg(&pdev->dev,
  7485. "%s: Set Sec SPDIF dai to ep92 codec\n",
  7486. __func__);
  7487. dai->codec_name = ep92_name;
  7488. dai->codec_dai_name = "ep92-arc";
  7489. break;
  7490. }
  7491. dai++;
  7492. }
  7493. return 0;
  7494. }
  7495. static int msm_asoc_machine_probe(struct platform_device *pdev)
  7496. {
  7497. struct snd_soc_card *card;
  7498. struct msm_asoc_mach_data *pdata;
  7499. int ret;
  7500. u32 val;
  7501. if (!pdev->dev.of_node) {
  7502. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  7503. return -EINVAL;
  7504. }
  7505. pdata = devm_kzalloc(&pdev->dev,
  7506. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  7507. if (!pdata)
  7508. return -ENOMEM;
  7509. /* test for ep92 HDMI bridge and update dai links accordingly */
  7510. ret = msm_detect_ep92_dev(pdev, card);
  7511. if (ret)
  7512. goto err;
  7513. card = populate_snd_card_dailinks(&pdev->dev);
  7514. if (!card) {
  7515. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  7516. ret = -EINVAL;
  7517. goto err;
  7518. }
  7519. card->dev = &pdev->dev;
  7520. platform_set_drvdata(pdev, card);
  7521. snd_soc_card_set_drvdata(card, pdata);
  7522. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  7523. if (ret) {
  7524. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  7525. ret);
  7526. goto err;
  7527. }
  7528. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  7529. if (ret) {
  7530. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  7531. ret);
  7532. goto err;
  7533. }
  7534. ret = msm_populate_dai_link_component_of_node(card);
  7535. if (ret) {
  7536. ret = -EPROBE_DEFER;
  7537. goto err;
  7538. }
  7539. ret = of_property_read_u32(pdev->dev.of_node, "qcom,csra-codec", &val);
  7540. if (ret) {
  7541. dev_info(&pdev->dev, "no 'qcom,csra-codec' in DT\n");
  7542. val = 0;
  7543. }
  7544. if (val) {
  7545. ret = msm_init_csra_dev(pdev, card);
  7546. if (ret)
  7547. goto err;
  7548. } else {
  7549. ret = msm_init_wsa_dev(pdev, card);
  7550. if (ret)
  7551. goto err;
  7552. }
  7553. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7554. "qcom,cdc-dmic01-gpios",
  7555. 0);
  7556. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7557. "qcom,cdc-dmic23-gpios",
  7558. 0);
  7559. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7560. "qcom,cdc-dmic45-gpios",
  7561. 0);
  7562. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7563. "qcom,cdc-dmic67-gpios",
  7564. 0);
  7565. ret = devm_snd_soc_register_card(&pdev->dev, card);
  7566. if (ret == -EPROBE_DEFER) {
  7567. if (codec_reg_done)
  7568. ret = -EINVAL;
  7569. goto err;
  7570. } else if (ret) {
  7571. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  7572. ret);
  7573. goto err;
  7574. }
  7575. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  7576. spdev = pdev;
  7577. ret = msm_mdf_mem_init();
  7578. if (ret)
  7579. dev_err(&pdev->dev, "msm_mdf_mem_init failed (%d)\n",
  7580. ret);
  7581. /* Parse pinctrl info from devicetree */
  7582. ret = msm_get_pinctrl(pdev);
  7583. if (!ret) {
  7584. pr_debug("%s: pinctrl parsing successful\n", __func__);
  7585. } else {
  7586. dev_dbg(&pdev->dev,
  7587. "%s: Parsing pinctrl failed with %d. Cannot use Ports\n",
  7588. __func__, ret);
  7589. ret = 0;
  7590. }
  7591. msm_i2s_auxpcm_init(pdev);
  7592. is_initial_boot = true;
  7593. return 0;
  7594. err:
  7595. msm_release_pinctrl(pdev);
  7596. return ret;
  7597. }
  7598. static int msm_asoc_machine_remove(struct platform_device *pdev)
  7599. {
  7600. audio_notifier_deregister("qcs405");
  7601. msm_i2s_auxpcm_deinit();
  7602. msm_mdf_mem_deinit();
  7603. msm_release_pinctrl(pdev);
  7604. return 0;
  7605. }
  7606. static struct platform_driver qcs405_asoc_machine_driver = {
  7607. .driver = {
  7608. .name = DRV_NAME,
  7609. .owner = THIS_MODULE,
  7610. .pm = &snd_soc_pm_ops,
  7611. .of_match_table = qcs405_asoc_machine_of_match,
  7612. },
  7613. .probe = msm_asoc_machine_probe,
  7614. .remove = msm_asoc_machine_remove,
  7615. };
  7616. module_platform_driver(qcs405_asoc_machine_driver);
  7617. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  7618. MODULE_LICENSE("GPL v2");
  7619. MODULE_ALIAS("platform:" DRV_NAME);
  7620. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);