sde_kms.c 113 KB

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  1. /*
  2. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <drm/drm_crtc.h>
  20. #include <drm/drm_fixed.h>
  21. #include <drm/drm_panel.h>
  22. #include <linux/debugfs.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_irq.h>
  25. #include <linux/dma-buf.h>
  26. #include <linux/memblock.h>
  27. #include <drm/drm_atomic_uapi.h>
  28. #include <drm/drm_probe_helper.h>
  29. #include "msm_drv.h"
  30. #include "msm_mmu.h"
  31. #include "msm_gem.h"
  32. #include "dsi_display.h"
  33. #include "dsi_drm.h"
  34. #include "sde_wb.h"
  35. #include "dp_display.h"
  36. #include "dp_drm.h"
  37. #include "dp_mst_drm.h"
  38. #include "sde_kms.h"
  39. #include "sde_core_irq.h"
  40. #include "sde_formats.h"
  41. #include "sde_hw_vbif.h"
  42. #include "sde_vbif.h"
  43. #include "sde_encoder.h"
  44. #include "sde_plane.h"
  45. #include "sde_crtc.h"
  46. #include "sde_color_processing.h"
  47. #include "sde_reg_dma.h"
  48. #include "sde_connector.h"
  49. #include "sde_vm.h"
  50. #include <linux/qcom_scm.h>
  51. #include "soc/qcom/secure_buffer.h"
  52. #include <linux/qtee_shmbridge.h>
  53. #include <linux/haven/hh_irq_lend.h>
  54. #define CREATE_TRACE_POINTS
  55. #include "sde_trace.h"
  56. /* defines for secure channel call */
  57. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  58. #define MDP_DEVICE_ID 0x1A
  59. EXPORT_TRACEPOINT_SYMBOL(tracing_mark_write);
  60. static const char * const iommu_ports[] = {
  61. "mdp_0",
  62. };
  63. /**
  64. * Controls size of event log buffer. Specified as a power of 2.
  65. */
  66. #define SDE_EVTLOG_SIZE 1024
  67. /*
  68. * To enable overall DRM driver logging
  69. * # echo 0x2 > /sys/module/drm/parameters/debug
  70. *
  71. * To enable DRM driver h/w logging
  72. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  73. *
  74. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  75. */
  76. #define SDE_DEBUGFS_DIR "msm_sde"
  77. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  78. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  79. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  80. /**
  81. * sdecustom - enable certain driver customizations for sde clients
  82. * Enabling this modifies the standard DRM behavior slightly and assumes
  83. * that the clients have specific knowledge about the modifications that
  84. * are involved, so don't enable this unless you know what you're doing.
  85. *
  86. * Parts of the driver that are affected by this setting may be located by
  87. * searching for invocations of the 'sde_is_custom_client()' function.
  88. *
  89. * This is disabled by default.
  90. */
  91. static bool sdecustom = true;
  92. module_param(sdecustom, bool, 0400);
  93. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  94. static int sde_kms_hw_init(struct msm_kms *kms);
  95. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  96. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  97. static int _sde_kms_register_events(struct msm_kms *kms,
  98. struct drm_mode_object *obj, u32 event, bool en);
  99. bool sde_is_custom_client(void)
  100. {
  101. return sdecustom;
  102. }
  103. #ifdef CONFIG_DEBUG_FS
  104. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  105. {
  106. struct msm_drm_private *priv;
  107. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  108. return NULL;
  109. priv = sde_kms->dev->dev_private;
  110. return priv->debug_root;
  111. }
  112. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  113. {
  114. void *p;
  115. int rc;
  116. void *debugfs_root;
  117. p = sde_hw_util_get_log_mask_ptr();
  118. if (!sde_kms || !p)
  119. return -EINVAL;
  120. debugfs_root = sde_debugfs_get_root(sde_kms);
  121. if (!debugfs_root)
  122. return -EINVAL;
  123. /* allow debugfs_root to be NULL */
  124. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  125. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  126. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  127. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  128. if (rc) {
  129. SDE_ERROR("failed to init perf %d\n", rc);
  130. return rc;
  131. }
  132. if (sde_kms->catalog->qdss_count)
  133. debugfs_create_u32("qdss", 0600, debugfs_root,
  134. (u32 *)&sde_kms->qdss_enabled);
  135. debugfs_create_u32("pm_suspend_clk_dump", 0600, debugfs_root,
  136. (u32 *)&sde_kms->pm_suspend_clk_dump);
  137. return 0;
  138. }
  139. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  140. {
  141. struct sde_kms *sde_kms = to_sde_kms(kms);
  142. /* don't need to NULL check debugfs_root */
  143. if (sde_kms) {
  144. sde_debugfs_vbif_destroy(sde_kms);
  145. sde_debugfs_core_irq_destroy(sde_kms);
  146. }
  147. }
  148. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  149. {
  150. int i;
  151. struct device *dev = sde_kms->dev->dev;
  152. SDE_INFO("runtime PM suspended:%d", pm_runtime_suspended(dev));
  153. for (i = 0; i < sde_kms->dsi_display_count; i++)
  154. dsi_display_dump_clks_state(sde_kms->dsi_displays[i]);
  155. return 0;
  156. }
  157. #else
  158. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  159. {
  160. return 0;
  161. }
  162. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  163. {
  164. }
  165. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  166. {
  167. return 0;
  168. }
  169. #endif
  170. static int sde_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  171. {
  172. int ret;
  173. if (!kms || !crtc)
  174. return -EINVAL;
  175. SDE_ATRACE_BEGIN("sde_kms_enable_vblank");
  176. ret = sde_crtc_vblank(crtc, true);
  177. SDE_ATRACE_END("sde_kms_enable_vblank");
  178. return ret;
  179. }
  180. static void sde_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  181. {
  182. if (!kms || !crtc)
  183. return;
  184. SDE_ATRACE_BEGIN("sde_kms_disable_vblank");
  185. sde_crtc_vblank(crtc, false);
  186. SDE_ATRACE_END("sde_kms_disable_vblank");
  187. }
  188. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  189. struct drm_crtc *crtc)
  190. {
  191. struct drm_encoder *encoder;
  192. struct drm_device *dev;
  193. int ret;
  194. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  195. SDE_ERROR("invalid params\n");
  196. return;
  197. }
  198. if (!crtc->state->enable) {
  199. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  200. return;
  201. }
  202. if (!crtc->state->active) {
  203. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  204. return;
  205. }
  206. dev = crtc->dev;
  207. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  208. if (encoder->crtc != crtc)
  209. continue;
  210. /*
  211. * Video Mode - Wait for VSYNC
  212. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  213. * complete
  214. */
  215. SDE_EVT32_VERBOSE(DRMID(crtc));
  216. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  217. if (ret && ret != -EWOULDBLOCK) {
  218. SDE_ERROR(
  219. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  220. crtc->base.id, encoder->base.id, ret);
  221. break;
  222. }
  223. }
  224. }
  225. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  226. struct drm_crtc *crtc, bool enable)
  227. {
  228. struct drm_device *dev;
  229. struct msm_drm_private *priv;
  230. struct sde_mdss_cfg *sde_cfg;
  231. struct drm_plane *plane;
  232. int i, ret;
  233. dev = sde_kms->dev;
  234. priv = dev->dev_private;
  235. sde_cfg = sde_kms->catalog;
  236. ret = sde_vbif_halt_xin_mask(sde_kms,
  237. sde_cfg->sui_block_xin_mask, enable);
  238. if (ret) {
  239. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  240. return ret;
  241. }
  242. if (enable) {
  243. for (i = 0; i < priv->num_planes; i++) {
  244. plane = priv->planes[i];
  245. sde_plane_secure_ctrl_xin_client(plane, crtc);
  246. }
  247. }
  248. return 0;
  249. }
  250. /**
  251. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  252. * @sde_kms: Pointer to sde_kms struct
  253. * @vimd: switch the stage 2 translation to this VMID
  254. */
  255. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  256. {
  257. struct device dummy = {};
  258. dma_addr_t dma_handle;
  259. uint32_t num_sids;
  260. uint32_t *sec_sid;
  261. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  262. int ret = 0, i;
  263. struct qtee_shm shm;
  264. bool qtee_en = qtee_shmbridge_is_enabled();
  265. phys_addr_t mem_addr;
  266. u64 mem_size;
  267. num_sids = sde_cfg->sec_sid_mask_count;
  268. if (!num_sids) {
  269. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  270. return -EINVAL;
  271. }
  272. if (qtee_en) {
  273. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  274. &shm);
  275. if (ret)
  276. return -ENOMEM;
  277. sec_sid = (uint32_t *) shm.vaddr;
  278. mem_addr = shm.paddr;
  279. /**
  280. * SMMUSecureModeSwitch requires the size to be number of SID's
  281. * but shm allocates size in pages. Modify the args as per
  282. * client requirement.
  283. */
  284. mem_size = sizeof(uint32_t) * num_sids;
  285. } else {
  286. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  287. if (!sec_sid)
  288. return -ENOMEM;
  289. mem_addr = virt_to_phys(sec_sid);
  290. mem_size = sizeof(uint32_t) * num_sids;
  291. }
  292. for (i = 0; i < num_sids; i++) {
  293. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  294. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  295. }
  296. ret = dma_coerce_mask_and_coherent(&dummy, DMA_BIT_MASK(64));
  297. if (ret) {
  298. SDE_ERROR("Failed to set dma mask for dummy dev %d\n", ret);
  299. goto map_error;
  300. }
  301. set_dma_ops(&dummy, NULL);
  302. dma_handle = dma_map_single(&dummy, sec_sid,
  303. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  304. if (dma_mapping_error(&dummy, dma_handle)) {
  305. SDE_ERROR("dma_map_single for dummy dev failed vmid 0x%x\n",
  306. vmid);
  307. goto map_error;
  308. }
  309. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  310. vmid, num_sids, qtee_en);
  311. ret = qcom_scm_mem_protect_sd_ctrl(MDP_DEVICE_ID, mem_addr,
  312. mem_size, vmid);
  313. if (ret)
  314. SDE_ERROR("Error:scm_call2, vmid %lld, ret%d\n",
  315. vmid, ret);
  316. SDE_EVT32(MEM_PROTECT_SD_CTRL_SWITCH, MDP_DEVICE_ID, mem_size,
  317. vmid, qtee_en, num_sids, ret);
  318. dma_unmap_single(&dummy, dma_handle,
  319. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  320. map_error:
  321. if (qtee_en)
  322. qtee_shmbridge_free_shm(&shm);
  323. else
  324. kfree(sec_sid);
  325. return ret;
  326. }
  327. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  328. {
  329. u32 ret;
  330. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  331. return 0;
  332. /* detach_all_contexts */
  333. ret = sde_kms_mmu_detach(sde_kms, false);
  334. if (ret) {
  335. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  336. goto mmu_error;
  337. }
  338. ret = _sde_kms_scm_call(sde_kms, vmid);
  339. if (ret) {
  340. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  341. goto scm_error;
  342. }
  343. return 0;
  344. scm_error:
  345. sde_kms_mmu_attach(sde_kms, false);
  346. mmu_error:
  347. atomic_dec(&sde_kms->detach_all_cb);
  348. return ret;
  349. }
  350. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, u32 vmid,
  351. u32 old_vmid)
  352. {
  353. u32 ret;
  354. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  355. return 0;
  356. ret = _sde_kms_scm_call(sde_kms, vmid);
  357. if (ret) {
  358. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  359. goto scm_error;
  360. }
  361. /* attach_all_contexts */
  362. ret = sde_kms_mmu_attach(sde_kms, false);
  363. if (ret) {
  364. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  365. goto mmu_error;
  366. }
  367. return 0;
  368. mmu_error:
  369. _sde_kms_scm_call(sde_kms, old_vmid);
  370. scm_error:
  371. atomic_inc(&sde_kms->detach_all_cb);
  372. return ret;
  373. }
  374. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  375. {
  376. u32 ret;
  377. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  378. return 0;
  379. /* detach secure_context */
  380. ret = sde_kms_mmu_detach(sde_kms, true);
  381. if (ret) {
  382. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  383. goto mmu_error;
  384. }
  385. ret = _sde_kms_scm_call(sde_kms, vmid);
  386. if (ret) {
  387. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  388. goto scm_error;
  389. }
  390. return 0;
  391. scm_error:
  392. sde_kms_mmu_attach(sde_kms, true);
  393. mmu_error:
  394. atomic_dec(&sde_kms->detach_sec_cb);
  395. return ret;
  396. }
  397. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, u32 vmid,
  398. u32 old_vmid)
  399. {
  400. u32 ret;
  401. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  402. return 0;
  403. ret = _sde_kms_scm_call(sde_kms, vmid);
  404. if (ret) {
  405. goto scm_error;
  406. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  407. }
  408. ret = sde_kms_mmu_attach(sde_kms, true);
  409. if (ret) {
  410. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  411. goto mmu_error;
  412. }
  413. return 0;
  414. mmu_error:
  415. _sde_kms_scm_call(sde_kms, old_vmid);
  416. scm_error:
  417. atomic_inc(&sde_kms->detach_sec_cb);
  418. return ret;
  419. }
  420. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  421. struct drm_crtc *crtc, bool enable)
  422. {
  423. int ret;
  424. if (enable) {
  425. ret = pm_runtime_get_sync(sde_kms->dev->dev);
  426. if (ret < 0) {
  427. SDE_ERROR("failed to enable resource, ret:%d\n", ret);
  428. return ret;
  429. }
  430. sde_crtc_misr_setup(crtc, true, 1);
  431. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  432. if (ret) {
  433. sde_crtc_misr_setup(crtc, false, 0);
  434. pm_runtime_put_sync(sde_kms->dev->dev);
  435. return ret;
  436. }
  437. } else {
  438. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  439. sde_crtc_misr_setup(crtc, false, 0);
  440. pm_runtime_put_sync(sde_kms->dev->dev);
  441. }
  442. return 0;
  443. }
  444. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  445. bool post_commit)
  446. {
  447. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  448. int old_smmu_state = smmu_state->state;
  449. int ret = 0;
  450. u32 vmid;
  451. if (!sde_kms || !crtc) {
  452. SDE_ERROR("invalid argument(s)\n");
  453. return -EINVAL;
  454. }
  455. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  456. post_commit, smmu_state->sui_misr_state,
  457. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  458. if ((!smmu_state->transition_type) ||
  459. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  460. /* Bail out */
  461. return 0;
  462. /* enable sui misr if requested, before the transition */
  463. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  464. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  465. if (ret) {
  466. smmu_state->sui_misr_state = NONE;
  467. goto end;
  468. }
  469. }
  470. mutex_lock(&sde_kms->secure_transition_lock);
  471. switch (smmu_state->state) {
  472. case DETACH_ALL_REQ:
  473. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  474. if (!ret)
  475. smmu_state->state = DETACHED;
  476. break;
  477. case ATTACH_ALL_REQ:
  478. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL,
  479. VMID_CP_SEC_DISPLAY);
  480. if (!ret) {
  481. smmu_state->state = ATTACHED;
  482. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  483. }
  484. break;
  485. case DETACH_SEC_REQ:
  486. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  487. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  488. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  489. if (!ret)
  490. smmu_state->state = DETACHED_SEC;
  491. break;
  492. case ATTACH_SEC_REQ:
  493. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  494. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  495. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL, vmid);
  496. if (!ret) {
  497. smmu_state->state = ATTACHED;
  498. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  499. }
  500. break;
  501. default:
  502. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  503. DRMID(crtc), smmu_state->state,
  504. smmu_state->transition_type);
  505. ret = -EINVAL;
  506. break;
  507. }
  508. mutex_unlock(&sde_kms->secure_transition_lock);
  509. /* disable sui misr if requested, after the transition */
  510. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  511. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  512. if (ret)
  513. goto end;
  514. }
  515. end:
  516. smmu_state->transition_error = false;
  517. if (ret) {
  518. smmu_state->transition_error = true;
  519. SDE_ERROR(
  520. "crtc%d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  521. DRMID(crtc), old_smmu_state, smmu_state->state,
  522. smmu_state->secure_level, ret);
  523. smmu_state->state = smmu_state->prev_state;
  524. smmu_state->secure_level = smmu_state->prev_secure_level;
  525. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ)
  526. _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  527. }
  528. SDE_DEBUG("crtc %d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  529. DRMID(crtc), old_smmu_state, smmu_state->state,
  530. smmu_state->secure_level, ret);
  531. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->prev_state,
  532. smmu_state->transition_type,
  533. smmu_state->transition_error,
  534. smmu_state->secure_level, smmu_state->prev_secure_level,
  535. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  536. smmu_state->sui_misr_state = NONE;
  537. smmu_state->transition_type = NONE;
  538. return ret;
  539. }
  540. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  541. struct drm_atomic_state *state)
  542. {
  543. struct drm_crtc *crtc;
  544. struct drm_crtc_state *old_crtc_state;
  545. struct drm_plane_state *old_plane_state, *new_plane_state;
  546. struct drm_plane *plane;
  547. struct drm_plane_state *plane_state;
  548. struct sde_kms *sde_kms = to_sde_kms(kms);
  549. struct drm_device *dev = sde_kms->dev;
  550. int i, ops = 0, ret = 0;
  551. bool old_valid_fb = false;
  552. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  553. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  554. if (!crtc->state || !crtc->state->active)
  555. continue;
  556. /*
  557. * It is safe to assume only one active crtc,
  558. * and compatible translation modes on the
  559. * planes staged on this crtc.
  560. * otherwise validation would have failed.
  561. * For this CRTC,
  562. */
  563. /*
  564. * 1. Check if old state on the CRTC has planes
  565. * staged with valid fbs
  566. */
  567. for_each_old_plane_in_state(state, plane, plane_state, i) {
  568. if (!plane_state->crtc)
  569. continue;
  570. if (plane_state->fb) {
  571. old_valid_fb = true;
  572. break;
  573. }
  574. }
  575. /*
  576. * 2.Get the operations needed to be performed before
  577. * secure transition can be initiated.
  578. */
  579. ops = sde_crtc_get_secure_transition_ops(crtc,
  580. old_crtc_state, old_valid_fb);
  581. if (ops < 0) {
  582. SDE_ERROR("invalid secure operations %x\n", ops);
  583. return ops;
  584. }
  585. if (!ops) {
  586. smmu_state->transition_error = false;
  587. goto no_ops;
  588. }
  589. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  590. crtc->base.id, ops, crtc->state);
  591. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  592. /* 3. Perform operations needed for secure transition */
  593. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  594. SDE_DEBUG("wait_for_transfer_done\n");
  595. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  596. }
  597. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  598. SDE_DEBUG("cleanup planes\n");
  599. drm_atomic_helper_cleanup_planes(dev, state);
  600. for_each_oldnew_plane_in_state(state, plane,
  601. old_plane_state, new_plane_state, i)
  602. sde_plane_destroy_fb(old_plane_state);
  603. }
  604. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  605. SDE_DEBUG("secure ctrl\n");
  606. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  607. }
  608. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  609. SDE_DEBUG("prepare planes %d",
  610. crtc->state->plane_mask);
  611. drm_atomic_crtc_for_each_plane(plane,
  612. crtc) {
  613. const struct drm_plane_helper_funcs *funcs;
  614. plane_state = plane->state;
  615. funcs = plane->helper_private;
  616. SDE_DEBUG("psde:%d FB[%u]\n",
  617. plane->base.id,
  618. plane->fb->base.id);
  619. if (!funcs)
  620. continue;
  621. if (funcs->prepare_fb(plane, plane_state)) {
  622. ret = funcs->prepare_fb(plane,
  623. plane_state);
  624. if (ret)
  625. return ret;
  626. }
  627. }
  628. }
  629. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  630. SDE_DEBUG("secure operations completed\n");
  631. }
  632. no_ops:
  633. return 0;
  634. }
  635. static int _sde_kms_release_splash_buffer(unsigned int mem_addr,
  636. unsigned int splash_buffer_size,
  637. unsigned int ramdump_base,
  638. unsigned int ramdump_buffer_size)
  639. {
  640. unsigned long pfn_start, pfn_end, pfn_idx;
  641. int ret = 0;
  642. if (!mem_addr || !splash_buffer_size) {
  643. SDE_ERROR("invalid params\n");
  644. return -EINVAL;
  645. }
  646. /* leave ramdump memory only if base address matches */
  647. if (ramdump_base == mem_addr &&
  648. ramdump_buffer_size <= splash_buffer_size) {
  649. mem_addr += ramdump_buffer_size;
  650. splash_buffer_size -= ramdump_buffer_size;
  651. }
  652. pfn_start = mem_addr >> PAGE_SHIFT;
  653. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  654. ret = memblock_free(mem_addr, splash_buffer_size);
  655. if (ret) {
  656. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  657. return ret;
  658. }
  659. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  660. free_reserved_page(pfn_to_page(pfn_idx));
  661. return ret;
  662. }
  663. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  664. struct sde_splash_mem *splash)
  665. {
  666. struct msm_mmu *mmu = NULL;
  667. int ret = 0;
  668. if (!sde_kms->aspace[0]) {
  669. SDE_ERROR("aspace not found for sde kms node\n");
  670. return -EINVAL;
  671. }
  672. mmu = sde_kms->aspace[0]->mmu;
  673. if (!mmu) {
  674. SDE_ERROR("mmu not found for aspace\n");
  675. return -EINVAL;
  676. }
  677. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  678. SDE_ERROR("invalid input params for map\n");
  679. return -EINVAL;
  680. }
  681. if (!splash->ref_cnt) {
  682. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  683. splash->splash_buf_base,
  684. splash->splash_buf_size,
  685. IOMMU_READ | IOMMU_NOEXEC);
  686. if (ret)
  687. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  688. }
  689. splash->ref_cnt++;
  690. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  691. splash->splash_buf_base,
  692. splash->splash_buf_size,
  693. splash->ref_cnt);
  694. return ret;
  695. }
  696. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  697. {
  698. int i = 0;
  699. int ret = 0;
  700. if (!sde_kms)
  701. return -EINVAL;
  702. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  703. ret = _sde_kms_splash_mem_get(sde_kms,
  704. sde_kms->splash_data.splash_display[i].splash);
  705. if (ret)
  706. return ret;
  707. }
  708. return ret;
  709. }
  710. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  711. struct sde_splash_mem *splash)
  712. {
  713. struct msm_mmu *mmu = NULL;
  714. int rc = 0;
  715. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  716. SDE_ERROR("invalid params\n");
  717. return -EINVAL;
  718. }
  719. mmu = sde_kms->aspace[0]->mmu;
  720. if (!splash || !splash->ref_cnt ||
  721. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  722. return -EINVAL;
  723. splash->ref_cnt--;
  724. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  725. splash->splash_buf_base, splash->ref_cnt);
  726. if (!splash->ref_cnt) {
  727. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  728. splash->splash_buf_size);
  729. rc = _sde_kms_release_splash_buffer(splash->splash_buf_base,
  730. splash->splash_buf_size, splash->ramdump_base,
  731. splash->ramdump_size);
  732. splash->splash_buf_base = 0;
  733. splash->splash_buf_size = 0;
  734. }
  735. return rc;
  736. }
  737. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  738. {
  739. int i = 0;
  740. int ret = 0;
  741. if (!sde_kms || !sde_kms->splash_data.num_splash_regions)
  742. return -EINVAL;
  743. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  744. ret = _sde_kms_splash_mem_put(sde_kms,
  745. sde_kms->splash_data.splash_display[i].splash);
  746. if (ret)
  747. return ret;
  748. }
  749. return ret;
  750. }
  751. static int _sde_kms_get_blank(struct drm_crtc_state *crtc_state,
  752. struct drm_connector_state *conn_state)
  753. {
  754. int lp_mode, blank;
  755. if (crtc_state->active)
  756. lp_mode = sde_connector_get_property(conn_state,
  757. CONNECTOR_PROP_LP);
  758. else
  759. lp_mode = SDE_MODE_DPMS_OFF;
  760. switch (lp_mode) {
  761. case SDE_MODE_DPMS_ON:
  762. blank = DRM_PANEL_BLANK_UNBLANK;
  763. break;
  764. case SDE_MODE_DPMS_LP1:
  765. case SDE_MODE_DPMS_LP2:
  766. blank = DRM_PANEL_BLANK_LP;
  767. break;
  768. case SDE_MODE_DPMS_OFF:
  769. default:
  770. blank = DRM_PANEL_BLANK_POWERDOWN;
  771. break;
  772. }
  773. return blank;
  774. }
  775. static void _sde_kms_drm_check_dpms(struct drm_atomic_state *old_state,
  776. unsigned long event)
  777. {
  778. struct drm_connector *connector;
  779. struct drm_connector_state *old_conn_state;
  780. struct drm_crtc_state *old_crtc_state;
  781. struct drm_crtc *crtc;
  782. int i, old_mode, new_mode, old_fps, new_fps;
  783. for_each_old_connector_in_state(old_state, connector,
  784. old_conn_state, i) {
  785. crtc = connector->state->crtc ? connector->state->crtc :
  786. old_conn_state->crtc;
  787. if (!crtc)
  788. continue;
  789. new_fps = crtc->state->mode.vrefresh;
  790. new_mode = _sde_kms_get_blank(crtc->state, connector->state);
  791. if (old_conn_state->crtc) {
  792. old_crtc_state = drm_atomic_get_existing_crtc_state(
  793. old_state, old_conn_state->crtc);
  794. old_fps = old_crtc_state->mode.vrefresh;
  795. old_mode = _sde_kms_get_blank(old_crtc_state,
  796. old_conn_state);
  797. } else {
  798. old_fps = 0;
  799. old_mode = DRM_PANEL_BLANK_POWERDOWN;
  800. }
  801. if ((old_mode != new_mode) || (old_fps != new_fps)) {
  802. struct drm_panel_notifier notifier_data;
  803. SDE_EVT32(old_mode, new_mode, old_fps, new_fps,
  804. connector->panel, crtc->state->active,
  805. old_conn_state->crtc, event);
  806. pr_debug("change detected (power mode %d->%d, fps %d->%d)\n",
  807. old_mode, new_mode, old_fps, new_fps);
  808. /* If suspend resume and fps change are happening
  809. * at the same time, give preference to power mode
  810. * changes rather than fps change.
  811. */
  812. if ((old_mode == new_mode) && (old_fps != new_fps))
  813. new_mode = DRM_PANEL_BLANK_FPS_CHANGE;
  814. notifier_data.data = &new_mode;
  815. notifier_data.refresh_rate = new_fps;
  816. notifier_data.id = connector->base.id;
  817. if (connector->panel)
  818. drm_panel_notifier_call_chain(connector->panel,
  819. event, &notifier_data);
  820. }
  821. }
  822. }
  823. int sde_kms_vm_primary_prepare_commit(struct sde_kms *sde_kms,
  824. struct drm_atomic_state *state)
  825. {
  826. struct drm_device *ddev;
  827. struct drm_crtc *crtc;
  828. struct drm_encoder *encoder;
  829. struct drm_connector *connector;
  830. struct sde_vm_ops *vm_ops;
  831. struct sde_crtc_state *cstate;
  832. enum sde_crtc_vm_req vm_req;
  833. int rc = 0;
  834. ddev = sde_kms->dev;
  835. vm_ops = sde_vm_get_ops(sde_kms);
  836. if (!vm_ops)
  837. return -EINVAL;
  838. crtc = state->crtcs[0].ptr;
  839. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  840. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  841. if (vm_req != VM_REQ_ACQUIRE)
  842. return 0;
  843. /* enable MDSS irq line */
  844. sde_irq_update(&sde_kms->base, true);
  845. /* clear the stale IRQ status bits */
  846. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  847. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  848. /* enable the display path IRQ's */
  849. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  850. sde_encoder_irq_control(encoder, true);
  851. /* Schedule ESD work */
  852. list_for_each_entry(connector, &ddev->mode_config.connector_list, head)
  853. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  854. sde_connector_schedule_status_work(connector, true);
  855. /* enable vblank events */
  856. drm_crtc_vblank_on(crtc);
  857. /* handle non-SDE pre_acquire */
  858. if (vm_ops->vm_client_post_acquire)
  859. rc = vm_ops->vm_client_post_acquire(sde_kms);
  860. return rc;
  861. }
  862. int sde_kms_vm_trusted_prepare_commit(struct sde_kms *sde_kms,
  863. struct drm_atomic_state *state)
  864. {
  865. struct drm_device *ddev;
  866. struct drm_plane *plane;
  867. struct sde_crtc_state *cstate;
  868. enum sde_crtc_vm_req vm_req;
  869. ddev = sde_kms->dev;
  870. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  871. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  872. if (vm_req != VM_REQ_ACQUIRE)
  873. return 0;
  874. /* Clear the stale IRQ status bits */
  875. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  876. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  877. /* Program the SID's for the trusted VM */
  878. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  879. sde_plane_set_sid(plane, 1);
  880. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 1);
  881. return 0;
  882. }
  883. static void sde_kms_prepare_commit(struct msm_kms *kms,
  884. struct drm_atomic_state *state)
  885. {
  886. struct sde_kms *sde_kms;
  887. struct msm_drm_private *priv;
  888. struct drm_device *dev;
  889. struct drm_encoder *encoder;
  890. struct drm_crtc *crtc;
  891. struct drm_crtc_state *crtc_state;
  892. struct sde_vm_ops *vm_ops;
  893. int i, rc;
  894. if (!kms)
  895. return;
  896. sde_kms = to_sde_kms(kms);
  897. dev = sde_kms->dev;
  898. if (!dev || !dev->dev_private)
  899. return;
  900. priv = dev->dev_private;
  901. SDE_ATRACE_BEGIN("prepare_commit");
  902. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  903. if (rc < 0) {
  904. SDE_ERROR("failed to enable power resources %d\n", rc);
  905. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  906. goto end;
  907. }
  908. if (sde_kms->first_kickoff) {
  909. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  910. sde_kms->first_kickoff = false;
  911. }
  912. for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
  913. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  914. head) {
  915. if (encoder->crtc != crtc)
  916. continue;
  917. if (sde_encoder_prepare_commit(encoder) == -ETIMEDOUT) {
  918. SDE_ERROR("crtc:%d, initiating hw reset\n",
  919. DRMID(crtc));
  920. sde_encoder_needs_hw_reset(encoder);
  921. sde_crtc_set_needs_hw_reset(crtc);
  922. }
  923. }
  924. }
  925. /*
  926. * NOTE: for secure use cases we want to apply the new HW
  927. * configuration only after completing preparation for secure
  928. * transitions prepare below if any transtions is required.
  929. */
  930. sde_kms_prepare_secure_transition(kms, state);
  931. vm_ops = sde_vm_get_ops(sde_kms);
  932. if (!vm_ops)
  933. goto end_vm;
  934. if (vm_ops->vm_prepare_commit)
  935. vm_ops->vm_prepare_commit(sde_kms, state);
  936. end_vm:
  937. _sde_kms_drm_check_dpms(state, DRM_PANEL_EARLY_EVENT_BLANK);
  938. end:
  939. SDE_ATRACE_END("prepare_commit");
  940. }
  941. static void sde_kms_commit(struct msm_kms *kms,
  942. struct drm_atomic_state *old_state)
  943. {
  944. struct sde_kms *sde_kms;
  945. struct drm_crtc *crtc;
  946. struct drm_crtc_state *old_crtc_state;
  947. int i;
  948. if (!kms || !old_state)
  949. return;
  950. sde_kms = to_sde_kms(kms);
  951. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  952. SDE_ERROR("power resource is not enabled\n");
  953. return;
  954. }
  955. SDE_ATRACE_BEGIN("sde_kms_commit");
  956. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  957. if (crtc->state->active) {
  958. SDE_EVT32(DRMID(crtc), old_state);
  959. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  960. }
  961. }
  962. SDE_ATRACE_END("sde_kms_commit");
  963. }
  964. static void _sde_kms_free_splash_display_data(struct sde_kms *sde_kms,
  965. struct sde_splash_display *splash_display)
  966. {
  967. if (!sde_kms || !splash_display ||
  968. !sde_kms->splash_data.num_splash_displays)
  969. return;
  970. if (sde_kms->splash_data.num_splash_regions)
  971. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  972. sde_kms->splash_data.num_splash_displays--;
  973. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  974. sde_kms->splash_data.num_splash_displays);
  975. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  976. }
  977. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  978. struct drm_crtc *crtc)
  979. {
  980. struct msm_drm_private *priv;
  981. struct sde_splash_display *splash_display;
  982. int i;
  983. if (!sde_kms || !crtc)
  984. return;
  985. priv = sde_kms->dev->dev_private;
  986. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  987. return;
  988. SDE_EVT32(DRMID(crtc), crtc->state->active,
  989. sde_kms->splash_data.num_splash_displays);
  990. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  991. splash_display = &sde_kms->splash_data.splash_display[i];
  992. if (splash_display->encoder &&
  993. crtc == splash_display->encoder->crtc)
  994. break;
  995. }
  996. if (i >= MAX_DSI_DISPLAYS)
  997. return;
  998. if (splash_display->cont_splash_enabled) {
  999. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  1000. splash_display, false);
  1001. _sde_kms_free_splash_display_data(sde_kms, splash_display);
  1002. }
  1003. /* remove the votes if all displays are done with splash */
  1004. if (!sde_kms->splash_data.num_splash_displays) {
  1005. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  1006. sde_power_data_bus_set_quota(&priv->phandle, i,
  1007. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  1008. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  1009. pm_runtime_put_sync(sde_kms->dev->dev);
  1010. }
  1011. }
  1012. void _sde_kms_program_mode_info(struct sde_kms *sde_kms)
  1013. {
  1014. struct drm_encoder *encoder;
  1015. struct drm_crtc *crtc;
  1016. struct drm_connector *connector;
  1017. struct drm_connector_list_iter conn_iter;
  1018. struct dsi_display *dsi_display;
  1019. struct drm_display_mode *drm_mode;
  1020. int i;
  1021. struct drm_device *dev;
  1022. u32 mode_index = 0;
  1023. if (!sde_kms->dev || !sde_kms->hw_mdp)
  1024. return;
  1025. dev = sde_kms->dev;
  1026. sde_kms->hw_mdp->ops.clear_mode_index(sde_kms->hw_mdp);
  1027. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  1028. dsi_display = (struct dsi_display *)sde_kms->dsi_displays[i];
  1029. if (dsi_display->bridge->base.encoder) {
  1030. encoder = dsi_display->bridge->base.encoder;
  1031. crtc = encoder->crtc;
  1032. if (!crtc->state->active)
  1033. continue;
  1034. mutex_lock(&dev->mode_config.mutex);
  1035. drm_connector_list_iter_begin(dev, &conn_iter);
  1036. drm_for_each_connector_iter(connector, &conn_iter) {
  1037. if (connector->encoder_ids[0]
  1038. == encoder->base.id)
  1039. break;
  1040. }
  1041. drm_connector_list_iter_end(&conn_iter);
  1042. mutex_unlock(&dev->mode_config.mutex);
  1043. list_for_each_entry(drm_mode, &connector->modes, head) {
  1044. if (drm_mode_equal(
  1045. &crtc->state->mode, drm_mode))
  1046. break;
  1047. mode_index++;
  1048. }
  1049. sde_kms->hw_mdp->ops.set_mode_index(
  1050. sde_kms->hw_mdp, i, mode_index);
  1051. SDE_DEBUG("crtc:%d, display_idx:%d, mode_index:%d\n",
  1052. DRMID(crtc), i, mode_index);
  1053. }
  1054. }
  1055. }
  1056. int sde_kms_vm_trusted_post_commit(struct sde_kms *sde_kms,
  1057. struct drm_atomic_state *state)
  1058. {
  1059. struct sde_vm_ops *vm_ops;
  1060. struct drm_device *ddev;
  1061. struct drm_crtc *crtc;
  1062. struct drm_plane *plane;
  1063. struct drm_encoder *encoder;
  1064. struct sde_crtc_state *cstate;
  1065. struct drm_crtc_state *new_cstate;
  1066. enum sde_crtc_vm_req vm_req;
  1067. int rc = 0;
  1068. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1069. return -EINVAL;
  1070. vm_ops = sde_vm_get_ops(sde_kms);
  1071. ddev = sde_kms->dev;
  1072. crtc = state->crtcs[0].ptr;
  1073. new_cstate = state->crtcs[0].new_state;
  1074. cstate = to_sde_crtc_state(new_cstate);
  1075. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1076. if (vm_req != VM_REQ_RELEASE)
  1077. return rc;
  1078. if (!new_cstate->active && !new_cstate->active_changed)
  1079. return rc;
  1080. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1081. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1082. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  1083. sde_encoder_irq_control(encoder, false);
  1084. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  1085. sde_plane_set_sid(plane, 0);
  1086. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 0);
  1087. sde_vm_lock(sde_kms);
  1088. if (vm_ops->vm_release)
  1089. rc = vm_ops->vm_release(sde_kms);
  1090. sde_vm_unlock(sde_kms);
  1091. return rc;
  1092. }
  1093. int sde_kms_vm_pre_release(struct sde_kms *sde_kms,
  1094. struct drm_atomic_state *state)
  1095. {
  1096. struct drm_device *ddev;
  1097. struct drm_crtc *crtc;
  1098. struct drm_encoder *encoder;
  1099. struct drm_connector *connector;
  1100. int rc = 0;
  1101. ddev = sde_kms->dev;
  1102. crtc = state->crtcs[0].ptr;
  1103. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1104. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1105. /* disable ESD work */
  1106. list_for_each_entry(connector,
  1107. &ddev->mode_config.connector_list, head) {
  1108. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  1109. sde_connector_schedule_status_work(connector, false);
  1110. }
  1111. /* disable SDE irq's */
  1112. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  1113. sde_encoder_irq_control(encoder, false);
  1114. /* disable IRQ line */
  1115. sde_irq_update(&sde_kms->base, false);
  1116. /* disable vblank events */
  1117. drm_crtc_vblank_off(crtc);
  1118. return rc;
  1119. }
  1120. int sde_kms_vm_primary_post_commit(struct sde_kms *sde_kms,
  1121. struct drm_atomic_state *state)
  1122. {
  1123. struct sde_vm_ops *vm_ops;
  1124. struct sde_crtc_state *cstate;
  1125. struct drm_crtc *crtc;
  1126. enum sde_crtc_vm_req vm_req;
  1127. int rc = 0;
  1128. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1129. return -EINVAL;
  1130. vm_ops = sde_vm_get_ops(sde_kms);
  1131. crtc = state->crtcs[0].ptr;
  1132. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  1133. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1134. if (vm_req != VM_REQ_RELEASE)
  1135. goto exit;
  1136. /* handle SDE pre-release */
  1137. sde_kms_vm_pre_release(sde_kms, state);
  1138. /* properly handoff color processing features */
  1139. sde_cp_crtc_vm_primary_handoff(crtc);
  1140. /* program the current drm mode info to scratch reg */
  1141. _sde_kms_program_mode_info(sde_kms);
  1142. /* handle non-SDE clients pre-release */
  1143. if (vm_ops->vm_client_pre_release) {
  1144. rc = vm_ops->vm_client_pre_release(sde_kms);
  1145. if (rc) {
  1146. SDE_ERROR("sde vm pre_release failed, rc=%d\n", rc);
  1147. goto exit;
  1148. }
  1149. }
  1150. sde_vm_lock(sde_kms);
  1151. /* release HW */
  1152. if (vm_ops->vm_release) {
  1153. rc = vm_ops->vm_release(sde_kms);
  1154. if (rc)
  1155. SDE_ERROR("sde vm assign failed, rc=%d\n", rc);
  1156. }
  1157. sde_vm_unlock(sde_kms);
  1158. exit:
  1159. return rc;
  1160. }
  1161. static void sde_kms_complete_commit(struct msm_kms *kms,
  1162. struct drm_atomic_state *old_state)
  1163. {
  1164. struct sde_kms *sde_kms;
  1165. struct msm_drm_private *priv;
  1166. struct drm_crtc *crtc;
  1167. struct drm_crtc_state *old_crtc_state;
  1168. struct drm_connector *connector;
  1169. struct drm_connector_state *old_conn_state;
  1170. struct msm_display_conn_params params;
  1171. struct sde_vm_ops *vm_ops;
  1172. int i, rc = 0;
  1173. if (!kms || !old_state)
  1174. return;
  1175. sde_kms = to_sde_kms(kms);
  1176. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  1177. return;
  1178. priv = sde_kms->dev->dev_private;
  1179. if (sde_kms_power_resource_is_enabled(sde_kms->dev) < 0) {
  1180. SDE_ERROR("power resource is not enabled\n");
  1181. return;
  1182. }
  1183. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  1184. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1185. sde_crtc_complete_commit(crtc, old_crtc_state);
  1186. /* complete secure transitions if any */
  1187. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  1188. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  1189. }
  1190. for_each_old_connector_in_state(old_state, connector,
  1191. old_conn_state, i) {
  1192. struct sde_connector *c_conn;
  1193. c_conn = to_sde_connector(connector);
  1194. if (!c_conn->ops.post_kickoff)
  1195. continue;
  1196. memset(&params, 0, sizeof(params));
  1197. sde_connector_complete_qsync_commit(connector, &params);
  1198. rc = c_conn->ops.post_kickoff(connector, &params);
  1199. if (rc) {
  1200. pr_err("Connector Post kickoff failed rc=%d\n",
  1201. rc);
  1202. }
  1203. }
  1204. vm_ops = sde_vm_get_ops(sde_kms);
  1205. if (vm_ops && vm_ops->vm_post_commit) {
  1206. rc = vm_ops->vm_post_commit(sde_kms, old_state);
  1207. if (rc)
  1208. SDE_ERROR("vm post commit failed, rc = %d\n",
  1209. rc);
  1210. }
  1211. _sde_kms_drm_check_dpms(old_state, DRM_PANEL_EVENT_BLANK);
  1212. pm_runtime_put_sync(sde_kms->dev->dev);
  1213. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  1214. _sde_kms_release_splash_resource(sde_kms, crtc);
  1215. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  1216. SDE_ATRACE_END("sde_kms_complete_commit");
  1217. }
  1218. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  1219. struct drm_crtc *crtc)
  1220. {
  1221. struct drm_encoder *encoder;
  1222. struct drm_device *dev;
  1223. int ret;
  1224. bool cwb_disabling;
  1225. if (!kms || !crtc || !crtc->state) {
  1226. SDE_ERROR("invalid params\n");
  1227. return;
  1228. }
  1229. dev = crtc->dev;
  1230. if (!crtc->state->enable) {
  1231. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  1232. return;
  1233. }
  1234. if (!crtc->state->active) {
  1235. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  1236. return;
  1237. }
  1238. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  1239. SDE_ERROR("power resource is not enabled\n");
  1240. return;
  1241. }
  1242. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  1243. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1244. cwb_disabling = false;
  1245. if (encoder->crtc != crtc) {
  1246. cwb_disabling = sde_encoder_is_cwb_disabling(encoder,
  1247. crtc);
  1248. if (!cwb_disabling)
  1249. continue;
  1250. }
  1251. /*
  1252. * Wait for post-flush if necessary to delay before
  1253. * plane_cleanup. For example, wait for vsync in case of video
  1254. * mode panels. This may be a no-op for command mode panels.
  1255. */
  1256. SDE_EVT32_VERBOSE(DRMID(crtc));
  1257. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
  1258. if (ret && ret != -EWOULDBLOCK) {
  1259. SDE_ERROR("wait for commit done returned %d\n", ret);
  1260. sde_crtc_request_frame_reset(crtc);
  1261. break;
  1262. }
  1263. sde_crtc_complete_flip(crtc, NULL);
  1264. if (cwb_disabling)
  1265. sde_encoder_virt_reset(encoder);
  1266. }
  1267. sde_crtc_static_cache_read_kickoff(crtc);
  1268. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  1269. }
  1270. static void sde_kms_prepare_fence(struct msm_kms *kms,
  1271. struct drm_atomic_state *old_state)
  1272. {
  1273. struct drm_crtc *crtc;
  1274. struct drm_crtc_state *old_crtc_state;
  1275. int i, rc;
  1276. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  1277. SDE_ERROR("invalid argument(s)\n");
  1278. return;
  1279. }
  1280. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  1281. retry:
  1282. /* attempt to acquire ww mutex for connection */
  1283. rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
  1284. old_state->acquire_ctx);
  1285. if (rc == -EDEADLK) {
  1286. drm_modeset_backoff(old_state->acquire_ctx);
  1287. goto retry;
  1288. }
  1289. /* old_state actually contains updated crtc pointers */
  1290. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1291. if (crtc->state->active || crtc->state->active_changed)
  1292. sde_crtc_prepare_commit(crtc, old_crtc_state);
  1293. }
  1294. SDE_ATRACE_END("sde_kms_prepare_fence");
  1295. }
  1296. /**
  1297. * _sde_kms_get_displays - query for underlying display handles and cache them
  1298. * @sde_kms: Pointer to sde kms structure
  1299. * Returns: Zero on success
  1300. */
  1301. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  1302. {
  1303. int rc = -ENOMEM;
  1304. if (!sde_kms) {
  1305. SDE_ERROR("invalid sde kms\n");
  1306. return -EINVAL;
  1307. }
  1308. /* dsi */
  1309. sde_kms->dsi_displays = NULL;
  1310. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  1311. if (sde_kms->dsi_display_count) {
  1312. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  1313. sizeof(void *),
  1314. GFP_KERNEL);
  1315. if (!sde_kms->dsi_displays) {
  1316. SDE_ERROR("failed to allocate dsi displays\n");
  1317. goto exit_deinit_dsi;
  1318. }
  1319. sde_kms->dsi_display_count =
  1320. dsi_display_get_active_displays(sde_kms->dsi_displays,
  1321. sde_kms->dsi_display_count);
  1322. }
  1323. /* wb */
  1324. sde_kms->wb_displays = NULL;
  1325. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  1326. if (sde_kms->wb_display_count) {
  1327. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  1328. sizeof(void *),
  1329. GFP_KERNEL);
  1330. if (!sde_kms->wb_displays) {
  1331. SDE_ERROR("failed to allocate wb displays\n");
  1332. goto exit_deinit_wb;
  1333. }
  1334. sde_kms->wb_display_count =
  1335. wb_display_get_displays(sde_kms->wb_displays,
  1336. sde_kms->wb_display_count);
  1337. }
  1338. /* dp */
  1339. sde_kms->dp_displays = NULL;
  1340. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  1341. if (sde_kms->dp_display_count) {
  1342. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  1343. sizeof(void *), GFP_KERNEL);
  1344. if (!sde_kms->dp_displays) {
  1345. SDE_ERROR("failed to allocate dp displays\n");
  1346. goto exit_deinit_dp;
  1347. }
  1348. sde_kms->dp_display_count =
  1349. dp_display_get_displays(sde_kms->dp_displays,
  1350. sde_kms->dp_display_count);
  1351. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  1352. }
  1353. return 0;
  1354. exit_deinit_dp:
  1355. kfree(sde_kms->dp_displays);
  1356. sde_kms->dp_stream_count = 0;
  1357. sde_kms->dp_display_count = 0;
  1358. sde_kms->dp_displays = NULL;
  1359. exit_deinit_wb:
  1360. kfree(sde_kms->wb_displays);
  1361. sde_kms->wb_display_count = 0;
  1362. sde_kms->wb_displays = NULL;
  1363. exit_deinit_dsi:
  1364. kfree(sde_kms->dsi_displays);
  1365. sde_kms->dsi_display_count = 0;
  1366. sde_kms->dsi_displays = NULL;
  1367. return rc;
  1368. }
  1369. /**
  1370. * _sde_kms_release_displays - release cache of underlying display handles
  1371. * @sde_kms: Pointer to sde kms structure
  1372. */
  1373. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  1374. {
  1375. if (!sde_kms) {
  1376. SDE_ERROR("invalid sde kms\n");
  1377. return;
  1378. }
  1379. kfree(sde_kms->wb_displays);
  1380. sde_kms->wb_displays = NULL;
  1381. sde_kms->wb_display_count = 0;
  1382. kfree(sde_kms->dsi_displays);
  1383. sde_kms->dsi_displays = NULL;
  1384. sde_kms->dsi_display_count = 0;
  1385. }
  1386. /**
  1387. * _sde_kms_setup_displays - create encoders, bridges and connectors
  1388. * for underlying displays
  1389. * @dev: Pointer to drm device structure
  1390. * @priv: Pointer to private drm device data
  1391. * @sde_kms: Pointer to sde kms structure
  1392. * Returns: Zero on success
  1393. */
  1394. static int _sde_kms_setup_displays(struct drm_device *dev,
  1395. struct msm_drm_private *priv,
  1396. struct sde_kms *sde_kms)
  1397. {
  1398. static const struct sde_connector_ops dsi_ops = {
  1399. .set_info_blob = dsi_conn_set_info_blob,
  1400. .detect = dsi_conn_detect,
  1401. .get_modes = dsi_connector_get_modes,
  1402. .pre_destroy = dsi_connector_put_modes,
  1403. .mode_valid = dsi_conn_mode_valid,
  1404. .get_info = dsi_display_get_info,
  1405. .set_backlight = dsi_display_set_backlight,
  1406. .soft_reset = dsi_display_soft_reset,
  1407. .pre_kickoff = dsi_conn_pre_kickoff,
  1408. .clk_ctrl = dsi_display_clk_ctrl,
  1409. .set_power = dsi_display_set_power,
  1410. .get_mode_info = dsi_conn_get_mode_info,
  1411. .get_dst_format = dsi_display_get_dst_format,
  1412. .post_kickoff = dsi_conn_post_kickoff,
  1413. .check_status = dsi_display_check_status,
  1414. .enable_event = dsi_conn_enable_event,
  1415. .cmd_transfer = dsi_display_cmd_transfer,
  1416. .cont_splash_config = dsi_display_cont_splash_config,
  1417. .cont_splash_res_disable = dsi_display_cont_splash_res_disable,
  1418. .get_panel_vfp = dsi_display_get_panel_vfp,
  1419. .get_default_lms = dsi_display_get_default_lms,
  1420. .cmd_receive = dsi_display_cmd_receive,
  1421. .install_properties = NULL,
  1422. .set_allowed_mode_switch = dsi_conn_set_allowed_mode_switch,
  1423. };
  1424. static const struct sde_connector_ops wb_ops = {
  1425. .post_init = sde_wb_connector_post_init,
  1426. .set_info_blob = sde_wb_connector_set_info_blob,
  1427. .detect = sde_wb_connector_detect,
  1428. .get_modes = sde_wb_connector_get_modes,
  1429. .set_property = sde_wb_connector_set_property,
  1430. .get_info = sde_wb_get_info,
  1431. .soft_reset = NULL,
  1432. .get_mode_info = sde_wb_get_mode_info,
  1433. .get_dst_format = NULL,
  1434. .check_status = NULL,
  1435. .cmd_transfer = NULL,
  1436. .cont_splash_config = NULL,
  1437. .cont_splash_res_disable = NULL,
  1438. .get_panel_vfp = NULL,
  1439. .cmd_receive = NULL,
  1440. .install_properties = NULL,
  1441. .set_allowed_mode_switch = NULL,
  1442. };
  1443. static const struct sde_connector_ops dp_ops = {
  1444. .post_init = dp_connector_post_init,
  1445. .detect = dp_connector_detect,
  1446. .get_modes = dp_connector_get_modes,
  1447. .atomic_check = dp_connector_atomic_check,
  1448. .mode_valid = dp_connector_mode_valid,
  1449. .get_info = dp_connector_get_info,
  1450. .get_mode_info = dp_connector_get_mode_info,
  1451. .post_open = dp_connector_post_open,
  1452. .check_status = NULL,
  1453. .set_colorspace = dp_connector_set_colorspace,
  1454. .config_hdr = dp_connector_config_hdr,
  1455. .cmd_transfer = NULL,
  1456. .cont_splash_config = NULL,
  1457. .cont_splash_res_disable = NULL,
  1458. .get_panel_vfp = NULL,
  1459. .update_pps = dp_connector_update_pps,
  1460. .cmd_receive = NULL,
  1461. .install_properties = dp_connector_install_properties,
  1462. .set_allowed_mode_switch = NULL,
  1463. };
  1464. struct msm_display_info info;
  1465. struct drm_encoder *encoder;
  1466. void *display, *connector;
  1467. int i, max_encoders;
  1468. int rc = 0;
  1469. u32 dsc_count = 0, mixer_count = 0;
  1470. u32 max_dp_dsc_count, max_dp_mixer_count;
  1471. if (!dev || !priv || !sde_kms) {
  1472. SDE_ERROR("invalid argument(s)\n");
  1473. return -EINVAL;
  1474. }
  1475. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1476. sde_kms->dp_display_count +
  1477. sde_kms->dp_stream_count;
  1478. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1479. max_encoders = ARRAY_SIZE(priv->encoders);
  1480. SDE_ERROR("capping number of displays to %d", max_encoders);
  1481. }
  1482. /* wb */
  1483. for (i = 0; i < sde_kms->wb_display_count &&
  1484. priv->num_encoders < max_encoders; ++i) {
  1485. display = sde_kms->wb_displays[i];
  1486. encoder = NULL;
  1487. memset(&info, 0x0, sizeof(info));
  1488. rc = sde_wb_get_info(NULL, &info, display);
  1489. if (rc) {
  1490. SDE_ERROR("wb get_info %d failed\n", i);
  1491. continue;
  1492. }
  1493. encoder = sde_encoder_init(dev, &info);
  1494. if (IS_ERR_OR_NULL(encoder)) {
  1495. SDE_ERROR("encoder init failed for wb %d\n", i);
  1496. continue;
  1497. }
  1498. rc = sde_wb_drm_init(display, encoder);
  1499. if (rc) {
  1500. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1501. sde_encoder_destroy(encoder);
  1502. continue;
  1503. }
  1504. connector = sde_connector_init(dev,
  1505. encoder,
  1506. 0,
  1507. display,
  1508. &wb_ops,
  1509. DRM_CONNECTOR_POLL_HPD,
  1510. DRM_MODE_CONNECTOR_VIRTUAL);
  1511. if (connector) {
  1512. priv->encoders[priv->num_encoders++] = encoder;
  1513. priv->connectors[priv->num_connectors++] = connector;
  1514. } else {
  1515. SDE_ERROR("wb %d connector init failed\n", i);
  1516. sde_wb_drm_deinit(display);
  1517. sde_encoder_destroy(encoder);
  1518. }
  1519. }
  1520. /* dsi */
  1521. for (i = 0; i < sde_kms->dsi_display_count &&
  1522. priv->num_encoders < max_encoders; ++i) {
  1523. display = sde_kms->dsi_displays[i];
  1524. encoder = NULL;
  1525. memset(&info, 0x0, sizeof(info));
  1526. rc = dsi_display_get_info(NULL, &info, display);
  1527. if (rc) {
  1528. SDE_ERROR("dsi get_info %d failed\n", i);
  1529. continue;
  1530. }
  1531. encoder = sde_encoder_init(dev, &info);
  1532. if (IS_ERR_OR_NULL(encoder)) {
  1533. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1534. continue;
  1535. }
  1536. rc = dsi_display_drm_bridge_init(display, encoder);
  1537. if (rc) {
  1538. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1539. sde_encoder_destroy(encoder);
  1540. continue;
  1541. }
  1542. connector = sde_connector_init(dev,
  1543. encoder,
  1544. dsi_display_get_drm_panel(display),
  1545. display,
  1546. &dsi_ops,
  1547. DRM_CONNECTOR_POLL_HPD,
  1548. DRM_MODE_CONNECTOR_DSI);
  1549. if (connector) {
  1550. priv->encoders[priv->num_encoders++] = encoder;
  1551. priv->connectors[priv->num_connectors++] = connector;
  1552. } else {
  1553. SDE_ERROR("dsi %d connector init failed\n", i);
  1554. dsi_display_drm_bridge_deinit(display);
  1555. sde_encoder_destroy(encoder);
  1556. continue;
  1557. }
  1558. rc = dsi_display_drm_ext_bridge_init(display,
  1559. encoder, connector);
  1560. if (rc) {
  1561. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1562. dsi_display_drm_bridge_deinit(display);
  1563. sde_connector_destroy(connector);
  1564. sde_encoder_destroy(encoder);
  1565. }
  1566. dsc_count += info.dsc_count;
  1567. mixer_count += info.lm_count;
  1568. }
  1569. max_dp_mixer_count = sde_kms->catalog->mixer_count > mixer_count ?
  1570. sde_kms->catalog->mixer_count - mixer_count : 0;
  1571. max_dp_dsc_count = sde_kms->catalog->dsc_count > dsc_count ?
  1572. sde_kms->catalog->dsc_count - dsc_count : 0;
  1573. /* dp */
  1574. for (i = 0; i < sde_kms->dp_display_count &&
  1575. priv->num_encoders < max_encoders; ++i) {
  1576. int idx;
  1577. display = sde_kms->dp_displays[i];
  1578. encoder = NULL;
  1579. memset(&info, 0x0, sizeof(info));
  1580. rc = dp_connector_get_info(NULL, &info, display);
  1581. if (rc) {
  1582. SDE_ERROR("dp get_info %d failed\n", i);
  1583. continue;
  1584. }
  1585. encoder = sde_encoder_init(dev, &info);
  1586. if (IS_ERR_OR_NULL(encoder)) {
  1587. SDE_ERROR("dp encoder init failed %d\n", i);
  1588. continue;
  1589. }
  1590. rc = dp_drm_bridge_init(display, encoder,
  1591. max_dp_mixer_count, max_dp_dsc_count);
  1592. if (rc) {
  1593. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1594. sde_encoder_destroy(encoder);
  1595. continue;
  1596. }
  1597. connector = sde_connector_init(dev,
  1598. encoder,
  1599. NULL,
  1600. display,
  1601. &dp_ops,
  1602. DRM_CONNECTOR_POLL_HPD,
  1603. DRM_MODE_CONNECTOR_DisplayPort);
  1604. if (connector) {
  1605. priv->encoders[priv->num_encoders++] = encoder;
  1606. priv->connectors[priv->num_connectors++] = connector;
  1607. } else {
  1608. SDE_ERROR("dp %d connector init failed\n", i);
  1609. dp_drm_bridge_deinit(display);
  1610. sde_encoder_destroy(encoder);
  1611. }
  1612. /* update display cap to MST_MODE for DP MST encoders */
  1613. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1614. for (idx = 0; idx < sde_kms->dp_stream_count &&
  1615. priv->num_encoders < max_encoders; idx++) {
  1616. info.h_tile_instance[0] = idx;
  1617. encoder = sde_encoder_init(dev, &info);
  1618. if (IS_ERR_OR_NULL(encoder)) {
  1619. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1620. continue;
  1621. }
  1622. rc = dp_mst_drm_bridge_init(display, encoder);
  1623. if (rc) {
  1624. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1625. i, rc);
  1626. sde_encoder_destroy(encoder);
  1627. continue;
  1628. }
  1629. priv->encoders[priv->num_encoders++] = encoder;
  1630. }
  1631. }
  1632. return 0;
  1633. }
  1634. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1635. {
  1636. struct msm_drm_private *priv;
  1637. int i;
  1638. if (!sde_kms) {
  1639. SDE_ERROR("invalid sde_kms\n");
  1640. return;
  1641. } else if (!sde_kms->dev) {
  1642. SDE_ERROR("invalid dev\n");
  1643. return;
  1644. } else if (!sde_kms->dev->dev_private) {
  1645. SDE_ERROR("invalid dev_private\n");
  1646. return;
  1647. }
  1648. priv = sde_kms->dev->dev_private;
  1649. for (i = 0; i < priv->num_crtcs; i++)
  1650. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1651. priv->num_crtcs = 0;
  1652. for (i = 0; i < priv->num_planes; i++)
  1653. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1654. priv->num_planes = 0;
  1655. for (i = 0; i < priv->num_connectors; i++)
  1656. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1657. priv->num_connectors = 0;
  1658. for (i = 0; i < priv->num_encoders; i++)
  1659. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1660. priv->num_encoders = 0;
  1661. _sde_kms_release_displays(sde_kms);
  1662. }
  1663. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1664. {
  1665. struct drm_device *dev;
  1666. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1667. struct drm_crtc *crtc;
  1668. struct msm_drm_private *priv;
  1669. struct sde_mdss_cfg *catalog;
  1670. int primary_planes_idx = 0, i, ret;
  1671. int max_crtc_count;
  1672. u32 sspp_id[MAX_PLANES];
  1673. u32 master_plane_id[MAX_PLANES];
  1674. u32 num_virt_planes = 0;
  1675. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1676. SDE_ERROR("invalid sde_kms\n");
  1677. return -EINVAL;
  1678. }
  1679. dev = sde_kms->dev;
  1680. priv = dev->dev_private;
  1681. catalog = sde_kms->catalog;
  1682. ret = sde_core_irq_domain_add(sde_kms);
  1683. if (ret)
  1684. goto fail_irq;
  1685. /*
  1686. * Query for underlying display drivers, and create connectors,
  1687. * bridges and encoders for them.
  1688. */
  1689. if (!_sde_kms_get_displays(sde_kms))
  1690. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1691. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1692. /* Create the planes */
  1693. for (i = 0; i < catalog->sspp_count; i++) {
  1694. bool primary = true;
  1695. if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
  1696. || primary_planes_idx >= max_crtc_count)
  1697. primary = false;
  1698. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1699. (1UL << max_crtc_count) - 1, 0);
  1700. if (IS_ERR(plane)) {
  1701. SDE_ERROR("sde_plane_init failed\n");
  1702. ret = PTR_ERR(plane);
  1703. goto fail;
  1704. }
  1705. priv->planes[priv->num_planes++] = plane;
  1706. if (primary)
  1707. primary_planes[primary_planes_idx++] = plane;
  1708. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1709. sde_is_custom_client()) {
  1710. int priority =
  1711. catalog->sspp[i].sblk->smart_dma_priority;
  1712. sspp_id[priority - 1] = catalog->sspp[i].id;
  1713. master_plane_id[priority - 1] = plane->base.id;
  1714. num_virt_planes++;
  1715. }
  1716. }
  1717. /* Initialize smart DMA virtual planes */
  1718. for (i = 0; i < num_virt_planes; i++) {
  1719. plane = sde_plane_init(dev, sspp_id[i], false,
  1720. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1721. if (IS_ERR(plane)) {
  1722. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1723. ret = PTR_ERR(plane);
  1724. goto fail;
  1725. }
  1726. priv->planes[priv->num_planes++] = plane;
  1727. }
  1728. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1729. /* Create one CRTC per encoder */
  1730. for (i = 0; i < max_crtc_count; i++) {
  1731. crtc = sde_crtc_init(dev, primary_planes[i]);
  1732. if (IS_ERR(crtc)) {
  1733. ret = PTR_ERR(crtc);
  1734. goto fail;
  1735. }
  1736. priv->crtcs[priv->num_crtcs++] = crtc;
  1737. }
  1738. if (sde_is_custom_client()) {
  1739. /* All CRTCs are compatible with all planes */
  1740. for (i = 0; i < priv->num_planes; i++)
  1741. priv->planes[i]->possible_crtcs =
  1742. (1 << priv->num_crtcs) - 1;
  1743. }
  1744. /* All CRTCs are compatible with all encoders */
  1745. for (i = 0; i < priv->num_encoders; i++)
  1746. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1747. return 0;
  1748. fail:
  1749. _sde_kms_drm_obj_destroy(sde_kms);
  1750. fail_irq:
  1751. sde_core_irq_domain_fini(sde_kms);
  1752. return ret;
  1753. }
  1754. /**
  1755. * sde_kms_timeline_status - provides current timeline status
  1756. * This API should be called without mode config lock.
  1757. * @dev: Pointer to drm device
  1758. */
  1759. void sde_kms_timeline_status(struct drm_device *dev)
  1760. {
  1761. struct drm_crtc *crtc;
  1762. struct drm_connector *conn;
  1763. struct drm_connector_list_iter conn_iter;
  1764. if (!dev) {
  1765. SDE_ERROR("invalid drm device node\n");
  1766. return;
  1767. }
  1768. drm_for_each_crtc(crtc, dev)
  1769. sde_crtc_timeline_status(crtc);
  1770. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1771. /*
  1772. *Probably locked from last close dumping status anyway
  1773. */
  1774. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1775. drm_connector_list_iter_begin(dev, &conn_iter);
  1776. drm_for_each_connector_iter(conn, &conn_iter)
  1777. sde_conn_timeline_status(conn);
  1778. drm_connector_list_iter_end(&conn_iter);
  1779. return;
  1780. }
  1781. mutex_lock(&dev->mode_config.mutex);
  1782. drm_connector_list_iter_begin(dev, &conn_iter);
  1783. drm_for_each_connector_iter(conn, &conn_iter)
  1784. sde_conn_timeline_status(conn);
  1785. drm_connector_list_iter_end(&conn_iter);
  1786. mutex_unlock(&dev->mode_config.mutex);
  1787. }
  1788. static int sde_kms_postinit(struct msm_kms *kms)
  1789. {
  1790. struct sde_kms *sde_kms = to_sde_kms(kms);
  1791. struct drm_device *dev;
  1792. struct drm_crtc *crtc;
  1793. int rc;
  1794. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1795. SDE_ERROR("invalid sde_kms\n");
  1796. return -EINVAL;
  1797. }
  1798. dev = sde_kms->dev;
  1799. rc = _sde_debugfs_init(sde_kms);
  1800. if (rc)
  1801. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1802. drm_for_each_crtc(crtc, dev)
  1803. sde_crtc_post_init(dev, crtc);
  1804. return rc;
  1805. }
  1806. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1807. struct drm_encoder *encoder)
  1808. {
  1809. return rate;
  1810. }
  1811. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1812. struct platform_device *pdev)
  1813. {
  1814. struct drm_device *dev;
  1815. struct msm_drm_private *priv;
  1816. struct sde_vm_ops *vm_ops;
  1817. int i;
  1818. if (!sde_kms || !pdev)
  1819. return;
  1820. dev = sde_kms->dev;
  1821. if (!dev)
  1822. return;
  1823. priv = dev->dev_private;
  1824. if (!priv)
  1825. return;
  1826. if (sde_kms->genpd_init) {
  1827. sde_kms->genpd_init = false;
  1828. pm_genpd_remove(&sde_kms->genpd);
  1829. of_genpd_del_provider(pdev->dev.of_node);
  1830. }
  1831. vm_ops = sde_vm_get_ops(sde_kms);
  1832. if (vm_ops && vm_ops->vm_deinit)
  1833. vm_ops->vm_deinit(sde_kms, vm_ops);
  1834. if (sde_kms->hw_intr)
  1835. sde_hw_intr_destroy(sde_kms->hw_intr);
  1836. sde_kms->hw_intr = NULL;
  1837. if (sde_kms->power_event)
  1838. sde_power_handle_unregister_event(
  1839. &priv->phandle, sde_kms->power_event);
  1840. _sde_kms_release_displays(sde_kms);
  1841. _sde_kms_unmap_all_splash_regions(sde_kms);
  1842. if (sde_kms->catalog) {
  1843. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1844. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1845. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1846. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1847. }
  1848. }
  1849. if (sde_kms->rm_init)
  1850. sde_rm_destroy(&sde_kms->rm);
  1851. sde_kms->rm_init = false;
  1852. if (sde_kms->catalog)
  1853. sde_hw_catalog_deinit(sde_kms->catalog);
  1854. sde_kms->catalog = NULL;
  1855. if (sde_kms->sid)
  1856. msm_iounmap(pdev, sde_kms->sid);
  1857. sde_kms->sid = NULL;
  1858. if (sde_kms->reg_dma)
  1859. msm_iounmap(pdev, sde_kms->reg_dma);
  1860. sde_kms->reg_dma = NULL;
  1861. if (sde_kms->vbif[VBIF_NRT])
  1862. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1863. sde_kms->vbif[VBIF_NRT] = NULL;
  1864. if (sde_kms->vbif[VBIF_RT])
  1865. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1866. sde_kms->vbif[VBIF_RT] = NULL;
  1867. if (sde_kms->mmio)
  1868. msm_iounmap(pdev, sde_kms->mmio);
  1869. sde_kms->mmio = NULL;
  1870. sde_reg_dma_deinit();
  1871. _sde_kms_mmu_destroy(sde_kms);
  1872. }
  1873. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1874. {
  1875. int i;
  1876. if (!sde_kms)
  1877. return -EINVAL;
  1878. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1879. struct msm_mmu *mmu;
  1880. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1881. if (!aspace)
  1882. continue;
  1883. mmu = sde_kms->aspace[i]->mmu;
  1884. if (secure_only &&
  1885. !aspace->mmu->funcs->is_domain_secure(mmu))
  1886. continue;
  1887. /* cleanup aspace before detaching */
  1888. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1889. SDE_DEBUG("Detaching domain:%d\n", i);
  1890. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1891. ARRAY_SIZE(iommu_ports));
  1892. aspace->domain_attached = false;
  1893. }
  1894. return 0;
  1895. }
  1896. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1897. {
  1898. int i;
  1899. if (!sde_kms)
  1900. return -EINVAL;
  1901. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1902. struct msm_mmu *mmu;
  1903. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1904. if (!aspace)
  1905. continue;
  1906. mmu = sde_kms->aspace[i]->mmu;
  1907. if (secure_only &&
  1908. !aspace->mmu->funcs->is_domain_secure(mmu))
  1909. continue;
  1910. SDE_DEBUG("Attaching domain:%d\n", i);
  1911. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1912. ARRAY_SIZE(iommu_ports));
  1913. aspace->domain_attached = true;
  1914. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1915. }
  1916. return 0;
  1917. }
  1918. static void sde_kms_destroy(struct msm_kms *kms)
  1919. {
  1920. struct sde_kms *sde_kms;
  1921. struct drm_device *dev;
  1922. if (!kms) {
  1923. SDE_ERROR("invalid kms\n");
  1924. return;
  1925. }
  1926. sde_kms = to_sde_kms(kms);
  1927. dev = sde_kms->dev;
  1928. if (!dev || !dev->dev) {
  1929. SDE_ERROR("invalid device\n");
  1930. return;
  1931. }
  1932. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1933. kfree(sde_kms);
  1934. }
  1935. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  1936. struct drm_atomic_state *state)
  1937. {
  1938. struct drm_device *dev = sde_kms->dev;
  1939. struct drm_plane *plane;
  1940. struct drm_plane_state *plane_state;
  1941. struct drm_crtc *crtc;
  1942. struct drm_crtc_state *crtc_state;
  1943. struct drm_connector *conn;
  1944. struct drm_connector_state *conn_state;
  1945. struct drm_connector_list_iter conn_iter;
  1946. int ret = 0;
  1947. drm_for_each_plane(plane, dev) {
  1948. plane_state = drm_atomic_get_plane_state(state, plane);
  1949. if (IS_ERR(plane_state)) {
  1950. ret = PTR_ERR(plane_state);
  1951. SDE_ERROR("error %d getting plane %d state\n",
  1952. ret, DRMID(plane));
  1953. return ret;
  1954. }
  1955. ret = sde_plane_helper_reset_custom_properties(plane,
  1956. plane_state);
  1957. if (ret) {
  1958. SDE_ERROR("error %d resetting plane props %d\n",
  1959. ret, DRMID(plane));
  1960. return ret;
  1961. }
  1962. }
  1963. drm_for_each_crtc(crtc, dev) {
  1964. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  1965. if (IS_ERR(crtc_state)) {
  1966. ret = PTR_ERR(crtc_state);
  1967. SDE_ERROR("error %d getting crtc %d state\n",
  1968. ret, DRMID(crtc));
  1969. return ret;
  1970. }
  1971. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  1972. if (ret) {
  1973. SDE_ERROR("error %d resetting crtc props %d\n",
  1974. ret, DRMID(crtc));
  1975. return ret;
  1976. }
  1977. }
  1978. drm_connector_list_iter_begin(dev, &conn_iter);
  1979. drm_for_each_connector_iter(conn, &conn_iter) {
  1980. conn_state = drm_atomic_get_connector_state(state, conn);
  1981. if (IS_ERR(conn_state)) {
  1982. ret = PTR_ERR(conn_state);
  1983. SDE_ERROR("error %d getting connector %d state\n",
  1984. ret, DRMID(conn));
  1985. return ret;
  1986. }
  1987. ret = sde_connector_helper_reset_custom_properties(conn,
  1988. conn_state);
  1989. if (ret) {
  1990. SDE_ERROR("error %d resetting connector props %d\n",
  1991. ret, DRMID(conn));
  1992. return ret;
  1993. }
  1994. }
  1995. drm_connector_list_iter_end(&conn_iter);
  1996. return ret;
  1997. }
  1998. static void sde_kms_lastclose(struct msm_kms *kms)
  1999. {
  2000. struct sde_kms *sde_kms;
  2001. struct drm_device *dev;
  2002. struct drm_atomic_state *state;
  2003. struct drm_modeset_acquire_ctx ctx;
  2004. int ret;
  2005. if (!kms) {
  2006. SDE_ERROR("invalid argument\n");
  2007. return;
  2008. }
  2009. sde_kms = to_sde_kms(kms);
  2010. dev = sde_kms->dev;
  2011. drm_modeset_acquire_init(&ctx, 0);
  2012. state = drm_atomic_state_alloc(dev);
  2013. if (!state) {
  2014. ret = -ENOMEM;
  2015. goto out_ctx;
  2016. }
  2017. state->acquire_ctx = &ctx;
  2018. retry:
  2019. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2020. if (ret)
  2021. goto out_state;
  2022. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  2023. if (ret)
  2024. goto out_state;
  2025. ret = drm_atomic_commit(state);
  2026. out_state:
  2027. if (ret == -EDEADLK)
  2028. goto backoff;
  2029. drm_atomic_state_put(state);
  2030. out_ctx:
  2031. drm_modeset_drop_locks(&ctx);
  2032. drm_modeset_acquire_fini(&ctx);
  2033. if (ret)
  2034. SDE_ERROR("kms lastclose failed: %d\n", ret);
  2035. return;
  2036. backoff:
  2037. drm_atomic_state_clear(state);
  2038. drm_modeset_backoff(&ctx);
  2039. goto retry;
  2040. }
  2041. static int sde_kms_check_vm_request(struct msm_kms *kms,
  2042. struct drm_atomic_state *state)
  2043. {
  2044. struct sde_kms *sde_kms;
  2045. struct drm_device *dev;
  2046. struct drm_crtc *crtc;
  2047. struct drm_crtc_state *new_cstate, *old_cstate;
  2048. uint32_t i, commit_crtc_cnt = 0, global_crtc_cnt = 0;
  2049. struct drm_crtc *active_crtc = NULL, *global_active_crtc = NULL;
  2050. enum sde_crtc_vm_req old_vm_req = VM_REQ_NONE, new_vm_req = VM_REQ_NONE;
  2051. struct sde_vm_ops *vm_ops;
  2052. bool vm_req_active = false;
  2053. enum sde_crtc_idle_pc_state idle_pc_state;
  2054. int rc = 0;
  2055. if (!kms || !state)
  2056. return -EINVAL;
  2057. sde_kms = to_sde_kms(kms);
  2058. dev = sde_kms->dev;
  2059. vm_ops = sde_vm_get_ops(sde_kms);
  2060. if (!vm_ops)
  2061. return 0;
  2062. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  2063. struct sde_crtc_state *old_state = NULL, *new_state = NULL;
  2064. if (!new_cstate->active && !old_cstate->active)
  2065. continue;
  2066. new_state = to_sde_crtc_state(new_cstate);
  2067. new_vm_req = sde_crtc_get_property(new_state,
  2068. CRTC_PROP_VM_REQ_STATE);
  2069. old_state = to_sde_crtc_state(old_cstate);
  2070. old_vm_req = sde_crtc_get_property(old_state,
  2071. CRTC_PROP_VM_REQ_STATE);
  2072. /**
  2073. * No active request if the transition is from
  2074. * VM_REQ_NONE to VM_REQ_NONE
  2075. */
  2076. if (new_vm_req || old_vm_req)
  2077. vm_req_active = true;
  2078. idle_pc_state = sde_crtc_get_property(new_state,
  2079. CRTC_PROP_IDLE_PC_STATE);
  2080. active_crtc = crtc;
  2081. commit_crtc_cnt++;
  2082. }
  2083. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2084. if (!crtc->state->active)
  2085. continue;
  2086. global_crtc_cnt++;
  2087. global_active_crtc = crtc;
  2088. }
  2089. /* Check for single crtc commits only on valid VM requests */
  2090. if (vm_req_active && active_crtc && global_active_crtc &&
  2091. (commit_crtc_cnt > sde_kms->catalog->max_trusted_vm_displays ||
  2092. global_crtc_cnt > sde_kms->catalog->max_trusted_vm_displays ||
  2093. active_crtc != global_active_crtc)) {
  2094. SDE_ERROR(
  2095. "failed to switch VM due to CRTC concurrencies: MAX_CNT: %d active_cnt: %d global_cnt: %d active_crtc: %d global_crtc: %d\n",
  2096. sde_kms->catalog->max_trusted_vm_displays,
  2097. commit_crtc_cnt, global_crtc_cnt, active_crtc,
  2098. global_active_crtc);
  2099. return -E2BIG;
  2100. }
  2101. if (!vm_req_active)
  2102. return 0;
  2103. /* disable idle-pc before releasing the HW */
  2104. if ((new_vm_req == VM_REQ_RELEASE) &&
  2105. (idle_pc_state == IDLE_PC_ENABLE)) {
  2106. SDE_ERROR("failed to switch VM since idle-pc is enabled\n");
  2107. return -EINVAL;
  2108. }
  2109. sde_vm_lock(sde_kms);
  2110. if (vm_ops->vm_request_valid)
  2111. rc = vm_ops->vm_request_valid(sde_kms, old_vm_req, new_vm_req);
  2112. if (rc)
  2113. SDE_ERROR(
  2114. "failed to complete vm transition request. old_state = %d, new_state = %d, hw_ownership: %d\n",
  2115. old_vm_req, new_vm_req, vm_ops->vm_owns_hw(sde_kms));
  2116. sde_vm_unlock(sde_kms);
  2117. return rc;
  2118. }
  2119. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  2120. struct drm_atomic_state *state)
  2121. {
  2122. struct sde_kms *sde_kms;
  2123. struct drm_device *dev;
  2124. struct drm_crtc *crtc;
  2125. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  2126. struct drm_crtc_state *crtc_state;
  2127. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  2128. bool sec_session = false, global_sec_session = false;
  2129. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  2130. int i;
  2131. if (!kms || !state) {
  2132. return -EINVAL;
  2133. SDE_ERROR("invalid arguments\n");
  2134. }
  2135. sde_kms = to_sde_kms(kms);
  2136. dev = sde_kms->dev;
  2137. /* iterate state object for active secure/non-secure crtc */
  2138. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  2139. if (!crtc_state->active)
  2140. continue;
  2141. active_crtc_cnt++;
  2142. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  2143. &fb_sec, &fb_sec_dir);
  2144. if (fb_sec_dir)
  2145. sec_session = true;
  2146. cur_crtc = crtc;
  2147. }
  2148. /* iterate global list for active and secure/non-secure crtc */
  2149. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2150. if (!crtc->state->active)
  2151. continue;
  2152. global_active_crtc_cnt++;
  2153. /* update only when crtc is not the same as current crtc */
  2154. if (crtc != cur_crtc) {
  2155. fb_ns = fb_sec = fb_sec_dir = 0;
  2156. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  2157. &fb_sec, &fb_sec_dir);
  2158. if (fb_sec_dir)
  2159. global_sec_session = true;
  2160. global_crtc = crtc;
  2161. }
  2162. }
  2163. if (!global_sec_session && !sec_session)
  2164. return 0;
  2165. /*
  2166. * - fail crtc commit, if secure-camera/secure-ui session is
  2167. * in-progress in any other display
  2168. * - fail secure-camera/secure-ui crtc commit, if any other display
  2169. * session is in-progress
  2170. */
  2171. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  2172. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  2173. SDE_ERROR(
  2174. "crtc%d secure check failed global_active:%d active:%d\n",
  2175. cur_crtc ? cur_crtc->base.id : -1,
  2176. global_active_crtc_cnt, active_crtc_cnt);
  2177. return -EPERM;
  2178. /*
  2179. * As only one crtc is allowed during secure session, the crtc
  2180. * in this commit should match with the global crtc
  2181. */
  2182. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  2183. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  2184. cur_crtc->base.id, sec_session,
  2185. global_crtc->base.id, global_sec_session);
  2186. return -EPERM;
  2187. }
  2188. return 0;
  2189. }
  2190. static void sde_kms_vm_res_release(struct msm_kms *kms,
  2191. struct drm_atomic_state *state)
  2192. {
  2193. struct drm_crtc *crtc;
  2194. struct drm_crtc_state *crtc_state;
  2195. struct sde_vm_ops *vm_ops;
  2196. enum sde_crtc_vm_req vm_req;
  2197. struct sde_kms *sde_kms = to_sde_kms(kms);
  2198. int i;
  2199. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  2200. struct sde_crtc_state *cstate;
  2201. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  2202. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  2203. if (vm_req != VM_REQ_ACQUIRE)
  2204. return;
  2205. }
  2206. vm_ops = sde_vm_get_ops(sde_kms);
  2207. if (!vm_ops)
  2208. return;
  2209. sde_vm_lock(sde_kms);
  2210. if (vm_ops->vm_acquire_fail_handler)
  2211. vm_ops->vm_acquire_fail_handler(sde_kms);
  2212. sde_vm_unlock(sde_kms);
  2213. }
  2214. static int sde_kms_atomic_check(struct msm_kms *kms,
  2215. struct drm_atomic_state *state)
  2216. {
  2217. struct sde_kms *sde_kms;
  2218. struct drm_device *dev;
  2219. int ret;
  2220. if (!kms || !state)
  2221. return -EINVAL;
  2222. sde_kms = to_sde_kms(kms);
  2223. dev = sde_kms->dev;
  2224. SDE_ATRACE_BEGIN("atomic_check");
  2225. if (sde_kms_is_suspend_blocked(dev)) {
  2226. SDE_DEBUG("suspended, skip atomic_check\n");
  2227. ret = -EBUSY;
  2228. goto end;
  2229. }
  2230. ret = sde_kms_check_vm_request(kms, state);
  2231. if (ret) {
  2232. SDE_ERROR("vm switch request checks failed\n");
  2233. goto end;
  2234. }
  2235. ret = drm_atomic_helper_check(dev, state);
  2236. if (ret)
  2237. goto vm_clean_up;
  2238. /*
  2239. * Check if any secure transition(moving CRTC between secure and
  2240. * non-secure state and vice-versa) is allowed or not. when moving
  2241. * to secure state, planes with fb_mode set to dir_translated only can
  2242. * be staged on the CRTC, and only one CRTC can be active during
  2243. * Secure state
  2244. */
  2245. ret = sde_kms_check_secure_transition(kms, state);
  2246. if (ret)
  2247. goto vm_clean_up;
  2248. goto end;
  2249. vm_clean_up:
  2250. sde_kms_vm_res_release(kms, state);
  2251. end:
  2252. SDE_ATRACE_END("atomic_check");
  2253. return ret;
  2254. }
  2255. static struct msm_gem_address_space*
  2256. _sde_kms_get_address_space(struct msm_kms *kms,
  2257. unsigned int domain)
  2258. {
  2259. struct sde_kms *sde_kms;
  2260. if (!kms) {
  2261. SDE_ERROR("invalid kms\n");
  2262. return NULL;
  2263. }
  2264. sde_kms = to_sde_kms(kms);
  2265. if (!sde_kms) {
  2266. SDE_ERROR("invalid sde_kms\n");
  2267. return NULL;
  2268. }
  2269. if (domain >= MSM_SMMU_DOMAIN_MAX)
  2270. return NULL;
  2271. return (sde_kms->aspace[domain] &&
  2272. sde_kms->aspace[domain]->domain_attached) ?
  2273. sde_kms->aspace[domain] : NULL;
  2274. }
  2275. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  2276. unsigned int domain)
  2277. {
  2278. struct sde_kms *sde_kms;
  2279. struct msm_gem_address_space *aspace;
  2280. if (!kms) {
  2281. SDE_ERROR("invalid kms\n");
  2282. return NULL;
  2283. }
  2284. sde_kms = to_sde_kms(kms);
  2285. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  2286. SDE_ERROR("invalid params\n");
  2287. return NULL;
  2288. }
  2289. aspace = _sde_kms_get_address_space(kms, domain);
  2290. return (aspace && aspace->domain_attached) ?
  2291. msm_gem_get_aspace_device(aspace) : NULL;
  2292. }
  2293. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  2294. {
  2295. struct drm_device *dev = NULL;
  2296. struct sde_kms *sde_kms = NULL;
  2297. struct drm_connector *connector = NULL;
  2298. struct drm_connector_list_iter conn_iter;
  2299. struct sde_connector *sde_conn = NULL;
  2300. if (!kms) {
  2301. SDE_ERROR("invalid kms\n");
  2302. return;
  2303. }
  2304. sde_kms = to_sde_kms(kms);
  2305. dev = sde_kms->dev;
  2306. if (!dev) {
  2307. SDE_ERROR("invalid device\n");
  2308. return;
  2309. }
  2310. if (!dev->mode_config.poll_enabled)
  2311. return;
  2312. mutex_lock(&dev->mode_config.mutex);
  2313. drm_connector_list_iter_begin(dev, &conn_iter);
  2314. drm_for_each_connector_iter(connector, &conn_iter) {
  2315. /* Only handle HPD capable connectors. */
  2316. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  2317. continue;
  2318. sde_conn = to_sde_connector(connector);
  2319. if (sde_conn->ops.post_open)
  2320. sde_conn->ops.post_open(&sde_conn->base,
  2321. sde_conn->display);
  2322. }
  2323. drm_connector_list_iter_end(&conn_iter);
  2324. mutex_unlock(&dev->mode_config.mutex);
  2325. }
  2326. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  2327. struct sde_splash_display *splash_display,
  2328. struct drm_crtc *crtc)
  2329. {
  2330. struct msm_drm_private *priv;
  2331. struct drm_plane *plane;
  2332. struct sde_splash_mem *splash;
  2333. enum sde_sspp plane_id;
  2334. bool is_virtual;
  2335. int i, j;
  2336. if (!sde_kms || !splash_display || !crtc) {
  2337. SDE_ERROR("invalid input args\n");
  2338. return -EINVAL;
  2339. }
  2340. priv = sde_kms->dev->dev_private;
  2341. for (i = 0; i < priv->num_planes; i++) {
  2342. plane = priv->planes[i];
  2343. plane_id = sde_plane_pipe(plane);
  2344. is_virtual = is_sde_plane_virtual(plane);
  2345. splash = splash_display->splash;
  2346. for (j = 0; j < splash_display->pipe_cnt; j++) {
  2347. if ((plane_id != splash_display->pipes[j].sspp) ||
  2348. (splash_display->pipes[j].is_virtual
  2349. != is_virtual))
  2350. continue;
  2351. if (splash && sde_plane_validate_src_addr(plane,
  2352. splash->splash_buf_base,
  2353. splash->splash_buf_size)) {
  2354. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  2355. plane_id, crtc->base.id);
  2356. }
  2357. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  2358. crtc->base.id, plane_id, is_virtual);
  2359. }
  2360. }
  2361. return 0;
  2362. }
  2363. static struct drm_display_mode *_sde_kms_get_splash_mode(
  2364. struct sde_kms *sde_kms, struct drm_connector *connector,
  2365. u32 display_idx)
  2366. {
  2367. struct drm_display_mode *drm_mode = NULL, *curr_mode = NULL;
  2368. u32 i = 0, mode_index;
  2369. if (sde_kms->splash_data.type == SDE_SPLASH_HANDOFF) {
  2370. /* currently consider modes[0] as the preferred mode */
  2371. curr_mode = list_first_entry(&connector->modes,
  2372. struct drm_display_mode, head);
  2373. } else if (sde_kms->hw_mdp && sde_kms->hw_mdp->ops.get_mode_index) {
  2374. mode_index = sde_kms->hw_mdp->ops.get_mode_index(
  2375. sde_kms->hw_mdp, display_idx);
  2376. list_for_each_entry(drm_mode, &connector->modes, head) {
  2377. if (mode_index == i) {
  2378. curr_mode = drm_mode;
  2379. break;
  2380. }
  2381. i++;
  2382. }
  2383. }
  2384. return curr_mode;
  2385. }
  2386. static int sde_kms_inform_cont_splash_res_disable(struct msm_kms *kms,
  2387. struct dsi_display *dsi_display)
  2388. {
  2389. void *display;
  2390. struct drm_encoder *encoder = NULL;
  2391. struct msm_display_info info;
  2392. struct drm_device *dev;
  2393. struct sde_kms *sde_kms;
  2394. struct drm_connector_list_iter conn_iter;
  2395. struct drm_connector *connector = NULL;
  2396. struct sde_connector *sde_conn = NULL;
  2397. int rc = 0;
  2398. sde_kms = to_sde_kms(kms);
  2399. dev = sde_kms->dev;
  2400. display = dsi_display;
  2401. if (dsi_display) {
  2402. if (dsi_display->bridge->base.encoder) {
  2403. encoder = dsi_display->bridge->base.encoder;
  2404. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2405. }
  2406. memset(&info, 0x0, sizeof(info));
  2407. rc = dsi_display_get_info(NULL, &info, display);
  2408. if (rc) {
  2409. SDE_ERROR("%s: dsi get_info failed: %d\n",
  2410. rc, __func__);
  2411. encoder = NULL;
  2412. }
  2413. }
  2414. drm_connector_list_iter_begin(dev, &conn_iter);
  2415. drm_for_each_connector_iter(connector, &conn_iter) {
  2416. /**
  2417. * Inform cont_splash is disabled to each interface/connector.
  2418. * This is currently supported for DSI interface.
  2419. */
  2420. sde_conn = to_sde_connector(connector);
  2421. if (sde_conn && sde_conn->ops.cont_splash_res_disable) {
  2422. if (!dsi_display || !encoder) {
  2423. sde_conn->ops.cont_splash_res_disable
  2424. (sde_conn->display);
  2425. } else if (connector->encoder_ids[0]
  2426. == encoder->base.id) {
  2427. /**
  2428. * This handles dual DSI
  2429. * configuration where one DSI
  2430. * interface has cont_splash
  2431. * enabled and the other doesn't.
  2432. */
  2433. sde_conn->ops.cont_splash_res_disable
  2434. (sde_conn->display);
  2435. break;
  2436. }
  2437. }
  2438. }
  2439. drm_connector_list_iter_end(&conn_iter);
  2440. return 0;
  2441. }
  2442. static int sde_kms_cont_splash_config(struct msm_kms *kms)
  2443. {
  2444. void *display;
  2445. struct dsi_display *dsi_display;
  2446. struct msm_display_info info;
  2447. struct drm_encoder *encoder = NULL;
  2448. struct drm_crtc *crtc = NULL;
  2449. int i, rc = 0;
  2450. struct drm_display_mode *drm_mode = NULL;
  2451. struct drm_device *dev;
  2452. struct msm_drm_private *priv;
  2453. struct sde_kms *sde_kms;
  2454. struct drm_connector_list_iter conn_iter;
  2455. struct drm_connector *connector = NULL;
  2456. struct sde_connector *sde_conn = NULL;
  2457. struct sde_splash_display *splash_display;
  2458. if (!kms) {
  2459. SDE_ERROR("invalid kms\n");
  2460. return -EINVAL;
  2461. }
  2462. sde_kms = to_sde_kms(kms);
  2463. dev = sde_kms->dev;
  2464. if (!dev) {
  2465. SDE_ERROR("invalid device\n");
  2466. return -EINVAL;
  2467. }
  2468. if (((sde_kms->splash_data.type == SDE_SPLASH_HANDOFF)
  2469. && (!sde_kms->splash_data.num_splash_regions)) ||
  2470. !sde_kms->splash_data.num_splash_displays) {
  2471. DRM_INFO("cont_splash feature not enabled\n");
  2472. sde_kms_inform_cont_splash_res_disable(kms, NULL);
  2473. return rc;
  2474. }
  2475. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  2476. sde_kms->splash_data.num_splash_displays,
  2477. sde_kms->dsi_display_count);
  2478. /* dsi */
  2479. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  2480. display = sde_kms->dsi_displays[i];
  2481. dsi_display = (struct dsi_display *)display;
  2482. splash_display = &sde_kms->splash_data.splash_display[i];
  2483. if (!splash_display->cont_splash_enabled) {
  2484. SDE_DEBUG("display->name = %s splash not enabled\n",
  2485. dsi_display->name);
  2486. sde_kms_inform_cont_splash_res_disable(kms,
  2487. dsi_display);
  2488. continue;
  2489. }
  2490. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  2491. if (dsi_display->bridge->base.encoder) {
  2492. encoder = dsi_display->bridge->base.encoder;
  2493. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2494. }
  2495. memset(&info, 0x0, sizeof(info));
  2496. rc = dsi_display_get_info(NULL, &info, display);
  2497. if (rc) {
  2498. SDE_ERROR("dsi get_info %d failed\n", i);
  2499. encoder = NULL;
  2500. continue;
  2501. }
  2502. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  2503. ((info.is_connected) ? "true" : "false"),
  2504. info.display_type);
  2505. if (!encoder) {
  2506. SDE_ERROR("encoder not initialized\n");
  2507. return -EINVAL;
  2508. }
  2509. priv = sde_kms->dev->dev_private;
  2510. encoder->crtc = priv->crtcs[i];
  2511. crtc = encoder->crtc;
  2512. splash_display->encoder = encoder;
  2513. SDE_DEBUG("for dsi-display:%d crtc id = %d enc id =%d\n",
  2514. i, crtc->base.id, encoder->base.id);
  2515. mutex_lock(&dev->mode_config.mutex);
  2516. drm_connector_list_iter_begin(dev, &conn_iter);
  2517. drm_for_each_connector_iter(connector, &conn_iter) {
  2518. /**
  2519. * SDE_KMS doesn't attach more than one encoder to
  2520. * a DSI connector. So it is safe to check only with
  2521. * the first encoder entry. Revisit this logic if we
  2522. * ever have to support continuous splash for
  2523. * external displays in MST configuration.
  2524. */
  2525. if (connector->encoder_ids[0] == encoder->base.id)
  2526. break;
  2527. }
  2528. drm_connector_list_iter_end(&conn_iter);
  2529. if (!connector) {
  2530. SDE_ERROR("connector not initialized\n");
  2531. mutex_unlock(&dev->mode_config.mutex);
  2532. return -EINVAL;
  2533. }
  2534. mutex_unlock(&dev->mode_config.mutex);
  2535. crtc->state->encoder_mask = (1 << drm_encoder_index(encoder));
  2536. drm_mode = _sde_kms_get_splash_mode(sde_kms, connector, i);
  2537. if (!drm_mode) {
  2538. SDE_ERROR("invalid drm-mode type:%d, index:%d\n",
  2539. sde_kms->splash_data.type, i);
  2540. return -EINVAL;
  2541. }
  2542. SDE_DEBUG("drm_mode->name = %s, type=0x%x, flags=0x%x\n",
  2543. drm_mode->name, drm_mode->type,
  2544. drm_mode->flags);
  2545. /* Update CRTC drm structure */
  2546. crtc->state->active = true;
  2547. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  2548. if (rc) {
  2549. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  2550. return rc;
  2551. }
  2552. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  2553. drm_mode_copy(&crtc->mode, drm_mode);
  2554. /* Update encoder structure */
  2555. sde_encoder_update_caps_for_cont_splash(encoder,
  2556. splash_display, true);
  2557. sde_crtc_update_cont_splash_settings(crtc);
  2558. sde_conn = to_sde_connector(connector);
  2559. if (sde_conn && sde_conn->ops.cont_splash_config)
  2560. sde_conn->ops.cont_splash_config(sde_conn->display);
  2561. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  2562. splash_display, crtc);
  2563. if (rc) {
  2564. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  2565. return rc;
  2566. }
  2567. }
  2568. return rc;
  2569. }
  2570. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  2571. {
  2572. struct sde_kms *sde_kms;
  2573. if (!kms) {
  2574. SDE_ERROR("invalid kms\n");
  2575. return false;
  2576. }
  2577. sde_kms = to_sde_kms(kms);
  2578. return sde_kms->splash_data.num_splash_displays;
  2579. }
  2580. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  2581. const struct drm_display_mode *mode,
  2582. const struct msm_resource_caps_info *res, u32 *num_lm)
  2583. {
  2584. struct sde_kms *sde_kms;
  2585. s64 mode_clock_hz = 0;
  2586. s64 max_mdp_clock_hz = 0;
  2587. s64 max_lm_width = 0;
  2588. s64 hdisplay_fp = 0;
  2589. s64 htotal_fp = 0;
  2590. s64 vtotal_fp = 0;
  2591. s64 vrefresh_fp = 0;
  2592. s64 mdp_fudge_factor = 0;
  2593. s64 num_lm_fp = 0;
  2594. s64 lm_clk_fp = 0;
  2595. s64 lm_width_fp = 0;
  2596. int rc = 0;
  2597. if (!num_lm) {
  2598. SDE_ERROR("invalid num_lm pointer\n");
  2599. return -EINVAL;
  2600. }
  2601. /* default to 1 layer mixer */
  2602. *num_lm = 1;
  2603. if (!kms || !mode || !res) {
  2604. SDE_ERROR("invalid input args\n");
  2605. return -EINVAL;
  2606. }
  2607. sde_kms = to_sde_kms(kms);
  2608. max_mdp_clock_hz = drm_int2fixp(sde_kms->perf.max_core_clk_rate);
  2609. max_lm_width = drm_int2fixp(res->max_mixer_width);
  2610. hdisplay_fp = drm_int2fixp(mode->hdisplay);
  2611. htotal_fp = drm_int2fixp(mode->htotal);
  2612. vtotal_fp = drm_int2fixp(mode->vtotal);
  2613. vrefresh_fp = drm_int2fixp(mode->vrefresh);
  2614. mdp_fudge_factor = drm_fixp_from_fraction(105, 100);
  2615. /* mode clock = [(h * v * fps * 1.05) / (num_lm)] */
  2616. mode_clock_hz = drm_fixp_mul(htotal_fp, vtotal_fp);
  2617. mode_clock_hz = drm_fixp_mul(mode_clock_hz, vrefresh_fp);
  2618. mode_clock_hz = drm_fixp_mul(mode_clock_hz, mdp_fudge_factor);
  2619. if (mode_clock_hz > max_mdp_clock_hz ||
  2620. hdisplay_fp > max_lm_width) {
  2621. *num_lm = 0;
  2622. do {
  2623. *num_lm += 2;
  2624. num_lm_fp = drm_int2fixp(*num_lm);
  2625. lm_clk_fp = drm_fixp_div(mode_clock_hz, num_lm_fp);
  2626. lm_width_fp = drm_fixp_div(hdisplay_fp, num_lm_fp);
  2627. if (*num_lm > 4) {
  2628. rc = -EINVAL;
  2629. goto error;
  2630. }
  2631. } while (lm_clk_fp > max_mdp_clock_hz ||
  2632. lm_width_fp > max_lm_width);
  2633. mode_clock_hz = lm_clk_fp;
  2634. }
  2635. SDE_DEBUG("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2636. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2637. *num_lm, drm_fixp2int(mode_clock_hz),
  2638. sde_kms->perf.max_core_clk_rate);
  2639. return 0;
  2640. error:
  2641. SDE_ERROR("required mode clk exceeds max mdp clk\n");
  2642. SDE_ERROR("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2643. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2644. *num_lm, drm_fixp2int(mode_clock_hz),
  2645. sde_kms->perf.max_core_clk_rate);
  2646. return rc;
  2647. }
  2648. static int sde_kms_get_dsc_count(const struct msm_kms *kms,
  2649. u32 hdisplay, u32 *num_dsc)
  2650. {
  2651. struct sde_kms *sde_kms;
  2652. uint32_t max_dsc_width;
  2653. if (!num_dsc) {
  2654. SDE_ERROR("invalid num_dsc pointer\n");
  2655. return -EINVAL;
  2656. }
  2657. *num_dsc = 0;
  2658. if (!kms || !hdisplay) {
  2659. SDE_ERROR("invalid input args\n");
  2660. return -EINVAL;
  2661. }
  2662. sde_kms = to_sde_kms(kms);
  2663. max_dsc_width = sde_kms->catalog->max_dsc_width;
  2664. *num_dsc = DIV_ROUND_UP(hdisplay, max_dsc_width);
  2665. SDE_DEBUG("h=%d, max_dsc_width=%d, num_dsc=%d\n",
  2666. hdisplay, max_dsc_width,
  2667. *num_dsc);
  2668. return 0;
  2669. }
  2670. static void _sde_kms_null_commit(struct drm_device *dev,
  2671. struct drm_encoder *enc)
  2672. {
  2673. struct drm_modeset_acquire_ctx ctx;
  2674. struct drm_connector *conn = NULL;
  2675. struct drm_connector *tmp_conn = NULL;
  2676. struct drm_connector_list_iter conn_iter;
  2677. struct drm_atomic_state *state = NULL;
  2678. struct drm_crtc_state *crtc_state = NULL;
  2679. struct drm_connector_state *conn_state = NULL;
  2680. int retry_cnt = 0;
  2681. int ret = 0;
  2682. drm_modeset_acquire_init(&ctx, 0);
  2683. retry:
  2684. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2685. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  2686. drm_modeset_backoff(&ctx);
  2687. retry_cnt++;
  2688. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  2689. goto retry;
  2690. } else if (WARN_ON(ret)) {
  2691. goto end;
  2692. }
  2693. state = drm_atomic_state_alloc(dev);
  2694. if (!state) {
  2695. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  2696. goto end;
  2697. }
  2698. state->acquire_ctx = &ctx;
  2699. drm_connector_list_iter_begin(dev, &conn_iter);
  2700. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2701. if (enc == tmp_conn->state->best_encoder) {
  2702. conn = tmp_conn;
  2703. break;
  2704. }
  2705. }
  2706. drm_connector_list_iter_end(&conn_iter);
  2707. if (!conn) {
  2708. SDE_ERROR("error in finding conn for enc:%d\n", DRMID(enc));
  2709. goto end;
  2710. }
  2711. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2712. conn_state = drm_atomic_get_connector_state(state, conn);
  2713. if (IS_ERR(conn_state)) {
  2714. SDE_ERROR("error %d getting connector %d state\n",
  2715. ret, DRMID(conn));
  2716. goto end;
  2717. }
  2718. crtc_state->active = true;
  2719. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2720. if (ret)
  2721. SDE_ERROR("error %d setting the crtc\n", ret);
  2722. ret = drm_atomic_commit(state);
  2723. if (ret)
  2724. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  2725. end:
  2726. if (state)
  2727. drm_atomic_state_put(state);
  2728. drm_modeset_drop_locks(&ctx);
  2729. drm_modeset_acquire_fini(&ctx);
  2730. }
  2731. void sde_kms_display_early_wakeup(struct drm_device *dev,
  2732. const int32_t connector_id)
  2733. {
  2734. struct drm_connector_list_iter conn_iter;
  2735. struct drm_connector *conn;
  2736. struct drm_encoder *drm_enc;
  2737. drm_connector_list_iter_begin(dev, &conn_iter);
  2738. drm_for_each_connector_iter(conn, &conn_iter) {
  2739. if (connector_id != DRM_MSM_WAKE_UP_ALL_DISPLAYS &&
  2740. connector_id != conn->base.id)
  2741. continue;
  2742. if (conn->state && conn->state->best_encoder)
  2743. drm_enc = conn->state->best_encoder;
  2744. else
  2745. drm_enc = conn->encoder;
  2746. if (drm_enc)
  2747. sde_encoder_early_wakeup(drm_enc);
  2748. }
  2749. drm_connector_list_iter_end(&conn_iter);
  2750. }
  2751. static void _sde_kms_pm_suspend_idle_helper(struct sde_kms *sde_kms,
  2752. struct device *dev)
  2753. {
  2754. int i, ret, crtc_id = 0;
  2755. struct drm_device *ddev = dev_get_drvdata(dev);
  2756. struct drm_connector *conn;
  2757. struct drm_connector_list_iter conn_iter;
  2758. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  2759. drm_connector_list_iter_begin(ddev, &conn_iter);
  2760. drm_for_each_connector_iter(conn, &conn_iter) {
  2761. uint64_t lp;
  2762. lp = sde_connector_get_lp(conn);
  2763. if (lp != SDE_MODE_DPMS_LP2)
  2764. continue;
  2765. if (sde_encoder_in_clone_mode(conn->encoder))
  2766. continue;
  2767. ret = sde_encoder_wait_for_event(conn->encoder,
  2768. MSM_ENC_TX_COMPLETE);
  2769. if (ret && ret != -EWOULDBLOCK) {
  2770. SDE_ERROR(
  2771. "[conn: %d] wait for commit done returned %d\n",
  2772. conn->base.id, ret);
  2773. } else if (!ret) {
  2774. crtc_id = drm_crtc_index(conn->state->crtc);
  2775. if (priv->event_thread[crtc_id].thread)
  2776. kthread_flush_worker(
  2777. &priv->event_thread[crtc_id].worker);
  2778. sde_encoder_idle_request(conn->encoder);
  2779. }
  2780. }
  2781. drm_connector_list_iter_end(&conn_iter);
  2782. for (i = 0; i < priv->num_crtcs; i++) {
  2783. if (priv->disp_thread[i].thread)
  2784. kthread_flush_worker(
  2785. &priv->disp_thread[i].worker);
  2786. if (priv->event_thread[i].thread)
  2787. kthread_flush_worker(
  2788. &priv->event_thread[i].worker);
  2789. }
  2790. kthread_flush_worker(&priv->pp_event_worker);
  2791. }
  2792. static int sde_kms_pm_suspend(struct device *dev)
  2793. {
  2794. struct drm_device *ddev;
  2795. struct drm_modeset_acquire_ctx ctx;
  2796. struct drm_connector *conn;
  2797. struct drm_encoder *enc;
  2798. struct drm_connector_list_iter conn_iter;
  2799. struct drm_atomic_state *state = NULL;
  2800. struct sde_kms *sde_kms;
  2801. int ret = 0, num_crtcs = 0;
  2802. if (!dev)
  2803. return -EINVAL;
  2804. ddev = dev_get_drvdata(dev);
  2805. if (!ddev || !ddev_to_msm_kms(ddev))
  2806. return -EINVAL;
  2807. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2808. SDE_EVT32(0);
  2809. /* disable hot-plug polling */
  2810. drm_kms_helper_poll_disable(ddev);
  2811. /* if a display stuck in CS trigger a null commit to complete handoff */
  2812. drm_for_each_encoder(enc, ddev) {
  2813. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  2814. _sde_kms_null_commit(ddev, enc);
  2815. }
  2816. /* acquire modeset lock(s) */
  2817. drm_modeset_acquire_init(&ctx, 0);
  2818. retry:
  2819. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2820. if (ret)
  2821. goto unlock;
  2822. /* save current state for resume */
  2823. if (sde_kms->suspend_state)
  2824. drm_atomic_state_put(sde_kms->suspend_state);
  2825. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  2826. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  2827. ret = PTR_ERR(sde_kms->suspend_state);
  2828. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  2829. sde_kms->suspend_state = NULL;
  2830. goto unlock;
  2831. }
  2832. /* create atomic state to disable all CRTCs */
  2833. state = drm_atomic_state_alloc(ddev);
  2834. if (!state) {
  2835. ret = -ENOMEM;
  2836. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  2837. goto unlock;
  2838. }
  2839. state->acquire_ctx = &ctx;
  2840. drm_connector_list_iter_begin(ddev, &conn_iter);
  2841. drm_for_each_connector_iter(conn, &conn_iter) {
  2842. struct drm_crtc_state *crtc_state;
  2843. uint64_t lp;
  2844. if (!conn->state || !conn->state->crtc ||
  2845. conn->dpms != DRM_MODE_DPMS_ON ||
  2846. sde_encoder_in_clone_mode(conn->encoder))
  2847. continue;
  2848. lp = sde_connector_get_lp(conn);
  2849. if (lp == SDE_MODE_DPMS_LP1) {
  2850. /* transition LP1->LP2 on pm suspend */
  2851. ret = sde_connector_set_property_for_commit(conn, state,
  2852. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  2853. if (ret) {
  2854. DRM_ERROR("failed to set lp2 for conn %d\n",
  2855. conn->base.id);
  2856. drm_connector_list_iter_end(&conn_iter);
  2857. goto unlock;
  2858. }
  2859. }
  2860. if (lp != SDE_MODE_DPMS_LP2) {
  2861. /* force CRTC to be inactive */
  2862. crtc_state = drm_atomic_get_crtc_state(state,
  2863. conn->state->crtc);
  2864. if (IS_ERR_OR_NULL(crtc_state)) {
  2865. DRM_ERROR("failed to get crtc %d state\n",
  2866. conn->state->crtc->base.id);
  2867. drm_connector_list_iter_end(&conn_iter);
  2868. goto unlock;
  2869. }
  2870. if (lp != SDE_MODE_DPMS_LP1)
  2871. crtc_state->active = false;
  2872. ++num_crtcs;
  2873. }
  2874. }
  2875. drm_connector_list_iter_end(&conn_iter);
  2876. /* check for nothing to do */
  2877. if (num_crtcs == 0) {
  2878. DRM_DEBUG("all crtcs are already in the off state\n");
  2879. sde_kms->suspend_block = true;
  2880. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2881. goto unlock;
  2882. }
  2883. /* commit the "disable all" state */
  2884. ret = drm_atomic_commit(state);
  2885. if (ret < 0) {
  2886. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  2887. goto unlock;
  2888. }
  2889. sde_kms->suspend_block = true;
  2890. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2891. unlock:
  2892. if (state) {
  2893. drm_atomic_state_put(state);
  2894. state = NULL;
  2895. }
  2896. if (ret == -EDEADLK) {
  2897. drm_modeset_backoff(&ctx);
  2898. goto retry;
  2899. }
  2900. drm_modeset_drop_locks(&ctx);
  2901. drm_modeset_acquire_fini(&ctx);
  2902. /*
  2903. * pm runtime driver avoids multiple runtime_suspend API call by
  2904. * checking runtime_status. However, this call helps when there is a
  2905. * race condition between pm_suspend call and doze_suspend/power_off
  2906. * commit. It removes the extra vote from suspend and adds it back
  2907. * later to allow power collapse during pm_suspend call
  2908. */
  2909. pm_runtime_put_sync(dev);
  2910. pm_runtime_get_noresume(dev);
  2911. /* dump clock state before entering suspend */
  2912. if (sde_kms->pm_suspend_clk_dump)
  2913. _sde_kms_dump_clks_state(sde_kms);
  2914. return ret;
  2915. }
  2916. static int sde_kms_pm_resume(struct device *dev)
  2917. {
  2918. struct drm_device *ddev;
  2919. struct sde_kms *sde_kms;
  2920. struct drm_modeset_acquire_ctx ctx;
  2921. int ret, i;
  2922. if (!dev)
  2923. return -EINVAL;
  2924. ddev = dev_get_drvdata(dev);
  2925. if (!ddev || !ddev_to_msm_kms(ddev))
  2926. return -EINVAL;
  2927. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2928. SDE_EVT32(sde_kms->suspend_state != NULL);
  2929. drm_mode_config_reset(ddev);
  2930. drm_modeset_acquire_init(&ctx, 0);
  2931. retry:
  2932. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2933. if (ret == -EDEADLK) {
  2934. drm_modeset_backoff(&ctx);
  2935. goto retry;
  2936. } else if (WARN_ON(ret)) {
  2937. goto end;
  2938. }
  2939. sde_kms->suspend_block = false;
  2940. if (sde_kms->suspend_state) {
  2941. sde_kms->suspend_state->acquire_ctx = &ctx;
  2942. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  2943. ret = drm_atomic_helper_commit_duplicated_state(
  2944. sde_kms->suspend_state, &ctx);
  2945. if (ret != -EDEADLK)
  2946. break;
  2947. drm_modeset_backoff(&ctx);
  2948. }
  2949. if (ret < 0)
  2950. DRM_ERROR("failed to restore state, %d\n", ret);
  2951. drm_atomic_state_put(sde_kms->suspend_state);
  2952. sde_kms->suspend_state = NULL;
  2953. }
  2954. end:
  2955. drm_modeset_drop_locks(&ctx);
  2956. drm_modeset_acquire_fini(&ctx);
  2957. /* enable hot-plug polling */
  2958. drm_kms_helper_poll_enable(ddev);
  2959. return 0;
  2960. }
  2961. static const struct msm_kms_funcs kms_funcs = {
  2962. .hw_init = sde_kms_hw_init,
  2963. .postinit = sde_kms_postinit,
  2964. .irq_preinstall = sde_irq_preinstall,
  2965. .irq_postinstall = sde_irq_postinstall,
  2966. .irq_uninstall = sde_irq_uninstall,
  2967. .irq = sde_irq,
  2968. .lastclose = sde_kms_lastclose,
  2969. .prepare_fence = sde_kms_prepare_fence,
  2970. .prepare_commit = sde_kms_prepare_commit,
  2971. .commit = sde_kms_commit,
  2972. .complete_commit = sde_kms_complete_commit,
  2973. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  2974. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  2975. .enable_vblank = sde_kms_enable_vblank,
  2976. .disable_vblank = sde_kms_disable_vblank,
  2977. .check_modified_format = sde_format_check_modified_format,
  2978. .atomic_check = sde_kms_atomic_check,
  2979. .get_format = sde_get_msm_format,
  2980. .round_pixclk = sde_kms_round_pixclk,
  2981. .display_early_wakeup = sde_kms_display_early_wakeup,
  2982. .pm_suspend = sde_kms_pm_suspend,
  2983. .pm_resume = sde_kms_pm_resume,
  2984. .destroy = sde_kms_destroy,
  2985. .debugfs_destroy = sde_kms_debugfs_destroy,
  2986. .cont_splash_config = sde_kms_cont_splash_config,
  2987. .register_events = _sde_kms_register_events,
  2988. .get_address_space = _sde_kms_get_address_space,
  2989. .get_address_space_device = _sde_kms_get_address_space_device,
  2990. .postopen = _sde_kms_post_open,
  2991. .check_for_splash = sde_kms_check_for_splash,
  2992. .get_mixer_count = sde_kms_get_mixer_count,
  2993. .get_dsc_count = sde_kms_get_dsc_count,
  2994. };
  2995. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  2996. {
  2997. int i;
  2998. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  2999. if (!sde_kms->aspace[i])
  3000. continue;
  3001. msm_gem_address_space_put(sde_kms->aspace[i]);
  3002. sde_kms->aspace[i] = NULL;
  3003. }
  3004. return 0;
  3005. }
  3006. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  3007. {
  3008. struct msm_mmu *mmu;
  3009. int i, ret;
  3010. int early_map = 0;
  3011. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev)
  3012. return -EINVAL;
  3013. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  3014. struct msm_gem_address_space *aspace;
  3015. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  3016. if (IS_ERR(mmu)) {
  3017. ret = PTR_ERR(mmu);
  3018. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  3019. i, ret);
  3020. continue;
  3021. }
  3022. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  3023. mmu, "sde");
  3024. if (IS_ERR(aspace)) {
  3025. ret = PTR_ERR(aspace);
  3026. mmu->funcs->destroy(mmu);
  3027. goto fail;
  3028. }
  3029. sde_kms->aspace[i] = aspace;
  3030. aspace->domain_attached = true;
  3031. /* Mapping splash memory block */
  3032. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  3033. sde_kms->splash_data.num_splash_regions) {
  3034. ret = _sde_kms_map_all_splash_regions(sde_kms);
  3035. if (ret) {
  3036. SDE_ERROR("failed to map ret:%d\n", ret);
  3037. goto fail;
  3038. }
  3039. }
  3040. /*
  3041. * disable early-map which would have been enabled during
  3042. * bootup by smmu through the device-tree hint for cont-spash
  3043. */
  3044. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  3045. &early_map);
  3046. if (ret) {
  3047. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  3048. ret, early_map);
  3049. goto early_map_fail;
  3050. }
  3051. }
  3052. sde_kms->base.aspace = sde_kms->aspace[0];
  3053. return 0;
  3054. early_map_fail:
  3055. _sde_kms_unmap_all_splash_regions(sde_kms);
  3056. fail:
  3057. _sde_kms_mmu_destroy(sde_kms);
  3058. return ret;
  3059. }
  3060. static void sde_kms_init_rot_sid_hw(struct sde_kms *sde_kms)
  3061. {
  3062. if (!sde_kms || !sde_kms->hw_sid || sde_in_trusted_vm(sde_kms))
  3063. return;
  3064. sde_hw_set_rotator_sid(sde_kms->hw_sid);
  3065. }
  3066. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  3067. {
  3068. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  3069. return;
  3070. if (sde_kms->hw_mdp->ops.reset_ubwc)
  3071. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  3072. sde_kms->catalog);
  3073. }
  3074. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  3075. {
  3076. struct sde_vbif_set_qos_params qos_params;
  3077. struct sde_mdss_cfg *catalog;
  3078. if (!sde_kms->catalog)
  3079. return;
  3080. catalog = sde_kms->catalog;
  3081. memset(&qos_params, 0, sizeof(qos_params));
  3082. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  3083. qos_params.xin_id = catalog->dma_cfg.xin_id;
  3084. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  3085. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  3086. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  3087. }
  3088. static int _sde_kms_active_override(struct sde_kms *sde_kms, bool enable)
  3089. {
  3090. struct sde_hw_uidle *uidle;
  3091. if (!sde_kms) {
  3092. SDE_ERROR("invalid kms\n");
  3093. return -EINVAL;
  3094. }
  3095. uidle = sde_kms->hw_uidle;
  3096. if (uidle && uidle->ops.active_override_enable)
  3097. uidle->ops.active_override_enable(uidle, enable);
  3098. return 0;
  3099. }
  3100. static void _sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
  3101. {
  3102. struct device *cpu_dev;
  3103. int cpu = 0;
  3104. u32 cpu_irq_latency = sde_kms->catalog->perf.cpu_irq_latency;
  3105. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3106. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3107. return;
  3108. }
  3109. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3110. cpu_dev = get_cpu_device(cpu);
  3111. if (!cpu_dev) {
  3112. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3113. cpu);
  3114. continue;
  3115. }
  3116. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3117. dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
  3118. cpu_irq_latency);
  3119. else
  3120. dev_pm_qos_add_request(cpu_dev,
  3121. &sde_kms->pm_qos_irq_req[cpu],
  3122. DEV_PM_QOS_RESUME_LATENCY,
  3123. cpu_irq_latency);
  3124. }
  3125. }
  3126. static void _sde_kms_remove_pm_qos_irq_request(struct sde_kms *sde_kms)
  3127. {
  3128. struct device *cpu_dev;
  3129. int cpu = 0;
  3130. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3131. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3132. return;
  3133. }
  3134. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3135. cpu_dev = get_cpu_device(cpu);
  3136. if (!cpu_dev) {
  3137. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3138. cpu);
  3139. continue;
  3140. }
  3141. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3142. dev_pm_qos_remove_request(
  3143. &sde_kms->pm_qos_irq_req[cpu]);
  3144. }
  3145. }
  3146. void sde_kms_cpu_vote_for_irq(struct sde_kms *sde_kms, bool enable)
  3147. {
  3148. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  3149. mutex_lock(&priv->phandle.phandle_lock);
  3150. if (enable && atomic_inc_return(&sde_kms->irq_vote_count) == 1)
  3151. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3152. else if (!enable && atomic_dec_return(&sde_kms->irq_vote_count) == 0)
  3153. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3154. mutex_unlock(&priv->phandle.phandle_lock);
  3155. }
  3156. static void sde_kms_irq_affinity_notify(
  3157. struct irq_affinity_notify *affinity_notify,
  3158. const cpumask_t *mask)
  3159. {
  3160. struct msm_drm_private *priv;
  3161. struct sde_kms *sde_kms = container_of(affinity_notify,
  3162. struct sde_kms, affinity_notify);
  3163. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  3164. return;
  3165. priv = sde_kms->dev->dev_private;
  3166. mutex_lock(&priv->phandle.phandle_lock);
  3167. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3168. // save irq cpu mask
  3169. sde_kms->irq_cpu_mask = *mask;
  3170. // request vote with updated irq cpu mask
  3171. if (atomic_read(&sde_kms->irq_vote_count))
  3172. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3173. mutex_unlock(&priv->phandle.phandle_lock);
  3174. }
  3175. static void sde_kms_irq_affinity_release(struct kref *ref) {}
  3176. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  3177. {
  3178. struct sde_kms *sde_kms = usr;
  3179. struct msm_kms *msm_kms;
  3180. msm_kms = &sde_kms->base;
  3181. if (!sde_kms)
  3182. return;
  3183. SDE_DEBUG("event_type:%d\n", event_type);
  3184. SDE_EVT32_VERBOSE(event_type);
  3185. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  3186. sde_irq_update(msm_kms, true);
  3187. sde_kms->first_kickoff = true;
  3188. /**
  3189. * Rotator sid needs to be programmed since uefi doesn't
  3190. * configure it during continuous splash
  3191. */
  3192. sde_kms_init_rot_sid_hw(sde_kms);
  3193. if (sde_kms->splash_data.num_splash_displays ||
  3194. sde_in_trusted_vm(sde_kms))
  3195. return;
  3196. sde_vbif_init_memtypes(sde_kms);
  3197. sde_kms_init_shared_hw(sde_kms);
  3198. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  3199. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  3200. sde_irq_update(msm_kms, false);
  3201. sde_kms->first_kickoff = false;
  3202. if (sde_in_trusted_vm(sde_kms))
  3203. return;
  3204. _sde_kms_active_override(sde_kms, true);
  3205. if (!is_sde_rsc_available(SDE_RSC_INDEX))
  3206. sde_vbif_axi_halt_request(sde_kms);
  3207. }
  3208. }
  3209. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  3210. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  3211. {
  3212. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3213. int rc = -EINVAL;
  3214. SDE_DEBUG("\n");
  3215. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  3216. if (rc > 0)
  3217. rc = 0;
  3218. SDE_EVT32(rc, genpd->device_count);
  3219. return rc;
  3220. }
  3221. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  3222. {
  3223. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3224. SDE_DEBUG("\n");
  3225. pm_runtime_put_sync(sde_kms->dev->dev);
  3226. SDE_EVT32(genpd->device_count);
  3227. return 0;
  3228. }
  3229. static int _sde_kms_get_splash_data(struct sde_kms *sde_kms,
  3230. struct sde_splash_data *data)
  3231. {
  3232. int i = 0;
  3233. int ret = 0;
  3234. struct device_node *parent, *node, *node1;
  3235. struct resource r, r1;
  3236. const char *node_name = "splash_region";
  3237. struct sde_splash_mem *mem;
  3238. bool share_splash_mem = false;
  3239. int num_displays, num_regions;
  3240. struct sde_splash_display *splash_display;
  3241. if (!data)
  3242. return -EINVAL;
  3243. memset(data, 0, sizeof(*data));
  3244. parent = of_find_node_by_path("/reserved-memory");
  3245. if (!parent) {
  3246. SDE_ERROR("failed to find reserved-memory node\n");
  3247. return -EINVAL;
  3248. }
  3249. node = of_find_node_by_name(parent, node_name);
  3250. if (!node) {
  3251. SDE_DEBUG("failed to find node %s\n", node_name);
  3252. return -EINVAL;
  3253. }
  3254. node1 = of_find_node_by_name(NULL, "disp_rdump_region");
  3255. if (!node1)
  3256. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  3257. /**
  3258. * Support sharing a single splash memory for all the built in displays
  3259. * and also independent splash region per displays. Incase of
  3260. * independent splash region for each connected display, dtsi node of
  3261. * cont_splash_region should be collection of all memory regions
  3262. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  3263. */
  3264. num_displays = dsi_display_get_num_of_displays();
  3265. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  3266. data->num_splash_displays = num_displays;
  3267. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  3268. if (num_displays > num_regions) {
  3269. share_splash_mem = true;
  3270. pr_info(":%d displays share same splash buf\n", num_displays);
  3271. }
  3272. for (i = 0; i < num_displays; i++) {
  3273. splash_display = &data->splash_display[i];
  3274. if (!i || !share_splash_mem) {
  3275. if (of_address_to_resource(node, i, &r)) {
  3276. SDE_ERROR("invalid data for:%s\n", node_name);
  3277. return -EINVAL;
  3278. }
  3279. mem = &data->splash_mem[i];
  3280. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  3281. SDE_DEBUG("failed to find ramdump memory\n");
  3282. mem->ramdump_base = 0;
  3283. mem->ramdump_size = 0;
  3284. } else {
  3285. mem->ramdump_base = (unsigned long)r1.start;
  3286. mem->ramdump_size = (r1.end - r1.start) + 1;
  3287. }
  3288. mem->splash_buf_base = (unsigned long)r.start;
  3289. mem->splash_buf_size = (r.end - r.start) + 1;
  3290. mem->ref_cnt = 0;
  3291. splash_display->splash = mem;
  3292. data->num_splash_regions++;
  3293. } else {
  3294. data->splash_display[i].splash = &data->splash_mem[0];
  3295. }
  3296. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  3297. splash_display->splash->splash_buf_base,
  3298. splash_display->splash->splash_buf_size);
  3299. }
  3300. sde_kms->splash_data.type = SDE_SPLASH_HANDOFF;
  3301. return ret;
  3302. }
  3303. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  3304. struct platform_device *platformdev)
  3305. {
  3306. int rc = -EINVAL;
  3307. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  3308. if (IS_ERR(sde_kms->mmio)) {
  3309. rc = PTR_ERR(sde_kms->mmio);
  3310. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  3311. sde_kms->mmio = NULL;
  3312. goto error;
  3313. }
  3314. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  3315. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  3316. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  3317. sde_kms->mmio_len);
  3318. if (rc)
  3319. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  3320. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",
  3321. "vbif_phys");
  3322. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  3323. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  3324. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  3325. sde_kms->vbif[VBIF_RT] = NULL;
  3326. goto error;
  3327. }
  3328. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,
  3329. "vbif_phys");
  3330. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  3331. sde_kms->vbif_len[VBIF_RT]);
  3332. if (rc)
  3333. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  3334. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",
  3335. "vbif_nrt_phys");
  3336. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  3337. sde_kms->vbif[VBIF_NRT] = NULL;
  3338. SDE_DEBUG("VBIF NRT is not defined");
  3339. } else {
  3340. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
  3341. "vbif_nrt_phys");
  3342. rc = sde_dbg_reg_register_base("vbif_nrt",
  3343. sde_kms->vbif[VBIF_NRT],
  3344. sde_kms->vbif_len[VBIF_NRT]);
  3345. if (rc)
  3346. SDE_ERROR("dbg base register vbif_nrt failed: %d\n",
  3347. rc);
  3348. }
  3349. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",
  3350. "regdma_phys");
  3351. if (IS_ERR(sde_kms->reg_dma)) {
  3352. sde_kms->reg_dma = NULL;
  3353. SDE_DEBUG("REG_DMA is not defined");
  3354. } else {
  3355. sde_kms->reg_dma_len = msm_iomap_size(platformdev,
  3356. "regdma_phys");
  3357. rc = sde_dbg_reg_register_base("reg_dma",
  3358. sde_kms->reg_dma,
  3359. sde_kms->reg_dma_len);
  3360. if (rc)
  3361. SDE_ERROR("dbg base register reg_dma failed: %d\n",
  3362. rc);
  3363. }
  3364. sde_kms->sid = msm_ioremap(platformdev, "sid_phys",
  3365. "sid_phys");
  3366. if (IS_ERR(sde_kms->sid)) {
  3367. SDE_DEBUG("sid register is not defined: %d\n", rc);
  3368. sde_kms->sid = NULL;
  3369. } else {
  3370. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  3371. rc = sde_dbg_reg_register_base("sid", sde_kms->sid,
  3372. sde_kms->sid_len);
  3373. if (rc)
  3374. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  3375. }
  3376. error:
  3377. return rc;
  3378. }
  3379. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  3380. struct sde_kms *sde_kms)
  3381. {
  3382. int rc = 0;
  3383. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  3384. sde_kms->genpd.name = dev->unique;
  3385. sde_kms->genpd.power_off = sde_kms_pd_disable;
  3386. sde_kms->genpd.power_on = sde_kms_pd_enable;
  3387. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  3388. if (rc < 0) {
  3389. SDE_ERROR("failed to init genpd provider %s: %d\n",
  3390. sde_kms->genpd.name, rc);
  3391. return rc;
  3392. }
  3393. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  3394. &sde_kms->genpd);
  3395. if (rc < 0) {
  3396. SDE_ERROR("failed to add genpd provider %s: %d\n",
  3397. sde_kms->genpd.name, rc);
  3398. pm_genpd_remove(&sde_kms->genpd);
  3399. return rc;
  3400. }
  3401. sde_kms->genpd_init = true;
  3402. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  3403. }
  3404. return rc;
  3405. }
  3406. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  3407. struct drm_device *dev,
  3408. struct msm_drm_private *priv)
  3409. {
  3410. struct sde_rm *rm = NULL;
  3411. int i, rc = -EINVAL;
  3412. sde_kms->catalog = sde_hw_catalog_init(dev);
  3413. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  3414. rc = PTR_ERR(sde_kms->catalog);
  3415. if (!sde_kms->catalog)
  3416. rc = -EINVAL;
  3417. SDE_ERROR("catalog init failed: %d\n", rc);
  3418. sde_kms->catalog = NULL;
  3419. goto power_error;
  3420. }
  3421. sde_kms->core_rev = sde_kms->catalog->hwversion;
  3422. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  3423. /* initialize power domain if defined */
  3424. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  3425. if (rc) {
  3426. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  3427. goto genpd_err;
  3428. }
  3429. rc = _sde_kms_mmu_init(sde_kms);
  3430. if (rc) {
  3431. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  3432. goto power_error;
  3433. }
  3434. /* Initialize reg dma block which is a singleton */
  3435. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  3436. sde_kms->dev);
  3437. if (rc) {
  3438. SDE_ERROR("failed: reg dma init failed\n");
  3439. goto power_error;
  3440. }
  3441. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  3442. rm = &sde_kms->rm;
  3443. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  3444. sde_kms->dev);
  3445. if (rc) {
  3446. SDE_ERROR("rm init failed: %d\n", rc);
  3447. goto power_error;
  3448. }
  3449. sde_kms->rm_init = true;
  3450. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  3451. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  3452. rc = PTR_ERR(sde_kms->hw_intr);
  3453. SDE_ERROR("hw_intr init failed: %d\n", rc);
  3454. sde_kms->hw_intr = NULL;
  3455. goto hw_intr_init_err;
  3456. }
  3457. /*
  3458. * Attempt continuous splash handoff only if reserved
  3459. * splash memory is found & release resources on any error
  3460. * in finding display hw config in splash
  3461. */
  3462. if (sde_kms->splash_data.num_splash_regions) {
  3463. struct sde_splash_display *display;
  3464. int ret, display_count =
  3465. sde_kms->splash_data.num_splash_displays;
  3466. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3467. &sde_kms->splash_data, sde_kms->catalog);
  3468. for (i = 0; i < display_count; i++) {
  3469. display = &sde_kms->splash_data.splash_display[i];
  3470. /*
  3471. * free splash region on resource init failure and
  3472. * cont-splash disabled case
  3473. */
  3474. if (!display->cont_splash_enabled || ret)
  3475. _sde_kms_free_splash_display_data(
  3476. sde_kms, display);
  3477. }
  3478. }
  3479. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  3480. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  3481. rc = PTR_ERR(sde_kms->hw_mdp);
  3482. if (!sde_kms->hw_mdp)
  3483. rc = -EINVAL;
  3484. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  3485. sde_kms->hw_mdp = NULL;
  3486. goto power_error;
  3487. }
  3488. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  3489. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  3490. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  3491. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  3492. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  3493. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  3494. if (!sde_kms->hw_vbif[vbif_idx])
  3495. rc = -EINVAL;
  3496. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  3497. sde_kms->hw_vbif[vbif_idx] = NULL;
  3498. goto power_error;
  3499. }
  3500. }
  3501. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  3502. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  3503. sde_kms->mmio_len, sde_kms->catalog);
  3504. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  3505. rc = PTR_ERR(sde_kms->hw_uidle);
  3506. if (!sde_kms->hw_uidle)
  3507. rc = -EINVAL;
  3508. /* uidle is optional, so do not make it a fatal error */
  3509. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  3510. sde_kms->hw_uidle = NULL;
  3511. rc = 0;
  3512. }
  3513. } else {
  3514. sde_kms->hw_uidle = NULL;
  3515. }
  3516. if (sde_kms->sid) {
  3517. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  3518. sde_kms->sid_len, sde_kms->catalog);
  3519. if (IS_ERR_OR_NULL(sde_kms->hw_sid)) {
  3520. rc = PTR_ERR(sde_kms->hw_sid);
  3521. SDE_ERROR("failed to init sid %ld\n", rc);
  3522. sde_kms->hw_sid = NULL;
  3523. goto power_error;
  3524. }
  3525. }
  3526. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  3527. &priv->phandle, "core_clk");
  3528. if (rc) {
  3529. SDE_ERROR("failed to init perf %d\n", rc);
  3530. goto perf_err;
  3531. }
  3532. /*
  3533. * _sde_kms_drm_obj_init should create the DRM related objects
  3534. * i.e. CRTCs, planes, encoders, connectors and so forth
  3535. */
  3536. rc = _sde_kms_drm_obj_init(sde_kms);
  3537. if (rc) {
  3538. SDE_ERROR("modeset init failed: %d\n", rc);
  3539. goto drm_obj_init_err;
  3540. }
  3541. return 0;
  3542. genpd_err:
  3543. drm_obj_init_err:
  3544. sde_core_perf_destroy(&sde_kms->perf);
  3545. hw_intr_init_err:
  3546. perf_err:
  3547. power_error:
  3548. return rc;
  3549. }
  3550. int sde_kms_get_io_resources(struct sde_kms *sde_kms, struct msm_io_res *io_res)
  3551. {
  3552. struct platform_device *pdev = to_platform_device(sde_kms->dev->dev);
  3553. int rc = 0;
  3554. rc = msm_dss_get_io_mem(pdev, &io_res->mem);
  3555. if (rc) {
  3556. SDE_ERROR("failed to get io mem for KMS, rc = %d\n", rc);
  3557. return rc;
  3558. }
  3559. rc = msm_dss_get_pmic_io_mem(pdev, &io_res->mem);
  3560. if (rc) {
  3561. SDE_ERROR("failed to get io mem for pmic, rc:%d\n", rc);
  3562. return rc;
  3563. }
  3564. rc = msm_dss_get_io_irq(pdev, &io_res->irq, HH_IRQ_LABEL_SDE);
  3565. if (rc) {
  3566. SDE_ERROR("failed to get io irq for KMS");
  3567. return rc;
  3568. }
  3569. return rc;
  3570. }
  3571. static int sde_kms_hw_init(struct msm_kms *kms)
  3572. {
  3573. struct sde_kms *sde_kms;
  3574. struct drm_device *dev;
  3575. struct msm_drm_private *priv;
  3576. struct platform_device *platformdev;
  3577. int i, irq_num, rc = -EINVAL;
  3578. if (!kms) {
  3579. SDE_ERROR("invalid kms\n");
  3580. goto end;
  3581. }
  3582. sde_kms = to_sde_kms(kms);
  3583. dev = sde_kms->dev;
  3584. if (!dev || !dev->dev) {
  3585. SDE_ERROR("invalid device\n");
  3586. goto end;
  3587. }
  3588. platformdev = to_platform_device(dev->dev);
  3589. priv = dev->dev_private;
  3590. if (!priv) {
  3591. SDE_ERROR("invalid private data\n");
  3592. goto end;
  3593. }
  3594. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  3595. if (rc)
  3596. goto error;
  3597. rc = _sde_kms_get_splash_data(sde_kms, &sde_kms->splash_data);
  3598. if (rc)
  3599. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  3600. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  3601. if (rc)
  3602. goto error;
  3603. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  3604. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  3605. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  3606. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  3607. mutex_init(&sde_kms->secure_transition_lock);
  3608. atomic_set(&sde_kms->detach_sec_cb, 0);
  3609. atomic_set(&sde_kms->detach_all_cb, 0);
  3610. atomic_set(&sde_kms->irq_vote_count, 0);
  3611. /*
  3612. * Support format modifiers for compression etc.
  3613. */
  3614. dev->mode_config.allow_fb_modifiers = true;
  3615. /*
  3616. * Handle (re)initializations during power enable
  3617. */
  3618. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  3619. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  3620. SDE_POWER_EVENT_POST_ENABLE |
  3621. SDE_POWER_EVENT_PRE_DISABLE,
  3622. sde_kms_handle_power_event, sde_kms, "kms");
  3623. if (sde_kms->splash_data.num_splash_displays) {
  3624. SDE_DEBUG("Skipping MDP Resources disable\n");
  3625. } else {
  3626. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  3627. sde_power_data_bus_set_quota(&priv->phandle, i,
  3628. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  3629. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  3630. pm_runtime_put_sync(sde_kms->dev->dev);
  3631. }
  3632. sde_kms->affinity_notify.notify = sde_kms_irq_affinity_notify;
  3633. sde_kms->affinity_notify.release = sde_kms_irq_affinity_release;
  3634. irq_num = platform_get_irq(to_platform_device(sde_kms->dev->dev), 0);
  3635. SDE_DEBUG("Registering for notification of irq_num: %d\n", irq_num);
  3636. irq_set_affinity_notifier(irq_num, &sde_kms->affinity_notify);
  3637. if (sde_in_trusted_vm(sde_kms))
  3638. rc = sde_vm_trusted_init(sde_kms);
  3639. else
  3640. rc = sde_vm_primary_init(sde_kms);
  3641. if (rc) {
  3642. SDE_ERROR("failed to initialize VM ops, rc: %d\n", rc);
  3643. goto error;
  3644. }
  3645. return 0;
  3646. error:
  3647. _sde_kms_hw_destroy(sde_kms, platformdev);
  3648. end:
  3649. return rc;
  3650. }
  3651. struct msm_kms *sde_kms_init(struct drm_device *dev)
  3652. {
  3653. struct msm_drm_private *priv;
  3654. struct sde_kms *sde_kms;
  3655. if (!dev || !dev->dev_private) {
  3656. SDE_ERROR("drm device node invalid\n");
  3657. return ERR_PTR(-EINVAL);
  3658. }
  3659. priv = dev->dev_private;
  3660. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  3661. if (!sde_kms) {
  3662. SDE_ERROR("failed to allocate sde kms\n");
  3663. return ERR_PTR(-ENOMEM);
  3664. }
  3665. msm_kms_init(&sde_kms->base, &kms_funcs);
  3666. sde_kms->dev = dev;
  3667. return &sde_kms->base;
  3668. }
  3669. void sde_kms_vm_trusted_resource_deinit(struct sde_kms *sde_kms)
  3670. {
  3671. struct dsi_display *display;
  3672. struct sde_splash_display *handoff_display;
  3673. int i;
  3674. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3675. handoff_display = &sde_kms->splash_data.splash_display[i];
  3676. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3677. if (handoff_display->cont_splash_enabled)
  3678. _sde_kms_free_splash_display_data(sde_kms,
  3679. handoff_display);
  3680. dsi_display_set_active_state(display, false);
  3681. }
  3682. memset(&sde_kms->splash_data, 0, sizeof(struct sde_splash_data));
  3683. }
  3684. int sde_kms_vm_trusted_resource_init(struct sde_kms *sde_kms)
  3685. {
  3686. struct drm_device *dev;
  3687. struct msm_drm_private *priv;
  3688. struct sde_splash_display *handoff_display;
  3689. struct dsi_display *display;
  3690. int ret, i;
  3691. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  3692. SDE_ERROR("invalid params\n");
  3693. return -EINVAL;
  3694. }
  3695. if (sde_kms->dsi_display_count != 1) {
  3696. SDE_ERROR("no. of displays not supported:%d\n",
  3697. sde_kms->dsi_display_count);
  3698. return -EINVAL;
  3699. }
  3700. dev = sde_kms->dev;
  3701. priv = dev->dev_private;
  3702. sde_kms->splash_data.type = SDE_VM_HANDOFF;
  3703. sde_kms->splash_data.num_splash_displays = sde_kms->dsi_display_count;
  3704. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3705. &sde_kms->splash_data, sde_kms->catalog);
  3706. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3707. handoff_display = &sde_kms->splash_data.splash_display[i];
  3708. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3709. if (!handoff_display->cont_splash_enabled || ret)
  3710. _sde_kms_free_splash_display_data(sde_kms,
  3711. handoff_display);
  3712. else
  3713. dsi_display_set_active_state(display, true);
  3714. }
  3715. ret = sde_kms_cont_splash_config(&sde_kms->base);
  3716. if (ret) {
  3717. SDE_ERROR("error in setting handoff configs\n");
  3718. goto error;
  3719. }
  3720. /**
  3721. * fill-in vote for the continuous splash hanodff path, which will be
  3722. * removed on the successful first commit.
  3723. */
  3724. pm_runtime_get_sync(sde_kms->dev->dev);
  3725. return 0;
  3726. error:
  3727. sde_kms_vm_trusted_resource_deinit(sde_kms);
  3728. return ret;
  3729. }
  3730. static int _sde_kms_register_events(struct msm_kms *kms,
  3731. struct drm_mode_object *obj, u32 event, bool en)
  3732. {
  3733. int ret = 0;
  3734. struct drm_crtc *crtc = NULL;
  3735. struct drm_connector *conn = NULL;
  3736. struct sde_kms *sde_kms = NULL;
  3737. if (!kms || !obj) {
  3738. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  3739. return -EINVAL;
  3740. }
  3741. sde_kms = to_sde_kms(kms);
  3742. switch (obj->type) {
  3743. case DRM_MODE_OBJECT_CRTC:
  3744. crtc = obj_to_crtc(obj);
  3745. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  3746. break;
  3747. case DRM_MODE_OBJECT_CONNECTOR:
  3748. conn = obj_to_connector(obj);
  3749. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  3750. en);
  3751. break;
  3752. }
  3753. return ret;
  3754. }
  3755. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  3756. {
  3757. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  3758. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  3759. }