dp_tx.c 143 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef ATH_SUPPORT_IQUE
  37. #include "dp_txrx_me.h"
  38. #endif
  39. #include "dp_hist.h"
  40. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  41. #include <dp_swlm.h>
  42. #endif
  43. #ifdef WIFI_MONITOR_SUPPORT
  44. #include <dp_mon.h>
  45. #endif
  46. #ifdef FEATURE_WDS
  47. #include "dp_txrx_wds.h"
  48. #endif
  49. /* Flag to skip CCE classify when mesh or tid override enabled */
  50. #define DP_TX_SKIP_CCE_CLASSIFY \
  51. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  52. /* TODO Add support in TSO */
  53. #define DP_DESC_NUM_FRAG(x) 0
  54. /* disable TQM_BYPASS */
  55. #define TQM_BYPASS_WAR 0
  56. /* invalid peer id for reinject*/
  57. #define DP_INVALID_PEER 0XFFFE
  58. #ifdef CONFIG_WLAN_SYSFS_MEM_STATS
  59. /**
  60. * dp_update_tx_desc_stats - Update the increase or decrease in
  61. * outstanding tx desc count
  62. * values on pdev and soc
  63. * @vdev: DP pdev handle
  64. *
  65. * Return: void
  66. */
  67. static inline void
  68. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  69. {
  70. int32_t tx_descs_cnt =
  71. qdf_atomic_read(&pdev->num_tx_outstanding);
  72. if (pdev->tx_descs_max < tx_descs_cnt)
  73. pdev->tx_descs_max = tx_descs_cnt;
  74. qdf_mem_tx_desc_cnt_update(pdev->num_tx_outstanding,
  75. pdev->tx_descs_max);
  76. }
  77. #else /* CONFIG_WLAN_SYSFS_MEM_STATS */
  78. static inline void
  79. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  80. {
  81. }
  82. #endif /* CONFIG_WLAN_SYSFS_MEM_STATS */
  83. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  84. static inline
  85. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  86. {
  87. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  88. QDF_DMA_TO_DEVICE,
  89. desc->nbuf->len);
  90. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  91. }
  92. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  93. {
  94. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  95. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  96. QDF_DMA_TO_DEVICE,
  97. desc->nbuf->len);
  98. }
  99. #else
  100. static inline
  101. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  102. {
  103. }
  104. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  105. {
  106. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  107. QDF_DMA_TO_DEVICE, desc->nbuf->len);
  108. }
  109. #endif
  110. #ifdef QCA_TX_LIMIT_CHECK
  111. /**
  112. * dp_tx_limit_check - Check if allocated tx descriptors reached
  113. * soc max limit and pdev max limit
  114. * @vdev: DP vdev handle
  115. *
  116. * Return: true if allocated tx descriptors reached max configured value, else
  117. * false
  118. */
  119. static inline bool
  120. dp_tx_limit_check(struct dp_vdev *vdev)
  121. {
  122. struct dp_pdev *pdev = vdev->pdev;
  123. struct dp_soc *soc = pdev->soc;
  124. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  125. soc->num_tx_allowed) {
  126. dp_tx_info("queued packets are more than max tx, drop the frame");
  127. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  128. return true;
  129. }
  130. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  131. pdev->num_tx_allowed) {
  132. dp_tx_info("queued packets are more than max tx, drop the frame");
  133. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  134. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_outstand.num, 1);
  135. return true;
  136. }
  137. return false;
  138. }
  139. /**
  140. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  141. * reached soc max limit
  142. * @vdev: DP vdev handle
  143. *
  144. * Return: true if allocated tx descriptors reached max configured value, else
  145. * false
  146. */
  147. static inline bool
  148. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  149. {
  150. struct dp_pdev *pdev = vdev->pdev;
  151. struct dp_soc *soc = pdev->soc;
  152. if (qdf_atomic_read(&soc->num_tx_exception) >=
  153. soc->num_msdu_exception_desc) {
  154. dp_info("exc packets are more than max drop the exc pkt");
  155. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  156. return true;
  157. }
  158. return false;
  159. }
  160. /**
  161. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  162. * @vdev: DP pdev handle
  163. *
  164. * Return: void
  165. */
  166. static inline void
  167. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  168. {
  169. struct dp_soc *soc = pdev->soc;
  170. qdf_atomic_inc(&pdev->num_tx_outstanding);
  171. qdf_atomic_inc(&soc->num_tx_outstanding);
  172. dp_update_tx_desc_stats(pdev);
  173. }
  174. /**
  175. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  176. * @vdev: DP pdev handle
  177. *
  178. * Return: void
  179. */
  180. static inline void
  181. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  182. {
  183. struct dp_soc *soc = pdev->soc;
  184. qdf_atomic_dec(&pdev->num_tx_outstanding);
  185. qdf_atomic_dec(&soc->num_tx_outstanding);
  186. dp_update_tx_desc_stats(pdev);
  187. }
  188. #else //QCA_TX_LIMIT_CHECK
  189. static inline bool
  190. dp_tx_limit_check(struct dp_vdev *vdev)
  191. {
  192. return false;
  193. }
  194. static inline bool
  195. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  196. {
  197. return false;
  198. }
  199. static inline void
  200. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  201. {
  202. qdf_atomic_inc(&pdev->num_tx_outstanding);
  203. dp_update_tx_desc_stats(pdev);
  204. }
  205. static inline void
  206. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  207. {
  208. qdf_atomic_dec(&pdev->num_tx_outstanding);
  209. dp_update_tx_desc_stats(pdev);
  210. }
  211. #endif //QCA_TX_LIMIT_CHECK
  212. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  213. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  214. {
  215. enum dp_tx_event_type type;
  216. if (flags & DP_TX_DESC_FLAG_FLUSH)
  217. type = DP_TX_DESC_FLUSH;
  218. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  219. type = DP_TX_COMP_UNMAP_ERR;
  220. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  221. type = DP_TX_COMP_UNMAP;
  222. else
  223. type = DP_TX_DESC_UNMAP;
  224. return type;
  225. }
  226. static inline void
  227. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  228. qdf_nbuf_t skb, uint32_t sw_cookie,
  229. enum dp_tx_event_type type)
  230. {
  231. struct dp_tx_desc_event *entry;
  232. uint32_t idx;
  233. if (qdf_unlikely(!soc->tx_tcl_history || !soc->tx_comp_history))
  234. return;
  235. switch (type) {
  236. case DP_TX_COMP_UNMAP:
  237. case DP_TX_COMP_UNMAP_ERR:
  238. case DP_TX_COMP_MSDU_EXT:
  239. idx = dp_history_get_next_index(&soc->tx_comp_history->index,
  240. DP_TX_COMP_HISTORY_SIZE);
  241. entry = &soc->tx_comp_history->entry[idx];
  242. break;
  243. case DP_TX_DESC_MAP:
  244. case DP_TX_DESC_UNMAP:
  245. case DP_TX_DESC_COOKIE:
  246. case DP_TX_DESC_FLUSH:
  247. idx = dp_history_get_next_index(&soc->tx_tcl_history->index,
  248. DP_TX_TCL_HISTORY_SIZE);
  249. entry = &soc->tx_tcl_history->entry[idx];
  250. break;
  251. default:
  252. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  253. return;
  254. }
  255. entry->skb = skb;
  256. entry->paddr = paddr;
  257. entry->sw_cookie = sw_cookie;
  258. entry->type = type;
  259. entry->ts = qdf_get_log_timestamp();
  260. }
  261. static inline void
  262. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  263. struct qdf_tso_seg_elem_t *tso_seg,
  264. qdf_nbuf_t skb, uint32_t sw_cookie,
  265. enum dp_tx_event_type type)
  266. {
  267. int i;
  268. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  269. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  270. skb, sw_cookie, type);
  271. }
  272. if (!tso_seg->next)
  273. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  274. skb, 0xFFFFFFFF, type);
  275. }
  276. static inline void
  277. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  278. qdf_nbuf_t skb, uint32_t sw_cookie,
  279. enum dp_tx_event_type type)
  280. {
  281. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  282. uint32_t num_segs = tso_info.num_segs;
  283. while (num_segs) {
  284. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  285. curr_seg = curr_seg->next;
  286. num_segs--;
  287. }
  288. }
  289. #else
  290. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  291. {
  292. return DP_TX_DESC_INVAL_EVT;
  293. }
  294. static inline void
  295. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  296. qdf_nbuf_t skb, uint32_t sw_cookie,
  297. enum dp_tx_event_type type)
  298. {
  299. }
  300. static inline void
  301. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  302. struct qdf_tso_seg_elem_t *tso_seg,
  303. qdf_nbuf_t skb, uint32_t sw_cookie,
  304. enum dp_tx_event_type type)
  305. {
  306. }
  307. static inline void
  308. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  309. qdf_nbuf_t skb, uint32_t sw_cookie,
  310. enum dp_tx_event_type type)
  311. {
  312. }
  313. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  314. #if defined(FEATURE_TSO)
  315. /**
  316. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  317. *
  318. * @soc - core txrx main context
  319. * @seg_desc - tso segment descriptor
  320. * @num_seg_desc - tso number segment descriptor
  321. */
  322. static void dp_tx_tso_unmap_segment(
  323. struct dp_soc *soc,
  324. struct qdf_tso_seg_elem_t *seg_desc,
  325. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  326. {
  327. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  328. if (qdf_unlikely(!seg_desc)) {
  329. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  330. __func__, __LINE__);
  331. qdf_assert(0);
  332. } else if (qdf_unlikely(!num_seg_desc)) {
  333. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  334. __func__, __LINE__);
  335. qdf_assert(0);
  336. } else {
  337. bool is_last_seg;
  338. /* no tso segment left to do dma unmap */
  339. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  340. return;
  341. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  342. true : false;
  343. qdf_nbuf_unmap_tso_segment(soc->osdev,
  344. seg_desc, is_last_seg);
  345. num_seg_desc->num_seg.tso_cmn_num_seg--;
  346. }
  347. }
  348. /**
  349. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  350. * back to the freelist
  351. *
  352. * @soc - soc device handle
  353. * @tx_desc - Tx software descriptor
  354. */
  355. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  356. struct dp_tx_desc_s *tx_desc)
  357. {
  358. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  359. if (qdf_unlikely(!tx_desc->tso_desc)) {
  360. dp_tx_err("SO desc is NULL!");
  361. qdf_assert(0);
  362. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  363. dp_tx_err("TSO num desc is NULL!");
  364. qdf_assert(0);
  365. } else {
  366. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  367. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  368. /* Add the tso num segment into the free list */
  369. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  370. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  371. tx_desc->tso_num_desc);
  372. tx_desc->tso_num_desc = NULL;
  373. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  374. }
  375. /* Add the tso segment into the free list*/
  376. dp_tx_tso_desc_free(soc,
  377. tx_desc->pool_id, tx_desc->tso_desc);
  378. tx_desc->tso_desc = NULL;
  379. }
  380. }
  381. #else
  382. static void dp_tx_tso_unmap_segment(
  383. struct dp_soc *soc,
  384. struct qdf_tso_seg_elem_t *seg_desc,
  385. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  386. {
  387. }
  388. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  389. struct dp_tx_desc_s *tx_desc)
  390. {
  391. }
  392. #endif
  393. /**
  394. * dp_tx_desc_release() - Release Tx Descriptor
  395. * @tx_desc : Tx Descriptor
  396. * @desc_pool_id: Descriptor Pool ID
  397. *
  398. * Deallocate all resources attached to Tx descriptor and free the Tx
  399. * descriptor.
  400. *
  401. * Return:
  402. */
  403. static void
  404. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  405. {
  406. struct dp_pdev *pdev = tx_desc->pdev;
  407. struct dp_soc *soc;
  408. uint8_t comp_status = 0;
  409. qdf_assert(pdev);
  410. soc = pdev->soc;
  411. dp_tx_outstanding_dec(pdev);
  412. if (tx_desc->frm_type == dp_tx_frm_tso)
  413. dp_tx_tso_desc_release(soc, tx_desc);
  414. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  415. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  416. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  417. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  418. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  419. qdf_atomic_dec(&soc->num_tx_exception);
  420. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  421. tx_desc->buffer_src)
  422. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  423. soc->hal_soc);
  424. else
  425. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  426. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  427. tx_desc->id, comp_status,
  428. qdf_atomic_read(&pdev->num_tx_outstanding));
  429. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  430. return;
  431. }
  432. /**
  433. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  434. * @vdev: DP vdev Handle
  435. * @nbuf: skb
  436. * @msdu_info: msdu_info required to create HTT metadata
  437. *
  438. * Prepares and fills HTT metadata in the frame pre-header for special frames
  439. * that should be transmitted using varying transmit parameters.
  440. * There are 2 VDEV modes that currently needs this special metadata -
  441. * 1) Mesh Mode
  442. * 2) DSRC Mode
  443. *
  444. * Return: HTT metadata size
  445. *
  446. */
  447. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  448. struct dp_tx_msdu_info_s *msdu_info)
  449. {
  450. uint32_t *meta_data = msdu_info->meta_data;
  451. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  452. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  453. uint8_t htt_desc_size;
  454. /* Size rounded of multiple of 8 bytes */
  455. uint8_t htt_desc_size_aligned;
  456. uint8_t *hdr = NULL;
  457. /*
  458. * Metadata - HTT MSDU Extension header
  459. */
  460. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  461. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  462. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  463. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  464. meta_data[0])) {
  465. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  466. htt_desc_size_aligned)) {
  467. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  468. htt_desc_size_aligned);
  469. if (!nbuf) {
  470. /*
  471. * qdf_nbuf_realloc_headroom won't do skb_clone
  472. * as skb_realloc_headroom does. so, no free is
  473. * needed here.
  474. */
  475. DP_STATS_INC(vdev,
  476. tx_i.dropped.headroom_insufficient,
  477. 1);
  478. qdf_print(" %s[%d] skb_realloc_headroom failed",
  479. __func__, __LINE__);
  480. return 0;
  481. }
  482. }
  483. /* Fill and add HTT metaheader */
  484. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  485. if (!hdr) {
  486. dp_tx_err("Error in filling HTT metadata");
  487. return 0;
  488. }
  489. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  490. } else if (vdev->opmode == wlan_op_mode_ocb) {
  491. /* Todo - Add support for DSRC */
  492. }
  493. return htt_desc_size_aligned;
  494. }
  495. /**
  496. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  497. * @tso_seg: TSO segment to process
  498. * @ext_desc: Pointer to MSDU extension descriptor
  499. *
  500. * Return: void
  501. */
  502. #if defined(FEATURE_TSO)
  503. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  504. void *ext_desc)
  505. {
  506. uint8_t num_frag;
  507. uint32_t tso_flags;
  508. /*
  509. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  510. * tcp_flag_mask
  511. *
  512. * Checksum enable flags are set in TCL descriptor and not in Extension
  513. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  514. */
  515. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  516. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  517. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  518. tso_seg->tso_flags.ip_len);
  519. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  520. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  521. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  522. uint32_t lo = 0;
  523. uint32_t hi = 0;
  524. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  525. (tso_seg->tso_frags[num_frag].length));
  526. qdf_dmaaddr_to_32s(
  527. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  528. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  529. tso_seg->tso_frags[num_frag].length);
  530. }
  531. return;
  532. }
  533. #else
  534. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  535. void *ext_desc)
  536. {
  537. return;
  538. }
  539. #endif
  540. #if defined(FEATURE_TSO)
  541. /**
  542. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  543. * allocated and free them
  544. *
  545. * @soc: soc handle
  546. * @free_seg: list of tso segments
  547. * @msdu_info: msdu descriptor
  548. *
  549. * Return - void
  550. */
  551. static void dp_tx_free_tso_seg_list(
  552. struct dp_soc *soc,
  553. struct qdf_tso_seg_elem_t *free_seg,
  554. struct dp_tx_msdu_info_s *msdu_info)
  555. {
  556. struct qdf_tso_seg_elem_t *next_seg;
  557. while (free_seg) {
  558. next_seg = free_seg->next;
  559. dp_tx_tso_desc_free(soc,
  560. msdu_info->tx_queue.desc_pool_id,
  561. free_seg);
  562. free_seg = next_seg;
  563. }
  564. }
  565. /**
  566. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  567. * allocated and free them
  568. *
  569. * @soc: soc handle
  570. * @free_num_seg: list of tso number segments
  571. * @msdu_info: msdu descriptor
  572. * Return - void
  573. */
  574. static void dp_tx_free_tso_num_seg_list(
  575. struct dp_soc *soc,
  576. struct qdf_tso_num_seg_elem_t *free_num_seg,
  577. struct dp_tx_msdu_info_s *msdu_info)
  578. {
  579. struct qdf_tso_num_seg_elem_t *next_num_seg;
  580. while (free_num_seg) {
  581. next_num_seg = free_num_seg->next;
  582. dp_tso_num_seg_free(soc,
  583. msdu_info->tx_queue.desc_pool_id,
  584. free_num_seg);
  585. free_num_seg = next_num_seg;
  586. }
  587. }
  588. /**
  589. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  590. * do dma unmap for each segment
  591. *
  592. * @soc: soc handle
  593. * @free_seg: list of tso segments
  594. * @num_seg_desc: tso number segment descriptor
  595. *
  596. * Return - void
  597. */
  598. static void dp_tx_unmap_tso_seg_list(
  599. struct dp_soc *soc,
  600. struct qdf_tso_seg_elem_t *free_seg,
  601. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  602. {
  603. struct qdf_tso_seg_elem_t *next_seg;
  604. if (qdf_unlikely(!num_seg_desc)) {
  605. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  606. return;
  607. }
  608. while (free_seg) {
  609. next_seg = free_seg->next;
  610. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  611. free_seg = next_seg;
  612. }
  613. }
  614. #ifdef FEATURE_TSO_STATS
  615. /**
  616. * dp_tso_get_stats_idx: Retrieve the tso packet id
  617. * @pdev - pdev handle
  618. *
  619. * Return: id
  620. */
  621. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  622. {
  623. uint32_t stats_idx;
  624. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  625. % CDP_MAX_TSO_PACKETS);
  626. return stats_idx;
  627. }
  628. #else
  629. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  630. {
  631. return 0;
  632. }
  633. #endif /* FEATURE_TSO_STATS */
  634. /**
  635. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  636. * free the tso segments descriptor and
  637. * tso num segments descriptor
  638. *
  639. * @soc: soc handle
  640. * @msdu_info: msdu descriptor
  641. * @tso_seg_unmap: flag to show if dma unmap is necessary
  642. *
  643. * Return - void
  644. */
  645. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  646. struct dp_tx_msdu_info_s *msdu_info,
  647. bool tso_seg_unmap)
  648. {
  649. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  650. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  651. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  652. tso_info->tso_num_seg_list;
  653. /* do dma unmap for each segment */
  654. if (tso_seg_unmap)
  655. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  656. /* free all tso number segment descriptor though looks only have 1 */
  657. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  658. /* free all tso segment descriptor */
  659. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  660. }
  661. /**
  662. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  663. * @vdev: virtual device handle
  664. * @msdu: network buffer
  665. * @msdu_info: meta data associated with the msdu
  666. *
  667. * Return: QDF_STATUS_SUCCESS success
  668. */
  669. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  670. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  671. {
  672. struct qdf_tso_seg_elem_t *tso_seg;
  673. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  674. struct dp_soc *soc = vdev->pdev->soc;
  675. struct dp_pdev *pdev = vdev->pdev;
  676. struct qdf_tso_info_t *tso_info;
  677. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  678. tso_info = &msdu_info->u.tso_info;
  679. tso_info->curr_seg = NULL;
  680. tso_info->tso_seg_list = NULL;
  681. tso_info->num_segs = num_seg;
  682. msdu_info->frm_type = dp_tx_frm_tso;
  683. tso_info->tso_num_seg_list = NULL;
  684. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  685. while (num_seg) {
  686. tso_seg = dp_tx_tso_desc_alloc(
  687. soc, msdu_info->tx_queue.desc_pool_id);
  688. if (tso_seg) {
  689. tso_seg->next = tso_info->tso_seg_list;
  690. tso_info->tso_seg_list = tso_seg;
  691. num_seg--;
  692. } else {
  693. dp_err_rl("Failed to alloc tso seg desc");
  694. DP_STATS_INC_PKT(vdev->pdev,
  695. tso_stats.tso_no_mem_dropped, 1,
  696. qdf_nbuf_len(msdu));
  697. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  698. return QDF_STATUS_E_NOMEM;
  699. }
  700. }
  701. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  702. tso_num_seg = dp_tso_num_seg_alloc(soc,
  703. msdu_info->tx_queue.desc_pool_id);
  704. if (tso_num_seg) {
  705. tso_num_seg->next = tso_info->tso_num_seg_list;
  706. tso_info->tso_num_seg_list = tso_num_seg;
  707. } else {
  708. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  709. __func__);
  710. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  711. return QDF_STATUS_E_NOMEM;
  712. }
  713. msdu_info->num_seg =
  714. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  715. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  716. msdu_info->num_seg);
  717. if (!(msdu_info->num_seg)) {
  718. /*
  719. * Free allocated TSO seg desc and number seg desc,
  720. * do unmap for segments if dma map has done.
  721. */
  722. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  723. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  724. return QDF_STATUS_E_INVAL;
  725. }
  726. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  727. msdu, 0, DP_TX_DESC_MAP);
  728. tso_info->curr_seg = tso_info->tso_seg_list;
  729. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  730. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  731. msdu, msdu_info->num_seg);
  732. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  733. tso_info->msdu_stats_idx);
  734. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  735. return QDF_STATUS_SUCCESS;
  736. }
  737. #else
  738. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  739. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  740. {
  741. return QDF_STATUS_E_NOMEM;
  742. }
  743. #endif
  744. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  745. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  746. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  747. /**
  748. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  749. * @vdev: DP Vdev handle
  750. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  751. * @desc_pool_id: Descriptor Pool ID
  752. *
  753. * Return:
  754. */
  755. static
  756. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  757. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  758. {
  759. uint8_t i;
  760. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  761. struct dp_tx_seg_info_s *seg_info;
  762. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  763. struct dp_soc *soc = vdev->pdev->soc;
  764. /* Allocate an extension descriptor */
  765. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  766. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  767. if (!msdu_ext_desc) {
  768. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  769. return NULL;
  770. }
  771. if (msdu_info->exception_fw &&
  772. qdf_unlikely(vdev->mesh_vdev)) {
  773. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  774. &msdu_info->meta_data[0],
  775. sizeof(struct htt_tx_msdu_desc_ext2_t));
  776. qdf_atomic_inc(&soc->num_tx_exception);
  777. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  778. }
  779. switch (msdu_info->frm_type) {
  780. case dp_tx_frm_sg:
  781. case dp_tx_frm_me:
  782. case dp_tx_frm_raw:
  783. seg_info = msdu_info->u.sg_info.curr_seg;
  784. /* Update the buffer pointers in MSDU Extension Descriptor */
  785. for (i = 0; i < seg_info->frag_cnt; i++) {
  786. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  787. seg_info->frags[i].paddr_lo,
  788. seg_info->frags[i].paddr_hi,
  789. seg_info->frags[i].len);
  790. }
  791. break;
  792. case dp_tx_frm_tso:
  793. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  794. &cached_ext_desc[0]);
  795. break;
  796. default:
  797. break;
  798. }
  799. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  800. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  801. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  802. msdu_ext_desc->vaddr);
  803. return msdu_ext_desc;
  804. }
  805. /**
  806. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  807. *
  808. * @skb: skb to be traced
  809. * @msdu_id: msdu_id of the packet
  810. * @vdev_id: vdev_id of the packet
  811. *
  812. * Return: None
  813. */
  814. #ifdef DP_DISABLE_TX_PKT_TRACE
  815. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  816. uint8_t vdev_id)
  817. {
  818. }
  819. #else
  820. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  821. uint8_t vdev_id)
  822. {
  823. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  824. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  825. DPTRACE(qdf_dp_trace_ptr(skb,
  826. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  827. QDF_TRACE_DEFAULT_PDEV_ID,
  828. qdf_nbuf_data_addr(skb),
  829. sizeof(qdf_nbuf_data(skb)),
  830. msdu_id, vdev_id, 0));
  831. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  832. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  833. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  834. msdu_id, QDF_TX));
  835. }
  836. #endif
  837. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  838. /**
  839. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  840. * exception by the upper layer (OS_IF)
  841. * @soc: DP soc handle
  842. * @nbuf: packet to be transmitted
  843. *
  844. * Returns: 1 if the packet is marked as exception,
  845. * 0, if the packet is not marked as exception.
  846. */
  847. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  848. qdf_nbuf_t nbuf)
  849. {
  850. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  851. }
  852. #else
  853. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  854. qdf_nbuf_t nbuf)
  855. {
  856. return 0;
  857. }
  858. #endif
  859. /**
  860. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  861. * @vdev: DP vdev handle
  862. * @nbuf: skb
  863. * @desc_pool_id: Descriptor pool ID
  864. * @meta_data: Metadata to the fw
  865. * @tx_exc_metadata: Handle that holds exception path metadata
  866. * Allocate and prepare Tx descriptor with msdu information.
  867. *
  868. * Return: Pointer to Tx Descriptor on success,
  869. * NULL on failure
  870. */
  871. static
  872. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  873. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  874. struct dp_tx_msdu_info_s *msdu_info,
  875. struct cdp_tx_exception_metadata *tx_exc_metadata)
  876. {
  877. uint8_t align_pad;
  878. uint8_t is_exception = 0;
  879. uint8_t htt_hdr_size;
  880. struct dp_tx_desc_s *tx_desc;
  881. struct dp_pdev *pdev = vdev->pdev;
  882. struct dp_soc *soc = pdev->soc;
  883. if (dp_tx_limit_check(vdev))
  884. return NULL;
  885. /* Allocate software Tx descriptor */
  886. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  887. if (qdf_unlikely(!tx_desc)) {
  888. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  889. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  890. return NULL;
  891. }
  892. dp_tx_outstanding_inc(pdev);
  893. /* Initialize the SW tx descriptor */
  894. tx_desc->nbuf = nbuf;
  895. tx_desc->frm_type = dp_tx_frm_std;
  896. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  897. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  898. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  899. tx_desc->vdev_id = vdev->vdev_id;
  900. tx_desc->pdev = pdev;
  901. tx_desc->msdu_ext_desc = NULL;
  902. tx_desc->pkt_offset = 0;
  903. tx_desc->length = qdf_nbuf_headlen(nbuf);
  904. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  905. if (qdf_unlikely(vdev->multipass_en)) {
  906. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  907. goto failure;
  908. }
  909. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  910. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  911. is_exception = 1;
  912. /*
  913. * For special modes (vdev_type == ocb or mesh), data frames should be
  914. * transmitted using varying transmit parameters (tx spec) which include
  915. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  916. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  917. * These frames are sent as exception packets to firmware.
  918. *
  919. * HW requirement is that metadata should always point to a
  920. * 8-byte aligned address. So we add alignment pad to start of buffer.
  921. * HTT Metadata should be ensured to be multiple of 8-bytes,
  922. * to get 8-byte aligned start address along with align_pad added
  923. *
  924. * |-----------------------------|
  925. * | |
  926. * |-----------------------------| <-----Buffer Pointer Address given
  927. * | | ^ in HW descriptor (aligned)
  928. * | HTT Metadata | |
  929. * | | |
  930. * | | | Packet Offset given in descriptor
  931. * | | |
  932. * |-----------------------------| |
  933. * | Alignment Pad | v
  934. * |-----------------------------| <----- Actual buffer start address
  935. * | SKB Data | (Unaligned)
  936. * | |
  937. * | |
  938. * | |
  939. * | |
  940. * | |
  941. * |-----------------------------|
  942. */
  943. if (qdf_unlikely((msdu_info->exception_fw)) ||
  944. (vdev->opmode == wlan_op_mode_ocb) ||
  945. (tx_exc_metadata &&
  946. tx_exc_metadata->is_tx_sniffer)) {
  947. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  948. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  949. DP_STATS_INC(vdev,
  950. tx_i.dropped.headroom_insufficient, 1);
  951. goto failure;
  952. }
  953. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  954. dp_tx_err("qdf_nbuf_push_head failed");
  955. goto failure;
  956. }
  957. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  958. msdu_info);
  959. if (htt_hdr_size == 0)
  960. goto failure;
  961. tx_desc->length = qdf_nbuf_headlen(nbuf);
  962. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  963. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  964. is_exception = 1;
  965. tx_desc->length -= tx_desc->pkt_offset;
  966. }
  967. #if !TQM_BYPASS_WAR
  968. if (is_exception || tx_exc_metadata)
  969. #endif
  970. {
  971. /* Temporary WAR due to TQM VP issues */
  972. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  973. qdf_atomic_inc(&soc->num_tx_exception);
  974. }
  975. return tx_desc;
  976. failure:
  977. dp_tx_desc_release(tx_desc, desc_pool_id);
  978. return NULL;
  979. }
  980. /**
  981. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  982. * @vdev: DP vdev handle
  983. * @nbuf: skb
  984. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  985. * @desc_pool_id : Descriptor Pool ID
  986. *
  987. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  988. * information. For frames wth fragments, allocate and prepare
  989. * an MSDU extension descriptor
  990. *
  991. * Return: Pointer to Tx Descriptor on success,
  992. * NULL on failure
  993. */
  994. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  995. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  996. uint8_t desc_pool_id)
  997. {
  998. struct dp_tx_desc_s *tx_desc;
  999. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1000. struct dp_pdev *pdev = vdev->pdev;
  1001. struct dp_soc *soc = pdev->soc;
  1002. if (dp_tx_limit_check(vdev))
  1003. return NULL;
  1004. /* Allocate software Tx descriptor */
  1005. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1006. if (!tx_desc) {
  1007. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1008. return NULL;
  1009. }
  1010. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1011. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1012. dp_tx_outstanding_inc(pdev);
  1013. /* Initialize the SW tx descriptor */
  1014. tx_desc->nbuf = nbuf;
  1015. tx_desc->frm_type = msdu_info->frm_type;
  1016. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1017. tx_desc->vdev_id = vdev->vdev_id;
  1018. tx_desc->pdev = pdev;
  1019. tx_desc->pkt_offset = 0;
  1020. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1021. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1022. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  1023. /* Handle scattered frames - TSO/SG/ME */
  1024. /* Allocate and prepare an extension descriptor for scattered frames */
  1025. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1026. if (!msdu_ext_desc) {
  1027. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1028. goto failure;
  1029. }
  1030. #if TQM_BYPASS_WAR
  1031. /* Temporary WAR due to TQM VP issues */
  1032. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1033. qdf_atomic_inc(&soc->num_tx_exception);
  1034. #endif
  1035. if (qdf_unlikely(msdu_info->exception_fw))
  1036. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1037. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1038. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1039. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1040. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1041. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1042. else
  1043. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1044. return tx_desc;
  1045. failure:
  1046. dp_tx_desc_release(tx_desc, desc_pool_id);
  1047. return NULL;
  1048. }
  1049. /**
  1050. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1051. * @vdev: DP vdev handle
  1052. * @nbuf: buffer pointer
  1053. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1054. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1055. * descriptor
  1056. *
  1057. * Return:
  1058. */
  1059. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1060. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1061. {
  1062. qdf_nbuf_t curr_nbuf = NULL;
  1063. uint16_t total_len = 0;
  1064. qdf_dma_addr_t paddr;
  1065. int32_t i;
  1066. int32_t mapped_buf_num = 0;
  1067. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1068. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1069. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1070. /* Continue only if frames are of DATA type */
  1071. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1072. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1073. dp_tx_debug("Pkt. recd is of not data type");
  1074. goto error;
  1075. }
  1076. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1077. if (vdev->raw_mode_war &&
  1078. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1079. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1080. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1081. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1082. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1083. /*
  1084. * Number of nbuf's must not exceed the size of the frags
  1085. * array in seg_info.
  1086. */
  1087. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1088. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1089. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1090. goto error;
  1091. }
  1092. if (QDF_STATUS_SUCCESS !=
  1093. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1094. curr_nbuf,
  1095. QDF_DMA_TO_DEVICE,
  1096. curr_nbuf->len)) {
  1097. dp_tx_err("%s dma map error ", __func__);
  1098. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1099. goto error;
  1100. }
  1101. /* Update the count of mapped nbuf's */
  1102. mapped_buf_num++;
  1103. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1104. seg_info->frags[i].paddr_lo = paddr;
  1105. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1106. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1107. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1108. total_len += qdf_nbuf_len(curr_nbuf);
  1109. }
  1110. seg_info->frag_cnt = i;
  1111. seg_info->total_len = total_len;
  1112. seg_info->next = NULL;
  1113. sg_info->curr_seg = seg_info;
  1114. msdu_info->frm_type = dp_tx_frm_raw;
  1115. msdu_info->num_seg = 1;
  1116. return nbuf;
  1117. error:
  1118. i = 0;
  1119. while (nbuf) {
  1120. curr_nbuf = nbuf;
  1121. if (i < mapped_buf_num) {
  1122. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1123. QDF_DMA_TO_DEVICE,
  1124. curr_nbuf->len);
  1125. i++;
  1126. }
  1127. nbuf = qdf_nbuf_next(nbuf);
  1128. qdf_nbuf_free(curr_nbuf);
  1129. }
  1130. return NULL;
  1131. }
  1132. /**
  1133. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1134. * @soc: DP soc handle
  1135. * @nbuf: Buffer pointer
  1136. *
  1137. * unmap the chain of nbufs that belong to this RAW frame.
  1138. *
  1139. * Return: None
  1140. */
  1141. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1142. qdf_nbuf_t nbuf)
  1143. {
  1144. qdf_nbuf_t cur_nbuf = nbuf;
  1145. do {
  1146. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1147. QDF_DMA_TO_DEVICE,
  1148. cur_nbuf->len);
  1149. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1150. } while (cur_nbuf);
  1151. }
  1152. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1153. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1154. qdf_nbuf_t nbuf)
  1155. {
  1156. qdf_nbuf_t nbuf_local;
  1157. struct dp_vdev *vdev_local = vdev_hdl;
  1158. do {
  1159. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1160. break;
  1161. nbuf_local = nbuf;
  1162. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1163. htt_cmn_pkt_type_raw))
  1164. break;
  1165. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1166. break;
  1167. else if (qdf_nbuf_is_tso((nbuf_local)))
  1168. break;
  1169. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1170. (nbuf_local),
  1171. NULL, 1, 0);
  1172. } while (0);
  1173. }
  1174. #endif
  1175. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1176. /**
  1177. * dp_tx_update_stats() - Update soc level tx stats
  1178. * @soc: DP soc handle
  1179. * @nbuf: packet being transmitted
  1180. *
  1181. * Returns: none
  1182. */
  1183. void dp_tx_update_stats(struct dp_soc *soc,
  1184. qdf_nbuf_t nbuf)
  1185. {
  1186. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1187. }
  1188. int
  1189. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1190. struct dp_tx_desc_s *tx_desc,
  1191. uint8_t tid)
  1192. {
  1193. struct dp_swlm *swlm = &soc->swlm;
  1194. union swlm_data swlm_query_data;
  1195. struct dp_swlm_tcl_data tcl_data;
  1196. QDF_STATUS status;
  1197. int ret;
  1198. if (qdf_unlikely(!swlm->is_enabled))
  1199. return 0;
  1200. tcl_data.nbuf = tx_desc->nbuf;
  1201. tcl_data.tid = tid;
  1202. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1203. swlm_query_data.tcl_data = &tcl_data;
  1204. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1205. if (QDF_IS_STATUS_ERROR(status)) {
  1206. dp_swlm_tcl_reset_session_data(soc);
  1207. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1208. return 0;
  1209. }
  1210. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1211. if (ret) {
  1212. DP_STATS_INC(swlm, tcl.coalesce_success, 1);
  1213. } else {
  1214. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1215. }
  1216. return ret;
  1217. }
  1218. void
  1219. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1220. int coalesce)
  1221. {
  1222. if (coalesce)
  1223. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1224. else
  1225. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1226. }
  1227. #endif
  1228. #ifdef FEATURE_RUNTIME_PM
  1229. /**
  1230. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1231. * @soc: Datapath soc handle
  1232. * @hal_ring_hdl: HAL ring handle
  1233. * @coalesce: Coalesce the current write or not
  1234. *
  1235. * Wrapper for HAL ring access end for data transmission for
  1236. * FEATURE_RUNTIME_PM
  1237. *
  1238. * Returns: none
  1239. */
  1240. void
  1241. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1242. hal_ring_handle_t hal_ring_hdl,
  1243. int coalesce)
  1244. {
  1245. int ret;
  1246. ret = hif_pm_runtime_get(soc->hif_handle,
  1247. RTPM_ID_DW_TX_HW_ENQUEUE, true);
  1248. switch (ret) {
  1249. case 0:
  1250. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1251. hif_pm_runtime_put(soc->hif_handle,
  1252. RTPM_ID_DW_TX_HW_ENQUEUE);
  1253. break;
  1254. /*
  1255. * If hif_pm_runtime_get returns -EBUSY or -EINPROGRESS,
  1256. * take the dp runtime refcount using dp_runtime_get,
  1257. * check link state,if up, write TX ring HP, else just set flush event.
  1258. * In dp_runtime_resume, wait until dp runtime refcount becomes
  1259. * zero or time out, then flush pending tx.
  1260. */
  1261. case -EBUSY:
  1262. case -EINPROGRESS:
  1263. dp_runtime_get(soc);
  1264. if (hif_pm_get_link_state(soc->hif_handle) ==
  1265. HIF_PM_LINK_STATE_UP) {
  1266. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1267. } else {
  1268. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1269. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1270. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1271. }
  1272. dp_runtime_put(soc);
  1273. break;
  1274. default:
  1275. dp_runtime_get(soc);
  1276. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1277. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1278. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1279. dp_runtime_put(soc);
  1280. }
  1281. }
  1282. #endif
  1283. /**
  1284. * dp_cce_classify() - Classify the frame based on CCE rules
  1285. * @vdev: DP vdev handle
  1286. * @nbuf: skb
  1287. *
  1288. * Classify frames based on CCE rules
  1289. * Return: bool( true if classified,
  1290. * else false)
  1291. */
  1292. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1293. {
  1294. qdf_ether_header_t *eh = NULL;
  1295. uint16_t ether_type;
  1296. qdf_llc_t *llcHdr;
  1297. qdf_nbuf_t nbuf_clone = NULL;
  1298. qdf_dot3_qosframe_t *qos_wh = NULL;
  1299. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1300. /*
  1301. * In case of mesh packets or hlos tid override enabled,
  1302. * don't do any classification
  1303. */
  1304. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1305. & DP_TX_SKIP_CCE_CLASSIFY))
  1306. return false;
  1307. }
  1308. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1309. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1310. ether_type = eh->ether_type;
  1311. llcHdr = (qdf_llc_t *)(nbuf->data +
  1312. sizeof(qdf_ether_header_t));
  1313. } else {
  1314. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1315. /* For encrypted packets don't do any classification */
  1316. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1317. return false;
  1318. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1319. if (qdf_unlikely(
  1320. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1321. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1322. ether_type = *(uint16_t *)(nbuf->data
  1323. + QDF_IEEE80211_4ADDR_HDR_LEN
  1324. + sizeof(qdf_llc_t)
  1325. - sizeof(ether_type));
  1326. llcHdr = (qdf_llc_t *)(nbuf->data +
  1327. QDF_IEEE80211_4ADDR_HDR_LEN);
  1328. } else {
  1329. ether_type = *(uint16_t *)(nbuf->data
  1330. + QDF_IEEE80211_3ADDR_HDR_LEN
  1331. + sizeof(qdf_llc_t)
  1332. - sizeof(ether_type));
  1333. llcHdr = (qdf_llc_t *)(nbuf->data +
  1334. QDF_IEEE80211_3ADDR_HDR_LEN);
  1335. }
  1336. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1337. && (ether_type ==
  1338. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1339. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1340. return true;
  1341. }
  1342. }
  1343. return false;
  1344. }
  1345. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1346. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1347. sizeof(*llcHdr));
  1348. nbuf_clone = qdf_nbuf_clone(nbuf);
  1349. if (qdf_unlikely(nbuf_clone)) {
  1350. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1351. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1352. qdf_nbuf_pull_head(nbuf_clone,
  1353. sizeof(qdf_net_vlanhdr_t));
  1354. }
  1355. }
  1356. } else {
  1357. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1358. nbuf_clone = qdf_nbuf_clone(nbuf);
  1359. if (qdf_unlikely(nbuf_clone)) {
  1360. qdf_nbuf_pull_head(nbuf_clone,
  1361. sizeof(qdf_net_vlanhdr_t));
  1362. }
  1363. }
  1364. }
  1365. if (qdf_unlikely(nbuf_clone))
  1366. nbuf = nbuf_clone;
  1367. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1368. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1369. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1370. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1371. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1372. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1373. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1374. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1375. if (qdf_unlikely(nbuf_clone))
  1376. qdf_nbuf_free(nbuf_clone);
  1377. return true;
  1378. }
  1379. if (qdf_unlikely(nbuf_clone))
  1380. qdf_nbuf_free(nbuf_clone);
  1381. return false;
  1382. }
  1383. /**
  1384. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1385. * @vdev: DP vdev handle
  1386. * @nbuf: skb
  1387. *
  1388. * Extract the DSCP or PCP information from frame and map into TID value.
  1389. *
  1390. * Return: void
  1391. */
  1392. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1393. struct dp_tx_msdu_info_s *msdu_info)
  1394. {
  1395. uint8_t tos = 0, dscp_tid_override = 0;
  1396. uint8_t *hdr_ptr, *L3datap;
  1397. uint8_t is_mcast = 0;
  1398. qdf_ether_header_t *eh = NULL;
  1399. qdf_ethervlan_header_t *evh = NULL;
  1400. uint16_t ether_type;
  1401. qdf_llc_t *llcHdr;
  1402. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1403. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1404. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1405. eh = (qdf_ether_header_t *)nbuf->data;
  1406. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1407. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1408. } else {
  1409. qdf_dot3_qosframe_t *qos_wh =
  1410. (qdf_dot3_qosframe_t *) nbuf->data;
  1411. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1412. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1413. return;
  1414. }
  1415. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1416. ether_type = eh->ether_type;
  1417. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1418. /*
  1419. * Check if packet is dot3 or eth2 type.
  1420. */
  1421. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1422. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1423. sizeof(*llcHdr));
  1424. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1425. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1426. sizeof(*llcHdr);
  1427. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1428. + sizeof(*llcHdr) +
  1429. sizeof(qdf_net_vlanhdr_t));
  1430. } else {
  1431. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1432. sizeof(*llcHdr);
  1433. }
  1434. } else {
  1435. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1436. evh = (qdf_ethervlan_header_t *) eh;
  1437. ether_type = evh->ether_type;
  1438. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1439. }
  1440. }
  1441. /*
  1442. * Find priority from IP TOS DSCP field
  1443. */
  1444. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1445. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1446. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1447. /* Only for unicast frames */
  1448. if (!is_mcast) {
  1449. /* send it on VO queue */
  1450. msdu_info->tid = DP_VO_TID;
  1451. }
  1452. } else {
  1453. /*
  1454. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1455. * from TOS byte.
  1456. */
  1457. tos = ip->ip_tos;
  1458. dscp_tid_override = 1;
  1459. }
  1460. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1461. /* TODO
  1462. * use flowlabel
  1463. *igmpmld cases to be handled in phase 2
  1464. */
  1465. unsigned long ver_pri_flowlabel;
  1466. unsigned long pri;
  1467. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1468. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1469. DP_IPV6_PRIORITY_SHIFT;
  1470. tos = pri;
  1471. dscp_tid_override = 1;
  1472. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1473. msdu_info->tid = DP_VO_TID;
  1474. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1475. /* Only for unicast frames */
  1476. if (!is_mcast) {
  1477. /* send ucast arp on VO queue */
  1478. msdu_info->tid = DP_VO_TID;
  1479. }
  1480. }
  1481. /*
  1482. * Assign all MCAST packets to BE
  1483. */
  1484. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1485. if (is_mcast) {
  1486. tos = 0;
  1487. dscp_tid_override = 1;
  1488. }
  1489. }
  1490. if (dscp_tid_override == 1) {
  1491. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1492. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1493. }
  1494. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1495. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1496. return;
  1497. }
  1498. /**
  1499. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1500. * @vdev: DP vdev handle
  1501. * @nbuf: skb
  1502. *
  1503. * Software based TID classification is required when more than 2 DSCP-TID
  1504. * mapping tables are needed.
  1505. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1506. *
  1507. * Return: void
  1508. */
  1509. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1510. struct dp_tx_msdu_info_s *msdu_info)
  1511. {
  1512. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1513. /*
  1514. * skip_sw_tid_classification flag will set in below cases-
  1515. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1516. * 2. hlos_tid_override enabled for vdev
  1517. * 3. mesh mode enabled for vdev
  1518. */
  1519. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1520. /* Update tid in msdu_info from skb priority */
  1521. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1522. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1523. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1524. return;
  1525. }
  1526. return;
  1527. }
  1528. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1529. }
  1530. #ifdef FEATURE_WLAN_TDLS
  1531. /**
  1532. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1533. * @soc: datapath SOC
  1534. * @vdev: datapath vdev
  1535. * @tx_desc: TX descriptor
  1536. *
  1537. * Return: None
  1538. */
  1539. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1540. struct dp_vdev *vdev,
  1541. struct dp_tx_desc_s *tx_desc)
  1542. {
  1543. if (vdev) {
  1544. if (vdev->is_tdls_frame) {
  1545. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1546. vdev->is_tdls_frame = false;
  1547. }
  1548. }
  1549. }
  1550. /**
  1551. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1552. * @soc: dp_soc handle
  1553. * @tx_desc: TX descriptor
  1554. * @vdev: datapath vdev handle
  1555. *
  1556. * Return: None
  1557. */
  1558. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1559. struct dp_tx_desc_s *tx_desc)
  1560. {
  1561. struct hal_tx_completion_status ts = {0};
  1562. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1563. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1564. DP_MOD_ID_TDLS);
  1565. if (qdf_unlikely(!vdev)) {
  1566. dp_err_rl("vdev is null!");
  1567. goto error;
  1568. }
  1569. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1570. if (vdev->tx_non_std_data_callback.func) {
  1571. qdf_nbuf_set_next(nbuf, NULL);
  1572. vdev->tx_non_std_data_callback.func(
  1573. vdev->tx_non_std_data_callback.ctxt,
  1574. nbuf, ts.status);
  1575. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1576. return;
  1577. } else {
  1578. dp_err_rl("callback func is null");
  1579. }
  1580. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1581. error:
  1582. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1583. qdf_nbuf_free(nbuf);
  1584. }
  1585. /**
  1586. * dp_tx_msdu_single_map() - do nbuf map
  1587. * @vdev: DP vdev handle
  1588. * @tx_desc: DP TX descriptor pointer
  1589. * @nbuf: skb pointer
  1590. *
  1591. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1592. * operation done in other component.
  1593. *
  1594. * Return: QDF_STATUS
  1595. */
  1596. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1597. struct dp_tx_desc_s *tx_desc,
  1598. qdf_nbuf_t nbuf)
  1599. {
  1600. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1601. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1602. nbuf,
  1603. QDF_DMA_TO_DEVICE,
  1604. nbuf->len);
  1605. else
  1606. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1607. QDF_DMA_TO_DEVICE);
  1608. }
  1609. #else
  1610. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1611. struct dp_vdev *vdev,
  1612. struct dp_tx_desc_s *tx_desc)
  1613. {
  1614. }
  1615. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1616. struct dp_tx_desc_s *tx_desc)
  1617. {
  1618. }
  1619. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1620. struct dp_tx_desc_s *tx_desc,
  1621. qdf_nbuf_t nbuf)
  1622. {
  1623. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1624. nbuf,
  1625. QDF_DMA_TO_DEVICE,
  1626. nbuf->len);
  1627. }
  1628. #endif
  1629. #ifdef MESH_MODE_SUPPORT
  1630. /**
  1631. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1632. * @soc: datapath SOC
  1633. * @vdev: datapath vdev
  1634. * @tx_desc: TX descriptor
  1635. *
  1636. * Return: None
  1637. */
  1638. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1639. struct dp_vdev *vdev,
  1640. struct dp_tx_desc_s *tx_desc)
  1641. {
  1642. if (qdf_unlikely(vdev->mesh_vdev))
  1643. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1644. }
  1645. /**
  1646. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1647. * @soc: dp_soc handle
  1648. * @tx_desc: TX descriptor
  1649. * @vdev: datapath vdev handle
  1650. *
  1651. * Return: None
  1652. */
  1653. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1654. struct dp_tx_desc_s *tx_desc)
  1655. {
  1656. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1657. struct dp_vdev *vdev = NULL;
  1658. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1659. qdf_nbuf_free(nbuf);
  1660. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1661. } else {
  1662. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1663. DP_MOD_ID_MESH);
  1664. if (vdev && vdev->osif_tx_free_ext)
  1665. vdev->osif_tx_free_ext((nbuf));
  1666. else
  1667. qdf_nbuf_free(nbuf);
  1668. if (vdev)
  1669. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1670. }
  1671. }
  1672. #else
  1673. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1674. struct dp_vdev *vdev,
  1675. struct dp_tx_desc_s *tx_desc)
  1676. {
  1677. }
  1678. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1679. struct dp_tx_desc_s *tx_desc)
  1680. {
  1681. }
  1682. #endif
  1683. /**
  1684. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1685. * @vdev: DP vdev handle
  1686. * @nbuf: skb
  1687. *
  1688. * Return: 1 if frame needs to be dropped else 0
  1689. */
  1690. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1691. {
  1692. struct dp_pdev *pdev = NULL;
  1693. struct dp_ast_entry *src_ast_entry = NULL;
  1694. struct dp_ast_entry *dst_ast_entry = NULL;
  1695. struct dp_soc *soc = NULL;
  1696. qdf_assert(vdev);
  1697. pdev = vdev->pdev;
  1698. qdf_assert(pdev);
  1699. soc = pdev->soc;
  1700. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1701. (soc, dstmac, vdev->pdev->pdev_id);
  1702. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1703. (soc, srcmac, vdev->pdev->pdev_id);
  1704. if (dst_ast_entry && src_ast_entry) {
  1705. if (dst_ast_entry->peer_id ==
  1706. src_ast_entry->peer_id)
  1707. return 1;
  1708. }
  1709. return 0;
  1710. }
  1711. /**
  1712. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1713. * @vdev: DP vdev handle
  1714. * @nbuf: skb
  1715. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1716. * @meta_data: Metadata to the fw
  1717. * @tx_q: Tx queue to be used for this Tx frame
  1718. * @peer_id: peer_id of the peer in case of NAWDS frames
  1719. * @tx_exc_metadata: Handle that holds exception path metadata
  1720. *
  1721. * Return: NULL on success,
  1722. * nbuf when it fails to send
  1723. */
  1724. qdf_nbuf_t
  1725. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1726. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1727. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1728. {
  1729. struct dp_pdev *pdev = vdev->pdev;
  1730. struct dp_soc *soc = pdev->soc;
  1731. struct dp_tx_desc_s *tx_desc;
  1732. QDF_STATUS status;
  1733. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1734. uint16_t htt_tcl_metadata = 0;
  1735. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1736. uint8_t tid = msdu_info->tid;
  1737. struct cdp_tid_tx_stats *tid_stats = NULL;
  1738. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1739. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1740. msdu_info, tx_exc_metadata);
  1741. if (!tx_desc) {
  1742. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1743. vdev, tx_q->desc_pool_id);
  1744. drop_code = TX_DESC_ERR;
  1745. goto fail_return;
  1746. }
  1747. if (qdf_unlikely(soc->cce_disable)) {
  1748. if (dp_cce_classify(vdev, nbuf) == true) {
  1749. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1750. tid = DP_VO_TID;
  1751. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1752. }
  1753. }
  1754. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1755. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1756. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1757. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1758. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1759. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1760. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1761. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1762. peer_id);
  1763. } else
  1764. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1765. if (msdu_info->exception_fw)
  1766. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1767. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1768. !dp_monitor_is_enable_enhanced_stats(pdev));
  1769. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1770. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1771. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1772. /* Handle failure */
  1773. dp_err("qdf_nbuf_map failed");
  1774. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1775. drop_code = TX_DMA_MAP_ERR;
  1776. goto release_desc;
  1777. }
  1778. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1779. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1780. tx_desc->id, DP_TX_DESC_MAP);
  1781. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1782. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  1783. htt_tcl_metadata,
  1784. tx_exc_metadata, msdu_info);
  1785. if (status != QDF_STATUS_SUCCESS) {
  1786. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1787. tx_desc, tx_q->ring_id);
  1788. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1789. tx_desc->id, DP_TX_DESC_UNMAP);
  1790. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1791. QDF_DMA_TO_DEVICE,
  1792. nbuf->len);
  1793. drop_code = TX_HW_ENQUEUE;
  1794. goto release_desc;
  1795. }
  1796. return NULL;
  1797. release_desc:
  1798. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1799. fail_return:
  1800. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1801. tid_stats = &pdev->stats.tid_stats.
  1802. tid_tx_stats[tx_q->ring_id][tid];
  1803. tid_stats->swdrop_cnt[drop_code]++;
  1804. return nbuf;
  1805. }
  1806. /**
  1807. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1808. * @soc: Soc handle
  1809. * @desc: software Tx descriptor to be processed
  1810. *
  1811. * Return: none
  1812. */
  1813. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1814. struct dp_tx_desc_s *desc)
  1815. {
  1816. qdf_nbuf_t nbuf = desc->nbuf;
  1817. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  1818. /* nbuf already freed in vdev detach path */
  1819. if (!nbuf)
  1820. return;
  1821. /* If it is TDLS mgmt, don't unmap or free the frame */
  1822. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1823. return dp_non_std_tx_comp_free_buff(soc, desc);
  1824. /* 0 : MSDU buffer, 1 : MLE */
  1825. if (desc->msdu_ext_desc) {
  1826. /* TSO free */
  1827. if (hal_tx_ext_desc_get_tso_enable(
  1828. desc->msdu_ext_desc->vaddr)) {
  1829. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  1830. desc->id, DP_TX_COMP_MSDU_EXT);
  1831. dp_tx_tso_seg_history_add(soc, desc->tso_desc,
  1832. desc->nbuf, desc->id, type);
  1833. /* unmap eash TSO seg before free the nbuf */
  1834. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  1835. desc->tso_num_desc);
  1836. qdf_nbuf_free(nbuf);
  1837. return;
  1838. }
  1839. }
  1840. /* If it's ME frame, dont unmap the cloned nbuf's */
  1841. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  1842. goto nbuf_free;
  1843. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  1844. dp_tx_unmap(soc, desc);
  1845. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  1846. return dp_mesh_tx_comp_free_buff(soc, desc);
  1847. nbuf_free:
  1848. qdf_nbuf_free(nbuf);
  1849. }
  1850. /**
  1851. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1852. * @vdev: DP vdev handle
  1853. * @nbuf: skb
  1854. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1855. *
  1856. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1857. *
  1858. * Return: NULL on success,
  1859. * nbuf when it fails to send
  1860. */
  1861. #if QDF_LOCK_STATS
  1862. noinline
  1863. #else
  1864. #endif
  1865. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1866. struct dp_tx_msdu_info_s *msdu_info)
  1867. {
  1868. uint32_t i;
  1869. struct dp_pdev *pdev = vdev->pdev;
  1870. struct dp_soc *soc = pdev->soc;
  1871. struct dp_tx_desc_s *tx_desc;
  1872. bool is_cce_classified = false;
  1873. QDF_STATUS status;
  1874. uint16_t htt_tcl_metadata = 0;
  1875. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1876. struct cdp_tid_tx_stats *tid_stats = NULL;
  1877. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  1878. if (qdf_unlikely(soc->cce_disable)) {
  1879. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1880. if (is_cce_classified) {
  1881. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1882. msdu_info->tid = DP_VO_TID;
  1883. }
  1884. }
  1885. if (msdu_info->frm_type == dp_tx_frm_me)
  1886. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1887. i = 0;
  1888. /* Print statement to track i and num_seg */
  1889. /*
  1890. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1891. * descriptors using information in msdu_info
  1892. */
  1893. while (i < msdu_info->num_seg) {
  1894. /*
  1895. * Setup Tx descriptor for an MSDU, and MSDU extension
  1896. * descriptor
  1897. */
  1898. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1899. tx_q->desc_pool_id);
  1900. if (!tx_desc) {
  1901. if (msdu_info->frm_type == dp_tx_frm_me) {
  1902. prep_desc_fail++;
  1903. dp_tx_me_free_buf(pdev,
  1904. (void *)(msdu_info->u.sg_info
  1905. .curr_seg->frags[0].vaddr));
  1906. if (prep_desc_fail == msdu_info->num_seg) {
  1907. /*
  1908. * Unmap is needed only if descriptor
  1909. * preparation failed for all segments.
  1910. */
  1911. qdf_nbuf_unmap(soc->osdev,
  1912. msdu_info->u.sg_info.
  1913. curr_seg->nbuf,
  1914. QDF_DMA_TO_DEVICE);
  1915. }
  1916. /*
  1917. * Free the nbuf for the current segment
  1918. * and make it point to the next in the list.
  1919. * For me, there are as many segments as there
  1920. * are no of clients.
  1921. */
  1922. qdf_nbuf_free(msdu_info->u.sg_info
  1923. .curr_seg->nbuf);
  1924. if (msdu_info->u.sg_info.curr_seg->next) {
  1925. msdu_info->u.sg_info.curr_seg =
  1926. msdu_info->u.sg_info
  1927. .curr_seg->next;
  1928. nbuf = msdu_info->u.sg_info
  1929. .curr_seg->nbuf;
  1930. }
  1931. i++;
  1932. continue;
  1933. }
  1934. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1935. dp_tx_tso_seg_history_add(
  1936. soc,
  1937. msdu_info->u.tso_info.curr_seg,
  1938. nbuf, 0, DP_TX_DESC_UNMAP);
  1939. dp_tx_tso_unmap_segment(soc,
  1940. msdu_info->u.tso_info.
  1941. curr_seg,
  1942. msdu_info->u.tso_info.
  1943. tso_num_seg_list);
  1944. if (msdu_info->u.tso_info.curr_seg->next) {
  1945. msdu_info->u.tso_info.curr_seg =
  1946. msdu_info->u.tso_info.curr_seg->next;
  1947. i++;
  1948. continue;
  1949. }
  1950. }
  1951. goto done;
  1952. }
  1953. if (msdu_info->frm_type == dp_tx_frm_me) {
  1954. tx_desc->me_buffer =
  1955. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1956. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1957. }
  1958. if (is_cce_classified)
  1959. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1960. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1961. if (msdu_info->exception_fw) {
  1962. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1963. }
  1964. /*
  1965. * For frames with multiple segments (TSO, ME), jump to next
  1966. * segment.
  1967. */
  1968. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1969. if (msdu_info->u.tso_info.curr_seg->next) {
  1970. msdu_info->u.tso_info.curr_seg =
  1971. msdu_info->u.tso_info.curr_seg->next;
  1972. /*
  1973. * If this is a jumbo nbuf, then increment the
  1974. * number of nbuf users for each additional
  1975. * segment of the msdu. This will ensure that
  1976. * the skb is freed only after receiving tx
  1977. * completion for all segments of an nbuf
  1978. */
  1979. qdf_nbuf_inc_users(nbuf);
  1980. /* Check with MCL if this is needed */
  1981. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  1982. */
  1983. }
  1984. }
  1985. /*
  1986. * Enqueue the Tx MSDU descriptor to HW for transmit
  1987. */
  1988. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  1989. htt_tcl_metadata,
  1990. NULL, msdu_info);
  1991. if (status != QDF_STATUS_SUCCESS) {
  1992. dp_info("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1993. tx_desc, tx_q->ring_id);
  1994. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1995. tid_stats = &pdev->stats.tid_stats.
  1996. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1997. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1998. if (msdu_info->frm_type == dp_tx_frm_me) {
  1999. hw_enq_fail++;
  2000. if (hw_enq_fail == msdu_info->num_seg) {
  2001. /*
  2002. * Unmap is needed only if enqueue
  2003. * failed for all segments.
  2004. */
  2005. qdf_nbuf_unmap(soc->osdev,
  2006. msdu_info->u.sg_info.
  2007. curr_seg->nbuf,
  2008. QDF_DMA_TO_DEVICE);
  2009. }
  2010. /*
  2011. * Free the nbuf for the current segment
  2012. * and make it point to the next in the list.
  2013. * For me, there are as many segments as there
  2014. * are no of clients.
  2015. */
  2016. qdf_nbuf_free(msdu_info->u.sg_info
  2017. .curr_seg->nbuf);
  2018. if (msdu_info->u.sg_info.curr_seg->next) {
  2019. msdu_info->u.sg_info.curr_seg =
  2020. msdu_info->u.sg_info
  2021. .curr_seg->next;
  2022. nbuf = msdu_info->u.sg_info
  2023. .curr_seg->nbuf;
  2024. } else
  2025. break;
  2026. i++;
  2027. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2028. continue;
  2029. }
  2030. /*
  2031. * For TSO frames, the nbuf users increment done for
  2032. * the current segment has to be reverted, since the
  2033. * hw enqueue for this segment failed
  2034. */
  2035. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2036. msdu_info->u.tso_info.curr_seg) {
  2037. /*
  2038. * unmap and free current,
  2039. * retransmit remaining segments
  2040. */
  2041. dp_tx_comp_free_buf(soc, tx_desc);
  2042. i++;
  2043. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2044. continue;
  2045. }
  2046. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2047. goto done;
  2048. }
  2049. /*
  2050. * TODO
  2051. * if tso_info structure can be modified to have curr_seg
  2052. * as first element, following 2 blocks of code (for TSO and SG)
  2053. * can be combined into 1
  2054. */
  2055. /*
  2056. * For Multicast-Unicast converted packets,
  2057. * each converted frame (for a client) is represented as
  2058. * 1 segment
  2059. */
  2060. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2061. (msdu_info->frm_type == dp_tx_frm_me)) {
  2062. if (msdu_info->u.sg_info.curr_seg->next) {
  2063. msdu_info->u.sg_info.curr_seg =
  2064. msdu_info->u.sg_info.curr_seg->next;
  2065. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2066. } else
  2067. break;
  2068. }
  2069. i++;
  2070. }
  2071. nbuf = NULL;
  2072. done:
  2073. return nbuf;
  2074. }
  2075. /**
  2076. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2077. * for SG frames
  2078. * @vdev: DP vdev handle
  2079. * @nbuf: skb
  2080. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2081. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2082. *
  2083. * Return: NULL on success,
  2084. * nbuf when it fails to send
  2085. */
  2086. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2087. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2088. {
  2089. uint32_t cur_frag, nr_frags, i;
  2090. qdf_dma_addr_t paddr;
  2091. struct dp_tx_sg_info_s *sg_info;
  2092. sg_info = &msdu_info->u.sg_info;
  2093. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2094. if (QDF_STATUS_SUCCESS !=
  2095. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2096. QDF_DMA_TO_DEVICE,
  2097. qdf_nbuf_headlen(nbuf))) {
  2098. dp_tx_err("dma map error");
  2099. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2100. qdf_nbuf_free(nbuf);
  2101. return NULL;
  2102. }
  2103. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2104. seg_info->frags[0].paddr_lo = paddr;
  2105. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2106. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2107. seg_info->frags[0].vaddr = (void *) nbuf;
  2108. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2109. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  2110. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  2111. dp_tx_err("frag dma map error");
  2112. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2113. goto map_err;
  2114. }
  2115. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2116. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2117. seg_info->frags[cur_frag + 1].paddr_hi =
  2118. ((uint64_t) paddr) >> 32;
  2119. seg_info->frags[cur_frag + 1].len =
  2120. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2121. }
  2122. seg_info->frag_cnt = (cur_frag + 1);
  2123. seg_info->total_len = qdf_nbuf_len(nbuf);
  2124. seg_info->next = NULL;
  2125. sg_info->curr_seg = seg_info;
  2126. msdu_info->frm_type = dp_tx_frm_sg;
  2127. msdu_info->num_seg = 1;
  2128. return nbuf;
  2129. map_err:
  2130. /* restore paddr into nbuf before calling unmap */
  2131. qdf_nbuf_mapped_paddr_set(nbuf,
  2132. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2133. ((uint64_t)
  2134. seg_info->frags[0].paddr_hi) << 32));
  2135. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2136. QDF_DMA_TO_DEVICE,
  2137. seg_info->frags[0].len);
  2138. for (i = 1; i <= cur_frag; i++) {
  2139. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2140. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2141. seg_info->frags[i].paddr_hi) << 32),
  2142. seg_info->frags[i].len,
  2143. QDF_DMA_TO_DEVICE);
  2144. }
  2145. qdf_nbuf_free(nbuf);
  2146. return NULL;
  2147. }
  2148. /**
  2149. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2150. * @vdev: DP vdev handle
  2151. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2152. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2153. *
  2154. * Return: NULL on failure,
  2155. * nbuf when extracted successfully
  2156. */
  2157. static
  2158. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2159. struct dp_tx_msdu_info_s *msdu_info,
  2160. uint16_t ppdu_cookie)
  2161. {
  2162. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2163. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2164. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2165. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2166. (msdu_info->meta_data[5], 1);
  2167. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2168. (msdu_info->meta_data[5], 1);
  2169. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2170. (msdu_info->meta_data[6], ppdu_cookie);
  2171. msdu_info->exception_fw = 1;
  2172. msdu_info->is_tx_sniffer = 1;
  2173. }
  2174. #ifdef MESH_MODE_SUPPORT
  2175. /**
  2176. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2177. and prepare msdu_info for mesh frames.
  2178. * @vdev: DP vdev handle
  2179. * @nbuf: skb
  2180. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2181. *
  2182. * Return: NULL on failure,
  2183. * nbuf when extracted successfully
  2184. */
  2185. static
  2186. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2187. struct dp_tx_msdu_info_s *msdu_info)
  2188. {
  2189. struct meta_hdr_s *mhdr;
  2190. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2191. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2192. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2193. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2194. msdu_info->exception_fw = 0;
  2195. goto remove_meta_hdr;
  2196. }
  2197. msdu_info->exception_fw = 1;
  2198. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2199. meta_data->host_tx_desc_pool = 1;
  2200. meta_data->update_peer_cache = 1;
  2201. meta_data->learning_frame = 1;
  2202. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2203. meta_data->power = mhdr->power;
  2204. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2205. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2206. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2207. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2208. meta_data->dyn_bw = 1;
  2209. meta_data->valid_pwr = 1;
  2210. meta_data->valid_mcs_mask = 1;
  2211. meta_data->valid_nss_mask = 1;
  2212. meta_data->valid_preamble_type = 1;
  2213. meta_data->valid_retries = 1;
  2214. meta_data->valid_bw_info = 1;
  2215. }
  2216. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2217. meta_data->encrypt_type = 0;
  2218. meta_data->valid_encrypt_type = 1;
  2219. meta_data->learning_frame = 0;
  2220. }
  2221. meta_data->valid_key_flags = 1;
  2222. meta_data->key_flags = (mhdr->keyix & 0x3);
  2223. remove_meta_hdr:
  2224. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2225. dp_tx_err("qdf_nbuf_pull_head failed");
  2226. qdf_nbuf_free(nbuf);
  2227. return NULL;
  2228. }
  2229. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2230. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2231. " tid %d to_fw %d",
  2232. msdu_info->meta_data[0],
  2233. msdu_info->meta_data[1],
  2234. msdu_info->meta_data[2],
  2235. msdu_info->meta_data[3],
  2236. msdu_info->meta_data[4],
  2237. msdu_info->meta_data[5],
  2238. msdu_info->tid, msdu_info->exception_fw);
  2239. return nbuf;
  2240. }
  2241. #else
  2242. static
  2243. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2244. struct dp_tx_msdu_info_s *msdu_info)
  2245. {
  2246. return nbuf;
  2247. }
  2248. #endif
  2249. /**
  2250. * dp_check_exc_metadata() - Checks if parameters are valid
  2251. * @tx_exc - holds all exception path parameters
  2252. *
  2253. * Returns true when all the parameters are valid else false
  2254. *
  2255. */
  2256. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2257. {
  2258. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2259. HTT_INVALID_TID);
  2260. bool invalid_encap_type =
  2261. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2262. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2263. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2264. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2265. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2266. tx_exc->ppdu_cookie == 0);
  2267. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2268. invalid_cookie) {
  2269. return false;
  2270. }
  2271. return true;
  2272. }
  2273. #ifdef ATH_SUPPORT_IQUE
  2274. /**
  2275. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2276. * @vdev: vdev handle
  2277. * @nbuf: skb
  2278. *
  2279. * Return: true on success,
  2280. * false on failure
  2281. */
  2282. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2283. {
  2284. qdf_ether_header_t *eh;
  2285. /* Mcast to Ucast Conversion*/
  2286. if (qdf_likely(!vdev->mcast_enhancement_en))
  2287. return true;
  2288. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2289. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2290. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2291. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2292. qdf_nbuf_set_next(nbuf, NULL);
  2293. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2294. qdf_nbuf_len(nbuf));
  2295. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2296. QDF_STATUS_SUCCESS) {
  2297. return false;
  2298. }
  2299. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2300. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2301. QDF_STATUS_SUCCESS) {
  2302. return false;
  2303. }
  2304. }
  2305. }
  2306. return true;
  2307. }
  2308. #else
  2309. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2310. {
  2311. return true;
  2312. }
  2313. #endif
  2314. /**
  2315. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2316. * @nbuf: qdf_nbuf_t
  2317. * @vdev: struct dp_vdev *
  2318. *
  2319. * Allow packet for processing only if it is for peer client which is
  2320. * connected with same vap. Drop packet if client is connected to
  2321. * different vap.
  2322. *
  2323. * Return: QDF_STATUS
  2324. */
  2325. static inline QDF_STATUS
  2326. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2327. {
  2328. struct dp_ast_entry *dst_ast_entry = NULL;
  2329. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2330. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2331. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2332. return QDF_STATUS_SUCCESS;
  2333. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2334. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2335. eh->ether_dhost,
  2336. vdev->vdev_id);
  2337. /* If there is no ast entry, return failure */
  2338. if (qdf_unlikely(!dst_ast_entry)) {
  2339. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2340. return QDF_STATUS_E_FAILURE;
  2341. }
  2342. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2343. return QDF_STATUS_SUCCESS;
  2344. }
  2345. /**
  2346. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2347. * @soc: DP soc handle
  2348. * @vdev_id: id of DP vdev handle
  2349. * @nbuf: skb
  2350. * @tx_exc_metadata: Handle that holds exception path meta data
  2351. *
  2352. * Entry point for Core Tx layer (DP_TX) invoked from
  2353. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2354. *
  2355. * Return: NULL on success,
  2356. * nbuf when it fails to send
  2357. */
  2358. qdf_nbuf_t
  2359. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2360. qdf_nbuf_t nbuf,
  2361. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2362. {
  2363. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2364. qdf_ether_header_t *eh = NULL;
  2365. struct dp_tx_msdu_info_s msdu_info;
  2366. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2367. DP_MOD_ID_TX_EXCEPTION);
  2368. if (qdf_unlikely(!vdev))
  2369. goto fail;
  2370. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2371. if (!tx_exc_metadata)
  2372. goto fail;
  2373. msdu_info.tid = tx_exc_metadata->tid;
  2374. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2375. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2376. QDF_MAC_ADDR_REF(nbuf->data));
  2377. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2378. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2379. dp_tx_err("Invalid parameters in exception path");
  2380. goto fail;
  2381. }
  2382. /* Basic sanity checks for unsupported packets */
  2383. /* MESH mode */
  2384. if (qdf_unlikely(vdev->mesh_vdev)) {
  2385. dp_tx_err("Mesh mode is not supported in exception path");
  2386. goto fail;
  2387. }
  2388. /*
  2389. * Classify the frame and call corresponding
  2390. * "prepare" function which extracts the segment (TSO)
  2391. * and fragmentation information (for TSO , SG, ME, or Raw)
  2392. * into MSDU_INFO structure which is later used to fill
  2393. * SW and HW descriptors.
  2394. */
  2395. if (qdf_nbuf_is_tso(nbuf)) {
  2396. dp_verbose_debug("TSO frame %pK", vdev);
  2397. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2398. qdf_nbuf_len(nbuf));
  2399. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2400. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2401. qdf_nbuf_len(nbuf));
  2402. goto fail;
  2403. }
  2404. goto send_multiple;
  2405. }
  2406. /* SG */
  2407. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2408. struct dp_tx_seg_info_s seg_info = {0};
  2409. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2410. if (!nbuf)
  2411. goto fail;
  2412. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2413. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2414. qdf_nbuf_len(nbuf));
  2415. goto send_multiple;
  2416. }
  2417. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2418. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2419. qdf_nbuf_len(nbuf));
  2420. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2421. tx_exc_metadata->ppdu_cookie);
  2422. }
  2423. /*
  2424. * Get HW Queue to use for this frame.
  2425. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2426. * dedicated for data and 1 for command.
  2427. * "queue_id" maps to one hardware ring.
  2428. * With each ring, we also associate a unique Tx descriptor pool
  2429. * to minimize lock contention for these resources.
  2430. */
  2431. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2432. /*
  2433. * Check exception descriptors
  2434. */
  2435. if (dp_tx_exception_limit_check(vdev))
  2436. goto fail;
  2437. /* Single linear frame */
  2438. /*
  2439. * If nbuf is a simple linear frame, use send_single function to
  2440. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2441. * SRNG. There is no need to setup a MSDU extension descriptor.
  2442. */
  2443. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2444. tx_exc_metadata->peer_id, tx_exc_metadata);
  2445. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2446. return nbuf;
  2447. send_multiple:
  2448. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2449. fail:
  2450. if (vdev)
  2451. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2452. dp_verbose_debug("pkt send failed");
  2453. return nbuf;
  2454. }
  2455. /**
  2456. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2457. * in exception path in special case to avoid regular exception path chk.
  2458. * @soc: DP soc handle
  2459. * @vdev_id: id of DP vdev handle
  2460. * @nbuf: skb
  2461. * @tx_exc_metadata: Handle that holds exception path meta data
  2462. *
  2463. * Entry point for Core Tx layer (DP_TX) invoked from
  2464. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2465. *
  2466. * Return: NULL on success,
  2467. * nbuf when it fails to send
  2468. */
  2469. qdf_nbuf_t
  2470. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2471. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2472. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2473. {
  2474. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2475. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2476. DP_MOD_ID_TX_EXCEPTION);
  2477. if (qdf_unlikely(!vdev))
  2478. goto fail;
  2479. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2480. == QDF_STATUS_E_FAILURE)) {
  2481. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2482. goto fail;
  2483. }
  2484. /* Unref count as it will agin be taken inside dp_tx_exception */
  2485. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2486. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2487. fail:
  2488. if (vdev)
  2489. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2490. dp_verbose_debug("pkt send failed");
  2491. return nbuf;
  2492. }
  2493. /**
  2494. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2495. * @soc: DP soc handle
  2496. * @vdev_id: DP vdev handle
  2497. * @nbuf: skb
  2498. *
  2499. * Entry point for Core Tx layer (DP_TX) invoked from
  2500. * hard_start_xmit in OSIF/HDD
  2501. *
  2502. * Return: NULL on success,
  2503. * nbuf when it fails to send
  2504. */
  2505. #ifdef MESH_MODE_SUPPORT
  2506. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2507. qdf_nbuf_t nbuf)
  2508. {
  2509. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2510. struct meta_hdr_s *mhdr;
  2511. qdf_nbuf_t nbuf_mesh = NULL;
  2512. qdf_nbuf_t nbuf_clone = NULL;
  2513. struct dp_vdev *vdev;
  2514. uint8_t no_enc_frame = 0;
  2515. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2516. if (!nbuf_mesh) {
  2517. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2518. "qdf_nbuf_unshare failed");
  2519. return nbuf;
  2520. }
  2521. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2522. if (!vdev) {
  2523. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2524. "vdev is NULL for vdev_id %d", vdev_id);
  2525. return nbuf;
  2526. }
  2527. nbuf = nbuf_mesh;
  2528. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2529. if ((vdev->sec_type != cdp_sec_type_none) &&
  2530. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2531. no_enc_frame = 1;
  2532. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2533. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2534. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2535. !no_enc_frame) {
  2536. nbuf_clone = qdf_nbuf_clone(nbuf);
  2537. if (!nbuf_clone) {
  2538. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2539. "qdf_nbuf_clone failed");
  2540. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2541. return nbuf;
  2542. }
  2543. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2544. }
  2545. if (nbuf_clone) {
  2546. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2547. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2548. } else {
  2549. qdf_nbuf_free(nbuf_clone);
  2550. }
  2551. }
  2552. if (no_enc_frame)
  2553. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2554. else
  2555. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2556. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2557. if ((!nbuf) && no_enc_frame) {
  2558. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2559. }
  2560. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2561. return nbuf;
  2562. }
  2563. #else
  2564. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2565. qdf_nbuf_t nbuf)
  2566. {
  2567. return dp_tx_send(soc, vdev_id, nbuf);
  2568. }
  2569. #endif
  2570. /**
  2571. * dp_tx_nawds_handler() - NAWDS handler
  2572. *
  2573. * @soc: DP soc handle
  2574. * @vdev_id: id of DP vdev handle
  2575. * @msdu_info: msdu_info required to create HTT metadata
  2576. * @nbuf: skb
  2577. *
  2578. * This API transfers the multicast frames with the peer id
  2579. * on NAWDS enabled peer.
  2580. * Return: none
  2581. */
  2582. static inline
  2583. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2584. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2585. {
  2586. struct dp_peer *peer = NULL;
  2587. qdf_nbuf_t nbuf_clone = NULL;
  2588. uint16_t peer_id = DP_INVALID_PEER;
  2589. uint16_t sa_peer_id = DP_INVALID_PEER;
  2590. struct dp_ast_entry *ast_entry = NULL;
  2591. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2592. qdf_spin_lock_bh(&soc->ast_lock);
  2593. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2594. (soc,
  2595. (uint8_t *)(eh->ether_shost),
  2596. vdev->pdev->pdev_id);
  2597. if (ast_entry)
  2598. sa_peer_id = ast_entry->peer_id;
  2599. qdf_spin_unlock_bh(&soc->ast_lock);
  2600. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2601. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2602. if (!peer->bss_peer && peer->nawds_enabled) {
  2603. peer_id = peer->peer_id;
  2604. /* Multicast packets needs to be
  2605. * dropped in case of intra bss forwarding
  2606. */
  2607. if (sa_peer_id == peer->peer_id) {
  2608. dp_tx_debug("multicast packet");
  2609. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  2610. continue;
  2611. }
  2612. nbuf_clone = qdf_nbuf_clone(nbuf);
  2613. if (!nbuf_clone) {
  2614. QDF_TRACE(QDF_MODULE_ID_DP,
  2615. QDF_TRACE_LEVEL_ERROR,
  2616. FL("nbuf clone failed"));
  2617. break;
  2618. }
  2619. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2620. msdu_info, peer_id,
  2621. NULL);
  2622. if (nbuf_clone) {
  2623. dp_tx_debug("pkt send failed");
  2624. qdf_nbuf_free(nbuf_clone);
  2625. } else {
  2626. if (peer_id != DP_INVALID_PEER)
  2627. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2628. 1, qdf_nbuf_len(nbuf));
  2629. }
  2630. }
  2631. }
  2632. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2633. }
  2634. /**
  2635. * dp_tx_send() - Transmit a frame on a given VAP
  2636. * @soc: DP soc handle
  2637. * @vdev_id: id of DP vdev handle
  2638. * @nbuf: skb
  2639. *
  2640. * Entry point for Core Tx layer (DP_TX) invoked from
  2641. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2642. * cases
  2643. *
  2644. * Return: NULL on success,
  2645. * nbuf when it fails to send
  2646. */
  2647. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2648. qdf_nbuf_t nbuf)
  2649. {
  2650. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2651. uint16_t peer_id = HTT_INVALID_PEER;
  2652. /*
  2653. * doing a memzero is causing additional function call overhead
  2654. * so doing static stack clearing
  2655. */
  2656. struct dp_tx_msdu_info_s msdu_info = {0};
  2657. struct dp_vdev *vdev = NULL;
  2658. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2659. return nbuf;
  2660. /*
  2661. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2662. * this in per packet path.
  2663. *
  2664. * As in this path vdev memory is already protected with netdev
  2665. * tx lock
  2666. */
  2667. vdev = soc->vdev_id_map[vdev_id];
  2668. if (qdf_unlikely(!vdev))
  2669. return nbuf;
  2670. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2671. QDF_MAC_ADDR_REF(nbuf->data));
  2672. /*
  2673. * Set Default Host TID value to invalid TID
  2674. * (TID override disabled)
  2675. */
  2676. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2677. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2678. if (qdf_unlikely(vdev->mesh_vdev)) {
  2679. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2680. &msdu_info);
  2681. if (!nbuf_mesh) {
  2682. dp_verbose_debug("Extracting mesh metadata failed");
  2683. return nbuf;
  2684. }
  2685. nbuf = nbuf_mesh;
  2686. }
  2687. /*
  2688. * Get HW Queue to use for this frame.
  2689. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2690. * dedicated for data and 1 for command.
  2691. * "queue_id" maps to one hardware ring.
  2692. * With each ring, we also associate a unique Tx descriptor pool
  2693. * to minimize lock contention for these resources.
  2694. */
  2695. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2696. /*
  2697. * TCL H/W supports 2 DSCP-TID mapping tables.
  2698. * Table 1 - Default DSCP-TID mapping table
  2699. * Table 2 - 1 DSCP-TID override table
  2700. *
  2701. * If we need a different DSCP-TID mapping for this vap,
  2702. * call tid_classify to extract DSCP/ToS from frame and
  2703. * map to a TID and store in msdu_info. This is later used
  2704. * to fill in TCL Input descriptor (per-packet TID override).
  2705. */
  2706. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2707. /*
  2708. * Classify the frame and call corresponding
  2709. * "prepare" function which extracts the segment (TSO)
  2710. * and fragmentation information (for TSO , SG, ME, or Raw)
  2711. * into MSDU_INFO structure which is later used to fill
  2712. * SW and HW descriptors.
  2713. */
  2714. if (qdf_nbuf_is_tso(nbuf)) {
  2715. dp_verbose_debug("TSO frame %pK", vdev);
  2716. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2717. qdf_nbuf_len(nbuf));
  2718. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2719. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2720. qdf_nbuf_len(nbuf));
  2721. return nbuf;
  2722. }
  2723. goto send_multiple;
  2724. }
  2725. /* SG */
  2726. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2727. struct dp_tx_seg_info_s seg_info = {0};
  2728. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2729. if (!nbuf)
  2730. return NULL;
  2731. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2732. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2733. qdf_nbuf_len(nbuf));
  2734. goto send_multiple;
  2735. }
  2736. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2737. return NULL;
  2738. /* RAW */
  2739. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2740. struct dp_tx_seg_info_s seg_info = {0};
  2741. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2742. if (!nbuf)
  2743. return NULL;
  2744. dp_verbose_debug("Raw frame %pK", vdev);
  2745. goto send_multiple;
  2746. }
  2747. if (qdf_unlikely(vdev->nawds_enabled)) {
  2748. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2749. qdf_nbuf_data(nbuf);
  2750. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2751. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2752. peer_id = DP_INVALID_PEER;
  2753. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2754. 1, qdf_nbuf_len(nbuf));
  2755. }
  2756. /* Single linear frame */
  2757. /*
  2758. * If nbuf is a simple linear frame, use send_single function to
  2759. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2760. * SRNG. There is no need to setup a MSDU extension descriptor.
  2761. */
  2762. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2763. return nbuf;
  2764. send_multiple:
  2765. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2766. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2767. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2768. return nbuf;
  2769. }
  2770. /**
  2771. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  2772. * case to vaoid check in perpkt path.
  2773. * @soc: DP soc handle
  2774. * @vdev_id: id of DP vdev handle
  2775. * @nbuf: skb
  2776. *
  2777. * Entry point for Core Tx layer (DP_TX) invoked from
  2778. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  2779. * with special condition to avoid per pkt check in dp_tx_send
  2780. *
  2781. * Return: NULL on success,
  2782. * nbuf when it fails to send
  2783. */
  2784. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2785. uint8_t vdev_id, qdf_nbuf_t nbuf)
  2786. {
  2787. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2788. struct dp_vdev *vdev = NULL;
  2789. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2790. return nbuf;
  2791. /*
  2792. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2793. * this in per packet path.
  2794. *
  2795. * As in this path vdev memory is already protected with netdev
  2796. * tx lock
  2797. */
  2798. vdev = soc->vdev_id_map[vdev_id];
  2799. if (qdf_unlikely(!vdev))
  2800. return nbuf;
  2801. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2802. == QDF_STATUS_E_FAILURE)) {
  2803. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2804. return nbuf;
  2805. }
  2806. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  2807. }
  2808. #ifdef UMAC_SUPPORT_PROXY_ARP
  2809. /**
  2810. * dp_tx_proxy_arp() - Tx proxy arp handler
  2811. * @vdev: datapath vdev handle
  2812. * @buf: sk buffer
  2813. *
  2814. * Return: status
  2815. */
  2816. static inline
  2817. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2818. {
  2819. if (vdev->osif_proxy_arp)
  2820. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  2821. /*
  2822. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  2823. * osif_proxy_arp has a valid function pointer assigned
  2824. * to it
  2825. */
  2826. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  2827. return QDF_STATUS_NOT_INITIALIZED;
  2828. }
  2829. #else
  2830. /**
  2831. * dp_tx_proxy_arp() - Tx proxy arp handler
  2832. * @vdev: datapath vdev handle
  2833. * @buf: sk buffer
  2834. *
  2835. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  2836. * is not defined.
  2837. *
  2838. * Return: status
  2839. */
  2840. static inline
  2841. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2842. {
  2843. return QDF_STATUS_SUCCESS;
  2844. }
  2845. #endif
  2846. /**
  2847. * dp_tx_reinject_handler() - Tx Reinject Handler
  2848. * @soc: datapath soc handle
  2849. * @vdev: datapath vdev handle
  2850. * @tx_desc: software descriptor head pointer
  2851. * @status : Tx completion status from HTT descriptor
  2852. *
  2853. * This function reinjects frames back to Target.
  2854. * Todo - Host queue needs to be added
  2855. *
  2856. * Return: none
  2857. */
  2858. static
  2859. void dp_tx_reinject_handler(struct dp_soc *soc,
  2860. struct dp_vdev *vdev,
  2861. struct dp_tx_desc_s *tx_desc,
  2862. uint8_t *status)
  2863. {
  2864. struct dp_peer *peer = NULL;
  2865. uint32_t peer_id = HTT_INVALID_PEER;
  2866. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2867. qdf_nbuf_t nbuf_copy = NULL;
  2868. struct dp_tx_msdu_info_s msdu_info;
  2869. #ifdef WDS_VENDOR_EXTENSION
  2870. int is_mcast = 0, is_ucast = 0;
  2871. int num_peers_3addr = 0;
  2872. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2873. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2874. #endif
  2875. qdf_assert(vdev);
  2876. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2877. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2878. dp_tx_debug("Tx reinject path");
  2879. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2880. qdf_nbuf_len(tx_desc->nbuf));
  2881. #ifdef WDS_VENDOR_EXTENSION
  2882. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2883. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2884. } else {
  2885. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2886. }
  2887. is_ucast = !is_mcast;
  2888. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2889. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2890. if (peer->bss_peer)
  2891. continue;
  2892. /* Detect wds peers that use 3-addr framing for mcast.
  2893. * if there are any, the bss_peer is used to send the
  2894. * the mcast frame using 3-addr format. all wds enabled
  2895. * peers that use 4-addr framing for mcast frames will
  2896. * be duplicated and sent as 4-addr frames below.
  2897. */
  2898. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2899. num_peers_3addr = 1;
  2900. break;
  2901. }
  2902. }
  2903. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2904. #endif
  2905. if (qdf_unlikely(vdev->mesh_vdev)) {
  2906. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2907. } else {
  2908. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2909. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2910. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2911. #ifdef WDS_VENDOR_EXTENSION
  2912. /*
  2913. * . if 3-addr STA, then send on BSS Peer
  2914. * . if Peer WDS enabled and accept 4-addr mcast,
  2915. * send mcast on that peer only
  2916. * . if Peer WDS enabled and accept 4-addr ucast,
  2917. * send ucast on that peer only
  2918. */
  2919. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2920. (peer->wds_enabled &&
  2921. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2922. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2923. #else
  2924. (peer->bss_peer &&
  2925. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  2926. #endif
  2927. peer_id = DP_INVALID_PEER;
  2928. nbuf_copy = qdf_nbuf_copy(nbuf);
  2929. if (!nbuf_copy) {
  2930. dp_tx_debug("nbuf copy failed");
  2931. break;
  2932. }
  2933. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2934. nbuf_copy,
  2935. &msdu_info,
  2936. peer_id,
  2937. NULL);
  2938. if (nbuf_copy) {
  2939. dp_tx_debug("pkt send failed");
  2940. qdf_nbuf_free(nbuf_copy);
  2941. }
  2942. }
  2943. }
  2944. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2945. }
  2946. qdf_nbuf_free(nbuf);
  2947. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2948. }
  2949. /**
  2950. * dp_tx_inspect_handler() - Tx Inspect Handler
  2951. * @soc: datapath soc handle
  2952. * @vdev: datapath vdev handle
  2953. * @tx_desc: software descriptor head pointer
  2954. * @status : Tx completion status from HTT descriptor
  2955. *
  2956. * Handles Tx frames sent back to Host for inspection
  2957. * (ProxyARP)
  2958. *
  2959. * Return: none
  2960. */
  2961. static void dp_tx_inspect_handler(struct dp_soc *soc,
  2962. struct dp_vdev *vdev,
  2963. struct dp_tx_desc_s *tx_desc,
  2964. uint8_t *status)
  2965. {
  2966. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2967. "%s Tx inspect path",
  2968. __func__);
  2969. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  2970. qdf_nbuf_len(tx_desc->nbuf));
  2971. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2972. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2973. }
  2974. #ifdef MESH_MODE_SUPPORT
  2975. /**
  2976. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2977. * in mesh meta header
  2978. * @tx_desc: software descriptor head pointer
  2979. * @ts: pointer to tx completion stats
  2980. * Return: none
  2981. */
  2982. static
  2983. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2984. struct hal_tx_completion_status *ts)
  2985. {
  2986. struct meta_hdr_s *mhdr;
  2987. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2988. if (!tx_desc->msdu_ext_desc) {
  2989. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2990. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2991. "netbuf %pK offset %d",
  2992. netbuf, tx_desc->pkt_offset);
  2993. return;
  2994. }
  2995. }
  2996. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2997. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2998. "netbuf %pK offset %zu", netbuf,
  2999. sizeof(struct meta_hdr_s));
  3000. return;
  3001. }
  3002. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  3003. mhdr->rssi = ts->ack_frame_rssi;
  3004. mhdr->band = tx_desc->pdev->operating_channel.band;
  3005. mhdr->channel = tx_desc->pdev->operating_channel.num;
  3006. }
  3007. #else
  3008. static
  3009. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3010. struct hal_tx_completion_status *ts)
  3011. {
  3012. }
  3013. #endif
  3014. #ifdef QCA_PEER_EXT_STATS
  3015. /*
  3016. * dp_tx_compute_tid_delay() - Compute per TID delay
  3017. * @stats: Per TID delay stats
  3018. * @tx_desc: Software Tx descriptor
  3019. *
  3020. * Compute the software enqueue and hw enqueue delays and
  3021. * update the respective histograms
  3022. *
  3023. * Return: void
  3024. */
  3025. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3026. struct dp_tx_desc_s *tx_desc)
  3027. {
  3028. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3029. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3030. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3031. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3032. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3033. timestamp_hw_enqueue = tx_desc->timestamp;
  3034. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3035. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3036. timestamp_hw_enqueue);
  3037. /*
  3038. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3039. */
  3040. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3041. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3042. }
  3043. /*
  3044. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  3045. * @peer: DP peer context
  3046. * @tx_desc: Tx software descriptor
  3047. * @tid: Transmission ID
  3048. * @ring_id: Rx CPU context ID/CPU_ID
  3049. *
  3050. * Update the peer extended stats. These are enhanced other
  3051. * delay stats per msdu level.
  3052. *
  3053. * Return: void
  3054. */
  3055. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3056. struct dp_tx_desc_s *tx_desc,
  3057. uint8_t tid, uint8_t ring_id)
  3058. {
  3059. struct dp_pdev *pdev = peer->vdev->pdev;
  3060. struct dp_soc *soc = NULL;
  3061. struct cdp_peer_ext_stats *pext_stats = NULL;
  3062. soc = pdev->soc;
  3063. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3064. return;
  3065. pext_stats = peer->pext_stats;
  3066. qdf_assert(pext_stats);
  3067. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3068. /*
  3069. * For non-TID packets use the TID 9
  3070. */
  3071. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3072. tid = CDP_MAX_DATA_TIDS - 1;
  3073. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  3074. tx_desc);
  3075. }
  3076. #else
  3077. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3078. struct dp_tx_desc_s *tx_desc,
  3079. uint8_t tid, uint8_t ring_id)
  3080. {
  3081. }
  3082. #endif
  3083. /**
  3084. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3085. * to pass in correct fields
  3086. *
  3087. * @vdev: pdev handle
  3088. * @tx_desc: tx descriptor
  3089. * @tid: tid value
  3090. * @ring_id: TCL or WBM ring number for transmit path
  3091. * Return: none
  3092. */
  3093. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  3094. struct dp_tx_desc_s *tx_desc,
  3095. uint8_t tid, uint8_t ring_id)
  3096. {
  3097. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3098. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3099. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  3100. return;
  3101. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3102. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3103. timestamp_hw_enqueue = tx_desc->timestamp;
  3104. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3105. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3106. timestamp_hw_enqueue);
  3107. interframe_delay = (uint32_t)(timestamp_ingress -
  3108. vdev->prev_tx_enq_tstamp);
  3109. /*
  3110. * Delay in software enqueue
  3111. */
  3112. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  3113. CDP_DELAY_STATS_SW_ENQ, ring_id);
  3114. /*
  3115. * Delay between packet enqueued to HW and Tx completion
  3116. */
  3117. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  3118. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  3119. /*
  3120. * Update interframe delay stats calculated at hardstart receive point.
  3121. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3122. * interframe delay will not be calculate correctly for 1st frame.
  3123. * On the other side, this will help in avoiding extra per packet check
  3124. * of !vdev->prev_tx_enq_tstamp.
  3125. */
  3126. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  3127. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  3128. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3129. }
  3130. #ifdef DISABLE_DP_STATS
  3131. static
  3132. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3133. {
  3134. }
  3135. #else
  3136. static
  3137. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3138. {
  3139. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3140. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3141. if (subtype != QDF_PROTO_INVALID)
  3142. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  3143. }
  3144. #endif
  3145. /**
  3146. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3147. * per wbm ring
  3148. *
  3149. * @tx_desc: software descriptor head pointer
  3150. * @ts: Tx completion status
  3151. * @peer: peer handle
  3152. * @ring_id: ring number
  3153. *
  3154. * Return: None
  3155. */
  3156. static inline void
  3157. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3158. struct hal_tx_completion_status *ts,
  3159. struct dp_peer *peer, uint8_t ring_id)
  3160. {
  3161. struct dp_pdev *pdev = peer->vdev->pdev;
  3162. struct dp_soc *soc = NULL;
  3163. uint8_t mcs, pkt_type;
  3164. uint8_t tid = ts->tid;
  3165. uint32_t length;
  3166. struct cdp_tid_tx_stats *tid_stats;
  3167. if (!pdev)
  3168. return;
  3169. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3170. tid = CDP_MAX_DATA_TIDS - 1;
  3171. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3172. soc = pdev->soc;
  3173. mcs = ts->mcs;
  3174. pkt_type = ts->pkt_type;
  3175. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3176. dp_err("Release source is not from TQM");
  3177. return;
  3178. }
  3179. length = qdf_nbuf_len(tx_desc->nbuf);
  3180. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3181. if (qdf_unlikely(pdev->delay_stats_flag))
  3182. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  3183. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  3184. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  3185. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  3186. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3187. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  3188. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  3189. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  3190. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  3191. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  3192. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  3193. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  3194. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  3195. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  3196. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  3197. /*
  3198. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  3199. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  3200. * are no completions for failed cases. Hence updating tx_failed from
  3201. * data path. Please note that if tx_failed is fixed to be from ppdu,
  3202. * then this has to be removed
  3203. */
  3204. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  3205. peer->stats.tx.dropped.fw_rem_notx +
  3206. peer->stats.tx.dropped.fw_rem_tx +
  3207. peer->stats.tx.dropped.age_out +
  3208. peer->stats.tx.dropped.fw_reason1 +
  3209. peer->stats.tx.dropped.fw_reason2 +
  3210. peer->stats.tx.dropped.fw_reason3;
  3211. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3212. tid_stats->tqm_status_cnt[ts->status]++;
  3213. }
  3214. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3215. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  3216. return;
  3217. }
  3218. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  3219. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  3220. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  3221. /*
  3222. * Following Rate Statistics are updated from HTT PPDU events from FW.
  3223. * Return from here if HTT PPDU events are enabled.
  3224. */
  3225. if (!(soc->process_tx_status))
  3226. return;
  3227. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3228. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3229. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3230. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3231. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3232. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3233. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3234. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3235. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3236. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3237. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3238. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3239. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3240. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3241. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3242. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3243. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3244. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3245. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3246. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3247. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  3248. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  3249. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3250. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3251. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  3252. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  3253. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  3254. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  3255. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  3256. &peer->stats, ts->peer_id,
  3257. UPDATE_PEER_STATS, pdev->pdev_id);
  3258. #endif
  3259. }
  3260. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3261. /**
  3262. * dp_tx_flow_pool_lock() - take flow pool lock
  3263. * @soc: core txrx main context
  3264. * @tx_desc: tx desc
  3265. *
  3266. * Return: None
  3267. */
  3268. static inline
  3269. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3270. struct dp_tx_desc_s *tx_desc)
  3271. {
  3272. struct dp_tx_desc_pool_s *pool;
  3273. uint8_t desc_pool_id;
  3274. desc_pool_id = tx_desc->pool_id;
  3275. pool = &soc->tx_desc[desc_pool_id];
  3276. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3277. }
  3278. /**
  3279. * dp_tx_flow_pool_unlock() - release flow pool lock
  3280. * @soc: core txrx main context
  3281. * @tx_desc: tx desc
  3282. *
  3283. * Return: None
  3284. */
  3285. static inline
  3286. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3287. struct dp_tx_desc_s *tx_desc)
  3288. {
  3289. struct dp_tx_desc_pool_s *pool;
  3290. uint8_t desc_pool_id;
  3291. desc_pool_id = tx_desc->pool_id;
  3292. pool = &soc->tx_desc[desc_pool_id];
  3293. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3294. }
  3295. #else
  3296. static inline
  3297. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3298. {
  3299. }
  3300. static inline
  3301. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3302. {
  3303. }
  3304. #endif
  3305. /**
  3306. * dp_tx_notify_completion() - Notify tx completion for this desc
  3307. * @soc: core txrx main context
  3308. * @vdev: datapath vdev handle
  3309. * @tx_desc: tx desc
  3310. * @netbuf: buffer
  3311. * @status: tx status
  3312. *
  3313. * Return: none
  3314. */
  3315. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3316. struct dp_vdev *vdev,
  3317. struct dp_tx_desc_s *tx_desc,
  3318. qdf_nbuf_t netbuf,
  3319. uint8_t status)
  3320. {
  3321. void *osif_dev;
  3322. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3323. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3324. qdf_assert(tx_desc);
  3325. dp_tx_flow_pool_lock(soc, tx_desc);
  3326. if (!vdev ||
  3327. !vdev->osif_vdev) {
  3328. dp_tx_flow_pool_unlock(soc, tx_desc);
  3329. return;
  3330. }
  3331. osif_dev = vdev->osif_vdev;
  3332. tx_compl_cbk = vdev->tx_comp;
  3333. dp_tx_flow_pool_unlock(soc, tx_desc);
  3334. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3335. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3336. if (tx_compl_cbk)
  3337. tx_compl_cbk(netbuf, osif_dev, flag);
  3338. }
  3339. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3340. * @pdev: pdev handle
  3341. * @tid: tid value
  3342. * @txdesc_ts: timestamp from txdesc
  3343. * @ppdu_id: ppdu id
  3344. *
  3345. * Return: none
  3346. */
  3347. #ifdef FEATURE_PERPKT_INFO
  3348. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3349. struct dp_peer *peer,
  3350. uint8_t tid,
  3351. uint64_t txdesc_ts,
  3352. uint32_t ppdu_id)
  3353. {
  3354. uint64_t delta_ms;
  3355. struct cdp_tx_sojourn_stats *sojourn_stats;
  3356. if (qdf_unlikely(!dp_monitor_is_enable_enhanced_stats(pdev)))
  3357. return;
  3358. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3359. tid >= CDP_DATA_TID_MAX))
  3360. return;
  3361. if (qdf_unlikely(!pdev->sojourn_buf))
  3362. return;
  3363. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3364. qdf_nbuf_data(pdev->sojourn_buf);
  3365. sojourn_stats->cookie = (void *)peer->rdkstats_ctx;
  3366. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  3367. txdesc_ts;
  3368. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  3369. delta_ms);
  3370. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3371. sojourn_stats->num_msdus[tid] = 1;
  3372. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3373. peer->avg_sojourn_msdu[tid].internal;
  3374. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3375. pdev->sojourn_buf, HTT_INVALID_PEER,
  3376. WDI_NO_VAL, pdev->pdev_id);
  3377. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3378. sojourn_stats->num_msdus[tid] = 0;
  3379. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3380. }
  3381. #else
  3382. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3383. struct dp_peer *peer,
  3384. uint8_t tid,
  3385. uint64_t txdesc_ts,
  3386. uint32_t ppdu_id)
  3387. {
  3388. }
  3389. #endif
  3390. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  3391. /**
  3392. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  3393. * @soc: dp_soc handle
  3394. * @desc: Tx Descriptor
  3395. * @ts: HAL Tx completion descriptor contents
  3396. *
  3397. * This function is used to send tx completion to packet capture
  3398. */
  3399. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  3400. struct dp_tx_desc_s *desc,
  3401. struct hal_tx_completion_status *ts)
  3402. {
  3403. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  3404. desc, ts->peer_id,
  3405. WDI_NO_VAL, desc->pdev->pdev_id);
  3406. }
  3407. #endif
  3408. /**
  3409. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3410. * @soc: DP Soc handle
  3411. * @tx_desc: software Tx descriptor
  3412. * @ts : Tx completion status from HAL/HTT descriptor
  3413. *
  3414. * Return: none
  3415. */
  3416. static inline void
  3417. dp_tx_comp_process_desc(struct dp_soc *soc,
  3418. struct dp_tx_desc_s *desc,
  3419. struct hal_tx_completion_status *ts,
  3420. struct dp_peer *peer)
  3421. {
  3422. uint64_t time_latency = 0;
  3423. /*
  3424. * m_copy/tx_capture modes are not supported for
  3425. * scatter gather packets
  3426. */
  3427. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3428. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3429. desc->timestamp);
  3430. }
  3431. dp_send_completion_to_pkt_capture(soc, desc, ts);
  3432. if (!(desc->msdu_ext_desc)) {
  3433. dp_tx_enh_unmap(soc, desc);
  3434. if (QDF_STATUS_SUCCESS ==
  3435. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3436. return;
  3437. }
  3438. if (QDF_STATUS_SUCCESS ==
  3439. dp_get_completion_indication_for_stack(soc,
  3440. desc->pdev,
  3441. peer, ts,
  3442. desc->nbuf,
  3443. time_latency)) {
  3444. dp_send_completion_to_stack(soc,
  3445. desc->pdev,
  3446. ts->peer_id,
  3447. ts->ppdu_id,
  3448. desc->nbuf);
  3449. return;
  3450. }
  3451. }
  3452. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  3453. dp_tx_comp_free_buf(soc, desc);
  3454. }
  3455. #ifdef DISABLE_DP_STATS
  3456. /**
  3457. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3458. * @soc: core txrx main context
  3459. * @tx_desc: tx desc
  3460. * @status: tx status
  3461. *
  3462. * Return: none
  3463. */
  3464. static inline
  3465. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3466. struct dp_vdev *vdev,
  3467. struct dp_tx_desc_s *tx_desc,
  3468. uint8_t status)
  3469. {
  3470. }
  3471. #else
  3472. static inline
  3473. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3474. struct dp_vdev *vdev,
  3475. struct dp_tx_desc_s *tx_desc,
  3476. uint8_t status)
  3477. {
  3478. void *osif_dev;
  3479. ol_txrx_stats_rx_fp stats_cbk;
  3480. uint8_t pkt_type;
  3481. qdf_assert(tx_desc);
  3482. if (!vdev ||
  3483. !vdev->osif_vdev ||
  3484. !vdev->stats_cb)
  3485. return;
  3486. osif_dev = vdev->osif_vdev;
  3487. stats_cbk = vdev->stats_cb;
  3488. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3489. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3490. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3491. &pkt_type);
  3492. }
  3493. #endif
  3494. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  3495. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3496. uint32_t delta_tsf)
  3497. {
  3498. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3499. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3500. DP_MOD_ID_CDP);
  3501. if (!vdev) {
  3502. dp_err_rl("vdev %d does not exist", vdev_id);
  3503. return;
  3504. }
  3505. vdev->delta_tsf = delta_tsf;
  3506. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  3507. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3508. }
  3509. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  3510. uint8_t vdev_id, bool enable)
  3511. {
  3512. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3513. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3514. DP_MOD_ID_CDP);
  3515. if (!vdev) {
  3516. dp_err_rl("vdev %d does not exist", vdev_id);
  3517. return QDF_STATUS_E_FAILURE;
  3518. }
  3519. qdf_atomic_set(&vdev->ul_delay_report, enable);
  3520. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3521. return QDF_STATUS_SUCCESS;
  3522. }
  3523. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3524. uint32_t *val)
  3525. {
  3526. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3527. struct dp_vdev *vdev;
  3528. uint32_t delay_accum;
  3529. uint32_t pkts_accum;
  3530. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  3531. if (!vdev) {
  3532. dp_err_rl("vdev %d does not exist", vdev_id);
  3533. return QDF_STATUS_E_FAILURE;
  3534. }
  3535. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  3536. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3537. return QDF_STATUS_E_FAILURE;
  3538. }
  3539. /* Average uplink delay based on current accumulated values */
  3540. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  3541. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  3542. *val = delay_accum / pkts_accum;
  3543. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  3544. delay_accum, pkts_accum);
  3545. /* Reset accumulated values to 0 */
  3546. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  3547. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  3548. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3549. return QDF_STATUS_SUCCESS;
  3550. }
  3551. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  3552. struct hal_tx_completion_status *ts)
  3553. {
  3554. uint32_t buffer_ts;
  3555. uint32_t delta_tsf;
  3556. uint32_t ul_delay;
  3557. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  3558. if (!ts->valid)
  3559. return;
  3560. if (qdf_unlikely(!vdev)) {
  3561. dp_info_rl("vdev is null or delete in progrss");
  3562. return;
  3563. }
  3564. if (!qdf_atomic_read(&vdev->ul_delay_report))
  3565. return;
  3566. delta_tsf = vdev->delta_tsf;
  3567. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  3568. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  3569. * valid up to 29 bits.
  3570. */
  3571. buffer_ts = ts->buffer_timestamp << 10;
  3572. ul_delay = ts->tsf - buffer_ts - delta_tsf;
  3573. ul_delay &= 0x1FFFFFFF; /* mask 29 BITS */
  3574. if (ul_delay > 0x1000000) {
  3575. dp_info_rl("----------------------\n"
  3576. "Tx completion status:\n"
  3577. "----------------------\n"
  3578. "release_src = %d\n"
  3579. "ppdu_id = 0x%x\n"
  3580. "release_reason = %d\n"
  3581. "tsf = %u (0x%x)\n"
  3582. "buffer_timestamp = %u (0x%x)\n"
  3583. "delta_tsf = %u (0x%x)\n",
  3584. ts->release_src, ts->ppdu_id, ts->status,
  3585. ts->tsf, ts->tsf, ts->buffer_timestamp,
  3586. ts->buffer_timestamp, delta_tsf, delta_tsf);
  3587. return;
  3588. }
  3589. ul_delay /= 1000; /* in unit of ms */
  3590. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  3591. qdf_atomic_inc(&vdev->ul_pkts_accum);
  3592. }
  3593. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  3594. static inline
  3595. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  3596. struct hal_tx_completion_status *ts)
  3597. {
  3598. }
  3599. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  3600. /**
  3601. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3602. * @soc: DP soc handle
  3603. * @tx_desc: software descriptor head pointer
  3604. * @ts: Tx completion status
  3605. * @peer: peer handle
  3606. * @ring_id: ring number
  3607. *
  3608. * Return: none
  3609. */
  3610. static inline
  3611. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3612. struct dp_tx_desc_s *tx_desc,
  3613. struct hal_tx_completion_status *ts,
  3614. struct dp_peer *peer, uint8_t ring_id)
  3615. {
  3616. uint32_t length;
  3617. qdf_ether_header_t *eh;
  3618. struct dp_vdev *vdev = NULL;
  3619. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3620. enum qdf_dp_tx_rx_status dp_status;
  3621. if (!nbuf) {
  3622. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3623. goto out;
  3624. }
  3625. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3626. length = qdf_nbuf_len(nbuf);
  3627. dp_status = dp_tx_hw_to_qdf(ts->status);
  3628. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3629. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3630. QDF_TRACE_DEFAULT_PDEV_ID,
  3631. qdf_nbuf_data_addr(nbuf),
  3632. sizeof(qdf_nbuf_data(nbuf)),
  3633. tx_desc->id, ts->status, dp_status));
  3634. dp_tx_comp_debug("-------------------- \n"
  3635. "Tx Completion Stats: \n"
  3636. "-------------------- \n"
  3637. "ack_frame_rssi = %d \n"
  3638. "first_msdu = %d \n"
  3639. "last_msdu = %d \n"
  3640. "msdu_part_of_amsdu = %d \n"
  3641. "rate_stats valid = %d \n"
  3642. "bw = %d \n"
  3643. "pkt_type = %d \n"
  3644. "stbc = %d \n"
  3645. "ldpc = %d \n"
  3646. "sgi = %d \n"
  3647. "mcs = %d \n"
  3648. "ofdma = %d \n"
  3649. "tones_in_ru = %d \n"
  3650. "tsf = %d \n"
  3651. "ppdu_id = %d \n"
  3652. "transmit_cnt = %d \n"
  3653. "tid = %d \n"
  3654. "peer_id = %d\n",
  3655. ts->ack_frame_rssi, ts->first_msdu,
  3656. ts->last_msdu, ts->msdu_part_of_amsdu,
  3657. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3658. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3659. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3660. ts->transmit_cnt, ts->tid, ts->peer_id);
  3661. /* Update SoC level stats */
  3662. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3663. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3664. if (!peer) {
  3665. dp_info_rl("peer is null or deletion in progress");
  3666. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3667. goto out;
  3668. }
  3669. vdev = peer->vdev;
  3670. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3671. dp_tx_update_uplink_delay(soc, vdev, ts);
  3672. /* Update per-packet stats for mesh mode */
  3673. if (qdf_unlikely(vdev->mesh_vdev) &&
  3674. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3675. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3676. /* Update peer level stats */
  3677. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3678. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3679. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3680. if ((peer->vdev->tx_encap_type ==
  3681. htt_cmn_pkt_type_ethernet) &&
  3682. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3683. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3684. }
  3685. }
  3686. } else {
  3687. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3688. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3689. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3690. if (qdf_unlikely(peer->in_twt)) {
  3691. DP_STATS_INC_PKT(peer,
  3692. tx.tx_success_twt,
  3693. 1, length);
  3694. }
  3695. }
  3696. }
  3697. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3698. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3699. #ifdef QCA_SUPPORT_RDK_STATS
  3700. if (soc->rdkstats_enabled)
  3701. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3702. tx_desc->timestamp,
  3703. ts->ppdu_id);
  3704. #endif
  3705. out:
  3706. return;
  3707. }
  3708. /**
  3709. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3710. * @soc: core txrx main context
  3711. * @comp_head: software descriptor head pointer
  3712. * @ring_id: ring number
  3713. *
  3714. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3715. * and release the software descriptors after processing is complete
  3716. *
  3717. * Return: none
  3718. */
  3719. static void
  3720. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3721. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3722. {
  3723. struct dp_tx_desc_s *desc;
  3724. struct dp_tx_desc_s *next;
  3725. struct hal_tx_completion_status ts;
  3726. struct dp_peer *peer = NULL;
  3727. uint16_t peer_id = DP_INVALID_PEER;
  3728. qdf_nbuf_t netbuf;
  3729. desc = comp_head;
  3730. while (desc) {
  3731. if (peer_id != desc->peer_id) {
  3732. if (peer)
  3733. dp_peer_unref_delete(peer,
  3734. DP_MOD_ID_TX_COMP);
  3735. peer_id = desc->peer_id;
  3736. peer = dp_peer_get_ref_by_id(soc, peer_id,
  3737. DP_MOD_ID_TX_COMP);
  3738. }
  3739. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3740. struct dp_pdev *pdev = desc->pdev;
  3741. if (qdf_likely(peer)) {
  3742. /*
  3743. * Increment peer statistics
  3744. * Minimal statistics update done here
  3745. */
  3746. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3747. desc->length);
  3748. if (desc->tx_status !=
  3749. HAL_TX_TQM_RR_FRAME_ACKED)
  3750. DP_STATS_INC(peer, tx.tx_failed, 1);
  3751. }
  3752. qdf_assert(pdev);
  3753. dp_tx_outstanding_dec(pdev);
  3754. /*
  3755. * Calling a QDF WRAPPER here is creating signifcant
  3756. * performance impact so avoided the wrapper call here
  3757. */
  3758. next = desc->next;
  3759. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  3760. desc->id, DP_TX_COMP_UNMAP);
  3761. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  3762. desc->nbuf,
  3763. desc->dma_addr,
  3764. QDF_DMA_TO_DEVICE,
  3765. desc->length);
  3766. qdf_nbuf_free(desc->nbuf);
  3767. dp_tx_desc_free(soc, desc, desc->pool_id);
  3768. desc = next;
  3769. continue;
  3770. }
  3771. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3772. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3773. netbuf = desc->nbuf;
  3774. /* check tx complete notification */
  3775. if (peer && qdf_nbuf_tx_notify_comp_get(netbuf))
  3776. dp_tx_notify_completion(soc, peer->vdev, desc,
  3777. netbuf, ts.status);
  3778. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3779. next = desc->next;
  3780. dp_tx_desc_release(desc, desc->pool_id);
  3781. desc = next;
  3782. }
  3783. if (peer)
  3784. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3785. }
  3786. /**
  3787. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3788. * @soc: Handle to DP soc structure
  3789. * @tx_desc: software descriptor head pointer
  3790. * @status : Tx completion status from HTT descriptor
  3791. * @ring_id: ring number
  3792. *
  3793. * This function will process HTT Tx indication messages from Target
  3794. *
  3795. * Return: none
  3796. */
  3797. static
  3798. void dp_tx_process_htt_completion(struct dp_soc *soc,
  3799. struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3800. uint8_t ring_id)
  3801. {
  3802. uint8_t tx_status;
  3803. struct dp_pdev *pdev;
  3804. struct dp_vdev *vdev;
  3805. struct hal_tx_completion_status ts = {0};
  3806. uint32_t *htt_desc = (uint32_t *)status;
  3807. struct dp_peer *peer;
  3808. struct cdp_tid_tx_stats *tid_stats = NULL;
  3809. struct htt_soc *htt_handle;
  3810. uint8_t vdev_id;
  3811. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3812. htt_handle = (struct htt_soc *)soc->htt_handle;
  3813. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3814. /*
  3815. * There can be scenario where WBM consuming descriptor enqueued
  3816. * from TQM2WBM first and TQM completion can happen before MEC
  3817. * notification comes from FW2WBM. Avoid access any field of tx
  3818. * descriptor in case of MEC notify.
  3819. */
  3820. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY) {
  3821. /*
  3822. * Get vdev id from HTT status word in case of MEC
  3823. * notification
  3824. */
  3825. vdev_id = HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(htt_desc[3]);
  3826. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3827. return;
  3828. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3829. DP_MOD_ID_HTT_COMP);
  3830. if (!vdev)
  3831. return;
  3832. dp_tx_mec_handler(vdev, status);
  3833. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3834. return;
  3835. }
  3836. /*
  3837. * If the descriptor is already freed in vdev_detach,
  3838. * continue to next descriptor
  3839. */
  3840. if ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) && !tx_desc->flags) {
  3841. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d", tx_desc->id);
  3842. return;
  3843. }
  3844. pdev = tx_desc->pdev;
  3845. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3846. dp_tx_comp_info_rl("pdev in down state %d", tx_desc->id);
  3847. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  3848. dp_tx_comp_free_buf(soc, tx_desc);
  3849. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3850. return;
  3851. }
  3852. qdf_assert(tx_desc->pdev);
  3853. vdev_id = tx_desc->vdev_id;
  3854. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3855. DP_MOD_ID_HTT_COMP);
  3856. if (!vdev)
  3857. return;
  3858. switch (tx_status) {
  3859. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3860. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3861. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3862. {
  3863. uint8_t tid;
  3864. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3865. ts.peer_id =
  3866. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3867. htt_desc[2]);
  3868. ts.tid =
  3869. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3870. htt_desc[2]);
  3871. } else {
  3872. ts.peer_id = HTT_INVALID_PEER;
  3873. ts.tid = HTT_INVALID_TID;
  3874. }
  3875. ts.ppdu_id =
  3876. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3877. htt_desc[1]);
  3878. ts.ack_frame_rssi =
  3879. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3880. htt_desc[1]);
  3881. ts.tsf = htt_desc[3];
  3882. ts.first_msdu = 1;
  3883. ts.last_msdu = 1;
  3884. tid = ts.tid;
  3885. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3886. tid = CDP_MAX_DATA_TIDS - 1;
  3887. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3888. if (qdf_unlikely(pdev->delay_stats_flag))
  3889. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3890. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3891. tid_stats->htt_status_cnt[tx_status]++;
  3892. }
  3893. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3894. DP_MOD_ID_HTT_COMP);
  3895. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3896. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3897. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3898. if (qdf_likely(peer))
  3899. dp_peer_unref_delete(peer, DP_MOD_ID_HTT_COMP);
  3900. break;
  3901. }
  3902. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3903. {
  3904. dp_tx_reinject_handler(soc, vdev, tx_desc, status);
  3905. break;
  3906. }
  3907. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3908. {
  3909. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  3910. break;
  3911. }
  3912. default:
  3913. dp_tx_comp_debug("Invalid HTT tx_status %d\n",
  3914. tx_status);
  3915. break;
  3916. }
  3917. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3918. }
  3919. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3920. static inline
  3921. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  3922. int max_reap_limit)
  3923. {
  3924. bool limit_hit = false;
  3925. limit_hit =
  3926. (num_reaped >= max_reap_limit) ? true : false;
  3927. if (limit_hit)
  3928. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3929. return limit_hit;
  3930. }
  3931. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3932. {
  3933. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3934. }
  3935. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  3936. {
  3937. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3938. return cfg->tx_comp_loop_pkt_limit;
  3939. }
  3940. #else
  3941. static inline
  3942. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  3943. int max_reap_limit)
  3944. {
  3945. return false;
  3946. }
  3947. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3948. {
  3949. return false;
  3950. }
  3951. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  3952. {
  3953. return 0;
  3954. }
  3955. #endif
  3956. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  3957. static inline int
  3958. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  3959. int *max_reap_limit)
  3960. {
  3961. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  3962. max_reap_limit);
  3963. }
  3964. #else
  3965. static inline int
  3966. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  3967. int *max_reap_limit)
  3968. {
  3969. return 0;
  3970. }
  3971. #endif
  3972. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3973. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3974. uint32_t quota)
  3975. {
  3976. void *tx_comp_hal_desc;
  3977. uint8_t buffer_src;
  3978. struct dp_tx_desc_s *tx_desc = NULL;
  3979. struct dp_tx_desc_s *head_desc = NULL;
  3980. struct dp_tx_desc_s *tail_desc = NULL;
  3981. uint32_t num_processed = 0;
  3982. uint32_t count;
  3983. uint32_t num_avail_for_reap = 0;
  3984. bool force_break = false;
  3985. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  3986. int max_reap_limit, ring_near_full;
  3987. DP_HIST_INIT();
  3988. more_data:
  3989. /* Re-initialize local variables to be re-used */
  3990. head_desc = NULL;
  3991. tail_desc = NULL;
  3992. count = 0;
  3993. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  3994. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  3995. &max_reap_limit);
  3996. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3997. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3998. return 0;
  3999. }
  4000. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  4001. if (num_avail_for_reap >= quota)
  4002. num_avail_for_reap = quota;
  4003. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  4004. /* Find head descriptor from completion ring */
  4005. while (qdf_likely(num_avail_for_reap--)) {
  4006. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  4007. if (qdf_unlikely(!tx_comp_hal_desc))
  4008. break;
  4009. buffer_src = hal_tx_comp_get_buffer_source(soc->hal_soc,
  4010. tx_comp_hal_desc);
  4011. /* If this buffer was not released by TQM or FW, then it is not
  4012. * Tx completion indication, assert */
  4013. if (qdf_unlikely(buffer_src !=
  4014. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  4015. (qdf_unlikely(buffer_src !=
  4016. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  4017. uint8_t wbm_internal_error;
  4018. dp_err_rl(
  4019. "Tx comp release_src != TQM | FW but from %d",
  4020. buffer_src);
  4021. hal_dump_comp_desc(tx_comp_hal_desc);
  4022. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  4023. /* When WBM sees NULL buffer_addr_info in any of
  4024. * ingress rings it sends an error indication,
  4025. * with wbm_internal_error=1, to a specific ring.
  4026. * The WBM2SW ring used to indicate these errors is
  4027. * fixed in HW, and that ring is being used as Tx
  4028. * completion ring. These errors are not related to
  4029. * Tx completions, and should just be ignored
  4030. */
  4031. wbm_internal_error = hal_get_wbm_internal_error(
  4032. soc->hal_soc,
  4033. tx_comp_hal_desc);
  4034. if (wbm_internal_error) {
  4035. dp_err_rl("Tx comp wbm_internal_error!!");
  4036. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  4037. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  4038. buffer_src)
  4039. dp_handle_wbm_internal_error(
  4040. soc,
  4041. tx_comp_hal_desc,
  4042. hal_tx_comp_get_buffer_type(
  4043. tx_comp_hal_desc));
  4044. } else {
  4045. dp_err_rl("Tx comp wbm_internal_error false");
  4046. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  4047. }
  4048. continue;
  4049. }
  4050. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  4051. tx_comp_hal_desc,
  4052. &tx_desc);
  4053. if (!tx_desc) {
  4054. dp_err("unable to retrieve tx_desc!");
  4055. QDF_BUG(0);
  4056. continue;
  4057. }
  4058. tx_desc->buffer_src = buffer_src;
  4059. /*
  4060. * If the release source is FW, process the HTT status
  4061. */
  4062. if (qdf_unlikely(buffer_src ==
  4063. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  4064. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  4065. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  4066. htt_tx_status);
  4067. dp_tx_process_htt_completion(soc, tx_desc,
  4068. htt_tx_status, ring_id);
  4069. } else {
  4070. tx_desc->peer_id =
  4071. hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  4072. tx_desc->tx_status =
  4073. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  4074. tx_desc->buffer_src = buffer_src;
  4075. /*
  4076. * If the fast completion mode is enabled extended
  4077. * metadata from descriptor is not copied
  4078. */
  4079. if (qdf_likely(tx_desc->flags &
  4080. DP_TX_DESC_FLAG_SIMPLE))
  4081. goto add_to_pool;
  4082. /*
  4083. * If the descriptor is already freed in vdev_detach,
  4084. * continue to next descriptor
  4085. */
  4086. if (qdf_unlikely
  4087. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4088. !tx_desc->flags)) {
  4089. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  4090. tx_desc->id);
  4091. continue;
  4092. }
  4093. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4094. dp_tx_comp_info_rl("pdev in down state %d",
  4095. tx_desc->id);
  4096. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  4097. dp_tx_comp_free_buf(soc, tx_desc);
  4098. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4099. goto next_desc;
  4100. }
  4101. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4102. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4103. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  4104. tx_desc->flags, tx_desc->id);
  4105. qdf_assert_always(0);
  4106. }
  4107. /* Collect hw completion contents */
  4108. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4109. &tx_desc->comp, 1);
  4110. add_to_pool:
  4111. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4112. /* First ring descriptor on the cycle */
  4113. if (!head_desc) {
  4114. head_desc = tx_desc;
  4115. tail_desc = tx_desc;
  4116. }
  4117. tail_desc->next = tx_desc;
  4118. tx_desc->next = NULL;
  4119. tail_desc = tx_desc;
  4120. }
  4121. next_desc:
  4122. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4123. /*
  4124. * Processed packet count is more than given quota
  4125. * stop to processing
  4126. */
  4127. count++;
  4128. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  4129. break;
  4130. }
  4131. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4132. /* Process the reaped descriptors */
  4133. if (head_desc)
  4134. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4135. /*
  4136. * If we are processing in near-full condition, there are 3 scenario
  4137. * 1) Ring entries has reached critical state
  4138. * 2) Ring entries are still near high threshold
  4139. * 3) Ring entries are below the safe level
  4140. *
  4141. * One more loop will move te state to normal processing and yield
  4142. */
  4143. if (ring_near_full)
  4144. goto more_data;
  4145. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4146. if (num_processed >= quota)
  4147. force_break = true;
  4148. if (!force_break &&
  4149. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4150. hal_ring_hdl)) {
  4151. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4152. if (!hif_exec_should_yield(soc->hif_handle,
  4153. int_ctx->dp_intr_id))
  4154. goto more_data;
  4155. }
  4156. }
  4157. DP_TX_HIST_STATS_PER_PDEV();
  4158. return num_processed;
  4159. }
  4160. #ifdef FEATURE_WLAN_TDLS
  4161. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4162. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4163. {
  4164. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4165. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4166. DP_MOD_ID_TDLS);
  4167. if (!vdev) {
  4168. dp_err("vdev handle for id %d is NULL", vdev_id);
  4169. return NULL;
  4170. }
  4171. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4172. vdev->is_tdls_frame = true;
  4173. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4174. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4175. }
  4176. #endif
  4177. static void dp_tx_vdev_update_feature_flags(struct dp_vdev *vdev)
  4178. {
  4179. struct wlan_cfg_dp_soc_ctxt *cfg;
  4180. struct dp_soc *soc;
  4181. soc = vdev->pdev->soc;
  4182. if (!soc)
  4183. return;
  4184. cfg = soc->wlan_cfg_ctx;
  4185. if (!cfg)
  4186. return;
  4187. if (vdev->opmode == wlan_op_mode_ndi)
  4188. vdev->csum_enabled = wlan_cfg_get_nan_checksum_offload(cfg);
  4189. else if ((vdev->subtype == wlan_op_subtype_p2p_device) ||
  4190. (vdev->subtype == wlan_op_subtype_p2p_cli) ||
  4191. (vdev->subtype == wlan_op_subtype_p2p_go))
  4192. vdev->csum_enabled = wlan_cfg_get_p2p_checksum_offload(cfg);
  4193. else
  4194. vdev->csum_enabled = wlan_cfg_get_checksum_offload(cfg);
  4195. }
  4196. /**
  4197. * dp_tx_vdev_attach() - attach vdev to dp tx
  4198. * @vdev: virtual device instance
  4199. *
  4200. * Return: QDF_STATUS_SUCCESS: success
  4201. * QDF_STATUS_E_RESOURCES: Error return
  4202. */
  4203. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4204. {
  4205. int pdev_id;
  4206. /*
  4207. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4208. */
  4209. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4210. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  4211. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4212. vdev->vdev_id);
  4213. pdev_id =
  4214. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4215. vdev->pdev->pdev_id);
  4216. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4217. /*
  4218. * Set HTT Extension Valid bit to 0 by default
  4219. */
  4220. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4221. dp_tx_vdev_update_search_flags(vdev);
  4222. dp_tx_vdev_update_feature_flags(vdev);
  4223. return QDF_STATUS_SUCCESS;
  4224. }
  4225. #ifndef FEATURE_WDS
  4226. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4227. {
  4228. return false;
  4229. }
  4230. #endif
  4231. /**
  4232. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4233. * @vdev: virtual device instance
  4234. *
  4235. * Return: void
  4236. *
  4237. */
  4238. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4239. {
  4240. struct dp_soc *soc = vdev->pdev->soc;
  4241. /*
  4242. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4243. * for TDLS link
  4244. *
  4245. * Enable AddrY (SA based search) only for non-WDS STA and
  4246. * ProxySTA VAP (in HKv1) modes.
  4247. *
  4248. * In all other VAP modes, only DA based search should be
  4249. * enabled
  4250. */
  4251. if (vdev->opmode == wlan_op_mode_sta &&
  4252. vdev->tdls_link_connected)
  4253. vdev->hal_desc_addr_search_flags =
  4254. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4255. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4256. !dp_tx_da_search_override(vdev))
  4257. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4258. else
  4259. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4260. /* Set search type only when peer map v2 messaging is enabled
  4261. * as we will have the search index (AST hash) only when v2 is
  4262. * enabled
  4263. */
  4264. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  4265. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  4266. else
  4267. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4268. }
  4269. static inline bool
  4270. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4271. struct dp_vdev *vdev,
  4272. struct dp_tx_desc_s *tx_desc)
  4273. {
  4274. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4275. return false;
  4276. /*
  4277. * if vdev is given, then only check whether desc
  4278. * vdev match. if vdev is NULL, then check whether
  4279. * desc pdev match.
  4280. */
  4281. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4282. (tx_desc->pdev == pdev);
  4283. }
  4284. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4285. /**
  4286. * dp_tx_desc_flush() - release resources associated
  4287. * to TX Desc
  4288. *
  4289. * @dp_pdev: Handle to DP pdev structure
  4290. * @vdev: virtual device instance
  4291. * NULL: no specific Vdev is required and check all allcated TX desc
  4292. * on this pdev.
  4293. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4294. *
  4295. * @force_free:
  4296. * true: flush the TX desc.
  4297. * false: only reset the Vdev in each allocated TX desc
  4298. * that associated to current Vdev.
  4299. *
  4300. * This function will go through the TX desc pool to flush
  4301. * the outstanding TX data or reset Vdev to NULL in associated TX
  4302. * Desc.
  4303. */
  4304. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4305. bool force_free)
  4306. {
  4307. uint8_t i;
  4308. uint32_t j;
  4309. uint32_t num_desc, page_id, offset;
  4310. uint16_t num_desc_per_page;
  4311. struct dp_soc *soc = pdev->soc;
  4312. struct dp_tx_desc_s *tx_desc = NULL;
  4313. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4314. if (!vdev && !force_free) {
  4315. dp_err("Reset TX desc vdev, Vdev param is required!");
  4316. return;
  4317. }
  4318. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4319. tx_desc_pool = &soc->tx_desc[i];
  4320. if (!(tx_desc_pool->pool_size) ||
  4321. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4322. !(tx_desc_pool->desc_pages.cacheable_pages))
  4323. continue;
  4324. /*
  4325. * Add flow pool lock protection in case pool is freed
  4326. * due to all tx_desc is recycled when handle TX completion.
  4327. * this is not necessary when do force flush as:
  4328. * a. double lock will happen if dp_tx_desc_release is
  4329. * also trying to acquire it.
  4330. * b. dp interrupt has been disabled before do force TX desc
  4331. * flush in dp_pdev_deinit().
  4332. */
  4333. if (!force_free)
  4334. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4335. num_desc = tx_desc_pool->pool_size;
  4336. num_desc_per_page =
  4337. tx_desc_pool->desc_pages.num_element_per_page;
  4338. for (j = 0; j < num_desc; j++) {
  4339. page_id = j / num_desc_per_page;
  4340. offset = j % num_desc_per_page;
  4341. if (qdf_unlikely(!(tx_desc_pool->
  4342. desc_pages.cacheable_pages)))
  4343. break;
  4344. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4345. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4346. /*
  4347. * Free TX desc if force free is
  4348. * required, otherwise only reset vdev
  4349. * in this TX desc.
  4350. */
  4351. if (force_free) {
  4352. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4353. dp_tx_comp_free_buf(soc, tx_desc);
  4354. dp_tx_desc_release(tx_desc, i);
  4355. } else {
  4356. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4357. }
  4358. }
  4359. }
  4360. if (!force_free)
  4361. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4362. }
  4363. }
  4364. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4365. /**
  4366. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4367. *
  4368. * @soc: Handle to DP soc structure
  4369. * @tx_desc: pointer of one TX desc
  4370. * @desc_pool_id: TX Desc pool id
  4371. */
  4372. static inline void
  4373. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4374. uint8_t desc_pool_id)
  4375. {
  4376. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4377. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4378. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4379. }
  4380. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4381. bool force_free)
  4382. {
  4383. uint8_t i, num_pool;
  4384. uint32_t j;
  4385. uint32_t num_desc, page_id, offset;
  4386. uint16_t num_desc_per_page;
  4387. struct dp_soc *soc = pdev->soc;
  4388. struct dp_tx_desc_s *tx_desc = NULL;
  4389. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4390. if (!vdev && !force_free) {
  4391. dp_err("Reset TX desc vdev, Vdev param is required!");
  4392. return;
  4393. }
  4394. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4395. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4396. for (i = 0; i < num_pool; i++) {
  4397. tx_desc_pool = &soc->tx_desc[i];
  4398. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4399. continue;
  4400. num_desc_per_page =
  4401. tx_desc_pool->desc_pages.num_element_per_page;
  4402. for (j = 0; j < num_desc; j++) {
  4403. page_id = j / num_desc_per_page;
  4404. offset = j % num_desc_per_page;
  4405. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4406. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4407. if (force_free) {
  4408. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4409. dp_tx_comp_free_buf(soc, tx_desc);
  4410. dp_tx_desc_release(tx_desc, i);
  4411. } else {
  4412. dp_tx_desc_reset_vdev(soc, tx_desc,
  4413. i);
  4414. }
  4415. }
  4416. }
  4417. }
  4418. }
  4419. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4420. /**
  4421. * dp_tx_vdev_detach() - detach vdev from dp tx
  4422. * @vdev: virtual device instance
  4423. *
  4424. * Return: QDF_STATUS_SUCCESS: success
  4425. * QDF_STATUS_E_RESOURCES: Error return
  4426. */
  4427. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4428. {
  4429. struct dp_pdev *pdev = vdev->pdev;
  4430. /* Reset TX desc associated to this Vdev as NULL */
  4431. dp_tx_desc_flush(pdev, vdev, false);
  4432. return QDF_STATUS_SUCCESS;
  4433. }
  4434. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4435. /* Pools will be allocated dynamically */
  4436. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4437. int num_desc)
  4438. {
  4439. uint8_t i;
  4440. for (i = 0; i < num_pool; i++) {
  4441. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4442. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4443. }
  4444. return QDF_STATUS_SUCCESS;
  4445. }
  4446. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4447. int num_desc)
  4448. {
  4449. return QDF_STATUS_SUCCESS;
  4450. }
  4451. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4452. {
  4453. }
  4454. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4455. {
  4456. uint8_t i;
  4457. for (i = 0; i < num_pool; i++)
  4458. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4459. }
  4460. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4461. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4462. int num_desc)
  4463. {
  4464. uint8_t i, count;
  4465. /* Allocate software Tx descriptor pools */
  4466. for (i = 0; i < num_pool; i++) {
  4467. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4468. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4469. FL("Tx Desc Pool alloc %d failed %pK"),
  4470. i, soc);
  4471. goto fail;
  4472. }
  4473. }
  4474. return QDF_STATUS_SUCCESS;
  4475. fail:
  4476. for (count = 0; count < i; count++)
  4477. dp_tx_desc_pool_free(soc, count);
  4478. return QDF_STATUS_E_NOMEM;
  4479. }
  4480. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4481. int num_desc)
  4482. {
  4483. uint8_t i;
  4484. for (i = 0; i < num_pool; i++) {
  4485. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4486. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4487. FL("Tx Desc Pool init %d failed %pK"),
  4488. i, soc);
  4489. return QDF_STATUS_E_NOMEM;
  4490. }
  4491. }
  4492. return QDF_STATUS_SUCCESS;
  4493. }
  4494. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4495. {
  4496. uint8_t i;
  4497. for (i = 0; i < num_pool; i++)
  4498. dp_tx_desc_pool_deinit(soc, i);
  4499. }
  4500. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4501. {
  4502. uint8_t i;
  4503. for (i = 0; i < num_pool; i++)
  4504. dp_tx_desc_pool_free(soc, i);
  4505. }
  4506. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4507. /**
  4508. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4509. * @soc: core txrx main context
  4510. * @num_pool: number of pools
  4511. *
  4512. */
  4513. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4514. {
  4515. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4516. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4517. }
  4518. /**
  4519. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4520. * @soc: core txrx main context
  4521. * @num_pool: number of pools
  4522. *
  4523. */
  4524. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4525. {
  4526. dp_tx_tso_desc_pool_free(soc, num_pool);
  4527. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4528. }
  4529. /**
  4530. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4531. * @soc: core txrx main context
  4532. *
  4533. * This function frees all tx related descriptors as below
  4534. * 1. Regular TX descriptors (static pools)
  4535. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4536. * 3. TSO descriptors
  4537. *
  4538. */
  4539. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4540. {
  4541. uint8_t num_pool;
  4542. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4543. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4544. dp_tx_ext_desc_pool_free(soc, num_pool);
  4545. dp_tx_delete_static_pools(soc, num_pool);
  4546. }
  4547. /**
  4548. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4549. * @soc: core txrx main context
  4550. *
  4551. * This function de-initializes all tx related descriptors as below
  4552. * 1. Regular TX descriptors (static pools)
  4553. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4554. * 3. TSO descriptors
  4555. *
  4556. */
  4557. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4558. {
  4559. uint8_t num_pool;
  4560. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4561. dp_tx_flow_control_deinit(soc);
  4562. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4563. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4564. dp_tx_deinit_static_pools(soc, num_pool);
  4565. }
  4566. /**
  4567. * dp_tso_attach() - TSO attach handler
  4568. * @txrx_soc: Opaque Dp handle
  4569. *
  4570. * Reserve TSO descriptor buffers
  4571. *
  4572. * Return: QDF_STATUS_E_FAILURE on failure or
  4573. * QDF_STATUS_SUCCESS on success
  4574. */
  4575. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4576. uint8_t num_pool,
  4577. uint16_t num_desc)
  4578. {
  4579. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4580. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4581. return QDF_STATUS_E_FAILURE;
  4582. }
  4583. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4584. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4585. num_pool, soc);
  4586. return QDF_STATUS_E_FAILURE;
  4587. }
  4588. return QDF_STATUS_SUCCESS;
  4589. }
  4590. /**
  4591. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4592. * @soc: DP soc handle
  4593. * @num_pool: Number of pools
  4594. * @num_desc: Number of descriptors
  4595. *
  4596. * Initialize TSO descriptor pools
  4597. *
  4598. * Return: QDF_STATUS_E_FAILURE on failure or
  4599. * QDF_STATUS_SUCCESS on success
  4600. */
  4601. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4602. uint8_t num_pool,
  4603. uint16_t num_desc)
  4604. {
  4605. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4606. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4607. return QDF_STATUS_E_FAILURE;
  4608. }
  4609. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4610. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4611. num_pool, soc);
  4612. return QDF_STATUS_E_FAILURE;
  4613. }
  4614. return QDF_STATUS_SUCCESS;
  4615. }
  4616. /**
  4617. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4618. * @soc: core txrx main context
  4619. *
  4620. * This function allocates memory for following descriptor pools
  4621. * 1. regular sw tx descriptor pools (static pools)
  4622. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4623. * 3. TSO descriptor pools
  4624. *
  4625. * Return: QDF_STATUS_SUCCESS: success
  4626. * QDF_STATUS_E_RESOURCES: Error return
  4627. */
  4628. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4629. {
  4630. uint8_t num_pool;
  4631. uint32_t num_desc;
  4632. uint32_t num_ext_desc;
  4633. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4634. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4635. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4636. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4637. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4638. __func__, num_pool, num_desc);
  4639. if ((num_pool > MAX_TXDESC_POOLS) ||
  4640. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4641. goto fail1;
  4642. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4643. goto fail1;
  4644. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4645. goto fail2;
  4646. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4647. return QDF_STATUS_SUCCESS;
  4648. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4649. goto fail3;
  4650. return QDF_STATUS_SUCCESS;
  4651. fail3:
  4652. dp_tx_ext_desc_pool_free(soc, num_pool);
  4653. fail2:
  4654. dp_tx_delete_static_pools(soc, num_pool);
  4655. fail1:
  4656. return QDF_STATUS_E_RESOURCES;
  4657. }
  4658. /**
  4659. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4660. * @soc: core txrx main context
  4661. *
  4662. * This function initializes the following TX descriptor pools
  4663. * 1. regular sw tx descriptor pools (static pools)
  4664. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4665. * 3. TSO descriptor pools
  4666. *
  4667. * Return: QDF_STATUS_SUCCESS: success
  4668. * QDF_STATUS_E_RESOURCES: Error return
  4669. */
  4670. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4671. {
  4672. uint8_t num_pool;
  4673. uint32_t num_desc;
  4674. uint32_t num_ext_desc;
  4675. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4676. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4677. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4678. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4679. goto fail1;
  4680. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4681. goto fail2;
  4682. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4683. return QDF_STATUS_SUCCESS;
  4684. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4685. goto fail3;
  4686. dp_tx_flow_control_init(soc);
  4687. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4688. return QDF_STATUS_SUCCESS;
  4689. fail3:
  4690. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4691. fail2:
  4692. dp_tx_deinit_static_pools(soc, num_pool);
  4693. fail1:
  4694. return QDF_STATUS_E_RESOURCES;
  4695. }
  4696. /**
  4697. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4698. * @txrx_soc: dp soc handle
  4699. *
  4700. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4701. * QDF_STATUS_E_FAILURE
  4702. */
  4703. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4704. {
  4705. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4706. uint8_t num_pool;
  4707. uint32_t num_desc;
  4708. uint32_t num_ext_desc;
  4709. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4710. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4711. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4712. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4713. return QDF_STATUS_E_FAILURE;
  4714. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4715. return QDF_STATUS_E_FAILURE;
  4716. return QDF_STATUS_SUCCESS;
  4717. }
  4718. /**
  4719. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4720. * @txrx_soc: dp soc handle
  4721. *
  4722. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4723. */
  4724. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4725. {
  4726. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4727. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4728. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4729. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4730. return QDF_STATUS_SUCCESS;
  4731. }