dp_tx.c 131 KB

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  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef FEATURE_WDS
  37. #include "dp_txrx_wds.h"
  38. #endif
  39. #ifdef ATH_SUPPORT_IQUE
  40. #include "dp_txrx_me.h"
  41. #endif
  42. #include "dp_hist.h"
  43. /* TODO Add support in TSO */
  44. #define DP_DESC_NUM_FRAG(x) 0
  45. /* disable TQM_BYPASS */
  46. #define TQM_BYPASS_WAR 0
  47. /* invalid peer id for reinject*/
  48. #define DP_INVALID_PEER 0XFFFE
  49. /*mapping between hal encrypt type and cdp_sec_type*/
  50. #define MAX_CDP_SEC_TYPE 12
  51. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  52. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  53. HAL_TX_ENCRYPT_TYPE_WEP_128,
  54. HAL_TX_ENCRYPT_TYPE_WEP_104,
  55. HAL_TX_ENCRYPT_TYPE_WEP_40,
  56. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  57. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  58. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  59. HAL_TX_ENCRYPT_TYPE_WAPI,
  60. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  61. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  62. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  63. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  64. #ifdef QCA_TX_LIMIT_CHECK
  65. /**
  66. * dp_tx_limit_check - Check if allocated tx descriptors reached
  67. * soc max limit and pdev max limit
  68. * @vdev: DP vdev handle
  69. *
  70. * Return: true if allocated tx descriptors reached max configured value, else
  71. * false
  72. */
  73. static inline bool
  74. dp_tx_limit_check(struct dp_vdev *vdev)
  75. {
  76. struct dp_pdev *pdev = vdev->pdev;
  77. struct dp_soc *soc = pdev->soc;
  78. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  79. soc->num_tx_allowed) {
  80. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  81. "%s: queued packets are more than max tx, drop the frame",
  82. __func__);
  83. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  84. return true;
  85. }
  86. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  87. pdev->num_tx_allowed) {
  88. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  89. "%s: queued packets are more than max tx, drop the frame",
  90. __func__);
  91. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  92. return true;
  93. }
  94. return false;
  95. }
  96. /**
  97. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  98. * reached soc max limit
  99. * @vdev: DP vdev handle
  100. *
  101. * Return: true if allocated tx descriptors reached max configured value, else
  102. * false
  103. */
  104. static inline bool
  105. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  106. {
  107. struct dp_pdev *pdev = vdev->pdev;
  108. struct dp_soc *soc = pdev->soc;
  109. if (qdf_atomic_read(&soc->num_tx_exception) >=
  110. soc->num_msdu_exception_desc) {
  111. dp_info("exc packets are more than max drop the exc pkt");
  112. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  113. return true;
  114. }
  115. return false;
  116. }
  117. /**
  118. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  119. * @vdev: DP pdev handle
  120. *
  121. * Return: void
  122. */
  123. static inline void
  124. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  125. {
  126. struct dp_soc *soc = pdev->soc;
  127. qdf_atomic_inc(&pdev->num_tx_outstanding);
  128. qdf_atomic_inc(&soc->num_tx_outstanding);
  129. }
  130. /**
  131. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  132. * @vdev: DP pdev handle
  133. *
  134. * Return: void
  135. */
  136. static inline void
  137. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  138. {
  139. struct dp_soc *soc = pdev->soc;
  140. qdf_atomic_dec(&pdev->num_tx_outstanding);
  141. qdf_atomic_dec(&soc->num_tx_outstanding);
  142. }
  143. #else //QCA_TX_LIMIT_CHECK
  144. static inline bool
  145. dp_tx_limit_check(struct dp_vdev *vdev)
  146. {
  147. return false;
  148. }
  149. static inline bool
  150. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  151. {
  152. return false;
  153. }
  154. static inline void
  155. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  156. {
  157. qdf_atomic_inc(&pdev->num_tx_outstanding);
  158. }
  159. static inline void
  160. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  161. {
  162. qdf_atomic_dec(&pdev->num_tx_outstanding);
  163. }
  164. #endif //QCA_TX_LIMIT_CHECK
  165. #if defined(FEATURE_TSO)
  166. /**
  167. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  168. *
  169. * @soc - core txrx main context
  170. * @seg_desc - tso segment descriptor
  171. * @num_seg_desc - tso number segment descriptor
  172. */
  173. static void dp_tx_tso_unmap_segment(
  174. struct dp_soc *soc,
  175. struct qdf_tso_seg_elem_t *seg_desc,
  176. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  177. {
  178. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  179. if (qdf_unlikely(!seg_desc)) {
  180. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  181. __func__, __LINE__);
  182. qdf_assert(0);
  183. } else if (qdf_unlikely(!num_seg_desc)) {
  184. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  185. __func__, __LINE__);
  186. qdf_assert(0);
  187. } else {
  188. bool is_last_seg;
  189. /* no tso segment left to do dma unmap */
  190. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  191. return;
  192. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  193. true : false;
  194. qdf_nbuf_unmap_tso_segment(soc->osdev,
  195. seg_desc, is_last_seg);
  196. num_seg_desc->num_seg.tso_cmn_num_seg--;
  197. }
  198. }
  199. /**
  200. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  201. * back to the freelist
  202. *
  203. * @soc - soc device handle
  204. * @tx_desc - Tx software descriptor
  205. */
  206. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  207. struct dp_tx_desc_s *tx_desc)
  208. {
  209. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  210. if (qdf_unlikely(!tx_desc->tso_desc)) {
  211. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  212. "%s %d TSO desc is NULL!",
  213. __func__, __LINE__);
  214. qdf_assert(0);
  215. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  216. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  217. "%s %d TSO num desc is NULL!",
  218. __func__, __LINE__);
  219. qdf_assert(0);
  220. } else {
  221. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  222. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  223. /* Add the tso num segment into the free list */
  224. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  225. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  226. tx_desc->tso_num_desc);
  227. tx_desc->tso_num_desc = NULL;
  228. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  229. }
  230. /* Add the tso segment into the free list*/
  231. dp_tx_tso_desc_free(soc,
  232. tx_desc->pool_id, tx_desc->tso_desc);
  233. tx_desc->tso_desc = NULL;
  234. }
  235. }
  236. #else
  237. static void dp_tx_tso_unmap_segment(
  238. struct dp_soc *soc,
  239. struct qdf_tso_seg_elem_t *seg_desc,
  240. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  241. {
  242. }
  243. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  244. struct dp_tx_desc_s *tx_desc)
  245. {
  246. }
  247. #endif
  248. /**
  249. * dp_tx_desc_release() - Release Tx Descriptor
  250. * @tx_desc : Tx Descriptor
  251. * @desc_pool_id: Descriptor Pool ID
  252. *
  253. * Deallocate all resources attached to Tx descriptor and free the Tx
  254. * descriptor.
  255. *
  256. * Return:
  257. */
  258. static void
  259. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  260. {
  261. struct dp_pdev *pdev = tx_desc->pdev;
  262. struct dp_soc *soc;
  263. uint8_t comp_status = 0;
  264. qdf_assert(pdev);
  265. soc = pdev->soc;
  266. dp_tx_outstanding_dec(pdev);
  267. if (tx_desc->frm_type == dp_tx_frm_tso)
  268. dp_tx_tso_desc_release(soc, tx_desc);
  269. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  270. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  271. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  272. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  273. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  274. qdf_atomic_dec(&soc->num_tx_exception);
  275. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  276. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  277. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  278. soc->hal_soc);
  279. else
  280. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  281. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  282. "Tx Completion Release desc %d status %d outstanding %d",
  283. tx_desc->id, comp_status,
  284. qdf_atomic_read(&pdev->num_tx_outstanding));
  285. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  286. return;
  287. }
  288. /**
  289. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  290. * @vdev: DP vdev Handle
  291. * @nbuf: skb
  292. * @msdu_info: msdu_info required to create HTT metadata
  293. *
  294. * Prepares and fills HTT metadata in the frame pre-header for special frames
  295. * that should be transmitted using varying transmit parameters.
  296. * There are 2 VDEV modes that currently needs this special metadata -
  297. * 1) Mesh Mode
  298. * 2) DSRC Mode
  299. *
  300. * Return: HTT metadata size
  301. *
  302. */
  303. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  304. struct dp_tx_msdu_info_s *msdu_info)
  305. {
  306. uint32_t *meta_data = msdu_info->meta_data;
  307. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  308. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  309. uint8_t htt_desc_size;
  310. /* Size rounded of multiple of 8 bytes */
  311. uint8_t htt_desc_size_aligned;
  312. uint8_t *hdr = NULL;
  313. /*
  314. * Metadata - HTT MSDU Extension header
  315. */
  316. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  317. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  318. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  319. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  320. meta_data[0])) {
  321. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  322. htt_desc_size_aligned)) {
  323. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  324. htt_desc_size_aligned);
  325. if (!nbuf) {
  326. /*
  327. * qdf_nbuf_realloc_headroom won't do skb_clone
  328. * as skb_realloc_headroom does. so, no free is
  329. * needed here.
  330. */
  331. DP_STATS_INC(vdev,
  332. tx_i.dropped.headroom_insufficient,
  333. 1);
  334. qdf_print(" %s[%d] skb_realloc_headroom failed",
  335. __func__, __LINE__);
  336. return 0;
  337. }
  338. }
  339. /* Fill and add HTT metaheader */
  340. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  341. if (!hdr) {
  342. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  343. "Error in filling HTT metadata");
  344. return 0;
  345. }
  346. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  347. } else if (vdev->opmode == wlan_op_mode_ocb) {
  348. /* Todo - Add support for DSRC */
  349. }
  350. return htt_desc_size_aligned;
  351. }
  352. /**
  353. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  354. * @tso_seg: TSO segment to process
  355. * @ext_desc: Pointer to MSDU extension descriptor
  356. *
  357. * Return: void
  358. */
  359. #if defined(FEATURE_TSO)
  360. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  361. void *ext_desc)
  362. {
  363. uint8_t num_frag;
  364. uint32_t tso_flags;
  365. /*
  366. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  367. * tcp_flag_mask
  368. *
  369. * Checksum enable flags are set in TCL descriptor and not in Extension
  370. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  371. */
  372. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  373. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  374. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  375. tso_seg->tso_flags.ip_len);
  376. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  377. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  378. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  379. uint32_t lo = 0;
  380. uint32_t hi = 0;
  381. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  382. (tso_seg->tso_frags[num_frag].length));
  383. qdf_dmaaddr_to_32s(
  384. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  385. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  386. tso_seg->tso_frags[num_frag].length);
  387. }
  388. return;
  389. }
  390. #else
  391. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  392. void *ext_desc)
  393. {
  394. return;
  395. }
  396. #endif
  397. #if defined(FEATURE_TSO)
  398. /**
  399. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  400. * allocated and free them
  401. *
  402. * @soc: soc handle
  403. * @free_seg: list of tso segments
  404. * @msdu_info: msdu descriptor
  405. *
  406. * Return - void
  407. */
  408. static void dp_tx_free_tso_seg_list(
  409. struct dp_soc *soc,
  410. struct qdf_tso_seg_elem_t *free_seg,
  411. struct dp_tx_msdu_info_s *msdu_info)
  412. {
  413. struct qdf_tso_seg_elem_t *next_seg;
  414. while (free_seg) {
  415. next_seg = free_seg->next;
  416. dp_tx_tso_desc_free(soc,
  417. msdu_info->tx_queue.desc_pool_id,
  418. free_seg);
  419. free_seg = next_seg;
  420. }
  421. }
  422. /**
  423. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  424. * allocated and free them
  425. *
  426. * @soc: soc handle
  427. * @free_num_seg: list of tso number segments
  428. * @msdu_info: msdu descriptor
  429. * Return - void
  430. */
  431. static void dp_tx_free_tso_num_seg_list(
  432. struct dp_soc *soc,
  433. struct qdf_tso_num_seg_elem_t *free_num_seg,
  434. struct dp_tx_msdu_info_s *msdu_info)
  435. {
  436. struct qdf_tso_num_seg_elem_t *next_num_seg;
  437. while (free_num_seg) {
  438. next_num_seg = free_num_seg->next;
  439. dp_tso_num_seg_free(soc,
  440. msdu_info->tx_queue.desc_pool_id,
  441. free_num_seg);
  442. free_num_seg = next_num_seg;
  443. }
  444. }
  445. /**
  446. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  447. * do dma unmap for each segment
  448. *
  449. * @soc: soc handle
  450. * @free_seg: list of tso segments
  451. * @num_seg_desc: tso number segment descriptor
  452. *
  453. * Return - void
  454. */
  455. static void dp_tx_unmap_tso_seg_list(
  456. struct dp_soc *soc,
  457. struct qdf_tso_seg_elem_t *free_seg,
  458. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  459. {
  460. struct qdf_tso_seg_elem_t *next_seg;
  461. if (qdf_unlikely(!num_seg_desc)) {
  462. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  463. return;
  464. }
  465. while (free_seg) {
  466. next_seg = free_seg->next;
  467. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  468. free_seg = next_seg;
  469. }
  470. }
  471. #ifdef FEATURE_TSO_STATS
  472. /**
  473. * dp_tso_get_stats_idx: Retrieve the tso packet id
  474. * @pdev - pdev handle
  475. *
  476. * Return: id
  477. */
  478. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  479. {
  480. uint32_t stats_idx;
  481. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  482. % CDP_MAX_TSO_PACKETS);
  483. return stats_idx;
  484. }
  485. #else
  486. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  487. {
  488. return 0;
  489. }
  490. #endif /* FEATURE_TSO_STATS */
  491. /**
  492. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  493. * free the tso segments descriptor and
  494. * tso num segments descriptor
  495. *
  496. * @soc: soc handle
  497. * @msdu_info: msdu descriptor
  498. * @tso_seg_unmap: flag to show if dma unmap is necessary
  499. *
  500. * Return - void
  501. */
  502. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  503. struct dp_tx_msdu_info_s *msdu_info,
  504. bool tso_seg_unmap)
  505. {
  506. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  507. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  508. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  509. tso_info->tso_num_seg_list;
  510. /* do dma unmap for each segment */
  511. if (tso_seg_unmap)
  512. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  513. /* free all tso number segment descriptor though looks only have 1 */
  514. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  515. /* free all tso segment descriptor */
  516. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  517. }
  518. /**
  519. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  520. * @vdev: virtual device handle
  521. * @msdu: network buffer
  522. * @msdu_info: meta data associated with the msdu
  523. *
  524. * Return: QDF_STATUS_SUCCESS success
  525. */
  526. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  527. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  528. {
  529. struct qdf_tso_seg_elem_t *tso_seg;
  530. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  531. struct dp_soc *soc = vdev->pdev->soc;
  532. struct dp_pdev *pdev = vdev->pdev;
  533. struct qdf_tso_info_t *tso_info;
  534. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  535. tso_info = &msdu_info->u.tso_info;
  536. tso_info->curr_seg = NULL;
  537. tso_info->tso_seg_list = NULL;
  538. tso_info->num_segs = num_seg;
  539. msdu_info->frm_type = dp_tx_frm_tso;
  540. tso_info->tso_num_seg_list = NULL;
  541. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  542. while (num_seg) {
  543. tso_seg = dp_tx_tso_desc_alloc(
  544. soc, msdu_info->tx_queue.desc_pool_id);
  545. if (tso_seg) {
  546. tso_seg->next = tso_info->tso_seg_list;
  547. tso_info->tso_seg_list = tso_seg;
  548. num_seg--;
  549. } else {
  550. dp_err_rl("Failed to alloc tso seg desc");
  551. DP_STATS_INC_PKT(vdev->pdev,
  552. tso_stats.tso_no_mem_dropped, 1,
  553. qdf_nbuf_len(msdu));
  554. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  555. return QDF_STATUS_E_NOMEM;
  556. }
  557. }
  558. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  559. tso_num_seg = dp_tso_num_seg_alloc(soc,
  560. msdu_info->tx_queue.desc_pool_id);
  561. if (tso_num_seg) {
  562. tso_num_seg->next = tso_info->tso_num_seg_list;
  563. tso_info->tso_num_seg_list = tso_num_seg;
  564. } else {
  565. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  566. __func__);
  567. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  568. return QDF_STATUS_E_NOMEM;
  569. }
  570. msdu_info->num_seg =
  571. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  572. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  573. msdu_info->num_seg);
  574. if (!(msdu_info->num_seg)) {
  575. /*
  576. * Free allocated TSO seg desc and number seg desc,
  577. * do unmap for segments if dma map has done.
  578. */
  579. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  580. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  581. return QDF_STATUS_E_INVAL;
  582. }
  583. tso_info->curr_seg = tso_info->tso_seg_list;
  584. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  585. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  586. msdu, msdu_info->num_seg);
  587. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  588. tso_info->msdu_stats_idx);
  589. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  590. return QDF_STATUS_SUCCESS;
  591. }
  592. #else
  593. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  594. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  595. {
  596. return QDF_STATUS_E_NOMEM;
  597. }
  598. #endif
  599. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  600. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  601. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  602. /**
  603. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  604. * @vdev: DP Vdev handle
  605. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  606. * @desc_pool_id: Descriptor Pool ID
  607. *
  608. * Return:
  609. */
  610. static
  611. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  612. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  613. {
  614. uint8_t i;
  615. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  616. struct dp_tx_seg_info_s *seg_info;
  617. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  618. struct dp_soc *soc = vdev->pdev->soc;
  619. /* Allocate an extension descriptor */
  620. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  621. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  622. if (!msdu_ext_desc) {
  623. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  624. return NULL;
  625. }
  626. if (msdu_info->exception_fw &&
  627. qdf_unlikely(vdev->mesh_vdev)) {
  628. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  629. &msdu_info->meta_data[0],
  630. sizeof(struct htt_tx_msdu_desc_ext2_t));
  631. qdf_atomic_inc(&soc->num_tx_exception);
  632. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  633. }
  634. switch (msdu_info->frm_type) {
  635. case dp_tx_frm_sg:
  636. case dp_tx_frm_me:
  637. case dp_tx_frm_raw:
  638. seg_info = msdu_info->u.sg_info.curr_seg;
  639. /* Update the buffer pointers in MSDU Extension Descriptor */
  640. for (i = 0; i < seg_info->frag_cnt; i++) {
  641. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  642. seg_info->frags[i].paddr_lo,
  643. seg_info->frags[i].paddr_hi,
  644. seg_info->frags[i].len);
  645. }
  646. break;
  647. case dp_tx_frm_tso:
  648. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  649. &cached_ext_desc[0]);
  650. break;
  651. default:
  652. break;
  653. }
  654. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  655. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  656. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  657. msdu_ext_desc->vaddr);
  658. return msdu_ext_desc;
  659. }
  660. /**
  661. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  662. *
  663. * @skb: skb to be traced
  664. * @msdu_id: msdu_id of the packet
  665. * @vdev_id: vdev_id of the packet
  666. *
  667. * Return: None
  668. */
  669. #ifdef DP_DISABLE_TX_PKT_TRACE
  670. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  671. uint8_t vdev_id)
  672. {
  673. }
  674. #else
  675. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  676. uint8_t vdev_id)
  677. {
  678. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  679. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  680. DPTRACE(qdf_dp_trace_ptr(skb,
  681. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  682. QDF_TRACE_DEFAULT_PDEV_ID,
  683. qdf_nbuf_data_addr(skb),
  684. sizeof(qdf_nbuf_data(skb)),
  685. msdu_id, vdev_id));
  686. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  687. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  688. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  689. msdu_id, QDF_TX));
  690. }
  691. #endif
  692. /**
  693. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  694. * @vdev: DP vdev handle
  695. * @nbuf: skb
  696. * @desc_pool_id: Descriptor pool ID
  697. * @meta_data: Metadata to the fw
  698. * @tx_exc_metadata: Handle that holds exception path metadata
  699. * Allocate and prepare Tx descriptor with msdu information.
  700. *
  701. * Return: Pointer to Tx Descriptor on success,
  702. * NULL on failure
  703. */
  704. static
  705. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  706. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  707. struct dp_tx_msdu_info_s *msdu_info,
  708. struct cdp_tx_exception_metadata *tx_exc_metadata)
  709. {
  710. uint8_t align_pad;
  711. uint8_t is_exception = 0;
  712. uint8_t htt_hdr_size;
  713. struct dp_tx_desc_s *tx_desc;
  714. struct dp_pdev *pdev = vdev->pdev;
  715. struct dp_soc *soc = pdev->soc;
  716. if (dp_tx_limit_check(vdev))
  717. return NULL;
  718. /* Allocate software Tx descriptor */
  719. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  720. if (qdf_unlikely(!tx_desc)) {
  721. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  722. return NULL;
  723. }
  724. dp_tx_outstanding_inc(pdev);
  725. /* Initialize the SW tx descriptor */
  726. tx_desc->nbuf = nbuf;
  727. tx_desc->frm_type = dp_tx_frm_std;
  728. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  729. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  730. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  731. tx_desc->vdev_id = vdev->vdev_id;
  732. tx_desc->pdev = pdev;
  733. tx_desc->msdu_ext_desc = NULL;
  734. tx_desc->pkt_offset = 0;
  735. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  736. if (qdf_unlikely(vdev->multipass_en)) {
  737. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  738. goto failure;
  739. }
  740. /*
  741. * For special modes (vdev_type == ocb or mesh), data frames should be
  742. * transmitted using varying transmit parameters (tx spec) which include
  743. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  744. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  745. * These frames are sent as exception packets to firmware.
  746. *
  747. * HW requirement is that metadata should always point to a
  748. * 8-byte aligned address. So we add alignment pad to start of buffer.
  749. * HTT Metadata should be ensured to be multiple of 8-bytes,
  750. * to get 8-byte aligned start address along with align_pad added
  751. *
  752. * |-----------------------------|
  753. * | |
  754. * |-----------------------------| <-----Buffer Pointer Address given
  755. * | | ^ in HW descriptor (aligned)
  756. * | HTT Metadata | |
  757. * | | |
  758. * | | | Packet Offset given in descriptor
  759. * | | |
  760. * |-----------------------------| |
  761. * | Alignment Pad | v
  762. * |-----------------------------| <----- Actual buffer start address
  763. * | SKB Data | (Unaligned)
  764. * | |
  765. * | |
  766. * | |
  767. * | |
  768. * | |
  769. * |-----------------------------|
  770. */
  771. if (qdf_unlikely((msdu_info->exception_fw)) ||
  772. (vdev->opmode == wlan_op_mode_ocb) ||
  773. (tx_exc_metadata &&
  774. tx_exc_metadata->is_tx_sniffer)) {
  775. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  776. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  777. DP_STATS_INC(vdev,
  778. tx_i.dropped.headroom_insufficient, 1);
  779. goto failure;
  780. }
  781. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  782. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  783. "qdf_nbuf_push_head failed");
  784. goto failure;
  785. }
  786. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  787. msdu_info);
  788. if (htt_hdr_size == 0)
  789. goto failure;
  790. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  791. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  792. is_exception = 1;
  793. }
  794. #if !TQM_BYPASS_WAR
  795. if (is_exception || tx_exc_metadata)
  796. #endif
  797. {
  798. /* Temporary WAR due to TQM VP issues */
  799. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  800. qdf_atomic_inc(&soc->num_tx_exception);
  801. }
  802. return tx_desc;
  803. failure:
  804. dp_tx_desc_release(tx_desc, desc_pool_id);
  805. return NULL;
  806. }
  807. /**
  808. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  809. * @vdev: DP vdev handle
  810. * @nbuf: skb
  811. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  812. * @desc_pool_id : Descriptor Pool ID
  813. *
  814. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  815. * information. For frames wth fragments, allocate and prepare
  816. * an MSDU extension descriptor
  817. *
  818. * Return: Pointer to Tx Descriptor on success,
  819. * NULL on failure
  820. */
  821. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  822. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  823. uint8_t desc_pool_id)
  824. {
  825. struct dp_tx_desc_s *tx_desc;
  826. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  827. struct dp_pdev *pdev = vdev->pdev;
  828. struct dp_soc *soc = pdev->soc;
  829. if (dp_tx_limit_check(vdev))
  830. return NULL;
  831. /* Allocate software Tx descriptor */
  832. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  833. if (!tx_desc) {
  834. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  835. return NULL;
  836. }
  837. dp_tx_outstanding_inc(pdev);
  838. /* Initialize the SW tx descriptor */
  839. tx_desc->nbuf = nbuf;
  840. tx_desc->frm_type = msdu_info->frm_type;
  841. tx_desc->tx_encap_type = vdev->tx_encap_type;
  842. tx_desc->vdev_id = vdev->vdev_id;
  843. tx_desc->pdev = pdev;
  844. tx_desc->pkt_offset = 0;
  845. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  846. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  847. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  848. /* Handle scattered frames - TSO/SG/ME */
  849. /* Allocate and prepare an extension descriptor for scattered frames */
  850. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  851. if (!msdu_ext_desc) {
  852. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  853. "%s Tx Extension Descriptor Alloc Fail",
  854. __func__);
  855. goto failure;
  856. }
  857. #if TQM_BYPASS_WAR
  858. /* Temporary WAR due to TQM VP issues */
  859. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  860. qdf_atomic_inc(&soc->num_tx_exception);
  861. #endif
  862. if (qdf_unlikely(msdu_info->exception_fw))
  863. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  864. tx_desc->msdu_ext_desc = msdu_ext_desc;
  865. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  866. return tx_desc;
  867. failure:
  868. dp_tx_desc_release(tx_desc, desc_pool_id);
  869. return NULL;
  870. }
  871. /**
  872. * dp_tx_prepare_raw() - Prepare RAW packet TX
  873. * @vdev: DP vdev handle
  874. * @nbuf: buffer pointer
  875. * @seg_info: Pointer to Segment info Descriptor to be prepared
  876. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  877. * descriptor
  878. *
  879. * Return:
  880. */
  881. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  882. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  883. {
  884. qdf_nbuf_t curr_nbuf = NULL;
  885. uint16_t total_len = 0;
  886. qdf_dma_addr_t paddr;
  887. int32_t i;
  888. int32_t mapped_buf_num = 0;
  889. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  890. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  891. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  892. /* Continue only if frames are of DATA type */
  893. if (!DP_FRAME_IS_DATA(qos_wh)) {
  894. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  895. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  896. "Pkt. recd is of not data type");
  897. goto error;
  898. }
  899. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  900. if (vdev->raw_mode_war &&
  901. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  902. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  903. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  904. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  905. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  906. if (QDF_STATUS_SUCCESS !=
  907. qdf_nbuf_map_nbytes_single(vdev->osdev,
  908. curr_nbuf,
  909. QDF_DMA_TO_DEVICE,
  910. curr_nbuf->len)) {
  911. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  912. "%s dma map error ", __func__);
  913. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  914. mapped_buf_num = i;
  915. goto error;
  916. }
  917. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  918. seg_info->frags[i].paddr_lo = paddr;
  919. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  920. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  921. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  922. total_len += qdf_nbuf_len(curr_nbuf);
  923. }
  924. seg_info->frag_cnt = i;
  925. seg_info->total_len = total_len;
  926. seg_info->next = NULL;
  927. sg_info->curr_seg = seg_info;
  928. msdu_info->frm_type = dp_tx_frm_raw;
  929. msdu_info->num_seg = 1;
  930. return nbuf;
  931. error:
  932. i = 0;
  933. while (nbuf) {
  934. curr_nbuf = nbuf;
  935. if (i < mapped_buf_num) {
  936. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  937. QDF_DMA_TO_DEVICE,
  938. curr_nbuf->len);
  939. i++;
  940. }
  941. nbuf = qdf_nbuf_next(nbuf);
  942. qdf_nbuf_free(curr_nbuf);
  943. }
  944. return NULL;
  945. }
  946. /**
  947. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  948. * @soc: DP soc handle
  949. * @nbuf: Buffer pointer
  950. *
  951. * unmap the chain of nbufs that belong to this RAW frame.
  952. *
  953. * Return: None
  954. */
  955. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  956. qdf_nbuf_t nbuf)
  957. {
  958. qdf_nbuf_t cur_nbuf = nbuf;
  959. do {
  960. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  961. QDF_DMA_TO_DEVICE,
  962. cur_nbuf->len);
  963. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  964. } while (cur_nbuf);
  965. }
  966. #ifdef VDEV_PEER_PROTOCOL_COUNT
  967. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, nbuf) \
  968. { \
  969. qdf_nbuf_t nbuf_local; \
  970. struct dp_vdev *vdev_local = vdev_hdl; \
  971. do { \
  972. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  973. break; \
  974. nbuf_local = nbuf; \
  975. if (qdf_unlikely(((vdev_local)->tx_encap_type) == \
  976. htt_cmn_pkt_type_raw)) \
  977. break; \
  978. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local)))) \
  979. break; \
  980. else if (qdf_nbuf_is_tso((nbuf_local))) \
  981. break; \
  982. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  983. (nbuf_local), \
  984. NULL, 1, 0); \
  985. } while (0); \
  986. }
  987. #else
  988. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, skb)
  989. #endif
  990. /**
  991. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  992. * @soc: DP Soc Handle
  993. * @vdev: DP vdev handle
  994. * @tx_desc: Tx Descriptor Handle
  995. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  996. * @fw_metadata: Metadata to send to Target Firmware along with frame
  997. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  998. * @tx_exc_metadata: Handle that holds exception path meta data
  999. *
  1000. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  1001. * from software Tx descriptor
  1002. *
  1003. * Return: QDF_STATUS_SUCCESS: success
  1004. * QDF_STATUS_E_RESOURCES: Error return
  1005. */
  1006. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  1007. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  1008. uint16_t fw_metadata, uint8_t ring_id,
  1009. struct cdp_tx_exception_metadata
  1010. *tx_exc_metadata)
  1011. {
  1012. uint8_t type;
  1013. void *hal_tx_desc;
  1014. uint32_t *hal_tx_desc_cached;
  1015. /*
  1016. * Setting it initialization statically here to avoid
  1017. * a memset call jump with qdf_mem_set call
  1018. */
  1019. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1020. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  1021. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  1022. tx_exc_metadata->sec_type : vdev->sec_type);
  1023. /* Return Buffer Manager ID */
  1024. uint8_t bm_id = dp_tx_get_rbm_id(soc, ring_id);
  1025. hal_ring_handle_t hal_ring_hdl = NULL;
  1026. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1027. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1028. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1029. return QDF_STATUS_E_RESOURCES;
  1030. }
  1031. hal_tx_desc_cached = (void *) cached_desc;
  1032. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  1033. type = HAL_TX_BUF_TYPE_EXT_DESC;
  1034. tx_desc->dma_addr = tx_desc->msdu_ext_desc->paddr;
  1035. if (tx_desc->msdu_ext_desc->flags &
  1036. DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1037. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1038. else
  1039. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1040. } else {
  1041. tx_desc->length = qdf_nbuf_len(tx_desc->nbuf) -
  1042. tx_desc->pkt_offset;
  1043. type = HAL_TX_BUF_TYPE_BUFFER;
  1044. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1045. }
  1046. qdf_assert_always(tx_desc->dma_addr);
  1047. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  1048. tx_desc->dma_addr, bm_id, tx_desc->id,
  1049. type);
  1050. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  1051. vdev->lmac_id);
  1052. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  1053. vdev->search_type);
  1054. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  1055. vdev->bss_ast_idx);
  1056. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  1057. vdev->dscp_tid_map_id);
  1058. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  1059. sec_type_map[sec_type]);
  1060. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1061. (vdev->bss_ast_hash & 0xF));
  1062. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1063. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1064. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1065. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  1066. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1067. vdev->hal_desc_addr_search_flags);
  1068. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1069. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1070. /* verify checksum offload configuration*/
  1071. if (vdev->csum_enabled &&
  1072. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1073. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1074. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1075. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1076. }
  1077. if (tid != HTT_TX_EXT_TID_INVALID)
  1078. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1079. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1080. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1081. if (qdf_unlikely(vdev->pdev->delay_stats_flag) ||
  1082. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  1083. soc->wlan_cfg_ctx)))
  1084. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  1085. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1086. tx_desc->length, type, (uint64_t)tx_desc->dma_addr,
  1087. tx_desc->pkt_offset, tx_desc->id);
  1088. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1089. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1090. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1091. "%s %d : HAL RING Access Failed -- %pK",
  1092. __func__, __LINE__, hal_ring_hdl);
  1093. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1094. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1095. return status;
  1096. }
  1097. /* Sync cached descriptor with HW */
  1098. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1099. if (qdf_unlikely(!hal_tx_desc)) {
  1100. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1101. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1102. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1103. goto ring_access_fail;
  1104. }
  1105. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1106. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1107. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1108. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  1109. status = QDF_STATUS_SUCCESS;
  1110. ring_access_fail:
  1111. if (hif_pm_runtime_get(soc->hif_handle,
  1112. RTPM_ID_DW_TX_HW_ENQUEUE) == 0) {
  1113. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1114. hif_pm_runtime_put(soc->hif_handle,
  1115. RTPM_ID_DW_TX_HW_ENQUEUE);
  1116. } else {
  1117. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1118. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1119. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1120. }
  1121. return status;
  1122. }
  1123. /**
  1124. * dp_cce_classify() - Classify the frame based on CCE rules
  1125. * @vdev: DP vdev handle
  1126. * @nbuf: skb
  1127. *
  1128. * Classify frames based on CCE rules
  1129. * Return: bool( true if classified,
  1130. * else false)
  1131. */
  1132. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1133. {
  1134. qdf_ether_header_t *eh = NULL;
  1135. uint16_t ether_type;
  1136. qdf_llc_t *llcHdr;
  1137. qdf_nbuf_t nbuf_clone = NULL;
  1138. qdf_dot3_qosframe_t *qos_wh = NULL;
  1139. /* for mesh packets don't do any classification */
  1140. if (qdf_unlikely(vdev->mesh_vdev))
  1141. return false;
  1142. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1143. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1144. ether_type = eh->ether_type;
  1145. llcHdr = (qdf_llc_t *)(nbuf->data +
  1146. sizeof(qdf_ether_header_t));
  1147. } else {
  1148. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1149. /* For encrypted packets don't do any classification */
  1150. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1151. return false;
  1152. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1153. if (qdf_unlikely(
  1154. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1155. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1156. ether_type = *(uint16_t *)(nbuf->data
  1157. + QDF_IEEE80211_4ADDR_HDR_LEN
  1158. + sizeof(qdf_llc_t)
  1159. - sizeof(ether_type));
  1160. llcHdr = (qdf_llc_t *)(nbuf->data +
  1161. QDF_IEEE80211_4ADDR_HDR_LEN);
  1162. } else {
  1163. ether_type = *(uint16_t *)(nbuf->data
  1164. + QDF_IEEE80211_3ADDR_HDR_LEN
  1165. + sizeof(qdf_llc_t)
  1166. - sizeof(ether_type));
  1167. llcHdr = (qdf_llc_t *)(nbuf->data +
  1168. QDF_IEEE80211_3ADDR_HDR_LEN);
  1169. }
  1170. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1171. && (ether_type ==
  1172. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1173. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1174. return true;
  1175. }
  1176. }
  1177. return false;
  1178. }
  1179. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1180. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1181. sizeof(*llcHdr));
  1182. nbuf_clone = qdf_nbuf_clone(nbuf);
  1183. if (qdf_unlikely(nbuf_clone)) {
  1184. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1185. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1186. qdf_nbuf_pull_head(nbuf_clone,
  1187. sizeof(qdf_net_vlanhdr_t));
  1188. }
  1189. }
  1190. } else {
  1191. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1192. nbuf_clone = qdf_nbuf_clone(nbuf);
  1193. if (qdf_unlikely(nbuf_clone)) {
  1194. qdf_nbuf_pull_head(nbuf_clone,
  1195. sizeof(qdf_net_vlanhdr_t));
  1196. }
  1197. }
  1198. }
  1199. if (qdf_unlikely(nbuf_clone))
  1200. nbuf = nbuf_clone;
  1201. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1202. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1203. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1204. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1205. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1206. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1207. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1208. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1209. if (qdf_unlikely(nbuf_clone))
  1210. qdf_nbuf_free(nbuf_clone);
  1211. return true;
  1212. }
  1213. if (qdf_unlikely(nbuf_clone))
  1214. qdf_nbuf_free(nbuf_clone);
  1215. return false;
  1216. }
  1217. /**
  1218. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1219. * @vdev: DP vdev handle
  1220. * @nbuf: skb
  1221. *
  1222. * Extract the DSCP or PCP information from frame and map into TID value.
  1223. *
  1224. * Return: void
  1225. */
  1226. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1227. struct dp_tx_msdu_info_s *msdu_info)
  1228. {
  1229. uint8_t tos = 0, dscp_tid_override = 0;
  1230. uint8_t *hdr_ptr, *L3datap;
  1231. uint8_t is_mcast = 0;
  1232. qdf_ether_header_t *eh = NULL;
  1233. qdf_ethervlan_header_t *evh = NULL;
  1234. uint16_t ether_type;
  1235. qdf_llc_t *llcHdr;
  1236. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1237. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1238. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1239. eh = (qdf_ether_header_t *)nbuf->data;
  1240. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1241. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1242. } else {
  1243. qdf_dot3_qosframe_t *qos_wh =
  1244. (qdf_dot3_qosframe_t *) nbuf->data;
  1245. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1246. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1247. return;
  1248. }
  1249. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1250. ether_type = eh->ether_type;
  1251. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1252. /*
  1253. * Check if packet is dot3 or eth2 type.
  1254. */
  1255. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1256. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1257. sizeof(*llcHdr));
  1258. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1259. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1260. sizeof(*llcHdr);
  1261. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1262. + sizeof(*llcHdr) +
  1263. sizeof(qdf_net_vlanhdr_t));
  1264. } else {
  1265. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1266. sizeof(*llcHdr);
  1267. }
  1268. } else {
  1269. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1270. evh = (qdf_ethervlan_header_t *) eh;
  1271. ether_type = evh->ether_type;
  1272. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1273. }
  1274. }
  1275. /*
  1276. * Find priority from IP TOS DSCP field
  1277. */
  1278. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1279. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1280. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1281. /* Only for unicast frames */
  1282. if (!is_mcast) {
  1283. /* send it on VO queue */
  1284. msdu_info->tid = DP_VO_TID;
  1285. }
  1286. } else {
  1287. /*
  1288. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1289. * from TOS byte.
  1290. */
  1291. tos = ip->ip_tos;
  1292. dscp_tid_override = 1;
  1293. }
  1294. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1295. /* TODO
  1296. * use flowlabel
  1297. *igmpmld cases to be handled in phase 2
  1298. */
  1299. unsigned long ver_pri_flowlabel;
  1300. unsigned long pri;
  1301. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1302. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1303. DP_IPV6_PRIORITY_SHIFT;
  1304. tos = pri;
  1305. dscp_tid_override = 1;
  1306. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1307. msdu_info->tid = DP_VO_TID;
  1308. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1309. /* Only for unicast frames */
  1310. if (!is_mcast) {
  1311. /* send ucast arp on VO queue */
  1312. msdu_info->tid = DP_VO_TID;
  1313. }
  1314. }
  1315. /*
  1316. * Assign all MCAST packets to BE
  1317. */
  1318. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1319. if (is_mcast) {
  1320. tos = 0;
  1321. dscp_tid_override = 1;
  1322. }
  1323. }
  1324. if (dscp_tid_override == 1) {
  1325. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1326. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1327. }
  1328. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1329. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1330. return;
  1331. }
  1332. /**
  1333. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1334. * @vdev: DP vdev handle
  1335. * @nbuf: skb
  1336. *
  1337. * Software based TID classification is required when more than 2 DSCP-TID
  1338. * mapping tables are needed.
  1339. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1340. *
  1341. * Return: void
  1342. */
  1343. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1344. struct dp_tx_msdu_info_s *msdu_info)
  1345. {
  1346. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1347. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1348. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1349. return;
  1350. /* for mesh packets don't do any classification */
  1351. if (qdf_unlikely(vdev->mesh_vdev))
  1352. return;
  1353. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1354. }
  1355. #ifdef FEATURE_WLAN_TDLS
  1356. /**
  1357. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1358. * @soc: datapath SOC
  1359. * @vdev: datapath vdev
  1360. * @tx_desc: TX descriptor
  1361. *
  1362. * Return: None
  1363. */
  1364. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1365. struct dp_vdev *vdev,
  1366. struct dp_tx_desc_s *tx_desc)
  1367. {
  1368. if (vdev) {
  1369. if (vdev->is_tdls_frame) {
  1370. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1371. vdev->is_tdls_frame = false;
  1372. }
  1373. }
  1374. }
  1375. /**
  1376. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1377. * @soc: dp_soc handle
  1378. * @tx_desc: TX descriptor
  1379. * @vdev: datapath vdev handle
  1380. *
  1381. * Return: None
  1382. */
  1383. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1384. struct dp_tx_desc_s *tx_desc)
  1385. {
  1386. struct hal_tx_completion_status ts = {0};
  1387. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1388. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1389. DP_MOD_ID_TDLS);
  1390. if (qdf_unlikely(!vdev)) {
  1391. dp_err_rl("vdev is null!");
  1392. goto error;
  1393. }
  1394. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1395. if (vdev->tx_non_std_data_callback.func) {
  1396. qdf_nbuf_set_next(nbuf, NULL);
  1397. vdev->tx_non_std_data_callback.func(
  1398. vdev->tx_non_std_data_callback.ctxt,
  1399. nbuf, ts.status);
  1400. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1401. return;
  1402. } else {
  1403. dp_err_rl("callback func is null");
  1404. }
  1405. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1406. error:
  1407. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1408. qdf_nbuf_free(nbuf);
  1409. }
  1410. /**
  1411. * dp_tx_msdu_single_map() - do nbuf map
  1412. * @vdev: DP vdev handle
  1413. * @tx_desc: DP TX descriptor pointer
  1414. * @nbuf: skb pointer
  1415. *
  1416. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1417. * operation done in other component.
  1418. *
  1419. * Return: QDF_STATUS
  1420. */
  1421. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1422. struct dp_tx_desc_s *tx_desc,
  1423. qdf_nbuf_t nbuf)
  1424. {
  1425. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1426. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1427. nbuf,
  1428. QDF_DMA_TO_DEVICE,
  1429. nbuf->len);
  1430. else
  1431. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1432. QDF_DMA_TO_DEVICE);
  1433. }
  1434. #else
  1435. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1436. struct dp_vdev *vdev,
  1437. struct dp_tx_desc_s *tx_desc)
  1438. {
  1439. }
  1440. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1441. struct dp_tx_desc_s *tx_desc)
  1442. {
  1443. }
  1444. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1445. struct dp_tx_desc_s *tx_desc,
  1446. qdf_nbuf_t nbuf)
  1447. {
  1448. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1449. nbuf,
  1450. QDF_DMA_TO_DEVICE,
  1451. nbuf->len);
  1452. }
  1453. #endif
  1454. #ifdef MESH_MODE_SUPPORT
  1455. /**
  1456. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1457. * @soc: datapath SOC
  1458. * @vdev: datapath vdev
  1459. * @tx_desc: TX descriptor
  1460. *
  1461. * Return: None
  1462. */
  1463. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1464. struct dp_vdev *vdev,
  1465. struct dp_tx_desc_s *tx_desc)
  1466. {
  1467. if (qdf_unlikely(vdev->mesh_vdev))
  1468. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1469. }
  1470. /**
  1471. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1472. * @soc: dp_soc handle
  1473. * @tx_desc: TX descriptor
  1474. * @vdev: datapath vdev handle
  1475. *
  1476. * Return: None
  1477. */
  1478. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1479. struct dp_tx_desc_s *tx_desc)
  1480. {
  1481. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1482. struct dp_vdev *vdev = NULL;
  1483. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1484. qdf_nbuf_free(nbuf);
  1485. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1486. } else {
  1487. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1488. DP_MOD_ID_MESH);
  1489. if (vdev && vdev->osif_tx_free_ext)
  1490. vdev->osif_tx_free_ext((nbuf));
  1491. else
  1492. qdf_nbuf_free(nbuf);
  1493. if (vdev)
  1494. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1495. }
  1496. }
  1497. #else
  1498. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1499. struct dp_vdev *vdev,
  1500. struct dp_tx_desc_s *tx_desc)
  1501. {
  1502. }
  1503. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1504. struct dp_tx_desc_s *tx_desc)
  1505. {
  1506. }
  1507. #endif
  1508. /**
  1509. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1510. * @vdev: DP vdev handle
  1511. * @nbuf: skb
  1512. *
  1513. * Return: 1 if frame needs to be dropped else 0
  1514. */
  1515. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1516. {
  1517. struct dp_pdev *pdev = NULL;
  1518. struct dp_ast_entry *src_ast_entry = NULL;
  1519. struct dp_ast_entry *dst_ast_entry = NULL;
  1520. struct dp_soc *soc = NULL;
  1521. qdf_assert(vdev);
  1522. pdev = vdev->pdev;
  1523. qdf_assert(pdev);
  1524. soc = pdev->soc;
  1525. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1526. (soc, dstmac, vdev->pdev->pdev_id);
  1527. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1528. (soc, srcmac, vdev->pdev->pdev_id);
  1529. if (dst_ast_entry && src_ast_entry) {
  1530. if (dst_ast_entry->peer_id ==
  1531. src_ast_entry->peer_id)
  1532. return 1;
  1533. }
  1534. return 0;
  1535. }
  1536. /**
  1537. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1538. * @vdev: DP vdev handle
  1539. * @nbuf: skb
  1540. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1541. * @meta_data: Metadata to the fw
  1542. * @tx_q: Tx queue to be used for this Tx frame
  1543. * @peer_id: peer_id of the peer in case of NAWDS frames
  1544. * @tx_exc_metadata: Handle that holds exception path metadata
  1545. *
  1546. * Return: NULL on success,
  1547. * nbuf when it fails to send
  1548. */
  1549. qdf_nbuf_t
  1550. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1551. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1552. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1553. {
  1554. struct dp_pdev *pdev = vdev->pdev;
  1555. struct dp_soc *soc = pdev->soc;
  1556. struct dp_tx_desc_s *tx_desc;
  1557. QDF_STATUS status;
  1558. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1559. uint16_t htt_tcl_metadata = 0;
  1560. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1561. uint8_t tid = msdu_info->tid;
  1562. struct cdp_tid_tx_stats *tid_stats = NULL;
  1563. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1564. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1565. msdu_info, tx_exc_metadata);
  1566. if (!tx_desc) {
  1567. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1568. vdev, tx_q->desc_pool_id);
  1569. drop_code = TX_DESC_ERR;
  1570. goto fail_return;
  1571. }
  1572. if (qdf_unlikely(soc->cce_disable)) {
  1573. if (dp_cce_classify(vdev, nbuf) == true) {
  1574. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1575. tid = DP_VO_TID;
  1576. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1577. }
  1578. }
  1579. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1580. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1581. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1582. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1583. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1584. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1585. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1586. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1587. peer_id);
  1588. } else
  1589. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1590. if (msdu_info->exception_fw)
  1591. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1592. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1593. !pdev->enhanced_stats_en);
  1594. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1595. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1596. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1597. /* Handle failure */
  1598. dp_err("qdf_nbuf_map failed");
  1599. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1600. drop_code = TX_DMA_MAP_ERR;
  1601. goto release_desc;
  1602. }
  1603. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1604. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1605. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1606. if (status != QDF_STATUS_SUCCESS) {
  1607. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1608. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1609. __func__, tx_desc, tx_q->ring_id);
  1610. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1611. QDF_DMA_TO_DEVICE,
  1612. nbuf->len);
  1613. drop_code = TX_HW_ENQUEUE;
  1614. goto release_desc;
  1615. }
  1616. return NULL;
  1617. release_desc:
  1618. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1619. fail_return:
  1620. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1621. tid_stats = &pdev->stats.tid_stats.
  1622. tid_tx_stats[tx_q->ring_id][tid];
  1623. tid_stats->swdrop_cnt[drop_code]++;
  1624. return nbuf;
  1625. }
  1626. /**
  1627. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1628. * @vdev: DP vdev handle
  1629. * @nbuf: skb
  1630. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1631. *
  1632. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1633. *
  1634. * Return: NULL on success,
  1635. * nbuf when it fails to send
  1636. */
  1637. #if QDF_LOCK_STATS
  1638. noinline
  1639. #else
  1640. #endif
  1641. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1642. struct dp_tx_msdu_info_s *msdu_info)
  1643. {
  1644. uint32_t i;
  1645. struct dp_pdev *pdev = vdev->pdev;
  1646. struct dp_soc *soc = pdev->soc;
  1647. struct dp_tx_desc_s *tx_desc;
  1648. bool is_cce_classified = false;
  1649. QDF_STATUS status;
  1650. uint16_t htt_tcl_metadata = 0;
  1651. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1652. struct cdp_tid_tx_stats *tid_stats = NULL;
  1653. if (qdf_unlikely(soc->cce_disable)) {
  1654. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1655. if (is_cce_classified) {
  1656. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1657. msdu_info->tid = DP_VO_TID;
  1658. }
  1659. }
  1660. if (msdu_info->frm_type == dp_tx_frm_me)
  1661. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1662. i = 0;
  1663. /* Print statement to track i and num_seg */
  1664. /*
  1665. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1666. * descriptors using information in msdu_info
  1667. */
  1668. while (i < msdu_info->num_seg) {
  1669. /*
  1670. * Setup Tx descriptor for an MSDU, and MSDU extension
  1671. * descriptor
  1672. */
  1673. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1674. tx_q->desc_pool_id);
  1675. if (!tx_desc) {
  1676. if (msdu_info->frm_type == dp_tx_frm_me) {
  1677. dp_tx_me_free_buf(pdev,
  1678. (void *)(msdu_info->u.sg_info
  1679. .curr_seg->frags[0].vaddr));
  1680. i++;
  1681. continue;
  1682. }
  1683. goto done;
  1684. }
  1685. if (msdu_info->frm_type == dp_tx_frm_me) {
  1686. tx_desc->me_buffer =
  1687. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1688. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1689. }
  1690. if (is_cce_classified)
  1691. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1692. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1693. if (msdu_info->exception_fw) {
  1694. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1695. }
  1696. /*
  1697. * Enqueue the Tx MSDU descriptor to HW for transmit
  1698. */
  1699. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1700. htt_tcl_metadata, tx_q->ring_id, NULL);
  1701. if (status != QDF_STATUS_SUCCESS) {
  1702. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1703. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1704. __func__, tx_desc, tx_q->ring_id);
  1705. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1706. tid_stats = &pdev->stats.tid_stats.
  1707. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1708. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1709. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1710. if (msdu_info->frm_type == dp_tx_frm_me) {
  1711. i++;
  1712. continue;
  1713. }
  1714. goto done;
  1715. }
  1716. /*
  1717. * TODO
  1718. * if tso_info structure can be modified to have curr_seg
  1719. * as first element, following 2 blocks of code (for TSO and SG)
  1720. * can be combined into 1
  1721. */
  1722. /*
  1723. * For frames with multiple segments (TSO, ME), jump to next
  1724. * segment.
  1725. */
  1726. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1727. if (msdu_info->u.tso_info.curr_seg->next) {
  1728. msdu_info->u.tso_info.curr_seg =
  1729. msdu_info->u.tso_info.curr_seg->next;
  1730. /*
  1731. * If this is a jumbo nbuf, then increment the number of
  1732. * nbuf users for each additional segment of the msdu.
  1733. * This will ensure that the skb is freed only after
  1734. * receiving tx completion for all segments of an nbuf
  1735. */
  1736. qdf_nbuf_inc_users(nbuf);
  1737. /* Check with MCL if this is needed */
  1738. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1739. }
  1740. }
  1741. /*
  1742. * For Multicast-Unicast converted packets,
  1743. * each converted frame (for a client) is represented as
  1744. * 1 segment
  1745. */
  1746. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1747. (msdu_info->frm_type == dp_tx_frm_me)) {
  1748. if (msdu_info->u.sg_info.curr_seg->next) {
  1749. msdu_info->u.sg_info.curr_seg =
  1750. msdu_info->u.sg_info.curr_seg->next;
  1751. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1752. }
  1753. }
  1754. i++;
  1755. }
  1756. nbuf = NULL;
  1757. done:
  1758. return nbuf;
  1759. }
  1760. /**
  1761. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1762. * for SG frames
  1763. * @vdev: DP vdev handle
  1764. * @nbuf: skb
  1765. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1766. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1767. *
  1768. * Return: NULL on success,
  1769. * nbuf when it fails to send
  1770. */
  1771. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1772. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1773. {
  1774. uint32_t cur_frag, nr_frags;
  1775. qdf_dma_addr_t paddr;
  1776. struct dp_tx_sg_info_s *sg_info;
  1777. sg_info = &msdu_info->u.sg_info;
  1778. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1779. if (QDF_STATUS_SUCCESS !=
  1780. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  1781. QDF_DMA_TO_DEVICE, nbuf->len)) {
  1782. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1783. "dma map error");
  1784. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1785. qdf_nbuf_free(nbuf);
  1786. return NULL;
  1787. }
  1788. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  1789. seg_info->frags[0].paddr_lo = paddr;
  1790. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1791. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1792. seg_info->frags[0].vaddr = (void *) nbuf;
  1793. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1794. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1795. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1796. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1797. "frag dma map error");
  1798. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1799. qdf_nbuf_free(nbuf);
  1800. return NULL;
  1801. }
  1802. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  1803. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1804. seg_info->frags[cur_frag + 1].paddr_hi =
  1805. ((uint64_t) paddr) >> 32;
  1806. seg_info->frags[cur_frag + 1].len =
  1807. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1808. }
  1809. seg_info->frag_cnt = (cur_frag + 1);
  1810. seg_info->total_len = qdf_nbuf_len(nbuf);
  1811. seg_info->next = NULL;
  1812. sg_info->curr_seg = seg_info;
  1813. msdu_info->frm_type = dp_tx_frm_sg;
  1814. msdu_info->num_seg = 1;
  1815. return nbuf;
  1816. }
  1817. /**
  1818. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1819. * @vdev: DP vdev handle
  1820. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1821. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1822. *
  1823. * Return: NULL on failure,
  1824. * nbuf when extracted successfully
  1825. */
  1826. static
  1827. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1828. struct dp_tx_msdu_info_s *msdu_info,
  1829. uint16_t ppdu_cookie)
  1830. {
  1831. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1832. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1833. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1834. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1835. (msdu_info->meta_data[5], 1);
  1836. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1837. (msdu_info->meta_data[5], 1);
  1838. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1839. (msdu_info->meta_data[6], ppdu_cookie);
  1840. msdu_info->exception_fw = 1;
  1841. msdu_info->is_tx_sniffer = 1;
  1842. }
  1843. #ifdef MESH_MODE_SUPPORT
  1844. /**
  1845. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1846. and prepare msdu_info for mesh frames.
  1847. * @vdev: DP vdev handle
  1848. * @nbuf: skb
  1849. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1850. *
  1851. * Return: NULL on failure,
  1852. * nbuf when extracted successfully
  1853. */
  1854. static
  1855. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1856. struct dp_tx_msdu_info_s *msdu_info)
  1857. {
  1858. struct meta_hdr_s *mhdr;
  1859. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1860. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1861. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1862. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1863. msdu_info->exception_fw = 0;
  1864. goto remove_meta_hdr;
  1865. }
  1866. msdu_info->exception_fw = 1;
  1867. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1868. meta_data->host_tx_desc_pool = 1;
  1869. meta_data->update_peer_cache = 1;
  1870. meta_data->learning_frame = 1;
  1871. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1872. meta_data->power = mhdr->power;
  1873. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1874. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1875. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1876. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1877. meta_data->dyn_bw = 1;
  1878. meta_data->valid_pwr = 1;
  1879. meta_data->valid_mcs_mask = 1;
  1880. meta_data->valid_nss_mask = 1;
  1881. meta_data->valid_preamble_type = 1;
  1882. meta_data->valid_retries = 1;
  1883. meta_data->valid_bw_info = 1;
  1884. }
  1885. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1886. meta_data->encrypt_type = 0;
  1887. meta_data->valid_encrypt_type = 1;
  1888. meta_data->learning_frame = 0;
  1889. }
  1890. meta_data->valid_key_flags = 1;
  1891. meta_data->key_flags = (mhdr->keyix & 0x3);
  1892. remove_meta_hdr:
  1893. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1894. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1895. "qdf_nbuf_pull_head failed");
  1896. qdf_nbuf_free(nbuf);
  1897. return NULL;
  1898. }
  1899. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1900. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1901. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1902. " tid %d to_fw %d",
  1903. __func__, msdu_info->meta_data[0],
  1904. msdu_info->meta_data[1],
  1905. msdu_info->meta_data[2],
  1906. msdu_info->meta_data[3],
  1907. msdu_info->meta_data[4],
  1908. msdu_info->meta_data[5],
  1909. msdu_info->tid, msdu_info->exception_fw);
  1910. return nbuf;
  1911. }
  1912. #else
  1913. static
  1914. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1915. struct dp_tx_msdu_info_s *msdu_info)
  1916. {
  1917. return nbuf;
  1918. }
  1919. #endif
  1920. /**
  1921. * dp_check_exc_metadata() - Checks if parameters are valid
  1922. * @tx_exc - holds all exception path parameters
  1923. *
  1924. * Returns true when all the parameters are valid else false
  1925. *
  1926. */
  1927. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1928. {
  1929. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1930. HTT_INVALID_TID);
  1931. bool invalid_encap_type =
  1932. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  1933. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  1934. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1935. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1936. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1937. tx_exc->ppdu_cookie == 0);
  1938. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1939. invalid_cookie) {
  1940. return false;
  1941. }
  1942. return true;
  1943. }
  1944. /**
  1945. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1946. * @soc: DP soc handle
  1947. * @vdev_id: id of DP vdev handle
  1948. * @nbuf: skb
  1949. * @tx_exc_metadata: Handle that holds exception path meta data
  1950. *
  1951. * Entry point for Core Tx layer (DP_TX) invoked from
  1952. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1953. *
  1954. * Return: NULL on success,
  1955. * nbuf when it fails to send
  1956. */
  1957. qdf_nbuf_t
  1958. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1959. qdf_nbuf_t nbuf,
  1960. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1961. {
  1962. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1963. qdf_ether_header_t *eh = NULL;
  1964. struct dp_tx_msdu_info_s msdu_info;
  1965. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  1966. DP_MOD_ID_TX_EXCEPTION);
  1967. if (qdf_unlikely(!vdev))
  1968. goto fail;
  1969. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1970. if (!tx_exc_metadata)
  1971. goto fail;
  1972. msdu_info.tid = tx_exc_metadata->tid;
  1973. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1974. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  1975. QDF_MAC_ADDR_REF(nbuf->data));
  1976. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1977. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1978. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1979. "Invalid parameters in exception path");
  1980. goto fail;
  1981. }
  1982. /* Basic sanity checks for unsupported packets */
  1983. /* MESH mode */
  1984. if (qdf_unlikely(vdev->mesh_vdev)) {
  1985. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1986. "Mesh mode is not supported in exception path");
  1987. goto fail;
  1988. }
  1989. /* TSO or SG */
  1990. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1991. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1992. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1993. "TSO and SG are not supported in exception path");
  1994. goto fail;
  1995. }
  1996. /* RAW */
  1997. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1998. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1999. "Raw frame is not supported in exception path");
  2000. goto fail;
  2001. }
  2002. /* Mcast enhancement*/
  2003. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  2004. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2005. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2006. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2007. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  2008. }
  2009. }
  2010. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2011. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2012. qdf_nbuf_len(nbuf));
  2013. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2014. tx_exc_metadata->ppdu_cookie);
  2015. }
  2016. /*
  2017. * Get HW Queue to use for this frame.
  2018. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2019. * dedicated for data and 1 for command.
  2020. * "queue_id" maps to one hardware ring.
  2021. * With each ring, we also associate a unique Tx descriptor pool
  2022. * to minimize lock contention for these resources.
  2023. */
  2024. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2025. /*
  2026. * Check exception descriptors
  2027. */
  2028. if (dp_tx_exception_limit_check(vdev))
  2029. goto fail;
  2030. /* Single linear frame */
  2031. /*
  2032. * If nbuf is a simple linear frame, use send_single function to
  2033. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2034. * SRNG. There is no need to setup a MSDU extension descriptor.
  2035. */
  2036. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2037. tx_exc_metadata->peer_id, tx_exc_metadata);
  2038. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2039. return nbuf;
  2040. fail:
  2041. if (vdev)
  2042. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2043. dp_verbose_debug("pkt send failed");
  2044. return nbuf;
  2045. }
  2046. /**
  2047. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2048. * @soc: DP soc handle
  2049. * @vdev_id: DP vdev handle
  2050. * @nbuf: skb
  2051. *
  2052. * Entry point for Core Tx layer (DP_TX) invoked from
  2053. * hard_start_xmit in OSIF/HDD
  2054. *
  2055. * Return: NULL on success,
  2056. * nbuf when it fails to send
  2057. */
  2058. #ifdef MESH_MODE_SUPPORT
  2059. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2060. qdf_nbuf_t nbuf)
  2061. {
  2062. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2063. struct meta_hdr_s *mhdr;
  2064. qdf_nbuf_t nbuf_mesh = NULL;
  2065. qdf_nbuf_t nbuf_clone = NULL;
  2066. struct dp_vdev *vdev;
  2067. uint8_t no_enc_frame = 0;
  2068. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2069. if (!nbuf_mesh) {
  2070. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2071. "qdf_nbuf_unshare failed");
  2072. return nbuf;
  2073. }
  2074. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2075. if (!vdev) {
  2076. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2077. "vdev is NULL for vdev_id %d", vdev_id);
  2078. return nbuf;
  2079. }
  2080. nbuf = nbuf_mesh;
  2081. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2082. if ((vdev->sec_type != cdp_sec_type_none) &&
  2083. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2084. no_enc_frame = 1;
  2085. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2086. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2087. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2088. !no_enc_frame) {
  2089. nbuf_clone = qdf_nbuf_clone(nbuf);
  2090. if (!nbuf_clone) {
  2091. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2092. "qdf_nbuf_clone failed");
  2093. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2094. return nbuf;
  2095. }
  2096. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2097. }
  2098. if (nbuf_clone) {
  2099. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2100. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2101. } else {
  2102. qdf_nbuf_free(nbuf_clone);
  2103. }
  2104. }
  2105. if (no_enc_frame)
  2106. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2107. else
  2108. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2109. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2110. if ((!nbuf) && no_enc_frame) {
  2111. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2112. }
  2113. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2114. return nbuf;
  2115. }
  2116. #else
  2117. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2118. qdf_nbuf_t nbuf)
  2119. {
  2120. return dp_tx_send(soc, vdev_id, nbuf);
  2121. }
  2122. #endif
  2123. /**
  2124. * dp_tx_nawds_handler() - NAWDS handler
  2125. *
  2126. * @soc: DP soc handle
  2127. * @vdev_id: id of DP vdev handle
  2128. * @msdu_info: msdu_info required to create HTT metadata
  2129. * @nbuf: skb
  2130. *
  2131. * This API transfers the multicast frames with the peer id
  2132. * on NAWDS enabled peer.
  2133. * Return: none
  2134. */
  2135. static inline
  2136. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2137. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2138. {
  2139. struct dp_peer *peer = NULL;
  2140. qdf_nbuf_t nbuf_clone = NULL;
  2141. uint16_t peer_id = DP_INVALID_PEER;
  2142. uint16_t sa_peer_id = DP_INVALID_PEER;
  2143. struct dp_ast_entry *ast_entry = NULL;
  2144. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2145. if (qdf_nbuf_get_tx_ftype(nbuf) == CB_FTYPE_INTRABSS_FWD) {
  2146. qdf_spin_lock_bh(&soc->ast_lock);
  2147. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2148. (soc,
  2149. (uint8_t *)(eh->ether_shost),
  2150. vdev->pdev->pdev_id);
  2151. if (ast_entry)
  2152. sa_peer_id = ast_entry->peer_id;
  2153. qdf_spin_unlock_bh(&soc->ast_lock);
  2154. }
  2155. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2156. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2157. if (!peer->bss_peer && peer->nawds_enabled) {
  2158. peer_id = peer->peer_id;
  2159. /* Multicast packets needs to be
  2160. * dropped in case of intra bss forwarding
  2161. */
  2162. if (sa_peer_id == peer->peer_id) {
  2163. QDF_TRACE(QDF_MODULE_ID_DP,
  2164. QDF_TRACE_LEVEL_DEBUG,
  2165. " %s: multicast packet", __func__);
  2166. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  2167. continue;
  2168. }
  2169. nbuf_clone = qdf_nbuf_clone(nbuf);
  2170. if (!nbuf_clone) {
  2171. QDF_TRACE(QDF_MODULE_ID_DP,
  2172. QDF_TRACE_LEVEL_ERROR,
  2173. FL("nbuf clone failed"));
  2174. break;
  2175. }
  2176. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2177. msdu_info, peer_id,
  2178. NULL);
  2179. if (nbuf_clone) {
  2180. QDF_TRACE(QDF_MODULE_ID_DP,
  2181. QDF_TRACE_LEVEL_DEBUG,
  2182. FL("pkt send failed"));
  2183. qdf_nbuf_free(nbuf_clone);
  2184. } else {
  2185. if (peer_id != DP_INVALID_PEER)
  2186. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2187. 1, qdf_nbuf_len(nbuf));
  2188. }
  2189. }
  2190. }
  2191. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2192. }
  2193. /**
  2194. * dp_tx_send() - Transmit a frame on a given VAP
  2195. * @soc: DP soc handle
  2196. * @vdev_id: id of DP vdev handle
  2197. * @nbuf: skb
  2198. *
  2199. * Entry point for Core Tx layer (DP_TX) invoked from
  2200. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2201. * cases
  2202. *
  2203. * Return: NULL on success,
  2204. * nbuf when it fails to send
  2205. */
  2206. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2207. qdf_nbuf_t nbuf)
  2208. {
  2209. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2210. uint16_t peer_id = HTT_INVALID_PEER;
  2211. /*
  2212. * doing a memzero is causing additional function call overhead
  2213. * so doing static stack clearing
  2214. */
  2215. struct dp_tx_msdu_info_s msdu_info = {0};
  2216. struct dp_vdev *vdev = NULL;
  2217. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2218. return nbuf;
  2219. /*
  2220. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2221. * this in per packet path.
  2222. *
  2223. * As in this path vdev memory is already protected with netdev
  2224. * tx lock
  2225. */
  2226. vdev = soc->vdev_id_map[vdev_id];
  2227. if (qdf_unlikely(!vdev))
  2228. return nbuf;
  2229. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2230. QDF_MAC_ADDR_REF(nbuf->data));
  2231. /*
  2232. * Set Default Host TID value to invalid TID
  2233. * (TID override disabled)
  2234. */
  2235. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2236. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2237. if (qdf_unlikely(vdev->mesh_vdev)) {
  2238. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2239. &msdu_info);
  2240. if (!nbuf_mesh) {
  2241. dp_verbose_debug("Extracting mesh metadata failed");
  2242. return nbuf;
  2243. }
  2244. nbuf = nbuf_mesh;
  2245. }
  2246. /*
  2247. * Get HW Queue to use for this frame.
  2248. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2249. * dedicated for data and 1 for command.
  2250. * "queue_id" maps to one hardware ring.
  2251. * With each ring, we also associate a unique Tx descriptor pool
  2252. * to minimize lock contention for these resources.
  2253. */
  2254. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2255. /*
  2256. * TCL H/W supports 2 DSCP-TID mapping tables.
  2257. * Table 1 - Default DSCP-TID mapping table
  2258. * Table 2 - 1 DSCP-TID override table
  2259. *
  2260. * If we need a different DSCP-TID mapping for this vap,
  2261. * call tid_classify to extract DSCP/ToS from frame and
  2262. * map to a TID and store in msdu_info. This is later used
  2263. * to fill in TCL Input descriptor (per-packet TID override).
  2264. */
  2265. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2266. /*
  2267. * Classify the frame and call corresponding
  2268. * "prepare" function which extracts the segment (TSO)
  2269. * and fragmentation information (for TSO , SG, ME, or Raw)
  2270. * into MSDU_INFO structure which is later used to fill
  2271. * SW and HW descriptors.
  2272. */
  2273. if (qdf_nbuf_is_tso(nbuf)) {
  2274. dp_verbose_debug("TSO frame %pK", vdev);
  2275. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2276. qdf_nbuf_len(nbuf));
  2277. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2278. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2279. qdf_nbuf_len(nbuf));
  2280. return nbuf;
  2281. }
  2282. goto send_multiple;
  2283. }
  2284. /* SG */
  2285. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2286. struct dp_tx_seg_info_s seg_info = {0};
  2287. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2288. if (!nbuf)
  2289. return NULL;
  2290. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2291. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2292. qdf_nbuf_len(nbuf));
  2293. goto send_multiple;
  2294. }
  2295. #ifdef ATH_SUPPORT_IQUE
  2296. /* Mcast to Ucast Conversion*/
  2297. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  2298. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2299. qdf_nbuf_data(nbuf);
  2300. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2301. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2302. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2303. DP_STATS_INC_PKT(vdev,
  2304. tx_i.mcast_en.mcast_pkt, 1,
  2305. qdf_nbuf_len(nbuf));
  2306. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2307. QDF_STATUS_SUCCESS) {
  2308. return NULL;
  2309. }
  2310. }
  2311. }
  2312. #endif
  2313. /* RAW */
  2314. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2315. struct dp_tx_seg_info_s seg_info = {0};
  2316. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2317. if (!nbuf)
  2318. return NULL;
  2319. dp_verbose_debug("Raw frame %pK", vdev);
  2320. goto send_multiple;
  2321. }
  2322. if (qdf_unlikely(vdev->nawds_enabled)) {
  2323. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2324. qdf_nbuf_data(nbuf);
  2325. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2326. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2327. peer_id = DP_INVALID_PEER;
  2328. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2329. 1, qdf_nbuf_len(nbuf));
  2330. }
  2331. /* Single linear frame */
  2332. /*
  2333. * If nbuf is a simple linear frame, use send_single function to
  2334. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2335. * SRNG. There is no need to setup a MSDU extension descriptor.
  2336. */
  2337. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2338. return nbuf;
  2339. send_multiple:
  2340. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2341. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2342. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2343. return nbuf;
  2344. }
  2345. /**
  2346. * dp_tx_reinject_handler() - Tx Reinject Handler
  2347. * @soc: datapath soc handle
  2348. * @vdev: datapath vdev handle
  2349. * @tx_desc: software descriptor head pointer
  2350. * @status : Tx completion status from HTT descriptor
  2351. *
  2352. * This function reinjects frames back to Target.
  2353. * Todo - Host queue needs to be added
  2354. *
  2355. * Return: none
  2356. */
  2357. static
  2358. void dp_tx_reinject_handler(struct dp_soc *soc,
  2359. struct dp_vdev *vdev,
  2360. struct dp_tx_desc_s *tx_desc,
  2361. uint8_t *status)
  2362. {
  2363. struct dp_peer *peer = NULL;
  2364. uint32_t peer_id = HTT_INVALID_PEER;
  2365. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2366. qdf_nbuf_t nbuf_copy = NULL;
  2367. struct dp_tx_msdu_info_s msdu_info;
  2368. #ifdef WDS_VENDOR_EXTENSION
  2369. int is_mcast = 0, is_ucast = 0;
  2370. int num_peers_3addr = 0;
  2371. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2372. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2373. #endif
  2374. qdf_assert(vdev);
  2375. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2376. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2377. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2378. "%s Tx reinject path", __func__);
  2379. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2380. qdf_nbuf_len(tx_desc->nbuf));
  2381. #ifdef WDS_VENDOR_EXTENSION
  2382. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2383. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2384. } else {
  2385. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2386. }
  2387. is_ucast = !is_mcast;
  2388. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2389. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2390. if (peer->bss_peer)
  2391. continue;
  2392. /* Detect wds peers that use 3-addr framing for mcast.
  2393. * if there are any, the bss_peer is used to send the
  2394. * the mcast frame using 3-addr format. all wds enabled
  2395. * peers that use 4-addr framing for mcast frames will
  2396. * be duplicated and sent as 4-addr frames below.
  2397. */
  2398. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2399. num_peers_3addr = 1;
  2400. break;
  2401. }
  2402. }
  2403. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2404. #endif
  2405. if (qdf_unlikely(vdev->mesh_vdev)) {
  2406. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2407. } else {
  2408. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2409. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2410. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2411. #ifdef WDS_VENDOR_EXTENSION
  2412. /*
  2413. * . if 3-addr STA, then send on BSS Peer
  2414. * . if Peer WDS enabled and accept 4-addr mcast,
  2415. * send mcast on that peer only
  2416. * . if Peer WDS enabled and accept 4-addr ucast,
  2417. * send ucast on that peer only
  2418. */
  2419. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2420. (peer->wds_enabled &&
  2421. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2422. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2423. #else
  2424. ((peer->bss_peer &&
  2425. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))))) {
  2426. #endif
  2427. peer_id = DP_INVALID_PEER;
  2428. nbuf_copy = qdf_nbuf_copy(nbuf);
  2429. if (!nbuf_copy) {
  2430. QDF_TRACE(QDF_MODULE_ID_DP,
  2431. QDF_TRACE_LEVEL_DEBUG,
  2432. FL("nbuf copy failed"));
  2433. break;
  2434. }
  2435. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2436. nbuf_copy,
  2437. &msdu_info,
  2438. peer_id,
  2439. NULL);
  2440. if (nbuf_copy) {
  2441. QDF_TRACE(QDF_MODULE_ID_DP,
  2442. QDF_TRACE_LEVEL_DEBUG,
  2443. FL("pkt send failed"));
  2444. qdf_nbuf_free(nbuf_copy);
  2445. }
  2446. }
  2447. }
  2448. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2449. }
  2450. qdf_nbuf_free(nbuf);
  2451. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2452. }
  2453. /**
  2454. * dp_tx_inspect_handler() - Tx Inspect Handler
  2455. * @soc: datapath soc handle
  2456. * @vdev: datapath vdev handle
  2457. * @tx_desc: software descriptor head pointer
  2458. * @status : Tx completion status from HTT descriptor
  2459. *
  2460. * Handles Tx frames sent back to Host for inspection
  2461. * (ProxyARP)
  2462. *
  2463. * Return: none
  2464. */
  2465. static void dp_tx_inspect_handler(struct dp_soc *soc,
  2466. struct dp_vdev *vdev,
  2467. struct dp_tx_desc_s *tx_desc,
  2468. uint8_t *status)
  2469. {
  2470. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2471. "%s Tx inspect path",
  2472. __func__);
  2473. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  2474. qdf_nbuf_len(tx_desc->nbuf));
  2475. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2476. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2477. }
  2478. #ifdef FEATURE_PERPKT_INFO
  2479. /**
  2480. * dp_get_completion_indication_for_stack() - send completion to stack
  2481. * @soc : dp_soc handle
  2482. * @pdev: dp_pdev handle
  2483. * @peer: dp peer handle
  2484. * @ts: transmit completion status structure
  2485. * @netbuf: Buffer pointer for free
  2486. *
  2487. * This function is used for indication whether buffer needs to be
  2488. * sent to stack for freeing or not
  2489. */
  2490. QDF_STATUS
  2491. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2492. struct dp_pdev *pdev,
  2493. struct dp_peer *peer,
  2494. struct hal_tx_completion_status *ts,
  2495. qdf_nbuf_t netbuf,
  2496. uint64_t time_latency)
  2497. {
  2498. struct tx_capture_hdr *ppdu_hdr;
  2499. uint16_t peer_id = ts->peer_id;
  2500. uint32_t ppdu_id = ts->ppdu_id;
  2501. uint8_t first_msdu = ts->first_msdu;
  2502. uint8_t last_msdu = ts->last_msdu;
  2503. uint32_t txcap_hdr_size = sizeof(struct tx_capture_hdr);
  2504. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2505. !pdev->latency_capture_enable))
  2506. return QDF_STATUS_E_NOSUPPORT;
  2507. if (!peer) {
  2508. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2509. FL("Peer Invalid"));
  2510. return QDF_STATUS_E_INVAL;
  2511. }
  2512. if (pdev->mcopy_mode) {
  2513. /* If mcopy is enabled and mcopy_mode is M_COPY deliver 1st MSDU
  2514. * per PPDU. If mcopy_mode is M_COPY_EXTENDED deliver 1st MSDU
  2515. * for each MPDU
  2516. */
  2517. if (pdev->mcopy_mode == M_COPY) {
  2518. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2519. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2520. return QDF_STATUS_E_INVAL;
  2521. }
  2522. }
  2523. if (!first_msdu)
  2524. return QDF_STATUS_E_INVAL;
  2525. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2526. pdev->m_copy_id.tx_peer_id = peer_id;
  2527. }
  2528. if (qdf_unlikely(qdf_nbuf_headroom(netbuf) < txcap_hdr_size)) {
  2529. netbuf = qdf_nbuf_realloc_headroom(netbuf, txcap_hdr_size);
  2530. if (!netbuf) {
  2531. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2532. FL("No headroom"));
  2533. return QDF_STATUS_E_NOMEM;
  2534. }
  2535. }
  2536. if (!qdf_nbuf_push_head(netbuf, txcap_hdr_size)) {
  2537. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2538. FL("No headroom"));
  2539. return QDF_STATUS_E_NOMEM;
  2540. }
  2541. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2542. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2543. QDF_MAC_ADDR_SIZE);
  2544. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2545. QDF_MAC_ADDR_SIZE);
  2546. ppdu_hdr->ppdu_id = ppdu_id;
  2547. ppdu_hdr->peer_id = peer_id;
  2548. ppdu_hdr->first_msdu = first_msdu;
  2549. ppdu_hdr->last_msdu = last_msdu;
  2550. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2551. ppdu_hdr->tsf = ts->tsf;
  2552. ppdu_hdr->time_latency = time_latency;
  2553. }
  2554. return QDF_STATUS_SUCCESS;
  2555. }
  2556. /**
  2557. * dp_send_completion_to_stack() - send completion to stack
  2558. * @soc : dp_soc handle
  2559. * @pdev: dp_pdev handle
  2560. * @peer_id: peer_id of the peer for which completion came
  2561. * @ppdu_id: ppdu_id
  2562. * @netbuf: Buffer pointer for free
  2563. *
  2564. * This function is used to send completion to stack
  2565. * to free buffer
  2566. */
  2567. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2568. uint16_t peer_id, uint32_t ppdu_id,
  2569. qdf_nbuf_t netbuf)
  2570. {
  2571. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2572. netbuf, peer_id,
  2573. WDI_NO_VAL, pdev->pdev_id);
  2574. }
  2575. #else
  2576. static QDF_STATUS
  2577. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2578. struct dp_pdev *pdev,
  2579. struct dp_peer *peer,
  2580. struct hal_tx_completion_status *ts,
  2581. qdf_nbuf_t netbuf,
  2582. uint64_t time_latency)
  2583. {
  2584. return QDF_STATUS_E_NOSUPPORT;
  2585. }
  2586. static void
  2587. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2588. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2589. {
  2590. }
  2591. #endif
  2592. /**
  2593. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2594. * @soc: Soc handle
  2595. * @desc: software Tx descriptor to be processed
  2596. *
  2597. * Return: none
  2598. */
  2599. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2600. struct dp_tx_desc_s *desc)
  2601. {
  2602. qdf_nbuf_t nbuf = desc->nbuf;
  2603. /* nbuf already freed in vdev detach path */
  2604. if (!nbuf)
  2605. return;
  2606. /* If it is TDLS mgmt, don't unmap or free the frame */
  2607. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2608. return dp_non_std_tx_comp_free_buff(soc, desc);
  2609. /* 0 : MSDU buffer, 1 : MLE */
  2610. if (desc->msdu_ext_desc) {
  2611. /* TSO free */
  2612. if (hal_tx_ext_desc_get_tso_enable(
  2613. desc->msdu_ext_desc->vaddr)) {
  2614. /* unmap eash TSO seg before free the nbuf */
  2615. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2616. desc->tso_num_desc);
  2617. qdf_nbuf_free(nbuf);
  2618. return;
  2619. }
  2620. }
  2621. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2622. QDF_DMA_TO_DEVICE, nbuf->len);
  2623. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2624. return dp_mesh_tx_comp_free_buff(soc, desc);
  2625. qdf_nbuf_free(nbuf);
  2626. }
  2627. #ifdef MESH_MODE_SUPPORT
  2628. /**
  2629. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2630. * in mesh meta header
  2631. * @tx_desc: software descriptor head pointer
  2632. * @ts: pointer to tx completion stats
  2633. * Return: none
  2634. */
  2635. static
  2636. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2637. struct hal_tx_completion_status *ts)
  2638. {
  2639. struct meta_hdr_s *mhdr;
  2640. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2641. if (!tx_desc->msdu_ext_desc) {
  2642. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2643. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2644. "netbuf %pK offset %d",
  2645. netbuf, tx_desc->pkt_offset);
  2646. return;
  2647. }
  2648. }
  2649. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2650. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2651. "netbuf %pK offset %lu", netbuf,
  2652. sizeof(struct meta_hdr_s));
  2653. return;
  2654. }
  2655. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2656. mhdr->rssi = ts->ack_frame_rssi;
  2657. mhdr->band = tx_desc->pdev->operating_channel.band;
  2658. mhdr->channel = tx_desc->pdev->operating_channel.num;
  2659. }
  2660. #else
  2661. static
  2662. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2663. struct hal_tx_completion_status *ts)
  2664. {
  2665. }
  2666. #endif
  2667. #ifdef QCA_PEER_EXT_STATS
  2668. /*
  2669. * dp_tx_compute_tid_delay() - Compute per TID delay
  2670. * @stats: Per TID delay stats
  2671. * @tx_desc: Software Tx descriptor
  2672. *
  2673. * Compute the software enqueue and hw enqueue delays and
  2674. * update the respective histograms
  2675. *
  2676. * Return: void
  2677. */
  2678. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  2679. struct dp_tx_desc_s *tx_desc)
  2680. {
  2681. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  2682. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2683. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  2684. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  2685. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2686. timestamp_hw_enqueue = tx_desc->timestamp;
  2687. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2688. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2689. timestamp_hw_enqueue);
  2690. /*
  2691. * Update the Tx software enqueue delay and HW enque-Completion delay.
  2692. */
  2693. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  2694. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  2695. }
  2696. /*
  2697. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  2698. * @peer: DP peer context
  2699. * @tx_desc: Tx software descriptor
  2700. * @tid: Transmission ID
  2701. * @ring_id: Rx CPU context ID/CPU_ID
  2702. *
  2703. * Update the peer extended stats. These are enhanced other
  2704. * delay stats per msdu level.
  2705. *
  2706. * Return: void
  2707. */
  2708. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  2709. struct dp_tx_desc_s *tx_desc,
  2710. uint8_t tid, uint8_t ring_id)
  2711. {
  2712. struct dp_pdev *pdev = peer->vdev->pdev;
  2713. struct dp_soc *soc = NULL;
  2714. struct cdp_peer_ext_stats *pext_stats = NULL;
  2715. soc = pdev->soc;
  2716. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  2717. return;
  2718. pext_stats = peer->pext_stats;
  2719. qdf_assert(pext_stats);
  2720. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  2721. /*
  2722. * For non-TID packets use the TID 9
  2723. */
  2724. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2725. tid = CDP_MAX_DATA_TIDS - 1;
  2726. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  2727. tx_desc);
  2728. }
  2729. #else
  2730. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  2731. struct dp_tx_desc_s *tx_desc,
  2732. uint8_t tid, uint8_t ring_id)
  2733. {
  2734. }
  2735. #endif
  2736. /**
  2737. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2738. * to pass in correct fields
  2739. *
  2740. * @vdev: pdev handle
  2741. * @tx_desc: tx descriptor
  2742. * @tid: tid value
  2743. * @ring_id: TCL or WBM ring number for transmit path
  2744. * Return: none
  2745. */
  2746. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2747. struct dp_tx_desc_s *tx_desc,
  2748. uint8_t tid, uint8_t ring_id)
  2749. {
  2750. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2751. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2752. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2753. return;
  2754. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  2755. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2756. timestamp_hw_enqueue = tx_desc->timestamp;
  2757. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2758. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2759. timestamp_hw_enqueue);
  2760. interframe_delay = (uint32_t)(timestamp_ingress -
  2761. vdev->prev_tx_enq_tstamp);
  2762. /*
  2763. * Delay in software enqueue
  2764. */
  2765. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2766. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2767. /*
  2768. * Delay between packet enqueued to HW and Tx completion
  2769. */
  2770. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2771. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2772. /*
  2773. * Update interframe delay stats calculated at hardstart receive point.
  2774. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2775. * interframe delay will not be calculate correctly for 1st frame.
  2776. * On the other side, this will help in avoiding extra per packet check
  2777. * of !vdev->prev_tx_enq_tstamp.
  2778. */
  2779. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2780. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2781. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2782. }
  2783. #ifdef DISABLE_DP_STATS
  2784. static
  2785. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  2786. {
  2787. }
  2788. #else
  2789. static
  2790. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  2791. {
  2792. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  2793. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  2794. if (subtype != QDF_PROTO_INVALID)
  2795. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  2796. }
  2797. #endif
  2798. /**
  2799. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2800. * per wbm ring
  2801. *
  2802. * @tx_desc: software descriptor head pointer
  2803. * @ts: Tx completion status
  2804. * @peer: peer handle
  2805. * @ring_id: ring number
  2806. *
  2807. * Return: None
  2808. */
  2809. static inline void
  2810. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2811. struct hal_tx_completion_status *ts,
  2812. struct dp_peer *peer, uint8_t ring_id)
  2813. {
  2814. struct dp_pdev *pdev = peer->vdev->pdev;
  2815. struct dp_soc *soc = NULL;
  2816. uint8_t mcs, pkt_type;
  2817. uint8_t tid = ts->tid;
  2818. uint32_t length;
  2819. struct cdp_tid_tx_stats *tid_stats;
  2820. if (!pdev)
  2821. return;
  2822. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2823. tid = CDP_MAX_DATA_TIDS - 1;
  2824. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2825. soc = pdev->soc;
  2826. mcs = ts->mcs;
  2827. pkt_type = ts->pkt_type;
  2828. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2829. dp_err("Release source is not from TQM");
  2830. return;
  2831. }
  2832. length = qdf_nbuf_len(tx_desc->nbuf);
  2833. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2834. if (qdf_unlikely(pdev->delay_stats_flag))
  2835. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2836. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2837. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2838. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2839. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2840. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2841. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2842. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2843. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2844. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2845. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2846. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2847. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2848. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2849. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2850. /*
  2851. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  2852. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  2853. * are no completions for failed cases. Hence updating tx_failed from
  2854. * data path. Please note that if tx_failed is fixed to be from ppdu,
  2855. * then this has to be removed
  2856. */
  2857. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  2858. peer->stats.tx.dropped.fw_rem_notx +
  2859. peer->stats.tx.dropped.fw_rem_tx +
  2860. peer->stats.tx.dropped.age_out +
  2861. peer->stats.tx.dropped.fw_reason1 +
  2862. peer->stats.tx.dropped.fw_reason2 +
  2863. peer->stats.tx.dropped.fw_reason3;
  2864. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  2865. tid_stats->tqm_status_cnt[ts->status]++;
  2866. }
  2867. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2868. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  2869. return;
  2870. }
  2871. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2872. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2873. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2874. /*
  2875. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2876. * Return from here if HTT PPDU events are enabled.
  2877. */
  2878. if (!(soc->process_tx_status))
  2879. return;
  2880. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2881. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2882. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2883. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2884. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2885. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2886. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2887. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2888. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2889. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2890. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2891. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2892. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2893. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2894. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2895. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2896. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2897. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2898. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2899. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2900. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2901. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2902. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2903. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2904. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2905. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2906. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2907. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2908. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2909. &peer->stats, ts->peer_id,
  2910. UPDATE_PEER_STATS, pdev->pdev_id);
  2911. #endif
  2912. }
  2913. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2914. /**
  2915. * dp_tx_flow_pool_lock() - take flow pool lock
  2916. * @soc: core txrx main context
  2917. * @tx_desc: tx desc
  2918. *
  2919. * Return: None
  2920. */
  2921. static inline
  2922. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2923. struct dp_tx_desc_s *tx_desc)
  2924. {
  2925. struct dp_tx_desc_pool_s *pool;
  2926. uint8_t desc_pool_id;
  2927. desc_pool_id = tx_desc->pool_id;
  2928. pool = &soc->tx_desc[desc_pool_id];
  2929. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2930. }
  2931. /**
  2932. * dp_tx_flow_pool_unlock() - release flow pool lock
  2933. * @soc: core txrx main context
  2934. * @tx_desc: tx desc
  2935. *
  2936. * Return: None
  2937. */
  2938. static inline
  2939. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2940. struct dp_tx_desc_s *tx_desc)
  2941. {
  2942. struct dp_tx_desc_pool_s *pool;
  2943. uint8_t desc_pool_id;
  2944. desc_pool_id = tx_desc->pool_id;
  2945. pool = &soc->tx_desc[desc_pool_id];
  2946. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2947. }
  2948. #else
  2949. static inline
  2950. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2951. {
  2952. }
  2953. static inline
  2954. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2955. {
  2956. }
  2957. #endif
  2958. /**
  2959. * dp_tx_notify_completion() - Notify tx completion for this desc
  2960. * @soc: core txrx main context
  2961. * @vdev: datapath vdev handle
  2962. * @tx_desc: tx desc
  2963. * @netbuf: buffer
  2964. * @status: tx status
  2965. *
  2966. * Return: none
  2967. */
  2968. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2969. struct dp_vdev *vdev,
  2970. struct dp_tx_desc_s *tx_desc,
  2971. qdf_nbuf_t netbuf,
  2972. uint8_t status)
  2973. {
  2974. void *osif_dev;
  2975. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2976. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  2977. qdf_assert(tx_desc);
  2978. dp_tx_flow_pool_lock(soc, tx_desc);
  2979. if (!vdev ||
  2980. !vdev->osif_vdev) {
  2981. dp_tx_flow_pool_unlock(soc, tx_desc);
  2982. return;
  2983. }
  2984. osif_dev = vdev->osif_vdev;
  2985. tx_compl_cbk = vdev->tx_comp;
  2986. dp_tx_flow_pool_unlock(soc, tx_desc);
  2987. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  2988. flag |= BIT(QDF_TX_RX_STATUS_OK);
  2989. if (tx_compl_cbk)
  2990. tx_compl_cbk(netbuf, osif_dev, flag);
  2991. }
  2992. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2993. * @pdev: pdev handle
  2994. * @tid: tid value
  2995. * @txdesc_ts: timestamp from txdesc
  2996. * @ppdu_id: ppdu id
  2997. *
  2998. * Return: none
  2999. */
  3000. #ifdef FEATURE_PERPKT_INFO
  3001. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3002. struct dp_peer *peer,
  3003. uint8_t tid,
  3004. uint64_t txdesc_ts,
  3005. uint32_t ppdu_id)
  3006. {
  3007. uint64_t delta_ms;
  3008. struct cdp_tx_sojourn_stats *sojourn_stats;
  3009. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  3010. return;
  3011. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3012. tid >= CDP_DATA_TID_MAX))
  3013. return;
  3014. if (qdf_unlikely(!pdev->sojourn_buf))
  3015. return;
  3016. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3017. qdf_nbuf_data(pdev->sojourn_buf);
  3018. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  3019. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  3020. txdesc_ts;
  3021. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  3022. delta_ms);
  3023. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3024. sojourn_stats->num_msdus[tid] = 1;
  3025. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3026. peer->avg_sojourn_msdu[tid].internal;
  3027. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3028. pdev->sojourn_buf, HTT_INVALID_PEER,
  3029. WDI_NO_VAL, pdev->pdev_id);
  3030. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3031. sojourn_stats->num_msdus[tid] = 0;
  3032. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3033. }
  3034. #else
  3035. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3036. struct dp_peer *peer,
  3037. uint8_t tid,
  3038. uint64_t txdesc_ts,
  3039. uint32_t ppdu_id)
  3040. {
  3041. }
  3042. #endif
  3043. /**
  3044. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3045. * @soc: DP Soc handle
  3046. * @tx_desc: software Tx descriptor
  3047. * @ts : Tx completion status from HAL/HTT descriptor
  3048. *
  3049. * Return: none
  3050. */
  3051. static inline void
  3052. dp_tx_comp_process_desc(struct dp_soc *soc,
  3053. struct dp_tx_desc_s *desc,
  3054. struct hal_tx_completion_status *ts,
  3055. struct dp_peer *peer)
  3056. {
  3057. uint64_t time_latency = 0;
  3058. /*
  3059. * m_copy/tx_capture modes are not supported for
  3060. * scatter gather packets
  3061. */
  3062. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3063. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3064. desc->timestamp);
  3065. }
  3066. if (!(desc->msdu_ext_desc)) {
  3067. if (QDF_STATUS_SUCCESS ==
  3068. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3069. return;
  3070. }
  3071. if (QDF_STATUS_SUCCESS ==
  3072. dp_get_completion_indication_for_stack(soc,
  3073. desc->pdev,
  3074. peer, ts,
  3075. desc->nbuf,
  3076. time_latency)) {
  3077. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  3078. QDF_DMA_TO_DEVICE,
  3079. desc->nbuf->len);
  3080. dp_send_completion_to_stack(soc,
  3081. desc->pdev,
  3082. ts->peer_id,
  3083. ts->ppdu_id,
  3084. desc->nbuf);
  3085. return;
  3086. }
  3087. }
  3088. dp_tx_comp_free_buf(soc, desc);
  3089. }
  3090. #ifdef DISABLE_DP_STATS
  3091. /**
  3092. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3093. * @soc: core txrx main context
  3094. * @tx_desc: tx desc
  3095. * @status: tx status
  3096. *
  3097. * Return: none
  3098. */
  3099. static inline
  3100. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3101. struct dp_vdev *vdev,
  3102. struct dp_tx_desc_s *tx_desc,
  3103. uint8_t status)
  3104. {
  3105. }
  3106. #else
  3107. static inline
  3108. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3109. struct dp_vdev *vdev,
  3110. struct dp_tx_desc_s *tx_desc,
  3111. uint8_t status)
  3112. {
  3113. void *osif_dev;
  3114. ol_txrx_stats_rx_fp stats_cbk;
  3115. uint8_t pkt_type;
  3116. qdf_assert(tx_desc);
  3117. if (!vdev ||
  3118. !vdev->osif_vdev ||
  3119. !vdev->stats_cb)
  3120. return;
  3121. osif_dev = vdev->osif_vdev;
  3122. stats_cbk = vdev->stats_cb;
  3123. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3124. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3125. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3126. &pkt_type);
  3127. }
  3128. #endif
  3129. /**
  3130. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3131. * @soc: DP soc handle
  3132. * @tx_desc: software descriptor head pointer
  3133. * @ts: Tx completion status
  3134. * @peer: peer handle
  3135. * @ring_id: ring number
  3136. *
  3137. * Return: none
  3138. */
  3139. static inline
  3140. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3141. struct dp_tx_desc_s *tx_desc,
  3142. struct hal_tx_completion_status *ts,
  3143. struct dp_peer *peer, uint8_t ring_id)
  3144. {
  3145. uint32_t length;
  3146. qdf_ether_header_t *eh;
  3147. struct dp_vdev *vdev = NULL;
  3148. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3149. uint8_t dp_status;
  3150. if (!nbuf) {
  3151. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3152. goto out;
  3153. }
  3154. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3155. length = qdf_nbuf_len(nbuf);
  3156. dp_status = qdf_dp_get_status_from_htt(ts->status);
  3157. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3158. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3159. QDF_TRACE_DEFAULT_PDEV_ID,
  3160. qdf_nbuf_data_addr(nbuf),
  3161. sizeof(qdf_nbuf_data(nbuf)),
  3162. tx_desc->id,
  3163. dp_status));
  3164. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3165. "-------------------- \n"
  3166. "Tx Completion Stats: \n"
  3167. "-------------------- \n"
  3168. "ack_frame_rssi = %d \n"
  3169. "first_msdu = %d \n"
  3170. "last_msdu = %d \n"
  3171. "msdu_part_of_amsdu = %d \n"
  3172. "rate_stats valid = %d \n"
  3173. "bw = %d \n"
  3174. "pkt_type = %d \n"
  3175. "stbc = %d \n"
  3176. "ldpc = %d \n"
  3177. "sgi = %d \n"
  3178. "mcs = %d \n"
  3179. "ofdma = %d \n"
  3180. "tones_in_ru = %d \n"
  3181. "tsf = %d \n"
  3182. "ppdu_id = %d \n"
  3183. "transmit_cnt = %d \n"
  3184. "tid = %d \n"
  3185. "peer_id = %d\n",
  3186. ts->ack_frame_rssi, ts->first_msdu,
  3187. ts->last_msdu, ts->msdu_part_of_amsdu,
  3188. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3189. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3190. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3191. ts->transmit_cnt, ts->tid, ts->peer_id);
  3192. /* Update SoC level stats */
  3193. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3194. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3195. if (!peer) {
  3196. dp_err_rl("peer is null or deletion in progress");
  3197. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3198. goto out;
  3199. }
  3200. vdev = peer->vdev;
  3201. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3202. /* Update per-packet stats for mesh mode */
  3203. if (qdf_unlikely(vdev->mesh_vdev) &&
  3204. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3205. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3206. /* Update peer level stats */
  3207. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3208. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3209. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3210. if ((peer->vdev->tx_encap_type ==
  3211. htt_cmn_pkt_type_ethernet) &&
  3212. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3213. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3214. }
  3215. }
  3216. } else {
  3217. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3218. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3219. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3220. if (qdf_unlikely(peer->in_twt)) {
  3221. DP_STATS_INC_PKT(peer,
  3222. tx.tx_success_twt,
  3223. 1, length);
  3224. }
  3225. }
  3226. }
  3227. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3228. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3229. #ifdef QCA_SUPPORT_RDK_STATS
  3230. if (soc->wlanstats_enabled)
  3231. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3232. tx_desc->timestamp,
  3233. ts->ppdu_id);
  3234. #endif
  3235. out:
  3236. return;
  3237. }
  3238. /**
  3239. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3240. * @soc: core txrx main context
  3241. * @comp_head: software descriptor head pointer
  3242. * @ring_id: ring number
  3243. *
  3244. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3245. * and release the software descriptors after processing is complete
  3246. *
  3247. * Return: none
  3248. */
  3249. static void
  3250. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3251. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3252. {
  3253. struct dp_tx_desc_s *desc;
  3254. struct dp_tx_desc_s *next;
  3255. struct hal_tx_completion_status ts;
  3256. struct dp_peer *peer;
  3257. qdf_nbuf_t netbuf;
  3258. desc = comp_head;
  3259. while (desc) {
  3260. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3261. struct dp_pdev *pdev = desc->pdev;
  3262. peer = dp_peer_get_ref_by_id(soc, desc->peer_id,
  3263. DP_MOD_ID_TX_COMP);
  3264. if (qdf_likely(peer)) {
  3265. /*
  3266. * Increment peer statistics
  3267. * Minimal statistics update done here
  3268. */
  3269. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3270. desc->length);
  3271. if (desc->tx_status !=
  3272. HAL_TX_TQM_RR_FRAME_ACKED)
  3273. peer->stats.tx.tx_failed++;
  3274. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3275. }
  3276. qdf_assert(pdev);
  3277. dp_tx_outstanding_dec(pdev);
  3278. /*
  3279. * Calling a QDF WRAPPER here is creating signifcant
  3280. * performance impact so avoided the wrapper call here
  3281. */
  3282. next = desc->next;
  3283. qdf_mem_unmap_nbytes_single(soc->osdev,
  3284. desc->dma_addr,
  3285. QDF_DMA_TO_DEVICE,
  3286. desc->length);
  3287. qdf_nbuf_free(desc->nbuf);
  3288. dp_tx_desc_free(soc, desc, desc->pool_id);
  3289. desc = next;
  3290. continue;
  3291. }
  3292. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3293. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3294. DP_MOD_ID_TX_COMP);
  3295. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3296. netbuf = desc->nbuf;
  3297. /* check tx complete notification */
  3298. if (peer &&
  3299. QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  3300. dp_tx_notify_completion(soc, peer->vdev, desc,
  3301. netbuf, ts.status);
  3302. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3303. if (peer)
  3304. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3305. next = desc->next;
  3306. dp_tx_desc_release(desc, desc->pool_id);
  3307. desc = next;
  3308. }
  3309. }
  3310. /**
  3311. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3312. * @tx_desc: software descriptor head pointer
  3313. * @status : Tx completion status from HTT descriptor
  3314. * @ring_id: ring number
  3315. *
  3316. * This function will process HTT Tx indication messages from Target
  3317. *
  3318. * Return: none
  3319. */
  3320. static
  3321. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3322. uint8_t ring_id)
  3323. {
  3324. uint8_t tx_status;
  3325. struct dp_pdev *pdev;
  3326. struct dp_vdev *vdev;
  3327. struct dp_soc *soc;
  3328. struct hal_tx_completion_status ts = {0};
  3329. uint32_t *htt_desc = (uint32_t *)status;
  3330. struct dp_peer *peer;
  3331. struct cdp_tid_tx_stats *tid_stats = NULL;
  3332. struct htt_soc *htt_handle;
  3333. /*
  3334. * If the descriptor is already freed in vdev_detach,
  3335. * continue to next descriptor
  3336. */
  3337. if ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) && !tx_desc->flags) {
  3338. QDF_TRACE(QDF_MODULE_ID_DP,
  3339. QDF_TRACE_LEVEL_INFO,
  3340. "Descriptor freed in vdev_detach %d",
  3341. tx_desc->id);
  3342. return;
  3343. }
  3344. pdev = tx_desc->pdev;
  3345. soc = pdev->soc;
  3346. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3347. QDF_TRACE(QDF_MODULE_ID_DP,
  3348. QDF_TRACE_LEVEL_INFO,
  3349. "pdev in down state %d",
  3350. tx_desc->id);
  3351. dp_tx_comp_free_buf(soc, tx_desc);
  3352. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3353. return;
  3354. }
  3355. qdf_assert(tx_desc->pdev);
  3356. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  3357. DP_MOD_ID_HTT_COMP);
  3358. if (!vdev)
  3359. return;
  3360. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3361. htt_handle = (struct htt_soc *)soc->htt_handle;
  3362. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3363. switch (tx_status) {
  3364. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3365. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3366. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3367. {
  3368. uint8_t tid;
  3369. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3370. ts.peer_id =
  3371. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3372. htt_desc[2]);
  3373. ts.tid =
  3374. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3375. htt_desc[2]);
  3376. } else {
  3377. ts.peer_id = HTT_INVALID_PEER;
  3378. ts.tid = HTT_INVALID_TID;
  3379. }
  3380. ts.ppdu_id =
  3381. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3382. htt_desc[1]);
  3383. ts.ack_frame_rssi =
  3384. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3385. htt_desc[1]);
  3386. ts.tsf = htt_desc[3];
  3387. ts.first_msdu = 1;
  3388. ts.last_msdu = 1;
  3389. tid = ts.tid;
  3390. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3391. tid = CDP_MAX_DATA_TIDS - 1;
  3392. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3393. if (qdf_unlikely(pdev->delay_stats_flag))
  3394. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3395. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3396. tid_stats->htt_status_cnt[tx_status]++;
  3397. }
  3398. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3399. DP_MOD_ID_HTT_COMP);
  3400. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3401. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3402. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3403. if (qdf_likely(peer))
  3404. dp_peer_unref_delete(peer, DP_MOD_ID_HTT_COMP);
  3405. break;
  3406. }
  3407. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3408. {
  3409. dp_tx_reinject_handler(soc, vdev, tx_desc, status);
  3410. break;
  3411. }
  3412. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3413. {
  3414. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  3415. break;
  3416. }
  3417. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  3418. {
  3419. dp_tx_mec_handler(vdev, status);
  3420. break;
  3421. }
  3422. default:
  3423. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3424. "%s Invalid HTT tx_status %d\n",
  3425. __func__, tx_status);
  3426. break;
  3427. }
  3428. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3429. }
  3430. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3431. static inline
  3432. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3433. {
  3434. bool limit_hit = false;
  3435. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3436. limit_hit =
  3437. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  3438. if (limit_hit)
  3439. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3440. return limit_hit;
  3441. }
  3442. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3443. {
  3444. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3445. }
  3446. #else
  3447. static inline
  3448. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3449. {
  3450. return false;
  3451. }
  3452. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3453. {
  3454. return false;
  3455. }
  3456. #endif
  3457. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3458. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3459. uint32_t quota)
  3460. {
  3461. void *tx_comp_hal_desc;
  3462. uint8_t buffer_src;
  3463. uint8_t pool_id;
  3464. uint32_t tx_desc_id;
  3465. struct dp_tx_desc_s *tx_desc = NULL;
  3466. struct dp_tx_desc_s *head_desc = NULL;
  3467. struct dp_tx_desc_s *tail_desc = NULL;
  3468. uint32_t num_processed = 0;
  3469. uint32_t count;
  3470. uint32_t num_avail_for_reap = 0;
  3471. bool force_break = false;
  3472. DP_HIST_INIT();
  3473. more_data:
  3474. /* Re-initialize local variables to be re-used */
  3475. head_desc = NULL;
  3476. tail_desc = NULL;
  3477. count = 0;
  3478. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3479. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3480. return 0;
  3481. }
  3482. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  3483. if (num_avail_for_reap >= quota)
  3484. num_avail_for_reap = quota;
  3485. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  3486. /* Find head descriptor from completion ring */
  3487. while (qdf_likely(num_avail_for_reap)) {
  3488. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  3489. if (qdf_unlikely(!tx_comp_hal_desc))
  3490. break;
  3491. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3492. /* If this buffer was not released by TQM or FW, then it is not
  3493. * Tx completion indication, assert */
  3494. if (qdf_unlikely(buffer_src !=
  3495. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3496. (qdf_unlikely(buffer_src !=
  3497. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  3498. uint8_t wbm_internal_error;
  3499. dp_err_rl(
  3500. "Tx comp release_src != TQM | FW but from %d",
  3501. buffer_src);
  3502. hal_dump_comp_desc(tx_comp_hal_desc);
  3503. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3504. /* When WBM sees NULL buffer_addr_info in any of
  3505. * ingress rings it sends an error indication,
  3506. * with wbm_internal_error=1, to a specific ring.
  3507. * The WBM2SW ring used to indicate these errors is
  3508. * fixed in HW, and that ring is being used as Tx
  3509. * completion ring. These errors are not related to
  3510. * Tx completions, and should just be ignored
  3511. */
  3512. wbm_internal_error = hal_get_wbm_internal_error(
  3513. soc->hal_soc,
  3514. tx_comp_hal_desc);
  3515. if (wbm_internal_error) {
  3516. dp_err_rl("Tx comp wbm_internal_error!!");
  3517. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3518. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3519. buffer_src)
  3520. dp_handle_wbm_internal_error(
  3521. soc,
  3522. tx_comp_hal_desc,
  3523. hal_tx_comp_get_buffer_type(
  3524. tx_comp_hal_desc));
  3525. } else {
  3526. dp_err_rl("Tx comp wbm_internal_error false");
  3527. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  3528. }
  3529. continue;
  3530. }
  3531. /* Get descriptor id */
  3532. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3533. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3534. DP_TX_DESC_ID_POOL_OS;
  3535. /* Find Tx descriptor */
  3536. tx_desc = dp_tx_desc_find(soc, pool_id,
  3537. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3538. DP_TX_DESC_ID_PAGE_OS,
  3539. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3540. DP_TX_DESC_ID_OFFSET_OS);
  3541. /*
  3542. * If the release source is FW, process the HTT status
  3543. */
  3544. if (qdf_unlikely(buffer_src ==
  3545. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3546. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3547. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3548. htt_tx_status);
  3549. dp_tx_process_htt_completion(tx_desc,
  3550. htt_tx_status, ring_id);
  3551. } else {
  3552. /*
  3553. * If the fast completion mode is enabled extended
  3554. * metadata from descriptor is not copied
  3555. */
  3556. if (qdf_likely(tx_desc->flags &
  3557. DP_TX_DESC_FLAG_SIMPLE)) {
  3558. tx_desc->peer_id =
  3559. hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  3560. tx_desc->tx_status =
  3561. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  3562. goto add_to_pool;
  3563. }
  3564. /*
  3565. * If the descriptor is already freed in vdev_detach,
  3566. * continue to next descriptor
  3567. */
  3568. if (qdf_unlikely
  3569. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  3570. !tx_desc->flags)) {
  3571. QDF_TRACE(QDF_MODULE_ID_DP,
  3572. QDF_TRACE_LEVEL_INFO,
  3573. "Descriptor freed in vdev_detach %d",
  3574. tx_desc_id);
  3575. continue;
  3576. }
  3577. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3578. QDF_TRACE(QDF_MODULE_ID_DP,
  3579. QDF_TRACE_LEVEL_INFO,
  3580. "pdev in down state %d",
  3581. tx_desc_id);
  3582. dp_tx_comp_free_buf(soc, tx_desc);
  3583. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3584. goto next_desc;
  3585. }
  3586. /* Pool id is not matching. Error */
  3587. if (tx_desc->pool_id != pool_id) {
  3588. QDF_TRACE(QDF_MODULE_ID_DP,
  3589. QDF_TRACE_LEVEL_FATAL,
  3590. "Tx Comp pool id %d not matched %d",
  3591. pool_id, tx_desc->pool_id);
  3592. qdf_assert_always(0);
  3593. }
  3594. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3595. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3596. QDF_TRACE(QDF_MODULE_ID_DP,
  3597. QDF_TRACE_LEVEL_FATAL,
  3598. "Txdesc invalid, flgs = %x,id = %d",
  3599. tx_desc->flags, tx_desc_id);
  3600. qdf_assert_always(0);
  3601. }
  3602. /* Collect hw completion contents */
  3603. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3604. &tx_desc->comp, 1);
  3605. add_to_pool:
  3606. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3607. /* First ring descriptor on the cycle */
  3608. if (!head_desc) {
  3609. head_desc = tx_desc;
  3610. tail_desc = tx_desc;
  3611. }
  3612. tail_desc->next = tx_desc;
  3613. tx_desc->next = NULL;
  3614. tail_desc = tx_desc;
  3615. }
  3616. next_desc:
  3617. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3618. /*
  3619. * Processed packet count is more than given quota
  3620. * stop to processing
  3621. */
  3622. count++;
  3623. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3624. break;
  3625. }
  3626. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3627. /* Process the reaped descriptors */
  3628. if (head_desc)
  3629. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3630. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3631. if (num_processed >= quota)
  3632. force_break = true;
  3633. if (!force_break &&
  3634. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3635. hal_ring_hdl)) {
  3636. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3637. if (!hif_exec_should_yield(soc->hif_handle,
  3638. int_ctx->dp_intr_id))
  3639. goto more_data;
  3640. }
  3641. }
  3642. DP_TX_HIST_STATS_PER_PDEV();
  3643. return num_processed;
  3644. }
  3645. #ifdef FEATURE_WLAN_TDLS
  3646. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3647. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3648. {
  3649. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3650. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3651. DP_MOD_ID_TDLS);
  3652. if (!vdev) {
  3653. dp_err("vdev handle for id %d is NULL", vdev_id);
  3654. return NULL;
  3655. }
  3656. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3657. vdev->is_tdls_frame = true;
  3658. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  3659. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  3660. }
  3661. #endif
  3662. static void dp_tx_vdev_update_feature_flags(struct dp_vdev *vdev)
  3663. {
  3664. struct wlan_cfg_dp_soc_ctxt *cfg;
  3665. struct dp_soc *soc;
  3666. soc = vdev->pdev->soc;
  3667. if (!soc)
  3668. return;
  3669. cfg = soc->wlan_cfg_ctx;
  3670. if (!cfg)
  3671. return;
  3672. if (vdev->opmode == wlan_op_mode_ndi)
  3673. vdev->csum_enabled = wlan_cfg_get_nan_checksum_offload(cfg);
  3674. else if ((vdev->subtype == wlan_op_subtype_p2p_device) ||
  3675. (vdev->subtype == wlan_op_subtype_p2p_cli) ||
  3676. (vdev->subtype == wlan_op_subtype_p2p_go))
  3677. vdev->csum_enabled = wlan_cfg_get_p2p_checksum_offload(cfg);
  3678. else
  3679. vdev->csum_enabled = wlan_cfg_get_checksum_offload(cfg);
  3680. }
  3681. /**
  3682. * dp_tx_vdev_attach() - attach vdev to dp tx
  3683. * @vdev: virtual device instance
  3684. *
  3685. * Return: QDF_STATUS_SUCCESS: success
  3686. * QDF_STATUS_E_RESOURCES: Error return
  3687. */
  3688. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3689. {
  3690. int pdev_id;
  3691. /*
  3692. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3693. */
  3694. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3695. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3696. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3697. vdev->vdev_id);
  3698. pdev_id =
  3699. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  3700. vdev->pdev->pdev_id);
  3701. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  3702. /*
  3703. * Set HTT Extension Valid bit to 0 by default
  3704. */
  3705. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3706. dp_tx_vdev_update_search_flags(vdev);
  3707. dp_tx_vdev_update_feature_flags(vdev);
  3708. return QDF_STATUS_SUCCESS;
  3709. }
  3710. #ifndef FEATURE_WDS
  3711. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3712. {
  3713. return false;
  3714. }
  3715. #endif
  3716. /**
  3717. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3718. * @vdev: virtual device instance
  3719. *
  3720. * Return: void
  3721. *
  3722. */
  3723. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3724. {
  3725. struct dp_soc *soc = vdev->pdev->soc;
  3726. /*
  3727. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3728. * for TDLS link
  3729. *
  3730. * Enable AddrY (SA based search) only for non-WDS STA and
  3731. * ProxySTA VAP (in HKv1) modes.
  3732. *
  3733. * In all other VAP modes, only DA based search should be
  3734. * enabled
  3735. */
  3736. if (vdev->opmode == wlan_op_mode_sta &&
  3737. vdev->tdls_link_connected)
  3738. vdev->hal_desc_addr_search_flags =
  3739. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3740. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3741. !dp_tx_da_search_override(vdev))
  3742. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3743. else
  3744. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3745. /* Set search type only when peer map v2 messaging is enabled
  3746. * as we will have the search index (AST hash) only when v2 is
  3747. * enabled
  3748. */
  3749. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3750. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3751. else
  3752. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3753. }
  3754. static inline bool
  3755. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3756. struct dp_vdev *vdev,
  3757. struct dp_tx_desc_s *tx_desc)
  3758. {
  3759. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3760. return false;
  3761. /*
  3762. * if vdev is given, then only check whether desc
  3763. * vdev match. if vdev is NULL, then check whether
  3764. * desc pdev match.
  3765. */
  3766. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  3767. (tx_desc->pdev == pdev);
  3768. }
  3769. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3770. /**
  3771. * dp_tx_desc_flush() - release resources associated
  3772. * to TX Desc
  3773. *
  3774. * @dp_pdev: Handle to DP pdev structure
  3775. * @vdev: virtual device instance
  3776. * NULL: no specific Vdev is required and check all allcated TX desc
  3777. * on this pdev.
  3778. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3779. *
  3780. * @force_free:
  3781. * true: flush the TX desc.
  3782. * false: only reset the Vdev in each allocated TX desc
  3783. * that associated to current Vdev.
  3784. *
  3785. * This function will go through the TX desc pool to flush
  3786. * the outstanding TX data or reset Vdev to NULL in associated TX
  3787. * Desc.
  3788. */
  3789. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  3790. bool force_free)
  3791. {
  3792. uint8_t i;
  3793. uint32_t j;
  3794. uint32_t num_desc, page_id, offset;
  3795. uint16_t num_desc_per_page;
  3796. struct dp_soc *soc = pdev->soc;
  3797. struct dp_tx_desc_s *tx_desc = NULL;
  3798. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3799. if (!vdev && !force_free) {
  3800. dp_err("Reset TX desc vdev, Vdev param is required!");
  3801. return;
  3802. }
  3803. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3804. tx_desc_pool = &soc->tx_desc[i];
  3805. if (!(tx_desc_pool->pool_size) ||
  3806. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3807. !(tx_desc_pool->desc_pages.cacheable_pages))
  3808. continue;
  3809. /*
  3810. * Add flow pool lock protection in case pool is freed
  3811. * due to all tx_desc is recycled when handle TX completion.
  3812. * this is not necessary when do force flush as:
  3813. * a. double lock will happen if dp_tx_desc_release is
  3814. * also trying to acquire it.
  3815. * b. dp interrupt has been disabled before do force TX desc
  3816. * flush in dp_pdev_deinit().
  3817. */
  3818. if (!force_free)
  3819. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  3820. num_desc = tx_desc_pool->pool_size;
  3821. num_desc_per_page =
  3822. tx_desc_pool->desc_pages.num_element_per_page;
  3823. for (j = 0; j < num_desc; j++) {
  3824. page_id = j / num_desc_per_page;
  3825. offset = j % num_desc_per_page;
  3826. if (qdf_unlikely(!(tx_desc_pool->
  3827. desc_pages.cacheable_pages)))
  3828. break;
  3829. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3830. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3831. /*
  3832. * Free TX desc if force free is
  3833. * required, otherwise only reset vdev
  3834. * in this TX desc.
  3835. */
  3836. if (force_free) {
  3837. dp_tx_comp_free_buf(soc, tx_desc);
  3838. dp_tx_desc_release(tx_desc, i);
  3839. } else {
  3840. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  3841. }
  3842. }
  3843. }
  3844. if (!force_free)
  3845. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  3846. }
  3847. }
  3848. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3849. /**
  3850. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3851. *
  3852. * @soc: Handle to DP soc structure
  3853. * @tx_desc: pointer of one TX desc
  3854. * @desc_pool_id: TX Desc pool id
  3855. */
  3856. static inline void
  3857. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3858. uint8_t desc_pool_id)
  3859. {
  3860. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3861. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  3862. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3863. }
  3864. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  3865. bool force_free)
  3866. {
  3867. uint8_t i, num_pool;
  3868. uint32_t j;
  3869. uint32_t num_desc, page_id, offset;
  3870. uint16_t num_desc_per_page;
  3871. struct dp_soc *soc = pdev->soc;
  3872. struct dp_tx_desc_s *tx_desc = NULL;
  3873. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3874. if (!vdev && !force_free) {
  3875. dp_err("Reset TX desc vdev, Vdev param is required!");
  3876. return;
  3877. }
  3878. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3879. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3880. for (i = 0; i < num_pool; i++) {
  3881. tx_desc_pool = &soc->tx_desc[i];
  3882. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3883. continue;
  3884. num_desc_per_page =
  3885. tx_desc_pool->desc_pages.num_element_per_page;
  3886. for (j = 0; j < num_desc; j++) {
  3887. page_id = j / num_desc_per_page;
  3888. offset = j % num_desc_per_page;
  3889. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3890. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3891. if (force_free) {
  3892. dp_tx_comp_free_buf(soc, tx_desc);
  3893. dp_tx_desc_release(tx_desc, i);
  3894. } else {
  3895. dp_tx_desc_reset_vdev(soc, tx_desc,
  3896. i);
  3897. }
  3898. }
  3899. }
  3900. }
  3901. }
  3902. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3903. /**
  3904. * dp_tx_vdev_detach() - detach vdev from dp tx
  3905. * @vdev: virtual device instance
  3906. *
  3907. * Return: QDF_STATUS_SUCCESS: success
  3908. * QDF_STATUS_E_RESOURCES: Error return
  3909. */
  3910. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3911. {
  3912. struct dp_pdev *pdev = vdev->pdev;
  3913. /* Reset TX desc associated to this Vdev as NULL */
  3914. dp_tx_desc_flush(pdev, vdev, false);
  3915. dp_tx_vdev_multipass_deinit(vdev);
  3916. return QDF_STATUS_SUCCESS;
  3917. }
  3918. /**
  3919. * dp_tx_pdev_attach() - attach pdev to dp tx
  3920. * @pdev: physical device instance
  3921. *
  3922. * Return: QDF_STATUS_SUCCESS: success
  3923. * QDF_STATUS_E_RESOURCES: Error return
  3924. */
  3925. QDF_STATUS dp_tx_pdev_init(struct dp_pdev *pdev)
  3926. {
  3927. struct dp_soc *soc = pdev->soc;
  3928. /* Initialize Flow control counters */
  3929. qdf_atomic_init(&pdev->num_tx_outstanding);
  3930. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3931. /* Initialize descriptors in TCL Ring */
  3932. hal_tx_init_data_ring(soc->hal_soc,
  3933. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3934. }
  3935. return QDF_STATUS_SUCCESS;
  3936. }
  3937. /**
  3938. * dp_tx_pdev_detach() - detach pdev from dp tx
  3939. * @pdev: physical device instance
  3940. *
  3941. * Return: QDF_STATUS_SUCCESS: success
  3942. * QDF_STATUS_E_RESOURCES: Error return
  3943. */
  3944. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3945. {
  3946. /* flush TX outstanding data per pdev */
  3947. dp_tx_desc_flush(pdev, NULL, true);
  3948. dp_tx_me_exit(pdev);
  3949. return QDF_STATUS_SUCCESS;
  3950. }
  3951. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3952. /* Pools will be allocated dynamically */
  3953. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3954. int num_desc)
  3955. {
  3956. uint8_t i;
  3957. for (i = 0; i < num_pool; i++) {
  3958. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3959. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3960. }
  3961. return QDF_STATUS_SUCCESS;
  3962. }
  3963. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  3964. int num_desc)
  3965. {
  3966. return QDF_STATUS_SUCCESS;
  3967. }
  3968. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  3969. {
  3970. }
  3971. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3972. {
  3973. uint8_t i;
  3974. for (i = 0; i < num_pool; i++)
  3975. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3976. }
  3977. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3978. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3979. int num_desc)
  3980. {
  3981. uint8_t i, count;
  3982. /* Allocate software Tx descriptor pools */
  3983. for (i = 0; i < num_pool; i++) {
  3984. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3985. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3986. FL("Tx Desc Pool alloc %d failed %pK"),
  3987. i, soc);
  3988. goto fail;
  3989. }
  3990. }
  3991. return QDF_STATUS_SUCCESS;
  3992. fail:
  3993. for (count = 0; count < i; count++)
  3994. dp_tx_desc_pool_free(soc, count);
  3995. return QDF_STATUS_E_NOMEM;
  3996. }
  3997. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  3998. int num_desc)
  3999. {
  4000. uint8_t i;
  4001. for (i = 0; i < num_pool; i++) {
  4002. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4003. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4004. FL("Tx Desc Pool init %d failed %pK"),
  4005. i, soc);
  4006. return QDF_STATUS_E_NOMEM;
  4007. }
  4008. }
  4009. return QDF_STATUS_SUCCESS;
  4010. }
  4011. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4012. {
  4013. uint8_t i;
  4014. for (i = 0; i < num_pool; i++)
  4015. dp_tx_desc_pool_deinit(soc, i);
  4016. }
  4017. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4018. {
  4019. uint8_t i;
  4020. for (i = 0; i < num_pool; i++)
  4021. dp_tx_desc_pool_free(soc, i);
  4022. }
  4023. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4024. /**
  4025. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4026. * @soc: core txrx main context
  4027. * @num_pool: number of pools
  4028. *
  4029. */
  4030. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4031. {
  4032. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4033. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4034. }
  4035. /**
  4036. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4037. * @soc: core txrx main context
  4038. * @num_pool: number of pools
  4039. *
  4040. */
  4041. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4042. {
  4043. dp_tx_tso_desc_pool_free(soc, num_pool);
  4044. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4045. }
  4046. /**
  4047. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4048. * @soc: core txrx main context
  4049. *
  4050. * This function frees all tx related descriptors as below
  4051. * 1. Regular TX descriptors (static pools)
  4052. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4053. * 3. TSO descriptors
  4054. *
  4055. */
  4056. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4057. {
  4058. uint8_t num_pool;
  4059. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4060. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4061. dp_tx_ext_desc_pool_free(soc, num_pool);
  4062. dp_tx_delete_static_pools(soc, num_pool);
  4063. }
  4064. /**
  4065. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4066. * @soc: core txrx main context
  4067. *
  4068. * This function de-initializes all tx related descriptors as below
  4069. * 1. Regular TX descriptors (static pools)
  4070. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4071. * 3. TSO descriptors
  4072. *
  4073. */
  4074. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4075. {
  4076. uint8_t num_pool;
  4077. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4078. dp_tx_flow_control_deinit(soc);
  4079. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4080. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4081. dp_tx_deinit_static_pools(soc, num_pool);
  4082. }
  4083. /**
  4084. * dp_tso_attach() - TSO attach handler
  4085. * @txrx_soc: Opaque Dp handle
  4086. *
  4087. * Reserve TSO descriptor buffers
  4088. *
  4089. * Return: QDF_STATUS_E_FAILURE on failure or
  4090. * QDF_STATUS_SUCCESS on success
  4091. */
  4092. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4093. uint8_t num_pool,
  4094. uint16_t num_desc)
  4095. {
  4096. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4097. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4098. return QDF_STATUS_E_FAILURE;
  4099. }
  4100. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4101. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4102. num_pool, soc);
  4103. return QDF_STATUS_E_FAILURE;
  4104. }
  4105. return QDF_STATUS_SUCCESS;
  4106. }
  4107. /**
  4108. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4109. * @soc: DP soc handle
  4110. * @num_pool: Number of pools
  4111. * @num_desc: Number of descriptors
  4112. *
  4113. * Initialize TSO descriptor pools
  4114. *
  4115. * Return: QDF_STATUS_E_FAILURE on failure or
  4116. * QDF_STATUS_SUCCESS on success
  4117. */
  4118. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4119. uint8_t num_pool,
  4120. uint16_t num_desc)
  4121. {
  4122. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4123. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4124. return QDF_STATUS_E_FAILURE;
  4125. }
  4126. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4127. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4128. num_pool, soc);
  4129. return QDF_STATUS_E_FAILURE;
  4130. }
  4131. return QDF_STATUS_SUCCESS;
  4132. }
  4133. /**
  4134. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4135. * @soc: core txrx main context
  4136. *
  4137. * This function allocates memory for following descriptor pools
  4138. * 1. regular sw tx descriptor pools (static pools)
  4139. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4140. * 3. TSO descriptor pools
  4141. *
  4142. * Return: QDF_STATUS_SUCCESS: success
  4143. * QDF_STATUS_E_RESOURCES: Error return
  4144. */
  4145. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4146. {
  4147. uint8_t num_pool;
  4148. uint32_t num_desc;
  4149. uint32_t num_ext_desc;
  4150. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4151. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4152. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4153. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4154. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4155. __func__, num_pool, num_desc);
  4156. if ((num_pool > MAX_TXDESC_POOLS) ||
  4157. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4158. goto fail1;
  4159. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4160. goto fail1;
  4161. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4162. goto fail2;
  4163. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4164. return QDF_STATUS_SUCCESS;
  4165. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4166. goto fail3;
  4167. return QDF_STATUS_SUCCESS;
  4168. fail3:
  4169. dp_tx_ext_desc_pool_free(soc, num_pool);
  4170. fail2:
  4171. dp_tx_delete_static_pools(soc, num_pool);
  4172. fail1:
  4173. return QDF_STATUS_E_RESOURCES;
  4174. }
  4175. /**
  4176. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4177. * @soc: core txrx main context
  4178. *
  4179. * This function initializes the following TX descriptor pools
  4180. * 1. regular sw tx descriptor pools (static pools)
  4181. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4182. * 3. TSO descriptor pools
  4183. *
  4184. * Return: QDF_STATUS_SUCCESS: success
  4185. * QDF_STATUS_E_RESOURCES: Error return
  4186. */
  4187. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4188. {
  4189. uint8_t num_pool;
  4190. uint32_t num_desc;
  4191. uint32_t num_ext_desc;
  4192. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4193. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4194. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4195. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4196. goto fail1;
  4197. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4198. goto fail2;
  4199. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4200. return QDF_STATUS_SUCCESS;
  4201. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4202. goto fail3;
  4203. dp_tx_flow_control_init(soc);
  4204. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4205. return QDF_STATUS_SUCCESS;
  4206. fail3:
  4207. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4208. fail2:
  4209. dp_tx_deinit_static_pools(soc, num_pool);
  4210. fail1:
  4211. return QDF_STATUS_E_RESOURCES;
  4212. }
  4213. /**
  4214. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4215. * @txrx_soc: dp soc handle
  4216. *
  4217. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4218. * QDF_STATUS_E_FAILURE
  4219. */
  4220. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4221. {
  4222. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4223. uint8_t num_pool;
  4224. uint32_t num_desc;
  4225. uint32_t num_ext_desc;
  4226. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4227. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4228. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4229. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4230. return QDF_STATUS_E_FAILURE;
  4231. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4232. return QDF_STATUS_E_FAILURE;
  4233. return QDF_STATUS_SUCCESS;
  4234. }
  4235. /**
  4236. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4237. * @txrx_soc: dp soc handle
  4238. *
  4239. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4240. */
  4241. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4242. {
  4243. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4244. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4245. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4246. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4247. return QDF_STATUS_SUCCESS;
  4248. }