c6257272d4
Fix dlkm compilation errors that are due to the use of -Werror flags used by the build system. Change-Id: I5e1e9bc63c1361d73e4930aab123212717872ecb Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
357 行
9.0 KiB
C
357 行
9.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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*/
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#include "sde_hw_mdss.h"
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#include "sde_hwio.h"
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#include "sde_hw_catalog.h"
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#include "sde_hw_dsc.h"
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#include "sde_hw_pingpong.h"
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#include "sde_dbg.h"
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#include "sde_kms.h"
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#define DSC_CMN_MAIN_CNF 0x00
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/* SDE_DSC_ENC regsiter offsets */
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#define ENC_DF_CTRL 0x00
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#define ENC_GENERAL_STATUS 0x04
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#define ENC_HSLICE_STATUS 0x08
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#define ENC_OUT_STATUS 0x0C
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#define ENC_INT_STAT 0x10
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#define ENC_INT_CLR 0x14
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#define ENC_INT_MASK 0x18
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#define DSC_MAIN_CONF 0x30
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#define DSC_PICTURE_SIZE 0x34
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#define DSC_SLICE_SIZE 0x38
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#define DSC_MISC_SIZE 0x3C
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#define DSC_HRD_DELAYS 0x40
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#define DSC_RC_SCALE 0x44
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#define DSC_RC_SCALE_INC_DEC 0x48
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#define DSC_RC_OFFSETS_1 0x4C
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#define DSC_RC_OFFSETS_2 0x50
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#define DSC_RC_OFFSETS_3 0x54
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#define DSC_RC_OFFSETS_4 0x58
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#define DSC_FLATNESS_QP 0x5C
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#define DSC_RC_MODEL_SIZE 0x60
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#define DSC_RC_CONFIG 0x64
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#define DSC_RC_BUF_THRESH_0 0x68
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#define DSC_RC_BUF_THRESH_1 0x6C
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#define DSC_RC_BUF_THRESH_2 0x70
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#define DSC_RC_BUF_THRESH_3 0x74
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#define DSC_RC_MIN_QP_0 0x78
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#define DSC_RC_MIN_QP_1 0x7C
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#define DSC_RC_MIN_QP_2 0x80
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#define DSC_RC_MAX_QP_0 0x84
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#define DSC_RC_MAX_QP_1 0x88
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#define DSC_RC_MAX_QP_2 0x8C
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#define DSC_RC_RANGE_BPG_OFFSETS_0 0x90
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#define DSC_RC_RANGE_BPG_OFFSETS_1 0x94
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#define DSC_RC_RANGE_BPG_OFFSETS_2 0x98
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/* SDE_DSC_CTL regsiter offsets */
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#define DSC_CTL 0x00
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#define DSC_CFG 0x04
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#define DSC_DATA_IN_SWAP 0x08
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#define DSC_CLK_CTRL 0x0C
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static int _dsc_calc_ob_max_addr(struct sde_hw_dsc *hw_dsc, int num_ss)
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{
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enum sde_dsc idx;
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idx = hw_dsc->idx;
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if ((idx == DSC_0) || (idx == DSC_1)) {
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if (num_ss == 1)
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return 2399;
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else if (num_ss == 2)
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return 1199;
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} else if ((idx == DSC_2) || (idx == DSC_3)) {
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if (num_ss == 1)
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return 1199;
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else if (num_ss == 2)
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return 599;
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}
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return 0;
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}
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static inline int _dsc_subblk_offset(struct sde_hw_dsc *hw_dsc, int s_id,
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u32 *idx)
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{
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const struct sde_dsc_sub_blks *sblk;
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if (!hw_dsc)
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return -EINVAL;
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sblk = hw_dsc->caps->sblk;
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switch (s_id) {
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case SDE_DSC_ENC:
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*idx = sblk->enc.base;
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break;
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case SDE_DSC_CTL:
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*idx = sblk->ctl.base;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static void sde_hw_dsc_disable(struct sde_hw_dsc *hw_dsc)
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{
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struct sde_hw_blk_reg_map *dsc_c;
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u32 idx;
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if (!hw_dsc)
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return;
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if (_dsc_subblk_offset(hw_dsc, SDE_DSC_CTL, &idx))
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return;
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dsc_c = &hw_dsc->hw;
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SDE_REG_WRITE(dsc_c, DSC_CFG + idx, 0);
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if (_dsc_subblk_offset(hw_dsc, SDE_DSC_ENC, &idx))
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return;
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SDE_REG_WRITE(dsc_c, ENC_DF_CTRL + idx, 0);
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SDE_REG_WRITE(dsc_c, DSC_MAIN_CONF + idx, 0);
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}
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static void sde_hw_dsc_config(struct sde_hw_dsc *hw_dsc,
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struct msm_display_dsc_info *dsc, u32 mode,
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bool ich_reset_override)
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{
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struct sde_hw_blk_reg_map *dsc_c;
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u32 idx;
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u32 data = 0;
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u32 slice_count_per_enc;
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if (!hw_dsc || !dsc)
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return;
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if (_dsc_subblk_offset(hw_dsc, SDE_DSC_ENC, &idx))
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return;
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dsc_c = &hw_dsc->hw;
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slice_count_per_enc = dsc->config.slice_count;
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if (mode & DSC_MODE_SPLIT_PANEL)
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data |= BIT(0);
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if (mode & DSC_MODE_MULTIPLEX)
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data |= BIT(1);
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if (dsc->dsc_4hsmerge_en)
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slice_count_per_enc = dsc->config.slice_count >> 2;
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else if ((mode & DSC_MODE_MULTIPLEX) || (dsc->half_panel_pu))
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slice_count_per_enc = dsc->config.slice_count >> 1;
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data |= (slice_count_per_enc & 0x3) << 7;
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SDE_REG_WRITE(dsc_c, DSC_CMN_MAIN_CNF, data);
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data = (dsc->initial_lines & 0xff);
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data |= ((mode & DSC_MODE_VIDEO) ? 1 : 0) << 9;
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if (ich_reset_override)
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data |= 0xC00; // set bit 10 and 11
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data |= (_dsc_calc_ob_max_addr(hw_dsc, slice_count_per_enc) << 18);
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SDE_REG_WRITE(dsc_c, ENC_DF_CTRL + idx, data);
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data = (dsc->config.dsc_version_minor & 0xf) << 28;
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if (dsc->config.dsc_version_minor == 0x2) {
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if (dsc->config.native_422)
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data |= BIT(22);
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if (dsc->config.native_420)
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data |= BIT(21);
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}
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data |= (dsc->config.block_pred_enable ? 1 : 0) << 20;
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data |= (dsc->config.bits_per_pixel << 10);
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data |= (dsc->config.line_buf_depth & 0xf) << 6;
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data |= dsc->config.convert_rgb << 4;
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data |= dsc->config.bits_per_component & 0xf;
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SDE_REG_WRITE(dsc_c, DSC_MAIN_CONF + idx, data);
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data = (dsc->config.pic_width & 0xffff) |
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((dsc->config.pic_height & 0xffff) << 16);
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SDE_REG_WRITE(dsc_c, DSC_PICTURE_SIZE + idx, data);
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data = (dsc->config.slice_width & 0xffff) |
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((dsc->config.slice_height & 0xffff) << 16);
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SDE_REG_WRITE(dsc_c, DSC_SLICE_SIZE + idx, data);
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SDE_REG_WRITE(dsc_c, DSC_MISC_SIZE + idx,
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(dsc->config.slice_chunk_size) & 0xffff);
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data = (dsc->config.initial_xmit_delay & 0xffff) |
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((dsc->config.initial_dec_delay & 0xffff) << 16);
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SDE_REG_WRITE(dsc_c, DSC_HRD_DELAYS + idx, data);
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SDE_REG_WRITE(dsc_c, DSC_RC_SCALE + idx,
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dsc->config.initial_scale_value & 0x3f);
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data = (dsc->config.scale_increment_interval & 0xffff) |
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((dsc->config.scale_decrement_interval & 0x7ff) << 16);
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SDE_REG_WRITE(dsc_c, DSC_RC_SCALE_INC_DEC + idx, data);
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data = (dsc->config.first_line_bpg_offset & 0x1f) |
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((dsc->config.second_line_bpg_offset & 0x1f) << 5);
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SDE_REG_WRITE(dsc_c, DSC_RC_OFFSETS_1 + idx, data);
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data = (dsc->config.nfl_bpg_offset & 0xffff) |
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((dsc->config.slice_bpg_offset & 0xffff) << 16);
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SDE_REG_WRITE(dsc_c, DSC_RC_OFFSETS_2 + idx, data);
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data = (dsc->config.initial_offset & 0xffff) |
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((dsc->config.final_offset & 0xffff) << 16);
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SDE_REG_WRITE(dsc_c, DSC_RC_OFFSETS_3 + idx, data);
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data = (dsc->config.nsl_bpg_offset & 0xffff) |
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((dsc->config.second_line_offset_adj & 0xffff) << 16);
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SDE_REG_WRITE(dsc_c, DSC_RC_OFFSETS_4 + idx, data);
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data = (dsc->config.flatness_min_qp & 0x1f);
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data |= (dsc->config.flatness_max_qp & 0x1f) << 5;
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data |= (dsc->det_thresh_flatness & 0xff) << 10;
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SDE_REG_WRITE(dsc_c, DSC_FLATNESS_QP + idx, data);
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SDE_REG_WRITE(dsc_c, DSC_RC_MODEL_SIZE + idx,
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(dsc->config.rc_model_size) & 0xffff);
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data = dsc->config.rc_edge_factor & 0xf;
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data |= (dsc->config.rc_quant_incr_limit0 & 0x1f) << 8;
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data |= (dsc->config.rc_quant_incr_limit1 & 0x1f) << 13;
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data |= (dsc->config.rc_tgt_offset_high & 0xf) << 20;
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data |= (dsc->config.rc_tgt_offset_low & 0xf) << 24;
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SDE_REG_WRITE(dsc_c, DSC_RC_CONFIG + idx, data);
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/* program the dsc wrapper */
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if (_dsc_subblk_offset(hw_dsc, SDE_DSC_CTL, &idx))
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return;
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data = BIT(0); /* encoder enable */
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if (dsc->config.native_422)
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data |= BIT(8);
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else if (dsc->config.native_420)
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data |= BIT(9);
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if (!dsc->config.convert_rgb)
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data |= BIT(10);
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if (dsc->config.bits_per_component == 8)
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data |= BIT(11);
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if (mode & DSC_MODE_SPLIT_PANEL)
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data |= BIT(12);
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if (mode & DSC_MODE_MULTIPLEX)
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data |= BIT(13);
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if (!(mode & DSC_MODE_VIDEO))
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data |= BIT(17);
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if (dsc->dsc_4hsmerge_en) {
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data |= dsc->dsc_4hsmerge_padding << 18;
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data |= dsc->dsc_4hsmerge_alignment << 22;
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data |= BIT(16);
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}
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SDE_REG_WRITE(dsc_c, DSC_CFG + idx, data);
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}
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static void sde_hw_dsc_config_thresh(struct sde_hw_dsc *hw_dsc,
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struct msm_display_dsc_info *dsc)
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{
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struct sde_hw_blk_reg_map *dsc_c;
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u32 idx, off;
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int i, j = 0;
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struct drm_dsc_rc_range_parameters *rc;
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u32 data = 0, min_qp = 0, max_qp = 0, bpg_off = 0;
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if (!hw_dsc || !dsc)
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return;
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if (_dsc_subblk_offset(hw_dsc, SDE_DSC_ENC, &idx))
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return;
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dsc_c = &hw_dsc->hw;
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rc = dsc->config.rc_range_params;
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off = 0;
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for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
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data |= dsc->config.rc_buf_thresh[i] << (8*j);
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j++;
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if ((j == 4) || (i == DSC_NUM_BUF_RANGES - 2)) {
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SDE_REG_WRITE(dsc_c, DSC_RC_BUF_THRESH_0 + idx + off,
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data);
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off += 4;
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j = 0;
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data = 0;
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}
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}
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off = 0;
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for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
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min_qp |= (rc[i].range_min_qp & 0x1f) << 5*j;
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max_qp |= (rc[i].range_max_qp & 0x1f) << 5*j;
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bpg_off |= (rc[i].range_bpg_offset & 0x3f) << 6*j;
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j++;
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if (j == 5) {
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SDE_REG_WRITE(dsc_c, DSC_RC_MIN_QP_0 + idx + off,
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min_qp);
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SDE_REG_WRITE(dsc_c, DSC_RC_MAX_QP_0 + idx + off,
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max_qp);
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SDE_REG_WRITE(dsc_c,
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DSC_RC_RANGE_BPG_OFFSETS_0 + idx + off,
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bpg_off);
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off += 4;
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j = 0;
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min_qp = 0;
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max_qp = 0;
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bpg_off = 0;
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}
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}
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}
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static void sde_hw_dsc_bind_pingpong_blk(
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struct sde_hw_dsc *hw_dsc,
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bool enable,
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const enum sde_pingpong pp)
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{
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struct sde_hw_blk_reg_map *dsc_c;
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int idx;
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int mux_cfg = 0xF; /* Disabled */
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if (!hw_dsc)
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return;
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if (_dsc_subblk_offset(hw_dsc, SDE_DSC_CTL, &idx))
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return;
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dsc_c = &hw_dsc->hw;
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if (enable)
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mux_cfg = (pp - PINGPONG_0) & 0x7;
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SDE_REG_WRITE(dsc_c, DSC_CTL + idx, mux_cfg);
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}
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void sde_dsc1_2_setup_ops(struct sde_hw_dsc_ops *ops,
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const unsigned long features)
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{
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ops->dsc_disable = sde_hw_dsc_disable;
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ops->dsc_config = sde_hw_dsc_config;
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ops->dsc_config_thresh = sde_hw_dsc_config_thresh;
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ops->bind_pingpong_blk = sde_hw_dsc_bind_pingpong_blk;
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}
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