sde_hw_sspp.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include "sde_hwio.h"
  6. #include "sde_hw_catalog.h"
  7. #include "sde_hw_lm.h"
  8. #include "sde_hw_sspp.h"
  9. #include "sde_hw_color_processing.h"
  10. #include "sde_dbg.h"
  11. #include "sde_kms.h"
  12. #include "sde_hw_reg_dma_v1_color_proc.h"
  13. #define SDE_FETCH_CONFIG_RESET_VALUE 0x00000087
  14. /* SDE_SSPP_SRC */
  15. #define SSPP_SRC_SIZE 0x00
  16. #define SSPP_SRC_XY 0x08
  17. #define SSPP_OUT_SIZE 0x0c
  18. #define SSPP_OUT_XY 0x10
  19. #define SSPP_SRC0_ADDR 0x14
  20. #define SSPP_SRC1_ADDR 0x18
  21. #define SSPP_SRC2_ADDR 0x1C
  22. #define SSPP_SRC3_ADDR 0x20
  23. #define SSPP_SRC_YSTRIDE0 0x24
  24. #define SSPP_SRC_YSTRIDE1 0x28
  25. #define SSPP_SRC_FORMAT 0x30
  26. #define SSPP_SRC_UNPACK_PATTERN 0x34
  27. #define SSPP_SRC_OP_MODE 0x38
  28. /* SSPP_MULTIRECT*/
  29. #define SSPP_SRC_SIZE_REC1 0x16C
  30. #define SSPP_SRC_XY_REC1 0x168
  31. #define SSPP_OUT_SIZE_REC1 0x160
  32. #define SSPP_OUT_XY_REC1 0x164
  33. #define SSPP_SRC_FORMAT_REC1 0x174
  34. #define SSPP_SRC_UNPACK_PATTERN_REC1 0x178
  35. #define SSPP_SRC_OP_MODE_REC1 0x17C
  36. #define SSPP_MULTIRECT_OPMODE 0x170
  37. #define SSPP_SRC_CONSTANT_COLOR_REC1 0x180
  38. #define SSPP_EXCL_REC_SIZE_REC1 0x184
  39. #define SSPP_EXCL_REC_XY_REC1 0x188
  40. #define SSPP_UIDLE_CTRL_VALUE 0x1f0
  41. #define SSPP_UIDLE_CTRL_VALUE_REC1 0x1f4
  42. /* SSPP_DGM */
  43. #define SSPP_DGM_OP_MODE 0x804
  44. #define SSPP_DGM_OP_MODE_REC1 0x1804
  45. #define SSPP_GAMUT_UNMULT_MODE 0x1EA0
  46. #define MDSS_MDP_OP_DEINTERLACE BIT(22)
  47. #define MDSS_MDP_OP_DEINTERLACE_ODD BIT(23)
  48. #define MDSS_MDP_OP_IGC_ROM_1 BIT(18)
  49. #define MDSS_MDP_OP_IGC_ROM_0 BIT(17)
  50. #define MDSS_MDP_OP_IGC_EN BIT(16)
  51. #define MDSS_MDP_OP_FLIP_UD BIT(14)
  52. #define MDSS_MDP_OP_FLIP_LR BIT(13)
  53. #define MDSS_MDP_OP_SPLIT_ORDER BIT(4)
  54. #define MDSS_MDP_OP_BWC_EN BIT(0)
  55. #define MDSS_MDP_OP_PE_OVERRIDE BIT(31)
  56. #define MDSS_MDP_OP_BWC_LOSSLESS (0 << 1)
  57. #define MDSS_MDP_OP_BWC_Q_HIGH (1 << 1)
  58. #define MDSS_MDP_OP_BWC_Q_MED (2 << 1)
  59. #define SSPP_SRC_CONSTANT_COLOR 0x3c
  60. #define SSPP_EXCL_REC_CTL 0x40
  61. #define SSPP_UBWC_STATIC_CTRL 0x44
  62. #define SSPP_FETCH_CONFIG 0x048
  63. #define SSPP_DANGER_LUT 0x60
  64. #define SSPP_SAFE_LUT 0x64
  65. #define SSPP_CREQ_LUT 0x68
  66. #define SSPP_QOS_CTRL 0x6C
  67. #define SSPP_DECIMATION_CONFIG 0xB4
  68. #define SSPP_SRC_ADDR_SW_STATUS 0x70
  69. #define SSPP_CREQ_LUT_0 0x74
  70. #define SSPP_CREQ_LUT_1 0x78
  71. #define SSPP_SW_PIX_EXT_C0_LR 0x100
  72. #define SSPP_SW_PIX_EXT_C0_TB 0x104
  73. #define SSPP_SW_PIX_EXT_C0_REQ_PIXELS 0x108
  74. #define SSPP_SW_PIX_EXT_C1C2_LR 0x110
  75. #define SSPP_SW_PIX_EXT_C1C2_TB 0x114
  76. #define SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS 0x118
  77. #define SSPP_SW_PIX_EXT_C3_LR 0x120
  78. #define SSPP_SW_PIX_EXT_C3_TB 0x124
  79. #define SSPP_SW_PIX_EXT_C3_REQ_PIXELS 0x128
  80. #define SSPP_TRAFFIC_SHAPER 0x130
  81. #define SSPP_CDP_CNTL 0x134
  82. #define SSPP_UBWC_ERROR_STATUS 0x138
  83. #define SSPP_CDP_CNTL_REC1 0x13c
  84. #define SSPP_TRAFFIC_SHAPER_PREFILL 0x150
  85. #define SSPP_TRAFFIC_SHAPER_REC1_PREFILL 0x154
  86. #define SSPP_TRAFFIC_SHAPER_REC1 0x158
  87. #define SSPP_EXCL_REC_SIZE 0x1B4
  88. #define SSPP_EXCL_REC_XY 0x1B8
  89. #define SSPP_VIG_OP_MODE 0x0
  90. #define SSPP_VIG_CSC_10_OP_MODE 0x0
  91. #define SSPP_TRAFFIC_SHAPER_BPC_MAX 0xFF
  92. /* SSPP_QOS_CTRL */
  93. #define SSPP_QOS_CTRL_VBLANK_EN BIT(16)
  94. #define SSPP_QOS_CTRL_DANGER_SAFE_EN BIT(0)
  95. #define SSPP_QOS_CTRL_DANGER_VBLANK_MASK 0x3
  96. #define SSPP_QOS_CTRL_DANGER_VBLANK_OFF 4
  97. #define SSPP_QOS_CTRL_CREQ_VBLANK_MASK 0x3
  98. #define SSPP_QOS_CTRL_CREQ_VBLANK_OFF 20
  99. #define SSPP_SYS_CACHE_MODE 0x1BC
  100. #define SSPP_SBUF_STATUS_PLANE0 0x1C0
  101. #define SSPP_SBUF_STATUS_PLANE1 0x1C4
  102. #define SSPP_SBUF_STATUS_PLANE_EMPTY BIT(16)
  103. /* SDE_SSPP_SCALER_QSEED2 */
  104. #define SCALE_CONFIG 0x04
  105. #define COMP0_3_PHASE_STEP_X 0x10
  106. #define COMP0_3_PHASE_STEP_Y 0x14
  107. #define COMP1_2_PHASE_STEP_X 0x18
  108. #define COMP1_2_PHASE_STEP_Y 0x1c
  109. #define COMP0_3_INIT_PHASE_X 0x20
  110. #define COMP0_3_INIT_PHASE_Y 0x24
  111. #define COMP1_2_INIT_PHASE_X 0x28
  112. #define COMP1_2_INIT_PHASE_Y 0x2C
  113. #define VIG_0_QSEED2_SHARP 0x30
  114. /*
  115. * Definitions for ViG op modes
  116. */
  117. #define VIG_OP_CSC_DST_DATAFMT BIT(19)
  118. #define VIG_OP_CSC_SRC_DATAFMT BIT(18)
  119. #define VIG_OP_CSC_EN BIT(17)
  120. #define VIG_OP_MEM_PROT_CONT BIT(15)
  121. #define VIG_OP_MEM_PROT_VAL BIT(14)
  122. #define VIG_OP_MEM_PROT_SAT BIT(13)
  123. #define VIG_OP_MEM_PROT_HUE BIT(12)
  124. #define VIG_OP_HIST BIT(8)
  125. #define VIG_OP_SKY_COL BIT(7)
  126. #define VIG_OP_FOIL BIT(6)
  127. #define VIG_OP_SKIN_COL BIT(5)
  128. #define VIG_OP_PA_EN BIT(4)
  129. #define VIG_OP_PA_SAT_ZERO_EXP BIT(2)
  130. #define VIG_OP_MEM_PROT_BLEND BIT(1)
  131. /*
  132. * Definitions for CSC 10 op modes
  133. */
  134. #define VIG_CSC_10_SRC_DATAFMT BIT(1)
  135. #define VIG_CSC_10_EN BIT(0)
  136. #define CSC_10BIT_OFFSET 4
  137. #define DGM_CSC_MATRIX_SHIFT 0
  138. /* traffic shaper clock in Hz */
  139. #define TS_CLK 19200000
  140. static inline int _sspp_subblk_offset(struct sde_hw_pipe *ctx,
  141. int s_id,
  142. u32 *idx)
  143. {
  144. int rc = 0;
  145. const struct sde_sspp_sub_blks *sblk;
  146. if (!ctx)
  147. return -EINVAL;
  148. sblk = ctx->cap->sblk;
  149. switch (s_id) {
  150. case SDE_SSPP_SRC:
  151. *idx = sblk->src_blk.base;
  152. break;
  153. case SDE_SSPP_SCALER_QSEED2:
  154. case SDE_SSPP_SCALER_QSEED3:
  155. case SDE_SSPP_SCALER_RGB:
  156. *idx = sblk->scaler_blk.base;
  157. break;
  158. case SDE_SSPP_CSC:
  159. case SDE_SSPP_CSC_10BIT:
  160. *idx = sblk->csc_blk.base;
  161. break;
  162. case SDE_SSPP_HSIC:
  163. *idx = sblk->hsic_blk.base;
  164. break;
  165. case SDE_SSPP_PCC:
  166. *idx = sblk->pcc_blk.base;
  167. break;
  168. case SDE_SSPP_MEMCOLOR:
  169. *idx = sblk->memcolor_blk.base;
  170. break;
  171. default:
  172. rc = -EINVAL;
  173. }
  174. return rc;
  175. }
  176. static void sde_hw_sspp_setup_multirect(struct sde_hw_pipe *ctx,
  177. enum sde_sspp_multirect_index index,
  178. enum sde_sspp_multirect_mode mode)
  179. {
  180. u32 mode_mask;
  181. u32 idx;
  182. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  183. return;
  184. if (index == SDE_SSPP_RECT_SOLO) {
  185. /**
  186. * if rect index is RECT_SOLO, we cannot expect a
  187. * virtual plane sharing the same SSPP id. So we go
  188. * and disable multirect
  189. */
  190. mode_mask = 0;
  191. } else {
  192. mode_mask = SDE_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx);
  193. mode_mask |= index;
  194. if (mode == SDE_SSPP_MULTIRECT_TIME_MX)
  195. mode_mask |= BIT(2);
  196. else
  197. mode_mask &= ~BIT(2);
  198. }
  199. SDE_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask);
  200. }
  201. static void _sspp_setup_opmode(struct sde_hw_pipe *ctx,
  202. u32 mask, u8 en)
  203. {
  204. u32 idx;
  205. u32 opmode;
  206. if (!test_bit(SDE_SSPP_SCALER_QSEED2, &ctx->cap->features) ||
  207. _sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED2, &idx) ||
  208. !test_bit(SDE_SSPP_CSC, &ctx->cap->features))
  209. return;
  210. opmode = SDE_REG_READ(&ctx->hw, SSPP_VIG_OP_MODE + idx);
  211. if (en)
  212. opmode |= mask;
  213. else
  214. opmode &= ~mask;
  215. SDE_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode);
  216. }
  217. static void _sspp_setup_csc10_opmode(struct sde_hw_pipe *ctx,
  218. u32 mask, u8 en)
  219. {
  220. u32 idx;
  221. u32 opmode;
  222. if (_sspp_subblk_offset(ctx, SDE_SSPP_CSC_10BIT, &idx))
  223. return;
  224. opmode = SDE_REG_READ(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx);
  225. if (en)
  226. opmode |= mask;
  227. else
  228. opmode &= ~mask;
  229. SDE_REG_WRITE(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx, opmode);
  230. }
  231. static void sde_hw_sspp_set_src_split_order(struct sde_hw_pipe *ctx,
  232. enum sde_sspp_multirect_index rect_mode, bool enable)
  233. {
  234. struct sde_hw_blk_reg_map *c;
  235. u32 opmode, idx, op_mode_off;
  236. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  237. return;
  238. if (rect_mode == SDE_SSPP_RECT_SOLO || rect_mode == SDE_SSPP_RECT_0)
  239. op_mode_off = SSPP_SRC_OP_MODE;
  240. else
  241. op_mode_off = SSPP_SRC_OP_MODE_REC1;
  242. c = &ctx->hw;
  243. opmode = SDE_REG_READ(c, op_mode_off + idx);
  244. if (enable)
  245. opmode |= MDSS_MDP_OP_SPLIT_ORDER;
  246. else
  247. opmode &= ~MDSS_MDP_OP_SPLIT_ORDER;
  248. SDE_REG_WRITE(c, op_mode_off + idx, opmode);
  249. }
  250. /**
  251. * Setup source pixel format, flip,
  252. */
  253. static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx,
  254. const struct sde_format *fmt,
  255. bool const_alpha_en, u32 flags,
  256. enum sde_sspp_multirect_index rect_mode)
  257. {
  258. struct sde_hw_blk_reg_map *c;
  259. u32 chroma_samp, unpack, src_format;
  260. u32 opmode = 0;
  261. u32 alpha_en_mask = 0, color_en_mask = 0;
  262. u32 op_mode_off, unpack_pat_off, format_off;
  263. u32 idx;
  264. bool const_color_en = true;
  265. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx) || !fmt)
  266. return;
  267. if (rect_mode == SDE_SSPP_RECT_SOLO || rect_mode == SDE_SSPP_RECT_0) {
  268. op_mode_off = SSPP_SRC_OP_MODE;
  269. unpack_pat_off = SSPP_SRC_UNPACK_PATTERN;
  270. format_off = SSPP_SRC_FORMAT;
  271. } else {
  272. op_mode_off = SSPP_SRC_OP_MODE_REC1;
  273. unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1;
  274. format_off = SSPP_SRC_FORMAT_REC1;
  275. }
  276. c = &ctx->hw;
  277. opmode = SDE_REG_READ(c, op_mode_off + idx);
  278. opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD |
  279. MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE);
  280. if (flags & SDE_SSPP_FLIP_LR)
  281. opmode |= MDSS_MDP_OP_FLIP_LR;
  282. if (flags & SDE_SSPP_FLIP_UD)
  283. opmode |= MDSS_MDP_OP_FLIP_UD;
  284. chroma_samp = fmt->chroma_sample;
  285. if (flags & SDE_SSPP_SOURCE_ROTATED_90) {
  286. if (chroma_samp == SDE_CHROMA_H2V1)
  287. chroma_samp = SDE_CHROMA_H1V2;
  288. else if (chroma_samp == SDE_CHROMA_H1V2)
  289. chroma_samp = SDE_CHROMA_H2V1;
  290. }
  291. src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) |
  292. (fmt->bits[C3_ALPHA] << 6) | (fmt->bits[C2_R_Cr] << 4) |
  293. (fmt->bits[C1_B_Cb] << 2) | (fmt->bits[C0_G_Y] << 0);
  294. if (flags & SDE_SSPP_ROT_90)
  295. src_format |= BIT(11); /* ROT90 */
  296. if (fmt->alpha_enable && fmt->fetch_planes == SDE_PLANE_INTERLEAVED)
  297. src_format |= BIT(8); /* SRCC3_EN */
  298. if (flags & SDE_SSPP_SOLID_FILL)
  299. src_format |= BIT(22);
  300. unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) |
  301. (fmt->element[1] << 8) | (fmt->element[0] << 0);
  302. src_format |= ((fmt->unpack_count - 1) << 12) |
  303. (fmt->unpack_tight << 17) |
  304. (fmt->unpack_align_msb << 18) |
  305. ((fmt->bpp - 1) << 9);
  306. if ((flags & SDE_SSPP_ROT_90) && test_bit(SDE_SSPP_INLINE_CONST_CLR,
  307. &ctx->cap->features))
  308. const_color_en = false;
  309. if (fmt->fetch_mode != SDE_FETCH_LINEAR) {
  310. if (SDE_FORMAT_IS_UBWC(fmt))
  311. opmode |= MDSS_MDP_OP_BWC_EN;
  312. src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
  313. SDE_REG_WRITE(c, SSPP_FETCH_CONFIG,
  314. SDE_FETCH_CONFIG_RESET_VALUE |
  315. ctx->mdp->highest_bank_bit << 18);
  316. if (IS_UBWC_40_SUPPORTED(ctx->catalog->ubwc_version)) {
  317. SDE_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
  318. SDE_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
  319. } else if (IS_UBWC_10_SUPPORTED(ctx->catalog->ubwc_version)) {
  320. alpha_en_mask = const_alpha_en ? BIT(31) : 0;
  321. SDE_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
  322. alpha_en_mask | (ctx->mdp->ubwc_swizzle & 0x1) |
  323. BIT(8) | (ctx->mdp->highest_bank_bit << 4));
  324. } else if (IS_UBWC_20_SUPPORTED(ctx->catalog->ubwc_version)) {
  325. alpha_en_mask = const_alpha_en ? BIT(31) : 0;
  326. SDE_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
  327. alpha_en_mask | (ctx->mdp->ubwc_swizzle) |
  328. (ctx->mdp->highest_bank_bit << 4));
  329. } else if (IS_UBWC_30_SUPPORTED(ctx->catalog->ubwc_version)) {
  330. color_en_mask = const_color_en ? BIT(30) : 0;
  331. SDE_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
  332. color_en_mask | (ctx->mdp->ubwc_swizzle) |
  333. (ctx->mdp->highest_bank_bit << 4));
  334. }
  335. }
  336. opmode |= MDSS_MDP_OP_PE_OVERRIDE;
  337. /* if this is YUV pixel format, enable CSC */
  338. if (SDE_FORMAT_IS_YUV(fmt))
  339. src_format |= BIT(15);
  340. if (SDE_FORMAT_IS_DX(fmt))
  341. src_format |= BIT(14);
  342. /* update scaler opmode, if appropriate */
  343. if (test_bit(SDE_SSPP_CSC, &ctx->cap->features))
  344. _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
  345. SDE_FORMAT_IS_YUV(fmt));
  346. else if (test_bit(SDE_SSPP_CSC_10BIT, &ctx->cap->features))
  347. _sspp_setup_csc10_opmode(ctx,
  348. VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
  349. SDE_FORMAT_IS_YUV(fmt));
  350. SDE_REG_WRITE(c, format_off + idx, src_format);
  351. SDE_REG_WRITE(c, unpack_pat_off + idx, unpack);
  352. SDE_REG_WRITE(c, op_mode_off + idx, opmode);
  353. /* clear previous UBWC error */
  354. SDE_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31));
  355. }
  356. static void sde_hw_sspp_clear_ubwc_error(struct sde_hw_pipe *ctx)
  357. {
  358. struct sde_hw_blk_reg_map *c;
  359. c = &ctx->hw;
  360. SDE_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31));
  361. }
  362. static u32 sde_hw_sspp_get_ubwc_error(struct sde_hw_pipe *ctx)
  363. {
  364. struct sde_hw_blk_reg_map *c;
  365. u32 reg_code;
  366. c = &ctx->hw;
  367. reg_code = SDE_REG_READ(c, SSPP_UBWC_ERROR_STATUS);
  368. return reg_code;
  369. }
  370. static void sde_hw_sspp_setup_secure(struct sde_hw_pipe *ctx,
  371. enum sde_sspp_multirect_index rect_mode,
  372. bool enable)
  373. {
  374. struct sde_hw_blk_reg_map *c;
  375. u32 secure = 0, secure_bit_mask;
  376. u32 idx;
  377. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  378. return;
  379. c = &ctx->hw;
  380. if ((rect_mode == SDE_SSPP_RECT_SOLO)
  381. || (rect_mode == SDE_SSPP_RECT_0))
  382. secure_bit_mask =
  383. (rect_mode == SDE_SSPP_RECT_SOLO) ? 0xF : 0x5;
  384. else
  385. secure_bit_mask = 0xA;
  386. secure = SDE_REG_READ(c, SSPP_SRC_ADDR_SW_STATUS + idx);
  387. if (enable)
  388. secure |= secure_bit_mask;
  389. else
  390. secure &= ~secure_bit_mask;
  391. SDE_REG_WRITE(c, SSPP_SRC_ADDR_SW_STATUS + idx, secure);
  392. /* multiple planes share same sw_status register */
  393. wmb();
  394. }
  395. static void sde_hw_sspp_setup_pe_config(struct sde_hw_pipe *ctx,
  396. struct sde_hw_pixel_ext *pe_ext)
  397. {
  398. struct sde_hw_blk_reg_map *c;
  399. u8 color;
  400. u32 lr_pe[4], tb_pe[4], tot_req_pixels[4];
  401. const u32 bytemask = 0xff;
  402. const u32 shortmask = 0xffff;
  403. u32 idx;
  404. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx) || !pe_ext)
  405. return;
  406. c = &ctx->hw;
  407. /* program SW pixel extension override for all pipes*/
  408. for (color = 0; color < SDE_MAX_PLANES; color++) {
  409. /* color 2 has the same set of registers as color 1 */
  410. if (color == 2)
  411. continue;
  412. lr_pe[color] = ((pe_ext->right_ftch[color] & bytemask) << 24)|
  413. ((pe_ext->right_rpt[color] & bytemask) << 16)|
  414. ((pe_ext->left_ftch[color] & bytemask) << 8)|
  415. (pe_ext->left_rpt[color] & bytemask);
  416. tb_pe[color] = ((pe_ext->btm_ftch[color] & bytemask) << 24)|
  417. ((pe_ext->btm_rpt[color] & bytemask) << 16)|
  418. ((pe_ext->top_ftch[color] & bytemask) << 8)|
  419. (pe_ext->top_rpt[color] & bytemask);
  420. tot_req_pixels[color] = (((pe_ext->roi_h[color] +
  421. pe_ext->num_ext_pxls_top[color] +
  422. pe_ext->num_ext_pxls_btm[color]) & shortmask) << 16) |
  423. ((pe_ext->roi_w[color] +
  424. pe_ext->num_ext_pxls_left[color] +
  425. pe_ext->num_ext_pxls_right[color]) & shortmask);
  426. }
  427. /* color 0 */
  428. SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_LR + idx, lr_pe[0]);
  429. SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_TB + idx, tb_pe[0]);
  430. SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_REQ_PIXELS + idx,
  431. tot_req_pixels[0]);
  432. /* color 1 and color 2 */
  433. SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_LR + idx, lr_pe[1]);
  434. SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_TB + idx, tb_pe[1]);
  435. SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS + idx,
  436. tot_req_pixels[1]);
  437. /* color 3 */
  438. SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_LR + idx, lr_pe[3]);
  439. SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_TB + idx, lr_pe[3]);
  440. SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_REQ_PIXELS + idx,
  441. tot_req_pixels[3]);
  442. }
  443. static void _sde_hw_sspp_setup_scaler(struct sde_hw_pipe *ctx,
  444. struct sde_hw_pipe_cfg *sspp,
  445. struct sde_hw_pixel_ext *pe,
  446. void *scaler_cfg)
  447. {
  448. struct sde_hw_blk_reg_map *c;
  449. int config_h = 0x0;
  450. int config_v = 0x0;
  451. u32 idx;
  452. (void)sspp;
  453. (void)scaler_cfg;
  454. if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED2, &idx) || !pe)
  455. return;
  456. c = &ctx->hw;
  457. /* enable scaler(s) if valid filter set */
  458. if (pe->horz_filter[SDE_SSPP_COMP_0] < SDE_SCALE_FILTER_MAX)
  459. config_h |= pe->horz_filter[SDE_SSPP_COMP_0] << 8;
  460. if (pe->horz_filter[SDE_SSPP_COMP_1_2] < SDE_SCALE_FILTER_MAX)
  461. config_h |= pe->horz_filter[SDE_SSPP_COMP_1_2] << 12;
  462. if (pe->horz_filter[SDE_SSPP_COMP_3] < SDE_SCALE_FILTER_MAX)
  463. config_h |= pe->horz_filter[SDE_SSPP_COMP_3] << 16;
  464. if (config_h)
  465. config_h |= BIT(0);
  466. if (pe->vert_filter[SDE_SSPP_COMP_0] < SDE_SCALE_FILTER_MAX)
  467. config_v |= pe->vert_filter[SDE_SSPP_COMP_0] << 10;
  468. if (pe->vert_filter[SDE_SSPP_COMP_1_2] < SDE_SCALE_FILTER_MAX)
  469. config_v |= pe->vert_filter[SDE_SSPP_COMP_1_2] << 14;
  470. if (pe->vert_filter[SDE_SSPP_COMP_3] < SDE_SCALE_FILTER_MAX)
  471. config_v |= pe->vert_filter[SDE_SSPP_COMP_3] << 18;
  472. if (config_v)
  473. config_v |= BIT(1);
  474. SDE_REG_WRITE(c, SCALE_CONFIG + idx, config_h | config_v);
  475. SDE_REG_WRITE(c, COMP0_3_INIT_PHASE_X + idx,
  476. pe->init_phase_x[SDE_SSPP_COMP_0]);
  477. SDE_REG_WRITE(c, COMP0_3_INIT_PHASE_Y + idx,
  478. pe->init_phase_y[SDE_SSPP_COMP_0]);
  479. SDE_REG_WRITE(c, COMP0_3_PHASE_STEP_X + idx,
  480. pe->phase_step_x[SDE_SSPP_COMP_0]);
  481. SDE_REG_WRITE(c, COMP0_3_PHASE_STEP_Y + idx,
  482. pe->phase_step_y[SDE_SSPP_COMP_0]);
  483. SDE_REG_WRITE(c, COMP1_2_INIT_PHASE_X + idx,
  484. pe->init_phase_x[SDE_SSPP_COMP_1_2]);
  485. SDE_REG_WRITE(c, COMP1_2_INIT_PHASE_Y + idx,
  486. pe->init_phase_y[SDE_SSPP_COMP_1_2]);
  487. SDE_REG_WRITE(c, COMP1_2_PHASE_STEP_X + idx,
  488. pe->phase_step_x[SDE_SSPP_COMP_1_2]);
  489. SDE_REG_WRITE(c, COMP1_2_PHASE_STEP_Y + idx,
  490. pe->phase_step_y[SDE_SSPP_COMP_1_2]);
  491. }
  492. static void _sde_hw_sspp_setup_scaler3(struct sde_hw_pipe *ctx,
  493. struct sde_hw_pipe_cfg *sspp,
  494. struct sde_hw_pixel_ext *pe,
  495. void *scaler_cfg)
  496. {
  497. u32 idx;
  498. struct sde_hw_scaler3_cfg *scaler3_cfg = scaler_cfg;
  499. (void)pe;
  500. if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED3, &idx) || !sspp
  501. || !scaler3_cfg || !ctx || !ctx->cap || !ctx->cap->sblk)
  502. return;
  503. sde_hw_setup_scaler3(&ctx->hw, scaler3_cfg,
  504. ctx->cap->sblk->scaler_blk.version, idx, sspp->layout.format);
  505. }
  506. static u32 _sde_hw_sspp_get_scaler3_ver(struct sde_hw_pipe *ctx)
  507. {
  508. u32 idx;
  509. if (!ctx || _sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED3, &idx))
  510. return 0;
  511. return sde_hw_get_scaler3_ver(&ctx->hw, idx);
  512. }
  513. /**
  514. * sde_hw_sspp_setup_rects()
  515. */
  516. static void sde_hw_sspp_setup_rects(struct sde_hw_pipe *ctx,
  517. struct sde_hw_pipe_cfg *cfg,
  518. enum sde_sspp_multirect_index rect_index)
  519. {
  520. struct sde_hw_blk_reg_map *c;
  521. u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
  522. u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
  523. u32 decimation = 0;
  524. u32 idx;
  525. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx) || !cfg)
  526. return;
  527. c = &ctx->hw;
  528. if (rect_index == SDE_SSPP_RECT_SOLO || rect_index == SDE_SSPP_RECT_0) {
  529. src_size_off = SSPP_SRC_SIZE;
  530. src_xy_off = SSPP_SRC_XY;
  531. out_size_off = SSPP_OUT_SIZE;
  532. out_xy_off = SSPP_OUT_XY;
  533. } else {
  534. src_size_off = SSPP_SRC_SIZE_REC1;
  535. src_xy_off = SSPP_SRC_XY_REC1;
  536. out_size_off = SSPP_OUT_SIZE_REC1;
  537. out_xy_off = SSPP_OUT_XY_REC1;
  538. }
  539. /* src and dest rect programming */
  540. src_xy = (cfg->src_rect.y << 16) | (cfg->src_rect.x);
  541. src_size = (cfg->src_rect.h << 16) | (cfg->src_rect.w);
  542. dst_xy = (cfg->dst_rect.y << 16) | (cfg->dst_rect.x);
  543. dst_size = (cfg->dst_rect.h << 16) | (cfg->dst_rect.w);
  544. if (rect_index == SDE_SSPP_RECT_SOLO) {
  545. ystride0 = (cfg->layout.plane_pitch[0]) |
  546. (cfg->layout.plane_pitch[1] << 16);
  547. ystride1 = (cfg->layout.plane_pitch[2]) |
  548. (cfg->layout.plane_pitch[3] << 16);
  549. } else {
  550. ystride0 = SDE_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx);
  551. ystride1 = SDE_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx);
  552. if (rect_index == SDE_SSPP_RECT_0) {
  553. ystride0 = (ystride0 & 0xFFFF0000) |
  554. (cfg->layout.plane_pitch[0] & 0x0000FFFF);
  555. ystride1 = (ystride1 & 0xFFFF0000)|
  556. (cfg->layout.plane_pitch[2] & 0x0000FFFF);
  557. } else {
  558. ystride0 = (ystride0 & 0x0000FFFF) |
  559. ((cfg->layout.plane_pitch[0] << 16) &
  560. 0xFFFF0000);
  561. ystride1 = (ystride1 & 0x0000FFFF) |
  562. ((cfg->layout.plane_pitch[2] << 16) &
  563. 0xFFFF0000);
  564. }
  565. }
  566. /* program scaler, phase registers, if pipes supporting scaling */
  567. if (ctx->cap->features & SDE_SSPP_SCALER) {
  568. /* program decimation */
  569. decimation = ((1 << cfg->horz_decimation) - 1) << 8;
  570. decimation |= ((1 << cfg->vert_decimation) - 1);
  571. }
  572. /* rectangle register programming */
  573. SDE_REG_WRITE(c, src_size_off + idx, src_size);
  574. SDE_REG_WRITE(c, src_xy_off + idx, src_xy);
  575. SDE_REG_WRITE(c, out_size_off + idx, dst_size);
  576. SDE_REG_WRITE(c, out_xy_off + idx, dst_xy);
  577. SDE_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0);
  578. SDE_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
  579. SDE_REG_WRITE(c, SSPP_DECIMATION_CONFIG + idx, decimation);
  580. }
  581. /**
  582. * _sde_hw_sspp_setup_excl_rect() - set exclusion rect configs
  583. * @ctx: Pointer to pipe context
  584. * @excl_rect: Exclusion rect configs
  585. */
  586. static void _sde_hw_sspp_setup_excl_rect(struct sde_hw_pipe *ctx,
  587. struct sde_rect *excl_rect,
  588. enum sde_sspp_multirect_index rect_index)
  589. {
  590. struct sde_hw_blk_reg_map *c;
  591. u32 size, xy;
  592. u32 idx;
  593. u32 reg_xy, reg_size;
  594. u32 excl_ctrl = BIT(0);
  595. u32 enable_bit;
  596. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx) || !excl_rect)
  597. return;
  598. if (rect_index == SDE_SSPP_RECT_0 || rect_index == SDE_SSPP_RECT_SOLO) {
  599. reg_xy = SSPP_EXCL_REC_XY;
  600. reg_size = SSPP_EXCL_REC_SIZE;
  601. enable_bit = BIT(0);
  602. } else {
  603. reg_xy = SSPP_EXCL_REC_XY_REC1;
  604. reg_size = SSPP_EXCL_REC_SIZE_REC1;
  605. enable_bit = BIT(1);
  606. }
  607. c = &ctx->hw;
  608. xy = (excl_rect->y << 16) | (excl_rect->x);
  609. size = (excl_rect->h << 16) | (excl_rect->w);
  610. /* Set if multi-rect disabled, read+modify only if multi-rect enabled */
  611. if (rect_index != SDE_SSPP_RECT_SOLO)
  612. excl_ctrl = SDE_REG_READ(c, SSPP_EXCL_REC_CTL + idx);
  613. if (!size) {
  614. SDE_REG_WRITE(c, SSPP_EXCL_REC_CTL + idx,
  615. excl_ctrl & ~enable_bit);
  616. } else {
  617. SDE_REG_WRITE(c, SSPP_EXCL_REC_CTL + idx,
  618. excl_ctrl | enable_bit);
  619. SDE_REG_WRITE(c, reg_size + idx, size);
  620. SDE_REG_WRITE(c, reg_xy + idx, xy);
  621. }
  622. }
  623. static void sde_hw_sspp_setup_sourceaddress(struct sde_hw_pipe *ctx,
  624. struct sde_hw_pipe_cfg *cfg,
  625. enum sde_sspp_multirect_index rect_mode)
  626. {
  627. int i;
  628. u32 idx;
  629. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  630. return;
  631. if (rect_mode == SDE_SSPP_RECT_SOLO) {
  632. for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
  633. SDE_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4,
  634. cfg->layout.plane_addr[i]);
  635. } else if (rect_mode == SDE_SSPP_RECT_0) {
  636. SDE_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx,
  637. cfg->layout.plane_addr[0]);
  638. SDE_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx,
  639. cfg->layout.plane_addr[2]);
  640. } else {
  641. SDE_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx,
  642. cfg->layout.plane_addr[0]);
  643. SDE_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
  644. cfg->layout.plane_addr[2]);
  645. }
  646. }
  647. u32 sde_hw_sspp_get_source_addr(struct sde_hw_pipe *ctx, bool is_virtual)
  648. {
  649. u32 idx;
  650. u32 offset = 0;
  651. if (!ctx || _sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  652. return 0;
  653. offset = is_virtual ? (SSPP_SRC1_ADDR + idx) : (SSPP_SRC0_ADDR + idx);
  654. return SDE_REG_READ(&ctx->hw, offset);
  655. }
  656. static void sde_hw_sspp_setup_csc(struct sde_hw_pipe *ctx,
  657. struct sde_csc_cfg *data)
  658. {
  659. u32 idx;
  660. bool csc10 = false;
  661. if (_sspp_subblk_offset(ctx, SDE_SSPP_CSC, &idx) || !data)
  662. return;
  663. if (test_bit(SDE_SSPP_CSC_10BIT, &ctx->cap->features)) {
  664. idx += CSC_10BIT_OFFSET;
  665. csc10 = true;
  666. }
  667. sde_hw_csc_setup(&ctx->hw, idx, data, csc10);
  668. }
  669. static void sde_hw_sspp_setup_sharpening(struct sde_hw_pipe *ctx,
  670. struct sde_hw_sharp_cfg *cfg)
  671. {
  672. struct sde_hw_blk_reg_map *c;
  673. u32 idx;
  674. if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED2, &idx) || !cfg ||
  675. !test_bit(SDE_SSPP_SCALER_QSEED2, &ctx->cap->features))
  676. return;
  677. c = &ctx->hw;
  678. SDE_REG_WRITE(c, VIG_0_QSEED2_SHARP + idx, cfg->strength);
  679. SDE_REG_WRITE(c, VIG_0_QSEED2_SHARP + idx + 0x4, cfg->edge_thr);
  680. SDE_REG_WRITE(c, VIG_0_QSEED2_SHARP + idx + 0x8, cfg->smooth_thr);
  681. SDE_REG_WRITE(c, VIG_0_QSEED2_SHARP + idx + 0xC, cfg->noise_thr);
  682. }
  683. static void sde_hw_sspp_setup_solidfill(struct sde_hw_pipe *ctx, u32 color, enum
  684. sde_sspp_multirect_index rect_index)
  685. {
  686. u32 idx;
  687. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  688. return;
  689. if (rect_index == SDE_SSPP_RECT_SOLO || rect_index == SDE_SSPP_RECT_0)
  690. SDE_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color);
  691. else
  692. SDE_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1 + idx,
  693. color);
  694. }
  695. static void sde_hw_sspp_setup_danger_safe_lut(struct sde_hw_pipe *ctx,
  696. struct sde_hw_pipe_qos_cfg *cfg)
  697. {
  698. u32 idx;
  699. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  700. return;
  701. SDE_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, cfg->danger_lut);
  702. SDE_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, cfg->safe_lut);
  703. }
  704. static void sde_hw_sspp_setup_creq_lut(struct sde_hw_pipe *ctx,
  705. struct sde_hw_pipe_qos_cfg *cfg)
  706. {
  707. u32 idx;
  708. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  709. return;
  710. if (ctx->cap && test_bit(SDE_PERF_SSPP_QOS_8LVL,
  711. &ctx->cap->perf_features)) {
  712. SDE_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, cfg->creq_lut);
  713. SDE_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_1 + idx,
  714. cfg->creq_lut >> 32);
  715. } else {
  716. SDE_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, cfg->creq_lut);
  717. }
  718. }
  719. static void sde_hw_sspp_setup_qos_ctrl(struct sde_hw_pipe *ctx,
  720. struct sde_hw_pipe_qos_cfg *cfg)
  721. {
  722. u32 idx;
  723. u32 qos_ctrl = 0;
  724. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  725. return;
  726. if (cfg->vblank_en) {
  727. qos_ctrl |= ((cfg->creq_vblank &
  728. SSPP_QOS_CTRL_CREQ_VBLANK_MASK) <<
  729. SSPP_QOS_CTRL_CREQ_VBLANK_OFF);
  730. qos_ctrl |= ((cfg->danger_vblank &
  731. SSPP_QOS_CTRL_DANGER_VBLANK_MASK) <<
  732. SSPP_QOS_CTRL_DANGER_VBLANK_OFF);
  733. qos_ctrl |= SSPP_QOS_CTRL_VBLANK_EN;
  734. }
  735. if (cfg->danger_safe_en)
  736. qos_ctrl |= SSPP_QOS_CTRL_DANGER_SAFE_EN;
  737. SDE_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl);
  738. }
  739. static void sde_hw_sspp_setup_ts_prefill(struct sde_hw_pipe *ctx,
  740. struct sde_hw_pipe_ts_cfg *cfg,
  741. enum sde_sspp_multirect_index index)
  742. {
  743. u32 idx;
  744. u32 ts_offset, ts_prefill_offset;
  745. u32 ts_count = 0, ts_bytes = 0;
  746. const struct sde_sspp_cfg *cap;
  747. if (!ctx || !cfg || !ctx->cap)
  748. return;
  749. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  750. return;
  751. cap = ctx->cap;
  752. if ((index == SDE_SSPP_RECT_SOLO || index == SDE_SSPP_RECT_0) &&
  753. test_bit(SDE_PERF_SSPP_TS_PREFILL,
  754. &cap->perf_features)) {
  755. ts_offset = SSPP_TRAFFIC_SHAPER;
  756. ts_prefill_offset = SSPP_TRAFFIC_SHAPER_PREFILL;
  757. } else if (index == SDE_SSPP_RECT_1 &&
  758. test_bit(SDE_PERF_SSPP_TS_PREFILL_REC1,
  759. &cap->perf_features)) {
  760. ts_offset = SSPP_TRAFFIC_SHAPER_REC1;
  761. ts_prefill_offset = SSPP_TRAFFIC_SHAPER_REC1_PREFILL;
  762. } else {
  763. pr_err("%s: unexpected idx:%d\n", __func__, index);
  764. return;
  765. }
  766. if (cfg->time) {
  767. u64 temp = DIV_ROUND_UP_ULL(TS_CLK * 1000000ULL, cfg->time);
  768. ts_bytes = temp * cfg->size;
  769. if (ts_bytes > SSPP_TRAFFIC_SHAPER_BPC_MAX)
  770. ts_bytes = SSPP_TRAFFIC_SHAPER_BPC_MAX;
  771. }
  772. if (ts_bytes) {
  773. ts_count = DIV_ROUND_UP_ULL(cfg->size, ts_bytes);
  774. ts_bytes |= BIT(31) | BIT(27);
  775. }
  776. SDE_REG_WRITE(&ctx->hw, ts_offset, ts_bytes);
  777. SDE_REG_WRITE(&ctx->hw, ts_prefill_offset, ts_count);
  778. }
  779. static void sde_hw_sspp_setup_cdp(struct sde_hw_pipe *ctx,
  780. struct sde_hw_pipe_cdp_cfg *cfg,
  781. enum sde_sspp_multirect_index index)
  782. {
  783. u32 idx;
  784. u32 cdp_cntl = 0;
  785. u32 cdp_cntl_offset = 0;
  786. if (!ctx || !cfg)
  787. return;
  788. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  789. return;
  790. if (index == SDE_SSPP_RECT_SOLO || index == SDE_SSPP_RECT_0) {
  791. cdp_cntl_offset = SSPP_CDP_CNTL;
  792. } else if (index == SDE_SSPP_RECT_1) {
  793. cdp_cntl_offset = SSPP_CDP_CNTL_REC1;
  794. } else {
  795. pr_err("%s: unexpected idx:%d\n", __func__, index);
  796. return;
  797. }
  798. if (cfg->enable)
  799. cdp_cntl |= BIT(0);
  800. if (cfg->ubwc_meta_enable)
  801. cdp_cntl |= BIT(1);
  802. if (cfg->tile_amortize_enable)
  803. cdp_cntl |= BIT(2);
  804. if (cfg->preload_ahead == SDE_SSPP_CDP_PRELOAD_AHEAD_64)
  805. cdp_cntl |= BIT(3);
  806. SDE_REG_WRITE(&ctx->hw, cdp_cntl_offset, cdp_cntl);
  807. }
  808. static void sde_hw_sspp_setup_sys_cache(struct sde_hw_pipe *ctx,
  809. struct sde_hw_pipe_sc_cfg *cfg)
  810. {
  811. u32 idx, val;
  812. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  813. return;
  814. if (!cfg)
  815. return;
  816. val = SDE_REG_READ(&ctx->hw, SSPP_SYS_CACHE_MODE + idx);
  817. if (cfg->flags & SSPP_SYS_CACHE_EN_FLAG)
  818. val = (val & ~BIT(15)) | ((cfg->rd_en & 0x1) << 15);
  819. if (cfg->flags & SSPP_SYS_CACHE_SCID)
  820. val = (val & ~0x1F00) | ((cfg->rd_scid & 0x1f) << 8);
  821. if (cfg->flags & SSPP_SYS_CACHE_OP_MODE)
  822. val = (val & ~0xC0000) | ((cfg->op_mode & 0x3) << 18);
  823. if (cfg->flags & SSPP_SYS_CACHE_OP_TYPE)
  824. val = (val & ~0xF) | ((cfg->rd_op_type & 0xf) << 0);
  825. if (cfg->flags & SSPP_SYS_CACHE_NO_ALLOC)
  826. val = (val & ~0x10) | ((cfg->rd_noallocate & 0x1) << 4);
  827. SDE_REG_WRITE(&ctx->hw, SSPP_SYS_CACHE_MODE + idx, val);
  828. }
  829. static void sde_hw_sspp_setup_uidle(struct sde_hw_pipe *ctx,
  830. struct sde_hw_pipe_uidle_cfg *cfg,
  831. enum sde_sspp_multirect_index index)
  832. {
  833. u32 idx, val;
  834. u32 offset;
  835. if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
  836. return;
  837. if (index == SDE_SSPP_RECT_1)
  838. offset = SSPP_UIDLE_CTRL_VALUE_REC1;
  839. else
  840. offset = SSPP_UIDLE_CTRL_VALUE;
  841. val = SDE_REG_READ(&ctx->hw, offset + idx);
  842. val = (val & ~BIT(31)) | (cfg->enable ? 0x0 : BIT(31));
  843. val = (val & ~0xFF00000) | (cfg->fal_allowed_threshold << 20);
  844. val = (val & ~0xF0000) | (cfg->fal10_exit_threshold << 16);
  845. val = (val & ~0xF00) | (cfg->fal10_threshold << 8);
  846. val = (val & ~0xF) | (cfg->fal1_threshold << 0);
  847. SDE_REG_WRITE(&ctx->hw, offset + idx, val);
  848. }
  849. static void _setup_layer_ops_colorproc(struct sde_hw_pipe *c,
  850. unsigned long features, bool is_virtual_pipe)
  851. {
  852. int ret = 0;
  853. if (is_virtual_pipe) {
  854. features &=
  855. ~(BIT(SDE_SSPP_VIG_IGC) | BIT(SDE_SSPP_VIG_GAMUT));
  856. c->cap->features = features;
  857. }
  858. if (test_bit(SDE_SSPP_HSIC, &features)) {
  859. if (c->cap->sblk->hsic_blk.version ==
  860. (SDE_COLOR_PROCESS_VER(0x1, 0x7))) {
  861. c->ops.setup_pa_hue = sde_setup_pipe_pa_hue_v1_7;
  862. c->ops.setup_pa_sat = sde_setup_pipe_pa_sat_v1_7;
  863. c->ops.setup_pa_val = sde_setup_pipe_pa_val_v1_7;
  864. c->ops.setup_pa_cont = sde_setup_pipe_pa_cont_v1_7;
  865. }
  866. }
  867. if (test_bit(SDE_SSPP_MEMCOLOR, &features)) {
  868. if (c->cap->sblk->memcolor_blk.version ==
  869. (SDE_COLOR_PROCESS_VER(0x1, 0x7)))
  870. c->ops.setup_pa_memcolor =
  871. sde_setup_pipe_pa_memcol_v1_7;
  872. }
  873. if (test_bit(SDE_SSPP_VIG_GAMUT, &features)) {
  874. if (c->cap->sblk->gamut_blk.version ==
  875. (SDE_COLOR_PROCESS_VER(0x5, 0x0))) {
  876. ret = reg_dmav1_init_sspp_op_v4(SDE_SSPP_VIG_GAMUT,
  877. c->idx);
  878. if (!ret)
  879. c->ops.setup_vig_gamut =
  880. reg_dmav1_setup_vig_gamutv5;
  881. else
  882. c->ops.setup_vig_gamut = NULL;
  883. }
  884. if (c->cap->sblk->gamut_blk.version ==
  885. (SDE_COLOR_PROCESS_VER(0x6, 0x0))) {
  886. ret = reg_dmav1_init_sspp_op_v4(SDE_SSPP_VIG_GAMUT,
  887. c->idx);
  888. if (!ret)
  889. c->ops.setup_vig_gamut =
  890. reg_dmav1_setup_vig_gamutv6;
  891. else
  892. c->ops.setup_vig_gamut = NULL;
  893. }
  894. }
  895. if (test_bit(SDE_SSPP_VIG_IGC, &features)) {
  896. if (c->cap->sblk->igc_blk[0].version ==
  897. (SDE_COLOR_PROCESS_VER(0x5, 0x0))) {
  898. ret = reg_dmav1_init_sspp_op_v4(SDE_SSPP_VIG_IGC,
  899. c->idx);
  900. if (!ret)
  901. c->ops.setup_vig_igc =
  902. reg_dmav1_setup_vig_igcv5;
  903. else
  904. c->ops.setup_vig_igc = NULL;
  905. }
  906. if (c->cap->sblk->igc_blk[0].version ==
  907. (SDE_COLOR_PROCESS_VER(0x6, 0x0))) {
  908. ret = reg_dmav1_init_sspp_op_v4(SDE_SSPP_VIG_IGC,
  909. c->idx);
  910. if (!ret)
  911. c->ops.setup_vig_igc =
  912. reg_dmav1_setup_vig_igcv6;
  913. else
  914. c->ops.setup_vig_igc = NULL;
  915. }
  916. }
  917. if (test_bit(SDE_SSPP_DMA_IGC, &features)) {
  918. if (c->cap->sblk->igc_blk[0].version ==
  919. (SDE_COLOR_PROCESS_VER(0x5, 0x0))) {
  920. ret = reg_dmav1_init_sspp_op_v4(SDE_SSPP_DMA_IGC,
  921. c->idx);
  922. if (!ret)
  923. c->ops.setup_dma_igc =
  924. reg_dmav1_setup_dma_igcv5;
  925. else
  926. c->ops.setup_dma_igc = NULL;
  927. }
  928. }
  929. if (test_bit(SDE_SSPP_DMA_GC, &features)) {
  930. if (c->cap->sblk->gc_blk[0].version ==
  931. (SDE_COLOR_PROCESS_VER(0x5, 0x0))) {
  932. ret = reg_dmav1_init_sspp_op_v4(SDE_SSPP_DMA_GC,
  933. c->idx);
  934. if (!ret)
  935. c->ops.setup_dma_gc =
  936. reg_dmav1_setup_dma_gcv5;
  937. else
  938. c->ops.setup_dma_gc = NULL;
  939. }
  940. }
  941. }
  942. static void sde_hw_sspp_setup_inverse_pma(struct sde_hw_pipe *ctx,
  943. enum sde_sspp_multirect_index index, u32 enable)
  944. {
  945. u32 op_mode = 0;
  946. if (!ctx || (index == SDE_SSPP_RECT_1))
  947. return;
  948. if (enable)
  949. op_mode |= BIT(0);
  950. SDE_REG_WRITE(&ctx->hw, SSPP_GAMUT_UNMULT_MODE, op_mode);
  951. }
  952. static void sde_hw_sspp_setup_dgm_inverse_pma(struct sde_hw_pipe *ctx,
  953. enum sde_sspp_multirect_index index, u32 enable)
  954. {
  955. u32 offset = SSPP_DGM_OP_MODE;
  956. u32 op_mode = 0;
  957. if (!ctx)
  958. return;
  959. if (index == SDE_SSPP_RECT_1)
  960. offset = SSPP_DGM_OP_MODE_REC1;
  961. op_mode = SDE_REG_READ(&ctx->hw, offset);
  962. if (enable)
  963. op_mode |= BIT(0);
  964. else
  965. op_mode &= ~BIT(0);
  966. SDE_REG_WRITE(&ctx->hw, offset, op_mode);
  967. }
  968. static void sde_hw_sspp_setup_dgm_csc(struct sde_hw_pipe *ctx,
  969. enum sde_sspp_multirect_index index, struct sde_csc_cfg *data)
  970. {
  971. u32 idx = 0;
  972. u32 offset;
  973. u32 op_mode = 0;
  974. const struct sde_sspp_sub_blks *sblk;
  975. if (!ctx || !ctx->cap || !ctx->cap->sblk)
  976. return;
  977. sblk = ctx->cap->sblk;
  978. if (index == SDE_SSPP_RECT_1)
  979. idx = 1;
  980. offset = sblk->dgm_csc_blk[idx].base;
  981. if (data) {
  982. op_mode |= BIT(0);
  983. sde_hw_csc_matrix_coeff_setup(&ctx->hw,
  984. offset + CSC_10BIT_OFFSET, data, DGM_CSC_MATRIX_SHIFT);
  985. }
  986. SDE_REG_WRITE(&ctx->hw, offset, op_mode);
  987. }
  988. static void _setup_layer_ops(struct sde_hw_pipe *c,
  989. unsigned long features, unsigned long perf_features,
  990. bool is_virtual_pipe)
  991. {
  992. int ret;
  993. if (test_bit(SDE_SSPP_SRC, &features)) {
  994. c->ops.setup_format = sde_hw_sspp_setup_format;
  995. c->ops.setup_rects = sde_hw_sspp_setup_rects;
  996. c->ops.setup_sourceaddress = sde_hw_sspp_setup_sourceaddress;
  997. c->ops.get_sourceaddress = sde_hw_sspp_get_source_addr;
  998. c->ops.setup_solidfill = sde_hw_sspp_setup_solidfill;
  999. c->ops.setup_pe = sde_hw_sspp_setup_pe_config;
  1000. c->ops.setup_secure_address = sde_hw_sspp_setup_secure;
  1001. c->ops.set_src_split_order = sde_hw_sspp_set_src_split_order;
  1002. }
  1003. if (test_bit(SDE_SSPP_EXCL_RECT, &features))
  1004. c->ops.setup_excl_rect = _sde_hw_sspp_setup_excl_rect;
  1005. if (test_bit(SDE_PERF_SSPP_QOS, &features)) {
  1006. c->ops.setup_danger_safe_lut =
  1007. sde_hw_sspp_setup_danger_safe_lut;
  1008. c->ops.setup_creq_lut = sde_hw_sspp_setup_creq_lut;
  1009. c->ops.setup_qos_ctrl = sde_hw_sspp_setup_qos_ctrl;
  1010. }
  1011. if (test_bit(SDE_PERF_SSPP_TS_PREFILL, &perf_features))
  1012. c->ops.setup_ts_prefill = sde_hw_sspp_setup_ts_prefill;
  1013. if (test_bit(SDE_SSPP_CSC, &features) ||
  1014. test_bit(SDE_SSPP_CSC_10BIT, &features))
  1015. c->ops.setup_csc = sde_hw_sspp_setup_csc;
  1016. if (test_bit(SDE_SSPP_DGM_CSC, &features))
  1017. c->ops.setup_dgm_csc = sde_hw_sspp_setup_dgm_csc;
  1018. if (test_bit(SDE_SSPP_SCALER_QSEED2, &features)) {
  1019. c->ops.setup_sharpening = sde_hw_sspp_setup_sharpening;
  1020. c->ops.setup_scaler = _sde_hw_sspp_setup_scaler;
  1021. }
  1022. if (sde_hw_sspp_multirect_enabled(c->cap))
  1023. c->ops.setup_multirect = sde_hw_sspp_setup_multirect;
  1024. if (test_bit(SDE_SSPP_SCALER_QSEED3, &features) ||
  1025. test_bit(SDE_SSPP_SCALER_QSEED3LITE, &features)) {
  1026. c->ops.setup_scaler = _sde_hw_sspp_setup_scaler3;
  1027. c->ops.get_scaler_ver = _sde_hw_sspp_get_scaler3_ver;
  1028. c->ops.setup_scaler_lut = is_qseed3_rev_qseed3lite(
  1029. c->catalog) ? reg_dmav1_setup_scaler3lite_lut
  1030. : reg_dmav1_setup_scaler3_lut;
  1031. ret = reg_dmav1_init_sspp_op_v4(is_qseed3_rev_qseed3lite(
  1032. c->catalog) ? SDE_SSPP_SCALER_QSEED3LITE
  1033. : SDE_SSPP_SCALER_QSEED3, c->idx);
  1034. if (!ret)
  1035. c->ops.setup_scaler = reg_dmav1_setup_vig_qseed3;
  1036. }
  1037. if (test_bit(SDE_PERF_SSPP_SYS_CACHE, &perf_features))
  1038. c->ops.setup_sys_cache = sde_hw_sspp_setup_sys_cache;
  1039. if (test_bit(SDE_PERF_SSPP_CDP, &perf_features))
  1040. c->ops.setup_cdp = sde_hw_sspp_setup_cdp;
  1041. if (test_bit(SDE_PERF_SSPP_UIDLE, &perf_features))
  1042. c->ops.setup_uidle = sde_hw_sspp_setup_uidle;
  1043. _setup_layer_ops_colorproc(c, features, is_virtual_pipe);
  1044. if (test_bit(SDE_SSPP_DGM_INVERSE_PMA, &features))
  1045. c->ops.setup_inverse_pma = sde_hw_sspp_setup_dgm_inverse_pma;
  1046. else if (test_bit(SDE_SSPP_INVERSE_PMA, &features))
  1047. c->ops.setup_inverse_pma = sde_hw_sspp_setup_inverse_pma;
  1048. c->ops.get_ubwc_error = sde_hw_sspp_get_ubwc_error;
  1049. c->ops.clear_ubwc_error = sde_hw_sspp_clear_ubwc_error;
  1050. }
  1051. static struct sde_sspp_cfg *_sspp_offset(enum sde_sspp sspp,
  1052. void __iomem *addr,
  1053. struct sde_mdss_cfg *catalog,
  1054. struct sde_hw_blk_reg_map *b)
  1055. {
  1056. int i;
  1057. struct sde_sspp_cfg *cfg;
  1058. if ((sspp < SSPP_MAX) && catalog && addr && b) {
  1059. for (i = 0; i < catalog->sspp_count; i++) {
  1060. if (sspp == catalog->sspp[i].id) {
  1061. b->base_off = addr;
  1062. b->blk_off = catalog->sspp[i].base;
  1063. b->length = catalog->sspp[i].len;
  1064. b->hwversion = catalog->hwversion;
  1065. b->log_mask = SDE_DBG_MASK_SSPP;
  1066. /* Only shallow copy is needed */
  1067. cfg = kmemdup(&catalog->sspp[i], sizeof(*cfg),
  1068. GFP_KERNEL);
  1069. if (!cfg)
  1070. return ERR_PTR(-ENOMEM);
  1071. return cfg;
  1072. }
  1073. }
  1074. }
  1075. return ERR_PTR(-ENOMEM);
  1076. }
  1077. static struct sde_hw_blk_ops sde_hw_ops = {
  1078. .start = NULL,
  1079. .stop = NULL,
  1080. };
  1081. struct sde_hw_pipe *sde_hw_sspp_init(enum sde_sspp idx,
  1082. void __iomem *addr, struct sde_mdss_cfg *catalog,
  1083. bool is_virtual_pipe)
  1084. {
  1085. struct sde_hw_pipe *hw_pipe;
  1086. struct sde_sspp_cfg *cfg;
  1087. int rc;
  1088. if (!addr || !catalog)
  1089. return ERR_PTR(-EINVAL);
  1090. hw_pipe = kzalloc(sizeof(*hw_pipe), GFP_KERNEL);
  1091. if (!hw_pipe)
  1092. return ERR_PTR(-ENOMEM);
  1093. cfg = _sspp_offset(idx, addr, catalog, &hw_pipe->hw);
  1094. if (IS_ERR_OR_NULL(cfg)) {
  1095. kfree(hw_pipe);
  1096. return ERR_PTR(-EINVAL);
  1097. }
  1098. /* Assign ops */
  1099. hw_pipe->catalog = catalog;
  1100. hw_pipe->mdp = &catalog->mdp[0];
  1101. hw_pipe->idx = idx;
  1102. hw_pipe->cap = cfg;
  1103. _setup_layer_ops(hw_pipe, hw_pipe->cap->features,
  1104. hw_pipe->cap->perf_features, is_virtual_pipe);
  1105. if (hw_pipe->ops.get_scaler_ver) {
  1106. sde_init_scaler_blk(&hw_pipe->cap->sblk->scaler_blk,
  1107. hw_pipe->ops.get_scaler_ver(hw_pipe));
  1108. }
  1109. rc = sde_hw_blk_init(&hw_pipe->base, SDE_HW_BLK_SSPP, idx, &sde_hw_ops);
  1110. if (rc) {
  1111. SDE_ERROR("failed to init hw blk %d\n", rc);
  1112. goto blk_init_error;
  1113. }
  1114. if (!is_virtual_pipe)
  1115. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name,
  1116. hw_pipe->hw.blk_off,
  1117. hw_pipe->hw.blk_off + hw_pipe->hw.length,
  1118. hw_pipe->hw.xin_id);
  1119. if (cfg->sblk->scaler_blk.len && !is_virtual_pipe)
  1120. sde_dbg_reg_register_dump_range(SDE_DBG_NAME,
  1121. cfg->sblk->scaler_blk.name,
  1122. hw_pipe->hw.blk_off + cfg->sblk->scaler_blk.base,
  1123. hw_pipe->hw.blk_off + cfg->sblk->scaler_blk.base +
  1124. cfg->sblk->scaler_blk.len,
  1125. hw_pipe->hw.xin_id);
  1126. return hw_pipe;
  1127. blk_init_error:
  1128. kzfree(hw_pipe);
  1129. return ERR_PTR(rc);
  1130. }
  1131. void sde_hw_sspp_destroy(struct sde_hw_pipe *ctx)
  1132. {
  1133. if (ctx) {
  1134. sde_hw_blk_destroy(&ctx->base);
  1135. reg_dmav1_deinit_sspp_ops(ctx->idx);
  1136. kfree(ctx->cap);
  1137. }
  1138. kfree(ctx);
  1139. }