sdx-port-config.h 2.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _LAHAINA_PORT_CONFIG
  6. #define _LAHAINA_PORT_CONFIG
  7. #include <soc/swr-common.h>
  8. #define WSA_MSTR_PORT_MASK 0xFF
  9. /*
  10. * Add port configuration in the format
  11. *{ si, off1, off2, hstart, hstop, wd_len, bp_mode, bgp_ctrl, lane_ctrl, dir,
  12. * stream_type}
  13. */
  14. static struct port_params wsa_frame_params_default[SWR_MSTR_PORT_LEN] = {
  15. {7, 1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
  16. {31, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
  17. {63, 12, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00},
  18. {7, 6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
  19. {31, 18, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
  20. {63, 13, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00},
  21. {15, 7, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
  22. {15, 10, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
  23. };
  24. static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = {
  25. {3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00},
  26. {31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x00},
  27. {31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0, 0x00, 0x00},
  28. {7, 9, 0, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0, 0x00, 0x00},
  29. {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 3, 0, 0x00, 0x00},
  30. };
  31. /* Headset + PCM Haptics */
  32. static struct port_params rx_frame_params_default[SWR_MSTR_PORT_LEN] = {
  33. {3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00}, /* HPH/EAR */
  34. {31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x00}, /* HPH_CLH */
  35. {31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0, 0x00, 0x00}, /* HPH_CMP */
  36. {7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* LO/AUX */
  37. {0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0x00, 0x00}, /* DSD */
  38. {0x18F, 0, 0, 0x8, 0x8, 0x0F, 0x00, 0, 0, 0x00, 0x01}, /* PCM_OUT */
  39. };
  40. /* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */
  41. static struct port_params tx_frame_params_default[SWR_MSTR_PORT_LEN] = {
  42. {7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */
  43. {3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX2 */
  44. {7, 5, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */
  45. };
  46. /* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */
  47. static struct port_params tx_frame_params_shima[SWR_MSTR_PORT_LEN] = {
  48. {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */
  49. {3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX2 */
  50. {7, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */
  51. };
  52. /* 4.8 MHz clock */
  53. static struct port_params tx_frame_params_4p8MHz[SWR_MSTR_PORT_LEN] = {
  54. {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */
  55. {3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX2 */
  56. {3, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */
  57. };
  58. #endif /* _LAHAINA_PORT_CONFIG */