dp_main.c 207 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167416841694170417141724173417441754176417741784179418041814182418341844185418641874188418941904191419241934194419541964197419841994200420142024203420442054206420742084209421042114212421342144215421642174218421942204221422242234224422542264227422842294230423142324233423442354236423742384239424042414242424342444245424642474248424942504251425242534254425542564257425842594260426142624263426442654266426742684269427042714272427342744275427642774278427942804281428242834284428542864287428842894290429142924293429442954296429742984299430043014302430343044305430643074308430943104311431243134314431543164317431843194320432143224323432443254326432743284329433043314332433343344335433643374338433943404341434243434344434543464347434843494350435143524353435443554356435743584359436043614362436343644365436643674368436943704371437243734374437543764377437843794380438143824383438443854386438743884389439043914392439343944395439643974398439944004401440244034404440544064407440844094410441144124413441444154416441744184419442044214422442344244425442644274428442944304431443244334434443544364437443844394440444144424443444444454446444744484449445044514452445344544455445644574458445944604461446244634464446544664467446844694470447144724473447444754476447744784479448044814482448344844485448644874488448944904491449244934494449544964497449844994500450145024503450445054506450745084509451045114512451345144515451645174518451945204521452245234524452545264527452845294530453145324533453445354536453745384539454045414542454345444545454645474548454945504551455245534554455545564557455845594560456145624563456445654566456745684569457045714572457345744575457645774578457945804581458245834584458545864587458845894590459145924593459445954596459745984599460046014602460346044605460646074608460946104611461246134614461546164617461846194620462146224623462446254626462746284629463046314632463346344635463646374638463946404641464246434644464546464647464846494650465146524653465446554656465746584659466046614662466346644665466646674668466946704671467246734674467546764677467846794680468146824683468446854686468746884689469046914692469346944695469646974698469947004701470247034704470547064707470847094710471147124713471447154716471747184719472047214722472347244725472647274728472947304731473247334734473547364737473847394740474147424743474447454746474747484749475047514752475347544755475647574758475947604761476247634764476547664767476847694770477147724773477447754776477747784779478047814782478347844785478647874788478947904791479247934794479547964797479847994800480148024803480448054806480748084809481048114812481348144815481648174818481948204821482248234824482548264827482848294830483148324833483448354836483748384839484048414842484348444845484648474848484948504851485248534854485548564857485848594860486148624863486448654866486748684869487048714872487348744875487648774878487948804881488248834884488548864887488848894890489148924893489448954896489748984899490049014902490349044905490649074908490949104911491249134914491549164917491849194920492149224923492449254926492749284929493049314932493349344935493649374938493949404941494249434944494549464947494849494950495149524953495449554956495749584959496049614962496349644965496649674968496949704971497249734974497549764977497849794980498149824983498449854986498749884989499049914992499349944995499649974998499950005001500250035004500550065007500850095010501150125013501450155016501750185019502050215022502350245025502650275028502950305031503250335034503550365037503850395040504150425043504450455046504750485049505050515052505350545055505650575058505950605061506250635064506550665067506850695070507150725073507450755076507750785079508050815082508350845085508650875088508950905091509250935094509550965097509850995100510151025103510451055106510751085109511051115112511351145115511651175118511951205121512251235124512551265127512851295130513151325133513451355136513751385139514051415142514351445145514651475148514951505151515251535154515551565157515851595160516151625163516451655166516751685169517051715172517351745175517651775178517951805181518251835184518551865187518851895190519151925193519451955196519751985199520052015202520352045205520652075208520952105211521252135214521552165217521852195220522152225223522452255226522752285229523052315232523352345235523652375238523952405241524252435244524552465247524852495250525152525253525452555256525752585259526052615262526352645265526652675268526952705271527252735274527552765277527852795280528152825283528452855286528752885289529052915292529352945295529652975298529953005301530253035304530553065307530853095310531153125313531453155316531753185319532053215322532353245325532653275328532953305331533253335334533553365337533853395340534153425343534453455346534753485349535053515352535353545355535653575358535953605361536253635364536553665367536853695370537153725373537453755376537753785379538053815382538353845385538653875388538953905391539253935394539553965397539853995400540154025403540454055406540754085409541054115412541354145415541654175418541954205421542254235424542554265427542854295430543154325433543454355436543754385439544054415442544354445445544654475448544954505451545254535454545554565457545854595460546154625463546454655466546754685469547054715472547354745475547654775478547954805481548254835484548554865487548854895490549154925493549454955496549754985499550055015502550355045505550655075508550955105511551255135514551555165517551855195520552155225523552455255526552755285529553055315532553355345535553655375538553955405541554255435544554555465547554855495550555155525553555455555556555755585559556055615562556355645565556655675568556955705571557255735574557555765577557855795580558155825583558455855586558755885589559055915592559355945595559655975598559956005601560256035604560556065607560856095610561156125613561456155616561756185619562056215622562356245625562656275628562956305631563256335634563556365637563856395640564156425643564456455646564756485649565056515652565356545655565656575658565956605661566256635664566556665667566856695670567156725673567456755676567756785679568056815682568356845685568656875688568956905691569256935694569556965697569856995700570157025703570457055706570757085709571057115712571357145715571657175718571957205721572257235724572557265727572857295730573157325733573457355736573757385739574057415742574357445745574657475748574957505751575257535754575557565757575857595760576157625763576457655766576757685769577057715772577357745775577657775778577957805781578257835784578557865787578857895790579157925793579457955796579757985799580058015802580358045805580658075808580958105811581258135814581558165817581858195820582158225823582458255826582758285829583058315832583358345835583658375838583958405841584258435844584558465847584858495850585158525853585458555856585758585859586058615862586358645865586658675868586958705871587258735874587558765877587858795880588158825883588458855886588758885889589058915892589358945895589658975898589959005901590259035904590559065907590859095910591159125913591459155916591759185919592059215922592359245925592659275928592959305931593259335934593559365937593859395940594159425943594459455946594759485949595059515952595359545955595659575958595959605961596259635964596559665967596859695970597159725973597459755976597759785979598059815982598359845985598659875988598959905991599259935994599559965997599859996000600160026003600460056006600760086009601060116012601360146015601660176018601960206021602260236024602560266027602860296030603160326033603460356036603760386039604060416042604360446045604660476048604960506051605260536054605560566057605860596060606160626063606460656066606760686069607060716072607360746075607660776078607960806081608260836084608560866087608860896090609160926093609460956096609760986099610061016102610361046105610661076108610961106111611261136114611561166117611861196120612161226123612461256126612761286129613061316132613361346135613661376138613961406141614261436144614561466147614861496150615161526153615461556156615761586159616061616162616361646165616661676168616961706171617261736174617561766177617861796180618161826183618461856186618761886189619061916192619361946195619661976198619962006201620262036204620562066207620862096210621162126213621462156216621762186219622062216222622362246225622662276228622962306231623262336234623562366237623862396240624162426243624462456246624762486249625062516252625362546255625662576258625962606261626262636264626562666267626862696270627162726273627462756276627762786279628062816282628362846285628662876288628962906291629262936294629562966297629862996300630163026303630463056306630763086309631063116312631363146315631663176318631963206321632263236324632563266327632863296330633163326333633463356336633763386339634063416342634363446345634663476348634963506351635263536354635563566357635863596360636163626363636463656366636763686369637063716372637363746375637663776378637963806381638263836384638563866387638863896390639163926393639463956396639763986399640064016402640364046405640664076408640964106411641264136414641564166417641864196420642164226423642464256426642764286429643064316432643364346435643664376438643964406441644264436444644564466447644864496450645164526453645464556456645764586459646064616462646364646465646664676468646964706471647264736474647564766477647864796480648164826483648464856486648764886489649064916492649364946495649664976498649965006501650265036504650565066507650865096510651165126513651465156516651765186519652065216522652365246525652665276528652965306531653265336534653565366537653865396540654165426543654465456546654765486549655065516552655365546555655665576558655965606561656265636564656565666567656865696570657165726573657465756576657765786579658065816582658365846585658665876588658965906591659265936594659565966597659865996600660166026603660466056606660766086609661066116612661366146615661666176618661966206621662266236624662566266627662866296630663166326633663466356636663766386639664066416642664366446645664666476648664966506651665266536654665566566657665866596660666166626663666466656666666766686669667066716672667366746675667666776678667966806681668266836684668566866687668866896690669166926693669466956696669766986699670067016702670367046705670667076708670967106711671267136714671567166717671867196720672167226723672467256726672767286729673067316732673367346735673667376738673967406741674267436744674567466747674867496750675167526753675467556756675767586759676067616762676367646765676667676768676967706771677267736774677567766777677867796780678167826783678467856786678767886789679067916792679367946795679667976798679968006801680268036804680568066807680868096810681168126813681468156816681768186819682068216822682368246825682668276828682968306831683268336834683568366837683868396840684168426843684468456846684768486849685068516852685368546855685668576858685968606861686268636864686568666867686868696870687168726873687468756876687768786879688068816882688368846885688668876888688968906891689268936894689568966897689868996900690169026903690469056906690769086909691069116912691369146915691669176918691969206921692269236924692569266927692869296930693169326933693469356936693769386939694069416942694369446945694669476948694969506951695269536954695569566957695869596960696169626963696469656966696769686969697069716972697369746975697669776978697969806981698269836984698569866987698869896990699169926993699469956996699769986999700070017002700370047005700670077008700970107011701270137014701570167017701870197020702170227023702470257026702770287029703070317032703370347035703670377038703970407041704270437044704570467047704870497050705170527053705470557056705770587059706070617062706370647065706670677068706970707071707270737074707570767077707870797080708170827083708470857086708770887089709070917092709370947095709670977098709971007101710271037104710571067107710871097110711171127113711471157116711771187119712071217122712371247125712671277128712971307131713271337134713571367137713871397140714171427143714471457146714771487149715071517152715371547155715671577158715971607161716271637164716571667167716871697170717171727173717471757176717771787179718071817182718371847185718671877188718971907191719271937194719571967197719871997200720172027203720472057206720772087209721072117212721372147215721672177218721972207221722272237224722572267227722872297230723172327233723472357236723772387239724072417242724372447245724672477248724972507251725272537254725572567257725872597260726172627263726472657266726772687269727072717272727372747275727672777278727972807281728272837284728572867287728872897290729172927293729472957296729772987299730073017302730373047305730673077308730973107311731273137314731573167317731873197320732173227323732473257326732773287329733073317332733373347335733673377338733973407341734273437344734573467347734873497350735173527353735473557356735773587359736073617362736373647365736673677368736973707371737273737374737573767377737873797380738173827383738473857386738773887389739073917392739373947395739673977398739974007401740274037404740574067407740874097410741174127413741474157416741774187419742074217422742374247425742674277428742974307431743274337434743574367437743874397440744174427443744474457446744774487449745074517452745374547455745674577458745974607461746274637464746574667467746874697470747174727473747474757476747774787479748074817482748374847485748674877488748974907491749274937494749574967497749874997500750175027503750475057506750775087509751075117512751375147515751675177518751975207521752275237524752575267527752875297530753175327533753475357536753775387539754075417542754375447545754675477548754975507551755275537554755575567557755875597560756175627563756475657566756775687569757075717572757375747575757675777578757975807581758275837584758575867587758875897590759175927593759475957596759775987599760076017602760376047605760676077608760976107611761276137614761576167617761876197620
  1. /*
  2. * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <qdf_net_types.h>
  21. #include <qdf_lro.h>
  22. #include <qdf_module.h>
  23. #include <hal_api.h>
  24. #include <hif.h>
  25. #include <htt.h>
  26. #include <wdi_event.h>
  27. #include <queue.h>
  28. #include "dp_htt.h"
  29. #include "dp_types.h"
  30. #include "dp_internal.h"
  31. #include "dp_tx.h"
  32. #include "dp_tx_desc.h"
  33. #include "dp_rx.h"
  34. #include <cdp_txrx_handle.h>
  35. #include <wlan_cfg.h>
  36. #include "cdp_txrx_cmn_struct.h"
  37. #include "cdp_txrx_stats_struct.h"
  38. #include <qdf_util.h>
  39. #include "dp_peer.h"
  40. #include "dp_rx_mon.h"
  41. #include "htt_stats.h"
  42. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  43. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  44. #include "cdp_txrx_flow_ctrl_v2.h"
  45. #else
  46. static inline void
  47. cdp_dump_flow_pool_info(struct cdp_soc_t *soc)
  48. {
  49. return;
  50. }
  51. #endif
  52. #include "dp_ipa.h"
  53. #ifdef CONFIG_MCL
  54. static void dp_service_mon_rings(void *arg);
  55. #ifndef REMOVE_PKT_LOG
  56. #include <pktlog_ac_api.h>
  57. #include <pktlog_ac.h>
  58. static void dp_pkt_log_con_service(struct cdp_pdev *ppdev, void *scn);
  59. #endif
  60. #endif
  61. static void dp_pktlogmod_exit(struct dp_pdev *handle);
  62. static void *dp_peer_create_wifi3(struct cdp_vdev *vdev_handle,
  63. uint8_t *peer_mac_addr);
  64. static void dp_peer_delete_wifi3(void *peer_handle, uint32_t bitmap);
  65. #define DP_INTR_POLL_TIMER_MS 10
  66. #define DP_WDS_AGING_TIMER_DEFAULT_MS 120000
  67. #define DP_MCS_LENGTH (6*MAX_MCS)
  68. #define DP_NSS_LENGTH (6*SS_COUNT)
  69. #define DP_RXDMA_ERR_LENGTH (6*HAL_RXDMA_ERR_MAX)
  70. #define DP_REO_ERR_LENGTH (6*HAL_REO_ERR_MAX)
  71. #define DP_MAX_MCS_STRING_LEN 30
  72. #define DP_CURR_FW_STATS_AVAIL 19
  73. #define DP_HTT_DBG_EXT_STATS_MAX 256
  74. #define DP_MAX_SLEEP_TIME 100
  75. #ifdef IPA_OFFLOAD
  76. /* Exclude IPA rings from the interrupt context */
  77. #define TX_RING_MASK_VAL 0xb
  78. #define RX_RING_MASK_VAL 0x7
  79. #else
  80. #define TX_RING_MASK_VAL 0xF
  81. #define RX_RING_MASK_VAL 0xF
  82. #endif
  83. bool rx_hash = 1;
  84. qdf_declare_param(rx_hash, bool);
  85. #define STR_MAXLEN 64
  86. #define DP_PPDU_STATS_CFG_ALL 0xFFFF
  87. /* PPDU stats mask sent to FW to enable enhanced stats */
  88. #define DP_PPDU_STATS_CFG_ENH_STATS 0xE67
  89. /* PPDU stats mask sent to FW to support debug sniffer feature */
  90. #define DP_PPDU_STATS_CFG_SNIFFER 0x2FFF
  91. /**
  92. * default_dscp_tid_map - Default DSCP-TID mapping
  93. *
  94. * DSCP TID
  95. * 000000 0
  96. * 001000 1
  97. * 010000 2
  98. * 011000 3
  99. * 100000 4
  100. * 101000 5
  101. * 110000 6
  102. * 111000 7
  103. */
  104. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  105. 0, 0, 0, 0, 0, 0, 0, 0,
  106. 1, 1, 1, 1, 1, 1, 1, 1,
  107. 2, 2, 2, 2, 2, 2, 2, 2,
  108. 3, 3, 3, 3, 3, 3, 3, 3,
  109. 4, 4, 4, 4, 4, 4, 4, 4,
  110. 5, 5, 5, 5, 5, 5, 5, 5,
  111. 6, 6, 6, 6, 6, 6, 6, 6,
  112. 7, 7, 7, 7, 7, 7, 7, 7,
  113. };
  114. /*
  115. * struct dp_rate_debug
  116. *
  117. * @mcs_type: print string for a given mcs
  118. * @valid: valid mcs rate?
  119. */
  120. struct dp_rate_debug {
  121. char mcs_type[DP_MAX_MCS_STRING_LEN];
  122. uint8_t valid;
  123. };
  124. #define MCS_VALID 1
  125. #define MCS_INVALID 0
  126. static const struct dp_rate_debug dp_rate_string[DOT11_MAX][MAX_MCS] = {
  127. {
  128. {"OFDM 48 Mbps", MCS_VALID},
  129. {"OFDM 24 Mbps", MCS_VALID},
  130. {"OFDM 12 Mbps", MCS_VALID},
  131. {"OFDM 6 Mbps ", MCS_VALID},
  132. {"OFDM 54 Mbps", MCS_VALID},
  133. {"OFDM 36 Mbps", MCS_VALID},
  134. {"OFDM 18 Mbps", MCS_VALID},
  135. {"OFDM 9 Mbps ", MCS_VALID},
  136. {"INVALID ", MCS_INVALID},
  137. {"INVALID ", MCS_INVALID},
  138. {"INVALID ", MCS_INVALID},
  139. {"INVALID ", MCS_INVALID},
  140. {"INVALID ", MCS_VALID},
  141. },
  142. {
  143. {"CCK 11 Mbps Long ", MCS_VALID},
  144. {"CCK 5.5 Mbps Long ", MCS_VALID},
  145. {"CCK 2 Mbps Long ", MCS_VALID},
  146. {"CCK 1 Mbps Long ", MCS_VALID},
  147. {"CCK 11 Mbps Short ", MCS_VALID},
  148. {"CCK 5.5 Mbps Short", MCS_VALID},
  149. {"CCK 2 Mbps Short ", MCS_VALID},
  150. {"INVALID ", MCS_INVALID},
  151. {"INVALID ", MCS_INVALID},
  152. {"INVALID ", MCS_INVALID},
  153. {"INVALID ", MCS_INVALID},
  154. {"INVALID ", MCS_INVALID},
  155. {"INVALID ", MCS_VALID},
  156. },
  157. {
  158. {"HT MCS 0 (BPSK 1/2) ", MCS_VALID},
  159. {"HT MCS 1 (QPSK 1/2) ", MCS_VALID},
  160. {"HT MCS 2 (QPSK 3/4) ", MCS_VALID},
  161. {"HT MCS 3 (16-QAM 1/2)", MCS_VALID},
  162. {"HT MCS 4 (16-QAM 3/4)", MCS_VALID},
  163. {"HT MCS 5 (64-QAM 2/3)", MCS_VALID},
  164. {"HT MCS 6 (64-QAM 3/4)", MCS_VALID},
  165. {"HT MCS 7 (64-QAM 5/6)", MCS_VALID},
  166. {"INVALID ", MCS_INVALID},
  167. {"INVALID ", MCS_INVALID},
  168. {"INVALID ", MCS_INVALID},
  169. {"INVALID ", MCS_INVALID},
  170. {"INVALID ", MCS_VALID},
  171. },
  172. {
  173. {"VHT MCS 0 (BPSK 1/2) ", MCS_VALID},
  174. {"VHT MCS 1 (QPSK 1/2) ", MCS_VALID},
  175. {"VHT MCS 2 (QPSK 3/4) ", MCS_VALID},
  176. {"VHT MCS 3 (16-QAM 1/2) ", MCS_VALID},
  177. {"VHT MCS 4 (16-QAM 3/4) ", MCS_VALID},
  178. {"VHT MCS 5 (64-QAM 2/3) ", MCS_VALID},
  179. {"VHT MCS 6 (64-QAM 3/4) ", MCS_VALID},
  180. {"VHT MCS 7 (64-QAM 5/6) ", MCS_VALID},
  181. {"VHT MCS 8 (256-QAM 3/4) ", MCS_VALID},
  182. {"VHT MCS 9 (256-QAM 5/6) ", MCS_VALID},
  183. {"VHT MCS 10 (1024-QAM 3/4)", MCS_VALID},
  184. {"VHT MCS 11 (1024-QAM 5/6)", MCS_VALID},
  185. {"INVALID ", MCS_VALID},
  186. },
  187. {
  188. {"HE MCS 0 (BPSK 1/2) ", MCS_VALID},
  189. {"HE MCS 1 (QPSK 1/2) ", MCS_VALID},
  190. {"HE MCS 2 (QPSK 3/4) ", MCS_VALID},
  191. {"HE MCS 3 (16-QAM 1/2) ", MCS_VALID},
  192. {"HE MCS 4 (16-QAM 3/4) ", MCS_VALID},
  193. {"HE MCS 5 (64-QAM 2/3) ", MCS_VALID},
  194. {"HE MCS 6 (64-QAM 3/4) ", MCS_VALID},
  195. {"HE MCS 7 (64-QAM 5/6) ", MCS_VALID},
  196. {"HE MCS 8 (256-QAM 3/4) ", MCS_VALID},
  197. {"HE MCS 9 (256-QAM 5/6) ", MCS_VALID},
  198. {"HE MCS 10 (1024-QAM 3/4)", MCS_VALID},
  199. {"HE MCS 11 (1024-QAM 5/6)", MCS_VALID},
  200. {"INVALID ", MCS_VALID},
  201. }
  202. };
  203. /**
  204. * @brief Cpu ring map types
  205. */
  206. enum dp_cpu_ring_map_types {
  207. DP_DEFAULT_MAP,
  208. DP_NSS_FIRST_RADIO_OFFLOADED_MAP,
  209. DP_NSS_SECOND_RADIO_OFFLOADED_MAP,
  210. DP_NSS_ALL_RADIO_OFFLOADED_MAP,
  211. DP_CPU_RING_MAP_MAX
  212. };
  213. /**
  214. * @brief Cpu to tx ring map
  215. */
  216. static uint8_t dp_cpu_ring_map[DP_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS] = {
  217. {0x0, 0x1, 0x2, 0x0},
  218. {0x1, 0x2, 0x1, 0x2},
  219. {0x0, 0x2, 0x0, 0x2},
  220. {0x2, 0x2, 0x2, 0x2}
  221. };
  222. /**
  223. * @brief Select the type of statistics
  224. */
  225. enum dp_stats_type {
  226. STATS_FW = 0,
  227. STATS_HOST = 1,
  228. STATS_TYPE_MAX = 2,
  229. };
  230. /**
  231. * @brief General Firmware statistics options
  232. *
  233. */
  234. enum dp_fw_stats {
  235. TXRX_FW_STATS_INVALID = -1,
  236. };
  237. /**
  238. * dp_stats_mapping_table - Firmware and Host statistics
  239. * currently supported
  240. */
  241. const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
  242. {HTT_DBG_EXT_STATS_RESET, TXRX_HOST_STATS_INVALID},
  243. {HTT_DBG_EXT_STATS_PDEV_TX, TXRX_HOST_STATS_INVALID},
  244. {HTT_DBG_EXT_STATS_PDEV_RX, TXRX_HOST_STATS_INVALID},
  245. {HTT_DBG_EXT_STATS_PDEV_TX_HWQ, TXRX_HOST_STATS_INVALID},
  246. {HTT_DBG_EXT_STATS_PDEV_TX_SCHED, TXRX_HOST_STATS_INVALID},
  247. {HTT_DBG_EXT_STATS_PDEV_ERROR, TXRX_HOST_STATS_INVALID},
  248. {HTT_DBG_EXT_STATS_PDEV_TQM, TXRX_HOST_STATS_INVALID},
  249. {HTT_DBG_EXT_STATS_TQM_CMDQ, TXRX_HOST_STATS_INVALID},
  250. {HTT_DBG_EXT_STATS_TX_DE_INFO, TXRX_HOST_STATS_INVALID},
  251. {HTT_DBG_EXT_STATS_PDEV_TX_RATE, TXRX_HOST_STATS_INVALID},
  252. {HTT_DBG_EXT_STATS_PDEV_RX_RATE, TXRX_HOST_STATS_INVALID},
  253. {TXRX_FW_STATS_INVALID, TXRX_HOST_STATS_INVALID},
  254. {HTT_DBG_EXT_STATS_TX_SELFGEN_INFO, TXRX_HOST_STATS_INVALID},
  255. {HTT_DBG_EXT_STATS_TX_MU_HWQ, TXRX_HOST_STATS_INVALID},
  256. {HTT_DBG_EXT_STATS_RING_IF_INFO, TXRX_HOST_STATS_INVALID},
  257. {HTT_DBG_EXT_STATS_SRNG_INFO, TXRX_HOST_STATS_INVALID},
  258. {HTT_DBG_EXT_STATS_SFM_INFO, TXRX_HOST_STATS_INVALID},
  259. {HTT_DBG_EXT_STATS_PDEV_TX_MU, TXRX_HOST_STATS_INVALID},
  260. {HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST, TXRX_HOST_STATS_INVALID},
  261. /* Last ENUM for HTT FW STATS */
  262. {DP_HTT_DBG_EXT_STATS_MAX, TXRX_HOST_STATS_INVALID},
  263. {TXRX_FW_STATS_INVALID, TXRX_CLEAR_STATS},
  264. {TXRX_FW_STATS_INVALID, TXRX_RX_RATE_STATS},
  265. {TXRX_FW_STATS_INVALID, TXRX_TX_RATE_STATS},
  266. {TXRX_FW_STATS_INVALID, TXRX_TX_HOST_STATS},
  267. {TXRX_FW_STATS_INVALID, TXRX_RX_HOST_STATS},
  268. {TXRX_FW_STATS_INVALID, TXRX_AST_STATS},
  269. {TXRX_FW_STATS_INVALID, TXRX_SRNG_PTR_STATS},
  270. };
  271. static int dp_peer_add_ast_wifi3(struct cdp_soc_t *soc_hdl,
  272. struct cdp_peer *peer_hdl,
  273. uint8_t *mac_addr,
  274. enum cdp_txrx_ast_entry_type type,
  275. uint32_t flags)
  276. {
  277. return dp_peer_add_ast((struct dp_soc *)soc_hdl,
  278. (struct dp_peer *)peer_hdl,
  279. mac_addr,
  280. type,
  281. flags);
  282. }
  283. static void dp_peer_del_ast_wifi3(struct cdp_soc_t *soc_hdl,
  284. void *ast_entry_hdl)
  285. {
  286. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  287. qdf_spin_lock_bh(&soc->ast_lock);
  288. dp_peer_del_ast((struct dp_soc *)soc_hdl,
  289. (struct dp_ast_entry *)ast_entry_hdl);
  290. qdf_spin_unlock_bh(&soc->ast_lock);
  291. }
  292. static int dp_peer_update_ast_wifi3(struct cdp_soc_t *soc_hdl,
  293. struct cdp_peer *peer_hdl,
  294. uint8_t *wds_macaddr,
  295. uint32_t flags)
  296. {
  297. int status;
  298. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  299. struct dp_ast_entry *ast_entry = NULL;
  300. qdf_spin_lock_bh(&soc->ast_lock);
  301. ast_entry = dp_peer_ast_hash_find(soc, wds_macaddr);
  302. status = dp_peer_update_ast(soc,
  303. (struct dp_peer *)peer_hdl,
  304. ast_entry,
  305. flags);
  306. qdf_spin_unlock_bh(&soc->ast_lock);
  307. return status;
  308. }
  309. /*
  310. * dp_wds_reset_ast_wifi3() - Reset the is_active param for ast entry
  311. * @soc_handle: Datapath SOC handle
  312. * @ast_entry_hdl: AST Entry handle
  313. * Return: None
  314. */
  315. static void dp_wds_reset_ast_wifi3(struct cdp_soc_t *soc_hdl,
  316. uint8_t *wds_macaddr)
  317. {
  318. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  319. struct dp_ast_entry *ast_entry = NULL;
  320. qdf_spin_lock_bh(&soc->ast_lock);
  321. ast_entry = dp_peer_ast_hash_find(soc, wds_macaddr);
  322. if (ast_entry->type != CDP_TXRX_AST_TYPE_STATIC) {
  323. ast_entry->is_active = TRUE;
  324. }
  325. qdf_spin_unlock_bh(&soc->ast_lock);
  326. }
  327. /*
  328. * dp_wds_reset_ast_table_wifi3() - Reset the is_active param for all ast entry
  329. * @soc: Datapath SOC handle
  330. *
  331. * Return: None
  332. */
  333. static void dp_wds_reset_ast_table_wifi3(struct cdp_soc_t *soc_hdl)
  334. {
  335. struct dp_soc *soc = (struct dp_soc *) soc_hdl;
  336. struct dp_pdev *pdev;
  337. struct dp_vdev *vdev;
  338. struct dp_peer *peer;
  339. struct dp_ast_entry *ase, *temp_ase;
  340. int i;
  341. qdf_spin_lock_bh(&soc->ast_lock);
  342. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  343. pdev = soc->pdev_list[i];
  344. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  345. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  346. DP_PEER_ITERATE_ASE_LIST(peer, ase, temp_ase) {
  347. if (ase->type ==
  348. CDP_TXRX_AST_TYPE_STATIC)
  349. continue;
  350. ase->is_active = TRUE;
  351. }
  352. }
  353. }
  354. }
  355. qdf_spin_unlock_bh(&soc->ast_lock);
  356. }
  357. /*
  358. * dp_wds_flush_ast_table_wifi3() - Delete all wds and hmwds ast entry
  359. * @soc: Datapath SOC handle
  360. *
  361. * Return: None
  362. */
  363. static void dp_wds_flush_ast_table_wifi3(struct cdp_soc_t *soc_hdl)
  364. {
  365. struct dp_soc *soc = (struct dp_soc *) soc_hdl;
  366. struct dp_pdev *pdev;
  367. struct dp_vdev *vdev;
  368. struct dp_peer *peer;
  369. struct dp_ast_entry *ase, *temp_ase;
  370. int i;
  371. qdf_spin_lock_bh(&soc->ast_lock);
  372. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  373. pdev = soc->pdev_list[i];
  374. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  375. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  376. DP_PEER_ITERATE_ASE_LIST(peer, ase, temp_ase) {
  377. if (ase->type ==
  378. CDP_TXRX_AST_TYPE_STATIC)
  379. continue;
  380. dp_peer_del_ast(soc, ase);
  381. }
  382. }
  383. }
  384. }
  385. qdf_spin_unlock_bh(&soc->ast_lock);
  386. }
  387. static void *dp_peer_ast_hash_find_wifi3(struct cdp_soc_t *soc_hdl,
  388. uint8_t *ast_mac_addr)
  389. {
  390. struct dp_ast_entry *ast_entry;
  391. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  392. qdf_spin_lock_bh(&soc->ast_lock);
  393. ast_entry = dp_peer_ast_hash_find(soc, ast_mac_addr);
  394. qdf_spin_unlock_bh(&soc->ast_lock);
  395. return (void *)ast_entry;
  396. }
  397. static uint8_t dp_peer_ast_get_pdev_id_wifi3(struct cdp_soc_t *soc_hdl,
  398. void *ast_entry_hdl)
  399. {
  400. return dp_peer_ast_get_pdev_id((struct dp_soc *)soc_hdl,
  401. (struct dp_ast_entry *)ast_entry_hdl);
  402. }
  403. static uint8_t dp_peer_ast_get_next_hop_wifi3(struct cdp_soc_t *soc_hdl,
  404. void *ast_entry_hdl)
  405. {
  406. return dp_peer_ast_get_next_hop((struct dp_soc *)soc_hdl,
  407. (struct dp_ast_entry *)ast_entry_hdl);
  408. }
  409. static void dp_peer_ast_set_type_wifi3(
  410. struct cdp_soc_t *soc_hdl,
  411. void *ast_entry_hdl,
  412. enum cdp_txrx_ast_entry_type type)
  413. {
  414. dp_peer_ast_set_type((struct dp_soc *)soc_hdl,
  415. (struct dp_ast_entry *)ast_entry_hdl,
  416. type);
  417. }
  418. /**
  419. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  420. * @ring_num: ring num of the ring being queried
  421. * @grp_mask: the grp_mask array for the ring type in question.
  422. *
  423. * The grp_mask array is indexed by group number and the bit fields correspond
  424. * to ring numbers. We are finding which interrupt group a ring belongs to.
  425. *
  426. * Return: the index in the grp_mask array with the ring number.
  427. * -QDF_STATUS_E_NOENT if no entry is found
  428. */
  429. static int dp_srng_find_ring_in_mask(int ring_num, int *grp_mask)
  430. {
  431. int ext_group_num;
  432. int mask = 1 << ring_num;
  433. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  434. ext_group_num++) {
  435. if (mask & grp_mask[ext_group_num])
  436. return ext_group_num;
  437. }
  438. return -QDF_STATUS_E_NOENT;
  439. }
  440. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  441. enum hal_ring_type ring_type,
  442. int ring_num)
  443. {
  444. int *grp_mask;
  445. switch (ring_type) {
  446. case WBM2SW_RELEASE:
  447. /* dp_tx_comp_handler - soc->tx_comp_ring */
  448. if (ring_num < 3)
  449. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  450. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  451. else if (ring_num == 3) {
  452. /* sw treats this as a separate ring type */
  453. grp_mask = &soc->wlan_cfg_ctx->
  454. int_rx_wbm_rel_ring_mask[0];
  455. ring_num = 0;
  456. } else {
  457. qdf_assert(0);
  458. return -QDF_STATUS_E_NOENT;
  459. }
  460. break;
  461. case REO_EXCEPTION:
  462. /* dp_rx_err_process - &soc->reo_exception_ring */
  463. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  464. break;
  465. case REO_DST:
  466. /* dp_rx_process - soc->reo_dest_ring */
  467. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  468. break;
  469. case REO_STATUS:
  470. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  471. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  472. break;
  473. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  474. case RXDMA_MONITOR_STATUS:
  475. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  476. case RXDMA_MONITOR_DST:
  477. /* dp_mon_process */
  478. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  479. break;
  480. case RXDMA_DST:
  481. /* dp_rxdma_err_process */
  482. grp_mask = &soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[0];
  483. break;
  484. case RXDMA_BUF:
  485. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_ring_mask[0];
  486. break;
  487. case RXDMA_MONITOR_BUF:
  488. /* TODO: support low_thresh interrupt */
  489. return -QDF_STATUS_E_NOENT;
  490. break;
  491. case TCL_DATA:
  492. case TCL_CMD:
  493. case REO_CMD:
  494. case SW2WBM_RELEASE:
  495. case WBM_IDLE_LINK:
  496. /* normally empty SW_TO_HW rings */
  497. return -QDF_STATUS_E_NOENT;
  498. break;
  499. case TCL_STATUS:
  500. case REO_REINJECT:
  501. /* misc unused rings */
  502. return -QDF_STATUS_E_NOENT;
  503. break;
  504. case CE_SRC:
  505. case CE_DST:
  506. case CE_DST_STATUS:
  507. /* CE_rings - currently handled by hif */
  508. default:
  509. return -QDF_STATUS_E_NOENT;
  510. break;
  511. }
  512. return dp_srng_find_ring_in_mask(ring_num, grp_mask);
  513. }
  514. static void dp_srng_msi_setup(struct dp_soc *soc, struct hal_srng_params
  515. *ring_params, int ring_type, int ring_num)
  516. {
  517. int msi_group_number;
  518. int msi_data_count;
  519. int ret;
  520. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  521. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  522. &msi_data_count, &msi_data_start,
  523. &msi_irq_start);
  524. if (ret)
  525. return;
  526. msi_group_number = dp_srng_calculate_msi_group(soc, ring_type,
  527. ring_num);
  528. if (msi_group_number < 0) {
  529. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  530. FL("ring not part of an ext_group; ring_type: %d,ring_num %d"),
  531. ring_type, ring_num);
  532. ring_params->msi_addr = 0;
  533. ring_params->msi_data = 0;
  534. return;
  535. }
  536. if (msi_group_number > msi_data_count) {
  537. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  538. FL("2 msi_groups will share an msi; msi_group_num %d"),
  539. msi_group_number);
  540. QDF_ASSERT(0);
  541. }
  542. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  543. ring_params->msi_addr = addr_low;
  544. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  545. ring_params->msi_data = (msi_group_number % msi_data_count)
  546. + msi_data_start;
  547. ring_params->flags |= HAL_SRNG_MSI_INTR;
  548. }
  549. /**
  550. * dp_print_ast_stats() - Dump AST table contents
  551. * @soc: Datapath soc handle
  552. *
  553. * return void
  554. */
  555. #ifdef FEATURE_AST
  556. static void dp_print_ast_stats(struct dp_soc *soc)
  557. {
  558. uint8_t i;
  559. uint8_t num_entries = 0;
  560. struct dp_vdev *vdev;
  561. struct dp_pdev *pdev;
  562. struct dp_peer *peer;
  563. struct dp_ast_entry *ase, *tmp_ase;
  564. char type[5][10] = {"NONE", "STATIC", "WDS", "MEC", "HMWDS"};
  565. DP_PRINT_STATS("AST Stats:");
  566. DP_PRINT_STATS(" Entries Added = %d", soc->stats.ast.added);
  567. DP_PRINT_STATS(" Entries Deleted = %d", soc->stats.ast.deleted);
  568. DP_PRINT_STATS(" Entries Agedout = %d", soc->stats.ast.aged_out);
  569. DP_PRINT_STATS("AST Table:");
  570. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  571. pdev = soc->pdev_list[i];
  572. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  573. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  574. DP_PEER_ITERATE_ASE_LIST(peer, ase, tmp_ase) {
  575. DP_PRINT_STATS("%6d mac_addr = %pM"
  576. " peer_mac_addr = %pM"
  577. " type = %s"
  578. " next_hop = %d"
  579. " is_active = %d"
  580. " is_bss = %d"
  581. " ast_idx = %d"
  582. " pdev_id = %d"
  583. " vdev_id = %d",
  584. ++num_entries,
  585. ase->mac_addr.raw,
  586. ase->peer->mac_addr.raw,
  587. type[ase->type],
  588. ase->next_hop,
  589. ase->is_active,
  590. ase->is_bss,
  591. ase->ast_idx,
  592. ase->pdev_id,
  593. ase->vdev_id);
  594. }
  595. }
  596. }
  597. }
  598. }
  599. #else
  600. static void dp_print_ast_stats(struct dp_soc *soc)
  601. {
  602. DP_PRINT_STATS("AST Stats not available.Enable FEATURE_AST");
  603. return;
  604. }
  605. #endif
  606. static void dp_print_peer_table(struct dp_vdev *vdev)
  607. {
  608. struct dp_peer *peer = NULL;
  609. DP_PRINT_STATS("Dumping Peer Table Stats:");
  610. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  611. if (!peer) {
  612. DP_PRINT_STATS("Invalid Peer");
  613. return;
  614. }
  615. DP_PRINT_STATS(" peer_mac_addr = %pM"
  616. " nawds_enabled = %d"
  617. " bss_peer = %d"
  618. " wapi = %d"
  619. " wds_enabled = %d"
  620. " delete in progress = %d",
  621. peer->mac_addr.raw,
  622. peer->nawds_enabled,
  623. peer->bss_peer,
  624. peer->wapi,
  625. peer->wds_enabled,
  626. peer->delete_in_progress);
  627. }
  628. }
  629. /*
  630. * dp_setup_srng - Internal function to setup SRNG rings used by data path
  631. */
  632. static int dp_srng_setup(struct dp_soc *soc, struct dp_srng *srng,
  633. int ring_type, int ring_num, int mac_id, uint32_t num_entries)
  634. {
  635. void *hal_soc = soc->hal_soc;
  636. uint32_t entry_size = hal_srng_get_entrysize(hal_soc, ring_type);
  637. /* TODO: See if we should get align size from hal */
  638. uint32_t ring_base_align = 8;
  639. struct hal_srng_params ring_params;
  640. uint32_t max_entries = hal_srng_max_entries(hal_soc, ring_type);
  641. /* TODO: Currently hal layer takes care of endianness related settings.
  642. * See if these settings need to passed from DP layer
  643. */
  644. ring_params.flags = 0;
  645. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  646. FL("Ring type: %d, num:%d"), ring_type, ring_num);
  647. num_entries = (num_entries > max_entries) ? max_entries : num_entries;
  648. srng->hal_srng = NULL;
  649. srng->alloc_size = (num_entries * entry_size) + ring_base_align - 1;
  650. srng->num_entries = num_entries;
  651. srng->base_vaddr_unaligned = qdf_mem_alloc_consistent(
  652. soc->osdev, soc->osdev->dev, srng->alloc_size,
  653. &(srng->base_paddr_unaligned));
  654. if (!srng->base_vaddr_unaligned) {
  655. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  656. FL("alloc failed - ring_type: %d, ring_num %d"),
  657. ring_type, ring_num);
  658. return QDF_STATUS_E_NOMEM;
  659. }
  660. ring_params.ring_base_vaddr = srng->base_vaddr_unaligned +
  661. ((unsigned long)srng->base_vaddr_unaligned % ring_base_align);
  662. ring_params.ring_base_paddr = srng->base_paddr_unaligned +
  663. ((unsigned long)(ring_params.ring_base_vaddr) -
  664. (unsigned long)srng->base_vaddr_unaligned);
  665. ring_params.num_entries = num_entries;
  666. if (soc->intr_mode == DP_INTR_MSI) {
  667. dp_srng_msi_setup(soc, &ring_params, ring_type, ring_num);
  668. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  669. FL("Using MSI for ring_type: %d, ring_num %d"),
  670. ring_type, ring_num);
  671. } else {
  672. ring_params.msi_data = 0;
  673. ring_params.msi_addr = 0;
  674. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  675. FL("Skipping MSI for ring_type: %d, ring_num %d"),
  676. ring_type, ring_num);
  677. }
  678. /*
  679. * Setup interrupt timer and batch counter thresholds for
  680. * interrupt mitigation based on ring type
  681. */
  682. if (ring_type == REO_DST) {
  683. ring_params.intr_timer_thres_us =
  684. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  685. ring_params.intr_batch_cntr_thres_entries =
  686. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  687. } else if (ring_type == WBM2SW_RELEASE && (ring_num < 3)) {
  688. ring_params.intr_timer_thres_us =
  689. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  690. ring_params.intr_batch_cntr_thres_entries =
  691. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  692. } else {
  693. ring_params.intr_timer_thres_us =
  694. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  695. ring_params.intr_batch_cntr_thres_entries =
  696. wlan_cfg_get_int_batch_threshold_other(soc->wlan_cfg_ctx);
  697. }
  698. /* Enable low threshold interrupts for rx buffer rings (regular and
  699. * monitor buffer rings.
  700. * TODO: See if this is required for any other ring
  701. */
  702. if ((ring_type == RXDMA_BUF) || (ring_type == RXDMA_MONITOR_BUF) ||
  703. (ring_type == RXDMA_MONITOR_STATUS)) {
  704. /* TODO: Setting low threshold to 1/8th of ring size
  705. * see if this needs to be configurable
  706. */
  707. ring_params.low_threshold = num_entries >> 3;
  708. ring_params.flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  709. ring_params.intr_timer_thres_us =
  710. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  711. ring_params.intr_batch_cntr_thres_entries = 0;
  712. }
  713. srng->hal_srng = hal_srng_setup(hal_soc, ring_type, ring_num,
  714. mac_id, &ring_params);
  715. if (!srng->hal_srng) {
  716. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  717. srng->alloc_size,
  718. srng->base_vaddr_unaligned,
  719. srng->base_paddr_unaligned, 0);
  720. }
  721. return 0;
  722. }
  723. /**
  724. * dp_srng_cleanup - Internal function to cleanup SRNG rings used by data path
  725. * Any buffers allocated and attached to ring entries are expected to be freed
  726. * before calling this function.
  727. */
  728. static void dp_srng_cleanup(struct dp_soc *soc, struct dp_srng *srng,
  729. int ring_type, int ring_num)
  730. {
  731. if (!srng->hal_srng) {
  732. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  733. FL("Ring type: %d, num:%d not setup"),
  734. ring_type, ring_num);
  735. return;
  736. }
  737. hal_srng_cleanup(soc->hal_soc, srng->hal_srng);
  738. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  739. srng->alloc_size,
  740. srng->base_vaddr_unaligned,
  741. srng->base_paddr_unaligned, 0);
  742. srng->hal_srng = NULL;
  743. }
  744. /* TODO: Need this interface from HIF */
  745. void *hif_get_hal_handle(void *hif_handle);
  746. /*
  747. * dp_service_srngs() - Top level interrupt handler for DP Ring interrupts
  748. * @dp_ctx: DP SOC handle
  749. * @budget: Number of frames/descriptors that can be processed in one shot
  750. *
  751. * Return: remaining budget/quota for the soc device
  752. */
  753. static uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget)
  754. {
  755. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  756. struct dp_soc *soc = int_ctx->soc;
  757. int ring = 0;
  758. uint32_t work_done = 0;
  759. int budget = dp_budget;
  760. uint8_t tx_mask = int_ctx->tx_ring_mask;
  761. uint8_t rx_mask = int_ctx->rx_ring_mask;
  762. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  763. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  764. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  765. uint32_t remaining_quota = dp_budget;
  766. struct dp_pdev *pdev = NULL;
  767. int mac_id;
  768. /* Process Tx completion interrupts first to return back buffers */
  769. while (tx_mask) {
  770. if (tx_mask & 0x1) {
  771. work_done = dp_tx_comp_handler(soc,
  772. soc->tx_comp_ring[ring].hal_srng,
  773. remaining_quota);
  774. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  775. "tx mask 0x%x ring %d, budget %d, work_done %d",
  776. tx_mask, ring, budget, work_done);
  777. budget -= work_done;
  778. if (budget <= 0)
  779. goto budget_done;
  780. remaining_quota = budget;
  781. }
  782. tx_mask = tx_mask >> 1;
  783. ring++;
  784. }
  785. /* Process REO Exception ring interrupt */
  786. if (rx_err_mask) {
  787. work_done = dp_rx_err_process(soc,
  788. soc->reo_exception_ring.hal_srng,
  789. remaining_quota);
  790. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  791. "REO Exception Ring: work_done %d budget %d",
  792. work_done, budget);
  793. budget -= work_done;
  794. if (budget <= 0) {
  795. goto budget_done;
  796. }
  797. remaining_quota = budget;
  798. }
  799. /* Process Rx WBM release ring interrupt */
  800. if (rx_wbm_rel_mask) {
  801. work_done = dp_rx_wbm_err_process(soc,
  802. soc->rx_rel_ring.hal_srng, remaining_quota);
  803. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  804. "WBM Release Ring: work_done %d budget %d",
  805. work_done, budget);
  806. budget -= work_done;
  807. if (budget <= 0) {
  808. goto budget_done;
  809. }
  810. remaining_quota = budget;
  811. }
  812. /* Process Rx interrupts */
  813. if (rx_mask) {
  814. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  815. if (rx_mask & (1 << ring)) {
  816. work_done = dp_rx_process(int_ctx,
  817. soc->reo_dest_ring[ring].hal_srng,
  818. remaining_quota);
  819. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  820. "rx mask 0x%x ring %d, work_done %d budget %d",
  821. rx_mask, ring, work_done, budget);
  822. budget -= work_done;
  823. if (budget <= 0)
  824. goto budget_done;
  825. remaining_quota = budget;
  826. }
  827. }
  828. for (ring = 0; ring < MAX_RX_MAC_RINGS; ring++) {
  829. work_done = dp_rxdma_err_process(soc, ring,
  830. remaining_quota);
  831. budget -= work_done;
  832. }
  833. }
  834. if (reo_status_mask)
  835. dp_reo_status_ring_handler(soc);
  836. /* Process LMAC interrupts */
  837. for (ring = 0 ; ring < MAX_PDEV_CNT; ring++) {
  838. pdev = soc->pdev_list[ring];
  839. if (pdev == NULL)
  840. continue;
  841. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  842. int mac_for_pdev = dp_get_mac_id_for_pdev(mac_id,
  843. pdev->pdev_id);
  844. if (int_ctx->rx_mon_ring_mask & (1 << mac_for_pdev)) {
  845. work_done = dp_mon_process(soc, mac_for_pdev,
  846. remaining_quota);
  847. budget -= work_done;
  848. if (budget <= 0)
  849. goto budget_done;
  850. remaining_quota = budget;
  851. }
  852. if (int_ctx->rxdma2host_ring_mask &
  853. (1 << mac_for_pdev)) {
  854. work_done = dp_rxdma_err_process(soc,
  855. mac_for_pdev,
  856. remaining_quota);
  857. budget -= work_done;
  858. if (budget <= 0)
  859. goto budget_done;
  860. remaining_quota = budget;
  861. }
  862. if (int_ctx->host2rxdma_ring_mask &
  863. (1 << mac_for_pdev)) {
  864. union dp_rx_desc_list_elem_t *desc_list = NULL;
  865. union dp_rx_desc_list_elem_t *tail = NULL;
  866. struct dp_srng *rx_refill_buf_ring =
  867. &pdev->rx_refill_buf_ring;
  868. DP_STATS_INC(pdev, replenish.low_thresh_intrs,
  869. 1);
  870. dp_rx_buffers_replenish(soc, mac_for_pdev,
  871. rx_refill_buf_ring,
  872. &soc->rx_desc_buf[mac_for_pdev], 0,
  873. &desc_list, &tail);
  874. }
  875. }
  876. }
  877. qdf_lro_flush(int_ctx->lro_ctx);
  878. budget_done:
  879. return dp_budget - budget;
  880. }
  881. #ifdef DP_INTR_POLL_BASED
  882. /* dp_interrupt_timer()- timer poll for interrupts
  883. *
  884. * @arg: SoC Handle
  885. *
  886. * Return:
  887. *
  888. */
  889. static void dp_interrupt_timer(void *arg)
  890. {
  891. struct dp_soc *soc = (struct dp_soc *) arg;
  892. int i;
  893. if (qdf_atomic_read(&soc->cmn_init_done)) {
  894. for (i = 0;
  895. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  896. dp_service_srngs(&soc->intr_ctx[i], 0xffff);
  897. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  898. }
  899. }
  900. /*
  901. * dp_soc_interrupt_attach_poll() - Register handlers for DP interrupts
  902. * @txrx_soc: DP SOC handle
  903. *
  904. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  905. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  906. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  907. *
  908. * Return: 0 for success. nonzero for failure.
  909. */
  910. static QDF_STATUS dp_soc_interrupt_attach_poll(void *txrx_soc)
  911. {
  912. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  913. int i;
  914. soc->intr_mode = DP_INTR_POLL;
  915. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  916. soc->intr_ctx[i].dp_intr_id = i;
  917. soc->intr_ctx[i].tx_ring_mask =
  918. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  919. soc->intr_ctx[i].rx_ring_mask =
  920. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  921. soc->intr_ctx[i].rx_mon_ring_mask =
  922. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  923. soc->intr_ctx[i].rx_err_ring_mask =
  924. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  925. soc->intr_ctx[i].rx_wbm_rel_ring_mask =
  926. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  927. soc->intr_ctx[i].reo_status_ring_mask =
  928. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  929. soc->intr_ctx[i].rxdma2host_ring_mask =
  930. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  931. soc->intr_ctx[i].soc = soc;
  932. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  933. }
  934. qdf_timer_init(soc->osdev, &soc->int_timer,
  935. dp_interrupt_timer, (void *)soc,
  936. QDF_TIMER_TYPE_WAKE_APPS);
  937. return QDF_STATUS_SUCCESS;
  938. }
  939. #if defined(CONFIG_MCL)
  940. extern int con_mode_monitor;
  941. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc);
  942. /*
  943. * dp_soc_interrupt_attach_wrapper() - Register handlers for DP interrupts
  944. * @txrx_soc: DP SOC handle
  945. *
  946. * Call the appropriate attach function based on the mode of operation.
  947. * This is a WAR for enabling monitor mode.
  948. *
  949. * Return: 0 for success. nonzero for failure.
  950. */
  951. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  952. {
  953. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  954. if (!(soc->wlan_cfg_ctx->napi_enabled) ||
  955. con_mode_monitor == QDF_GLOBAL_MONITOR_MODE) {
  956. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  957. "%s: Poll mode", __func__);
  958. return dp_soc_interrupt_attach_poll(txrx_soc);
  959. } else {
  960. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  961. "%s: Interrupt mode", __func__);
  962. return dp_soc_interrupt_attach(txrx_soc);
  963. }
  964. }
  965. #else
  966. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  967. {
  968. return dp_soc_interrupt_attach_poll(txrx_soc);
  969. }
  970. #endif
  971. #endif
  972. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  973. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  974. {
  975. int j;
  976. int num_irq = 0;
  977. int tx_mask =
  978. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  979. int rx_mask =
  980. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  981. int rx_mon_mask =
  982. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  983. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  984. soc->wlan_cfg_ctx, intr_ctx_num);
  985. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  986. soc->wlan_cfg_ctx, intr_ctx_num);
  987. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  988. soc->wlan_cfg_ctx, intr_ctx_num);
  989. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  990. soc->wlan_cfg_ctx, intr_ctx_num);
  991. int host2rxdma_ring_mask = wlan_cfg_get_host2rxdma_ring_mask(
  992. soc->wlan_cfg_ctx, intr_ctx_num);
  993. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  994. if (tx_mask & (1 << j)) {
  995. irq_id_map[num_irq++] =
  996. (wbm2host_tx_completions_ring1 - j);
  997. }
  998. if (rx_mask & (1 << j)) {
  999. irq_id_map[num_irq++] =
  1000. (reo2host_destination_ring1 - j);
  1001. }
  1002. if (rxdma2host_ring_mask & (1 << j)) {
  1003. irq_id_map[num_irq++] =
  1004. rxdma2host_destination_ring_mac1 -
  1005. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  1006. }
  1007. if (host2rxdma_ring_mask & (1 << j)) {
  1008. irq_id_map[num_irq++] =
  1009. host2rxdma_host_buf_ring_mac1 -
  1010. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  1011. }
  1012. if (rx_mon_mask & (1 << j)) {
  1013. irq_id_map[num_irq++] =
  1014. ppdu_end_interrupts_mac1 -
  1015. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  1016. irq_id_map[num_irq++] =
  1017. rxdma2host_monitor_status_ring_mac1 -
  1018. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  1019. }
  1020. if (rx_wbm_rel_ring_mask & (1 << j))
  1021. irq_id_map[num_irq++] = wbm2host_rx_release;
  1022. if (rx_err_ring_mask & (1 << j))
  1023. irq_id_map[num_irq++] = reo2host_exception;
  1024. if (reo_status_ring_mask & (1 << j))
  1025. irq_id_map[num_irq++] = reo2host_status;
  1026. }
  1027. *num_irq_r = num_irq;
  1028. }
  1029. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  1030. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  1031. int msi_vector_count, int msi_vector_start)
  1032. {
  1033. int tx_mask = wlan_cfg_get_tx_ring_mask(
  1034. soc->wlan_cfg_ctx, intr_ctx_num);
  1035. int rx_mask = wlan_cfg_get_rx_ring_mask(
  1036. soc->wlan_cfg_ctx, intr_ctx_num);
  1037. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  1038. soc->wlan_cfg_ctx, intr_ctx_num);
  1039. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  1040. soc->wlan_cfg_ctx, intr_ctx_num);
  1041. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  1042. soc->wlan_cfg_ctx, intr_ctx_num);
  1043. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  1044. soc->wlan_cfg_ctx, intr_ctx_num);
  1045. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  1046. soc->wlan_cfg_ctx, intr_ctx_num);
  1047. unsigned int vector =
  1048. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  1049. int num_irq = 0;
  1050. soc->intr_mode = DP_INTR_MSI;
  1051. if (tx_mask | rx_mask | rx_mon_mask | rx_err_ring_mask |
  1052. rx_wbm_rel_ring_mask | reo_status_ring_mask | rxdma2host_ring_mask)
  1053. irq_id_map[num_irq++] =
  1054. pld_get_msi_irq(soc->osdev->dev, vector);
  1055. *num_irq_r = num_irq;
  1056. }
  1057. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  1058. int *irq_id_map, int *num_irq)
  1059. {
  1060. int msi_vector_count, ret;
  1061. uint32_t msi_base_data, msi_vector_start;
  1062. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  1063. &msi_vector_count,
  1064. &msi_base_data,
  1065. &msi_vector_start);
  1066. if (ret)
  1067. return dp_soc_interrupt_map_calculate_integrated(soc,
  1068. intr_ctx_num, irq_id_map, num_irq);
  1069. else
  1070. dp_soc_interrupt_map_calculate_msi(soc,
  1071. intr_ctx_num, irq_id_map, num_irq,
  1072. msi_vector_count, msi_vector_start);
  1073. }
  1074. /*
  1075. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  1076. * @txrx_soc: DP SOC handle
  1077. *
  1078. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  1079. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  1080. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  1081. *
  1082. * Return: 0 for success. nonzero for failure.
  1083. */
  1084. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  1085. {
  1086. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1087. int i = 0;
  1088. int num_irq = 0;
  1089. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1090. int ret = 0;
  1091. /* Map of IRQ ids registered with one interrupt context */
  1092. int irq_id_map[HIF_MAX_GRP_IRQ];
  1093. int tx_mask =
  1094. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  1095. int rx_mask =
  1096. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  1097. int rx_mon_mask =
  1098. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  1099. int rx_err_ring_mask =
  1100. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  1101. int rx_wbm_rel_ring_mask =
  1102. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  1103. int reo_status_ring_mask =
  1104. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  1105. int rxdma2host_ring_mask =
  1106. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  1107. int host2rxdma_ring_mask =
  1108. wlan_cfg_get_host2rxdma_ring_mask(soc->wlan_cfg_ctx, i);
  1109. soc->intr_ctx[i].dp_intr_id = i;
  1110. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  1111. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  1112. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  1113. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  1114. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  1115. soc->intr_ctx[i].host2rxdma_ring_mask = host2rxdma_ring_mask;
  1116. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  1117. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  1118. soc->intr_ctx[i].soc = soc;
  1119. num_irq = 0;
  1120. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  1121. &num_irq);
  1122. ret = hif_register_ext_group(soc->hif_handle,
  1123. num_irq, irq_id_map, dp_service_srngs,
  1124. &soc->intr_ctx[i], "dp_intr",
  1125. HIF_EXEC_NAPI_TYPE, QCA_NAPI_DEF_SCALE_BIN_SHIFT);
  1126. if (ret) {
  1127. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1128. FL("failed, ret = %d"), ret);
  1129. return QDF_STATUS_E_FAILURE;
  1130. }
  1131. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  1132. }
  1133. hif_configure_ext_group_interrupts(soc->hif_handle);
  1134. return QDF_STATUS_SUCCESS;
  1135. }
  1136. /*
  1137. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  1138. * @txrx_soc: DP SOC handle
  1139. *
  1140. * Return: void
  1141. */
  1142. static void dp_soc_interrupt_detach(void *txrx_soc)
  1143. {
  1144. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1145. int i;
  1146. if (soc->intr_mode == DP_INTR_POLL) {
  1147. qdf_timer_stop(&soc->int_timer);
  1148. qdf_timer_free(&soc->int_timer);
  1149. } else {
  1150. hif_deregister_exec_group(soc->hif_handle, "dp_intr");
  1151. }
  1152. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1153. soc->intr_ctx[i].tx_ring_mask = 0;
  1154. soc->intr_ctx[i].rx_ring_mask = 0;
  1155. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  1156. soc->intr_ctx[i].rx_err_ring_mask = 0;
  1157. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  1158. soc->intr_ctx[i].reo_status_ring_mask = 0;
  1159. soc->intr_ctx[i].rxdma2host_ring_mask = 0;
  1160. soc->intr_ctx[i].host2rxdma_ring_mask = 0;
  1161. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  1162. }
  1163. }
  1164. #define AVG_MAX_MPDUS_PER_TID 128
  1165. #define AVG_TIDS_PER_CLIENT 2
  1166. #define AVG_FLOWS_PER_TID 2
  1167. #define AVG_MSDUS_PER_FLOW 128
  1168. #define AVG_MSDUS_PER_MPDU 4
  1169. /*
  1170. * Allocate and setup link descriptor pool that will be used by HW for
  1171. * various link and queue descriptors and managed by WBM
  1172. */
  1173. static int dp_hw_link_desc_pool_setup(struct dp_soc *soc)
  1174. {
  1175. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  1176. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  1177. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  1178. uint32_t num_mpdus_per_link_desc =
  1179. hal_num_mpdus_per_link_desc(soc->hal_soc);
  1180. uint32_t num_msdus_per_link_desc =
  1181. hal_num_msdus_per_link_desc(soc->hal_soc);
  1182. uint32_t num_mpdu_links_per_queue_desc =
  1183. hal_num_mpdu_links_per_queue_desc(soc->hal_soc);
  1184. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1185. uint32_t total_link_descs, total_mem_size;
  1186. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  1187. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  1188. uint32_t num_link_desc_banks;
  1189. uint32_t last_bank_size = 0;
  1190. uint32_t entry_size, num_entries;
  1191. int i;
  1192. uint32_t desc_id = 0;
  1193. /* Only Tx queue descriptors are allocated from common link descriptor
  1194. * pool Rx queue descriptors are not included in this because (REO queue
  1195. * extension descriptors) they are expected to be allocated contiguously
  1196. * with REO queue descriptors
  1197. */
  1198. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1199. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  1200. num_mpdu_queue_descs = num_mpdu_link_descs /
  1201. num_mpdu_links_per_queue_desc;
  1202. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1203. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  1204. num_msdus_per_link_desc;
  1205. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1206. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  1207. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  1208. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  1209. /* Round up to power of 2 */
  1210. total_link_descs = 1;
  1211. while (total_link_descs < num_entries)
  1212. total_link_descs <<= 1;
  1213. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1214. FL("total_link_descs: %u, link_desc_size: %d"),
  1215. total_link_descs, link_desc_size);
  1216. total_mem_size = total_link_descs * link_desc_size;
  1217. total_mem_size += link_desc_align;
  1218. if (total_mem_size <= max_alloc_size) {
  1219. num_link_desc_banks = 0;
  1220. last_bank_size = total_mem_size;
  1221. } else {
  1222. num_link_desc_banks = (total_mem_size) /
  1223. (max_alloc_size - link_desc_align);
  1224. last_bank_size = total_mem_size %
  1225. (max_alloc_size - link_desc_align);
  1226. }
  1227. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1228. FL("total_mem_size: %d, num_link_desc_banks: %u"),
  1229. total_mem_size, num_link_desc_banks);
  1230. for (i = 0; i < num_link_desc_banks; i++) {
  1231. soc->link_desc_banks[i].base_vaddr_unaligned =
  1232. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1233. max_alloc_size,
  1234. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1235. soc->link_desc_banks[i].size = max_alloc_size;
  1236. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)(
  1237. soc->link_desc_banks[i].base_vaddr_unaligned) +
  1238. ((unsigned long)(
  1239. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1240. link_desc_align));
  1241. soc->link_desc_banks[i].base_paddr = (unsigned long)(
  1242. soc->link_desc_banks[i].base_paddr_unaligned) +
  1243. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1244. (unsigned long)(
  1245. soc->link_desc_banks[i].base_vaddr_unaligned));
  1246. if (!soc->link_desc_banks[i].base_vaddr_unaligned) {
  1247. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1248. FL("Link descriptor memory alloc failed"));
  1249. goto fail;
  1250. }
  1251. }
  1252. if (last_bank_size) {
  1253. /* Allocate last bank in case total memory required is not exact
  1254. * multiple of max_alloc_size
  1255. */
  1256. soc->link_desc_banks[i].base_vaddr_unaligned =
  1257. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1258. last_bank_size,
  1259. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1260. soc->link_desc_banks[i].size = last_bank_size;
  1261. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)
  1262. (soc->link_desc_banks[i].base_vaddr_unaligned) +
  1263. ((unsigned long)(
  1264. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1265. link_desc_align));
  1266. soc->link_desc_banks[i].base_paddr =
  1267. (unsigned long)(
  1268. soc->link_desc_banks[i].base_paddr_unaligned) +
  1269. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1270. (unsigned long)(
  1271. soc->link_desc_banks[i].base_vaddr_unaligned));
  1272. }
  1273. /* Allocate and setup link descriptor idle list for HW internal use */
  1274. entry_size = hal_srng_get_entrysize(soc->hal_soc, WBM_IDLE_LINK);
  1275. total_mem_size = entry_size * total_link_descs;
  1276. if (total_mem_size <= max_alloc_size) {
  1277. void *desc;
  1278. if (dp_srng_setup(soc, &soc->wbm_idle_link_ring,
  1279. WBM_IDLE_LINK, 0, 0, total_link_descs)) {
  1280. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1281. FL("Link desc idle ring setup failed"));
  1282. goto fail;
  1283. }
  1284. hal_srng_access_start_unlocked(soc->hal_soc,
  1285. soc->wbm_idle_link_ring.hal_srng);
  1286. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1287. soc->link_desc_banks[i].base_paddr; i++) {
  1288. uint32_t num_entries = (soc->link_desc_banks[i].size -
  1289. ((unsigned long)(
  1290. soc->link_desc_banks[i].base_vaddr) -
  1291. (unsigned long)(
  1292. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1293. / link_desc_size;
  1294. unsigned long paddr = (unsigned long)(
  1295. soc->link_desc_banks[i].base_paddr);
  1296. while (num_entries && (desc = hal_srng_src_get_next(
  1297. soc->hal_soc,
  1298. soc->wbm_idle_link_ring.hal_srng))) {
  1299. hal_set_link_desc_addr(desc,
  1300. LINK_DESC_COOKIE(desc_id, i), paddr);
  1301. num_entries--;
  1302. desc_id++;
  1303. paddr += link_desc_size;
  1304. }
  1305. }
  1306. hal_srng_access_end_unlocked(soc->hal_soc,
  1307. soc->wbm_idle_link_ring.hal_srng);
  1308. } else {
  1309. uint32_t num_scatter_bufs;
  1310. uint32_t num_entries_per_buf;
  1311. uint32_t rem_entries;
  1312. uint8_t *scatter_buf_ptr;
  1313. uint16_t scatter_buf_num;
  1314. soc->wbm_idle_scatter_buf_size =
  1315. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1316. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  1317. soc->hal_soc, soc->wbm_idle_scatter_buf_size);
  1318. num_scatter_bufs = hal_idle_list_num_scatter_bufs(
  1319. soc->hal_soc, total_mem_size,
  1320. soc->wbm_idle_scatter_buf_size);
  1321. for (i = 0; i < num_scatter_bufs; i++) {
  1322. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1323. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1324. soc->wbm_idle_scatter_buf_size,
  1325. &(soc->wbm_idle_scatter_buf_base_paddr[i]));
  1326. if (soc->wbm_idle_scatter_buf_base_vaddr[i] == NULL) {
  1327. QDF_TRACE(QDF_MODULE_ID_DP,
  1328. QDF_TRACE_LEVEL_ERROR,
  1329. FL("Scatter list memory alloc failed"));
  1330. goto fail;
  1331. }
  1332. }
  1333. /* Populate idle list scatter buffers with link descriptor
  1334. * pointers
  1335. */
  1336. scatter_buf_num = 0;
  1337. scatter_buf_ptr = (uint8_t *)(
  1338. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  1339. rem_entries = num_entries_per_buf;
  1340. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1341. soc->link_desc_banks[i].base_paddr; i++) {
  1342. uint32_t num_link_descs =
  1343. (soc->link_desc_banks[i].size -
  1344. ((unsigned long)(
  1345. soc->link_desc_banks[i].base_vaddr) -
  1346. (unsigned long)(
  1347. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1348. / link_desc_size;
  1349. unsigned long paddr = (unsigned long)(
  1350. soc->link_desc_banks[i].base_paddr);
  1351. while (num_link_descs) {
  1352. hal_set_link_desc_addr((void *)scatter_buf_ptr,
  1353. LINK_DESC_COOKIE(desc_id, i), paddr);
  1354. num_link_descs--;
  1355. desc_id++;
  1356. paddr += link_desc_size;
  1357. rem_entries--;
  1358. if (rem_entries) {
  1359. scatter_buf_ptr += entry_size;
  1360. } else {
  1361. rem_entries = num_entries_per_buf;
  1362. scatter_buf_num++;
  1363. if (scatter_buf_num >= num_scatter_bufs)
  1364. break;
  1365. scatter_buf_ptr = (uint8_t *)(
  1366. soc->wbm_idle_scatter_buf_base_vaddr[
  1367. scatter_buf_num]);
  1368. }
  1369. }
  1370. }
  1371. /* Setup link descriptor idle list in HW */
  1372. hal_setup_link_idle_list(soc->hal_soc,
  1373. soc->wbm_idle_scatter_buf_base_paddr,
  1374. soc->wbm_idle_scatter_buf_base_vaddr,
  1375. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  1376. (uint32_t)(scatter_buf_ptr -
  1377. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  1378. scatter_buf_num-1])), total_link_descs);
  1379. }
  1380. return 0;
  1381. fail:
  1382. if (soc->wbm_idle_link_ring.hal_srng) {
  1383. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  1384. WBM_IDLE_LINK, 0);
  1385. }
  1386. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1387. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1388. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1389. soc->wbm_idle_scatter_buf_size,
  1390. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1391. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1392. soc->wbm_idle_scatter_buf_base_vaddr[i] = NULL;
  1393. }
  1394. }
  1395. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1396. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1397. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1398. soc->link_desc_banks[i].size,
  1399. soc->link_desc_banks[i].base_vaddr_unaligned,
  1400. soc->link_desc_banks[i].base_paddr_unaligned,
  1401. 0);
  1402. soc->link_desc_banks[i].base_vaddr_unaligned = NULL;
  1403. }
  1404. }
  1405. return QDF_STATUS_E_FAILURE;
  1406. }
  1407. /*
  1408. * Free link descriptor pool that was setup HW
  1409. */
  1410. static void dp_hw_link_desc_pool_cleanup(struct dp_soc *soc)
  1411. {
  1412. int i;
  1413. if (soc->wbm_idle_link_ring.hal_srng) {
  1414. dp_srng_cleanup(soc, &soc->wbm_idle_link_ring,
  1415. WBM_IDLE_LINK, 0);
  1416. }
  1417. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1418. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1419. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1420. soc->wbm_idle_scatter_buf_size,
  1421. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1422. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1423. soc->wbm_idle_scatter_buf_base_vaddr[i] = NULL;
  1424. }
  1425. }
  1426. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1427. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1428. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1429. soc->link_desc_banks[i].size,
  1430. soc->link_desc_banks[i].base_vaddr_unaligned,
  1431. soc->link_desc_banks[i].base_paddr_unaligned,
  1432. 0);
  1433. soc->link_desc_banks[i].base_vaddr_unaligned = NULL;
  1434. }
  1435. }
  1436. }
  1437. /* TODO: Following should be configurable */
  1438. #define WBM_RELEASE_RING_SIZE 64
  1439. #define TCL_CMD_RING_SIZE 32
  1440. #define TCL_STATUS_RING_SIZE 32
  1441. #if defined(QCA_WIFI_QCA6290)
  1442. #define REO_DST_RING_SIZE 1024
  1443. #else
  1444. #define REO_DST_RING_SIZE 2048
  1445. #endif
  1446. #define REO_REINJECT_RING_SIZE 32
  1447. #define RX_RELEASE_RING_SIZE 1024
  1448. #define REO_EXCEPTION_RING_SIZE 128
  1449. #define REO_CMD_RING_SIZE 64
  1450. #define REO_STATUS_RING_SIZE 128
  1451. #define RXDMA_BUF_RING_SIZE 1024
  1452. #define RXDMA_REFILL_RING_SIZE 4096
  1453. #define RXDMA_MONITOR_BUF_RING_SIZE 4096
  1454. #define RXDMA_MONITOR_DST_RING_SIZE 2048
  1455. #define RXDMA_MONITOR_STATUS_RING_SIZE 1024
  1456. #define RXDMA_MONITOR_DESC_RING_SIZE 4096
  1457. #define RXDMA_ERR_DST_RING_SIZE 1024
  1458. /*
  1459. * dp_wds_aging_timer_fn() - Timer callback function for WDS aging
  1460. * @soc: Datapath SOC handle
  1461. *
  1462. * This is a timer function used to age out stale AST nodes from
  1463. * AST table
  1464. */
  1465. #ifdef FEATURE_WDS
  1466. static void dp_wds_aging_timer_fn(void *soc_hdl)
  1467. {
  1468. struct dp_soc *soc = (struct dp_soc *) soc_hdl;
  1469. struct dp_pdev *pdev;
  1470. struct dp_vdev *vdev;
  1471. struct dp_peer *peer;
  1472. struct dp_ast_entry *ase, *temp_ase;
  1473. int i;
  1474. qdf_spin_lock_bh(&soc->ast_lock);
  1475. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  1476. pdev = soc->pdev_list[i];
  1477. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  1478. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  1479. DP_PEER_ITERATE_ASE_LIST(peer, ase, temp_ase) {
  1480. /*
  1481. * Do not expire static ast entries
  1482. * and HM WDS entries
  1483. */
  1484. if (ase->type ==
  1485. CDP_TXRX_AST_TYPE_STATIC ||
  1486. ase->type ==
  1487. CDP_TXRX_AST_TYPE_WDS_HM)
  1488. continue;
  1489. if (ase->is_active) {
  1490. ase->is_active = FALSE;
  1491. continue;
  1492. }
  1493. DP_STATS_INC(soc, ast.aged_out, 1);
  1494. dp_peer_del_ast(soc, ase);
  1495. }
  1496. }
  1497. }
  1498. }
  1499. qdf_spin_unlock_bh(&soc->ast_lock);
  1500. if (qdf_atomic_read(&soc->cmn_init_done))
  1501. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1502. }
  1503. /*
  1504. * dp_soc_wds_attach() - Setup WDS timer and AST table
  1505. * @soc: Datapath SOC handle
  1506. *
  1507. * Return: None
  1508. */
  1509. static void dp_soc_wds_attach(struct dp_soc *soc)
  1510. {
  1511. qdf_timer_init(soc->osdev, &soc->wds_aging_timer,
  1512. dp_wds_aging_timer_fn, (void *)soc,
  1513. QDF_TIMER_TYPE_WAKE_APPS);
  1514. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1515. }
  1516. /*
  1517. * dp_soc_wds_detach() - Detach WDS data structures and timers
  1518. * @txrx_soc: DP SOC handle
  1519. *
  1520. * Return: None
  1521. */
  1522. static void dp_soc_wds_detach(struct dp_soc *soc)
  1523. {
  1524. qdf_timer_stop(&soc->wds_aging_timer);
  1525. qdf_timer_free(&soc->wds_aging_timer);
  1526. }
  1527. #else
  1528. static void dp_soc_wds_attach(struct dp_soc *soc)
  1529. {
  1530. }
  1531. static void dp_soc_wds_detach(struct dp_soc *soc)
  1532. {
  1533. }
  1534. #endif
  1535. /*
  1536. * dp_soc_reset_ring_map() - Reset cpu ring map
  1537. * @soc: Datapath soc handler
  1538. *
  1539. * This api resets the default cpu ring map
  1540. */
  1541. static void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  1542. {
  1543. uint8_t i;
  1544. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1545. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  1546. if (nss_config == 1) {
  1547. /*
  1548. * Setting Tx ring map for one nss offloaded radio
  1549. */
  1550. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  1551. } else if (nss_config == 2) {
  1552. /*
  1553. * Setting Tx ring for two nss offloaded radios
  1554. */
  1555. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  1556. } else {
  1557. /*
  1558. * Setting Tx ring map for all nss offloaded radios
  1559. */
  1560. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_ALL_RADIO_OFFLOADED_MAP][i];
  1561. }
  1562. }
  1563. }
  1564. /*
  1565. * dp_soc_ring_if_nss_offloaded() - find if ring is offloaded to NSS
  1566. * @dp_soc - DP soc handle
  1567. * @ring_type - ring type
  1568. * @ring_num - ring_num
  1569. *
  1570. * return 0 or 1
  1571. */
  1572. static uint8_t dp_soc_ring_if_nss_offloaded(struct dp_soc *soc, enum hal_ring_type ring_type, int ring_num)
  1573. {
  1574. uint8_t nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1575. uint8_t status = 0;
  1576. switch (ring_type) {
  1577. case WBM2SW_RELEASE:
  1578. case REO_DST:
  1579. case RXDMA_BUF:
  1580. status = ((nss_config) & (1 << ring_num));
  1581. break;
  1582. default:
  1583. break;
  1584. }
  1585. return status;
  1586. }
  1587. /*
  1588. * dp_soc_reset_intr_mask() - reset interrupt mask
  1589. * @dp_soc - DP Soc handle
  1590. *
  1591. * Return: Return void
  1592. */
  1593. static void dp_soc_reset_intr_mask(struct dp_soc *soc)
  1594. {
  1595. uint8_t j;
  1596. int *grp_mask = NULL;
  1597. int group_number, mask, num_ring;
  1598. /* number of tx ring */
  1599. num_ring = wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1600. /*
  1601. * group mask for tx completion ring.
  1602. */
  1603. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  1604. /* loop and reset the mask for only offloaded ring */
  1605. for (j = 0; j < num_ring; j++) {
  1606. if (!dp_soc_ring_if_nss_offloaded(soc, WBM2SW_RELEASE, j)) {
  1607. continue;
  1608. }
  1609. /*
  1610. * Group number corresponding to tx offloaded ring.
  1611. */
  1612. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  1613. if (group_number < 0) {
  1614. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1615. FL("ring not part of any group; ring_type: %d,ring_num %d"),
  1616. WBM2SW_RELEASE, j);
  1617. return;
  1618. }
  1619. /* reset the tx mask for offloaded ring */
  1620. mask = wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, group_number);
  1621. mask &= (~(1 << j));
  1622. /*
  1623. * reset the interrupt mask for offloaded ring.
  1624. */
  1625. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  1626. }
  1627. /* number of rx rings */
  1628. num_ring = wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1629. /*
  1630. * group mask for reo destination ring.
  1631. */
  1632. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  1633. /* loop and reset the mask for only offloaded ring */
  1634. for (j = 0; j < num_ring; j++) {
  1635. if (!dp_soc_ring_if_nss_offloaded(soc, REO_DST, j)) {
  1636. continue;
  1637. }
  1638. /*
  1639. * Group number corresponding to rx offloaded ring.
  1640. */
  1641. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  1642. if (group_number < 0) {
  1643. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1644. FL("ring not part of any group; ring_type: %d,ring_num %d"),
  1645. REO_DST, j);
  1646. return;
  1647. }
  1648. /* set the interrupt mask for offloaded ring */
  1649. mask = wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, group_number);
  1650. mask &= (~(1 << j));
  1651. /*
  1652. * set the interrupt mask to zero for rx offloaded radio.
  1653. */
  1654. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  1655. }
  1656. /*
  1657. * group mask for Rx buffer refill ring
  1658. */
  1659. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_ring_mask[0];
  1660. /* loop and reset the mask for only offloaded ring */
  1661. for (j = 0; j < MAX_PDEV_CNT; j++) {
  1662. if (!dp_soc_ring_if_nss_offloaded(soc, RXDMA_BUF, j)) {
  1663. continue;
  1664. }
  1665. /*
  1666. * Group number corresponding to rx offloaded ring.
  1667. */
  1668. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  1669. if (group_number < 0) {
  1670. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1671. FL("ring not part of any group; ring_type: %d,ring_num %d"),
  1672. REO_DST, j);
  1673. return;
  1674. }
  1675. /* set the interrupt mask for offloaded ring */
  1676. mask = wlan_cfg_get_host2rxdma_ring_mask(soc->wlan_cfg_ctx,
  1677. group_number);
  1678. mask &= (~(1 << j));
  1679. /*
  1680. * set the interrupt mask to zero for rx offloaded radio.
  1681. */
  1682. wlan_cfg_set_host2rxdma_ring_mask(soc->wlan_cfg_ctx,
  1683. group_number, mask);
  1684. }
  1685. }
  1686. #ifdef IPA_OFFLOAD
  1687. /**
  1688. * dp_reo_remap_config() - configure reo remap register value based
  1689. * nss configuration.
  1690. * based on offload_radio value below remap configuration
  1691. * get applied.
  1692. * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4)
  1693. * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4)
  1694. * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4)
  1695. * 3 - both Radios handled by NSS (remap not required)
  1696. * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3)
  1697. *
  1698. * @remap1: output parameter indicates reo remap 1 register value
  1699. * @remap2: output parameter indicates reo remap 2 register value
  1700. * Return: bool type, true if remap is configured else false.
  1701. */
  1702. static bool dp_reo_remap_config(struct dp_soc *soc,
  1703. uint32_t *remap1,
  1704. uint32_t *remap2)
  1705. {
  1706. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) | (0x1 << 9) |
  1707. (0x2 << 12) | (0x3 << 15) | (0x1 << 18) | (0x2 << 21)) << 8;
  1708. *remap2 = ((0x3 << 0) | (0x1 << 3) | (0x2 << 6) | (0x3 << 9) |
  1709. (0x1 << 12) | (0x2 << 15) | (0x3 << 18) | (0x1 << 21)) << 8;
  1710. return true;
  1711. }
  1712. #else
  1713. static bool dp_reo_remap_config(struct dp_soc *soc,
  1714. uint32_t *remap1,
  1715. uint32_t *remap2)
  1716. {
  1717. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1718. switch (offload_radio) {
  1719. case 0:
  1720. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1721. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1722. (0x3 << 18) | (0x4 << 21)) << 8;
  1723. *remap2 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1724. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1725. (0x3 << 18) | (0x4 << 21)) << 8;
  1726. break;
  1727. case 1:
  1728. *remap1 = ((0x2 << 0) | (0x3 << 3) | (0x4 << 6) |
  1729. (0x2 << 9) | (0x3 << 12) | (0x4 << 15) |
  1730. (0x2 << 18) | (0x3 << 21)) << 8;
  1731. *remap2 = ((0x4 << 0) | (0x2 << 3) | (0x3 << 6) |
  1732. (0x4 << 9) | (0x2 << 12) | (0x3 << 15) |
  1733. (0x4 << 18) | (0x2 << 21)) << 8;
  1734. break;
  1735. case 2:
  1736. *remap1 = ((0x1 << 0) | (0x3 << 3) | (0x4 << 6) |
  1737. (0x1 << 9) | (0x3 << 12) | (0x4 << 15) |
  1738. (0x1 << 18) | (0x3 << 21)) << 8;
  1739. *remap2 = ((0x4 << 0) | (0x1 << 3) | (0x3 << 6) |
  1740. (0x4 << 9) | (0x1 << 12) | (0x3 << 15) |
  1741. (0x4 << 18) | (0x1 << 21)) << 8;
  1742. break;
  1743. case 3:
  1744. /* return false if both radios are offloaded to NSS */
  1745. return false;
  1746. }
  1747. return true;
  1748. }
  1749. #endif
  1750. /*
  1751. * dp_reo_frag_dst_set() - configure reo register to set the
  1752. * fragment destination ring
  1753. * @soc : Datapath soc
  1754. * @frag_dst_ring : output parameter to set fragment destination ring
  1755. *
  1756. * Based on offload_radio below fragment destination rings is selected
  1757. * 0 - TCL
  1758. * 1 - SW1
  1759. * 2 - SW2
  1760. * 3 - SW3
  1761. * 4 - SW4
  1762. * 5 - Release
  1763. * 6 - FW
  1764. * 7 - alternate select
  1765. *
  1766. * return: void
  1767. */
  1768. static void dp_reo_frag_dst_set(struct dp_soc *soc, uint8_t *frag_dst_ring)
  1769. {
  1770. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1771. switch (offload_radio) {
  1772. case 0:
  1773. *frag_dst_ring = HAL_SRNG_REO_EXCEPTION;
  1774. break;
  1775. case 3:
  1776. *frag_dst_ring = HAL_SRNG_REO_ALTERNATE_SELECT;
  1777. break;
  1778. default:
  1779. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1780. FL("dp_reo_frag_dst_set invalid offload radio config"));
  1781. break;
  1782. }
  1783. }
  1784. /*
  1785. * dp_soc_cmn_setup() - Common SoC level initializion
  1786. * @soc: Datapath SOC handle
  1787. *
  1788. * This is an internal function used to setup common SOC data structures,
  1789. * to be called from PDEV attach after receiving HW mode capabilities from FW
  1790. */
  1791. static int dp_soc_cmn_setup(struct dp_soc *soc)
  1792. {
  1793. int i;
  1794. struct hal_reo_params reo_params;
  1795. int tx_ring_size;
  1796. int tx_comp_ring_size;
  1797. if (qdf_atomic_read(&soc->cmn_init_done))
  1798. return 0;
  1799. if (dp_peer_find_attach(soc))
  1800. goto fail0;
  1801. if (dp_hw_link_desc_pool_setup(soc))
  1802. goto fail1;
  1803. /* Setup SRNG rings */
  1804. /* Common rings */
  1805. if (dp_srng_setup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0,
  1806. WBM_RELEASE_RING_SIZE)) {
  1807. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1808. FL("dp_srng_setup failed for wbm_desc_rel_ring"));
  1809. goto fail1;
  1810. }
  1811. soc->num_tcl_data_rings = 0;
  1812. /* Tx data rings */
  1813. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1814. soc->num_tcl_data_rings =
  1815. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1816. tx_comp_ring_size =
  1817. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1818. tx_ring_size =
  1819. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1820. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  1821. if (dp_srng_setup(soc, &soc->tcl_data_ring[i],
  1822. TCL_DATA, i, 0, tx_ring_size)) {
  1823. QDF_TRACE(QDF_MODULE_ID_DP,
  1824. QDF_TRACE_LEVEL_ERROR,
  1825. FL("dp_srng_setup failed for tcl_data_ring[%d]"), i);
  1826. goto fail1;
  1827. }
  1828. /*
  1829. * TBD: Set IPA WBM ring size with ini IPA UC tx buffer
  1830. * count
  1831. */
  1832. if (dp_srng_setup(soc, &soc->tx_comp_ring[i],
  1833. WBM2SW_RELEASE, i, 0, tx_comp_ring_size)) {
  1834. QDF_TRACE(QDF_MODULE_ID_DP,
  1835. QDF_TRACE_LEVEL_ERROR,
  1836. FL("dp_srng_setup failed for tx_comp_ring[%d]"), i);
  1837. goto fail1;
  1838. }
  1839. }
  1840. } else {
  1841. /* This will be incremented during per pdev ring setup */
  1842. soc->num_tcl_data_rings = 0;
  1843. }
  1844. if (dp_tx_soc_attach(soc)) {
  1845. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1846. FL("dp_tx_soc_attach failed"));
  1847. goto fail1;
  1848. }
  1849. /* TCL command and status rings */
  1850. if (dp_srng_setup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0, 0,
  1851. TCL_CMD_RING_SIZE)) {
  1852. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1853. FL("dp_srng_setup failed for tcl_cmd_ring"));
  1854. goto fail1;
  1855. }
  1856. if (dp_srng_setup(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0,
  1857. TCL_STATUS_RING_SIZE)) {
  1858. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1859. FL("dp_srng_setup failed for tcl_status_ring"));
  1860. goto fail1;
  1861. }
  1862. /* TBD: call dp_tx_init to setup Tx SW descriptors and MSDU extension
  1863. * descriptors
  1864. */
  1865. /* Rx data rings */
  1866. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1867. soc->num_reo_dest_rings =
  1868. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1869. QDF_TRACE(QDF_MODULE_ID_DP,
  1870. QDF_TRACE_LEVEL_ERROR,
  1871. FL("num_reo_dest_rings %d\n"), soc->num_reo_dest_rings);
  1872. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  1873. if (dp_srng_setup(soc, &soc->reo_dest_ring[i], REO_DST,
  1874. i, 0, REO_DST_RING_SIZE)) {
  1875. QDF_TRACE(QDF_MODULE_ID_DP,
  1876. QDF_TRACE_LEVEL_ERROR,
  1877. FL("dp_srng_setup failed for reo_dest_ring[%d]"), i);
  1878. goto fail1;
  1879. }
  1880. }
  1881. } else {
  1882. /* This will be incremented during per pdev ring setup */
  1883. soc->num_reo_dest_rings = 0;
  1884. }
  1885. /* LMAC RxDMA to SW Rings configuration */
  1886. if (!wlan_cfg_per_pdev_lmac_ring(soc->wlan_cfg_ctx)) {
  1887. /* Only valid for MCL */
  1888. struct dp_pdev *pdev = soc->pdev_list[0];
  1889. for (i = 0; i < MAX_RX_MAC_RINGS; i++) {
  1890. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring[i],
  1891. RXDMA_DST, 0, i, RXDMA_ERR_DST_RING_SIZE)) {
  1892. QDF_TRACE(QDF_MODULE_ID_DP,
  1893. QDF_TRACE_LEVEL_ERROR,
  1894. FL("dp_srng_setup failed for rxdma_err_dst_ring"));
  1895. goto fail1;
  1896. }
  1897. }
  1898. }
  1899. /* TBD: call dp_rx_init to setup Rx SW descriptors */
  1900. /* REO reinjection ring */
  1901. if (dp_srng_setup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0,
  1902. REO_REINJECT_RING_SIZE)) {
  1903. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1904. FL("dp_srng_setup failed for reo_reinject_ring"));
  1905. goto fail1;
  1906. }
  1907. /* Rx release ring */
  1908. if (dp_srng_setup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 3, 0,
  1909. RX_RELEASE_RING_SIZE)) {
  1910. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1911. FL("dp_srng_setup failed for rx_rel_ring"));
  1912. goto fail1;
  1913. }
  1914. /* Rx exception ring */
  1915. if (dp_srng_setup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0,
  1916. MAX_REO_DEST_RINGS, REO_EXCEPTION_RING_SIZE)) {
  1917. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1918. FL("dp_srng_setup failed for reo_exception_ring"));
  1919. goto fail1;
  1920. }
  1921. /* REO command and status rings */
  1922. if (dp_srng_setup(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0,
  1923. REO_CMD_RING_SIZE)) {
  1924. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1925. FL("dp_srng_setup failed for reo_cmd_ring"));
  1926. goto fail1;
  1927. }
  1928. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  1929. TAILQ_INIT(&soc->rx.reo_cmd_list);
  1930. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  1931. if (dp_srng_setup(soc, &soc->reo_status_ring, REO_STATUS, 0, 0,
  1932. REO_STATUS_RING_SIZE)) {
  1933. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1934. FL("dp_srng_setup failed for reo_status_ring"));
  1935. goto fail1;
  1936. }
  1937. qdf_spinlock_create(&soc->ast_lock);
  1938. dp_soc_wds_attach(soc);
  1939. /* Reset the cpu ring map if radio is NSS offloaded */
  1940. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  1941. dp_soc_reset_cpu_ring_map(soc);
  1942. dp_soc_reset_intr_mask(soc);
  1943. }
  1944. /* Setup HW REO */
  1945. qdf_mem_zero(&reo_params, sizeof(reo_params));
  1946. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1947. /*
  1948. * Reo ring remap is not required if both radios
  1949. * are offloaded to NSS
  1950. */
  1951. if (!dp_reo_remap_config(soc,
  1952. &reo_params.remap1,
  1953. &reo_params.remap2))
  1954. goto out;
  1955. reo_params.rx_hash_enabled = true;
  1956. }
  1957. /* setup the global rx defrag waitlist */
  1958. TAILQ_INIT(&soc->rx.defrag.waitlist);
  1959. soc->rx.defrag.timeout_ms =
  1960. wlan_cfg_get_rx_defrag_min_timeout(soc->wlan_cfg_ctx);
  1961. soc->rx.flags.defrag_timeout_check =
  1962. wlan_cfg_get_defrag_timeout_check(soc->wlan_cfg_ctx);
  1963. out:
  1964. /*
  1965. * set the fragment destination ring
  1966. */
  1967. dp_reo_frag_dst_set(soc, &reo_params.frag_dst_ring);
  1968. hal_reo_setup(soc->hal_soc, &reo_params);
  1969. qdf_atomic_set(&soc->cmn_init_done, 1);
  1970. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  1971. return 0;
  1972. fail1:
  1973. /*
  1974. * Cleanup will be done as part of soc_detach, which will
  1975. * be called on pdev attach failure
  1976. */
  1977. fail0:
  1978. return QDF_STATUS_E_FAILURE;
  1979. }
  1980. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force);
  1981. static void dp_lro_hash_setup(struct dp_soc *soc)
  1982. {
  1983. struct cdp_lro_hash_config lro_hash;
  1984. if (!wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  1985. !wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1986. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1987. FL("LRO disabled RX hash disabled"));
  1988. return;
  1989. }
  1990. qdf_mem_zero(&lro_hash, sizeof(lro_hash));
  1991. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx)) {
  1992. lro_hash.lro_enable = 1;
  1993. lro_hash.tcp_flag = QDF_TCPHDR_ACK;
  1994. lro_hash.tcp_flag_mask = QDF_TCPHDR_FIN | QDF_TCPHDR_SYN |
  1995. QDF_TCPHDR_RST | QDF_TCPHDR_ACK | QDF_TCPHDR_URG |
  1996. QDF_TCPHDR_ECE | QDF_TCPHDR_CWR;
  1997. }
  1998. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW, FL("enabled"));
  1999. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv4,
  2000. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  2001. LRO_IPV4_SEED_ARR_SZ));
  2002. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv6,
  2003. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  2004. LRO_IPV6_SEED_ARR_SZ));
  2005. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  2006. "lro_hash: lro_enable: 0x%x tcp_flag 0x%x tcp_flag_mask 0x%x",
  2007. lro_hash.lro_enable, lro_hash.tcp_flag,
  2008. lro_hash.tcp_flag_mask);
  2009. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  2010. QDF_TRACE_LEVEL_ERROR,
  2011. (void *)lro_hash.toeplitz_hash_ipv4,
  2012. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  2013. LRO_IPV4_SEED_ARR_SZ));
  2014. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  2015. QDF_TRACE_LEVEL_ERROR,
  2016. (void *)lro_hash.toeplitz_hash_ipv6,
  2017. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  2018. LRO_IPV6_SEED_ARR_SZ));
  2019. qdf_assert(soc->cdp_soc.ol_ops->lro_hash_config);
  2020. if (soc->cdp_soc.ol_ops->lro_hash_config)
  2021. (void)soc->cdp_soc.ol_ops->lro_hash_config
  2022. (soc->ctrl_psoc, &lro_hash);
  2023. }
  2024. /*
  2025. * dp_rxdma_ring_setup() - configure the RX DMA rings
  2026. * @soc: data path SoC handle
  2027. * @pdev: Physical device handle
  2028. *
  2029. * Return: 0 - success, > 0 - failure
  2030. */
  2031. #ifdef QCA_HOST2FW_RXBUF_RING
  2032. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  2033. struct dp_pdev *pdev)
  2034. {
  2035. int max_mac_rings =
  2036. wlan_cfg_get_num_mac_rings
  2037. (pdev->wlan_cfg_ctx);
  2038. int i;
  2039. for (i = 0; i < max_mac_rings; i++) {
  2040. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2041. "%s: pdev_id %d mac_id %d\n",
  2042. __func__, pdev->pdev_id, i);
  2043. if (dp_srng_setup(soc, &pdev->rx_mac_buf_ring[i],
  2044. RXDMA_BUF, 1, i, RXDMA_BUF_RING_SIZE)) {
  2045. QDF_TRACE(QDF_MODULE_ID_DP,
  2046. QDF_TRACE_LEVEL_ERROR,
  2047. FL("failed rx mac ring setup"));
  2048. return QDF_STATUS_E_FAILURE;
  2049. }
  2050. }
  2051. return QDF_STATUS_SUCCESS;
  2052. }
  2053. #else
  2054. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  2055. struct dp_pdev *pdev)
  2056. {
  2057. return QDF_STATUS_SUCCESS;
  2058. }
  2059. #endif
  2060. /**
  2061. * dp_dscp_tid_map_setup(): Initialize the dscp-tid maps
  2062. * @pdev - DP_PDEV handle
  2063. *
  2064. * Return: void
  2065. */
  2066. static inline void
  2067. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  2068. {
  2069. uint8_t map_id;
  2070. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  2071. qdf_mem_copy(pdev->dscp_tid_map[map_id], default_dscp_tid_map,
  2072. sizeof(default_dscp_tid_map));
  2073. }
  2074. for (map_id = 0; map_id < HAL_MAX_HW_DSCP_TID_MAPS; map_id++) {
  2075. hal_tx_set_dscp_tid_map(pdev->soc->hal_soc,
  2076. pdev->dscp_tid_map[map_id],
  2077. map_id);
  2078. }
  2079. }
  2080. #ifdef QCA_SUPPORT_SON
  2081. /**
  2082. * dp_mark_peer_inact(): Update peer inactivity status
  2083. * @peer_handle - datapath peer handle
  2084. *
  2085. * Return: void
  2086. */
  2087. void dp_mark_peer_inact(void *peer_handle, bool inactive)
  2088. {
  2089. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2090. struct dp_pdev *pdev;
  2091. struct dp_soc *soc;
  2092. bool inactive_old;
  2093. if (!peer)
  2094. return;
  2095. pdev = peer->vdev->pdev;
  2096. soc = pdev->soc;
  2097. inactive_old = peer->peer_bs_inact_flag == 1;
  2098. if (!inactive)
  2099. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  2100. peer->peer_bs_inact_flag = inactive ? 1 : 0;
  2101. if (inactive_old != inactive) {
  2102. /**
  2103. * Note: a node lookup can happen in RX datapath context
  2104. * when a node changes from inactive to active (at most once
  2105. * per inactivity timeout threshold)
  2106. */
  2107. if (soc->cdp_soc.ol_ops->record_act_change) {
  2108. soc->cdp_soc.ol_ops->record_act_change(pdev->osif_pdev,
  2109. peer->mac_addr.raw, !inactive);
  2110. }
  2111. }
  2112. }
  2113. /**
  2114. * dp_txrx_peer_find_inact_timeout_handler(): Inactivity timeout function
  2115. *
  2116. * Periodically checks the inactivity status
  2117. */
  2118. static os_timer_func(dp_txrx_peer_find_inact_timeout_handler)
  2119. {
  2120. struct dp_pdev *pdev;
  2121. struct dp_vdev *vdev;
  2122. struct dp_peer *peer;
  2123. struct dp_soc *soc;
  2124. int i;
  2125. OS_GET_TIMER_ARG(soc, struct dp_soc *);
  2126. qdf_spin_lock(&soc->peer_ref_mutex);
  2127. for (i = 0; i < soc->pdev_count; i++) {
  2128. pdev = soc->pdev_list[i];
  2129. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  2130. if (vdev->opmode != wlan_op_mode_ap)
  2131. continue;
  2132. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2133. if (!peer->authorize) {
  2134. /**
  2135. * Inactivity check only interested in
  2136. * connected node
  2137. */
  2138. continue;
  2139. }
  2140. if (peer->peer_bs_inact > soc->pdev_bs_inact_reload) {
  2141. /**
  2142. * This check ensures we do not wait extra long
  2143. * due to the potential race condition
  2144. */
  2145. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  2146. }
  2147. if (peer->peer_bs_inact > 0) {
  2148. /* Do not let it wrap around */
  2149. peer->peer_bs_inact--;
  2150. }
  2151. if (peer->peer_bs_inact == 0)
  2152. dp_mark_peer_inact(peer, true);
  2153. }
  2154. }
  2155. }
  2156. qdf_spin_unlock(&soc->peer_ref_mutex);
  2157. qdf_timer_mod(&soc->pdev_bs_inact_timer,
  2158. soc->pdev_bs_inact_interval * 1000);
  2159. }
  2160. /**
  2161. * dp_free_inact_timer(): free inact timer
  2162. * @timer - inact timer handle
  2163. *
  2164. * Return: bool
  2165. */
  2166. void dp_free_inact_timer(struct dp_soc *soc)
  2167. {
  2168. qdf_timer_free(&soc->pdev_bs_inact_timer);
  2169. }
  2170. #else
  2171. void dp_mark_peer_inact(void *peer, bool inactive)
  2172. {
  2173. return;
  2174. }
  2175. void dp_free_inact_timer(struct dp_soc *soc)
  2176. {
  2177. return;
  2178. }
  2179. #endif
  2180. #ifdef IPA_OFFLOAD
  2181. /**
  2182. * dp_setup_ipa_rx_refill_buf_ring - Setup second Rx refill buffer ring
  2183. * @soc: data path instance
  2184. * @pdev: core txrx pdev context
  2185. *
  2186. * Return: QDF_STATUS_SUCCESS: success
  2187. * QDF_STATUS_E_RESOURCES: Error return
  2188. */
  2189. static int dp_setup_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2190. struct dp_pdev *pdev)
  2191. {
  2192. /* Setup second Rx refill buffer ring */
  2193. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring2, RXDMA_BUF,
  2194. IPA_RX_REFILL_BUF_RING_IDX,
  2195. pdev->pdev_id, RXDMA_REFILL_RING_SIZE)) {
  2196. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2197. FL("dp_srng_setup failed second rx refill ring"));
  2198. return QDF_STATUS_E_FAILURE;
  2199. }
  2200. return QDF_STATUS_SUCCESS;
  2201. }
  2202. /**
  2203. * dp_cleanup_ipa_rx_refill_buf_ring - Cleanup second Rx refill buffer ring
  2204. * @soc: data path instance
  2205. * @pdev: core txrx pdev context
  2206. *
  2207. * Return: void
  2208. */
  2209. static void dp_cleanup_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2210. struct dp_pdev *pdev)
  2211. {
  2212. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring2, RXDMA_BUF,
  2213. IPA_RX_REFILL_BUF_RING_IDX);
  2214. }
  2215. #else
  2216. static int dp_setup_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2217. struct dp_pdev *pdev)
  2218. {
  2219. return QDF_STATUS_SUCCESS;
  2220. }
  2221. static void dp_cleanup_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2222. struct dp_pdev *pdev)
  2223. {
  2224. }
  2225. #endif
  2226. /*
  2227. * dp_pdev_attach_wifi3() - attach txrx pdev
  2228. * @ctrl_pdev: Opaque PDEV object
  2229. * @txrx_soc: Datapath SOC handle
  2230. * @htc_handle: HTC handle for host-target interface
  2231. * @qdf_osdev: QDF OS device
  2232. * @pdev_id: PDEV ID
  2233. *
  2234. * Return: DP PDEV handle on success, NULL on failure
  2235. */
  2236. static struct cdp_pdev *dp_pdev_attach_wifi3(struct cdp_soc_t *txrx_soc,
  2237. struct cdp_cfg *ctrl_pdev,
  2238. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev, uint8_t pdev_id)
  2239. {
  2240. int tx_ring_size;
  2241. int tx_comp_ring_size;
  2242. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2243. struct dp_pdev *pdev = qdf_mem_malloc(sizeof(*pdev));
  2244. int mac_id;
  2245. if (!pdev) {
  2246. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2247. FL("DP PDEV memory allocation failed"));
  2248. goto fail0;
  2249. }
  2250. pdev->wlan_cfg_ctx = wlan_cfg_pdev_attach();
  2251. if (!pdev->wlan_cfg_ctx) {
  2252. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2253. FL("pdev cfg_attach failed"));
  2254. qdf_mem_free(pdev);
  2255. goto fail0;
  2256. }
  2257. /*
  2258. * set nss pdev config based on soc config
  2259. */
  2260. wlan_cfg_set_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx,
  2261. (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx) & (1 << pdev_id)));
  2262. pdev->soc = soc;
  2263. pdev->osif_pdev = ctrl_pdev;
  2264. pdev->pdev_id = pdev_id;
  2265. soc->pdev_list[pdev_id] = pdev;
  2266. soc->pdev_count++;
  2267. TAILQ_INIT(&pdev->vdev_list);
  2268. pdev->vdev_count = 0;
  2269. qdf_spinlock_create(&pdev->tx_mutex);
  2270. qdf_spinlock_create(&pdev->neighbour_peer_mutex);
  2271. TAILQ_INIT(&pdev->neighbour_peers_list);
  2272. if (dp_soc_cmn_setup(soc)) {
  2273. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2274. FL("dp_soc_cmn_setup failed"));
  2275. goto fail1;
  2276. }
  2277. /* Setup per PDEV TCL rings if configured */
  2278. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2279. tx_ring_size =
  2280. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2281. tx_comp_ring_size =
  2282. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  2283. if (dp_srng_setup(soc, &soc->tcl_data_ring[pdev_id], TCL_DATA,
  2284. pdev_id, pdev_id, tx_ring_size)) {
  2285. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2286. FL("dp_srng_setup failed for tcl_data_ring"));
  2287. goto fail1;
  2288. }
  2289. if (dp_srng_setup(soc, &soc->tx_comp_ring[pdev_id],
  2290. WBM2SW_RELEASE, pdev_id, pdev_id, tx_comp_ring_size)) {
  2291. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2292. FL("dp_srng_setup failed for tx_comp_ring"));
  2293. goto fail1;
  2294. }
  2295. soc->num_tcl_data_rings++;
  2296. }
  2297. /* Tx specific init */
  2298. if (dp_tx_pdev_attach(pdev)) {
  2299. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2300. FL("dp_tx_pdev_attach failed"));
  2301. goto fail1;
  2302. }
  2303. /* Setup per PDEV REO rings if configured */
  2304. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2305. if (dp_srng_setup(soc, &soc->reo_dest_ring[pdev_id], REO_DST,
  2306. pdev_id, pdev_id, REO_DST_RING_SIZE)) {
  2307. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2308. FL("dp_srng_setup failed for reo_dest_ringn"));
  2309. goto fail1;
  2310. }
  2311. soc->num_reo_dest_rings++;
  2312. }
  2313. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0, pdev_id,
  2314. RXDMA_REFILL_RING_SIZE)) {
  2315. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2316. FL("dp_srng_setup failed rx refill ring"));
  2317. goto fail1;
  2318. }
  2319. if (dp_rxdma_ring_setup(soc, pdev)) {
  2320. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2321. FL("RXDMA ring config failed"));
  2322. goto fail1;
  2323. }
  2324. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  2325. int mac_for_pdev = dp_get_mac_id_for_pdev(mac_id, pdev_id);
  2326. if (dp_srng_setup(soc, &pdev->rxdma_mon_buf_ring[mac_id],
  2327. RXDMA_MONITOR_BUF, 0, mac_for_pdev,
  2328. RXDMA_MONITOR_BUF_RING_SIZE)) {
  2329. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2330. FL("dp_srng_setup failed for rxdma_mon_buf_ring"));
  2331. goto fail1;
  2332. }
  2333. if (dp_srng_setup(soc, &pdev->rxdma_mon_dst_ring[mac_id],
  2334. RXDMA_MONITOR_DST, 0, mac_for_pdev,
  2335. RXDMA_MONITOR_DST_RING_SIZE)) {
  2336. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2337. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  2338. goto fail1;
  2339. }
  2340. if (dp_srng_setup(soc, &pdev->rxdma_mon_status_ring[mac_id],
  2341. RXDMA_MONITOR_STATUS, 0, mac_for_pdev,
  2342. RXDMA_MONITOR_STATUS_RING_SIZE)) {
  2343. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2344. FL("dp_srng_setup failed for rxdma_mon_status_ring"));
  2345. goto fail1;
  2346. }
  2347. if (dp_srng_setup(soc, &pdev->rxdma_mon_desc_ring[mac_id],
  2348. RXDMA_MONITOR_DESC, 0, mac_for_pdev,
  2349. RXDMA_MONITOR_DESC_RING_SIZE)) {
  2350. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2351. "dp_srng_setup failed for rxdma_mon_desc_ring\n");
  2352. goto fail1;
  2353. }
  2354. }
  2355. if (wlan_cfg_per_pdev_lmac_ring(soc->wlan_cfg_ctx)) {
  2356. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring[0], RXDMA_DST,
  2357. 0, pdev_id, RXDMA_ERR_DST_RING_SIZE)) {
  2358. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2359. FL("dp_srng_setup failed for rxdma_err_dst_ring"));
  2360. goto fail1;
  2361. }
  2362. }
  2363. if (dp_setup_ipa_rx_refill_buf_ring(soc, pdev))
  2364. goto fail1;
  2365. if (dp_ipa_ring_resource_setup(soc, pdev))
  2366. goto fail1;
  2367. if (dp_ipa_uc_attach(soc, pdev) != QDF_STATUS_SUCCESS) {
  2368. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2369. FL("dp_ipa_uc_attach failed"));
  2370. goto fail1;
  2371. }
  2372. /* Rx specific init */
  2373. if (dp_rx_pdev_attach(pdev)) {
  2374. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2375. FL("dp_rx_pdev_attach failed"));
  2376. goto fail0;
  2377. }
  2378. DP_STATS_INIT(pdev);
  2379. /* Monitor filter init */
  2380. pdev->mon_filter_mode = MON_FILTER_ALL;
  2381. pdev->fp_mgmt_filter = FILTER_MGMT_ALL;
  2382. pdev->fp_ctrl_filter = FILTER_CTRL_ALL;
  2383. pdev->fp_data_filter = FILTER_DATA_ALL;
  2384. pdev->mo_mgmt_filter = FILTER_MGMT_ALL;
  2385. pdev->mo_ctrl_filter = FILTER_CTRL_ALL;
  2386. pdev->mo_data_filter = FILTER_DATA_ALL;
  2387. #ifndef CONFIG_WIN
  2388. /* MCL */
  2389. dp_local_peer_id_pool_init(pdev);
  2390. #endif
  2391. dp_dscp_tid_map_setup(pdev);
  2392. /* Rx monitor mode specific init */
  2393. if (dp_rx_pdev_mon_attach(pdev)) {
  2394. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2395. "dp_rx_pdev_attach failed\n");
  2396. goto fail1;
  2397. }
  2398. if (dp_wdi_event_attach(pdev)) {
  2399. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2400. "dp_wdi_evet_attach failed\n");
  2401. goto fail1;
  2402. }
  2403. /* set the reo destination during initialization */
  2404. pdev->reo_dest = pdev->pdev_id + 1;
  2405. /*
  2406. * initialize ppdu tlv list
  2407. */
  2408. TAILQ_INIT(&pdev->ppdu_info_list);
  2409. pdev->tlv_count = 0;
  2410. pdev->list_depth = 0;
  2411. return (struct cdp_pdev *)pdev;
  2412. fail1:
  2413. dp_pdev_detach_wifi3((struct cdp_pdev *)pdev, 0);
  2414. fail0:
  2415. return NULL;
  2416. }
  2417. /*
  2418. * dp_rxdma_ring_cleanup() - configure the RX DMA rings
  2419. * @soc: data path SoC handle
  2420. * @pdev: Physical device handle
  2421. *
  2422. * Return: void
  2423. */
  2424. #ifdef QCA_HOST2FW_RXBUF_RING
  2425. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2426. struct dp_pdev *pdev)
  2427. {
  2428. int max_mac_rings =
  2429. wlan_cfg_get_num_mac_rings(pdev->wlan_cfg_ctx);
  2430. int i;
  2431. max_mac_rings = max_mac_rings < MAX_RX_MAC_RINGS ?
  2432. max_mac_rings : MAX_RX_MAC_RINGS;
  2433. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  2434. dp_srng_cleanup(soc, &pdev->rx_mac_buf_ring[i],
  2435. RXDMA_BUF, 1);
  2436. qdf_timer_free(&soc->mon_reap_timer);
  2437. }
  2438. #else
  2439. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2440. struct dp_pdev *pdev)
  2441. {
  2442. }
  2443. #endif
  2444. /*
  2445. * dp_neighbour_peers_detach() - Detach neighbour peers(nac clients)
  2446. * @pdev: device object
  2447. *
  2448. * Return: void
  2449. */
  2450. static void dp_neighbour_peers_detach(struct dp_pdev *pdev)
  2451. {
  2452. struct dp_neighbour_peer *peer = NULL;
  2453. struct dp_neighbour_peer *temp_peer = NULL;
  2454. TAILQ_FOREACH_SAFE(peer, &pdev->neighbour_peers_list,
  2455. neighbour_peer_list_elem, temp_peer) {
  2456. /* delete this peer from the list */
  2457. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2458. peer, neighbour_peer_list_elem);
  2459. qdf_mem_free(peer);
  2460. }
  2461. qdf_spinlock_destroy(&pdev->neighbour_peer_mutex);
  2462. }
  2463. /**
  2464. * dp_htt_ppdu_stats_detach() - detach stats resources
  2465. * @pdev: Datapath PDEV handle
  2466. *
  2467. * Return: void
  2468. */
  2469. static void dp_htt_ppdu_stats_detach(struct dp_pdev *pdev)
  2470. {
  2471. struct ppdu_info *ppdu_info, *ppdu_info_next;
  2472. TAILQ_FOREACH_SAFE(ppdu_info, &pdev->ppdu_info_list,
  2473. ppdu_info_list_elem, ppdu_info_next) {
  2474. if (!ppdu_info)
  2475. break;
  2476. qdf_assert_always(ppdu_info->nbuf);
  2477. qdf_nbuf_free(ppdu_info->nbuf);
  2478. qdf_mem_free(ppdu_info);
  2479. }
  2480. }
  2481. /*
  2482. * dp_pdev_detach_wifi3() - detach txrx pdev
  2483. * @txrx_pdev: Datapath PDEV handle
  2484. * @force: Force detach
  2485. *
  2486. */
  2487. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force)
  2488. {
  2489. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2490. struct dp_soc *soc = pdev->soc;
  2491. qdf_nbuf_t curr_nbuf, next_nbuf;
  2492. int mac_id;
  2493. dp_wdi_event_detach(pdev);
  2494. dp_tx_pdev_detach(pdev);
  2495. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2496. dp_srng_cleanup(soc, &soc->tcl_data_ring[pdev->pdev_id],
  2497. TCL_DATA, pdev->pdev_id);
  2498. dp_srng_cleanup(soc, &soc->tx_comp_ring[pdev->pdev_id],
  2499. WBM2SW_RELEASE, pdev->pdev_id);
  2500. }
  2501. dp_pktlogmod_exit(pdev);
  2502. dp_rx_pdev_detach(pdev);
  2503. dp_rx_pdev_mon_detach(pdev);
  2504. dp_neighbour_peers_detach(pdev);
  2505. qdf_spinlock_destroy(&pdev->tx_mutex);
  2506. dp_ipa_uc_detach(soc, pdev);
  2507. dp_cleanup_ipa_rx_refill_buf_ring(soc, pdev);
  2508. /* Cleanup per PDEV REO rings if configured */
  2509. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2510. dp_srng_cleanup(soc, &soc->reo_dest_ring[pdev->pdev_id],
  2511. REO_DST, pdev->pdev_id);
  2512. }
  2513. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0);
  2514. dp_rxdma_ring_cleanup(soc, pdev);
  2515. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  2516. dp_srng_cleanup(soc, &pdev->rxdma_mon_buf_ring[mac_id],
  2517. RXDMA_MONITOR_BUF, 0);
  2518. dp_srng_cleanup(soc, &pdev->rxdma_mon_dst_ring[mac_id],
  2519. RXDMA_MONITOR_DST, 0);
  2520. dp_srng_cleanup(soc, &pdev->rxdma_mon_status_ring[mac_id],
  2521. RXDMA_MONITOR_STATUS, 0);
  2522. dp_srng_cleanup(soc, &pdev->rxdma_mon_desc_ring[mac_id],
  2523. RXDMA_MONITOR_DESC, 0);
  2524. dp_srng_cleanup(soc, &pdev->rxdma_err_dst_ring[mac_id],
  2525. RXDMA_DST, 0);
  2526. }
  2527. curr_nbuf = pdev->invalid_peer_head_msdu;
  2528. while (curr_nbuf) {
  2529. next_nbuf = qdf_nbuf_next(curr_nbuf);
  2530. qdf_nbuf_free(curr_nbuf);
  2531. curr_nbuf = next_nbuf;
  2532. }
  2533. dp_htt_ppdu_stats_detach(pdev);
  2534. soc->pdev_list[pdev->pdev_id] = NULL;
  2535. soc->pdev_count--;
  2536. wlan_cfg_pdev_detach(pdev->wlan_cfg_ctx);
  2537. qdf_mem_free(pdev->dp_txrx_handle);
  2538. qdf_mem_free(pdev);
  2539. }
  2540. /*
  2541. * dp_reo_desc_freelist_destroy() - Flush REO descriptors from deferred freelist
  2542. * @soc: DP SOC handle
  2543. */
  2544. static inline void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  2545. {
  2546. struct reo_desc_list_node *desc;
  2547. struct dp_rx_tid *rx_tid;
  2548. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  2549. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  2550. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2551. rx_tid = &desc->rx_tid;
  2552. qdf_mem_unmap_nbytes_single(soc->osdev,
  2553. rx_tid->hw_qdesc_paddr,
  2554. QDF_DMA_BIDIRECTIONAL,
  2555. rx_tid->hw_qdesc_alloc_size);
  2556. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  2557. qdf_mem_free(desc);
  2558. }
  2559. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  2560. qdf_list_destroy(&soc->reo_desc_freelist);
  2561. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  2562. }
  2563. /*
  2564. * dp_soc_detach_wifi3() - Detach txrx SOC
  2565. * @txrx_soc: DP SOC handle, struct cdp_soc_t is first element of struct dp_soc.
  2566. */
  2567. static void dp_soc_detach_wifi3(void *txrx_soc)
  2568. {
  2569. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2570. int i;
  2571. qdf_atomic_set(&soc->cmn_init_done, 0);
  2572. qdf_flush_work(&soc->htt_stats.work);
  2573. qdf_disable_work(&soc->htt_stats.work);
  2574. /* Free pending htt stats messages */
  2575. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  2576. dp_free_inact_timer(soc);
  2577. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2578. if (soc->pdev_list[i])
  2579. dp_pdev_detach_wifi3(
  2580. (struct cdp_pdev *)soc->pdev_list[i], 1);
  2581. }
  2582. dp_peer_find_detach(soc);
  2583. /* TBD: Call Tx and Rx cleanup functions to free buffers and
  2584. * SW descriptors
  2585. */
  2586. /* Free the ring memories */
  2587. /* Common rings */
  2588. dp_srng_cleanup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  2589. dp_tx_soc_detach(soc);
  2590. /* Tx data rings */
  2591. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2592. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2593. dp_srng_cleanup(soc, &soc->tcl_data_ring[i],
  2594. TCL_DATA, i);
  2595. dp_srng_cleanup(soc, &soc->tx_comp_ring[i],
  2596. WBM2SW_RELEASE, i);
  2597. }
  2598. }
  2599. /* TCL command and status rings */
  2600. dp_srng_cleanup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0);
  2601. dp_srng_cleanup(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  2602. /* Rx data rings */
  2603. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2604. soc->num_reo_dest_rings =
  2605. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  2606. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  2607. /* TODO: Get number of rings and ring sizes
  2608. * from wlan_cfg
  2609. */
  2610. dp_srng_cleanup(soc, &soc->reo_dest_ring[i],
  2611. REO_DST, i);
  2612. }
  2613. }
  2614. /* REO reinjection ring */
  2615. dp_srng_cleanup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  2616. /* Rx release ring */
  2617. dp_srng_cleanup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  2618. /* Rx exception ring */
  2619. /* TODO: Better to store ring_type and ring_num in
  2620. * dp_srng during setup
  2621. */
  2622. dp_srng_cleanup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  2623. /* REO command and status rings */
  2624. dp_srng_cleanup(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  2625. dp_srng_cleanup(soc, &soc->reo_status_ring, REO_STATUS, 0);
  2626. dp_hw_link_desc_pool_cleanup(soc);
  2627. qdf_spinlock_destroy(&soc->peer_ref_mutex);
  2628. qdf_spinlock_destroy(&soc->htt_stats.lock);
  2629. htt_soc_detach(soc->htt_handle);
  2630. dp_reo_cmdlist_destroy(soc);
  2631. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2632. dp_reo_desc_freelist_destroy(soc);
  2633. wlan_cfg_soc_detach(soc->wlan_cfg_ctx);
  2634. dp_soc_wds_detach(soc);
  2635. qdf_spinlock_destroy(&soc->ast_lock);
  2636. qdf_mem_free(soc);
  2637. }
  2638. /*
  2639. * dp_rxdma_ring_config() - configure the RX DMA rings
  2640. *
  2641. * This function is used to configure the MAC rings.
  2642. * On MCL host provides buffers in Host2FW ring
  2643. * FW refills (copies) buffers to the ring and updates
  2644. * ring_idx in register
  2645. *
  2646. * @soc: data path SoC handle
  2647. *
  2648. * Return: void
  2649. */
  2650. #ifdef QCA_HOST2FW_RXBUF_RING
  2651. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2652. {
  2653. int i;
  2654. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2655. struct dp_pdev *pdev = soc->pdev_list[i];
  2656. if (pdev) {
  2657. int mac_id;
  2658. bool dbs_enable = 0;
  2659. int max_mac_rings =
  2660. wlan_cfg_get_num_mac_rings
  2661. (pdev->wlan_cfg_ctx);
  2662. htt_srng_setup(soc->htt_handle, 0,
  2663. pdev->rx_refill_buf_ring.hal_srng,
  2664. RXDMA_BUF);
  2665. if (pdev->rx_refill_buf_ring2.hal_srng)
  2666. htt_srng_setup(soc->htt_handle, 0,
  2667. pdev->rx_refill_buf_ring2.hal_srng,
  2668. RXDMA_BUF);
  2669. if (soc->cdp_soc.ol_ops->
  2670. is_hw_dbs_2x2_capable) {
  2671. dbs_enable = soc->cdp_soc.ol_ops->
  2672. is_hw_dbs_2x2_capable(soc->ctrl_psoc);
  2673. }
  2674. if (dbs_enable) {
  2675. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2676. QDF_TRACE_LEVEL_ERROR,
  2677. FL("DBS enabled max_mac_rings %d\n"),
  2678. max_mac_rings);
  2679. } else {
  2680. max_mac_rings = 1;
  2681. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2682. QDF_TRACE_LEVEL_ERROR,
  2683. FL("DBS disabled, max_mac_rings %d\n"),
  2684. max_mac_rings);
  2685. }
  2686. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2687. FL("pdev_id %d max_mac_rings %d\n"),
  2688. pdev->pdev_id, max_mac_rings);
  2689. for (mac_id = 0; mac_id < max_mac_rings; mac_id++) {
  2690. int mac_for_pdev = dp_get_mac_id_for_pdev(
  2691. mac_id, pdev->pdev_id);
  2692. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2693. QDF_TRACE_LEVEL_ERROR,
  2694. FL("mac_id %d\n"), mac_for_pdev);
  2695. htt_srng_setup(soc->htt_handle, mac_for_pdev,
  2696. pdev->rx_mac_buf_ring[mac_id]
  2697. .hal_srng,
  2698. RXDMA_BUF);
  2699. htt_srng_setup(soc->htt_handle, mac_for_pdev,
  2700. pdev->rxdma_err_dst_ring[mac_id]
  2701. .hal_srng,
  2702. RXDMA_DST);
  2703. /* Configure monitor mode rings */
  2704. htt_srng_setup(soc->htt_handle, mac_for_pdev,
  2705. pdev->rxdma_mon_buf_ring[mac_id].hal_srng,
  2706. RXDMA_MONITOR_BUF);
  2707. htt_srng_setup(soc->htt_handle, mac_for_pdev,
  2708. pdev->rxdma_mon_dst_ring[mac_id].hal_srng,
  2709. RXDMA_MONITOR_DST);
  2710. htt_srng_setup(soc->htt_handle, mac_for_pdev,
  2711. pdev->rxdma_mon_status_ring[mac_id].hal_srng,
  2712. RXDMA_MONITOR_STATUS);
  2713. htt_srng_setup(soc->htt_handle, mac_for_pdev,
  2714. pdev->rxdma_mon_desc_ring[mac_id].hal_srng,
  2715. RXDMA_MONITOR_DESC);
  2716. }
  2717. }
  2718. }
  2719. /*
  2720. * Timer to reap rxdma status rings.
  2721. * Needed until we enable ppdu end interrupts
  2722. */
  2723. qdf_timer_init(soc->osdev, &soc->mon_reap_timer,
  2724. dp_service_mon_rings, (void *)soc,
  2725. QDF_TIMER_TYPE_WAKE_APPS);
  2726. soc->reap_timer_init = 1;
  2727. }
  2728. #else
  2729. /* This is only for WIN */
  2730. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2731. {
  2732. int i;
  2733. int mac_id;
  2734. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2735. struct dp_pdev *pdev = soc->pdev_list[i];
  2736. if (pdev == NULL)
  2737. continue;
  2738. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  2739. int mac_for_pdev = dp_get_mac_id_for_pdev(mac_id, i);
  2740. htt_srng_setup(soc->htt_handle, mac_for_pdev,
  2741. pdev->rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2742. htt_srng_setup(soc->htt_handle, mac_for_pdev,
  2743. pdev->rxdma_mon_buf_ring[mac_id].hal_srng,
  2744. RXDMA_MONITOR_BUF);
  2745. htt_srng_setup(soc->htt_handle, mac_for_pdev,
  2746. pdev->rxdma_mon_dst_ring[mac_id].hal_srng,
  2747. RXDMA_MONITOR_DST);
  2748. htt_srng_setup(soc->htt_handle, mac_for_pdev,
  2749. pdev->rxdma_mon_status_ring[mac_id].hal_srng,
  2750. RXDMA_MONITOR_STATUS);
  2751. htt_srng_setup(soc->htt_handle, mac_for_pdev,
  2752. pdev->rxdma_mon_desc_ring[mac_id].hal_srng,
  2753. RXDMA_MONITOR_DESC);
  2754. htt_srng_setup(soc->htt_handle, mac_for_pdev,
  2755. pdev->rxdma_err_dst_ring[mac_id].hal_srng,
  2756. RXDMA_DST);
  2757. }
  2758. }
  2759. }
  2760. #endif
  2761. /*
  2762. * dp_soc_attach_target_wifi3() - SOC initialization in the target
  2763. * @txrx_soc: Datapath SOC handle
  2764. */
  2765. static int dp_soc_attach_target_wifi3(struct cdp_soc_t *cdp_soc)
  2766. {
  2767. struct dp_soc *soc = (struct dp_soc *)cdp_soc;
  2768. htt_soc_attach_target(soc->htt_handle);
  2769. dp_rxdma_ring_config(soc);
  2770. DP_STATS_INIT(soc);
  2771. /* initialize work queue for stats processing */
  2772. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  2773. return 0;
  2774. }
  2775. /*
  2776. * dp_soc_get_nss_cfg_wifi3() - SOC get nss config
  2777. * @txrx_soc: Datapath SOC handle
  2778. */
  2779. static int dp_soc_get_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc)
  2780. {
  2781. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2782. return wlan_cfg_get_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx);
  2783. }
  2784. /*
  2785. * dp_soc_set_nss_cfg_wifi3() - SOC set nss config
  2786. * @txrx_soc: Datapath SOC handle
  2787. * @nss_cfg: nss config
  2788. */
  2789. static void dp_soc_set_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc, int config)
  2790. {
  2791. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2792. struct wlan_cfg_dp_soc_ctxt *wlan_cfg_ctx = dsoc->wlan_cfg_ctx;
  2793. wlan_cfg_set_dp_soc_nss_cfg(wlan_cfg_ctx, config);
  2794. /*
  2795. * TODO: masked out based on the per offloaded radio
  2796. */
  2797. if (config == dp_nss_cfg_dbdc) {
  2798. wlan_cfg_set_num_tx_desc_pool(wlan_cfg_ctx, 0);
  2799. wlan_cfg_set_num_tx_ext_desc_pool(wlan_cfg_ctx, 0);
  2800. wlan_cfg_set_num_tx_desc(wlan_cfg_ctx, 0);
  2801. wlan_cfg_set_num_tx_ext_desc(wlan_cfg_ctx, 0);
  2802. }
  2803. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2804. FL("nss-wifi<0> nss config is enabled"));
  2805. }
  2806. /*
  2807. * dp_vdev_attach_wifi3() - attach txrx vdev
  2808. * @txrx_pdev: Datapath PDEV handle
  2809. * @vdev_mac_addr: MAC address of the virtual interface
  2810. * @vdev_id: VDEV Id
  2811. * @wlan_op_mode: VDEV operating mode
  2812. *
  2813. * Return: DP VDEV handle on success, NULL on failure
  2814. */
  2815. static struct cdp_vdev *dp_vdev_attach_wifi3(struct cdp_pdev *txrx_pdev,
  2816. uint8_t *vdev_mac_addr, uint8_t vdev_id, enum wlan_op_mode op_mode)
  2817. {
  2818. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2819. struct dp_soc *soc = pdev->soc;
  2820. struct dp_vdev *vdev = qdf_mem_malloc(sizeof(*vdev));
  2821. int tx_ring_size;
  2822. if (!vdev) {
  2823. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2824. FL("DP VDEV memory allocation failed"));
  2825. goto fail0;
  2826. }
  2827. vdev->pdev = pdev;
  2828. vdev->vdev_id = vdev_id;
  2829. vdev->opmode = op_mode;
  2830. vdev->osdev = soc->osdev;
  2831. vdev->osif_rx = NULL;
  2832. vdev->osif_rsim_rx_decap = NULL;
  2833. vdev->osif_get_key = NULL;
  2834. vdev->osif_rx_mon = NULL;
  2835. vdev->osif_tx_free_ext = NULL;
  2836. vdev->osif_vdev = NULL;
  2837. vdev->delete.pending = 0;
  2838. vdev->safemode = 0;
  2839. vdev->drop_unenc = 1;
  2840. vdev->sec_type = cdp_sec_type_none;
  2841. #ifdef notyet
  2842. vdev->filters_num = 0;
  2843. #endif
  2844. qdf_mem_copy(
  2845. &vdev->mac_addr.raw[0], vdev_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2846. vdev->tx_encap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2847. vdev->rx_decap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2848. vdev->dscp_tid_map_id = 0;
  2849. vdev->mcast_enhancement_en = 0;
  2850. tx_ring_size = wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2851. /* TODO: Initialize default HTT meta data that will be used in
  2852. * TCL descriptors for packets transmitted from this VDEV
  2853. */
  2854. TAILQ_INIT(&vdev->peer_list);
  2855. /* add this vdev into the pdev's list */
  2856. TAILQ_INSERT_TAIL(&pdev->vdev_list, vdev, vdev_list_elem);
  2857. pdev->vdev_count++;
  2858. dp_tx_vdev_attach(vdev);
  2859. if (QDF_STATUS_SUCCESS != dp_tx_flow_pool_map_handler(pdev, vdev_id,
  2860. FLOW_TYPE_VDEV, vdev_id, tx_ring_size))
  2861. goto fail1;
  2862. if ((soc->intr_mode == DP_INTR_POLL) &&
  2863. wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx) != 0) {
  2864. if (pdev->vdev_count == 1)
  2865. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  2866. }
  2867. dp_lro_hash_setup(soc);
  2868. /* LRO */
  2869. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  2870. wlan_op_mode_sta == vdev->opmode)
  2871. vdev->lro_enable = true;
  2872. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2873. "LRO: vdev_id %d lro_enable %d", vdev_id, vdev->lro_enable);
  2874. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2875. "Created vdev %pK (%pM)", vdev, vdev->mac_addr.raw);
  2876. DP_STATS_INIT(vdev);
  2877. if (wlan_op_mode_sta == vdev->opmode)
  2878. dp_peer_create_wifi3((struct cdp_vdev *)vdev,
  2879. vdev->mac_addr.raw);
  2880. return (struct cdp_vdev *)vdev;
  2881. fail1:
  2882. dp_tx_vdev_detach(vdev);
  2883. qdf_mem_free(vdev);
  2884. fail0:
  2885. return NULL;
  2886. }
  2887. /**
  2888. * dp_vdev_register_wifi3() - Register VDEV operations from osif layer
  2889. * @vdev: Datapath VDEV handle
  2890. * @osif_vdev: OSIF vdev handle
  2891. * @txrx_ops: Tx and Rx operations
  2892. *
  2893. * Return: DP VDEV handle on success, NULL on failure
  2894. */
  2895. static void dp_vdev_register_wifi3(struct cdp_vdev *vdev_handle,
  2896. void *osif_vdev,
  2897. struct ol_txrx_ops *txrx_ops)
  2898. {
  2899. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2900. vdev->osif_vdev = osif_vdev;
  2901. vdev->osif_rx = txrx_ops->rx.rx;
  2902. vdev->osif_rsim_rx_decap = txrx_ops->rx.rsim_rx_decap;
  2903. vdev->osif_get_key = txrx_ops->get_key;
  2904. vdev->osif_rx_mon = txrx_ops->rx.mon;
  2905. vdev->osif_tx_free_ext = txrx_ops->tx.tx_free_ext;
  2906. #ifdef notyet
  2907. #if ATH_SUPPORT_WAPI
  2908. vdev->osif_check_wai = txrx_ops->rx.wai_check;
  2909. #endif
  2910. #endif
  2911. #ifdef UMAC_SUPPORT_PROXY_ARP
  2912. vdev->osif_proxy_arp = txrx_ops->proxy_arp;
  2913. #endif
  2914. vdev->me_convert = txrx_ops->me_convert;
  2915. /* TODO: Enable the following once Tx code is integrated */
  2916. if (vdev->mesh_vdev)
  2917. txrx_ops->tx.tx = dp_tx_send_mesh;
  2918. else
  2919. txrx_ops->tx.tx = dp_tx_send;
  2920. txrx_ops->tx.tx_exception = dp_tx_send_exception;
  2921. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  2922. "DP Vdev Register success");
  2923. }
  2924. /**
  2925. * dp_vdev_flush_peers() - Forcibily Flush peers of vdev
  2926. * @vdev: Datapath VDEV handle
  2927. *
  2928. * Return: void
  2929. */
  2930. static void dp_vdev_flush_peers(struct dp_vdev *vdev)
  2931. {
  2932. struct dp_pdev *pdev = vdev->pdev;
  2933. struct dp_soc *soc = pdev->soc;
  2934. struct dp_peer *peer;
  2935. uint16_t *peer_ids;
  2936. uint8_t i = 0, j = 0;
  2937. peer_ids = qdf_mem_malloc(soc->max_peers * sizeof(peer_ids[0]));
  2938. if (!peer_ids) {
  2939. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2940. "DP alloc failure - unable to flush peers");
  2941. return;
  2942. }
  2943. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2944. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2945. for (i = 0; i < MAX_NUM_PEER_ID_PER_PEER; i++)
  2946. if (peer->peer_ids[i] != HTT_INVALID_PEER)
  2947. if (j < soc->max_peers)
  2948. peer_ids[j++] = peer->peer_ids[i];
  2949. }
  2950. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2951. for (i = 0; i < j ; i++)
  2952. dp_rx_peer_unmap_handler(soc, peer_ids[i]);
  2953. qdf_mem_free(peer_ids);
  2954. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2955. FL("Flushed peers for vdev object %pK "), vdev);
  2956. }
  2957. /*
  2958. * dp_vdev_detach_wifi3() - Detach txrx vdev
  2959. * @txrx_vdev: Datapath VDEV handle
  2960. * @callback: Callback OL_IF on completion of detach
  2961. * @cb_context: Callback context
  2962. *
  2963. */
  2964. static void dp_vdev_detach_wifi3(struct cdp_vdev *vdev_handle,
  2965. ol_txrx_vdev_delete_cb callback, void *cb_context)
  2966. {
  2967. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2968. struct dp_pdev *pdev = vdev->pdev;
  2969. struct dp_soc *soc = pdev->soc;
  2970. /* preconditions */
  2971. qdf_assert(vdev);
  2972. /* remove the vdev from its parent pdev's list */
  2973. TAILQ_REMOVE(&pdev->vdev_list, vdev, vdev_list_elem);
  2974. if (wlan_op_mode_sta == vdev->opmode)
  2975. dp_peer_delete_wifi3(vdev->vap_bss_peer, 0);
  2976. /*
  2977. * If Target is hung, flush all peers before detaching vdev
  2978. * this will free all references held due to missing
  2979. * unmap commands from Target
  2980. */
  2981. if (hif_get_target_status(soc->hif_handle) == TARGET_STATUS_RESET)
  2982. dp_vdev_flush_peers(vdev);
  2983. /*
  2984. * Use peer_ref_mutex while accessing peer_list, in case
  2985. * a peer is in the process of being removed from the list.
  2986. */
  2987. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2988. /* check that the vdev has no peers allocated */
  2989. if (!TAILQ_EMPTY(&vdev->peer_list)) {
  2990. /* debug print - will be removed later */
  2991. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2992. FL("not deleting vdev object %pK (%pM)"
  2993. "until deletion finishes for all its peers"),
  2994. vdev, vdev->mac_addr.raw);
  2995. /* indicate that the vdev needs to be deleted */
  2996. vdev->delete.pending = 1;
  2997. vdev->delete.callback = callback;
  2998. vdev->delete.context = cb_context;
  2999. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  3000. return;
  3001. }
  3002. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  3003. dp_tx_flow_pool_unmap_handler(pdev, vdev->vdev_id, FLOW_TYPE_VDEV,
  3004. vdev->vdev_id);
  3005. dp_tx_vdev_detach(vdev);
  3006. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  3007. FL("deleting vdev object %pK (%pM)"), vdev, vdev->mac_addr.raw);
  3008. qdf_mem_free(vdev);
  3009. if (callback)
  3010. callback(cb_context);
  3011. }
  3012. /*
  3013. * dp_peer_create_wifi3() - attach txrx peer
  3014. * @txrx_vdev: Datapath VDEV handle
  3015. * @peer_mac_addr: Peer MAC address
  3016. *
  3017. * Return: DP peeer handle on success, NULL on failure
  3018. */
  3019. static void *dp_peer_create_wifi3(struct cdp_vdev *vdev_handle,
  3020. uint8_t *peer_mac_addr)
  3021. {
  3022. struct dp_peer *peer;
  3023. int i;
  3024. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3025. struct dp_pdev *pdev;
  3026. struct dp_soc *soc;
  3027. /* preconditions */
  3028. qdf_assert(vdev);
  3029. qdf_assert(peer_mac_addr);
  3030. pdev = vdev->pdev;
  3031. soc = pdev->soc;
  3032. peer = dp_peer_find_hash_find(pdev->soc, peer_mac_addr,
  3033. 0, vdev->vdev_id);
  3034. if (peer) {
  3035. peer->delete_in_progress = false;
  3036. /*
  3037. * on peer create, peer ref count decrements, sice new peer is not
  3038. * getting created earlier reference is reused, peer_unref_delete will
  3039. * take care of incrementing count
  3040. * */
  3041. if (soc->cdp_soc.ol_ops->peer_unref_delete) {
  3042. soc->cdp_soc.ol_ops->peer_unref_delete(pdev->osif_pdev,
  3043. vdev->vdev_id, peer->mac_addr.raw);
  3044. }
  3045. return (void *)peer;
  3046. }
  3047. #ifdef notyet
  3048. peer = (struct dp_peer *)qdf_mempool_alloc(soc->osdev,
  3049. soc->mempool_ol_ath_peer);
  3050. #else
  3051. peer = (struct dp_peer *)qdf_mem_malloc(sizeof(*peer));
  3052. #endif
  3053. if (!peer)
  3054. return NULL; /* failure */
  3055. qdf_mem_zero(peer, sizeof(struct dp_peer));
  3056. TAILQ_INIT(&peer->ast_entry_list);
  3057. /* store provided params */
  3058. peer->vdev = vdev;
  3059. dp_peer_add_ast(soc, peer, peer_mac_addr, CDP_TXRX_AST_TYPE_STATIC, 0);
  3060. qdf_spinlock_create(&peer->peer_info_lock);
  3061. qdf_mem_copy(
  3062. &peer->mac_addr.raw[0], peer_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  3063. /* TODO: See of rx_opt_proc is really required */
  3064. peer->rx_opt_proc = soc->rx_opt_proc;
  3065. /* initialize the peer_id */
  3066. for (i = 0; i < MAX_NUM_PEER_ID_PER_PEER; i++)
  3067. peer->peer_ids[i] = HTT_INVALID_PEER;
  3068. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  3069. qdf_atomic_init(&peer->ref_cnt);
  3070. /* keep one reference for attach */
  3071. qdf_atomic_inc(&peer->ref_cnt);
  3072. /* add this peer into the vdev's list */
  3073. if (wlan_op_mode_sta == vdev->opmode)
  3074. TAILQ_INSERT_HEAD(&vdev->peer_list, peer, peer_list_elem);
  3075. else
  3076. TAILQ_INSERT_TAIL(&vdev->peer_list, peer, peer_list_elem);
  3077. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  3078. /* TODO: See if hash based search is required */
  3079. dp_peer_find_hash_add(soc, peer);
  3080. /* Initialize the peer state */
  3081. peer->state = OL_TXRX_PEER_STATE_DISC;
  3082. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  3083. "vdev %pK created peer %pK (%pM) ref_cnt: %d",
  3084. vdev, peer, peer->mac_addr.raw,
  3085. qdf_atomic_read(&peer->ref_cnt));
  3086. /*
  3087. * For every peer MAp message search and set if bss_peer
  3088. */
  3089. if (memcmp(peer->mac_addr.raw, vdev->mac_addr.raw, 6) == 0) {
  3090. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  3091. "vdev bss_peer!!!!");
  3092. peer->bss_peer = 1;
  3093. vdev->vap_bss_peer = peer;
  3094. }
  3095. #ifndef CONFIG_WIN
  3096. dp_local_peer_id_alloc(pdev, peer);
  3097. #endif
  3098. DP_STATS_INIT(peer);
  3099. return (void *)peer;
  3100. }
  3101. /*
  3102. * dp_peer_setup_wifi3() - initialize the peer
  3103. * @vdev_hdl: virtual device object
  3104. * @peer: Peer object
  3105. *
  3106. * Return: void
  3107. */
  3108. static void dp_peer_setup_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  3109. {
  3110. struct dp_peer *peer = (struct dp_peer *)peer_hdl;
  3111. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3112. struct dp_pdev *pdev;
  3113. struct dp_soc *soc;
  3114. bool hash_based = 0;
  3115. enum cdp_host_reo_dest_ring reo_dest;
  3116. /* preconditions */
  3117. qdf_assert(vdev);
  3118. qdf_assert(peer);
  3119. pdev = vdev->pdev;
  3120. soc = pdev->soc;
  3121. peer->last_assoc_rcvd = 0;
  3122. peer->last_disassoc_rcvd = 0;
  3123. peer->last_deauth_rcvd = 0;
  3124. /*
  3125. * hash based steering is disabled for Radios which are offloaded
  3126. * to NSS
  3127. */
  3128. if (!wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx))
  3129. hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  3130. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3131. FL("hash based steering for pdev: %d is %d\n"),
  3132. pdev->pdev_id, hash_based);
  3133. /*
  3134. * Below line of code will ensure the proper reo_dest ring is choosen
  3135. * for cases where toeplitz hash cannot be generated (ex: non TCP/UDP)
  3136. */
  3137. reo_dest = pdev->reo_dest;
  3138. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  3139. /* TODO: Check the destination ring number to be passed to FW */
  3140. soc->cdp_soc.ol_ops->peer_set_default_routing(
  3141. pdev->osif_pdev, peer->mac_addr.raw,
  3142. peer->vdev->vdev_id, hash_based, reo_dest);
  3143. }
  3144. dp_peer_rx_init(pdev, peer);
  3145. return;
  3146. }
  3147. /*
  3148. * dp_set_vdev_tx_encap_type() - set the encap type of the vdev
  3149. * @vdev_handle: virtual device object
  3150. * @htt_pkt_type: type of pkt
  3151. *
  3152. * Return: void
  3153. */
  3154. static void dp_set_vdev_tx_encap_type(struct cdp_vdev *vdev_handle,
  3155. enum htt_cmn_pkt_type val)
  3156. {
  3157. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3158. vdev->tx_encap_type = val;
  3159. }
  3160. /*
  3161. * dp_set_vdev_rx_decap_type() - set the decap type of the vdev
  3162. * @vdev_handle: virtual device object
  3163. * @htt_pkt_type: type of pkt
  3164. *
  3165. * Return: void
  3166. */
  3167. static void dp_set_vdev_rx_decap_type(struct cdp_vdev *vdev_handle,
  3168. enum htt_cmn_pkt_type val)
  3169. {
  3170. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3171. vdev->rx_decap_type = val;
  3172. }
  3173. /*
  3174. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  3175. * @pdev_handle: physical device object
  3176. * @val: reo destination ring index (1 - 4)
  3177. *
  3178. * Return: void
  3179. */
  3180. static void dp_set_pdev_reo_dest(struct cdp_pdev *pdev_handle,
  3181. enum cdp_host_reo_dest_ring val)
  3182. {
  3183. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3184. if (pdev)
  3185. pdev->reo_dest = val;
  3186. }
  3187. /*
  3188. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  3189. * @pdev_handle: physical device object
  3190. *
  3191. * Return: reo destination ring index
  3192. */
  3193. static enum cdp_host_reo_dest_ring
  3194. dp_get_pdev_reo_dest(struct cdp_pdev *pdev_handle)
  3195. {
  3196. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3197. if (pdev)
  3198. return pdev->reo_dest;
  3199. else
  3200. return cdp_host_reo_dest_ring_unknown;
  3201. }
  3202. #ifdef QCA_SUPPORT_SON
  3203. static void dp_son_peer_authorize(struct dp_peer *peer)
  3204. {
  3205. struct dp_soc *soc;
  3206. soc = peer->vdev->pdev->soc;
  3207. peer->peer_bs_inact_flag = 0;
  3208. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  3209. return;
  3210. }
  3211. #else
  3212. static void dp_son_peer_authorize(struct dp_peer *peer)
  3213. {
  3214. return;
  3215. }
  3216. #endif
  3217. /*
  3218. * dp_set_filter_neighbour_peers() - set filter neighbour peers for smart mesh
  3219. * @pdev_handle: device object
  3220. * @val: value to be set
  3221. *
  3222. * Return: void
  3223. */
  3224. static int dp_set_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  3225. uint32_t val)
  3226. {
  3227. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3228. /* Enable/Disable smart mesh filtering. This flag will be checked
  3229. * during rx processing to check if packets are from NAC clients.
  3230. */
  3231. pdev->filter_neighbour_peers = val;
  3232. return 0;
  3233. }
  3234. /*
  3235. * dp_update_filter_neighbour_peers() - set neighbour peers(nac clients)
  3236. * address for smart mesh filtering
  3237. * @pdev_handle: device object
  3238. * @cmd: Add/Del command
  3239. * @macaddr: nac client mac address
  3240. *
  3241. * Return: void
  3242. */
  3243. static int dp_update_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  3244. uint32_t cmd, uint8_t *macaddr)
  3245. {
  3246. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3247. struct dp_neighbour_peer *peer = NULL;
  3248. if (!macaddr)
  3249. goto fail0;
  3250. /* Store address of NAC (neighbour peer) which will be checked
  3251. * against TA of received packets.
  3252. */
  3253. if (cmd == DP_NAC_PARAM_ADD) {
  3254. peer = (struct dp_neighbour_peer *) qdf_mem_malloc(
  3255. sizeof(*peer));
  3256. if (!peer) {
  3257. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3258. FL("DP neighbour peer node memory allocation failed"));
  3259. goto fail0;
  3260. }
  3261. qdf_mem_copy(&peer->neighbour_peers_macaddr.raw[0],
  3262. macaddr, DP_MAC_ADDR_LEN);
  3263. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  3264. /* add this neighbour peer into the list */
  3265. TAILQ_INSERT_TAIL(&pdev->neighbour_peers_list, peer,
  3266. neighbour_peer_list_elem);
  3267. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  3268. return 1;
  3269. } else if (cmd == DP_NAC_PARAM_DEL) {
  3270. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  3271. TAILQ_FOREACH(peer, &pdev->neighbour_peers_list,
  3272. neighbour_peer_list_elem) {
  3273. if (!qdf_mem_cmp(&peer->neighbour_peers_macaddr.raw[0],
  3274. macaddr, DP_MAC_ADDR_LEN)) {
  3275. /* delete this peer from the list */
  3276. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  3277. peer, neighbour_peer_list_elem);
  3278. qdf_mem_free(peer);
  3279. break;
  3280. }
  3281. }
  3282. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  3283. return 1;
  3284. }
  3285. fail0:
  3286. return 0;
  3287. }
  3288. /*
  3289. * dp_get_sec_type() - Get the security type
  3290. * @peer: Datapath peer handle
  3291. * @sec_idx: Security id (mcast, ucast)
  3292. *
  3293. * return sec_type: Security type
  3294. */
  3295. static int dp_get_sec_type(struct cdp_peer *peer, uint8_t sec_idx)
  3296. {
  3297. struct dp_peer *dpeer = (struct dp_peer *)peer;
  3298. return dpeer->security[sec_idx].sec_type;
  3299. }
  3300. /*
  3301. * dp_peer_authorize() - authorize txrx peer
  3302. * @peer_handle: Datapath peer handle
  3303. * @authorize
  3304. *
  3305. */
  3306. static void dp_peer_authorize(struct cdp_peer *peer_handle, uint32_t authorize)
  3307. {
  3308. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  3309. struct dp_soc *soc;
  3310. if (peer != NULL) {
  3311. soc = peer->vdev->pdev->soc;
  3312. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  3313. dp_son_peer_authorize(peer);
  3314. peer->authorize = authorize ? 1 : 0;
  3315. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  3316. }
  3317. }
  3318. #ifdef QCA_SUPPORT_SON
  3319. /*
  3320. * dp_txrx_update_inact_threshold() - Update inact timer threshold
  3321. * @pdev_handle: Device handle
  3322. * @new_threshold : updated threshold value
  3323. *
  3324. */
  3325. static void
  3326. dp_txrx_update_inact_threshold(struct cdp_pdev *pdev_handle,
  3327. u_int16_t new_threshold)
  3328. {
  3329. struct dp_vdev *vdev;
  3330. struct dp_peer *peer;
  3331. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3332. struct dp_soc *soc = pdev->soc;
  3333. u_int16_t old_threshold = soc->pdev_bs_inact_reload;
  3334. if (old_threshold == new_threshold)
  3335. return;
  3336. soc->pdev_bs_inact_reload = new_threshold;
  3337. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  3338. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3339. if (vdev->opmode != wlan_op_mode_ap)
  3340. continue;
  3341. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3342. if (!peer->authorize)
  3343. continue;
  3344. if (old_threshold - peer->peer_bs_inact >=
  3345. new_threshold) {
  3346. dp_mark_peer_inact((void *)peer, true);
  3347. peer->peer_bs_inact = 0;
  3348. } else {
  3349. peer->peer_bs_inact = new_threshold -
  3350. (old_threshold - peer->peer_bs_inact);
  3351. }
  3352. }
  3353. }
  3354. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  3355. }
  3356. /**
  3357. * dp_txrx_reset_inact_count(): Reset inact count
  3358. * @pdev_handle - device handle
  3359. *
  3360. * Return: void
  3361. */
  3362. static void
  3363. dp_txrx_reset_inact_count(struct cdp_pdev *pdev_handle)
  3364. {
  3365. struct dp_vdev *vdev = NULL;
  3366. struct dp_peer *peer = NULL;
  3367. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3368. struct dp_soc *soc = pdev->soc;
  3369. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  3370. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3371. if (vdev->opmode != wlan_op_mode_ap)
  3372. continue;
  3373. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3374. if (!peer->authorize)
  3375. continue;
  3376. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  3377. }
  3378. }
  3379. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  3380. }
  3381. /**
  3382. * dp_set_inact_params(): set inactivity params
  3383. * @pdev_handle - device handle
  3384. * @inact_check_interval - inactivity interval
  3385. * @inact_normal - Inactivity normal
  3386. * @inact_overload - Inactivity overload
  3387. *
  3388. * Return: bool
  3389. */
  3390. bool dp_set_inact_params(struct cdp_pdev *pdev_handle,
  3391. u_int16_t inact_check_interval,
  3392. u_int16_t inact_normal, u_int16_t inact_overload)
  3393. {
  3394. struct dp_soc *soc;
  3395. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3396. if (!pdev)
  3397. return false;
  3398. soc = pdev->soc;
  3399. if (!soc)
  3400. return false;
  3401. soc->pdev_bs_inact_interval = inact_check_interval;
  3402. soc->pdev_bs_inact_normal = inact_normal;
  3403. soc->pdev_bs_inact_overload = inact_overload;
  3404. dp_txrx_update_inact_threshold((struct cdp_pdev *)pdev,
  3405. soc->pdev_bs_inact_normal);
  3406. return true;
  3407. }
  3408. /**
  3409. * dp_start_inact_timer(): Inactivity timer start
  3410. * @pdev_handle - device handle
  3411. * @enable - Inactivity timer start/stop
  3412. *
  3413. * Return: bool
  3414. */
  3415. bool dp_start_inact_timer(struct cdp_pdev *pdev_handle, bool enable)
  3416. {
  3417. struct dp_soc *soc;
  3418. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3419. if (!pdev)
  3420. return false;
  3421. soc = pdev->soc;
  3422. if (!soc)
  3423. return false;
  3424. if (enable) {
  3425. dp_txrx_reset_inact_count((struct cdp_pdev *)pdev);
  3426. qdf_timer_mod(&soc->pdev_bs_inact_timer,
  3427. soc->pdev_bs_inact_interval * 1000);
  3428. } else {
  3429. qdf_timer_stop(&soc->pdev_bs_inact_timer);
  3430. }
  3431. return true;
  3432. }
  3433. /**
  3434. * dp_set_overload(): Set inactivity overload
  3435. * @pdev_handle - device handle
  3436. * @overload - overload status
  3437. *
  3438. * Return: void
  3439. */
  3440. void dp_set_overload(struct cdp_pdev *pdev_handle, bool overload)
  3441. {
  3442. struct dp_soc *soc;
  3443. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3444. if (!pdev)
  3445. return;
  3446. soc = pdev->soc;
  3447. if (!soc)
  3448. return;
  3449. dp_txrx_update_inact_threshold((struct cdp_pdev *)pdev,
  3450. overload ? soc->pdev_bs_inact_overload :
  3451. soc->pdev_bs_inact_normal);
  3452. }
  3453. /**
  3454. * dp_peer_is_inact(): check whether peer is inactive
  3455. * @peer_handle - datapath peer handle
  3456. *
  3457. * Return: bool
  3458. */
  3459. bool dp_peer_is_inact(void *peer_handle)
  3460. {
  3461. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  3462. if (!peer)
  3463. return false;
  3464. return peer->peer_bs_inact_flag == 1;
  3465. }
  3466. /**
  3467. * dp_init_inact_timer: initialize the inact timer
  3468. * @soc - SOC handle
  3469. *
  3470. * Return: void
  3471. */
  3472. void dp_init_inact_timer(struct dp_soc *soc)
  3473. {
  3474. qdf_timer_init(soc->osdev, &soc->pdev_bs_inact_timer,
  3475. dp_txrx_peer_find_inact_timeout_handler,
  3476. (void *)soc, QDF_TIMER_TYPE_WAKE_APPS);
  3477. }
  3478. #else
  3479. bool dp_set_inact_params(struct cdp_pdev *pdev, u_int16_t inact_check_interval,
  3480. u_int16_t inact_normal, u_int16_t inact_overload)
  3481. {
  3482. return false;
  3483. }
  3484. bool dp_start_inact_timer(struct cdp_pdev *pdev, bool enable)
  3485. {
  3486. return false;
  3487. }
  3488. void dp_set_overload(struct cdp_pdev *pdev, bool overload)
  3489. {
  3490. return;
  3491. }
  3492. void dp_init_inact_timer(struct dp_soc *soc)
  3493. {
  3494. return;
  3495. }
  3496. bool dp_peer_is_inact(void *peer)
  3497. {
  3498. return false;
  3499. }
  3500. #endif
  3501. /*
  3502. * dp_peer_unref_delete() - unref and delete peer
  3503. * @peer_handle: Datapath peer handle
  3504. *
  3505. */
  3506. void dp_peer_unref_delete(void *peer_handle)
  3507. {
  3508. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  3509. struct dp_peer *bss_peer = NULL;
  3510. struct dp_vdev *vdev = peer->vdev;
  3511. struct dp_pdev *pdev = vdev->pdev;
  3512. struct dp_soc *soc = pdev->soc;
  3513. struct dp_peer *tmppeer;
  3514. int found = 0;
  3515. uint16_t peer_id;
  3516. uint16_t vdev_id;
  3517. /*
  3518. * Hold the lock all the way from checking if the peer ref count
  3519. * is zero until the peer references are removed from the hash
  3520. * table and vdev list (if the peer ref count is zero).
  3521. * This protects against a new HL tx operation starting to use the
  3522. * peer object just after this function concludes it's done being used.
  3523. * Furthermore, the lock needs to be held while checking whether the
  3524. * vdev's list of peers is empty, to make sure that list is not modified
  3525. * concurrently with the empty check.
  3526. */
  3527. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  3528. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3529. "%s: peer %pK ref_cnt(before decrement): %d\n", __func__,
  3530. peer, qdf_atomic_read(&peer->ref_cnt));
  3531. if (qdf_atomic_dec_and_test(&peer->ref_cnt)) {
  3532. peer_id = peer->peer_ids[0];
  3533. vdev_id = vdev->vdev_id;
  3534. /*
  3535. * Make sure that the reference to the peer in
  3536. * peer object map is removed
  3537. */
  3538. if (peer_id != HTT_INVALID_PEER)
  3539. soc->peer_id_to_obj_map[peer_id] = NULL;
  3540. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  3541. "Deleting peer %pK (%pM)", peer, peer->mac_addr.raw);
  3542. /* remove the reference to the peer from the hash table */
  3543. dp_peer_find_hash_remove(soc, peer);
  3544. TAILQ_FOREACH(tmppeer, &peer->vdev->peer_list, peer_list_elem) {
  3545. if (tmppeer == peer) {
  3546. found = 1;
  3547. break;
  3548. }
  3549. }
  3550. if (found) {
  3551. TAILQ_REMOVE(&peer->vdev->peer_list, peer,
  3552. peer_list_elem);
  3553. } else {
  3554. /*Ignoring the remove operation as peer not found*/
  3555. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  3556. "peer %pK not found in vdev (%pK)->peer_list:%pK",
  3557. peer, vdev, &peer->vdev->peer_list);
  3558. }
  3559. /* cleanup the peer data */
  3560. dp_peer_cleanup(vdev, peer);
  3561. /* check whether the parent vdev has no peers left */
  3562. if (TAILQ_EMPTY(&vdev->peer_list)) {
  3563. /*
  3564. * Now that there are no references to the peer, we can
  3565. * release the peer reference lock.
  3566. */
  3567. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  3568. /*
  3569. * Check if the parent vdev was waiting for its peers
  3570. * to be deleted, in order for it to be deleted too.
  3571. */
  3572. if (vdev->delete.pending) {
  3573. ol_txrx_vdev_delete_cb vdev_delete_cb =
  3574. vdev->delete.callback;
  3575. void *vdev_delete_context =
  3576. vdev->delete.context;
  3577. QDF_TRACE(QDF_MODULE_ID_DP,
  3578. QDF_TRACE_LEVEL_INFO_HIGH,
  3579. FL("deleting vdev object %pK (%pM)"
  3580. " - its last peer is done"),
  3581. vdev, vdev->mac_addr.raw);
  3582. /* all peers are gone, go ahead and delete it */
  3583. dp_tx_flow_pool_unmap_handler(pdev, vdev_id,
  3584. FLOW_TYPE_VDEV,
  3585. vdev_id);
  3586. dp_tx_vdev_detach(vdev);
  3587. QDF_TRACE(QDF_MODULE_ID_DP,
  3588. QDF_TRACE_LEVEL_INFO_HIGH,
  3589. FL("deleting vdev object %pK (%pM)"),
  3590. vdev, vdev->mac_addr.raw);
  3591. qdf_mem_free(vdev);
  3592. vdev = NULL;
  3593. if (vdev_delete_cb)
  3594. vdev_delete_cb(vdev_delete_context);
  3595. }
  3596. } else {
  3597. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  3598. }
  3599. if (vdev) {
  3600. if (vdev->vap_bss_peer == peer) {
  3601. vdev->vap_bss_peer = NULL;
  3602. }
  3603. }
  3604. if (soc->cdp_soc.ol_ops->peer_unref_delete) {
  3605. soc->cdp_soc.ol_ops->peer_unref_delete(pdev->osif_pdev,
  3606. vdev_id, peer->mac_addr.raw);
  3607. }
  3608. if (!vdev || !vdev->vap_bss_peer) {
  3609. goto free_peer;
  3610. }
  3611. #ifdef notyet
  3612. qdf_mempool_free(soc->osdev, soc->mempool_ol_ath_peer, peer);
  3613. #else
  3614. bss_peer = vdev->vap_bss_peer;
  3615. DP_UPDATE_STATS(bss_peer, peer);
  3616. free_peer:
  3617. qdf_mem_free(peer);
  3618. #endif
  3619. } else {
  3620. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  3621. }
  3622. }
  3623. /*
  3624. * dp_peer_detach_wifi3() – Detach txrx peer
  3625. * @peer_handle: Datapath peer handle
  3626. * @bitmap: bitmap indicating special handling of request.
  3627. *
  3628. */
  3629. static void dp_peer_delete_wifi3(void *peer_handle, uint32_t bitmap)
  3630. {
  3631. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  3632. /* redirect the peer's rx delivery function to point to a
  3633. * discard func
  3634. */
  3635. peer->rx_opt_proc = dp_rx_discard;
  3636. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  3637. FL("peer %pK (%pM)"), peer, peer->mac_addr.raw);
  3638. #ifndef CONFIG_WIN
  3639. dp_local_peer_id_free(peer->vdev->pdev, peer);
  3640. #endif
  3641. qdf_spinlock_destroy(&peer->peer_info_lock);
  3642. /*
  3643. * Remove the reference added during peer_attach.
  3644. * The peer will still be left allocated until the
  3645. * PEER_UNMAP message arrives to remove the other
  3646. * reference, added by the PEER_MAP message.
  3647. */
  3648. dp_peer_unref_delete(peer_handle);
  3649. }
  3650. /*
  3651. * dp_get_vdev_mac_addr_wifi3() – Detach txrx peer
  3652. * @peer_handle: Datapath peer handle
  3653. *
  3654. */
  3655. static uint8 *dp_get_vdev_mac_addr_wifi3(struct cdp_vdev *pvdev)
  3656. {
  3657. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  3658. return vdev->mac_addr.raw;
  3659. }
  3660. /*
  3661. * dp_vdev_set_wds() - Enable per packet stats
  3662. * @vdev_handle: DP VDEV handle
  3663. * @val: value
  3664. *
  3665. * Return: none
  3666. */
  3667. static int dp_vdev_set_wds(void *vdev_handle, uint32_t val)
  3668. {
  3669. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3670. vdev->wds_enabled = val;
  3671. return 0;
  3672. }
  3673. /*
  3674. * dp_get_vdev_from_vdev_id_wifi3() – Detach txrx peer
  3675. * @peer_handle: Datapath peer handle
  3676. *
  3677. */
  3678. static struct cdp_vdev *dp_get_vdev_from_vdev_id_wifi3(struct cdp_pdev *dev,
  3679. uint8_t vdev_id)
  3680. {
  3681. struct dp_pdev *pdev = (struct dp_pdev *)dev;
  3682. struct dp_vdev *vdev = NULL;
  3683. if (qdf_unlikely(!pdev))
  3684. return NULL;
  3685. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3686. if (vdev->vdev_id == vdev_id)
  3687. break;
  3688. }
  3689. return (struct cdp_vdev *)vdev;
  3690. }
  3691. static int dp_get_opmode(struct cdp_vdev *vdev_handle)
  3692. {
  3693. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3694. return vdev->opmode;
  3695. }
  3696. static struct cdp_cfg *dp_get_ctrl_pdev_from_vdev_wifi3(struct cdp_vdev *pvdev)
  3697. {
  3698. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  3699. struct dp_pdev *pdev = vdev->pdev;
  3700. return (struct cdp_cfg *)pdev->wlan_cfg_ctx;
  3701. }
  3702. /**
  3703. * dp_reset_monitor_mode() - Disable monitor mode
  3704. * @pdev_handle: Datapath PDEV handle
  3705. *
  3706. * Return: 0 on success, not 0 on failure
  3707. */
  3708. static int dp_reset_monitor_mode(struct cdp_pdev *pdev_handle)
  3709. {
  3710. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3711. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3712. struct dp_soc *soc = pdev->soc;
  3713. uint8_t pdev_id;
  3714. int mac_id;
  3715. pdev_id = pdev->pdev_id;
  3716. soc = pdev->soc;
  3717. qdf_spin_lock_bh(&pdev->mon_lock);
  3718. qdf_mem_set(&(htt_tlv_filter), sizeof(htt_tlv_filter), 0x0);
  3719. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  3720. int mac_for_pdev = dp_get_mac_id_for_pdev(mac_id, pdev_id);
  3721. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  3722. pdev->rxdma_mon_buf_ring[mac_id].hal_srng,
  3723. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3724. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  3725. pdev->rxdma_mon_status_ring[mac_id].hal_srng,
  3726. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE, &htt_tlv_filter);
  3727. }
  3728. pdev->monitor_vdev = NULL;
  3729. qdf_spin_unlock_bh(&pdev->mon_lock);
  3730. return 0;
  3731. }
  3732. /**
  3733. * dp_set_nac() - set peer_nac
  3734. * @peer_handle: Datapath PEER handle
  3735. *
  3736. * Return: void
  3737. */
  3738. static void dp_set_nac(struct cdp_peer *peer_handle)
  3739. {
  3740. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  3741. peer->nac = 1;
  3742. }
  3743. /**
  3744. * dp_get_tx_pending() - read pending tx
  3745. * @pdev_handle: Datapath PDEV handle
  3746. *
  3747. * Return: outstanding tx
  3748. */
  3749. static int dp_get_tx_pending(struct cdp_pdev *pdev_handle)
  3750. {
  3751. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3752. return qdf_atomic_read(&pdev->num_tx_outstanding);
  3753. }
  3754. /**
  3755. * dp_get_peer_mac_from_peer_id() - get peer mac
  3756. * @pdev_handle: Datapath PDEV handle
  3757. * @peer_id: Peer ID
  3758. * @peer_mac: MAC addr of PEER
  3759. *
  3760. * Return: void
  3761. */
  3762. static void dp_get_peer_mac_from_peer_id(struct cdp_pdev *pdev_handle,
  3763. uint32_t peer_id, uint8_t *peer_mac)
  3764. {
  3765. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3766. struct dp_peer *peer;
  3767. if (pdev && peer_mac) {
  3768. peer = dp_peer_find_by_id(pdev->soc, (uint16_t)peer_id);
  3769. if (peer && peer->mac_addr.raw) {
  3770. qdf_mem_copy(peer_mac, peer->mac_addr.raw,
  3771. DP_MAC_ADDR_LEN);
  3772. }
  3773. }
  3774. }
  3775. /**
  3776. * dp_vdev_set_monitor_mode() - Set DP VDEV to monitor mode
  3777. * @vdev_handle: Datapath VDEV handle
  3778. * @smart_monitor: Flag to denote if its smart monitor mode
  3779. *
  3780. * Return: 0 on success, not 0 on failure
  3781. */
  3782. static int dp_vdev_set_monitor_mode(struct cdp_vdev *vdev_handle,
  3783. uint8_t smart_monitor)
  3784. {
  3785. /* Many monitor VAPs can exists in a system but only one can be up at
  3786. * anytime
  3787. */
  3788. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3789. struct dp_pdev *pdev;
  3790. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3791. struct dp_soc *soc;
  3792. uint8_t pdev_id;
  3793. int mac_id;
  3794. qdf_assert(vdev);
  3795. pdev = vdev->pdev;
  3796. pdev_id = pdev->pdev_id;
  3797. soc = pdev->soc;
  3798. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  3799. "pdev=%pK, pdev_id=%d, soc=%pK vdev=%pK\n",
  3800. pdev, pdev_id, soc, vdev);
  3801. /*Check if current pdev's monitor_vdev exists */
  3802. if (pdev->monitor_vdev) {
  3803. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3804. "vdev=%pK\n", vdev);
  3805. qdf_assert(vdev);
  3806. }
  3807. pdev->monitor_vdev = vdev;
  3808. /* If smart monitor mode, do not configure monitor ring */
  3809. if (smart_monitor)
  3810. return QDF_STATUS_SUCCESS;
  3811. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_INFO_HIGH,
  3812. "MODE[%x] FP[%02x|%02x|%02x] MO[%02x|%02x|%02x]\n",
  3813. pdev->mon_filter_mode, pdev->fp_mgmt_filter,
  3814. pdev->fp_ctrl_filter, pdev->fp_data_filter,
  3815. pdev->mo_mgmt_filter, pdev->mo_ctrl_filter,
  3816. pdev->mo_data_filter);
  3817. htt_tlv_filter.mpdu_start = 1;
  3818. htt_tlv_filter.msdu_start = 1;
  3819. htt_tlv_filter.packet = 1;
  3820. htt_tlv_filter.msdu_end = 1;
  3821. htt_tlv_filter.mpdu_end = 1;
  3822. htt_tlv_filter.packet_header = 1;
  3823. htt_tlv_filter.attention = 1;
  3824. htt_tlv_filter.ppdu_start = 0;
  3825. htt_tlv_filter.ppdu_end = 0;
  3826. htt_tlv_filter.ppdu_end_user_stats = 0;
  3827. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  3828. htt_tlv_filter.ppdu_end_status_done = 0;
  3829. htt_tlv_filter.header_per_msdu = 1;
  3830. htt_tlv_filter.enable_fp =
  3831. (pdev->mon_filter_mode & MON_FILTER_PASS) ? 1 : 0;
  3832. htt_tlv_filter.enable_md = 0;
  3833. htt_tlv_filter.enable_mo =
  3834. (pdev->mon_filter_mode & MON_FILTER_OTHER) ? 1 : 0;
  3835. htt_tlv_filter.fp_mgmt_filter = pdev->fp_mgmt_filter;
  3836. htt_tlv_filter.fp_ctrl_filter = pdev->fp_ctrl_filter;
  3837. htt_tlv_filter.fp_data_filter = pdev->fp_data_filter;
  3838. htt_tlv_filter.mo_mgmt_filter = pdev->mo_mgmt_filter;
  3839. htt_tlv_filter.mo_ctrl_filter = pdev->mo_ctrl_filter;
  3840. htt_tlv_filter.mo_data_filter = pdev->mo_data_filter;
  3841. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  3842. int mac_for_pdev = dp_get_mac_id_for_pdev(mac_id, pdev_id);
  3843. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  3844. pdev->rxdma_mon_buf_ring[mac_id].hal_srng,
  3845. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3846. }
  3847. htt_tlv_filter.mpdu_start = 1;
  3848. htt_tlv_filter.msdu_start = 1;
  3849. htt_tlv_filter.packet = 0;
  3850. htt_tlv_filter.msdu_end = 1;
  3851. htt_tlv_filter.mpdu_end = 1;
  3852. htt_tlv_filter.packet_header = 1;
  3853. htt_tlv_filter.attention = 1;
  3854. htt_tlv_filter.ppdu_start = 1;
  3855. htt_tlv_filter.ppdu_end = 1;
  3856. htt_tlv_filter.ppdu_end_user_stats = 1;
  3857. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3858. htt_tlv_filter.ppdu_end_status_done = 1;
  3859. htt_tlv_filter.header_per_msdu = 0;
  3860. htt_tlv_filter.enable_fp =
  3861. (pdev->mon_filter_mode & MON_FILTER_PASS) ? 1 : 0;
  3862. htt_tlv_filter.enable_md = 0;
  3863. htt_tlv_filter.enable_mo =
  3864. (pdev->mon_filter_mode & MON_FILTER_OTHER) ? 1 : 0;
  3865. htt_tlv_filter.fp_mgmt_filter = pdev->fp_mgmt_filter;
  3866. htt_tlv_filter.fp_ctrl_filter = pdev->fp_ctrl_filter;
  3867. htt_tlv_filter.fp_data_filter = pdev->fp_data_filter;
  3868. htt_tlv_filter.mo_mgmt_filter = pdev->mo_mgmt_filter;
  3869. htt_tlv_filter.mo_ctrl_filter = pdev->mo_ctrl_filter;
  3870. htt_tlv_filter.mo_data_filter = pdev->mo_data_filter;
  3871. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  3872. int mac_for_pdev = dp_get_mac_id_for_pdev(mac_id, pdev_id);
  3873. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  3874. pdev->rxdma_mon_status_ring[mac_id].hal_srng,
  3875. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE, &htt_tlv_filter);
  3876. }
  3877. return QDF_STATUS_SUCCESS;
  3878. }
  3879. /**
  3880. * dp_pdev_set_advance_monitor_filter() - Set DP PDEV monitor filter
  3881. * @pdev_handle: Datapath PDEV handle
  3882. * @filter_val: Flag to select Filter for monitor mode
  3883. * Return: 0 on success, not 0 on failure
  3884. */
  3885. static int dp_pdev_set_advance_monitor_filter(struct cdp_pdev *pdev_handle,
  3886. struct cdp_monitor_filter *filter_val)
  3887. {
  3888. /* Many monitor VAPs can exists in a system but only one can be up at
  3889. * anytime
  3890. */
  3891. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3892. struct dp_vdev *vdev = pdev->monitor_vdev;
  3893. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3894. struct dp_soc *soc;
  3895. uint8_t pdev_id;
  3896. int mac_id;
  3897. pdev_id = pdev->pdev_id;
  3898. soc = pdev->soc;
  3899. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  3900. "pdev=%pK, pdev_id=%d, soc=%pK vdev=%pK\n",
  3901. pdev, pdev_id, soc, vdev);
  3902. /*Check if current pdev's monitor_vdev exists */
  3903. if (!pdev->monitor_vdev) {
  3904. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3905. "vdev=%pK\n", vdev);
  3906. qdf_assert(vdev);
  3907. }
  3908. /* update filter mode, type in pdev structure */
  3909. pdev->mon_filter_mode = filter_val->mode;
  3910. pdev->fp_mgmt_filter = filter_val->fp_mgmt;
  3911. pdev->fp_ctrl_filter = filter_val->fp_ctrl;
  3912. pdev->fp_data_filter = filter_val->fp_data;
  3913. pdev->mo_mgmt_filter = filter_val->mo_mgmt;
  3914. pdev->mo_ctrl_filter = filter_val->mo_ctrl;
  3915. pdev->mo_data_filter = filter_val->mo_data;
  3916. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_INFO_HIGH,
  3917. "MODE[%x] FP[%02x|%02x|%02x] MO[%02x|%02x|%02x]\n",
  3918. pdev->mon_filter_mode, pdev->fp_mgmt_filter,
  3919. pdev->fp_ctrl_filter, pdev->fp_data_filter,
  3920. pdev->mo_mgmt_filter, pdev->mo_ctrl_filter,
  3921. pdev->mo_data_filter);
  3922. qdf_mem_set(&(htt_tlv_filter), sizeof(htt_tlv_filter), 0x0);
  3923. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  3924. int mac_for_pdev = dp_get_mac_id_for_pdev(mac_id, pdev_id);
  3925. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  3926. pdev->rxdma_mon_buf_ring[mac_id].hal_srng,
  3927. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3928. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  3929. pdev->rxdma_mon_status_ring[mac_id].hal_srng,
  3930. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE, &htt_tlv_filter);
  3931. }
  3932. htt_tlv_filter.mpdu_start = 1;
  3933. htt_tlv_filter.msdu_start = 1;
  3934. htt_tlv_filter.packet = 1;
  3935. htt_tlv_filter.msdu_end = 1;
  3936. htt_tlv_filter.mpdu_end = 1;
  3937. htt_tlv_filter.packet_header = 1;
  3938. htt_tlv_filter.attention = 1;
  3939. htt_tlv_filter.ppdu_start = 0;
  3940. htt_tlv_filter.ppdu_end = 0;
  3941. htt_tlv_filter.ppdu_end_user_stats = 0;
  3942. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  3943. htt_tlv_filter.ppdu_end_status_done = 0;
  3944. htt_tlv_filter.header_per_msdu = 1;
  3945. htt_tlv_filter.enable_fp =
  3946. (pdev->mon_filter_mode & MON_FILTER_PASS) ? 1 : 0;
  3947. htt_tlv_filter.enable_md = 0;
  3948. htt_tlv_filter.enable_mo =
  3949. (pdev->mon_filter_mode & MON_FILTER_OTHER) ? 1 : 0;
  3950. htt_tlv_filter.fp_mgmt_filter = pdev->fp_mgmt_filter;
  3951. htt_tlv_filter.fp_ctrl_filter = pdev->fp_ctrl_filter;
  3952. htt_tlv_filter.fp_data_filter = pdev->fp_data_filter;
  3953. htt_tlv_filter.mo_mgmt_filter = pdev->mo_mgmt_filter;
  3954. htt_tlv_filter.mo_ctrl_filter = pdev->mo_ctrl_filter;
  3955. htt_tlv_filter.mo_data_filter = pdev->mo_data_filter;
  3956. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  3957. int mac_for_pdev = dp_get_mac_id_for_pdev(mac_id, pdev_id);
  3958. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  3959. pdev->rxdma_mon_buf_ring[mac_id].hal_srng,
  3960. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3961. }
  3962. htt_tlv_filter.mpdu_start = 1;
  3963. htt_tlv_filter.msdu_start = 1;
  3964. htt_tlv_filter.packet = 0;
  3965. htt_tlv_filter.msdu_end = 1;
  3966. htt_tlv_filter.mpdu_end = 1;
  3967. htt_tlv_filter.packet_header = 1;
  3968. htt_tlv_filter.attention = 1;
  3969. htt_tlv_filter.ppdu_start = 1;
  3970. htt_tlv_filter.ppdu_end = 1;
  3971. htt_tlv_filter.ppdu_end_user_stats = 1;
  3972. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3973. htt_tlv_filter.ppdu_end_status_done = 1;
  3974. htt_tlv_filter.header_per_msdu = 0;
  3975. htt_tlv_filter.enable_fp =
  3976. (pdev->mon_filter_mode & MON_FILTER_PASS) ? 1 : 0;
  3977. htt_tlv_filter.enable_md = 0;
  3978. htt_tlv_filter.enable_mo =
  3979. (pdev->mon_filter_mode & MON_FILTER_OTHER) ? 1 : 0;
  3980. htt_tlv_filter.fp_mgmt_filter = pdev->fp_mgmt_filter;
  3981. htt_tlv_filter.fp_ctrl_filter = pdev->fp_ctrl_filter;
  3982. htt_tlv_filter.fp_data_filter = pdev->fp_data_filter;
  3983. htt_tlv_filter.mo_mgmt_filter = pdev->mo_mgmt_filter;
  3984. htt_tlv_filter.mo_ctrl_filter = pdev->mo_ctrl_filter;
  3985. htt_tlv_filter.mo_data_filter = pdev->mo_data_filter;
  3986. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  3987. int mac_for_pdev = dp_get_mac_id_for_pdev(mac_id, pdev_id);
  3988. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  3989. pdev->rxdma_mon_status_ring[mac_id].hal_srng,
  3990. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE, &htt_tlv_filter);
  3991. }
  3992. return QDF_STATUS_SUCCESS;
  3993. }
  3994. /**
  3995. * dp_get_pdev_id_frm_pdev() - get pdev_id
  3996. * @pdev_handle: Datapath PDEV handle
  3997. *
  3998. * Return: pdev_id
  3999. */
  4000. static
  4001. uint8_t dp_get_pdev_id_frm_pdev(struct cdp_pdev *pdev_handle)
  4002. {
  4003. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4004. return pdev->pdev_id;
  4005. }
  4006. /**
  4007. * dp_vdev_get_filter_ucast_data() - get DP VDEV monitor ucast filter
  4008. * @vdev_handle: Datapath VDEV handle
  4009. * Return: true on ucast filter flag set
  4010. */
  4011. static bool dp_vdev_get_filter_ucast_data(struct cdp_vdev *vdev_handle)
  4012. {
  4013. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4014. struct dp_pdev *pdev;
  4015. pdev = vdev->pdev;
  4016. if ((pdev->fp_data_filter & FILTER_DATA_UCAST) ||
  4017. (pdev->mo_data_filter & FILTER_DATA_UCAST))
  4018. return true;
  4019. return false;
  4020. }
  4021. /**
  4022. * dp_vdev_get_filter_mcast_data() - get DP VDEV monitor mcast filter
  4023. * @vdev_handle: Datapath VDEV handle
  4024. * Return: true on mcast filter flag set
  4025. */
  4026. static bool dp_vdev_get_filter_mcast_data(struct cdp_vdev *vdev_handle)
  4027. {
  4028. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4029. struct dp_pdev *pdev;
  4030. pdev = vdev->pdev;
  4031. if ((pdev->fp_data_filter & FILTER_DATA_MCAST) ||
  4032. (pdev->mo_data_filter & FILTER_DATA_MCAST))
  4033. return true;
  4034. return false;
  4035. }
  4036. /**
  4037. * dp_vdev_get_filter_non_data() - get DP VDEV monitor non_data filter
  4038. * @vdev_handle: Datapath VDEV handle
  4039. * Return: true on non data filter flag set
  4040. */
  4041. static bool dp_vdev_get_filter_non_data(struct cdp_vdev *vdev_handle)
  4042. {
  4043. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4044. struct dp_pdev *pdev;
  4045. pdev = vdev->pdev;
  4046. if ((pdev->fp_mgmt_filter & FILTER_MGMT_ALL) ||
  4047. (pdev->mo_mgmt_filter & FILTER_MGMT_ALL)) {
  4048. if ((pdev->fp_ctrl_filter & FILTER_CTRL_ALL) ||
  4049. (pdev->mo_ctrl_filter & FILTER_CTRL_ALL)) {
  4050. return true;
  4051. }
  4052. }
  4053. return false;
  4054. }
  4055. #ifdef MESH_MODE_SUPPORT
  4056. void dp_peer_set_mesh_mode(struct cdp_vdev *vdev_hdl, uint32_t val)
  4057. {
  4058. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  4059. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4060. FL("val %d"), val);
  4061. vdev->mesh_vdev = val;
  4062. }
  4063. /*
  4064. * dp_peer_set_mesh_rx_filter() - to set the mesh rx filter
  4065. * @vdev_hdl: virtual device object
  4066. * @val: value to be set
  4067. *
  4068. * Return: void
  4069. */
  4070. void dp_peer_set_mesh_rx_filter(struct cdp_vdev *vdev_hdl, uint32_t val)
  4071. {
  4072. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  4073. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4074. FL("val %d"), val);
  4075. vdev->mesh_rx_filter = val;
  4076. }
  4077. #endif
  4078. /*
  4079. * dp_aggregate_pdev_ctrl_frames_stats()- function to agreegate peer stats
  4080. * Current scope is bar recieved count
  4081. *
  4082. * @pdev_handle: DP_PDEV handle
  4083. *
  4084. * Return: void
  4085. */
  4086. #define STATS_PROC_TIMEOUT (HZ/1000)
  4087. static void
  4088. dp_aggregate_pdev_ctrl_frames_stats(struct dp_pdev *pdev)
  4089. {
  4090. struct dp_vdev *vdev;
  4091. struct dp_peer *peer;
  4092. uint32_t waitcnt;
  4093. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  4094. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  4095. if (!peer) {
  4096. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4097. FL("DP Invalid Peer refernce"));
  4098. return;
  4099. }
  4100. if (peer->delete_in_progress) {
  4101. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4102. FL("DP Peer deletion in progress"));
  4103. continue;
  4104. }
  4105. qdf_atomic_inc(&peer->ref_cnt);
  4106. waitcnt = 0;
  4107. dp_peer_rxtid_stats(peer, dp_rx_bar_stats_cb, pdev);
  4108. while (!(qdf_atomic_read(&(pdev->stats_cmd_complete)))
  4109. && waitcnt < 10) {
  4110. schedule_timeout_interruptible(
  4111. STATS_PROC_TIMEOUT);
  4112. waitcnt++;
  4113. }
  4114. qdf_atomic_set(&(pdev->stats_cmd_complete), 0);
  4115. dp_peer_unref_delete(peer);
  4116. }
  4117. }
  4118. }
  4119. /**
  4120. * dp_rx_bar_stats_cb(): BAR received stats callback
  4121. * @soc: SOC handle
  4122. * @cb_ctxt: Call back context
  4123. * @reo_status: Reo status
  4124. *
  4125. * return: void
  4126. */
  4127. void dp_rx_bar_stats_cb(struct dp_soc *soc, void *cb_ctxt,
  4128. union hal_reo_status *reo_status)
  4129. {
  4130. struct dp_pdev *pdev = (struct dp_pdev *)cb_ctxt;
  4131. struct hal_reo_queue_status *queue_status = &(reo_status->queue_status);
  4132. if (queue_status->header.status != HAL_REO_CMD_SUCCESS) {
  4133. DP_TRACE_STATS(FATAL, "REO stats failure %d \n",
  4134. queue_status->header.status);
  4135. qdf_atomic_set(&(pdev->stats_cmd_complete), 1);
  4136. return;
  4137. }
  4138. pdev->stats.rx.bar_recv_cnt += queue_status->bar_rcvd_cnt;
  4139. qdf_atomic_set(&(pdev->stats_cmd_complete), 1);
  4140. }
  4141. /**
  4142. * dp_aggregate_vdev_stats(): Consolidate stats at VDEV level
  4143. * @vdev: DP VDEV handle
  4144. *
  4145. * return: void
  4146. */
  4147. void dp_aggregate_vdev_stats(struct dp_vdev *vdev)
  4148. {
  4149. struct dp_peer *peer = NULL;
  4150. struct dp_soc *soc = vdev->pdev->soc;
  4151. qdf_mem_set(&(vdev->stats.tx), sizeof(vdev->stats.tx), 0x0);
  4152. qdf_mem_set(&(vdev->stats.rx), sizeof(vdev->stats.rx), 0x0);
  4153. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem)
  4154. DP_UPDATE_STATS(vdev, peer);
  4155. if (soc->cdp_soc.ol_ops->update_dp_stats)
  4156. soc->cdp_soc.ol_ops->update_dp_stats(vdev->pdev->osif_pdev,
  4157. &vdev->stats, (uint16_t) vdev->vdev_id,
  4158. UPDATE_VDEV_STATS);
  4159. }
  4160. /**
  4161. * dp_aggregate_pdev_stats(): Consolidate stats at PDEV level
  4162. * @pdev: DP PDEV handle
  4163. *
  4164. * return: void
  4165. */
  4166. static inline void dp_aggregate_pdev_stats(struct dp_pdev *pdev)
  4167. {
  4168. struct dp_vdev *vdev = NULL;
  4169. struct dp_soc *soc = pdev->soc;
  4170. qdf_mem_set(&(pdev->stats.tx), sizeof(pdev->stats.tx), 0x0);
  4171. qdf_mem_set(&(pdev->stats.rx), sizeof(pdev->stats.rx), 0x0);
  4172. qdf_mem_set(&(pdev->stats.tx_i), sizeof(pdev->stats.tx_i), 0x0);
  4173. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  4174. dp_aggregate_vdev_stats(vdev);
  4175. DP_UPDATE_STATS(pdev, vdev);
  4176. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.nawds_mcast);
  4177. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.rcvd);
  4178. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.processed);
  4179. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.reinject_pkts);
  4180. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.inspect_pkts);
  4181. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.raw.raw_pkt);
  4182. DP_STATS_AGGR(pdev, vdev, tx_i.raw.dma_map_error);
  4183. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.tso.tso_pkt);
  4184. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_host);
  4185. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_target);
  4186. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_host);
  4187. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_target);
  4188. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.sg.sg_pkt);
  4189. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.mcast_en.mcast_pkt);
  4190. DP_STATS_AGGR(pdev, vdev,
  4191. tx_i.mcast_en.dropped_map_error);
  4192. DP_STATS_AGGR(pdev, vdev,
  4193. tx_i.mcast_en.dropped_self_mac);
  4194. DP_STATS_AGGR(pdev, vdev,
  4195. tx_i.mcast_en.dropped_send_fail);
  4196. DP_STATS_AGGR(pdev, vdev, tx_i.mcast_en.ucast);
  4197. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.dma_error);
  4198. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.ring_full);
  4199. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.enqueue_fail);
  4200. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.desc_na);
  4201. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.res_full);
  4202. DP_STATS_AGGR(pdev, vdev, tx_i.cce_classified);
  4203. DP_STATS_AGGR(pdev, vdev, tx_i.cce_classified_raw);
  4204. DP_STATS_AGGR(pdev, vdev, tx_i.mesh.exception_fw);
  4205. DP_STATS_AGGR(pdev, vdev, tx_i.mesh.completion_fw);
  4206. pdev->stats.tx_i.dropped.dropped_pkt.num =
  4207. pdev->stats.tx_i.dropped.dma_error +
  4208. pdev->stats.tx_i.dropped.ring_full +
  4209. pdev->stats.tx_i.dropped.enqueue_fail +
  4210. pdev->stats.tx_i.dropped.desc_na +
  4211. pdev->stats.tx_i.dropped.res_full;
  4212. pdev->stats.tx.last_ack_rssi =
  4213. vdev->stats.tx.last_ack_rssi;
  4214. pdev->stats.tx_i.tso.num_seg =
  4215. vdev->stats.tx_i.tso.num_seg;
  4216. }
  4217. if (soc->cdp_soc.ol_ops->update_dp_stats)
  4218. soc->cdp_soc.ol_ops->update_dp_stats(pdev->osif_pdev,
  4219. &pdev->stats, pdev->pdev_id, UPDATE_PDEV_STATS);
  4220. }
  4221. /**
  4222. * dp_pdev_getstats() - get pdev packet level stats
  4223. * @pdev_handle: Datapath PDEV handle
  4224. * @stats: cdp network device stats structure
  4225. *
  4226. * Return: void
  4227. */
  4228. static void dp_pdev_getstats(struct cdp_pdev *pdev_handle,
  4229. struct cdp_dev_stats *stats)
  4230. {
  4231. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4232. dp_aggregate_pdev_stats(pdev);
  4233. stats->tx_packets = pdev->stats.tx_i.rcvd.num;
  4234. stats->tx_bytes = pdev->stats.tx_i.rcvd.bytes;
  4235. stats->tx_errors = pdev->stats.tx.tx_failed +
  4236. pdev->stats.tx_i.dropped.dropped_pkt.num;
  4237. stats->tx_dropped = stats->tx_errors;
  4238. stats->rx_packets = pdev->stats.rx.unicast.num +
  4239. pdev->stats.rx.multicast.num;
  4240. stats->rx_bytes = pdev->stats.rx.unicast.bytes +
  4241. pdev->stats.rx.multicast.bytes;
  4242. }
  4243. /**
  4244. * dp_print_pdev_tx_stats(): Print Pdev level TX stats
  4245. * @pdev: DP_PDEV Handle
  4246. *
  4247. * Return:void
  4248. */
  4249. static inline void
  4250. dp_print_pdev_tx_stats(struct dp_pdev *pdev)
  4251. {
  4252. uint8_t index = 0;
  4253. DP_PRINT_STATS("PDEV Tx Stats:\n");
  4254. DP_PRINT_STATS("Received From Stack:");
  4255. DP_PRINT_STATS(" Packets = %d",
  4256. pdev->stats.tx_i.rcvd.num);
  4257. DP_PRINT_STATS(" Bytes = %llu",
  4258. pdev->stats.tx_i.rcvd.bytes);
  4259. DP_PRINT_STATS("Processed:");
  4260. DP_PRINT_STATS(" Packets = %d",
  4261. pdev->stats.tx_i.processed.num);
  4262. DP_PRINT_STATS(" Bytes = %llu",
  4263. pdev->stats.tx_i.processed.bytes);
  4264. DP_PRINT_STATS("Total Completions:");
  4265. DP_PRINT_STATS(" Packets = %u",
  4266. pdev->stats.tx.comp_pkt.num);
  4267. DP_PRINT_STATS(" Bytes = %llu",
  4268. pdev->stats.tx.comp_pkt.bytes);
  4269. DP_PRINT_STATS("Successful Completions:");
  4270. DP_PRINT_STATS(" Packets = %u",
  4271. pdev->stats.tx.tx_success.num);
  4272. DP_PRINT_STATS(" Bytes = %llu",
  4273. pdev->stats.tx.tx_success.bytes);
  4274. DP_PRINT_STATS("Dropped:");
  4275. DP_PRINT_STATS(" Total = %d",
  4276. pdev->stats.tx_i.dropped.dropped_pkt.num);
  4277. DP_PRINT_STATS(" Dma_map_error = %d",
  4278. pdev->stats.tx_i.dropped.dma_error);
  4279. DP_PRINT_STATS(" Ring Full = %d",
  4280. pdev->stats.tx_i.dropped.ring_full);
  4281. DP_PRINT_STATS(" Descriptor Not available = %d",
  4282. pdev->stats.tx_i.dropped.desc_na);
  4283. DP_PRINT_STATS(" HW enqueue failed= %d",
  4284. pdev->stats.tx_i.dropped.enqueue_fail);
  4285. DP_PRINT_STATS(" Resources Full = %d",
  4286. pdev->stats.tx_i.dropped.res_full);
  4287. DP_PRINT_STATS(" FW removed = %d",
  4288. pdev->stats.tx.dropped.fw_rem);
  4289. DP_PRINT_STATS(" FW removed transmitted = %d",
  4290. pdev->stats.tx.dropped.fw_rem_tx);
  4291. DP_PRINT_STATS(" FW removed untransmitted = %d",
  4292. pdev->stats.tx.dropped.fw_rem_notx);
  4293. DP_PRINT_STATS(" FW removed untransmitted fw_reason1 = %d",
  4294. pdev->stats.tx.dropped.fw_reason1);
  4295. DP_PRINT_STATS(" FW removed untransmitted fw_reason2 = %d",
  4296. pdev->stats.tx.dropped.fw_reason2);
  4297. DP_PRINT_STATS(" FW removed untransmitted fw_reason3 = %d",
  4298. pdev->stats.tx.dropped.fw_reason3);
  4299. DP_PRINT_STATS(" Aged Out from msdu/mpdu queues = %d",
  4300. pdev->stats.tx.dropped.age_out);
  4301. DP_PRINT_STATS("Scatter Gather:");
  4302. DP_PRINT_STATS(" Packets = %d",
  4303. pdev->stats.tx_i.sg.sg_pkt.num);
  4304. DP_PRINT_STATS(" Bytes = %llu",
  4305. pdev->stats.tx_i.sg.sg_pkt.bytes);
  4306. DP_PRINT_STATS(" Dropped By Host = %d",
  4307. pdev->stats.tx_i.sg.dropped_host);
  4308. DP_PRINT_STATS(" Dropped By Target = %d",
  4309. pdev->stats.tx_i.sg.dropped_target);
  4310. DP_PRINT_STATS("TSO:");
  4311. DP_PRINT_STATS(" Number of Segments = %d",
  4312. pdev->stats.tx_i.tso.num_seg);
  4313. DP_PRINT_STATS(" Packets = %d",
  4314. pdev->stats.tx_i.tso.tso_pkt.num);
  4315. DP_PRINT_STATS(" Bytes = %llu",
  4316. pdev->stats.tx_i.tso.tso_pkt.bytes);
  4317. DP_PRINT_STATS(" Dropped By Host = %d",
  4318. pdev->stats.tx_i.tso.dropped_host);
  4319. DP_PRINT_STATS("Mcast Enhancement:");
  4320. DP_PRINT_STATS(" Packets = %d",
  4321. pdev->stats.tx_i.mcast_en.mcast_pkt.num);
  4322. DP_PRINT_STATS(" Bytes = %llu",
  4323. pdev->stats.tx_i.mcast_en.mcast_pkt.bytes);
  4324. DP_PRINT_STATS(" Dropped: Map Errors = %d",
  4325. pdev->stats.tx_i.mcast_en.dropped_map_error);
  4326. DP_PRINT_STATS(" Dropped: Self Mac = %d",
  4327. pdev->stats.tx_i.mcast_en.dropped_self_mac);
  4328. DP_PRINT_STATS(" Dropped: Send Fail = %d",
  4329. pdev->stats.tx_i.mcast_en.dropped_send_fail);
  4330. DP_PRINT_STATS(" Unicast sent = %d",
  4331. pdev->stats.tx_i.mcast_en.ucast);
  4332. DP_PRINT_STATS("Raw:");
  4333. DP_PRINT_STATS(" Packets = %d",
  4334. pdev->stats.tx_i.raw.raw_pkt.num);
  4335. DP_PRINT_STATS(" Bytes = %llu",
  4336. pdev->stats.tx_i.raw.raw_pkt.bytes);
  4337. DP_PRINT_STATS(" DMA map error = %d",
  4338. pdev->stats.tx_i.raw.dma_map_error);
  4339. DP_PRINT_STATS("Reinjected:");
  4340. DP_PRINT_STATS(" Packets = %d",
  4341. pdev->stats.tx_i.reinject_pkts.num);
  4342. DP_PRINT_STATS("Bytes = %llu\n",
  4343. pdev->stats.tx_i.reinject_pkts.bytes);
  4344. DP_PRINT_STATS("Inspected:");
  4345. DP_PRINT_STATS(" Packets = %d",
  4346. pdev->stats.tx_i.inspect_pkts.num);
  4347. DP_PRINT_STATS(" Bytes = %llu",
  4348. pdev->stats.tx_i.inspect_pkts.bytes);
  4349. DP_PRINT_STATS("Nawds Multicast:");
  4350. DP_PRINT_STATS(" Packets = %d",
  4351. pdev->stats.tx_i.nawds_mcast.num);
  4352. DP_PRINT_STATS(" Bytes = %llu",
  4353. pdev->stats.tx_i.nawds_mcast.bytes);
  4354. DP_PRINT_STATS("CCE Classified:");
  4355. DP_PRINT_STATS(" CCE Classified Packets: %u",
  4356. pdev->stats.tx_i.cce_classified);
  4357. DP_PRINT_STATS(" RAW CCE Classified Packets: %u",
  4358. pdev->stats.tx_i.cce_classified_raw);
  4359. DP_PRINT_STATS("Mesh stats:");
  4360. DP_PRINT_STATS(" frames to firmware: %u",
  4361. pdev->stats.tx_i.mesh.exception_fw);
  4362. DP_PRINT_STATS(" completions from fw: %u",
  4363. pdev->stats.tx_i.mesh.completion_fw);
  4364. DP_PRINT_STATS("PPDU stats counter");
  4365. for (index = 0; index < CDP_PPDU_STATS_MAX_TAG; index++) {
  4366. DP_PRINT_STATS(" Tag[%d] = %llu", index,
  4367. pdev->stats.ppdu_stats_counter[index]);
  4368. }
  4369. }
  4370. /**
  4371. * dp_print_pdev_rx_stats(): Print Pdev level RX stats
  4372. * @pdev: DP_PDEV Handle
  4373. *
  4374. * Return: void
  4375. */
  4376. static inline void
  4377. dp_print_pdev_rx_stats(struct dp_pdev *pdev)
  4378. {
  4379. DP_PRINT_STATS("PDEV Rx Stats:\n");
  4380. DP_PRINT_STATS("Received From HW (Per Rx Ring):");
  4381. DP_PRINT_STATS(" Packets = %d %d %d %d",
  4382. pdev->stats.rx.rcvd_reo[0].num,
  4383. pdev->stats.rx.rcvd_reo[1].num,
  4384. pdev->stats.rx.rcvd_reo[2].num,
  4385. pdev->stats.rx.rcvd_reo[3].num);
  4386. DP_PRINT_STATS(" Bytes = %llu %llu %llu %llu",
  4387. pdev->stats.rx.rcvd_reo[0].bytes,
  4388. pdev->stats.rx.rcvd_reo[1].bytes,
  4389. pdev->stats.rx.rcvd_reo[2].bytes,
  4390. pdev->stats.rx.rcvd_reo[3].bytes);
  4391. DP_PRINT_STATS("Replenished:");
  4392. DP_PRINT_STATS(" Packets = %d",
  4393. pdev->stats.replenish.pkts.num);
  4394. DP_PRINT_STATS(" Bytes = %llu",
  4395. pdev->stats.replenish.pkts.bytes);
  4396. DP_PRINT_STATS(" Buffers Added To Freelist = %d",
  4397. pdev->stats.buf_freelist);
  4398. DP_PRINT_STATS(" Low threshold intr = %d",
  4399. pdev->stats.replenish.low_thresh_intrs);
  4400. DP_PRINT_STATS("Dropped:");
  4401. DP_PRINT_STATS(" msdu_not_done = %d",
  4402. pdev->stats.dropped.msdu_not_done);
  4403. DP_PRINT_STATS(" mon_rx_drop = %d",
  4404. pdev->stats.dropped.mon_rx_drop);
  4405. DP_PRINT_STATS("Sent To Stack:");
  4406. DP_PRINT_STATS(" Packets = %d",
  4407. pdev->stats.rx.to_stack.num);
  4408. DP_PRINT_STATS(" Bytes = %llu",
  4409. pdev->stats.rx.to_stack.bytes);
  4410. DP_PRINT_STATS("Multicast/Broadcast:");
  4411. DP_PRINT_STATS(" Packets = %d",
  4412. pdev->stats.rx.multicast.num);
  4413. DP_PRINT_STATS(" Bytes = %llu",
  4414. pdev->stats.rx.multicast.bytes);
  4415. DP_PRINT_STATS("Errors:");
  4416. DP_PRINT_STATS(" Rxdma Ring Un-inititalized = %d",
  4417. pdev->stats.replenish.rxdma_err);
  4418. DP_PRINT_STATS(" Desc Alloc Failed: = %d",
  4419. pdev->stats.err.desc_alloc_fail);
  4420. /* Get bar_recv_cnt */
  4421. dp_aggregate_pdev_ctrl_frames_stats(pdev);
  4422. DP_PRINT_STATS("BAR Received Count: = %d",
  4423. pdev->stats.rx.bar_recv_cnt);
  4424. }
  4425. /**
  4426. * dp_print_soc_tx_stats(): Print SOC level stats
  4427. * @soc DP_SOC Handle
  4428. *
  4429. * Return: void
  4430. */
  4431. static inline void
  4432. dp_print_soc_tx_stats(struct dp_soc *soc)
  4433. {
  4434. DP_PRINT_STATS("SOC Tx Stats:\n");
  4435. DP_PRINT_STATS("Tx Descriptors In Use = %d",
  4436. soc->stats.tx.desc_in_use);
  4437. DP_PRINT_STATS("Invalid peer:");
  4438. DP_PRINT_STATS(" Packets = %d",
  4439. soc->stats.tx.tx_invalid_peer.num);
  4440. DP_PRINT_STATS(" Bytes = %llu",
  4441. soc->stats.tx.tx_invalid_peer.bytes);
  4442. DP_PRINT_STATS("Packets dropped due to TCL ring full = %d %d %d",
  4443. soc->stats.tx.tcl_ring_full[0],
  4444. soc->stats.tx.tcl_ring_full[1],
  4445. soc->stats.tx.tcl_ring_full[2]);
  4446. }
  4447. /**
  4448. * dp_print_soc_rx_stats: Print SOC level Rx stats
  4449. * @soc: DP_SOC Handle
  4450. *
  4451. * Return:void
  4452. */
  4453. static inline void
  4454. dp_print_soc_rx_stats(struct dp_soc *soc)
  4455. {
  4456. uint32_t i;
  4457. char reo_error[DP_REO_ERR_LENGTH];
  4458. char rxdma_error[DP_RXDMA_ERR_LENGTH];
  4459. uint8_t index = 0;
  4460. DP_PRINT_STATS("SOC Rx Stats:\n");
  4461. DP_PRINT_STATS("Errors:\n");
  4462. DP_PRINT_STATS("Rx Decrypt Errors = %d",
  4463. (soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_DECRYPT] +
  4464. soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_TKIP_MIC]));
  4465. DP_PRINT_STATS("Invalid RBM = %d",
  4466. soc->stats.rx.err.invalid_rbm);
  4467. DP_PRINT_STATS("Invalid Vdev = %d",
  4468. soc->stats.rx.err.invalid_vdev);
  4469. DP_PRINT_STATS("Invalid Pdev = %d",
  4470. soc->stats.rx.err.invalid_pdev);
  4471. DP_PRINT_STATS("Invalid Peer = %d",
  4472. soc->stats.rx.err.rx_invalid_peer.num);
  4473. DP_PRINT_STATS("HAL Ring Access Fail = %d",
  4474. soc->stats.rx.err.hal_ring_access_fail);
  4475. for (i = 0; i < HAL_RXDMA_ERR_MAX; i++) {
  4476. index += qdf_snprint(&rxdma_error[index],
  4477. DP_RXDMA_ERR_LENGTH - index,
  4478. " %d", soc->stats.rx.err.rxdma_error[i]);
  4479. }
  4480. DP_PRINT_STATS("RXDMA Error (0-31):%s",
  4481. rxdma_error);
  4482. index = 0;
  4483. for (i = 0; i < HAL_REO_ERR_MAX; i++) {
  4484. index += qdf_snprint(&reo_error[index],
  4485. DP_REO_ERR_LENGTH - index,
  4486. " %d", soc->stats.rx.err.reo_error[i]);
  4487. }
  4488. DP_PRINT_STATS("REO Error(0-14):%s",
  4489. reo_error);
  4490. }
  4491. /**
  4492. * dp_print_ring_stat_from_hal(): Print hal level ring stats
  4493. * @soc: DP_SOC handle
  4494. * @srng: DP_SRNG handle
  4495. * @ring_name: SRNG name
  4496. *
  4497. * Return: void
  4498. */
  4499. static inline void
  4500. dp_print_ring_stat_from_hal(struct dp_soc *soc, struct dp_srng *srng,
  4501. char *ring_name)
  4502. {
  4503. uint32_t tailp;
  4504. uint32_t headp;
  4505. if (srng->hal_srng != NULL) {
  4506. hal_api_get_tphp(soc->hal_soc, srng->hal_srng, &tailp, &headp);
  4507. DP_PRINT_STATS("%s : Head pointer = %d Tail Pointer = %d\n",
  4508. ring_name, headp, tailp);
  4509. }
  4510. }
  4511. /**
  4512. * dp_print_ring_stats(): Print tail and head pointer
  4513. * @pdev: DP_PDEV handle
  4514. *
  4515. * Return:void
  4516. */
  4517. static inline void
  4518. dp_print_ring_stats(struct dp_pdev *pdev)
  4519. {
  4520. uint32_t i;
  4521. char ring_name[STR_MAXLEN + 1];
  4522. int mac_id;
  4523. dp_print_ring_stat_from_hal(pdev->soc,
  4524. &pdev->soc->reo_exception_ring,
  4525. "Reo Exception Ring");
  4526. dp_print_ring_stat_from_hal(pdev->soc,
  4527. &pdev->soc->reo_reinject_ring,
  4528. "Reo Inject Ring");
  4529. dp_print_ring_stat_from_hal(pdev->soc,
  4530. &pdev->soc->reo_cmd_ring,
  4531. "Reo Command Ring");
  4532. dp_print_ring_stat_from_hal(pdev->soc,
  4533. &pdev->soc->reo_status_ring,
  4534. "Reo Status Ring");
  4535. dp_print_ring_stat_from_hal(pdev->soc,
  4536. &pdev->soc->rx_rel_ring,
  4537. "Rx Release ring");
  4538. dp_print_ring_stat_from_hal(pdev->soc,
  4539. &pdev->soc->tcl_cmd_ring,
  4540. "Tcl command Ring");
  4541. dp_print_ring_stat_from_hal(pdev->soc,
  4542. &pdev->soc->tcl_status_ring,
  4543. "Tcl Status Ring");
  4544. dp_print_ring_stat_from_hal(pdev->soc,
  4545. &pdev->soc->wbm_desc_rel_ring,
  4546. "Wbm Desc Rel Ring");
  4547. for (i = 0; i < MAX_REO_DEST_RINGS; i++) {
  4548. snprintf(ring_name, STR_MAXLEN, "Reo Dest Ring %d", i);
  4549. dp_print_ring_stat_from_hal(pdev->soc,
  4550. &pdev->soc->reo_dest_ring[i],
  4551. ring_name);
  4552. }
  4553. for (i = 0; i < pdev->soc->num_tcl_data_rings; i++) {
  4554. snprintf(ring_name, STR_MAXLEN, "Tcl Data Ring %d", i);
  4555. dp_print_ring_stat_from_hal(pdev->soc,
  4556. &pdev->soc->tcl_data_ring[i],
  4557. ring_name);
  4558. }
  4559. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  4560. snprintf(ring_name, STR_MAXLEN, "Tx Comp Ring %d", i);
  4561. dp_print_ring_stat_from_hal(pdev->soc,
  4562. &pdev->soc->tx_comp_ring[i],
  4563. ring_name);
  4564. }
  4565. dp_print_ring_stat_from_hal(pdev->soc,
  4566. &pdev->rx_refill_buf_ring,
  4567. "Rx Refill Buf Ring");
  4568. dp_print_ring_stat_from_hal(pdev->soc,
  4569. &pdev->rx_refill_buf_ring2,
  4570. "Second Rx Refill Buf Ring");
  4571. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  4572. dp_print_ring_stat_from_hal(pdev->soc,
  4573. &pdev->rxdma_mon_buf_ring[mac_id],
  4574. "Rxdma Mon Buf Ring");
  4575. dp_print_ring_stat_from_hal(pdev->soc,
  4576. &pdev->rxdma_mon_dst_ring[mac_id],
  4577. "Rxdma Mon Dst Ring");
  4578. dp_print_ring_stat_from_hal(pdev->soc,
  4579. &pdev->rxdma_mon_status_ring[mac_id],
  4580. "Rxdma Mon Status Ring");
  4581. dp_print_ring_stat_from_hal(pdev->soc,
  4582. &pdev->rxdma_mon_desc_ring[mac_id],
  4583. "Rxdma mon desc Ring");
  4584. }
  4585. for (i = 0; i < MAX_RX_MAC_RINGS; i++) {
  4586. snprintf(ring_name, STR_MAXLEN, "Rxdma err dst ring %d", i);
  4587. dp_print_ring_stat_from_hal(pdev->soc,
  4588. &pdev->rxdma_err_dst_ring[i],
  4589. ring_name);
  4590. }
  4591. for (i = 0; i < MAX_RX_MAC_RINGS; i++) {
  4592. snprintf(ring_name, STR_MAXLEN, "Rx mac buf ring %d", i);
  4593. dp_print_ring_stat_from_hal(pdev->soc,
  4594. &pdev->rx_mac_buf_ring[i],
  4595. ring_name);
  4596. }
  4597. }
  4598. /**
  4599. * dp_txrx_host_stats_clr(): Reinitialize the txrx stats
  4600. * @vdev: DP_VDEV handle
  4601. *
  4602. * Return:void
  4603. */
  4604. static inline void
  4605. dp_txrx_host_stats_clr(struct dp_vdev *vdev)
  4606. {
  4607. struct dp_peer *peer = NULL;
  4608. struct dp_soc *soc = (struct dp_soc *)vdev->pdev->soc;
  4609. DP_STATS_CLR(vdev->pdev);
  4610. DP_STATS_CLR(vdev->pdev->soc);
  4611. DP_STATS_CLR(vdev);
  4612. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  4613. if (!peer)
  4614. return;
  4615. DP_STATS_CLR(peer);
  4616. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  4617. soc->cdp_soc.ol_ops->update_dp_stats(
  4618. vdev->pdev->osif_pdev,
  4619. &peer->stats,
  4620. peer->peer_ids[0],
  4621. UPDATE_PEER_STATS);
  4622. }
  4623. }
  4624. if (soc->cdp_soc.ol_ops->update_dp_stats)
  4625. soc->cdp_soc.ol_ops->update_dp_stats(vdev->pdev->osif_pdev,
  4626. &vdev->stats, (uint16_t)vdev->vdev_id,
  4627. UPDATE_VDEV_STATS);
  4628. }
  4629. /**
  4630. * dp_print_rx_rates(): Print Rx rate stats
  4631. * @vdev: DP_VDEV handle
  4632. *
  4633. * Return:void
  4634. */
  4635. static inline void
  4636. dp_print_rx_rates(struct dp_vdev *vdev)
  4637. {
  4638. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  4639. uint8_t i, mcs, pkt_type;
  4640. uint8_t index = 0;
  4641. char nss[DP_NSS_LENGTH];
  4642. DP_PRINT_STATS("Rx Rate Info:\n");
  4643. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  4644. index = 0;
  4645. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  4646. if (!dp_rate_string[pkt_type][mcs].valid)
  4647. continue;
  4648. DP_PRINT_STATS(" %s = %d",
  4649. dp_rate_string[pkt_type][mcs].mcs_type,
  4650. pdev->stats.rx.pkt_type[pkt_type].
  4651. mcs_count[mcs]);
  4652. }
  4653. DP_PRINT_STATS("\n");
  4654. }
  4655. index = 0;
  4656. for (i = 0; i < SS_COUNT; i++) {
  4657. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  4658. " %d", pdev->stats.rx.nss[i]);
  4659. }
  4660. DP_PRINT_STATS("NSS(1-8) = %s",
  4661. nss);
  4662. DP_PRINT_STATS("SGI ="
  4663. " 0.8us %d,"
  4664. " 0.4us %d,"
  4665. " 1.6us %d,"
  4666. " 3.2us %d,",
  4667. pdev->stats.rx.sgi_count[0],
  4668. pdev->stats.rx.sgi_count[1],
  4669. pdev->stats.rx.sgi_count[2],
  4670. pdev->stats.rx.sgi_count[3]);
  4671. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  4672. pdev->stats.rx.bw[0], pdev->stats.rx.bw[1],
  4673. pdev->stats.rx.bw[2], pdev->stats.rx.bw[3]);
  4674. DP_PRINT_STATS("Reception Type ="
  4675. " SU: %d,"
  4676. " MU_MIMO:%d,"
  4677. " MU_OFDMA:%d,"
  4678. " MU_OFDMA_MIMO:%d\n",
  4679. pdev->stats.rx.reception_type[0],
  4680. pdev->stats.rx.reception_type[1],
  4681. pdev->stats.rx.reception_type[2],
  4682. pdev->stats.rx.reception_type[3]);
  4683. DP_PRINT_STATS("Aggregation:\n");
  4684. DP_PRINT_STATS("Number of Msdu's Part of Ampdus = %d",
  4685. pdev->stats.rx.ampdu_cnt);
  4686. DP_PRINT_STATS("Number of Msdu's With No Mpdu Level Aggregation : %d",
  4687. pdev->stats.rx.non_ampdu_cnt);
  4688. DP_PRINT_STATS("Number of Msdu's Part of Amsdu: %d",
  4689. pdev->stats.rx.amsdu_cnt);
  4690. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation: %d",
  4691. pdev->stats.rx.non_amsdu_cnt);
  4692. }
  4693. /**
  4694. * dp_print_tx_rates(): Print tx rates
  4695. * @vdev: DP_VDEV handle
  4696. *
  4697. * Return:void
  4698. */
  4699. static inline void
  4700. dp_print_tx_rates(struct dp_vdev *vdev)
  4701. {
  4702. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  4703. uint8_t mcs, pkt_type;
  4704. uint32_t index;
  4705. DP_PRINT_STATS("Tx Rate Info:\n");
  4706. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  4707. index = 0;
  4708. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  4709. if (!dp_rate_string[pkt_type][mcs].valid)
  4710. continue;
  4711. DP_PRINT_STATS(" %s = %d",
  4712. dp_rate_string[pkt_type][mcs].mcs_type,
  4713. pdev->stats.tx.pkt_type[pkt_type].
  4714. mcs_count[mcs]);
  4715. }
  4716. DP_PRINT_STATS("\n");
  4717. }
  4718. DP_PRINT_STATS("SGI ="
  4719. " 0.8us %d"
  4720. " 0.4us %d"
  4721. " 1.6us %d"
  4722. " 3.2us %d",
  4723. pdev->stats.tx.sgi_count[0],
  4724. pdev->stats.tx.sgi_count[1],
  4725. pdev->stats.tx.sgi_count[2],
  4726. pdev->stats.tx.sgi_count[3]);
  4727. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  4728. pdev->stats.tx.bw[0], pdev->stats.tx.bw[1],
  4729. pdev->stats.tx.bw[2], pdev->stats.tx.bw[3]);
  4730. DP_PRINT_STATS("OFDMA = %d", pdev->stats.tx.ofdma);
  4731. DP_PRINT_STATS("STBC = %d", pdev->stats.tx.stbc);
  4732. DP_PRINT_STATS("LDPC = %d", pdev->stats.tx.ldpc);
  4733. DP_PRINT_STATS("Retries = %d", pdev->stats.tx.retries);
  4734. DP_PRINT_STATS("Last ack rssi = %d\n", pdev->stats.tx.last_ack_rssi);
  4735. DP_PRINT_STATS("Aggregation:\n");
  4736. DP_PRINT_STATS("Number of Msdu's Part of Amsdu = %d",
  4737. pdev->stats.tx.amsdu_cnt);
  4738. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation = %d",
  4739. pdev->stats.tx.non_amsdu_cnt);
  4740. }
  4741. /**
  4742. * dp_print_peer_stats():print peer stats
  4743. * @peer: DP_PEER handle
  4744. *
  4745. * return void
  4746. */
  4747. static inline void dp_print_peer_stats(struct dp_peer *peer)
  4748. {
  4749. uint8_t i, mcs, pkt_type;
  4750. uint32_t index;
  4751. char nss[DP_NSS_LENGTH];
  4752. DP_PRINT_STATS("Node Tx Stats:\n");
  4753. DP_PRINT_STATS("Total Packet Completions = %d",
  4754. peer->stats.tx.comp_pkt.num);
  4755. DP_PRINT_STATS("Total Bytes Completions = %llu",
  4756. peer->stats.tx.comp_pkt.bytes);
  4757. DP_PRINT_STATS("Success Packets = %d",
  4758. peer->stats.tx.tx_success.num);
  4759. DP_PRINT_STATS("Success Bytes = %llu",
  4760. peer->stats.tx.tx_success.bytes);
  4761. DP_PRINT_STATS("Unicast Success Packets = %d",
  4762. peer->stats.tx.ucast.num);
  4763. DP_PRINT_STATS("Unicast Success Bytes = %llu",
  4764. peer->stats.tx.ucast.bytes);
  4765. DP_PRINT_STATS("Multicast Success Packets = %d",
  4766. peer->stats.tx.mcast.num);
  4767. DP_PRINT_STATS("Multicast Success Bytes = %llu",
  4768. peer->stats.tx.mcast.bytes);
  4769. DP_PRINT_STATS("Broadcast Success Packets = %d",
  4770. peer->stats.tx.bcast.num);
  4771. DP_PRINT_STATS("Broadcast Success Bytes = %llu",
  4772. peer->stats.tx.bcast.bytes);
  4773. DP_PRINT_STATS("Packets Failed = %d",
  4774. peer->stats.tx.tx_failed);
  4775. DP_PRINT_STATS("Packets In OFDMA = %d",
  4776. peer->stats.tx.ofdma);
  4777. DP_PRINT_STATS("Packets In STBC = %d",
  4778. peer->stats.tx.stbc);
  4779. DP_PRINT_STATS("Packets In LDPC = %d",
  4780. peer->stats.tx.ldpc);
  4781. DP_PRINT_STATS("Packet Retries = %d",
  4782. peer->stats.tx.retries);
  4783. DP_PRINT_STATS("MSDU's Part of AMSDU = %d",
  4784. peer->stats.tx.amsdu_cnt);
  4785. DP_PRINT_STATS("Last Packet RSSI = %d",
  4786. peer->stats.tx.last_ack_rssi);
  4787. DP_PRINT_STATS("Dropped At FW: Removed = %d",
  4788. peer->stats.tx.dropped.fw_rem);
  4789. DP_PRINT_STATS("Dropped At FW: Removed transmitted = %d",
  4790. peer->stats.tx.dropped.fw_rem_tx);
  4791. DP_PRINT_STATS("Dropped At FW: Removed Untransmitted = %d",
  4792. peer->stats.tx.dropped.fw_rem_notx);
  4793. DP_PRINT_STATS("Dropped : Age Out = %d",
  4794. peer->stats.tx.dropped.age_out);
  4795. DP_PRINT_STATS("NAWDS : ");
  4796. DP_PRINT_STATS(" Nawds multicast Drop Tx Packet = %d",
  4797. peer->stats.tx.nawds_mcast_drop);
  4798. DP_PRINT_STATS(" Nawds multicast Tx Packet Count = %d",
  4799. peer->stats.tx.nawds_mcast.num);
  4800. DP_PRINT_STATS(" Nawds multicast Tx Packet Bytes = %llu",
  4801. peer->stats.tx.nawds_mcast.bytes);
  4802. DP_PRINT_STATS("Rate Info:");
  4803. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  4804. index = 0;
  4805. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  4806. if (!dp_rate_string[pkt_type][mcs].valid)
  4807. continue;
  4808. DP_PRINT_STATS(" %s = %d",
  4809. dp_rate_string[pkt_type][mcs].mcs_type,
  4810. peer->stats.tx.pkt_type[pkt_type].
  4811. mcs_count[mcs]);
  4812. }
  4813. DP_PRINT_STATS("\n");
  4814. }
  4815. DP_PRINT_STATS("SGI = "
  4816. " 0.8us %d"
  4817. " 0.4us %d"
  4818. " 1.6us %d"
  4819. " 3.2us %d",
  4820. peer->stats.tx.sgi_count[0],
  4821. peer->stats.tx.sgi_count[1],
  4822. peer->stats.tx.sgi_count[2],
  4823. peer->stats.tx.sgi_count[3]);
  4824. DP_PRINT_STATS("Excess Retries per AC ");
  4825. DP_PRINT_STATS(" Best effort = %d",
  4826. peer->stats.tx.excess_retries_per_ac[0]);
  4827. DP_PRINT_STATS(" Background= %d",
  4828. peer->stats.tx.excess_retries_per_ac[1]);
  4829. DP_PRINT_STATS(" Video = %d",
  4830. peer->stats.tx.excess_retries_per_ac[2]);
  4831. DP_PRINT_STATS(" Voice = %d",
  4832. peer->stats.tx.excess_retries_per_ac[3]);
  4833. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d\n",
  4834. peer->stats.tx.bw[2], peer->stats.tx.bw[3],
  4835. peer->stats.tx.bw[4], peer->stats.tx.bw[5]);
  4836. index = 0;
  4837. for (i = 0; i < SS_COUNT; i++) {
  4838. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  4839. " %d", peer->stats.tx.nss[i]);
  4840. }
  4841. DP_PRINT_STATS("NSS(1-8) = %s",
  4842. nss);
  4843. DP_PRINT_STATS("Aggregation:");
  4844. DP_PRINT_STATS(" Number of Msdu's Part of Amsdu = %d",
  4845. peer->stats.tx.amsdu_cnt);
  4846. DP_PRINT_STATS(" Number of Msdu's With No Msdu Level Aggregation = %d\n",
  4847. peer->stats.tx.non_amsdu_cnt);
  4848. DP_PRINT_STATS("Node Rx Stats:");
  4849. DP_PRINT_STATS("Packets Sent To Stack = %d",
  4850. peer->stats.rx.to_stack.num);
  4851. DP_PRINT_STATS("Bytes Sent To Stack = %llu",
  4852. peer->stats.rx.to_stack.bytes);
  4853. for (i = 0; i < CDP_MAX_RX_RINGS; i++) {
  4854. DP_PRINT_STATS("Ring Id = %d", i);
  4855. DP_PRINT_STATS(" Packets Received = %d",
  4856. peer->stats.rx.rcvd_reo[i].num);
  4857. DP_PRINT_STATS(" Bytes Received = %llu",
  4858. peer->stats.rx.rcvd_reo[i].bytes);
  4859. }
  4860. DP_PRINT_STATS("Multicast Packets Received = %d",
  4861. peer->stats.rx.multicast.num);
  4862. DP_PRINT_STATS("Multicast Bytes Received = %llu",
  4863. peer->stats.rx.multicast.bytes);
  4864. DP_PRINT_STATS("Broadcast Packets Received = %d",
  4865. peer->stats.rx.bcast.num);
  4866. DP_PRINT_STATS("Broadcast Bytes Received = %llu",
  4867. peer->stats.rx.bcast.bytes);
  4868. DP_PRINT_STATS("Intra BSS Packets Received = %d",
  4869. peer->stats.rx.intra_bss.pkts.num);
  4870. DP_PRINT_STATS("Intra BSS Bytes Received = %llu",
  4871. peer->stats.rx.intra_bss.pkts.bytes);
  4872. DP_PRINT_STATS("Raw Packets Received = %d",
  4873. peer->stats.rx.raw.num);
  4874. DP_PRINT_STATS("Raw Bytes Received = %llu",
  4875. peer->stats.rx.raw.bytes);
  4876. DP_PRINT_STATS("Errors: MIC Errors = %d",
  4877. peer->stats.rx.err.mic_err);
  4878. DP_PRINT_STATS("Erros: Decryption Errors = %d",
  4879. peer->stats.rx.err.decrypt_err);
  4880. DP_PRINT_STATS("Msdu's Received As Part of Ampdu = %d",
  4881. peer->stats.rx.non_ampdu_cnt);
  4882. DP_PRINT_STATS("Msdu's Recived As Ampdu = %d",
  4883. peer->stats.rx.ampdu_cnt);
  4884. DP_PRINT_STATS("Msdu's Received Not Part of Amsdu's = %d",
  4885. peer->stats.rx.non_amsdu_cnt);
  4886. DP_PRINT_STATS("MSDUs Received As Part of Amsdu = %d",
  4887. peer->stats.rx.amsdu_cnt);
  4888. DP_PRINT_STATS("NAWDS : ");
  4889. DP_PRINT_STATS(" Nawds multicast Drop Rx Packet = %d",
  4890. peer->stats.rx.nawds_mcast_drop.num);
  4891. DP_PRINT_STATS(" Nawds multicast Drop Rx Packet Bytes = %llu",
  4892. peer->stats.rx.nawds_mcast_drop.bytes);
  4893. DP_PRINT_STATS("SGI ="
  4894. " 0.8us %d"
  4895. " 0.4us %d"
  4896. " 1.6us %d"
  4897. " 3.2us %d",
  4898. peer->stats.rx.sgi_count[0],
  4899. peer->stats.rx.sgi_count[1],
  4900. peer->stats.rx.sgi_count[2],
  4901. peer->stats.rx.sgi_count[3]);
  4902. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d",
  4903. peer->stats.rx.bw[0], peer->stats.rx.bw[1],
  4904. peer->stats.rx.bw[2], peer->stats.rx.bw[3]);
  4905. DP_PRINT_STATS("Reception Type ="
  4906. " SU %d,"
  4907. " MU_MIMO %d,"
  4908. " MU_OFDMA %d,"
  4909. " MU_OFDMA_MIMO %d",
  4910. peer->stats.rx.reception_type[0],
  4911. peer->stats.rx.reception_type[1],
  4912. peer->stats.rx.reception_type[2],
  4913. peer->stats.rx.reception_type[3]);
  4914. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  4915. index = 0;
  4916. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  4917. if (!dp_rate_string[pkt_type][mcs].valid)
  4918. continue;
  4919. DP_PRINT_STATS(" %s = %d",
  4920. dp_rate_string[pkt_type][mcs].mcs_type,
  4921. peer->stats.rx.pkt_type[pkt_type].
  4922. mcs_count[mcs]);
  4923. }
  4924. DP_PRINT_STATS("\n");
  4925. }
  4926. index = 0;
  4927. for (i = 0; i < SS_COUNT; i++) {
  4928. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  4929. " %d", peer->stats.rx.nss[i]);
  4930. }
  4931. DP_PRINT_STATS("NSS(1-8) = %s",
  4932. nss);
  4933. DP_PRINT_STATS("Aggregation:");
  4934. DP_PRINT_STATS(" Msdu's Part of Ampdu = %d",
  4935. peer->stats.rx.ampdu_cnt);
  4936. DP_PRINT_STATS(" Msdu's With No Mpdu Level Aggregation = %d",
  4937. peer->stats.rx.non_ampdu_cnt);
  4938. DP_PRINT_STATS(" Msdu's Part of Amsdu = %d",
  4939. peer->stats.rx.amsdu_cnt);
  4940. DP_PRINT_STATS(" Msdu's With No Msdu Level Aggregation = %d",
  4941. peer->stats.rx.non_amsdu_cnt);
  4942. }
  4943. /**
  4944. * dp_print_host_stats()- Function to print the stats aggregated at host
  4945. * @vdev_handle: DP_VDEV handle
  4946. * @type: host stats type
  4947. *
  4948. * Available Stat types
  4949. * TXRX_CLEAR_STATS : Clear the stats
  4950. * TXRX_RX_RATE_STATS: Print Rx Rate Info
  4951. * TXRX_TX_RATE_STATS: Print Tx Rate Info
  4952. * TXRX_TX_HOST_STATS: Print Tx Stats
  4953. * TXRX_RX_HOST_STATS: Print Rx Stats
  4954. * TXRX_AST_STATS: Print AST Stats
  4955. * TXRX_SRNG_PTR_STATS: Print SRNG ring pointer stats
  4956. *
  4957. * Return: 0 on success, print error message in case of failure
  4958. */
  4959. static int
  4960. dp_print_host_stats(struct cdp_vdev *vdev_handle, enum cdp_host_txrx_stats type)
  4961. {
  4962. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4963. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  4964. dp_aggregate_pdev_stats(pdev);
  4965. switch (type) {
  4966. case TXRX_CLEAR_STATS:
  4967. dp_txrx_host_stats_clr(vdev);
  4968. break;
  4969. case TXRX_RX_RATE_STATS:
  4970. dp_print_rx_rates(vdev);
  4971. break;
  4972. case TXRX_TX_RATE_STATS:
  4973. dp_print_tx_rates(vdev);
  4974. break;
  4975. case TXRX_TX_HOST_STATS:
  4976. dp_print_pdev_tx_stats(pdev);
  4977. dp_print_soc_tx_stats(pdev->soc);
  4978. break;
  4979. case TXRX_RX_HOST_STATS:
  4980. dp_print_pdev_rx_stats(pdev);
  4981. dp_print_soc_rx_stats(pdev->soc);
  4982. break;
  4983. case TXRX_AST_STATS:
  4984. dp_print_ast_stats(pdev->soc);
  4985. dp_print_peer_table(vdev);
  4986. break;
  4987. case TXRX_SRNG_PTR_STATS:
  4988. dp_print_ring_stats(pdev);
  4989. break;
  4990. default:
  4991. DP_TRACE(FATAL, "Wrong Input For TxRx Host Stats");
  4992. break;
  4993. }
  4994. return 0;
  4995. }
  4996. /*
  4997. * dp_get_host_peer_stats()- function to print peer stats
  4998. * @pdev_handle: DP_PDEV handle
  4999. * @mac_addr: mac address of the peer
  5000. *
  5001. * Return: void
  5002. */
  5003. static void
  5004. dp_get_host_peer_stats(struct cdp_pdev *pdev_handle, char *mac_addr)
  5005. {
  5006. struct dp_peer *peer;
  5007. uint8_t local_id;
  5008. peer = (struct dp_peer *)dp_find_peer_by_addr(pdev_handle, mac_addr,
  5009. &local_id);
  5010. if (!peer) {
  5011. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  5012. "%s: Invalid peer\n", __func__);
  5013. return;
  5014. }
  5015. dp_print_peer_stats(peer);
  5016. dp_peer_rxtid_stats(peer, dp_rx_tid_stats_cb, NULL);
  5017. return;
  5018. }
  5019. /*
  5020. * dp_ppdu_ring_reset()- Reset PPDU Stats ring
  5021. * @pdev: DP_PDEV handle
  5022. *
  5023. * Return: void
  5024. */
  5025. static void
  5026. dp_ppdu_ring_reset(struct dp_pdev *pdev)
  5027. {
  5028. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  5029. int mac_id;
  5030. qdf_mem_set(&(htt_tlv_filter), sizeof(htt_tlv_filter), 0x0);
  5031. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  5032. int mac_for_pdev = dp_get_mac_id_for_pdev(mac_id,
  5033. pdev->pdev_id);
  5034. htt_h2t_rx_ring_cfg(pdev->soc->htt_handle, mac_for_pdev,
  5035. pdev->rxdma_mon_status_ring[mac_id].hal_srng,
  5036. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE, &htt_tlv_filter);
  5037. }
  5038. }
  5039. /*
  5040. * dp_ppdu_ring_cfg()- Configure PPDU Stats ring
  5041. * @pdev: DP_PDEV handle
  5042. *
  5043. * Return: void
  5044. */
  5045. static void
  5046. dp_ppdu_ring_cfg(struct dp_pdev *pdev)
  5047. {
  5048. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  5049. int mac_id;
  5050. htt_tlv_filter.mpdu_start = 1;
  5051. htt_tlv_filter.msdu_start = 0;
  5052. htt_tlv_filter.packet = 0;
  5053. htt_tlv_filter.msdu_end = 0;
  5054. htt_tlv_filter.mpdu_end = 0;
  5055. htt_tlv_filter.packet_header = 1;
  5056. htt_tlv_filter.attention = 1;
  5057. htt_tlv_filter.ppdu_start = 1;
  5058. htt_tlv_filter.ppdu_end = 1;
  5059. htt_tlv_filter.ppdu_end_user_stats = 1;
  5060. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  5061. htt_tlv_filter.ppdu_end_status_done = 1;
  5062. htt_tlv_filter.enable_fp = 1;
  5063. htt_tlv_filter.enable_md = 0;
  5064. if (pdev->mcopy_mode)
  5065. htt_tlv_filter.enable_mo = 1;
  5066. htt_tlv_filter.fp_mgmt_filter = FILTER_MGMT_ALL;
  5067. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_ALL;
  5068. htt_tlv_filter.fp_data_filter = FILTER_DATA_ALL;
  5069. htt_tlv_filter.mo_mgmt_filter = FILTER_MGMT_ALL;
  5070. htt_tlv_filter.mo_ctrl_filter = FILTER_CTRL_ALL;
  5071. htt_tlv_filter.mo_data_filter = FILTER_DATA_ALL;
  5072. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  5073. int mac_for_pdev = dp_get_mac_id_for_pdev(mac_id,
  5074. pdev->pdev_id);
  5075. htt_h2t_rx_ring_cfg(pdev->soc->htt_handle, mac_for_pdev,
  5076. pdev->rxdma_mon_status_ring[mac_id].hal_srng,
  5077. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE, &htt_tlv_filter);
  5078. }
  5079. }
  5080. /*
  5081. * dp_config_debug_sniffer()- API to enable/disable debug sniffer
  5082. * @pdev_handle: DP_PDEV handle
  5083. * @val: user provided value
  5084. *
  5085. * Return: void
  5086. */
  5087. static void
  5088. dp_config_debug_sniffer(struct cdp_pdev *pdev_handle, int val)
  5089. {
  5090. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  5091. switch (val) {
  5092. case 0:
  5093. pdev->tx_sniffer_enable = 0;
  5094. pdev->mcopy_mode = 0;
  5095. if (!pdev->pktlog_ppdu_stats && !pdev->enhanced_stats_en) {
  5096. dp_h2t_cfg_stats_msg_send(pdev, 0, pdev->pdev_id);
  5097. dp_ppdu_ring_reset(pdev);
  5098. } else if (pdev->enhanced_stats_en) {
  5099. dp_h2t_cfg_stats_msg_send(pdev,
  5100. DP_PPDU_STATS_CFG_ENH_STATS, pdev->pdev_id);
  5101. }
  5102. break;
  5103. case 1:
  5104. pdev->tx_sniffer_enable = 1;
  5105. pdev->mcopy_mode = 0;
  5106. if (!pdev->pktlog_ppdu_stats)
  5107. dp_h2t_cfg_stats_msg_send(pdev,
  5108. DP_PPDU_STATS_CFG_SNIFFER, pdev->pdev_id);
  5109. break;
  5110. case 2:
  5111. pdev->mcopy_mode = 1;
  5112. pdev->tx_sniffer_enable = 0;
  5113. if (!pdev->enhanced_stats_en)
  5114. dp_ppdu_ring_cfg(pdev);
  5115. if (!pdev->pktlog_ppdu_stats)
  5116. dp_h2t_cfg_stats_msg_send(pdev,
  5117. DP_PPDU_STATS_CFG_SNIFFER, pdev->pdev_id);
  5118. break;
  5119. default:
  5120. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5121. "Invalid value\n");
  5122. break;
  5123. }
  5124. }
  5125. /*
  5126. * dp_enable_enhanced_stats()- API to enable enhanced statistcs
  5127. * @pdev_handle: DP_PDEV handle
  5128. *
  5129. * Return: void
  5130. */
  5131. static void
  5132. dp_enable_enhanced_stats(struct cdp_pdev *pdev_handle)
  5133. {
  5134. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  5135. pdev->enhanced_stats_en = 1;
  5136. if (!pdev->mcopy_mode)
  5137. dp_ppdu_ring_cfg(pdev);
  5138. if (!pdev->pktlog_ppdu_stats && !pdev->tx_sniffer_enable && !pdev->mcopy_mode)
  5139. dp_h2t_cfg_stats_msg_send(pdev, DP_PPDU_STATS_CFG_ENH_STATS, pdev->pdev_id);
  5140. }
  5141. /*
  5142. * dp_disable_enhanced_stats()- API to disable enhanced statistcs
  5143. * @pdev_handle: DP_PDEV handle
  5144. *
  5145. * Return: void
  5146. */
  5147. static void
  5148. dp_disable_enhanced_stats(struct cdp_pdev *pdev_handle)
  5149. {
  5150. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  5151. pdev->enhanced_stats_en = 0;
  5152. if (!pdev->pktlog_ppdu_stats && !pdev->tx_sniffer_enable && !pdev->mcopy_mode)
  5153. dp_h2t_cfg_stats_msg_send(pdev, 0, pdev->pdev_id);
  5154. if (!pdev->mcopy_mode)
  5155. dp_ppdu_ring_reset(pdev);
  5156. }
  5157. /*
  5158. * dp_get_fw_peer_stats()- function to print peer stats
  5159. * @pdev_handle: DP_PDEV handle
  5160. * @mac_addr: mac address of the peer
  5161. * @cap: Type of htt stats requested
  5162. *
  5163. * Currently Supporting only MAC ID based requests Only
  5164. * 1: HTT_PEER_STATS_REQ_MODE_NO_QUERY
  5165. * 2: HTT_PEER_STATS_REQ_MODE_QUERY_TQM
  5166. * 3: HTT_PEER_STATS_REQ_MODE_FLUSH_TQM
  5167. *
  5168. * Return: void
  5169. */
  5170. static void
  5171. dp_get_fw_peer_stats(struct cdp_pdev *pdev_handle, uint8_t *mac_addr,
  5172. uint32_t cap)
  5173. {
  5174. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  5175. int i;
  5176. uint32_t config_param0 = 0;
  5177. uint32_t config_param1 = 0;
  5178. uint32_t config_param2 = 0;
  5179. uint32_t config_param3 = 0;
  5180. HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(config_param0, 1);
  5181. config_param0 |= (1 << (cap + 1));
  5182. for (i = 0; i < HTT_PEER_STATS_MAX_TLV; i++) {
  5183. config_param1 |= (1 << i);
  5184. }
  5185. config_param2 |= (mac_addr[0] & 0x000000ff);
  5186. config_param2 |= ((mac_addr[1] << 8) & 0x0000ff00);
  5187. config_param2 |= ((mac_addr[2] << 16) & 0x00ff0000);
  5188. config_param2 |= ((mac_addr[3] << 24) & 0xff000000);
  5189. config_param3 |= (mac_addr[4] & 0x000000ff);
  5190. config_param3 |= ((mac_addr[5] << 8) & 0x0000ff00);
  5191. dp_h2t_ext_stats_msg_send(pdev, HTT_DBG_EXT_STATS_PEER_INFO,
  5192. config_param0, config_param1, config_param2,
  5193. config_param3, 0, 0, 0);
  5194. }
  5195. /* This struct definition will be removed from here
  5196. * once it get added in FW headers*/
  5197. struct httstats_cmd_req {
  5198. uint32_t config_param0;
  5199. uint32_t config_param1;
  5200. uint32_t config_param2;
  5201. uint32_t config_param3;
  5202. int cookie;
  5203. u_int8_t stats_id;
  5204. };
  5205. /*
  5206. * dp_get_htt_stats: function to process the httstas request
  5207. * @pdev_handle: DP pdev handle
  5208. * @data: pointer to request data
  5209. * @data_len: length for request data
  5210. *
  5211. * return: void
  5212. */
  5213. static void
  5214. dp_get_htt_stats(struct cdp_pdev *pdev_handle, void *data, uint32_t data_len)
  5215. {
  5216. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  5217. struct httstats_cmd_req *req = (struct httstats_cmd_req *)data;
  5218. QDF_ASSERT(data_len == sizeof(struct httstats_cmd_req));
  5219. dp_h2t_ext_stats_msg_send(pdev, req->stats_id,
  5220. req->config_param0, req->config_param1,
  5221. req->config_param2, req->config_param3,
  5222. req->cookie, 0, 0);
  5223. }
  5224. /*
  5225. * dp_set_pdev_param: function to set parameters in pdev
  5226. * @pdev_handle: DP pdev handle
  5227. * @param: parameter type to be set
  5228. * @val: value of parameter to be set
  5229. *
  5230. * return: void
  5231. */
  5232. static void dp_set_pdev_param(struct cdp_pdev *pdev_handle,
  5233. enum cdp_pdev_param_type param, uint8_t val)
  5234. {
  5235. switch (param) {
  5236. case CDP_CONFIG_DEBUG_SNIFFER:
  5237. dp_config_debug_sniffer(pdev_handle, val);
  5238. break;
  5239. default:
  5240. break;
  5241. }
  5242. }
  5243. /*
  5244. * dp_set_vdev_param: function to set parameters in vdev
  5245. * @param: parameter type to be set
  5246. * @val: value of parameter to be set
  5247. *
  5248. * return: void
  5249. */
  5250. static void dp_set_vdev_param(struct cdp_vdev *vdev_handle,
  5251. enum cdp_vdev_param_type param, uint32_t val)
  5252. {
  5253. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  5254. switch (param) {
  5255. case CDP_ENABLE_WDS:
  5256. vdev->wds_enabled = val;
  5257. break;
  5258. case CDP_ENABLE_NAWDS:
  5259. vdev->nawds_enabled = val;
  5260. break;
  5261. case CDP_ENABLE_MCAST_EN:
  5262. vdev->mcast_enhancement_en = val;
  5263. break;
  5264. case CDP_ENABLE_PROXYSTA:
  5265. vdev->proxysta_vdev = val;
  5266. break;
  5267. case CDP_UPDATE_TDLS_FLAGS:
  5268. vdev->tdls_link_connected = val;
  5269. break;
  5270. case CDP_CFG_WDS_AGING_TIMER:
  5271. if (val == 0)
  5272. qdf_timer_stop(&vdev->pdev->soc->wds_aging_timer);
  5273. else if (val != vdev->wds_aging_timer_val)
  5274. qdf_timer_mod(&vdev->pdev->soc->wds_aging_timer, val);
  5275. vdev->wds_aging_timer_val = val;
  5276. break;
  5277. case CDP_ENABLE_AP_BRIDGE:
  5278. if (wlan_op_mode_sta != vdev->opmode)
  5279. vdev->ap_bridge_enabled = val;
  5280. else
  5281. vdev->ap_bridge_enabled = false;
  5282. break;
  5283. case CDP_ENABLE_CIPHER:
  5284. vdev->sec_type = val;
  5285. break;
  5286. case CDP_ENABLE_QWRAP_ISOLATION:
  5287. vdev->isolation_vdev = val;
  5288. break;
  5289. default:
  5290. break;
  5291. }
  5292. dp_tx_vdev_update_search_flags(vdev);
  5293. }
  5294. /**
  5295. * dp_peer_set_nawds: set nawds bit in peer
  5296. * @peer_handle: pointer to peer
  5297. * @value: enable/disable nawds
  5298. *
  5299. * return: void
  5300. */
  5301. static void dp_peer_set_nawds(struct cdp_peer *peer_handle, uint8_t value)
  5302. {
  5303. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  5304. peer->nawds_enabled = value;
  5305. }
  5306. /*
  5307. * dp_set_vdev_dscp_tid_map_wifi3(): Update Map ID selected for particular vdev
  5308. * @vdev_handle: DP_VDEV handle
  5309. * @map_id:ID of map that needs to be updated
  5310. *
  5311. * Return: void
  5312. */
  5313. static void dp_set_vdev_dscp_tid_map_wifi3(struct cdp_vdev *vdev_handle,
  5314. uint8_t map_id)
  5315. {
  5316. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  5317. vdev->dscp_tid_map_id = map_id;
  5318. return;
  5319. }
  5320. /*
  5321. * dp_txrx_stats_publish(): publish pdev stats into a buffer
  5322. * @pdev_handle: DP_PDEV handle
  5323. * @buf: to hold pdev_stats
  5324. *
  5325. * Return: int
  5326. */
  5327. static int
  5328. dp_txrx_stats_publish(struct cdp_pdev *pdev_handle, void *buf)
  5329. {
  5330. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  5331. struct cdp_pdev_stats *buffer = (struct cdp_pdev_stats *) buf;
  5332. struct cdp_txrx_stats_req req = {0,};
  5333. dp_aggregate_pdev_stats(pdev);
  5334. req.stats = HTT_DBG_EXT_STATS_PDEV_TX;
  5335. req.cookie_val = 1;
  5336. dp_h2t_ext_stats_msg_send(pdev, req.stats, req.param0,
  5337. req.param1, req.param2, req.param3, 0,
  5338. req.cookie_val, 0);
  5339. msleep(DP_MAX_SLEEP_TIME);
  5340. req.stats = HTT_DBG_EXT_STATS_PDEV_RX;
  5341. req.cookie_val = 1;
  5342. dp_h2t_ext_stats_msg_send(pdev, req.stats, req.param0,
  5343. req.param1, req.param2, req.param3, 0,
  5344. req.cookie_val, 0);
  5345. msleep(DP_MAX_SLEEP_TIME);
  5346. qdf_mem_copy(buffer, &pdev->stats, sizeof(pdev->stats));
  5347. return TXRX_STATS_LEVEL;
  5348. }
  5349. /**
  5350. * dp_set_pdev_dscp_tid_map_wifi3(): update dscp tid map in pdev
  5351. * @pdev: DP_PDEV handle
  5352. * @map_id: ID of map that needs to be updated
  5353. * @tos: index value in map
  5354. * @tid: tid value passed by the user
  5355. *
  5356. * Return: void
  5357. */
  5358. static void dp_set_pdev_dscp_tid_map_wifi3(struct cdp_pdev *pdev_handle,
  5359. uint8_t map_id, uint8_t tos, uint8_t tid)
  5360. {
  5361. uint8_t dscp;
  5362. struct dp_pdev *pdev = (struct dp_pdev *) pdev_handle;
  5363. dscp = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  5364. pdev->dscp_tid_map[map_id][dscp] = tid;
  5365. if (map_id < HAL_MAX_HW_DSCP_TID_MAPS)
  5366. hal_tx_update_dscp_tid(pdev->soc->hal_soc, tid,
  5367. map_id, dscp);
  5368. return;
  5369. }
  5370. /**
  5371. * dp_fw_stats_process(): Process TxRX FW stats request
  5372. * @vdev_handle: DP VDEV handle
  5373. * @req: stats request
  5374. *
  5375. * return: int
  5376. */
  5377. static int dp_fw_stats_process(struct cdp_vdev *vdev_handle,
  5378. struct cdp_txrx_stats_req *req)
  5379. {
  5380. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  5381. struct dp_pdev *pdev = NULL;
  5382. uint32_t stats = req->stats;
  5383. uint8_t channel = req->channel;
  5384. if (!vdev) {
  5385. DP_TRACE(NONE, "VDEV not found");
  5386. return 1;
  5387. }
  5388. pdev = vdev->pdev;
  5389. /*
  5390. * For HTT_DBG_EXT_STATS_RESET command, FW need to config
  5391. * from param0 to param3 according to below rule:
  5392. *
  5393. * PARAM:
  5394. * - config_param0 : start_offset (stats type)
  5395. * - config_param1 : stats bmask from start offset
  5396. * - config_param2 : stats bmask from start offset + 32
  5397. * - config_param3 : stats bmask from start offset + 64
  5398. */
  5399. if (req->stats == CDP_TXRX_STATS_0) {
  5400. req->param0 = HTT_DBG_EXT_STATS_PDEV_TX;
  5401. req->param1 = 0xFFFFFFFF;
  5402. req->param2 = 0xFFFFFFFF;
  5403. req->param3 = 0xFFFFFFFF;
  5404. }
  5405. return dp_h2t_ext_stats_msg_send(pdev, stats, req->param0,
  5406. req->param1, req->param2, req->param3,
  5407. 0, 0, channel);
  5408. }
  5409. /**
  5410. * dp_txrx_stats_request - function to map to firmware and host stats
  5411. * @vdev: virtual handle
  5412. * @req: stats request
  5413. *
  5414. * Return: integer
  5415. */
  5416. static int dp_txrx_stats_request(struct cdp_vdev *vdev,
  5417. struct cdp_txrx_stats_req *req)
  5418. {
  5419. int host_stats;
  5420. int fw_stats;
  5421. enum cdp_stats stats;
  5422. if (!vdev || !req) {
  5423. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5424. "Invalid vdev/req instance");
  5425. return 0;
  5426. }
  5427. stats = req->stats;
  5428. if (stats >= CDP_TXRX_MAX_STATS)
  5429. return 0;
  5430. /*
  5431. * DP_CURR_FW_STATS_AVAIL: no of FW stats currently available
  5432. * has to be updated if new FW HTT stats added
  5433. */
  5434. if (stats > CDP_TXRX_STATS_HTT_MAX)
  5435. stats = stats + DP_CURR_FW_STATS_AVAIL - DP_HTT_DBG_EXT_STATS_MAX;
  5436. fw_stats = dp_stats_mapping_table[stats][STATS_FW];
  5437. host_stats = dp_stats_mapping_table[stats][STATS_HOST];
  5438. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5439. "stats: %u fw_stats_type: %d host_stats_type: %d",
  5440. stats, fw_stats, host_stats);
  5441. if (fw_stats != TXRX_FW_STATS_INVALID) {
  5442. /* update request with FW stats type */
  5443. req->stats = fw_stats;
  5444. return dp_fw_stats_process(vdev, req);
  5445. }
  5446. if ((host_stats != TXRX_HOST_STATS_INVALID) &&
  5447. (host_stats <= TXRX_HOST_STATS_MAX))
  5448. return dp_print_host_stats(vdev, host_stats);
  5449. else
  5450. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5451. "Wrong Input for TxRx Stats");
  5452. return 0;
  5453. }
  5454. /*
  5455. * dp_print_napi_stats(): NAPI stats
  5456. * @soc - soc handle
  5457. */
  5458. static void dp_print_napi_stats(struct dp_soc *soc)
  5459. {
  5460. hif_print_napi_stats(soc->hif_handle);
  5461. }
  5462. /*
  5463. * dp_print_per_ring_stats(): Packet count per ring
  5464. * @soc - soc handle
  5465. */
  5466. static void dp_print_per_ring_stats(struct dp_soc *soc)
  5467. {
  5468. uint8_t ring;
  5469. uint16_t core;
  5470. uint64_t total_packets;
  5471. DP_TRACE(FATAL, "Reo packets per ring:");
  5472. for (ring = 0; ring < MAX_REO_DEST_RINGS; ring++) {
  5473. total_packets = 0;
  5474. DP_TRACE(FATAL, "Packets on ring %u:", ring);
  5475. for (core = 0; core < NR_CPUS; core++) {
  5476. DP_TRACE(FATAL, "Packets arriving on core %u: %llu",
  5477. core, soc->stats.rx.ring_packets[core][ring]);
  5478. total_packets += soc->stats.rx.ring_packets[core][ring];
  5479. }
  5480. DP_TRACE(FATAL, "Total packets on ring %u: %llu",
  5481. ring, total_packets);
  5482. }
  5483. }
  5484. /*
  5485. * dp_txrx_path_stats() - Function to display dump stats
  5486. * @soc - soc handle
  5487. *
  5488. * return: none
  5489. */
  5490. static void dp_txrx_path_stats(struct dp_soc *soc)
  5491. {
  5492. uint8_t error_code;
  5493. uint8_t loop_pdev;
  5494. struct dp_pdev *pdev;
  5495. uint8_t i;
  5496. for (loop_pdev = 0; loop_pdev < soc->pdev_count; loop_pdev++) {
  5497. pdev = soc->pdev_list[loop_pdev];
  5498. dp_aggregate_pdev_stats(pdev);
  5499. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5500. "Tx path Statistics:");
  5501. DP_TRACE(FATAL, "from stack: %u msdus (%llu bytes)",
  5502. pdev->stats.tx_i.rcvd.num,
  5503. pdev->stats.tx_i.rcvd.bytes);
  5504. DP_TRACE(FATAL, "processed from host: %u msdus (%llu bytes)",
  5505. pdev->stats.tx_i.processed.num,
  5506. pdev->stats.tx_i.processed.bytes);
  5507. DP_TRACE(FATAL, "successfully transmitted: %u msdus (%llu bytes)",
  5508. pdev->stats.tx.tx_success.num,
  5509. pdev->stats.tx.tx_success.bytes);
  5510. DP_TRACE(FATAL, "Dropped in host:");
  5511. DP_TRACE(FATAL, "Total packets dropped: %u,",
  5512. pdev->stats.tx_i.dropped.dropped_pkt.num);
  5513. DP_TRACE(FATAL, "Descriptor not available: %u",
  5514. pdev->stats.tx_i.dropped.desc_na);
  5515. DP_TRACE(FATAL, "Ring full: %u",
  5516. pdev->stats.tx_i.dropped.ring_full);
  5517. DP_TRACE(FATAL, "Enqueue fail: %u",
  5518. pdev->stats.tx_i.dropped.enqueue_fail);
  5519. DP_TRACE(FATAL, "DMA Error: %u",
  5520. pdev->stats.tx_i.dropped.dma_error);
  5521. DP_TRACE(FATAL, "Dropped in hardware:");
  5522. DP_TRACE(FATAL, "total packets dropped: %u",
  5523. pdev->stats.tx.tx_failed);
  5524. DP_TRACE(FATAL, "mpdu age out: %u",
  5525. pdev->stats.tx.dropped.age_out);
  5526. DP_TRACE(FATAL, "firmware removed: %u",
  5527. pdev->stats.tx.dropped.fw_rem);
  5528. DP_TRACE(FATAL, "firmware removed tx: %u",
  5529. pdev->stats.tx.dropped.fw_rem_tx);
  5530. DP_TRACE(FATAL, "firmware removed notx %u",
  5531. pdev->stats.tx.dropped.fw_rem_notx);
  5532. DP_TRACE(FATAL, "peer_invalid: %u",
  5533. pdev->soc->stats.tx.tx_invalid_peer.num);
  5534. DP_TRACE(FATAL, "Tx packets sent per interrupt:");
  5535. DP_TRACE(FATAL, "Single Packet: %u",
  5536. pdev->stats.tx_comp_histogram.pkts_1);
  5537. DP_TRACE(FATAL, "2-20 Packets: %u",
  5538. pdev->stats.tx_comp_histogram.pkts_2_20);
  5539. DP_TRACE(FATAL, "21-40 Packets: %u",
  5540. pdev->stats.tx_comp_histogram.pkts_21_40);
  5541. DP_TRACE(FATAL, "41-60 Packets: %u",
  5542. pdev->stats.tx_comp_histogram.pkts_41_60);
  5543. DP_TRACE(FATAL, "61-80 Packets: %u",
  5544. pdev->stats.tx_comp_histogram.pkts_61_80);
  5545. DP_TRACE(FATAL, "81-100 Packets: %u",
  5546. pdev->stats.tx_comp_histogram.pkts_81_100);
  5547. DP_TRACE(FATAL, "101-200 Packets: %u",
  5548. pdev->stats.tx_comp_histogram.pkts_101_200);
  5549. DP_TRACE(FATAL, " 201+ Packets: %u",
  5550. pdev->stats.tx_comp_histogram.pkts_201_plus);
  5551. DP_TRACE(FATAL, "Rx path statistics");
  5552. DP_TRACE(FATAL, "delivered %u msdus ( %llu bytes),",
  5553. pdev->stats.rx.to_stack.num,
  5554. pdev->stats.rx.to_stack.bytes);
  5555. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  5556. DP_TRACE(FATAL, "received on reo[%d] %u msdus ( %llu bytes),",
  5557. i, pdev->stats.rx.rcvd_reo[i].num,
  5558. pdev->stats.rx.rcvd_reo[i].bytes);
  5559. DP_TRACE(FATAL, "intra-bss packets %u msdus ( %llu bytes),",
  5560. pdev->stats.rx.intra_bss.pkts.num,
  5561. pdev->stats.rx.intra_bss.pkts.bytes);
  5562. DP_TRACE(FATAL, "intra-bss fails %u msdus ( %llu bytes),",
  5563. pdev->stats.rx.intra_bss.fail.num,
  5564. pdev->stats.rx.intra_bss.fail.bytes);
  5565. DP_TRACE(FATAL, "raw packets %u msdus ( %llu bytes),",
  5566. pdev->stats.rx.raw.num,
  5567. pdev->stats.rx.raw.bytes);
  5568. DP_TRACE(FATAL, "dropped: error %u msdus",
  5569. pdev->stats.rx.err.mic_err);
  5570. DP_TRACE(FATAL, "peer invalid %u",
  5571. pdev->soc->stats.rx.err.rx_invalid_peer.num);
  5572. DP_TRACE(FATAL, "Reo Statistics");
  5573. DP_TRACE(FATAL, "rbm error: %u msdus",
  5574. pdev->soc->stats.rx.err.invalid_rbm);
  5575. DP_TRACE(FATAL, "hal ring access fail: %u msdus",
  5576. pdev->soc->stats.rx.err.hal_ring_access_fail);
  5577. DP_TRACE(FATAL, "Reo errors");
  5578. for (error_code = 0; error_code < HAL_REO_ERR_MAX;
  5579. error_code++) {
  5580. DP_TRACE(FATAL, "Reo error number (%u): %u msdus",
  5581. error_code,
  5582. pdev->soc->stats.rx.err.reo_error[error_code]);
  5583. }
  5584. for (error_code = 0; error_code < HAL_RXDMA_ERR_MAX;
  5585. error_code++) {
  5586. DP_TRACE(FATAL, "Rxdma error number (%u): %u msdus",
  5587. error_code,
  5588. pdev->soc->stats.rx.err
  5589. .rxdma_error[error_code]);
  5590. }
  5591. DP_TRACE(FATAL, "Rx packets reaped per interrupt:");
  5592. DP_TRACE(FATAL, "Single Packet: %u",
  5593. pdev->stats.rx_ind_histogram.pkts_1);
  5594. DP_TRACE(FATAL, "2-20 Packets: %u",
  5595. pdev->stats.rx_ind_histogram.pkts_2_20);
  5596. DP_TRACE(FATAL, "21-40 Packets: %u",
  5597. pdev->stats.rx_ind_histogram.pkts_21_40);
  5598. DP_TRACE(FATAL, "41-60 Packets: %u",
  5599. pdev->stats.rx_ind_histogram.pkts_41_60);
  5600. DP_TRACE(FATAL, "61-80 Packets: %u",
  5601. pdev->stats.rx_ind_histogram.pkts_61_80);
  5602. DP_TRACE(FATAL, "81-100 Packets: %u",
  5603. pdev->stats.rx_ind_histogram.pkts_81_100);
  5604. DP_TRACE(FATAL, "101-200 Packets: %u",
  5605. pdev->stats.rx_ind_histogram.pkts_101_200);
  5606. DP_TRACE(FATAL, " 201+ Packets: %u",
  5607. pdev->stats.rx_ind_histogram.pkts_201_plus);
  5608. DP_TRACE_STATS(ERROR, "%s: tso_enable: %u lro_enable: %u rx_hash: %u napi_enable: %u",
  5609. __func__,
  5610. pdev->soc->wlan_cfg_ctx->tso_enabled,
  5611. pdev->soc->wlan_cfg_ctx->lro_enabled,
  5612. pdev->soc->wlan_cfg_ctx->rx_hash,
  5613. pdev->soc->wlan_cfg_ctx->napi_enabled);
  5614. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5615. DP_TRACE_STATS(ERROR, "%s: Tx flow stop queue: %u tx flow start queue offset: %u",
  5616. __func__,
  5617. pdev->soc->wlan_cfg_ctx->tx_flow_stop_queue_threshold,
  5618. pdev->soc->wlan_cfg_ctx->tx_flow_start_queue_offset);
  5619. #endif
  5620. }
  5621. }
  5622. /*
  5623. * dp_txrx_dump_stats() - Dump statistics
  5624. * @value - Statistics option
  5625. */
  5626. static QDF_STATUS dp_txrx_dump_stats(void *psoc, uint16_t value,
  5627. enum qdf_stats_verbosity_level level)
  5628. {
  5629. struct dp_soc *soc =
  5630. (struct dp_soc *)psoc;
  5631. QDF_STATUS status = QDF_STATUS_SUCCESS;
  5632. if (!soc) {
  5633. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5634. "%s: soc is NULL", __func__);
  5635. return QDF_STATUS_E_INVAL;
  5636. }
  5637. switch (value) {
  5638. case CDP_TXRX_PATH_STATS:
  5639. dp_txrx_path_stats(soc);
  5640. break;
  5641. case CDP_RX_RING_STATS:
  5642. dp_print_per_ring_stats(soc);
  5643. break;
  5644. case CDP_TXRX_TSO_STATS:
  5645. /* TODO: NOT IMPLEMENTED */
  5646. break;
  5647. case CDP_DUMP_TX_FLOW_POOL_INFO:
  5648. cdp_dump_flow_pool_info((struct cdp_soc_t *)soc);
  5649. break;
  5650. case CDP_DP_NAPI_STATS:
  5651. dp_print_napi_stats(soc);
  5652. break;
  5653. case CDP_TXRX_DESC_STATS:
  5654. /* TODO: NOT IMPLEMENTED */
  5655. break;
  5656. default:
  5657. status = QDF_STATUS_E_INVAL;
  5658. break;
  5659. }
  5660. return status;
  5661. }
  5662. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5663. /**
  5664. * dp_update_flow_control_parameters() - API to store datapath
  5665. * config parameters
  5666. * @soc: soc handle
  5667. * @cfg: ini parameter handle
  5668. *
  5669. * Return: void
  5670. */
  5671. static inline
  5672. void dp_update_flow_control_parameters(struct dp_soc *soc,
  5673. struct cdp_config_params *params)
  5674. {
  5675. soc->wlan_cfg_ctx->tx_flow_stop_queue_threshold =
  5676. params->tx_flow_stop_queue_threshold;
  5677. soc->wlan_cfg_ctx->tx_flow_start_queue_offset =
  5678. params->tx_flow_start_queue_offset;
  5679. }
  5680. #else
  5681. static inline
  5682. void dp_update_flow_control_parameters(struct dp_soc *soc,
  5683. struct cdp_config_params *params)
  5684. {
  5685. }
  5686. #endif
  5687. /**
  5688. * dp_update_config_parameters() - API to store datapath
  5689. * config parameters
  5690. * @soc: soc handle
  5691. * @cfg: ini parameter handle
  5692. *
  5693. * Return: status
  5694. */
  5695. static
  5696. QDF_STATUS dp_update_config_parameters(struct cdp_soc *psoc,
  5697. struct cdp_config_params *params)
  5698. {
  5699. struct dp_soc *soc = (struct dp_soc *)psoc;
  5700. if (!(soc)) {
  5701. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5702. "%s: Invalid handle", __func__);
  5703. return QDF_STATUS_E_INVAL;
  5704. }
  5705. soc->wlan_cfg_ctx->tso_enabled = params->tso_enable;
  5706. soc->wlan_cfg_ctx->lro_enabled = params->lro_enable;
  5707. soc->wlan_cfg_ctx->rx_hash = params->flow_steering_enable;
  5708. soc->wlan_cfg_ctx->tcp_udp_checksumoffload =
  5709. params->tcp_udp_checksumoffload;
  5710. soc->wlan_cfg_ctx->napi_enabled = params->napi_enable;
  5711. dp_update_flow_control_parameters(soc, params);
  5712. return QDF_STATUS_SUCCESS;
  5713. }
  5714. /**
  5715. * dp_txrx_set_wds_rx_policy() - API to store datapath
  5716. * config parameters
  5717. * @vdev_handle - datapath vdev handle
  5718. * @cfg: ini parameter handle
  5719. *
  5720. * Return: status
  5721. */
  5722. #ifdef WDS_VENDOR_EXTENSION
  5723. void
  5724. dp_txrx_set_wds_rx_policy(
  5725. struct cdp_vdev *vdev_handle,
  5726. u_int32_t val)
  5727. {
  5728. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  5729. struct dp_peer *peer;
  5730. if (vdev->opmode == wlan_op_mode_ap) {
  5731. /* for ap, set it on bss_peer */
  5732. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  5733. if (peer->bss_peer) {
  5734. peer->wds_ecm.wds_rx_filter = 1;
  5735. peer->wds_ecm.wds_rx_ucast_4addr = (val & WDS_POLICY_RX_UCAST_4ADDR) ? 1:0;
  5736. peer->wds_ecm.wds_rx_mcast_4addr = (val & WDS_POLICY_RX_MCAST_4ADDR) ? 1:0;
  5737. break;
  5738. }
  5739. }
  5740. } else if (vdev->opmode == wlan_op_mode_sta) {
  5741. peer = TAILQ_FIRST(&vdev->peer_list);
  5742. peer->wds_ecm.wds_rx_filter = 1;
  5743. peer->wds_ecm.wds_rx_ucast_4addr = (val & WDS_POLICY_RX_UCAST_4ADDR) ? 1:0;
  5744. peer->wds_ecm.wds_rx_mcast_4addr = (val & WDS_POLICY_RX_MCAST_4ADDR) ? 1:0;
  5745. }
  5746. }
  5747. /**
  5748. * dp_txrx_peer_wds_tx_policy_update() - API to set tx wds policy
  5749. *
  5750. * @peer_handle - datapath peer handle
  5751. * @wds_tx_ucast: policy for unicast transmission
  5752. * @wds_tx_mcast: policy for multicast transmission
  5753. *
  5754. * Return: void
  5755. */
  5756. void
  5757. dp_txrx_peer_wds_tx_policy_update(struct cdp_peer *peer_handle,
  5758. int wds_tx_ucast, int wds_tx_mcast)
  5759. {
  5760. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  5761. if (wds_tx_ucast || wds_tx_mcast) {
  5762. peer->wds_enabled = 1;
  5763. peer->wds_ecm.wds_tx_ucast_4addr = wds_tx_ucast;
  5764. peer->wds_ecm.wds_tx_mcast_4addr = wds_tx_mcast;
  5765. } else {
  5766. peer->wds_enabled = 0;
  5767. peer->wds_ecm.wds_tx_ucast_4addr = 0;
  5768. peer->wds_ecm.wds_tx_mcast_4addr = 0;
  5769. }
  5770. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5771. FL("Policy Update set to :\
  5772. peer->wds_enabled %d\
  5773. peer->wds_ecm.wds_tx_ucast_4addr %d\
  5774. peer->wds_ecm.wds_tx_mcast_4addr %d\n"),
  5775. peer->wds_enabled, peer->wds_ecm.wds_tx_ucast_4addr,
  5776. peer->wds_ecm.wds_tx_mcast_4addr);
  5777. return;
  5778. }
  5779. #endif
  5780. static struct cdp_wds_ops dp_ops_wds = {
  5781. .vdev_set_wds = dp_vdev_set_wds,
  5782. #ifdef WDS_VENDOR_EXTENSION
  5783. .txrx_set_wds_rx_policy = dp_txrx_set_wds_rx_policy,
  5784. .txrx_wds_peer_tx_policy_update = dp_txrx_peer_wds_tx_policy_update,
  5785. #endif
  5786. };
  5787. /*
  5788. * dp_peer_delete_ast_entries(): Delete all AST entries for a peer
  5789. * @soc - datapath soc handle
  5790. * @peer - datapath peer handle
  5791. *
  5792. * Delete the AST entries belonging to a peer
  5793. */
  5794. #ifdef FEATURE_AST
  5795. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  5796. struct dp_peer *peer)
  5797. {
  5798. struct dp_ast_entry *ast_entry, *temp_ast_entry;
  5799. qdf_spin_lock_bh(&soc->ast_lock);
  5800. DP_PEER_ITERATE_ASE_LIST(peer, ast_entry, temp_ast_entry)
  5801. dp_peer_del_ast(soc, ast_entry);
  5802. qdf_spin_unlock_bh(&soc->ast_lock);
  5803. }
  5804. #else
  5805. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  5806. struct dp_peer *peer)
  5807. {
  5808. }
  5809. #endif
  5810. /*
  5811. * dp_txrx_data_tx_cb_set(): set the callback for non standard tx
  5812. * @vdev_handle - datapath vdev handle
  5813. * @callback - callback function
  5814. * @ctxt: callback context
  5815. *
  5816. */
  5817. static void
  5818. dp_txrx_data_tx_cb_set(struct cdp_vdev *vdev_handle,
  5819. ol_txrx_data_tx_cb callback, void *ctxt)
  5820. {
  5821. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  5822. vdev->tx_non_std_data_callback.func = callback;
  5823. vdev->tx_non_std_data_callback.ctxt = ctxt;
  5824. }
  5825. /**
  5826. * dp_pdev_get_dp_txrx_handle() - get dp handle from pdev
  5827. * @pdev_hdl: datapath pdev handle
  5828. *
  5829. * Return: opaque pointer to dp txrx handle
  5830. */
  5831. static void *dp_pdev_get_dp_txrx_handle(struct cdp_pdev *pdev_hdl)
  5832. {
  5833. struct dp_pdev *pdev = (struct dp_pdev *)pdev_hdl;
  5834. return pdev->dp_txrx_handle;
  5835. }
  5836. /**
  5837. * dp_pdev_set_dp_txrx_handle() - set dp handle in pdev
  5838. * @pdev_hdl: datapath pdev handle
  5839. * @dp_txrx_hdl: opaque pointer for dp_txrx_handle
  5840. *
  5841. * Return: void
  5842. */
  5843. static void
  5844. dp_pdev_set_dp_txrx_handle(struct cdp_pdev *pdev_hdl, void *dp_txrx_hdl)
  5845. {
  5846. struct dp_pdev *pdev = (struct dp_pdev *)pdev_hdl;
  5847. pdev->dp_txrx_handle = dp_txrx_hdl;
  5848. }
  5849. /**
  5850. * dp_soc_get_dp_txrx_handle() - get context for external-dp from dp soc
  5851. * @soc_handle: datapath soc handle
  5852. *
  5853. * Return: opaque pointer to external dp (non-core DP)
  5854. */
  5855. static void *dp_soc_get_dp_txrx_handle(struct cdp_soc *soc_handle)
  5856. {
  5857. struct dp_soc *soc = (struct dp_soc *)soc_handle;
  5858. return soc->external_txrx_handle;
  5859. }
  5860. /**
  5861. * dp_soc_set_dp_txrx_handle() - set external dp handle in soc
  5862. * @soc_handle: datapath soc handle
  5863. * @txrx_handle: opaque pointer to external dp (non-core DP)
  5864. *
  5865. * Return: void
  5866. */
  5867. static void
  5868. dp_soc_set_dp_txrx_handle(struct cdp_soc *soc_handle, void *txrx_handle)
  5869. {
  5870. struct dp_soc *soc = (struct dp_soc *)soc_handle;
  5871. soc->external_txrx_handle = txrx_handle;
  5872. }
  5873. #ifdef FEATURE_AST
  5874. static void dp_peer_teardown_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  5875. {
  5876. struct dp_vdev *vdev = (struct dp_vdev *) vdev_hdl;
  5877. struct dp_peer *peer = (struct dp_peer *) peer_hdl;
  5878. struct dp_soc *soc = (struct dp_soc *) vdev->pdev->soc;
  5879. /*
  5880. * For BSS peer, new peer is not created on alloc_node if the
  5881. * peer with same address already exists , instead refcnt is
  5882. * increased for existing peer. Correspondingly in delete path,
  5883. * only refcnt is decreased; and peer is only deleted , when all
  5884. * references are deleted. So delete_in_progress should not be set
  5885. * for bss_peer, unless only 2 reference remains (peer map reference
  5886. * and peer hash table reference).
  5887. */
  5888. if (peer->bss_peer && (qdf_atomic_read(&peer->ref_cnt) > 2)) {
  5889. return;
  5890. }
  5891. peer->delete_in_progress = true;
  5892. dp_peer_delete_ast_entries(soc, peer);
  5893. }
  5894. #endif
  5895. #ifdef ATH_SUPPORT_NAC_RSSI
  5896. static QDF_STATUS dp_config_for_nac_rssi(struct cdp_vdev *vdev_handle,
  5897. enum cdp_nac_param_cmd cmd, char *bssid, char *client_macaddr,
  5898. uint8_t chan_num)
  5899. {
  5900. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  5901. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  5902. struct dp_soc *soc = (struct dp_soc *) vdev->pdev->soc;
  5903. pdev->nac_rssi_filtering = 1;
  5904. /* Store address of NAC (neighbour peer) which will be checked
  5905. * against TA of received packets.
  5906. */
  5907. if (cmd == CDP_NAC_PARAM_ADD) {
  5908. qdf_mem_copy(vdev->cdp_nac_rssi.client_mac,
  5909. client_macaddr, DP_MAC_ADDR_LEN);
  5910. vdev->cdp_nac_rssi_enabled = 1;
  5911. } else if (cmd == CDP_NAC_PARAM_DEL) {
  5912. if (!qdf_mem_cmp(vdev->cdp_nac_rssi.client_mac,
  5913. client_macaddr, DP_MAC_ADDR_LEN)) {
  5914. /* delete this peer from the list */
  5915. qdf_mem_zero(vdev->cdp_nac_rssi.client_mac,
  5916. DP_MAC_ADDR_LEN);
  5917. }
  5918. vdev->cdp_nac_rssi_enabled = 0;
  5919. }
  5920. if (soc->cdp_soc.ol_ops->config_bssid_in_fw_for_nac_rssi)
  5921. soc->cdp_soc.ol_ops->config_bssid_in_fw_for_nac_rssi
  5922. (vdev->pdev->osif_pdev, vdev->vdev_id, cmd, bssid);
  5923. return QDF_STATUS_SUCCESS;
  5924. }
  5925. #endif
  5926. static struct cdp_cmn_ops dp_ops_cmn = {
  5927. .txrx_soc_attach_target = dp_soc_attach_target_wifi3,
  5928. .txrx_vdev_attach = dp_vdev_attach_wifi3,
  5929. .txrx_vdev_detach = dp_vdev_detach_wifi3,
  5930. .txrx_pdev_attach = dp_pdev_attach_wifi3,
  5931. .txrx_pdev_detach = dp_pdev_detach_wifi3,
  5932. .txrx_peer_create = dp_peer_create_wifi3,
  5933. .txrx_peer_setup = dp_peer_setup_wifi3,
  5934. #ifdef FEATURE_AST
  5935. .txrx_peer_teardown = dp_peer_teardown_wifi3,
  5936. #else
  5937. .txrx_peer_teardown = NULL,
  5938. #endif
  5939. .txrx_peer_add_ast = dp_peer_add_ast_wifi3,
  5940. .txrx_peer_del_ast = dp_peer_del_ast_wifi3,
  5941. .txrx_peer_update_ast = dp_peer_update_ast_wifi3,
  5942. .txrx_peer_ast_hash_find = dp_peer_ast_hash_find_wifi3,
  5943. .txrx_peer_ast_get_pdev_id = dp_peer_ast_get_pdev_id_wifi3,
  5944. .txrx_peer_ast_get_next_hop = dp_peer_ast_get_next_hop_wifi3,
  5945. .txrx_peer_ast_set_type = dp_peer_ast_set_type_wifi3,
  5946. .txrx_peer_delete = dp_peer_delete_wifi3,
  5947. .txrx_vdev_register = dp_vdev_register_wifi3,
  5948. .txrx_soc_detach = dp_soc_detach_wifi3,
  5949. .txrx_get_vdev_mac_addr = dp_get_vdev_mac_addr_wifi3,
  5950. .txrx_get_vdev_from_vdev_id = dp_get_vdev_from_vdev_id_wifi3,
  5951. .txrx_get_ctrl_pdev_from_vdev = dp_get_ctrl_pdev_from_vdev_wifi3,
  5952. .txrx_ath_getstats = dp_pdev_getstats,
  5953. .addba_requestprocess = dp_addba_requestprocess_wifi3,
  5954. .addba_responsesetup = dp_addba_responsesetup_wifi3,
  5955. .delba_process = dp_delba_process_wifi3,
  5956. .set_addba_response = dp_set_addba_response,
  5957. .get_peer_mac_addr_frm_id = dp_get_peer_mac_addr_frm_id,
  5958. .flush_cache_rx_queue = NULL,
  5959. /* TODO: get API's for dscp-tid need to be added*/
  5960. .set_vdev_dscp_tid_map = dp_set_vdev_dscp_tid_map_wifi3,
  5961. .set_pdev_dscp_tid_map = dp_set_pdev_dscp_tid_map_wifi3,
  5962. .txrx_stats_request = dp_txrx_stats_request,
  5963. .txrx_set_monitor_mode = dp_vdev_set_monitor_mode,
  5964. .txrx_get_pdev_id_frm_pdev = dp_get_pdev_id_frm_pdev,
  5965. .txrx_set_nac = dp_set_nac,
  5966. .txrx_get_tx_pending = dp_get_tx_pending,
  5967. .txrx_set_pdev_tx_capture = dp_config_debug_sniffer,
  5968. .txrx_get_peer_mac_from_peer_id = dp_get_peer_mac_from_peer_id,
  5969. .display_stats = dp_txrx_dump_stats,
  5970. .txrx_soc_set_nss_cfg = dp_soc_set_nss_cfg_wifi3,
  5971. .txrx_soc_get_nss_cfg = dp_soc_get_nss_cfg_wifi3,
  5972. #ifdef DP_INTR_POLL_BASED
  5973. .txrx_intr_attach = dp_soc_interrupt_attach_wrapper,
  5974. #else
  5975. .txrx_intr_attach = dp_soc_interrupt_attach,
  5976. #endif
  5977. .txrx_intr_detach = dp_soc_interrupt_detach,
  5978. .set_pn_check = dp_set_pn_check_wifi3,
  5979. .update_config_parameters = dp_update_config_parameters,
  5980. /* TODO: Add other functions */
  5981. .txrx_data_tx_cb_set = dp_txrx_data_tx_cb_set,
  5982. .get_dp_txrx_handle = dp_pdev_get_dp_txrx_handle,
  5983. .set_dp_txrx_handle = dp_pdev_set_dp_txrx_handle,
  5984. .get_soc_dp_txrx_handle = dp_soc_get_dp_txrx_handle,
  5985. .set_soc_dp_txrx_handle = dp_soc_set_dp_txrx_handle,
  5986. .tx_send = dp_tx_send,
  5987. .txrx_peer_reset_ast = dp_wds_reset_ast_wifi3,
  5988. .txrx_peer_reset_ast_table = dp_wds_reset_ast_table_wifi3,
  5989. .txrx_peer_flush_ast_table = dp_wds_flush_ast_table_wifi3,
  5990. };
  5991. static struct cdp_ctrl_ops dp_ops_ctrl = {
  5992. .txrx_peer_authorize = dp_peer_authorize,
  5993. #ifdef QCA_SUPPORT_SON
  5994. .txrx_set_inact_params = dp_set_inact_params,
  5995. .txrx_start_inact_timer = dp_start_inact_timer,
  5996. .txrx_set_overload = dp_set_overload,
  5997. .txrx_peer_is_inact = dp_peer_is_inact,
  5998. .txrx_mark_peer_inact = dp_mark_peer_inact,
  5999. #endif
  6000. .txrx_set_vdev_rx_decap_type = dp_set_vdev_rx_decap_type,
  6001. .txrx_set_tx_encap_type = dp_set_vdev_tx_encap_type,
  6002. #ifdef MESH_MODE_SUPPORT
  6003. .txrx_set_mesh_mode = dp_peer_set_mesh_mode,
  6004. .txrx_set_mesh_rx_filter = dp_peer_set_mesh_rx_filter,
  6005. #endif
  6006. .txrx_set_vdev_param = dp_set_vdev_param,
  6007. .txrx_peer_set_nawds = dp_peer_set_nawds,
  6008. .txrx_set_pdev_reo_dest = dp_set_pdev_reo_dest,
  6009. .txrx_get_pdev_reo_dest = dp_get_pdev_reo_dest,
  6010. .txrx_set_filter_neighbour_peers = dp_set_filter_neighbour_peers,
  6011. .txrx_update_filter_neighbour_peers =
  6012. dp_update_filter_neighbour_peers,
  6013. .txrx_get_sec_type = dp_get_sec_type,
  6014. /* TODO: Add other functions */
  6015. .txrx_wdi_event_sub = dp_wdi_event_sub,
  6016. .txrx_wdi_event_unsub = dp_wdi_event_unsub,
  6017. #ifdef WDI_EVENT_ENABLE
  6018. .txrx_get_pldev = dp_get_pldev,
  6019. #endif
  6020. .txrx_set_pdev_param = dp_set_pdev_param,
  6021. #ifdef ATH_SUPPORT_NAC_RSSI
  6022. .txrx_vdev_config_for_nac_rssi = dp_config_for_nac_rssi,
  6023. #endif
  6024. };
  6025. static struct cdp_me_ops dp_ops_me = {
  6026. #ifdef ATH_SUPPORT_IQUE
  6027. .tx_me_alloc_descriptor = dp_tx_me_alloc_descriptor,
  6028. .tx_me_free_descriptor = dp_tx_me_free_descriptor,
  6029. .tx_me_convert_ucast = dp_tx_me_send_convert_ucast,
  6030. #endif
  6031. };
  6032. static struct cdp_mon_ops dp_ops_mon = {
  6033. .txrx_monitor_set_filter_ucast_data = NULL,
  6034. .txrx_monitor_set_filter_mcast_data = NULL,
  6035. .txrx_monitor_set_filter_non_data = NULL,
  6036. .txrx_monitor_get_filter_ucast_data = dp_vdev_get_filter_ucast_data,
  6037. .txrx_monitor_get_filter_mcast_data = dp_vdev_get_filter_mcast_data,
  6038. .txrx_monitor_get_filter_non_data = dp_vdev_get_filter_non_data,
  6039. .txrx_reset_monitor_mode = dp_reset_monitor_mode,
  6040. /* Added support for HK advance filter */
  6041. .txrx_set_advance_monitor_filter = dp_pdev_set_advance_monitor_filter,
  6042. };
  6043. static struct cdp_host_stats_ops dp_ops_host_stats = {
  6044. .txrx_per_peer_stats = dp_get_host_peer_stats,
  6045. .get_fw_peer_stats = dp_get_fw_peer_stats,
  6046. .get_htt_stats = dp_get_htt_stats,
  6047. .txrx_enable_enhanced_stats = dp_enable_enhanced_stats,
  6048. .txrx_disable_enhanced_stats = dp_disable_enhanced_stats,
  6049. .txrx_stats_publish = dp_txrx_stats_publish,
  6050. /* TODO */
  6051. };
  6052. static struct cdp_raw_ops dp_ops_raw = {
  6053. /* TODO */
  6054. };
  6055. #ifdef CONFIG_WIN
  6056. static struct cdp_pflow_ops dp_ops_pflow = {
  6057. /* TODO */
  6058. };
  6059. #endif /* CONFIG_WIN */
  6060. #ifdef FEATURE_RUNTIME_PM
  6061. /**
  6062. * dp_runtime_suspend() - ensure DP is ready to runtime suspend
  6063. * @opaque_pdev: DP pdev context
  6064. *
  6065. * DP is ready to runtime suspend if there are no pending TX packets.
  6066. *
  6067. * Return: QDF_STATUS
  6068. */
  6069. static QDF_STATUS dp_runtime_suspend(struct cdp_pdev *opaque_pdev)
  6070. {
  6071. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  6072. struct dp_soc *soc = pdev->soc;
  6073. /* Call DP TX flow control API to check if there is any
  6074. pending packets */
  6075. if (soc->intr_mode == DP_INTR_POLL)
  6076. qdf_timer_stop(&soc->int_timer);
  6077. return QDF_STATUS_SUCCESS;
  6078. }
  6079. /**
  6080. * dp_runtime_resume() - ensure DP is ready to runtime resume
  6081. * @opaque_pdev: DP pdev context
  6082. *
  6083. * Resume DP for runtime PM.
  6084. *
  6085. * Return: QDF_STATUS
  6086. */
  6087. static QDF_STATUS dp_runtime_resume(struct cdp_pdev *opaque_pdev)
  6088. {
  6089. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  6090. struct dp_soc *soc = pdev->soc;
  6091. void *hal_srng;
  6092. int i;
  6093. if (soc->intr_mode == DP_INTR_POLL)
  6094. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  6095. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  6096. hal_srng = soc->tcl_data_ring[i].hal_srng;
  6097. if (hal_srng) {
  6098. /* We actually only need to acquire the lock */
  6099. hal_srng_access_start(soc->hal_soc, hal_srng);
  6100. /* Update SRC ring head pointer for HW to send
  6101. all pending packets */
  6102. hal_srng_access_end(soc->hal_soc, hal_srng);
  6103. }
  6104. }
  6105. return QDF_STATUS_SUCCESS;
  6106. }
  6107. #endif /* FEATURE_RUNTIME_PM */
  6108. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  6109. {
  6110. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  6111. struct dp_soc *soc = pdev->soc;
  6112. if (soc->intr_mode == DP_INTR_POLL)
  6113. qdf_timer_stop(&soc->int_timer);
  6114. return QDF_STATUS_SUCCESS;
  6115. }
  6116. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  6117. {
  6118. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  6119. struct dp_soc *soc = pdev->soc;
  6120. if (soc->intr_mode == DP_INTR_POLL)
  6121. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  6122. return QDF_STATUS_SUCCESS;
  6123. }
  6124. #ifndef CONFIG_WIN
  6125. static struct cdp_misc_ops dp_ops_misc = {
  6126. .tx_non_std = dp_tx_non_std,
  6127. .get_opmode = dp_get_opmode,
  6128. #ifdef FEATURE_RUNTIME_PM
  6129. .runtime_suspend = dp_runtime_suspend,
  6130. .runtime_resume = dp_runtime_resume,
  6131. #endif /* FEATURE_RUNTIME_PM */
  6132. .pkt_log_init = dp_pkt_log_init,
  6133. .pkt_log_con_service = dp_pkt_log_con_service,
  6134. };
  6135. static struct cdp_flowctl_ops dp_ops_flowctl = {
  6136. /* WIFI 3.0 DP implement as required. */
  6137. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  6138. .register_pause_cb = dp_txrx_register_pause_cb,
  6139. .dump_flow_pool_info = dp_tx_dump_flow_pool_info,
  6140. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  6141. };
  6142. static struct cdp_lflowctl_ops dp_ops_l_flowctl = {
  6143. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  6144. };
  6145. #ifdef IPA_OFFLOAD
  6146. static struct cdp_ipa_ops dp_ops_ipa = {
  6147. .ipa_get_resource = dp_ipa_get_resource,
  6148. .ipa_set_doorbell_paddr = dp_ipa_set_doorbell_paddr,
  6149. .ipa_op_response = dp_ipa_op_response,
  6150. .ipa_register_op_cb = dp_ipa_register_op_cb,
  6151. .ipa_get_stat = dp_ipa_get_stat,
  6152. .ipa_tx_data_frame = dp_tx_send_ipa_data_frame,
  6153. .ipa_enable_autonomy = dp_ipa_enable_autonomy,
  6154. .ipa_disable_autonomy = dp_ipa_disable_autonomy,
  6155. .ipa_setup = dp_ipa_setup,
  6156. .ipa_cleanup = dp_ipa_cleanup,
  6157. .ipa_setup_iface = dp_ipa_setup_iface,
  6158. .ipa_cleanup_iface = dp_ipa_cleanup_iface,
  6159. .ipa_enable_pipes = dp_ipa_enable_pipes,
  6160. .ipa_disable_pipes = dp_ipa_disable_pipes,
  6161. .ipa_set_perf_level = dp_ipa_set_perf_level
  6162. };
  6163. #endif
  6164. static struct cdp_bus_ops dp_ops_bus = {
  6165. .bus_suspend = dp_bus_suspend,
  6166. .bus_resume = dp_bus_resume
  6167. };
  6168. static struct cdp_ocb_ops dp_ops_ocb = {
  6169. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  6170. };
  6171. static struct cdp_throttle_ops dp_ops_throttle = {
  6172. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  6173. };
  6174. static struct cdp_mob_stats_ops dp_ops_mob_stats = {
  6175. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  6176. };
  6177. static struct cdp_cfg_ops dp_ops_cfg = {
  6178. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  6179. };
  6180. /*
  6181. * dp_wrapper_peer_get_ref_by_addr - wrapper function to get to peer
  6182. * @dev: physical device instance
  6183. * @peer_mac_addr: peer mac address
  6184. * @local_id: local id for the peer
  6185. * @debug_id: to track enum peer access
  6186. * Return: peer instance pointer
  6187. */
  6188. static inline void *
  6189. dp_wrapper_peer_get_ref_by_addr(struct cdp_pdev *dev, u8 *peer_mac_addr,
  6190. u8 *local_id,
  6191. enum peer_debug_id_type debug_id)
  6192. {
  6193. /*
  6194. * Currently this function does not implement the "get ref"
  6195. * functionality and is mapped to dp_find_peer_by_addr which does not
  6196. * increment the peer ref count. So the peer state is uncertain after
  6197. * calling this API. The functionality needs to be implemented.
  6198. * Accordingly the corresponding release_ref function is NULL.
  6199. */
  6200. return dp_find_peer_by_addr(dev, peer_mac_addr, local_id);
  6201. }
  6202. static struct cdp_peer_ops dp_ops_peer = {
  6203. .register_peer = dp_register_peer,
  6204. .clear_peer = dp_clear_peer,
  6205. .find_peer_by_addr = dp_find_peer_by_addr,
  6206. .find_peer_by_addr_and_vdev = dp_find_peer_by_addr_and_vdev,
  6207. .peer_get_ref_by_addr = dp_wrapper_peer_get_ref_by_addr,
  6208. .peer_release_ref = NULL,
  6209. .local_peer_id = dp_local_peer_id,
  6210. .peer_find_by_local_id = dp_peer_find_by_local_id,
  6211. .peer_state_update = dp_peer_state_update,
  6212. .get_vdevid = dp_get_vdevid,
  6213. .get_vdev_by_sta_id = dp_get_vdev_by_sta_id,
  6214. .peer_get_peer_mac_addr = dp_peer_get_peer_mac_addr,
  6215. .get_vdev_for_peer = dp_get_vdev_for_peer,
  6216. .get_peer_state = dp_get_peer_state,
  6217. .last_assoc_received = dp_get_last_assoc_received,
  6218. .last_disassoc_received = dp_get_last_disassoc_received,
  6219. .last_deauth_received = dp_get_last_deauth_received,
  6220. };
  6221. #endif
  6222. static struct cdp_ops dp_txrx_ops = {
  6223. .cmn_drv_ops = &dp_ops_cmn,
  6224. .ctrl_ops = &dp_ops_ctrl,
  6225. .me_ops = &dp_ops_me,
  6226. .mon_ops = &dp_ops_mon,
  6227. .host_stats_ops = &dp_ops_host_stats,
  6228. .wds_ops = &dp_ops_wds,
  6229. .raw_ops = &dp_ops_raw,
  6230. #ifdef CONFIG_WIN
  6231. .pflow_ops = &dp_ops_pflow,
  6232. #endif /* CONFIG_WIN */
  6233. #ifndef CONFIG_WIN
  6234. .misc_ops = &dp_ops_misc,
  6235. .cfg_ops = &dp_ops_cfg,
  6236. .flowctl_ops = &dp_ops_flowctl,
  6237. .l_flowctl_ops = &dp_ops_l_flowctl,
  6238. #ifdef IPA_OFFLOAD
  6239. .ipa_ops = &dp_ops_ipa,
  6240. #endif
  6241. .bus_ops = &dp_ops_bus,
  6242. .ocb_ops = &dp_ops_ocb,
  6243. .peer_ops = &dp_ops_peer,
  6244. .throttle_ops = &dp_ops_throttle,
  6245. .mob_stats_ops = &dp_ops_mob_stats,
  6246. #endif
  6247. };
  6248. /*
  6249. * dp_soc_set_txrx_ring_map()
  6250. * @dp_soc: DP handler for soc
  6251. *
  6252. * Return: Void
  6253. */
  6254. static void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  6255. {
  6256. uint32_t i;
  6257. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  6258. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_DEFAULT_MAP][i];
  6259. }
  6260. }
  6261. /*
  6262. * dp_soc_attach_wifi3() - Attach txrx SOC
  6263. * @ctrl_psoc: Opaque SOC handle from control plane
  6264. * @htc_handle: Opaque HTC handle
  6265. * @hif_handle: Opaque HIF handle
  6266. * @qdf_osdev: QDF device
  6267. *
  6268. * Return: DP SOC handle on success, NULL on failure
  6269. */
  6270. /*
  6271. * Local prototype added to temporarily address warning caused by
  6272. * -Wmissing-prototypes. A more correct solution, namely to expose
  6273. * a prototype in an appropriate header file, will come later.
  6274. */
  6275. void *dp_soc_attach_wifi3(void *ctrl_psoc, void *hif_handle,
  6276. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  6277. struct ol_if_ops *ol_ops);
  6278. void *dp_soc_attach_wifi3(void *ctrl_psoc, void *hif_handle,
  6279. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  6280. struct ol_if_ops *ol_ops)
  6281. {
  6282. struct dp_soc *soc = qdf_mem_malloc(sizeof(*soc));
  6283. if (!soc) {
  6284. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  6285. FL("DP SOC memory allocation failed"));
  6286. goto fail0;
  6287. }
  6288. soc->cdp_soc.ops = &dp_txrx_ops;
  6289. soc->cdp_soc.ol_ops = ol_ops;
  6290. soc->ctrl_psoc = ctrl_psoc;
  6291. soc->osdev = qdf_osdev;
  6292. soc->hif_handle = hif_handle;
  6293. soc->hal_soc = hif_get_hal_handle(hif_handle);
  6294. soc->htt_handle = htt_soc_attach(soc, ctrl_psoc, htc_handle,
  6295. soc->hal_soc, qdf_osdev);
  6296. if (!soc->htt_handle) {
  6297. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  6298. FL("HTT attach failed"));
  6299. goto fail1;
  6300. }
  6301. soc->wlan_cfg_ctx = wlan_cfg_soc_attach();
  6302. if (!soc->wlan_cfg_ctx) {
  6303. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  6304. FL("wlan_cfg_soc_attach failed"));
  6305. goto fail2;
  6306. }
  6307. wlan_cfg_set_rx_hash(soc->wlan_cfg_ctx, rx_hash);
  6308. soc->cce_disable = false;
  6309. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  6310. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc->ctrl_psoc,
  6311. CDP_CFG_MAX_PEER_ID);
  6312. if (ret != -EINVAL) {
  6313. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  6314. }
  6315. ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc->ctrl_psoc,
  6316. CDP_CFG_CCE_DISABLE);
  6317. if (ret == 1)
  6318. soc->cce_disable = true;
  6319. }
  6320. qdf_spinlock_create(&soc->peer_ref_mutex);
  6321. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  6322. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  6323. /* fill the tx/rx cpu ring map*/
  6324. dp_soc_set_txrx_ring_map(soc);
  6325. qdf_spinlock_create(&soc->htt_stats.lock);
  6326. /* initialize work queue for stats processing */
  6327. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  6328. /*Initialize inactivity timer for wifison */
  6329. dp_init_inact_timer(soc);
  6330. return (void *)soc;
  6331. fail2:
  6332. htt_soc_detach(soc->htt_handle);
  6333. fail1:
  6334. qdf_mem_free(soc);
  6335. fail0:
  6336. return NULL;
  6337. }
  6338. /*
  6339. * dp_get_pdev_for_mac_id() - Return pdev for mac_id
  6340. *
  6341. * @soc: handle to DP soc
  6342. * @mac_id: MAC id
  6343. *
  6344. * Return: Return pdev corresponding to MAC
  6345. */
  6346. void *dp_get_pdev_for_mac_id(struct dp_soc *soc, uint32_t mac_id)
  6347. {
  6348. if (wlan_cfg_per_pdev_lmac_ring(soc->wlan_cfg_ctx))
  6349. return soc->pdev_list[mac_id];
  6350. /* Typically for MCL as there only 1 PDEV*/
  6351. return soc->pdev_list[0];
  6352. }
  6353. /*
  6354. * dp_is_hw_dbs_enable() - Procedure to check if DBS is supported
  6355. * @soc: DP SoC context
  6356. * @max_mac_rings: No of MAC rings
  6357. *
  6358. * Return: None
  6359. */
  6360. static
  6361. void dp_is_hw_dbs_enable(struct dp_soc *soc,
  6362. int *max_mac_rings)
  6363. {
  6364. bool dbs_enable = false;
  6365. if (soc->cdp_soc.ol_ops->is_hw_dbs_2x2_capable)
  6366. dbs_enable = soc->cdp_soc.ol_ops->
  6367. is_hw_dbs_2x2_capable(soc->ctrl_psoc);
  6368. *max_mac_rings = (dbs_enable)?(*max_mac_rings):1;
  6369. }
  6370. /*
  6371. * dp_set_pktlog_wifi3() - attach txrx vdev
  6372. * @pdev: Datapath PDEV handle
  6373. * @event: which event's notifications are being subscribed to
  6374. * @enable: WDI event subscribe or not. (True or False)
  6375. *
  6376. * Return: Success, NULL on failure
  6377. */
  6378. #ifdef WDI_EVENT_ENABLE
  6379. int dp_set_pktlog_wifi3(struct dp_pdev *pdev, uint32_t event,
  6380. bool enable)
  6381. {
  6382. struct dp_soc *soc = pdev->soc;
  6383. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  6384. int max_mac_rings = wlan_cfg_get_num_mac_rings
  6385. (pdev->wlan_cfg_ctx);
  6386. uint8_t mac_id = 0;
  6387. dp_is_hw_dbs_enable(soc, &max_mac_rings);
  6388. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  6389. FL("Max_mac_rings %d \n"),
  6390. max_mac_rings);
  6391. if (enable) {
  6392. switch (event) {
  6393. case WDI_EVENT_RX_DESC:
  6394. if (pdev->monitor_vdev) {
  6395. /* Nothing needs to be done if monitor mode is
  6396. * enabled
  6397. */
  6398. return 0;
  6399. }
  6400. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_FULL) {
  6401. pdev->rx_pktlog_mode = DP_RX_PKTLOG_FULL;
  6402. htt_tlv_filter.mpdu_start = 1;
  6403. htt_tlv_filter.msdu_start = 1;
  6404. htt_tlv_filter.msdu_end = 1;
  6405. htt_tlv_filter.mpdu_end = 1;
  6406. htt_tlv_filter.packet_header = 1;
  6407. htt_tlv_filter.attention = 1;
  6408. htt_tlv_filter.ppdu_start = 1;
  6409. htt_tlv_filter.ppdu_end = 1;
  6410. htt_tlv_filter.ppdu_end_user_stats = 1;
  6411. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  6412. htt_tlv_filter.ppdu_end_status_done = 1;
  6413. htt_tlv_filter.enable_fp = 1;
  6414. htt_tlv_filter.fp_mgmt_filter = FILTER_MGMT_ALL;
  6415. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_ALL;
  6416. htt_tlv_filter.fp_data_filter = FILTER_DATA_ALL;
  6417. htt_tlv_filter.mo_mgmt_filter = FILTER_MGMT_ALL;
  6418. htt_tlv_filter.mo_ctrl_filter = FILTER_CTRL_ALL;
  6419. htt_tlv_filter.mo_data_filter = FILTER_DATA_ALL;
  6420. for (mac_id = 0; mac_id < max_mac_rings;
  6421. mac_id++) {
  6422. int mac_for_pdev =
  6423. dp_get_mac_id_for_pdev(mac_id,
  6424. pdev->pdev_id);
  6425. htt_h2t_rx_ring_cfg(soc->htt_handle,
  6426. mac_for_pdev,
  6427. pdev->rxdma_mon_status_ring[mac_id]
  6428. .hal_srng,
  6429. RXDMA_MONITOR_STATUS,
  6430. RX_BUFFER_SIZE,
  6431. &htt_tlv_filter);
  6432. }
  6433. if (soc->reap_timer_init)
  6434. qdf_timer_mod(&soc->mon_reap_timer,
  6435. DP_INTR_POLL_TIMER_MS);
  6436. }
  6437. break;
  6438. case WDI_EVENT_LITE_RX:
  6439. if (pdev->monitor_vdev) {
  6440. /* Nothing needs to be done if monitor mode is
  6441. * enabled
  6442. */
  6443. return 0;
  6444. }
  6445. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_LITE) {
  6446. pdev->rx_pktlog_mode = DP_RX_PKTLOG_LITE;
  6447. htt_tlv_filter.ppdu_start = 1;
  6448. htt_tlv_filter.ppdu_end = 1;
  6449. htt_tlv_filter.ppdu_end_user_stats = 1;
  6450. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  6451. htt_tlv_filter.ppdu_end_status_done = 1;
  6452. htt_tlv_filter.mpdu_start = 1;
  6453. htt_tlv_filter.enable_fp = 1;
  6454. htt_tlv_filter.fp_mgmt_filter = FILTER_MGMT_ALL;
  6455. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_ALL;
  6456. htt_tlv_filter.fp_data_filter = FILTER_DATA_ALL;
  6457. htt_tlv_filter.mo_mgmt_filter = FILTER_MGMT_ALL;
  6458. htt_tlv_filter.mo_ctrl_filter = FILTER_CTRL_ALL;
  6459. htt_tlv_filter.mo_data_filter = FILTER_DATA_ALL;
  6460. for (mac_id = 0; mac_id < max_mac_rings;
  6461. mac_id++) {
  6462. int mac_for_pdev =
  6463. dp_get_mac_id_for_pdev(mac_id,
  6464. pdev->pdev_id);
  6465. htt_h2t_rx_ring_cfg(soc->htt_handle,
  6466. mac_for_pdev,
  6467. pdev->rxdma_mon_status_ring[mac_id]
  6468. .hal_srng,
  6469. RXDMA_MONITOR_STATUS,
  6470. RX_BUFFER_SIZE_PKTLOG_LITE,
  6471. &htt_tlv_filter);
  6472. }
  6473. if (soc->reap_timer_init)
  6474. qdf_timer_mod(&soc->mon_reap_timer,
  6475. DP_INTR_POLL_TIMER_MS);
  6476. }
  6477. break;
  6478. case WDI_EVENT_LITE_T2H:
  6479. if (pdev->monitor_vdev) {
  6480. /* Nothing needs to be done if monitor mode is
  6481. * enabled
  6482. */
  6483. return 0;
  6484. }
  6485. for (mac_id = 0; mac_id < max_mac_rings; mac_id++) {
  6486. int mac_for_pdev = dp_get_mac_id_for_pdev(
  6487. mac_id, pdev->pdev_id);
  6488. pdev->pktlog_ppdu_stats = true;
  6489. dp_h2t_cfg_stats_msg_send(pdev,
  6490. DP_PPDU_TXLITE_STATS_BITMASK_CFG,
  6491. mac_for_pdev);
  6492. }
  6493. break;
  6494. default:
  6495. /* Nothing needs to be done for other pktlog types */
  6496. break;
  6497. }
  6498. } else {
  6499. switch (event) {
  6500. case WDI_EVENT_RX_DESC:
  6501. case WDI_EVENT_LITE_RX:
  6502. if (pdev->monitor_vdev) {
  6503. /* Nothing needs to be done if monitor mode is
  6504. * enabled
  6505. */
  6506. return 0;
  6507. }
  6508. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_DISABLED) {
  6509. pdev->rx_pktlog_mode = DP_RX_PKTLOG_DISABLED;
  6510. for (mac_id = 0; mac_id < max_mac_rings;
  6511. mac_id++) {
  6512. int mac_for_pdev =
  6513. dp_get_mac_id_for_pdev(mac_id,
  6514. pdev->pdev_id);
  6515. htt_h2t_rx_ring_cfg(soc->htt_handle,
  6516. mac_for_pdev,
  6517. pdev->rxdma_mon_status_ring[mac_id]
  6518. .hal_srng,
  6519. RXDMA_MONITOR_STATUS,
  6520. RX_BUFFER_SIZE,
  6521. &htt_tlv_filter);
  6522. }
  6523. if (soc->reap_timer_init)
  6524. qdf_timer_stop(&soc->mon_reap_timer);
  6525. }
  6526. break;
  6527. case WDI_EVENT_LITE_T2H:
  6528. if (pdev->monitor_vdev) {
  6529. /* Nothing needs to be done if monitor mode is
  6530. * enabled
  6531. */
  6532. return 0;
  6533. }
  6534. /* To disable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  6535. * passing value 0. Once these macros will define in htt
  6536. * header file will use proper macros
  6537. */
  6538. for (mac_id = 0; mac_id < max_mac_rings; mac_id++) {
  6539. int mac_for_pdev =
  6540. dp_get_mac_id_for_pdev(mac_id,
  6541. pdev->pdev_id);
  6542. pdev->pktlog_ppdu_stats = false;
  6543. if (!pdev->enhanced_stats_en && !pdev->tx_sniffer_enable && !pdev->mcopy_mode) {
  6544. dp_h2t_cfg_stats_msg_send(pdev, 0,
  6545. mac_for_pdev);
  6546. } else if (pdev->tx_sniffer_enable || pdev->mcopy_mode) {
  6547. dp_h2t_cfg_stats_msg_send(pdev, DP_PPDU_STATS_CFG_SNIFFER,
  6548. mac_for_pdev);
  6549. } else if (pdev->enhanced_stats_en) {
  6550. dp_h2t_cfg_stats_msg_send(pdev, DP_PPDU_STATS_CFG_ENH_STATS,
  6551. mac_for_pdev);
  6552. }
  6553. }
  6554. break;
  6555. default:
  6556. /* Nothing needs to be done for other pktlog types */
  6557. break;
  6558. }
  6559. }
  6560. return 0;
  6561. }
  6562. #endif
  6563. #ifdef CONFIG_MCL
  6564. /*
  6565. * dp_service_mon_rings()- timer to reap monitor rings
  6566. * reqd as we are not getting ppdu end interrupts
  6567. * @arg: SoC Handle
  6568. *
  6569. * Return:
  6570. *
  6571. */
  6572. static void dp_service_mon_rings(void *arg)
  6573. {
  6574. struct dp_soc *soc = (struct dp_soc *) arg;
  6575. int ring = 0, work_done, mac_id;
  6576. struct dp_pdev *pdev = NULL;
  6577. for (ring = 0 ; ring < MAX_PDEV_CNT; ring++) {
  6578. pdev = soc->pdev_list[ring];
  6579. if (pdev == NULL)
  6580. continue;
  6581. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  6582. int mac_for_pdev = dp_get_mac_id_for_pdev(mac_id,
  6583. pdev->pdev_id);
  6584. work_done = dp_mon_process(soc, mac_for_pdev,
  6585. QCA_NAPI_BUDGET);
  6586. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  6587. FL("Reaped %d descs from Monitor rings"),
  6588. work_done);
  6589. }
  6590. }
  6591. qdf_timer_mod(&soc->mon_reap_timer, DP_INTR_POLL_TIMER_MS);
  6592. }
  6593. #ifndef REMOVE_PKT_LOG
  6594. /**
  6595. * dp_pkt_log_init() - API to initialize packet log
  6596. * @ppdev: physical device handle
  6597. * @scn: HIF context
  6598. *
  6599. * Return: none
  6600. */
  6601. void dp_pkt_log_init(struct cdp_pdev *ppdev, void *scn)
  6602. {
  6603. struct dp_pdev *handle = (struct dp_pdev *)ppdev;
  6604. if (handle->pkt_log_init) {
  6605. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  6606. "%s: Packet log not initialized", __func__);
  6607. return;
  6608. }
  6609. pktlog_sethandle(&handle->pl_dev, scn);
  6610. pktlog_set_callback_regtype(PKTLOG_LITE_CALLBACK_REGISTRATION);
  6611. if (pktlogmod_init(scn)) {
  6612. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  6613. "%s: pktlogmod_init failed", __func__);
  6614. handle->pkt_log_init = false;
  6615. } else {
  6616. handle->pkt_log_init = true;
  6617. }
  6618. }
  6619. /**
  6620. * dp_pkt_log_con_service() - connect packet log service
  6621. * @ppdev: physical device handle
  6622. * @scn: device context
  6623. *
  6624. * Return: none
  6625. */
  6626. static void dp_pkt_log_con_service(struct cdp_pdev *ppdev, void *scn)
  6627. {
  6628. struct dp_pdev *pdev = (struct dp_pdev *)ppdev;
  6629. dp_pkt_log_init((struct cdp_pdev *)pdev, scn);
  6630. pktlog_htc_attach();
  6631. }
  6632. /**
  6633. * dp_pktlogmod_exit() - API to cleanup pktlog info
  6634. * @handle: Pdev handle
  6635. *
  6636. * Return: none
  6637. */
  6638. static void dp_pktlogmod_exit(struct dp_pdev *handle)
  6639. {
  6640. void *scn = (void *)handle->soc->hif_handle;
  6641. if (!scn) {
  6642. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  6643. "%s: Invalid hif(scn) handle", __func__);
  6644. return;
  6645. }
  6646. pktlogmod_exit(scn);
  6647. handle->pkt_log_init = false;
  6648. }
  6649. #endif
  6650. #else
  6651. static void dp_pktlogmod_exit(struct dp_pdev *handle) { }
  6652. #endif