main.c 102 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/devcoredump.h>
  8. #include <linux/elf.h>
  9. #include <linux/jiffies.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_device.h>
  13. #include <linux/of_gpio.h>
  14. #include <linux/pm_wakeup.h>
  15. #include <linux/reboot.h>
  16. #include <linux/rwsem.h>
  17. #include <linux/suspend.h>
  18. #include <linux/timer.h>
  19. #include <linux/version.h>
  20. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0))
  21. #include <linux/panic_notifier.h>
  22. #endif
  23. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  24. #include <soc/qcom/minidump.h>
  25. #endif
  26. #include "cnss_plat_ipc_qmi.h"
  27. #include "cnss_utils.h"
  28. #include "main.h"
  29. #include "bus.h"
  30. #include "debug.h"
  31. #include "genl.h"
  32. #define CNSS_DUMP_FORMAT_VER 0x11
  33. #define CNSS_DUMP_FORMAT_VER_V2 0x22
  34. #define CNSS_DUMP_MAGIC_VER_V2 0x42445953
  35. #define CNSS_DUMP_NAME "CNSS_WLAN"
  36. #define CNSS_DUMP_DESC_SIZE 0x1000
  37. #define CNSS_DUMP_SEG_VER 0x1
  38. #define FILE_SYSTEM_READY 1
  39. #define FW_READY_TIMEOUT 20000
  40. #define FW_ASSERT_TIMEOUT 5000
  41. #define CNSS_EVENT_PENDING 2989
  42. #define POWER_RESET_MIN_DELAY_MS 100
  43. #define CNSS_QUIRKS_DEFAULT 0
  44. #ifdef CONFIG_CNSS_EMULATION
  45. #define CNSS_MHI_TIMEOUT_DEFAULT 90000
  46. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 2000
  47. #define CNSS_QMI_TIMEOUT_DEFAULT 90000
  48. #else
  49. #define CNSS_MHI_TIMEOUT_DEFAULT 0
  50. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 25
  51. #define CNSS_QMI_TIMEOUT_DEFAULT 10000
  52. #endif
  53. #define CNSS_BDF_TYPE_DEFAULT CNSS_BDF_ELF
  54. #define CNSS_TIME_SYNC_PERIOD_DEFAULT 900000
  55. #define CNSS_DMS_QMI_CONNECTION_WAIT_MS 50
  56. #define CNSS_DMS_QMI_CONNECTION_WAIT_RETRY 200
  57. #define CNSS_DAEMON_CONNECT_TIMEOUT_MS 30000
  58. #define CNSS_CAL_DB_FILE_NAME "wlfw_cal_db.bin"
  59. #define CNSS_CAL_START_PROBE_WAIT_RETRY_MAX 100
  60. #define CNSS_CAL_START_PROBE_WAIT_MS 500
  61. enum cnss_cal_db_op {
  62. CNSS_CAL_DB_UPLOAD,
  63. CNSS_CAL_DB_DOWNLOAD,
  64. CNSS_CAL_DB_INVALID_OP,
  65. };
  66. static struct cnss_plat_data *plat_env;
  67. static DECLARE_RWSEM(cnss_pm_sem);
  68. static struct cnss_fw_files FW_FILES_QCA6174_FW_3_0 = {
  69. "qwlan30.bin", "bdwlan30.bin", "otp30.bin", "utf30.bin",
  70. "utfbd30.bin", "epping30.bin", "evicted30.bin"
  71. };
  72. static struct cnss_fw_files FW_FILES_DEFAULT = {
  73. "qwlan.bin", "bdwlan.bin", "otp.bin", "utf.bin",
  74. "utfbd.bin", "epping.bin", "evicted.bin"
  75. };
  76. struct cnss_driver_event {
  77. struct list_head list;
  78. enum cnss_driver_event_type type;
  79. bool sync;
  80. struct completion complete;
  81. int ret;
  82. void *data;
  83. };
  84. static void cnss_set_plat_priv(struct platform_device *plat_dev,
  85. struct cnss_plat_data *plat_priv)
  86. {
  87. plat_env = plat_priv;
  88. }
  89. struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev)
  90. {
  91. return plat_env;
  92. }
  93. /**
  94. * cnss_get_mem_seg_count - Get segment count of memory
  95. * @type: memory type
  96. * @seg: segment count
  97. *
  98. * Return: 0 on success, negative value on failure
  99. */
  100. int cnss_get_mem_seg_count(enum cnss_remote_mem_type type, u32 *seg)
  101. {
  102. struct cnss_plat_data *plat_priv;
  103. plat_priv = cnss_get_plat_priv(NULL);
  104. if (!plat_priv)
  105. return -ENODEV;
  106. switch (type) {
  107. case CNSS_REMOTE_MEM_TYPE_FW:
  108. *seg = plat_priv->fw_mem_seg_len;
  109. break;
  110. case CNSS_REMOTE_MEM_TYPE_QDSS:
  111. *seg = plat_priv->qdss_mem_seg_len;
  112. break;
  113. default:
  114. return -EINVAL;
  115. }
  116. return 0;
  117. }
  118. EXPORT_SYMBOL(cnss_get_mem_seg_count);
  119. /**
  120. * cnss_get_mem_segment_info - Get memory info of different type
  121. * @type: memory type
  122. * @segment: array to save the segment info
  123. * @seg: segment count
  124. *
  125. * Return: 0 on success, negative value on failure
  126. */
  127. int cnss_get_mem_segment_info(enum cnss_remote_mem_type type,
  128. struct cnss_mem_segment segment[],
  129. u32 segment_count)
  130. {
  131. struct cnss_plat_data *plat_priv;
  132. u32 i;
  133. plat_priv = cnss_get_plat_priv(NULL);
  134. if (!plat_priv)
  135. return -ENODEV;
  136. switch (type) {
  137. case CNSS_REMOTE_MEM_TYPE_FW:
  138. if (segment_count > plat_priv->fw_mem_seg_len)
  139. segment_count = plat_priv->fw_mem_seg_len;
  140. for (i = 0; i < segment_count; i++) {
  141. segment[i].size = plat_priv->fw_mem[i].size;
  142. segment[i].va = plat_priv->fw_mem[i].va;
  143. segment[i].pa = plat_priv->fw_mem[i].pa;
  144. }
  145. break;
  146. case CNSS_REMOTE_MEM_TYPE_QDSS:
  147. if (segment_count > plat_priv->qdss_mem_seg_len)
  148. segment_count = plat_priv->qdss_mem_seg_len;
  149. for (i = 0; i < segment_count; i++) {
  150. segment[i].size = plat_priv->qdss_mem[i].size;
  151. segment[i].va = plat_priv->qdss_mem[i].va;
  152. segment[i].pa = plat_priv->qdss_mem[i].pa;
  153. }
  154. break;
  155. default:
  156. return -EINVAL;
  157. }
  158. return 0;
  159. }
  160. EXPORT_SYMBOL(cnss_get_mem_segment_info);
  161. int cnss_set_feature_list(struct cnss_plat_data *plat_priv,
  162. enum cnss_feature_v01 feature)
  163. {
  164. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  165. return -EINVAL;
  166. plat_priv->feature_list |= 1 << feature;
  167. return 0;
  168. }
  169. int cnss_clear_feature_list(struct cnss_plat_data *plat_priv,
  170. enum cnss_feature_v01 feature)
  171. {
  172. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  173. return -EINVAL;
  174. plat_priv->feature_list &= ~(1 << feature);
  175. return 0;
  176. }
  177. int cnss_get_feature_list(struct cnss_plat_data *plat_priv,
  178. u64 *feature_list)
  179. {
  180. if (unlikely(!plat_priv))
  181. return -EINVAL;
  182. *feature_list = plat_priv->feature_list;
  183. return 0;
  184. }
  185. static int cnss_pm_notify(struct notifier_block *b,
  186. unsigned long event, void *p)
  187. {
  188. switch (event) {
  189. case PM_SUSPEND_PREPARE:
  190. down_write(&cnss_pm_sem);
  191. break;
  192. case PM_POST_SUSPEND:
  193. up_write(&cnss_pm_sem);
  194. break;
  195. }
  196. return NOTIFY_DONE;
  197. }
  198. static struct notifier_block cnss_pm_notifier = {
  199. .notifier_call = cnss_pm_notify,
  200. };
  201. void cnss_pm_stay_awake(struct cnss_plat_data *plat_priv)
  202. {
  203. if (atomic_inc_return(&plat_priv->pm_count) != 1)
  204. return;
  205. cnss_pr_dbg("PM stay awake, state: 0x%lx, count: %d\n",
  206. plat_priv->driver_state,
  207. atomic_read(&plat_priv->pm_count));
  208. pm_stay_awake(&plat_priv->plat_dev->dev);
  209. }
  210. void cnss_pm_relax(struct cnss_plat_data *plat_priv)
  211. {
  212. int r = atomic_dec_return(&plat_priv->pm_count);
  213. WARN_ON(r < 0);
  214. if (r != 0)
  215. return;
  216. cnss_pr_dbg("PM relax, state: 0x%lx, count: %d\n",
  217. plat_priv->driver_state,
  218. atomic_read(&plat_priv->pm_count));
  219. pm_relax(&plat_priv->plat_dev->dev);
  220. }
  221. void cnss_lock_pm_sem(struct device *dev)
  222. {
  223. down_read(&cnss_pm_sem);
  224. }
  225. EXPORT_SYMBOL(cnss_lock_pm_sem);
  226. void cnss_release_pm_sem(struct device *dev)
  227. {
  228. up_read(&cnss_pm_sem);
  229. }
  230. EXPORT_SYMBOL(cnss_release_pm_sem);
  231. int cnss_get_fw_files_for_target(struct device *dev,
  232. struct cnss_fw_files *pfw_files,
  233. u32 target_type, u32 target_version)
  234. {
  235. if (!pfw_files)
  236. return -ENODEV;
  237. switch (target_version) {
  238. case QCA6174_REV3_VERSION:
  239. case QCA6174_REV3_2_VERSION:
  240. memcpy(pfw_files, &FW_FILES_QCA6174_FW_3_0, sizeof(*pfw_files));
  241. break;
  242. default:
  243. memcpy(pfw_files, &FW_FILES_DEFAULT, sizeof(*pfw_files));
  244. cnss_pr_err("Unknown target version, type: 0x%X, version: 0x%X",
  245. target_type, target_version);
  246. break;
  247. }
  248. return 0;
  249. }
  250. EXPORT_SYMBOL(cnss_get_fw_files_for_target);
  251. int cnss_get_platform_cap(struct device *dev, struct cnss_platform_cap *cap)
  252. {
  253. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  254. if (!plat_priv)
  255. return -ENODEV;
  256. if (!cap)
  257. return -EINVAL;
  258. *cap = plat_priv->cap;
  259. cnss_pr_dbg("Platform cap_flag is 0x%x\n", cap->cap_flag);
  260. return 0;
  261. }
  262. EXPORT_SYMBOL(cnss_get_platform_cap);
  263. void cnss_request_pm_qos(struct device *dev, u32 qos_val)
  264. {
  265. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  266. if (!plat_priv)
  267. return;
  268. cpu_latency_qos_add_request(&plat_priv->qos_request, qos_val);
  269. }
  270. EXPORT_SYMBOL(cnss_request_pm_qos);
  271. void cnss_remove_pm_qos(struct device *dev)
  272. {
  273. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  274. if (!plat_priv)
  275. return;
  276. cpu_latency_qos_remove_request(&plat_priv->qos_request);
  277. }
  278. EXPORT_SYMBOL(cnss_remove_pm_qos);
  279. int cnss_wlan_enable(struct device *dev,
  280. struct cnss_wlan_enable_cfg *config,
  281. enum cnss_driver_mode mode,
  282. const char *host_version)
  283. {
  284. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  285. int ret = 0;
  286. if (!plat_priv)
  287. return -ENODEV;
  288. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  289. return 0;
  290. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  291. return 0;
  292. if (!config || !host_version) {
  293. cnss_pr_err("Invalid config or host_version pointer\n");
  294. return -EINVAL;
  295. }
  296. cnss_pr_dbg("Mode: %d, config: %pK, host_version: %s\n",
  297. mode, config, host_version);
  298. if (mode == CNSS_WALTEST || mode == CNSS_CCPM)
  299. goto skip_cfg;
  300. ret = cnss_wlfw_wlan_cfg_send_sync(plat_priv, config, host_version);
  301. if (ret)
  302. goto out;
  303. skip_cfg:
  304. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, mode);
  305. out:
  306. return ret;
  307. }
  308. EXPORT_SYMBOL(cnss_wlan_enable);
  309. int cnss_wlan_disable(struct device *dev, enum cnss_driver_mode mode)
  310. {
  311. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  312. int ret = 0;
  313. if (!plat_priv)
  314. return -ENODEV;
  315. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  316. return 0;
  317. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  318. return 0;
  319. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  320. cnss_bus_free_qdss_mem(plat_priv);
  321. return ret;
  322. }
  323. EXPORT_SYMBOL(cnss_wlan_disable);
  324. int cnss_athdiag_read(struct device *dev, u32 offset, u32 mem_type,
  325. u32 data_len, u8 *output)
  326. {
  327. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  328. int ret = 0;
  329. if (!plat_priv) {
  330. cnss_pr_err("plat_priv is NULL!\n");
  331. return -EINVAL;
  332. }
  333. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  334. return 0;
  335. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  336. cnss_pr_err("Invalid state for athdiag read: 0x%lx\n",
  337. plat_priv->driver_state);
  338. ret = -EINVAL;
  339. goto out;
  340. }
  341. ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, offset, mem_type,
  342. data_len, output);
  343. out:
  344. return ret;
  345. }
  346. EXPORT_SYMBOL(cnss_athdiag_read);
  347. int cnss_athdiag_write(struct device *dev, u32 offset, u32 mem_type,
  348. u32 data_len, u8 *input)
  349. {
  350. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  351. int ret = 0;
  352. if (!plat_priv) {
  353. cnss_pr_err("plat_priv is NULL!\n");
  354. return -EINVAL;
  355. }
  356. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  357. return 0;
  358. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  359. cnss_pr_err("Invalid state for athdiag write: 0x%lx\n",
  360. plat_priv->driver_state);
  361. ret = -EINVAL;
  362. goto out;
  363. }
  364. ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, offset, mem_type,
  365. data_len, input);
  366. out:
  367. return ret;
  368. }
  369. EXPORT_SYMBOL(cnss_athdiag_write);
  370. int cnss_set_fw_log_mode(struct device *dev, u8 fw_log_mode)
  371. {
  372. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  373. if (!plat_priv)
  374. return -ENODEV;
  375. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  376. return 0;
  377. return cnss_wlfw_ini_send_sync(plat_priv, fw_log_mode);
  378. }
  379. EXPORT_SYMBOL(cnss_set_fw_log_mode);
  380. int cnss_set_pcie_gen_speed(struct device *dev, u8 pcie_gen_speed)
  381. {
  382. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  383. if (!plat_priv)
  384. return -EINVAL;
  385. if (plat_priv->device_id != QCA6490_DEVICE_ID ||
  386. !plat_priv->fw_pcie_gen_switch)
  387. return -EOPNOTSUPP;
  388. if (pcie_gen_speed < QMI_PCIE_GEN_SPEED_1_V01 ||
  389. pcie_gen_speed > QMI_PCIE_GEN_SPEED_3_V01)
  390. return -EINVAL;
  391. cnss_pr_dbg("WLAN provided PCIE gen speed: %d\n", pcie_gen_speed);
  392. plat_priv->pcie_gen_speed = pcie_gen_speed;
  393. return 0;
  394. }
  395. EXPORT_SYMBOL(cnss_set_pcie_gen_speed);
  396. static int cnss_fw_mem_ready_hdlr(struct cnss_plat_data *plat_priv)
  397. {
  398. int ret = 0;
  399. if (!plat_priv)
  400. return -ENODEV;
  401. set_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  402. ret = cnss_wlfw_tgt_cap_send_sync(plat_priv);
  403. if (ret)
  404. goto out;
  405. if (plat_priv->hds_enabled)
  406. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_HDS);
  407. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_REGDB);
  408. ret = cnss_wlfw_bdf_dnld_send_sync(plat_priv,
  409. plat_priv->ctrl_params.bdf_type);
  410. if (ret)
  411. goto out;
  412. ret = cnss_bus_load_m3(plat_priv);
  413. if (ret)
  414. goto out;
  415. ret = cnss_wlfw_m3_dnld_send_sync(plat_priv);
  416. if (ret)
  417. goto out;
  418. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  419. return 0;
  420. out:
  421. return ret;
  422. }
  423. static int cnss_request_antenna_sharing(struct cnss_plat_data *plat_priv)
  424. {
  425. int ret = 0;
  426. if (!plat_priv->antenna) {
  427. ret = cnss_wlfw_antenna_switch_send_sync(plat_priv);
  428. if (ret)
  429. goto out;
  430. }
  431. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state)) {
  432. ret = coex_antenna_switch_to_wlan_send_sync_msg(plat_priv);
  433. if (ret)
  434. goto out;
  435. }
  436. ret = cnss_wlfw_antenna_grant_send_sync(plat_priv);
  437. if (ret)
  438. goto out;
  439. return 0;
  440. out:
  441. return ret;
  442. }
  443. static void cnss_release_antenna_sharing(struct cnss_plat_data *plat_priv)
  444. {
  445. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state))
  446. coex_antenna_switch_to_mdm_send_sync_msg(plat_priv);
  447. }
  448. static int cnss_setup_dms_mac(struct cnss_plat_data *plat_priv)
  449. {
  450. u32 i;
  451. int ret = 0;
  452. struct cnss_plat_ipc_daemon_config *cfg;
  453. ret = cnss_qmi_get_dms_mac(plat_priv);
  454. if (ret == 0 && plat_priv->dms.mac_valid)
  455. goto qmi_send;
  456. /* DTSI property use-nv-mac is used to force DMS MAC address for WLAN.
  457. * Thus assert on failure to get MAC from DMS even after retries
  458. */
  459. if (plat_priv->use_nv_mac) {
  460. /* Check if Daemon says platform support DMS MAC provisioning */
  461. cfg = cnss_plat_ipc_qmi_daemon_config();
  462. if (cfg) {
  463. if (!cfg->dms_mac_addr_supported) {
  464. cnss_pr_err("DMS MAC address not supported\n");
  465. CNSS_ASSERT(0);
  466. return -EINVAL;
  467. }
  468. }
  469. for (i = 0; i < CNSS_DMS_QMI_CONNECTION_WAIT_RETRY; i++) {
  470. if (plat_priv->dms.mac_valid)
  471. break;
  472. ret = cnss_qmi_get_dms_mac(plat_priv);
  473. if (ret == 0)
  474. break;
  475. msleep(CNSS_DMS_QMI_CONNECTION_WAIT_MS);
  476. }
  477. if (!plat_priv->dms.mac_valid) {
  478. cnss_pr_err("Unable to get MAC from DMS after retries\n");
  479. CNSS_ASSERT(0);
  480. return -EINVAL;
  481. }
  482. }
  483. qmi_send:
  484. if (plat_priv->dms.mac_valid)
  485. ret =
  486. cnss_wlfw_wlan_mac_req_send_sync(plat_priv, plat_priv->dms.mac,
  487. ARRAY_SIZE(plat_priv->dms.mac));
  488. return ret;
  489. }
  490. static int cnss_cal_db_mem_update(struct cnss_plat_data *plat_priv,
  491. enum cnss_cal_db_op op, u32 *size)
  492. {
  493. int ret = 0;
  494. u32 timeout = cnss_get_timeout(plat_priv,
  495. CNSS_TIMEOUT_DAEMON_CONNECTION);
  496. enum cnss_plat_ipc_qmi_client_id_v01 client_id =
  497. CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01;
  498. if (op >= CNSS_CAL_DB_INVALID_OP)
  499. return -EINVAL;
  500. if (!plat_priv->cbc_file_download) {
  501. cnss_pr_info("CAL DB file not required as per BDF\n");
  502. return 0;
  503. }
  504. if (*size == 0) {
  505. cnss_pr_err("Invalid cal file size\n");
  506. return -EINVAL;
  507. }
  508. if (!test_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state)) {
  509. cnss_pr_info("Waiting for CNSS Daemon connection\n");
  510. ret = wait_for_completion_timeout(&plat_priv->daemon_connected,
  511. msecs_to_jiffies(timeout));
  512. if (!ret) {
  513. cnss_pr_err("Daemon not yet connected\n");
  514. CNSS_ASSERT(0);
  515. return ret;
  516. }
  517. }
  518. if (!plat_priv->cal_mem->va) {
  519. cnss_pr_err("CAL DB Memory not setup for FW\n");
  520. return -EINVAL;
  521. }
  522. /* Copy CAL DB file contents to/from CAL_TYPE_DDR mem allocated to FW */
  523. if (op == CNSS_CAL_DB_DOWNLOAD) {
  524. cnss_pr_dbg("Initiating Calibration file download to mem\n");
  525. ret = cnss_plat_ipc_qmi_file_download(client_id,
  526. CNSS_CAL_DB_FILE_NAME,
  527. plat_priv->cal_mem->va,
  528. size);
  529. } else {
  530. cnss_pr_dbg("Initiating Calibration mem upload to file\n");
  531. ret = cnss_plat_ipc_qmi_file_upload(client_id,
  532. CNSS_CAL_DB_FILE_NAME,
  533. plat_priv->cal_mem->va,
  534. *size);
  535. }
  536. if (ret)
  537. cnss_pr_err("Cal DB file %s %s failure\n",
  538. CNSS_CAL_DB_FILE_NAME,
  539. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload");
  540. else
  541. cnss_pr_dbg("Cal DB file %s %s size %d done\n",
  542. CNSS_CAL_DB_FILE_NAME,
  543. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload",
  544. *size);
  545. return ret;
  546. }
  547. static int cnss_cal_mem_upload_to_file(struct cnss_plat_data *plat_priv)
  548. {
  549. if (plat_priv->cal_file_size > plat_priv->cal_mem->size) {
  550. cnss_pr_err("Cal file size is larger than Cal DB Mem size\n");
  551. return -EINVAL;
  552. }
  553. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_UPLOAD,
  554. &plat_priv->cal_file_size);
  555. }
  556. static int cnss_cal_file_download_to_mem(struct cnss_plat_data *plat_priv,
  557. u32 *cal_file_size)
  558. {
  559. /* To download pass the total size of cal DB mem allocated.
  560. * After cal file is download to mem, its size is updated in
  561. * return pointer
  562. */
  563. *cal_file_size = plat_priv->cal_mem->size;
  564. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_DOWNLOAD,
  565. cal_file_size);
  566. }
  567. static int cnss_fw_ready_hdlr(struct cnss_plat_data *plat_priv)
  568. {
  569. int ret = 0;
  570. u32 cal_file_size = 0;
  571. if (!plat_priv)
  572. return -ENODEV;
  573. cnss_pr_dbg("Processing FW Init Done..\n");
  574. del_timer(&plat_priv->fw_boot_timer);
  575. set_bit(CNSS_FW_READY, &plat_priv->driver_state);
  576. clear_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state);
  577. cnss_wlfw_send_pcie_gen_speed_sync(plat_priv);
  578. if (test_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state)) {
  579. clear_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state);
  580. clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  581. }
  582. if (test_bit(ENABLE_WALTEST, &plat_priv->ctrl_params.quirks)) {
  583. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  584. CNSS_WALTEST);
  585. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  586. cnss_request_antenna_sharing(plat_priv);
  587. cnss_cal_file_download_to_mem(plat_priv, &cal_file_size);
  588. cnss_wlfw_cal_report_req_send_sync(plat_priv, cal_file_size);
  589. plat_priv->cal_time = jiffies;
  590. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  591. CNSS_CALIBRATION);
  592. } else {
  593. ret = cnss_setup_dms_mac(plat_priv);
  594. ret = cnss_bus_call_driver_probe(plat_priv);
  595. }
  596. if (ret && test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  597. goto out;
  598. else if (ret)
  599. goto shutdown;
  600. cnss_vreg_unvote_type(plat_priv, CNSS_VREG_PRIM);
  601. return 0;
  602. shutdown:
  603. cnss_bus_dev_shutdown(plat_priv);
  604. clear_bit(CNSS_FW_READY, &plat_priv->driver_state);
  605. clear_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  606. out:
  607. return ret;
  608. }
  609. static char *cnss_driver_event_to_str(enum cnss_driver_event_type type)
  610. {
  611. switch (type) {
  612. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  613. return "SERVER_ARRIVE";
  614. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  615. return "SERVER_EXIT";
  616. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  617. return "REQUEST_MEM";
  618. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  619. return "FW_MEM_READY";
  620. case CNSS_DRIVER_EVENT_FW_READY:
  621. return "FW_READY";
  622. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  623. return "COLD_BOOT_CAL_START";
  624. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  625. return "COLD_BOOT_CAL_DONE";
  626. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  627. return "REGISTER_DRIVER";
  628. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  629. return "UNREGISTER_DRIVER";
  630. case CNSS_DRIVER_EVENT_RECOVERY:
  631. return "RECOVERY";
  632. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  633. return "FORCE_FW_ASSERT";
  634. case CNSS_DRIVER_EVENT_POWER_UP:
  635. return "POWER_UP";
  636. case CNSS_DRIVER_EVENT_POWER_DOWN:
  637. return "POWER_DOWN";
  638. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  639. return "IDLE_RESTART";
  640. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  641. return "IDLE_SHUTDOWN";
  642. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  643. return "IMS_WFC_CALL_IND";
  644. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  645. return "WLFW_TWC_CFG_IND";
  646. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  647. return "QDSS_TRACE_REQ_MEM";
  648. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  649. return "FW_MEM_FILE_SAVE";
  650. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  651. return "QDSS_TRACE_FREE";
  652. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  653. return "QDSS_TRACE_REQ_DATA";
  654. case CNSS_DRIVER_EVENT_MAX:
  655. return "EVENT_MAX";
  656. }
  657. return "UNKNOWN";
  658. };
  659. int cnss_driver_event_post(struct cnss_plat_data *plat_priv,
  660. enum cnss_driver_event_type type,
  661. u32 flags, void *data)
  662. {
  663. struct cnss_driver_event *event;
  664. unsigned long irq_flags;
  665. int gfp = GFP_KERNEL;
  666. int ret = 0;
  667. if (!plat_priv)
  668. return -ENODEV;
  669. cnss_pr_dbg("Posting event: %s(%d)%s, state: 0x%lx flags: 0x%0x\n",
  670. cnss_driver_event_to_str(type), type,
  671. flags ? "-sync" : "", plat_priv->driver_state, flags);
  672. if (type >= CNSS_DRIVER_EVENT_MAX) {
  673. cnss_pr_err("Invalid Event type: %d, can't post", type);
  674. return -EINVAL;
  675. }
  676. if (in_interrupt() || irqs_disabled())
  677. gfp = GFP_ATOMIC;
  678. event = kzalloc(sizeof(*event), gfp);
  679. if (!event)
  680. return -ENOMEM;
  681. cnss_pm_stay_awake(plat_priv);
  682. event->type = type;
  683. event->data = data;
  684. init_completion(&event->complete);
  685. event->ret = CNSS_EVENT_PENDING;
  686. event->sync = !!(flags & CNSS_EVENT_SYNC);
  687. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  688. list_add_tail(&event->list, &plat_priv->event_list);
  689. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  690. queue_work(plat_priv->event_wq, &plat_priv->event_work);
  691. if (!(flags & CNSS_EVENT_SYNC))
  692. goto out;
  693. if (flags & CNSS_EVENT_UNKILLABLE)
  694. wait_for_completion(&event->complete);
  695. else if (flags & CNSS_EVENT_UNINTERRUPTIBLE)
  696. ret = wait_for_completion_killable(&event->complete);
  697. else
  698. ret = wait_for_completion_interruptible(&event->complete);
  699. cnss_pr_dbg("Completed event: %s(%d), state: 0x%lx, ret: %d/%d\n",
  700. cnss_driver_event_to_str(type), type,
  701. plat_priv->driver_state, ret, event->ret);
  702. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  703. if (ret == -ERESTARTSYS && event->ret == CNSS_EVENT_PENDING) {
  704. event->sync = false;
  705. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  706. ret = -EINTR;
  707. goto out;
  708. }
  709. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  710. ret = event->ret;
  711. kfree(event);
  712. out:
  713. cnss_pm_relax(plat_priv);
  714. return ret;
  715. }
  716. /**
  717. * cnss_get_timeout - Get timeout for corresponding type.
  718. * @plat_priv: Pointer to platform driver context.
  719. * @cnss_timeout_type: Timeout type.
  720. *
  721. * Return: Timeout in milliseconds.
  722. */
  723. unsigned int cnss_get_timeout(struct cnss_plat_data *plat_priv,
  724. enum cnss_timeout_type timeout_type)
  725. {
  726. unsigned int qmi_timeout = cnss_get_qmi_timeout(plat_priv);
  727. switch (timeout_type) {
  728. case CNSS_TIMEOUT_QMI:
  729. return qmi_timeout;
  730. case CNSS_TIMEOUT_POWER_UP:
  731. return (qmi_timeout << 2);
  732. case CNSS_TIMEOUT_IDLE_RESTART:
  733. /* In idle restart power up sequence, we have fw_boot_timer to
  734. * handle FW initialization failure.
  735. * It uses WLAN_MISSION_MODE_TIMEOUT, so setup 3x that time to
  736. * account for FW dump collection and FW re-initialization on
  737. * retry.
  738. */
  739. return (qmi_timeout + WLAN_MISSION_MODE_TIMEOUT * 3);
  740. case CNSS_TIMEOUT_CALIBRATION:
  741. /* Similar to mission mode, in CBC if FW init fails
  742. * fw recovery is tried. Thus return 2x the CBC timeout.
  743. */
  744. return (qmi_timeout + WLAN_COLD_BOOT_CAL_TIMEOUT * 2);
  745. case CNSS_TIMEOUT_WLAN_WATCHDOG:
  746. return ((qmi_timeout << 1) + WLAN_WD_TIMEOUT_MS);
  747. case CNSS_TIMEOUT_RDDM:
  748. return CNSS_RDDM_TIMEOUT_MS;
  749. case CNSS_TIMEOUT_RECOVERY:
  750. return RECOVERY_TIMEOUT;
  751. case CNSS_TIMEOUT_DAEMON_CONNECTION:
  752. return qmi_timeout + CNSS_DAEMON_CONNECT_TIMEOUT_MS;
  753. default:
  754. return qmi_timeout;
  755. }
  756. }
  757. unsigned int cnss_get_boot_timeout(struct device *dev)
  758. {
  759. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  760. if (!plat_priv) {
  761. cnss_pr_err("plat_priv is NULL\n");
  762. return 0;
  763. }
  764. return cnss_get_timeout(plat_priv, CNSS_TIMEOUT_QMI);
  765. }
  766. EXPORT_SYMBOL(cnss_get_boot_timeout);
  767. int cnss_power_up(struct device *dev)
  768. {
  769. int ret = 0;
  770. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  771. unsigned int timeout;
  772. if (!plat_priv) {
  773. cnss_pr_err("plat_priv is NULL\n");
  774. return -ENODEV;
  775. }
  776. cnss_pr_dbg("Powering up device\n");
  777. ret = cnss_driver_event_post(plat_priv,
  778. CNSS_DRIVER_EVENT_POWER_UP,
  779. CNSS_EVENT_SYNC, NULL);
  780. if (ret)
  781. goto out;
  782. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  783. goto out;
  784. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_POWER_UP);
  785. reinit_completion(&plat_priv->power_up_complete);
  786. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  787. msecs_to_jiffies(timeout));
  788. if (!ret) {
  789. cnss_pr_err("Timeout (%ums) waiting for power up to complete\n",
  790. timeout);
  791. ret = -EAGAIN;
  792. goto out;
  793. }
  794. return 0;
  795. out:
  796. return ret;
  797. }
  798. EXPORT_SYMBOL(cnss_power_up);
  799. int cnss_power_down(struct device *dev)
  800. {
  801. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  802. if (!plat_priv) {
  803. cnss_pr_err("plat_priv is NULL\n");
  804. return -ENODEV;
  805. }
  806. cnss_pr_dbg("Powering down device\n");
  807. return cnss_driver_event_post(plat_priv,
  808. CNSS_DRIVER_EVENT_POWER_DOWN,
  809. CNSS_EVENT_SYNC, NULL);
  810. }
  811. EXPORT_SYMBOL(cnss_power_down);
  812. int cnss_idle_restart(struct device *dev)
  813. {
  814. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  815. unsigned int timeout;
  816. int ret = 0;
  817. if (!plat_priv) {
  818. cnss_pr_err("plat_priv is NULL\n");
  819. return -ENODEV;
  820. }
  821. if (!mutex_trylock(&plat_priv->driver_ops_lock)) {
  822. cnss_pr_dbg("Another driver operation is in progress, ignore idle restart\n");
  823. return -EBUSY;
  824. }
  825. cnss_pr_dbg("Doing idle restart\n");
  826. reinit_completion(&plat_priv->power_up_complete);
  827. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  828. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  829. ret = -EINVAL;
  830. goto out;
  831. }
  832. ret = cnss_driver_event_post(plat_priv,
  833. CNSS_DRIVER_EVENT_IDLE_RESTART,
  834. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  835. if (ret)
  836. goto out;
  837. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  838. ret = cnss_bus_call_driver_probe(plat_priv);
  839. goto out;
  840. }
  841. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_IDLE_RESTART);
  842. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  843. msecs_to_jiffies(timeout));
  844. if (plat_priv->power_up_error) {
  845. ret = plat_priv->power_up_error;
  846. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  847. cnss_pr_dbg("Power up error:%d, exiting\n",
  848. plat_priv->power_up_error);
  849. goto out;
  850. }
  851. if (!ret) {
  852. /* This exception occurs after attempting retry of FW recovery.
  853. * Thus we can safely power off the device.
  854. */
  855. cnss_fatal_err("Timeout (%ums) waiting for idle restart to complete\n",
  856. timeout);
  857. ret = -ETIMEDOUT;
  858. cnss_power_down(dev);
  859. CNSS_ASSERT(0);
  860. goto out;
  861. }
  862. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  863. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  864. del_timer(&plat_priv->fw_boot_timer);
  865. ret = -EINVAL;
  866. goto out;
  867. }
  868. mutex_unlock(&plat_priv->driver_ops_lock);
  869. return 0;
  870. out:
  871. mutex_unlock(&plat_priv->driver_ops_lock);
  872. return ret;
  873. }
  874. EXPORT_SYMBOL(cnss_idle_restart);
  875. int cnss_idle_shutdown(struct device *dev)
  876. {
  877. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  878. unsigned int timeout;
  879. int ret;
  880. if (!plat_priv) {
  881. cnss_pr_err("plat_priv is NULL\n");
  882. return -ENODEV;
  883. }
  884. if (test_bit(CNSS_IN_SUSPEND_RESUME, &plat_priv->driver_state)) {
  885. cnss_pr_dbg("System suspend or resume in progress, ignore idle shutdown\n");
  886. return -EAGAIN;
  887. }
  888. cnss_pr_dbg("Doing idle shutdown\n");
  889. if (!test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state) &&
  890. !test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  891. goto skip_wait;
  892. reinit_completion(&plat_priv->recovery_complete);
  893. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RECOVERY);
  894. ret = wait_for_completion_timeout(&plat_priv->recovery_complete,
  895. msecs_to_jiffies(timeout));
  896. if (!ret) {
  897. cnss_pr_err("Timeout (%ums) waiting for recovery to complete\n",
  898. timeout);
  899. CNSS_ASSERT(0);
  900. }
  901. skip_wait:
  902. return cnss_driver_event_post(plat_priv,
  903. CNSS_DRIVER_EVENT_IDLE_SHUTDOWN,
  904. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  905. }
  906. EXPORT_SYMBOL(cnss_idle_shutdown);
  907. static int cnss_get_resources(struct cnss_plat_data *plat_priv)
  908. {
  909. int ret = 0;
  910. ret = cnss_get_vreg_type(plat_priv, CNSS_VREG_PRIM);
  911. if (ret) {
  912. cnss_pr_err("Failed to get vreg, err = %d\n", ret);
  913. goto out;
  914. }
  915. ret = cnss_get_clk(plat_priv);
  916. if (ret) {
  917. cnss_pr_err("Failed to get clocks, err = %d\n", ret);
  918. goto put_vreg;
  919. }
  920. ret = cnss_get_pinctrl(plat_priv);
  921. if (ret) {
  922. cnss_pr_err("Failed to get pinctrl, err = %d\n", ret);
  923. goto put_clk;
  924. }
  925. return 0;
  926. put_clk:
  927. cnss_put_clk(plat_priv);
  928. put_vreg:
  929. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  930. out:
  931. return ret;
  932. }
  933. static void cnss_put_resources(struct cnss_plat_data *plat_priv)
  934. {
  935. cnss_put_clk(plat_priv);
  936. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  937. }
  938. #if IS_ENABLED(CONFIG_ESOC) && IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  939. static int cnss_modem_notifier_nb(struct notifier_block *nb,
  940. unsigned long code,
  941. void *ss_handle)
  942. {
  943. struct cnss_plat_data *plat_priv =
  944. container_of(nb, struct cnss_plat_data, modem_nb);
  945. struct cnss_esoc_info *esoc_info;
  946. cnss_pr_dbg("Modem notifier: event %lu\n", code);
  947. if (!plat_priv)
  948. return NOTIFY_DONE;
  949. esoc_info = &plat_priv->esoc_info;
  950. if (code == SUBSYS_AFTER_POWERUP)
  951. esoc_info->modem_current_status = 1;
  952. else if (code == SUBSYS_BEFORE_SHUTDOWN)
  953. esoc_info->modem_current_status = 0;
  954. else
  955. return NOTIFY_DONE;
  956. if (!cnss_bus_call_driver_modem_status(plat_priv,
  957. esoc_info->modem_current_status))
  958. return NOTIFY_DONE;
  959. return NOTIFY_OK;
  960. }
  961. static int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  962. {
  963. int ret = 0;
  964. struct device *dev;
  965. struct cnss_esoc_info *esoc_info;
  966. struct esoc_desc *esoc_desc;
  967. const char *client_desc;
  968. dev = &plat_priv->plat_dev->dev;
  969. esoc_info = &plat_priv->esoc_info;
  970. esoc_info->notify_modem_status =
  971. of_property_read_bool(dev->of_node,
  972. "qcom,notify-modem-status");
  973. if (!esoc_info->notify_modem_status)
  974. goto out;
  975. ret = of_property_read_string_index(dev->of_node, "esoc-names", 0,
  976. &client_desc);
  977. if (ret) {
  978. cnss_pr_dbg("esoc-names is not defined in DT, skip!\n");
  979. } else {
  980. esoc_desc = devm_register_esoc_client(dev, client_desc);
  981. if (IS_ERR_OR_NULL(esoc_desc)) {
  982. ret = PTR_RET(esoc_desc);
  983. cnss_pr_err("Failed to register esoc_desc, err = %d\n",
  984. ret);
  985. goto out;
  986. }
  987. esoc_info->esoc_desc = esoc_desc;
  988. }
  989. plat_priv->modem_nb.notifier_call = cnss_modem_notifier_nb;
  990. esoc_info->modem_current_status = 0;
  991. esoc_info->modem_notify_handler =
  992. subsys_notif_register_notifier(esoc_info->esoc_desc ?
  993. esoc_info->esoc_desc->name :
  994. "modem", &plat_priv->modem_nb);
  995. if (IS_ERR(esoc_info->modem_notify_handler)) {
  996. ret = PTR_ERR(esoc_info->modem_notify_handler);
  997. cnss_pr_err("Failed to register esoc notifier, err = %d\n",
  998. ret);
  999. goto unreg_esoc;
  1000. }
  1001. return 0;
  1002. unreg_esoc:
  1003. if (esoc_info->esoc_desc)
  1004. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1005. out:
  1006. return ret;
  1007. }
  1008. static void cnss_unregister_esoc(struct cnss_plat_data *plat_priv)
  1009. {
  1010. struct device *dev;
  1011. struct cnss_esoc_info *esoc_info;
  1012. dev = &plat_priv->plat_dev->dev;
  1013. esoc_info = &plat_priv->esoc_info;
  1014. if (esoc_info->notify_modem_status)
  1015. subsys_notif_unregister_notifier
  1016. (esoc_info->modem_notify_handler,
  1017. &plat_priv->modem_nb);
  1018. if (esoc_info->esoc_desc)
  1019. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1020. }
  1021. #else
  1022. static inline int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  1023. {
  1024. return 0;
  1025. }
  1026. static inline void cnss_unregister_esoc(struct cnss_plat_data *plat_priv) {}
  1027. #endif
  1028. int cnss_enable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1029. {
  1030. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1031. int ret = 0;
  1032. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1033. return 0;
  1034. enable_irq(sol_gpio->dev_sol_irq);
  1035. ret = enable_irq_wake(sol_gpio->dev_sol_irq);
  1036. if (ret)
  1037. cnss_pr_err("Failed to enable device SOL as wake IRQ, err = %d\n",
  1038. ret);
  1039. return ret;
  1040. }
  1041. int cnss_disable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1042. {
  1043. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1044. int ret = 0;
  1045. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1046. return 0;
  1047. ret = disable_irq_wake(sol_gpio->dev_sol_irq);
  1048. if (ret)
  1049. cnss_pr_err("Failed to disable device SOL as wake IRQ, err = %d\n",
  1050. ret);
  1051. disable_irq(sol_gpio->dev_sol_irq);
  1052. return ret;
  1053. }
  1054. int cnss_get_dev_sol_value(struct cnss_plat_data *plat_priv)
  1055. {
  1056. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1057. if (sol_gpio->dev_sol_gpio < 0)
  1058. return -EINVAL;
  1059. return gpio_get_value(sol_gpio->dev_sol_gpio);
  1060. }
  1061. static irqreturn_t cnss_dev_sol_handler(int irq, void *data)
  1062. {
  1063. struct cnss_plat_data *plat_priv = data;
  1064. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1065. sol_gpio->dev_sol_counter++;
  1066. cnss_pr_dbg("WLAN device SOL IRQ (%u) is asserted #%u\n",
  1067. irq, sol_gpio->dev_sol_counter);
  1068. /* Make sure abort current suspend */
  1069. cnss_pm_stay_awake(plat_priv);
  1070. cnss_pm_relax(plat_priv);
  1071. pm_system_wakeup();
  1072. cnss_bus_handle_dev_sol_irq(plat_priv);
  1073. return IRQ_HANDLED;
  1074. }
  1075. static int cnss_init_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1076. {
  1077. struct device *dev = &plat_priv->plat_dev->dev;
  1078. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1079. int ret = 0;
  1080. sol_gpio->dev_sol_gpio = of_get_named_gpio(dev->of_node,
  1081. "wlan-dev-sol-gpio", 0);
  1082. if (sol_gpio->dev_sol_gpio < 0)
  1083. goto out;
  1084. cnss_pr_dbg("Get device SOL GPIO (%d) from device node\n",
  1085. sol_gpio->dev_sol_gpio);
  1086. ret = gpio_request(sol_gpio->dev_sol_gpio, "wlan_dev_sol_gpio");
  1087. if (ret) {
  1088. cnss_pr_err("Failed to request device SOL GPIO, err = %d\n",
  1089. ret);
  1090. goto out;
  1091. }
  1092. gpio_direction_input(sol_gpio->dev_sol_gpio);
  1093. sol_gpio->dev_sol_irq = gpio_to_irq(sol_gpio->dev_sol_gpio);
  1094. ret = request_irq(sol_gpio->dev_sol_irq, cnss_dev_sol_handler,
  1095. IRQF_TRIGGER_FALLING, "wlan_dev_sol_irq", plat_priv);
  1096. if (ret) {
  1097. cnss_pr_err("Failed to request device SOL IRQ, err = %d\n", ret);
  1098. goto free_gpio;
  1099. }
  1100. return 0;
  1101. free_gpio:
  1102. gpio_free(sol_gpio->dev_sol_gpio);
  1103. out:
  1104. return ret;
  1105. }
  1106. static void cnss_deinit_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1107. {
  1108. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1109. if (sol_gpio->dev_sol_gpio < 0)
  1110. return;
  1111. free_irq(sol_gpio->dev_sol_irq, plat_priv);
  1112. gpio_free(sol_gpio->dev_sol_gpio);
  1113. }
  1114. int cnss_set_host_sol_value(struct cnss_plat_data *plat_priv, int value)
  1115. {
  1116. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1117. if (sol_gpio->host_sol_gpio < 0)
  1118. return -EINVAL;
  1119. if (value)
  1120. cnss_pr_dbg("Assert host SOL GPIO\n");
  1121. gpio_set_value(sol_gpio->host_sol_gpio, value);
  1122. return 0;
  1123. }
  1124. int cnss_get_host_sol_value(struct cnss_plat_data *plat_priv)
  1125. {
  1126. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1127. if (sol_gpio->host_sol_gpio < 0)
  1128. return -EINVAL;
  1129. return gpio_get_value(sol_gpio->host_sol_gpio);
  1130. }
  1131. static int cnss_init_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1132. {
  1133. struct device *dev = &plat_priv->plat_dev->dev;
  1134. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1135. int ret = 0;
  1136. sol_gpio->host_sol_gpio = of_get_named_gpio(dev->of_node,
  1137. "wlan-host-sol-gpio", 0);
  1138. if (sol_gpio->host_sol_gpio < 0)
  1139. goto out;
  1140. cnss_pr_dbg("Get host SOL GPIO (%d) from device node\n",
  1141. sol_gpio->host_sol_gpio);
  1142. ret = gpio_request(sol_gpio->host_sol_gpio, "wlan_host_sol_gpio");
  1143. if (ret) {
  1144. cnss_pr_err("Failed to request host SOL GPIO, err = %d\n",
  1145. ret);
  1146. goto out;
  1147. }
  1148. gpio_direction_output(sol_gpio->host_sol_gpio, 0);
  1149. return 0;
  1150. out:
  1151. return ret;
  1152. }
  1153. static void cnss_deinit_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1154. {
  1155. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1156. if (sol_gpio->host_sol_gpio < 0)
  1157. return;
  1158. gpio_free(sol_gpio->host_sol_gpio);
  1159. }
  1160. static int cnss_init_sol_gpio(struct cnss_plat_data *plat_priv)
  1161. {
  1162. int ret;
  1163. ret = cnss_init_dev_sol_gpio(plat_priv);
  1164. if (ret)
  1165. goto out;
  1166. ret = cnss_init_host_sol_gpio(plat_priv);
  1167. if (ret)
  1168. goto deinit_dev_sol;
  1169. return 0;
  1170. deinit_dev_sol:
  1171. cnss_deinit_dev_sol_gpio(plat_priv);
  1172. out:
  1173. return ret;
  1174. }
  1175. static void cnss_deinit_sol_gpio(struct cnss_plat_data *plat_priv)
  1176. {
  1177. cnss_deinit_host_sol_gpio(plat_priv);
  1178. cnss_deinit_dev_sol_gpio(plat_priv);
  1179. }
  1180. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1181. static int cnss_subsys_powerup(const struct subsys_desc *subsys_desc)
  1182. {
  1183. struct cnss_plat_data *plat_priv;
  1184. int ret = 0;
  1185. if (!subsys_desc->dev) {
  1186. cnss_pr_err("dev from subsys_desc is NULL\n");
  1187. return -ENODEV;
  1188. }
  1189. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1190. if (!plat_priv) {
  1191. cnss_pr_err("plat_priv is NULL\n");
  1192. return -ENODEV;
  1193. }
  1194. if (!plat_priv->driver_state) {
  1195. cnss_pr_dbg("Powerup is ignored\n");
  1196. return 0;
  1197. }
  1198. ret = cnss_bus_dev_powerup(plat_priv);
  1199. if (ret)
  1200. __pm_relax(plat_priv->recovery_ws);
  1201. return ret;
  1202. }
  1203. static int cnss_subsys_shutdown(const struct subsys_desc *subsys_desc,
  1204. bool force_stop)
  1205. {
  1206. struct cnss_plat_data *plat_priv;
  1207. if (!subsys_desc->dev) {
  1208. cnss_pr_err("dev from subsys_desc is NULL\n");
  1209. return -ENODEV;
  1210. }
  1211. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1212. if (!plat_priv) {
  1213. cnss_pr_err("plat_priv is NULL\n");
  1214. return -ENODEV;
  1215. }
  1216. if (!plat_priv->driver_state) {
  1217. cnss_pr_dbg("shutdown is ignored\n");
  1218. return 0;
  1219. }
  1220. return cnss_bus_dev_shutdown(plat_priv);
  1221. }
  1222. void cnss_device_crashed(struct device *dev)
  1223. {
  1224. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1225. struct cnss_subsys_info *subsys_info;
  1226. if (!plat_priv)
  1227. return;
  1228. subsys_info = &plat_priv->subsys_info;
  1229. if (subsys_info->subsys_device) {
  1230. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1231. subsys_set_crash_status(subsys_info->subsys_device, true);
  1232. subsystem_restart_dev(subsys_info->subsys_device);
  1233. }
  1234. }
  1235. EXPORT_SYMBOL(cnss_device_crashed);
  1236. static void cnss_subsys_crash_shutdown(const struct subsys_desc *subsys_desc)
  1237. {
  1238. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1239. if (!plat_priv) {
  1240. cnss_pr_err("plat_priv is NULL\n");
  1241. return;
  1242. }
  1243. cnss_bus_dev_crash_shutdown(plat_priv);
  1244. }
  1245. static int cnss_subsys_ramdump(int enable,
  1246. const struct subsys_desc *subsys_desc)
  1247. {
  1248. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1249. if (!plat_priv) {
  1250. cnss_pr_err("plat_priv is NULL\n");
  1251. return -ENODEV;
  1252. }
  1253. if (!enable)
  1254. return 0;
  1255. return cnss_bus_dev_ramdump(plat_priv);
  1256. }
  1257. static void cnss_recovery_work_handler(struct work_struct *work)
  1258. {
  1259. }
  1260. #else
  1261. static void cnss_recovery_work_handler(struct work_struct *work)
  1262. {
  1263. int ret;
  1264. struct cnss_plat_data *plat_priv =
  1265. container_of(work, struct cnss_plat_data, recovery_work);
  1266. if (!plat_priv->recovery_enabled)
  1267. panic("subsys-restart: Resetting the SoC wlan crashed\n");
  1268. cnss_bus_dev_shutdown(plat_priv);
  1269. cnss_bus_dev_ramdump(plat_priv);
  1270. msleep(POWER_RESET_MIN_DELAY_MS);
  1271. ret = cnss_bus_dev_powerup(plat_priv);
  1272. if (ret)
  1273. __pm_relax(plat_priv->recovery_ws);
  1274. return;
  1275. }
  1276. void cnss_device_crashed(struct device *dev)
  1277. {
  1278. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1279. if (!plat_priv)
  1280. return;
  1281. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1282. schedule_work(&plat_priv->recovery_work);
  1283. }
  1284. EXPORT_SYMBOL(cnss_device_crashed);
  1285. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  1286. void *cnss_get_virt_ramdump_mem(struct device *dev, unsigned long *size)
  1287. {
  1288. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1289. struct cnss_ramdump_info *ramdump_info;
  1290. if (!plat_priv)
  1291. return NULL;
  1292. ramdump_info = &plat_priv->ramdump_info;
  1293. *size = ramdump_info->ramdump_size;
  1294. return ramdump_info->ramdump_va;
  1295. }
  1296. EXPORT_SYMBOL(cnss_get_virt_ramdump_mem);
  1297. static const char *cnss_recovery_reason_to_str(enum cnss_recovery_reason reason)
  1298. {
  1299. switch (reason) {
  1300. case CNSS_REASON_DEFAULT:
  1301. return "DEFAULT";
  1302. case CNSS_REASON_LINK_DOWN:
  1303. return "LINK_DOWN";
  1304. case CNSS_REASON_RDDM:
  1305. return "RDDM";
  1306. case CNSS_REASON_TIMEOUT:
  1307. return "TIMEOUT";
  1308. }
  1309. return "UNKNOWN";
  1310. };
  1311. static int cnss_do_recovery(struct cnss_plat_data *plat_priv,
  1312. enum cnss_recovery_reason reason)
  1313. {
  1314. plat_priv->recovery_count++;
  1315. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  1316. goto self_recovery;
  1317. if (test_bit(SKIP_RECOVERY, &plat_priv->ctrl_params.quirks)) {
  1318. cnss_pr_dbg("Skip device recovery\n");
  1319. return 0;
  1320. }
  1321. /* FW recovery sequence has multiple steps and firmware load requires
  1322. * linux PM in awake state. Thus hold the cnss wake source until
  1323. * WLAN MISSION enabled. CNSS_TIMEOUT_RECOVERY option should cover all
  1324. * time taken in this process.
  1325. */
  1326. pm_wakeup_ws_event(plat_priv->recovery_ws,
  1327. cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RECOVERY),
  1328. true);
  1329. switch (reason) {
  1330. case CNSS_REASON_LINK_DOWN:
  1331. if (!cnss_bus_check_link_status(plat_priv)) {
  1332. cnss_pr_dbg("Skip link down recovery as link is already up\n");
  1333. return 0;
  1334. }
  1335. if (test_bit(LINK_DOWN_SELF_RECOVERY,
  1336. &plat_priv->ctrl_params.quirks))
  1337. goto self_recovery;
  1338. if (!cnss_bus_recover_link_down(plat_priv)) {
  1339. /* clear recovery bit here to avoid skipping
  1340. * the recovery work for RDDM later
  1341. */
  1342. clear_bit(CNSS_DRIVER_RECOVERY,
  1343. &plat_priv->driver_state);
  1344. return 0;
  1345. }
  1346. break;
  1347. case CNSS_REASON_RDDM:
  1348. cnss_bus_collect_dump_info(plat_priv, false);
  1349. break;
  1350. case CNSS_REASON_DEFAULT:
  1351. case CNSS_REASON_TIMEOUT:
  1352. break;
  1353. default:
  1354. cnss_pr_err("Unsupported recovery reason: %s(%d)\n",
  1355. cnss_recovery_reason_to_str(reason), reason);
  1356. break;
  1357. }
  1358. cnss_bus_device_crashed(plat_priv);
  1359. return 0;
  1360. self_recovery:
  1361. cnss_pr_dbg("Going for self recovery\n");
  1362. cnss_bus_dev_shutdown(plat_priv);
  1363. if (test_bit(LINK_DOWN_SELF_RECOVERY, &plat_priv->ctrl_params.quirks))
  1364. clear_bit(LINK_DOWN_SELF_RECOVERY,
  1365. &plat_priv->ctrl_params.quirks);
  1366. cnss_bus_dev_powerup(plat_priv);
  1367. return 0;
  1368. }
  1369. static int cnss_driver_recovery_hdlr(struct cnss_plat_data *plat_priv,
  1370. void *data)
  1371. {
  1372. struct cnss_recovery_data *recovery_data = data;
  1373. int ret = 0;
  1374. cnss_pr_dbg("Driver recovery is triggered with reason: %s(%d)\n",
  1375. cnss_recovery_reason_to_str(recovery_data->reason),
  1376. recovery_data->reason);
  1377. if (!plat_priv->driver_state) {
  1378. cnss_pr_err("Improper driver state, ignore recovery\n");
  1379. ret = -EINVAL;
  1380. goto out;
  1381. }
  1382. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1383. cnss_pr_err("Reboot is in progress, ignore recovery\n");
  1384. ret = -EINVAL;
  1385. goto out;
  1386. }
  1387. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1388. cnss_pr_err("Recovery is already in progress\n");
  1389. CNSS_ASSERT(0);
  1390. ret = -EINVAL;
  1391. goto out;
  1392. }
  1393. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1394. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1395. cnss_pr_err("Driver unload or idle shutdown is in progress, ignore recovery\n");
  1396. ret = -EINVAL;
  1397. goto out;
  1398. }
  1399. switch (plat_priv->device_id) {
  1400. case QCA6174_DEVICE_ID:
  1401. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1402. test_bit(CNSS_DRIVER_IDLE_RESTART,
  1403. &plat_priv->driver_state)) {
  1404. cnss_pr_err("Driver load or idle restart is in progress, ignore recovery\n");
  1405. ret = -EINVAL;
  1406. goto out;
  1407. }
  1408. break;
  1409. default:
  1410. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1411. set_bit(CNSS_FW_BOOT_RECOVERY,
  1412. &plat_priv->driver_state);
  1413. }
  1414. break;
  1415. }
  1416. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1417. ret = cnss_do_recovery(plat_priv, recovery_data->reason);
  1418. out:
  1419. kfree(data);
  1420. return ret;
  1421. }
  1422. int cnss_self_recovery(struct device *dev,
  1423. enum cnss_recovery_reason reason)
  1424. {
  1425. cnss_schedule_recovery(dev, reason);
  1426. return 0;
  1427. }
  1428. EXPORT_SYMBOL(cnss_self_recovery);
  1429. void cnss_schedule_recovery(struct device *dev,
  1430. enum cnss_recovery_reason reason)
  1431. {
  1432. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1433. struct cnss_recovery_data *data;
  1434. int gfp = GFP_KERNEL;
  1435. if (!test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  1436. cnss_bus_update_status(plat_priv, CNSS_FW_DOWN);
  1437. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1438. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1439. cnss_pr_dbg("Driver unload or idle shutdown is in progress, ignore schedule recovery\n");
  1440. return;
  1441. }
  1442. if (in_interrupt() || irqs_disabled())
  1443. gfp = GFP_ATOMIC;
  1444. data = kzalloc(sizeof(*data), gfp);
  1445. if (!data)
  1446. return;
  1447. data->reason = reason;
  1448. cnss_driver_event_post(plat_priv,
  1449. CNSS_DRIVER_EVENT_RECOVERY,
  1450. 0, data);
  1451. }
  1452. EXPORT_SYMBOL(cnss_schedule_recovery);
  1453. int cnss_force_fw_assert(struct device *dev)
  1454. {
  1455. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1456. if (!plat_priv) {
  1457. cnss_pr_err("plat_priv is NULL\n");
  1458. return -ENODEV;
  1459. }
  1460. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1461. cnss_pr_info("Forced FW assert is not supported\n");
  1462. return -EOPNOTSUPP;
  1463. }
  1464. if (cnss_bus_is_device_down(plat_priv)) {
  1465. cnss_pr_info("Device is already in bad state, ignore force assert\n");
  1466. return 0;
  1467. }
  1468. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1469. cnss_pr_info("Recovery is already in progress, ignore forced FW assert\n");
  1470. return 0;
  1471. }
  1472. if (in_interrupt() || irqs_disabled())
  1473. cnss_driver_event_post(plat_priv,
  1474. CNSS_DRIVER_EVENT_FORCE_FW_ASSERT,
  1475. 0, NULL);
  1476. else
  1477. cnss_bus_force_fw_assert_hdlr(plat_priv);
  1478. return 0;
  1479. }
  1480. EXPORT_SYMBOL(cnss_force_fw_assert);
  1481. int cnss_force_collect_rddm(struct device *dev)
  1482. {
  1483. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1484. unsigned int timeout;
  1485. int ret = 0;
  1486. if (!plat_priv) {
  1487. cnss_pr_err("plat_priv is NULL\n");
  1488. return -ENODEV;
  1489. }
  1490. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1491. cnss_pr_info("Force collect rddm is not supported\n");
  1492. return -EOPNOTSUPP;
  1493. }
  1494. if (cnss_bus_is_device_down(plat_priv)) {
  1495. cnss_pr_info("Device is already in bad state, wait to collect rddm\n");
  1496. goto wait_rddm;
  1497. }
  1498. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1499. cnss_pr_info("Recovery is already in progress, wait to collect rddm\n");
  1500. goto wait_rddm;
  1501. }
  1502. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1503. test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1504. test_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state) ||
  1505. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1506. cnss_pr_info("Loading/Unloading/idle restart/shutdown is in progress, ignore forced collect rddm\n");
  1507. return 0;
  1508. }
  1509. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  1510. if (ret)
  1511. return ret;
  1512. wait_rddm:
  1513. reinit_completion(&plat_priv->rddm_complete);
  1514. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RDDM);
  1515. ret = wait_for_completion_timeout(&plat_priv->rddm_complete,
  1516. msecs_to_jiffies(timeout));
  1517. if (!ret) {
  1518. cnss_pr_err("Timeout (%ums) waiting for RDDM to complete\n",
  1519. timeout);
  1520. ret = -ETIMEDOUT;
  1521. } else if (ret > 0) {
  1522. ret = 0;
  1523. }
  1524. return ret;
  1525. }
  1526. EXPORT_SYMBOL(cnss_force_collect_rddm);
  1527. int cnss_qmi_send_get(struct device *dev)
  1528. {
  1529. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1530. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1531. return 0;
  1532. return cnss_bus_qmi_send_get(plat_priv);
  1533. }
  1534. EXPORT_SYMBOL(cnss_qmi_send_get);
  1535. int cnss_qmi_send_put(struct device *dev)
  1536. {
  1537. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1538. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1539. return 0;
  1540. return cnss_bus_qmi_send_put(plat_priv);
  1541. }
  1542. EXPORT_SYMBOL(cnss_qmi_send_put);
  1543. int cnss_qmi_send(struct device *dev, int type, void *cmd,
  1544. int cmd_len, void *cb_ctx,
  1545. int (*cb)(void *ctx, void *event, int event_len))
  1546. {
  1547. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1548. int ret;
  1549. if (!plat_priv)
  1550. return -ENODEV;
  1551. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1552. return -EINVAL;
  1553. plat_priv->get_info_cb = cb;
  1554. plat_priv->get_info_cb_ctx = cb_ctx;
  1555. ret = cnss_wlfw_get_info_send_sync(plat_priv, type, cmd, cmd_len);
  1556. if (ret) {
  1557. plat_priv->get_info_cb = NULL;
  1558. plat_priv->get_info_cb_ctx = NULL;
  1559. }
  1560. return ret;
  1561. }
  1562. EXPORT_SYMBOL(cnss_qmi_send);
  1563. static int cnss_cold_boot_cal_start_hdlr(struct cnss_plat_data *plat_priv)
  1564. {
  1565. int ret = 0;
  1566. u32 retry = 0, timeout;
  1567. if (test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state)) {
  1568. cnss_pr_dbg("Calibration complete. Ignore calibration req\n");
  1569. goto out;
  1570. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  1571. cnss_pr_dbg("Calibration in progress. Ignore new calibration req\n");
  1572. goto out;
  1573. }
  1574. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1575. test_bit(CNSS_DRIVER_PROBED, &plat_priv->driver_state) ||
  1576. test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1577. cnss_pr_err("WLAN in mission mode before cold boot calibration\n");
  1578. CNSS_ASSERT(0);
  1579. return -EINVAL;
  1580. }
  1581. while (retry++ < CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  1582. if (test_bit(CNSS_PCI_PROBE_DONE, &plat_priv->driver_state))
  1583. break;
  1584. msleep(CNSS_CAL_START_PROBE_WAIT_MS);
  1585. if (retry == CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  1586. cnss_pr_err("Calibration start failed as PCI probe not complete\n");
  1587. CNSS_ASSERT(0);
  1588. ret = -EINVAL;
  1589. goto mark_cal_fail;
  1590. }
  1591. }
  1592. set_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1593. if (test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state)) {
  1594. timeout = cnss_get_timeout(plat_priv,
  1595. CNSS_TIMEOUT_CALIBRATION);
  1596. cnss_pr_dbg("Restarting calibration %ds timeout\n",
  1597. timeout / 1000);
  1598. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  1599. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  1600. msecs_to_jiffies(timeout));
  1601. }
  1602. reinit_completion(&plat_priv->cal_complete);
  1603. ret = cnss_bus_dev_powerup(plat_priv);
  1604. mark_cal_fail:
  1605. if (ret) {
  1606. complete(&plat_priv->cal_complete);
  1607. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1608. /* Set CBC done in driver state to mark attempt and note error
  1609. * since calibration cannot be retried at boot.
  1610. */
  1611. plat_priv->cal_done = CNSS_CAL_FAILURE;
  1612. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  1613. }
  1614. out:
  1615. return ret;
  1616. }
  1617. static int cnss_cold_boot_cal_done_hdlr(struct cnss_plat_data *plat_priv,
  1618. void *data)
  1619. {
  1620. struct cnss_cal_info *cal_info = data;
  1621. if (!test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state) ||
  1622. test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state))
  1623. goto out;
  1624. switch (cal_info->cal_status) {
  1625. case CNSS_CAL_DONE:
  1626. cnss_pr_dbg("Calibration completed successfully\n");
  1627. plat_priv->cal_done = true;
  1628. break;
  1629. case CNSS_CAL_TIMEOUT:
  1630. case CNSS_CAL_FAILURE:
  1631. cnss_pr_dbg("Calibration failed. Status: %d, force shutdown\n",
  1632. cal_info->cal_status);
  1633. break;
  1634. default:
  1635. cnss_pr_err("Unknown calibration status: %u\n",
  1636. cal_info->cal_status);
  1637. break;
  1638. }
  1639. cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  1640. cnss_bus_free_qdss_mem(plat_priv);
  1641. cnss_release_antenna_sharing(plat_priv);
  1642. cnss_bus_dev_shutdown(plat_priv);
  1643. msleep(POWER_RESET_MIN_DELAY_MS);
  1644. complete(&plat_priv->cal_complete);
  1645. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1646. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  1647. if (cal_info->cal_status == CNSS_CAL_DONE) {
  1648. cnss_cal_mem_upload_to_file(plat_priv);
  1649. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state))
  1650. goto out;
  1651. cnss_pr_dbg("Schedule WLAN driver load\n");
  1652. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  1653. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  1654. 0);
  1655. }
  1656. out:
  1657. kfree(data);
  1658. return 0;
  1659. }
  1660. static int cnss_power_up_hdlr(struct cnss_plat_data *plat_priv)
  1661. {
  1662. int ret;
  1663. ret = cnss_bus_dev_powerup(plat_priv);
  1664. if (ret)
  1665. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  1666. return ret;
  1667. }
  1668. static int cnss_power_down_hdlr(struct cnss_plat_data *plat_priv)
  1669. {
  1670. cnss_bus_dev_shutdown(plat_priv);
  1671. return 0;
  1672. }
  1673. static int cnss_qdss_trace_req_mem_hdlr(struct cnss_plat_data *plat_priv)
  1674. {
  1675. int ret = 0;
  1676. ret = cnss_bus_alloc_qdss_mem(plat_priv);
  1677. if (ret < 0)
  1678. return ret;
  1679. return cnss_wlfw_qdss_trace_mem_info_send_sync(plat_priv);
  1680. }
  1681. static void *cnss_get_fw_mem_pa_to_va(struct cnss_fw_mem *fw_mem,
  1682. u32 mem_seg_len, u64 pa, u32 size)
  1683. {
  1684. int i = 0;
  1685. u64 offset = 0;
  1686. void *va = NULL;
  1687. u64 local_pa;
  1688. u32 local_size;
  1689. for (i = 0; i < mem_seg_len; i++) {
  1690. local_pa = (u64)fw_mem[i].pa;
  1691. local_size = (u32)fw_mem[i].size;
  1692. if (pa == local_pa && size <= local_size) {
  1693. va = fw_mem[i].va;
  1694. break;
  1695. }
  1696. if (pa > local_pa &&
  1697. pa < local_pa + local_size &&
  1698. pa + size <= local_pa + local_size) {
  1699. offset = pa - local_pa;
  1700. va = fw_mem[i].va + offset;
  1701. break;
  1702. }
  1703. }
  1704. return va;
  1705. }
  1706. static int cnss_fw_mem_file_save_hdlr(struct cnss_plat_data *plat_priv,
  1707. void *data)
  1708. {
  1709. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  1710. struct cnss_fw_mem *fw_mem_seg;
  1711. int ret = 0L;
  1712. void *va = NULL;
  1713. u32 i, fw_mem_seg_len;
  1714. switch (event_data->mem_type) {
  1715. case QMI_WLFW_MEM_TYPE_DDR_V01:
  1716. if (!plat_priv->fw_mem_seg_len)
  1717. goto invalid_mem_save;
  1718. fw_mem_seg = plat_priv->fw_mem;
  1719. fw_mem_seg_len = plat_priv->fw_mem_seg_len;
  1720. break;
  1721. case QMI_WLFW_MEM_QDSS_V01:
  1722. if (!plat_priv->qdss_mem_seg_len)
  1723. goto invalid_mem_save;
  1724. fw_mem_seg = plat_priv->qdss_mem;
  1725. fw_mem_seg_len = plat_priv->qdss_mem_seg_len;
  1726. break;
  1727. default:
  1728. goto invalid_mem_save;
  1729. }
  1730. for (i = 0; i < event_data->mem_seg_len; i++) {
  1731. va = cnss_get_fw_mem_pa_to_va(fw_mem_seg, fw_mem_seg_len,
  1732. event_data->mem_seg[i].addr,
  1733. event_data->mem_seg[i].size);
  1734. if (!va) {
  1735. cnss_pr_err("Fail to find matching va of pa %pa for mem type: %d\n",
  1736. &event_data->mem_seg[i].addr,
  1737. event_data->mem_type);
  1738. ret = -EINVAL;
  1739. break;
  1740. }
  1741. ret = cnss_genl_send_msg(va, CNSS_GENL_MSG_TYPE_QDSS,
  1742. event_data->file_name,
  1743. event_data->mem_seg[i].size);
  1744. if (ret < 0) {
  1745. cnss_pr_err("Fail to save fw mem data: %d\n",
  1746. ret);
  1747. break;
  1748. }
  1749. }
  1750. kfree(data);
  1751. return ret;
  1752. invalid_mem_save:
  1753. cnss_pr_err("FW Mem type %d not allocated. Invalid save request\n",
  1754. event_data->mem_type);
  1755. kfree(data);
  1756. return -EINVAL;
  1757. }
  1758. static int cnss_qdss_trace_free_hdlr(struct cnss_plat_data *plat_priv)
  1759. {
  1760. cnss_bus_free_qdss_mem(plat_priv);
  1761. return 0;
  1762. }
  1763. static int cnss_qdss_trace_req_data_hdlr(struct cnss_plat_data *plat_priv,
  1764. void *data)
  1765. {
  1766. int ret = 0;
  1767. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  1768. if (!plat_priv)
  1769. return -ENODEV;
  1770. ret = cnss_wlfw_qdss_data_send_sync(plat_priv, event_data->file_name,
  1771. event_data->total_size);
  1772. kfree(data);
  1773. return ret;
  1774. }
  1775. static void cnss_driver_event_work(struct work_struct *work)
  1776. {
  1777. struct cnss_plat_data *plat_priv =
  1778. container_of(work, struct cnss_plat_data, event_work);
  1779. struct cnss_driver_event *event;
  1780. unsigned long flags;
  1781. int ret = 0;
  1782. if (!plat_priv) {
  1783. cnss_pr_err("plat_priv is NULL!\n");
  1784. return;
  1785. }
  1786. cnss_pm_stay_awake(plat_priv);
  1787. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1788. while (!list_empty(&plat_priv->event_list)) {
  1789. event = list_first_entry(&plat_priv->event_list,
  1790. struct cnss_driver_event, list);
  1791. list_del(&event->list);
  1792. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1793. cnss_pr_dbg("Processing driver event: %s%s(%d), state: 0x%lx\n",
  1794. cnss_driver_event_to_str(event->type),
  1795. event->sync ? "-sync" : "", event->type,
  1796. plat_priv->driver_state);
  1797. switch (event->type) {
  1798. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  1799. ret = cnss_wlfw_server_arrive(plat_priv, event->data);
  1800. break;
  1801. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  1802. ret = cnss_wlfw_server_exit(plat_priv);
  1803. break;
  1804. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  1805. ret = cnss_bus_alloc_fw_mem(plat_priv);
  1806. if (ret)
  1807. break;
  1808. ret = cnss_wlfw_respond_mem_send_sync(plat_priv);
  1809. break;
  1810. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  1811. ret = cnss_fw_mem_ready_hdlr(plat_priv);
  1812. break;
  1813. case CNSS_DRIVER_EVENT_FW_READY:
  1814. ret = cnss_fw_ready_hdlr(plat_priv);
  1815. break;
  1816. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  1817. ret = cnss_cold_boot_cal_start_hdlr(plat_priv);
  1818. break;
  1819. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  1820. ret = cnss_cold_boot_cal_done_hdlr(plat_priv,
  1821. event->data);
  1822. break;
  1823. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  1824. ret = cnss_bus_register_driver_hdlr(plat_priv,
  1825. event->data);
  1826. break;
  1827. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  1828. ret = cnss_bus_unregister_driver_hdlr(plat_priv);
  1829. break;
  1830. case CNSS_DRIVER_EVENT_RECOVERY:
  1831. ret = cnss_driver_recovery_hdlr(plat_priv,
  1832. event->data);
  1833. break;
  1834. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  1835. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  1836. break;
  1837. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  1838. set_bit(CNSS_DRIVER_IDLE_RESTART,
  1839. &plat_priv->driver_state);
  1840. /* fall through */
  1841. case CNSS_DRIVER_EVENT_POWER_UP:
  1842. ret = cnss_power_up_hdlr(plat_priv);
  1843. break;
  1844. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  1845. set_bit(CNSS_DRIVER_IDLE_SHUTDOWN,
  1846. &plat_priv->driver_state);
  1847. /* fall through */
  1848. case CNSS_DRIVER_EVENT_POWER_DOWN:
  1849. ret = cnss_power_down_hdlr(plat_priv);
  1850. break;
  1851. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  1852. ret = cnss_process_wfc_call_ind_event(plat_priv,
  1853. event->data);
  1854. break;
  1855. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  1856. ret = cnss_process_twt_cfg_ind_event(plat_priv,
  1857. event->data);
  1858. break;
  1859. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  1860. ret = cnss_qdss_trace_req_mem_hdlr(plat_priv);
  1861. break;
  1862. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  1863. ret = cnss_fw_mem_file_save_hdlr(plat_priv,
  1864. event->data);
  1865. break;
  1866. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  1867. ret = cnss_qdss_trace_free_hdlr(plat_priv);
  1868. break;
  1869. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  1870. ret = cnss_qdss_trace_req_data_hdlr(plat_priv,
  1871. event->data);
  1872. break;
  1873. default:
  1874. cnss_pr_err("Invalid driver event type: %d",
  1875. event->type);
  1876. kfree(event);
  1877. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1878. continue;
  1879. }
  1880. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1881. if (event->sync) {
  1882. event->ret = ret;
  1883. complete(&event->complete);
  1884. continue;
  1885. }
  1886. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1887. kfree(event);
  1888. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1889. }
  1890. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1891. cnss_pm_relax(plat_priv);
  1892. }
  1893. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1894. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  1895. {
  1896. int ret = 0;
  1897. struct cnss_subsys_info *subsys_info;
  1898. subsys_info = &plat_priv->subsys_info;
  1899. subsys_info->subsys_desc.name = "wlan";
  1900. subsys_info->subsys_desc.owner = THIS_MODULE;
  1901. subsys_info->subsys_desc.powerup = cnss_subsys_powerup;
  1902. subsys_info->subsys_desc.shutdown = cnss_subsys_shutdown;
  1903. subsys_info->subsys_desc.ramdump = cnss_subsys_ramdump;
  1904. subsys_info->subsys_desc.crash_shutdown = cnss_subsys_crash_shutdown;
  1905. subsys_info->subsys_desc.dev = &plat_priv->plat_dev->dev;
  1906. subsys_info->subsys_device = subsys_register(&subsys_info->subsys_desc);
  1907. if (IS_ERR(subsys_info->subsys_device)) {
  1908. ret = PTR_ERR(subsys_info->subsys_device);
  1909. cnss_pr_err("Failed to register subsys, err = %d\n", ret);
  1910. goto out;
  1911. }
  1912. subsys_info->subsys_handle =
  1913. subsystem_get(subsys_info->subsys_desc.name);
  1914. if (!subsys_info->subsys_handle) {
  1915. cnss_pr_err("Failed to get subsys_handle!\n");
  1916. ret = -EINVAL;
  1917. goto unregister_subsys;
  1918. } else if (IS_ERR(subsys_info->subsys_handle)) {
  1919. ret = PTR_ERR(subsys_info->subsys_handle);
  1920. cnss_pr_err("Failed to do subsystem_get, err = %d\n", ret);
  1921. goto unregister_subsys;
  1922. }
  1923. return 0;
  1924. unregister_subsys:
  1925. subsys_unregister(subsys_info->subsys_device);
  1926. out:
  1927. return ret;
  1928. }
  1929. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  1930. {
  1931. struct cnss_subsys_info *subsys_info;
  1932. subsys_info = &plat_priv->subsys_info;
  1933. subsystem_put(subsys_info->subsys_handle);
  1934. subsys_unregister(subsys_info->subsys_device);
  1935. }
  1936. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  1937. {
  1938. struct cnss_subsys_info *subsys_info = &plat_priv->subsys_info;
  1939. return create_ramdump_device(subsys_info->subsys_desc.name,
  1940. subsys_info->subsys_desc.dev);
  1941. }
  1942. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  1943. void *ramdump_dev)
  1944. {
  1945. destroy_ramdump_device(ramdump_dev);
  1946. }
  1947. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  1948. {
  1949. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  1950. struct ramdump_segment segment;
  1951. memset(&segment, 0, sizeof(segment));
  1952. segment.v_address = (void __iomem *)ramdump_info->ramdump_va;
  1953. segment.size = ramdump_info->ramdump_size;
  1954. return qcom_ramdump(ramdump_info->ramdump_dev, &segment, 1);
  1955. }
  1956. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  1957. {
  1958. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  1959. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  1960. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  1961. struct ramdump_segment *ramdump_segs, *s;
  1962. struct cnss_dump_meta_info meta_info = {0};
  1963. int i, ret = 0;
  1964. ramdump_segs = kcalloc(dump_data->nentries + 1,
  1965. sizeof(*ramdump_segs),
  1966. GFP_KERNEL);
  1967. if (!ramdump_segs)
  1968. return -ENOMEM;
  1969. s = ramdump_segs + 1;
  1970. for (i = 0; i < dump_data->nentries; i++) {
  1971. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  1972. cnss_pr_err("Unsupported dump type: %d",
  1973. dump_seg->type);
  1974. continue;
  1975. }
  1976. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  1977. meta_info.entry[dump_seg->type].type = dump_seg->type;
  1978. meta_info.entry[dump_seg->type].entry_start = i + 1;
  1979. }
  1980. meta_info.entry[dump_seg->type].entry_num++;
  1981. s->address = dump_seg->address;
  1982. s->v_address = (void __iomem *)dump_seg->v_address;
  1983. s->size = dump_seg->size;
  1984. s++;
  1985. dump_seg++;
  1986. }
  1987. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  1988. meta_info.version = CNSS_RAMDUMP_VERSION;
  1989. meta_info.chipset = plat_priv->device_id;
  1990. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  1991. ramdump_segs->v_address = (void __iomem *)(&meta_info);
  1992. ramdump_segs->size = sizeof(meta_info);
  1993. ret = qcom_elf_ramdump(info_v2->ramdump_dev, ramdump_segs,
  1994. dump_data->nentries + 1);
  1995. kfree(ramdump_segs);
  1996. return ret;
  1997. }
  1998. #else
  1999. static int cnss_panic_handler(struct notifier_block *nb, unsigned long action,
  2000. void *data)
  2001. {
  2002. struct cnss_plat_data *plat_priv =
  2003. container_of(nb, struct cnss_plat_data, panic_nb);
  2004. cnss_bus_dev_crash_shutdown(plat_priv);
  2005. return NOTIFY_DONE;
  2006. }
  2007. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  2008. {
  2009. int ret;
  2010. if (!plat_priv)
  2011. return -ENODEV;
  2012. plat_priv->panic_nb.notifier_call = cnss_panic_handler;
  2013. ret = atomic_notifier_chain_register(&panic_notifier_list,
  2014. &plat_priv->panic_nb);
  2015. if (ret) {
  2016. cnss_pr_err("Failed to register panic handler\n");
  2017. return -EINVAL;
  2018. }
  2019. return 0;
  2020. }
  2021. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  2022. {
  2023. int ret;
  2024. ret = atomic_notifier_chain_unregister(&panic_notifier_list,
  2025. &plat_priv->panic_nb);
  2026. if (ret)
  2027. cnss_pr_err("Failed to unregister panic handler\n");
  2028. }
  2029. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2030. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  2031. {
  2032. return &plat_priv->plat_dev->dev;
  2033. }
  2034. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  2035. void *ramdump_dev)
  2036. {
  2037. }
  2038. #endif
  2039. #if IS_ENABLED(CONFIG_QCOM_RAMDUMP)
  2040. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2041. {
  2042. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  2043. struct qcom_dump_segment segment;
  2044. struct list_head head;
  2045. INIT_LIST_HEAD(&head);
  2046. memset(&segment, 0, sizeof(segment));
  2047. segment.va = ramdump_info->ramdump_va;
  2048. segment.size = ramdump_info->ramdump_size;
  2049. list_add(&segment.node, &head);
  2050. return qcom_dump(&head, ramdump_info->ramdump_dev);
  2051. }
  2052. #else
  2053. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2054. {
  2055. return 0;
  2056. }
  2057. /* Using completion event inside dynamically allocated ramdump_desc
  2058. * may result a race between freeing the event after setting it to
  2059. * complete inside dev coredump free callback and the thread that is
  2060. * waiting for completion.
  2061. */
  2062. DECLARE_COMPLETION(dump_done);
  2063. #define TIMEOUT_SAVE_DUMP_MS 30000
  2064. #define SIZEOF_ELF_STRUCT(__xhdr) \
  2065. static inline size_t sizeof_elf_##__xhdr(unsigned char class) \
  2066. { \
  2067. if (class == ELFCLASS32) \
  2068. return sizeof(struct elf32_##__xhdr); \
  2069. else \
  2070. return sizeof(struct elf64_##__xhdr); \
  2071. }
  2072. SIZEOF_ELF_STRUCT(phdr)
  2073. SIZEOF_ELF_STRUCT(hdr)
  2074. #define set_xhdr_property(__xhdr, arg, class, member, value) \
  2075. do { \
  2076. if (class == ELFCLASS32) \
  2077. ((struct elf32_##__xhdr *)arg)->member = value; \
  2078. else \
  2079. ((struct elf64_##__xhdr *)arg)->member = value; \
  2080. } while (0)
  2081. #define set_ehdr_property(arg, class, member, value) \
  2082. set_xhdr_property(hdr, arg, class, member, value)
  2083. #define set_phdr_property(arg, class, member, value) \
  2084. set_xhdr_property(phdr, arg, class, member, value)
  2085. /* These replace qcom_ramdump driver APIs called from common API
  2086. * cnss_do_elf_dump() by the ones defined here.
  2087. */
  2088. #define qcom_dump_segment cnss_qcom_dump_segment
  2089. #define qcom_elf_dump cnss_qcom_elf_dump
  2090. #define dump_enabled cnss_dump_enabled
  2091. struct cnss_qcom_dump_segment {
  2092. struct list_head node;
  2093. dma_addr_t da;
  2094. void *va;
  2095. size_t size;
  2096. };
  2097. struct cnss_qcom_ramdump_desc {
  2098. void *data;
  2099. struct completion dump_done;
  2100. };
  2101. static ssize_t cnss_qcom_devcd_readv(char *buffer, loff_t offset, size_t count,
  2102. void *data, size_t datalen)
  2103. {
  2104. struct cnss_qcom_ramdump_desc *desc = data;
  2105. return memory_read_from_buffer(buffer, count, &offset, desc->data,
  2106. datalen);
  2107. }
  2108. static void cnss_qcom_devcd_freev(void *data)
  2109. {
  2110. struct cnss_qcom_ramdump_desc *desc = data;
  2111. cnss_pr_dbg("Free dump data for dev coredump\n");
  2112. complete(&dump_done);
  2113. vfree(desc->data);
  2114. kfree(desc);
  2115. }
  2116. static int cnss_qcom_devcd_dump(struct device *dev, void *data, size_t datalen,
  2117. gfp_t gfp)
  2118. {
  2119. struct cnss_qcom_ramdump_desc *desc;
  2120. unsigned int timeout = TIMEOUT_SAVE_DUMP_MS;
  2121. int ret;
  2122. desc = kmalloc(sizeof(*desc), GFP_KERNEL);
  2123. if (!desc)
  2124. return -ENOMEM;
  2125. desc->data = data;
  2126. reinit_completion(&dump_done);
  2127. dev_coredumpm(dev, NULL, desc, datalen, gfp,
  2128. cnss_qcom_devcd_readv, cnss_qcom_devcd_freev);
  2129. ret = wait_for_completion_timeout(&dump_done,
  2130. msecs_to_jiffies(timeout));
  2131. if (!ret)
  2132. cnss_pr_err("Timeout waiting (%dms) for saving dump to file system\n",
  2133. timeout);
  2134. return ret ? 0 : -ETIMEDOUT;
  2135. }
  2136. /* Since the elf32 and elf64 identification is identical apart from
  2137. * the class, use elf32 by default.
  2138. */
  2139. static void init_elf_identification(struct elf32_hdr *ehdr, unsigned char class)
  2140. {
  2141. memcpy(ehdr->e_ident, ELFMAG, SELFMAG);
  2142. ehdr->e_ident[EI_CLASS] = class;
  2143. ehdr->e_ident[EI_DATA] = ELFDATA2LSB;
  2144. ehdr->e_ident[EI_VERSION] = EV_CURRENT;
  2145. ehdr->e_ident[EI_OSABI] = ELFOSABI_NONE;
  2146. }
  2147. int cnss_qcom_elf_dump(struct list_head *segs, struct device *dev,
  2148. unsigned char class)
  2149. {
  2150. struct cnss_qcom_dump_segment *segment;
  2151. void *phdr, *ehdr;
  2152. size_t data_size, offset;
  2153. int phnum = 0;
  2154. void *data;
  2155. void __iomem *ptr;
  2156. if (!segs || list_empty(segs))
  2157. return -EINVAL;
  2158. data_size = sizeof_elf_hdr(class);
  2159. list_for_each_entry(segment, segs, node) {
  2160. data_size += sizeof_elf_phdr(class) + segment->size;
  2161. phnum++;
  2162. }
  2163. data = vmalloc(data_size);
  2164. if (!data)
  2165. return -ENOMEM;
  2166. cnss_pr_dbg("Creating ELF file with size %d\n", data_size);
  2167. ehdr = data;
  2168. memset(ehdr, 0, sizeof_elf_hdr(class));
  2169. init_elf_identification(ehdr, class);
  2170. set_ehdr_property(ehdr, class, e_type, ET_CORE);
  2171. set_ehdr_property(ehdr, class, e_machine, EM_NONE);
  2172. set_ehdr_property(ehdr, class, e_version, EV_CURRENT);
  2173. set_ehdr_property(ehdr, class, e_phoff, sizeof_elf_hdr(class));
  2174. set_ehdr_property(ehdr, class, e_ehsize, sizeof_elf_hdr(class));
  2175. set_ehdr_property(ehdr, class, e_phentsize, sizeof_elf_phdr(class));
  2176. set_ehdr_property(ehdr, class, e_phnum, phnum);
  2177. phdr = data + sizeof_elf_hdr(class);
  2178. offset = sizeof_elf_hdr(class) + sizeof_elf_phdr(class) * phnum;
  2179. list_for_each_entry(segment, segs, node) {
  2180. memset(phdr, 0, sizeof_elf_phdr(class));
  2181. set_phdr_property(phdr, class, p_type, PT_LOAD);
  2182. set_phdr_property(phdr, class, p_offset, offset);
  2183. set_phdr_property(phdr, class, p_vaddr, segment->da);
  2184. set_phdr_property(phdr, class, p_paddr, segment->da);
  2185. set_phdr_property(phdr, class, p_filesz, segment->size);
  2186. set_phdr_property(phdr, class, p_memsz, segment->size);
  2187. set_phdr_property(phdr, class, p_flags, PF_R | PF_W | PF_X);
  2188. set_phdr_property(phdr, class, p_align, 0);
  2189. if (segment->va) {
  2190. memcpy(data + offset, segment->va, segment->size);
  2191. } else {
  2192. ptr = devm_ioremap(dev, segment->da, segment->size);
  2193. if (!ptr) {
  2194. cnss_pr_err("Invalid coredump segment (%pad, %zu)\n",
  2195. &segment->da, segment->size);
  2196. memset(data + offset, 0xff, segment->size);
  2197. } else {
  2198. memcpy_fromio(data + offset, ptr,
  2199. segment->size);
  2200. }
  2201. }
  2202. offset += segment->size;
  2203. phdr += sizeof_elf_phdr(class);
  2204. }
  2205. return cnss_qcom_devcd_dump(dev, data, data_size, GFP_KERNEL);
  2206. }
  2207. /* Saving dump to file system is always needed in this case. */
  2208. static bool cnss_dump_enabled(void)
  2209. {
  2210. return true;
  2211. }
  2212. #endif /* CONFIG_QCOM_RAMDUMP */
  2213. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  2214. {
  2215. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2216. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  2217. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  2218. struct qcom_dump_segment *seg;
  2219. struct cnss_dump_meta_info meta_info = {0};
  2220. struct list_head head;
  2221. int i, ret = 0;
  2222. if (!dump_enabled()) {
  2223. cnss_pr_info("Dump collection is not enabled\n");
  2224. return ret;
  2225. }
  2226. INIT_LIST_HEAD(&head);
  2227. for (i = 0; i < dump_data->nentries; i++) {
  2228. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  2229. cnss_pr_err("Unsupported dump type: %d",
  2230. dump_seg->type);
  2231. continue;
  2232. }
  2233. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2234. if (!seg)
  2235. continue;
  2236. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  2237. meta_info.entry[dump_seg->type].type = dump_seg->type;
  2238. meta_info.entry[dump_seg->type].entry_start = i + 1;
  2239. }
  2240. meta_info.entry[dump_seg->type].entry_num++;
  2241. seg->da = dump_seg->address;
  2242. seg->va = dump_seg->v_address;
  2243. seg->size = dump_seg->size;
  2244. list_add_tail(&seg->node, &head);
  2245. dump_seg++;
  2246. }
  2247. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2248. if (!seg)
  2249. goto do_elf_dump;
  2250. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2251. meta_info.version = CNSS_RAMDUMP_VERSION;
  2252. meta_info.chipset = plat_priv->device_id;
  2253. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  2254. seg->va = &meta_info;
  2255. seg->size = sizeof(meta_info);
  2256. list_add(&seg->node, &head);
  2257. do_elf_dump:
  2258. ret = qcom_elf_dump(&head, info_v2->ramdump_dev, ELF_CLASS);
  2259. while (!list_empty(&head)) {
  2260. seg = list_first_entry(&head, struct qcom_dump_segment, node);
  2261. list_del(&seg->node);
  2262. kfree(seg);
  2263. }
  2264. return ret;
  2265. }
  2266. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  2267. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2268. static int cnss_init_dump_entry(struct cnss_plat_data *plat_priv)
  2269. {
  2270. struct cnss_ramdump_info *ramdump_info;
  2271. struct msm_dump_entry dump_entry;
  2272. ramdump_info = &plat_priv->ramdump_info;
  2273. ramdump_info->dump_data.addr = ramdump_info->ramdump_pa;
  2274. ramdump_info->dump_data.len = ramdump_info->ramdump_size;
  2275. ramdump_info->dump_data.version = CNSS_DUMP_FORMAT_VER;
  2276. ramdump_info->dump_data.magic = CNSS_DUMP_MAGIC_VER_V2;
  2277. strlcpy(ramdump_info->dump_data.name, CNSS_DUMP_NAME,
  2278. sizeof(ramdump_info->dump_data.name));
  2279. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2280. dump_entry.addr = virt_to_phys(&ramdump_info->dump_data);
  2281. return msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  2282. &dump_entry);
  2283. }
  2284. static int cnss_register_ramdump_v1(struct cnss_plat_data *plat_priv)
  2285. {
  2286. int ret = 0;
  2287. struct device *dev;
  2288. struct cnss_ramdump_info *ramdump_info;
  2289. u32 ramdump_size = 0;
  2290. dev = &plat_priv->plat_dev->dev;
  2291. ramdump_info = &plat_priv->ramdump_info;
  2292. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2293. &ramdump_size) == 0) {
  2294. ramdump_info->ramdump_va =
  2295. dma_alloc_coherent(dev, ramdump_size,
  2296. &ramdump_info->ramdump_pa,
  2297. GFP_KERNEL);
  2298. if (ramdump_info->ramdump_va)
  2299. ramdump_info->ramdump_size = ramdump_size;
  2300. }
  2301. cnss_pr_dbg("ramdump va: %pK, pa: %pa\n",
  2302. ramdump_info->ramdump_va, &ramdump_info->ramdump_pa);
  2303. if (ramdump_info->ramdump_size == 0) {
  2304. cnss_pr_info("Ramdump will not be collected");
  2305. goto out;
  2306. }
  2307. ret = cnss_init_dump_entry(plat_priv);
  2308. if (ret) {
  2309. cnss_pr_err("Failed to setup dump table, err = %d\n", ret);
  2310. goto free_ramdump;
  2311. }
  2312. ramdump_info->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  2313. if (!ramdump_info->ramdump_dev) {
  2314. cnss_pr_err("Failed to create ramdump device!");
  2315. ret = -ENOMEM;
  2316. goto free_ramdump;
  2317. }
  2318. return 0;
  2319. free_ramdump:
  2320. dma_free_coherent(dev, ramdump_info->ramdump_size,
  2321. ramdump_info->ramdump_va, ramdump_info->ramdump_pa);
  2322. out:
  2323. return ret;
  2324. }
  2325. static void cnss_unregister_ramdump_v1(struct cnss_plat_data *plat_priv)
  2326. {
  2327. struct device *dev;
  2328. struct cnss_ramdump_info *ramdump_info;
  2329. dev = &plat_priv->plat_dev->dev;
  2330. ramdump_info = &plat_priv->ramdump_info;
  2331. if (ramdump_info->ramdump_dev)
  2332. cnss_destroy_ramdump_device(plat_priv,
  2333. ramdump_info->ramdump_dev);
  2334. if (ramdump_info->ramdump_va)
  2335. dma_free_coherent(dev, ramdump_info->ramdump_size,
  2336. ramdump_info->ramdump_va,
  2337. ramdump_info->ramdump_pa);
  2338. }
  2339. /**
  2340. * cnss_ignore_dump_data_reg_fail - Ignore Ramdump table register failure
  2341. * @ret: Error returned by msm_dump_data_register_nominidump
  2342. *
  2343. * For Lahaina GKI boot, we dont have support for mem dump feature. So
  2344. * ignore failure.
  2345. *
  2346. * Return: Same given error code if mem dump feature enabled, 0 otherwise
  2347. */
  2348. static int cnss_ignore_dump_data_reg_fail(int ret)
  2349. {
  2350. return ret;
  2351. }
  2352. static int cnss_register_ramdump_v2(struct cnss_plat_data *plat_priv)
  2353. {
  2354. int ret = 0;
  2355. struct cnss_ramdump_info_v2 *info_v2;
  2356. struct cnss_dump_data *dump_data;
  2357. struct msm_dump_entry dump_entry;
  2358. struct device *dev = &plat_priv->plat_dev->dev;
  2359. u32 ramdump_size = 0;
  2360. info_v2 = &plat_priv->ramdump_info_v2;
  2361. dump_data = &info_v2->dump_data;
  2362. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2363. &ramdump_size) == 0)
  2364. info_v2->ramdump_size = ramdump_size;
  2365. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  2366. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  2367. if (!info_v2->dump_data_vaddr)
  2368. return -ENOMEM;
  2369. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  2370. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  2371. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  2372. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  2373. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  2374. sizeof(dump_data->name));
  2375. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2376. dump_entry.addr = virt_to_phys(dump_data);
  2377. ret = msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  2378. &dump_entry);
  2379. if (ret) {
  2380. ret = cnss_ignore_dump_data_reg_fail(ret);
  2381. cnss_pr_err("Failed to setup dump table, %s (%d)\n",
  2382. ret ? "Error" : "Ignoring", ret);
  2383. goto free_ramdump;
  2384. }
  2385. info_v2->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  2386. if (!info_v2->ramdump_dev) {
  2387. cnss_pr_err("Failed to create ramdump device!\n");
  2388. ret = -ENOMEM;
  2389. goto free_ramdump;
  2390. }
  2391. return 0;
  2392. free_ramdump:
  2393. kfree(info_v2->dump_data_vaddr);
  2394. info_v2->dump_data_vaddr = NULL;
  2395. return ret;
  2396. }
  2397. static void cnss_unregister_ramdump_v2(struct cnss_plat_data *plat_priv)
  2398. {
  2399. struct cnss_ramdump_info_v2 *info_v2;
  2400. info_v2 = &plat_priv->ramdump_info_v2;
  2401. if (info_v2->ramdump_dev)
  2402. cnss_destroy_ramdump_device(plat_priv, info_v2->ramdump_dev);
  2403. kfree(info_v2->dump_data_vaddr);
  2404. info_v2->dump_data_vaddr = NULL;
  2405. info_v2->dump_data_valid = false;
  2406. }
  2407. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  2408. {
  2409. int ret = 0;
  2410. switch (plat_priv->device_id) {
  2411. case QCA6174_DEVICE_ID:
  2412. ret = cnss_register_ramdump_v1(plat_priv);
  2413. break;
  2414. case QCA6290_DEVICE_ID:
  2415. case QCA6390_DEVICE_ID:
  2416. case QCA6490_DEVICE_ID:
  2417. case KIWI_DEVICE_ID:
  2418. ret = cnss_register_ramdump_v2(plat_priv);
  2419. break;
  2420. default:
  2421. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  2422. ret = -ENODEV;
  2423. break;
  2424. }
  2425. return ret;
  2426. }
  2427. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  2428. {
  2429. switch (plat_priv->device_id) {
  2430. case QCA6174_DEVICE_ID:
  2431. cnss_unregister_ramdump_v1(plat_priv);
  2432. break;
  2433. case QCA6290_DEVICE_ID:
  2434. case QCA6390_DEVICE_ID:
  2435. case QCA6490_DEVICE_ID:
  2436. case KIWI_DEVICE_ID:
  2437. cnss_unregister_ramdump_v2(plat_priv);
  2438. break;
  2439. default:
  2440. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  2441. break;
  2442. }
  2443. }
  2444. #else
  2445. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  2446. {
  2447. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2448. struct cnss_dump_data *dump_data = dump_data = &info_v2->dump_data;
  2449. struct device *dev = &plat_priv->plat_dev->dev;
  2450. u32 ramdump_size = 0;
  2451. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2452. &ramdump_size) == 0)
  2453. info_v2->ramdump_size = ramdump_size;
  2454. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  2455. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  2456. if (!info_v2->dump_data_vaddr)
  2457. return -ENOMEM;
  2458. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  2459. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  2460. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  2461. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  2462. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  2463. sizeof(dump_data->name));
  2464. info_v2->ramdump_dev = dev;
  2465. return 0;
  2466. }
  2467. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  2468. {
  2469. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2470. info_v2->ramdump_dev = NULL;
  2471. kfree(info_v2->dump_data_vaddr);
  2472. info_v2->dump_data_vaddr = NULL;
  2473. info_v2->dump_data_valid = false;
  2474. }
  2475. #endif /* CONFIG_QCOM_MEMORY_DUMP_V2 */
  2476. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  2477. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  2478. phys_addr_t *pa, unsigned long attrs)
  2479. {
  2480. struct sg_table sgt;
  2481. int ret;
  2482. ret = dma_get_sgtable_attrs(dev, &sgt, va, dma, size, attrs);
  2483. if (ret) {
  2484. cnss_pr_err("Failed to get sgtable for va: 0x%pK, dma: %pa, size: 0x%zx, attrs: 0x%x\n",
  2485. va, &dma, size, attrs);
  2486. return -EINVAL;
  2487. }
  2488. *pa = page_to_phys(sg_page(sgt.sgl));
  2489. sg_free_table(&sgt);
  2490. return 0;
  2491. }
  2492. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  2493. enum cnss_fw_dump_type type, int seg_no,
  2494. void *va, phys_addr_t pa, size_t size)
  2495. {
  2496. struct md_region md_entry;
  2497. int ret;
  2498. switch (type) {
  2499. case CNSS_FW_IMAGE:
  2500. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  2501. seg_no);
  2502. break;
  2503. case CNSS_FW_RDDM:
  2504. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  2505. seg_no);
  2506. break;
  2507. case CNSS_FW_REMOTE_HEAP:
  2508. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  2509. seg_no);
  2510. break;
  2511. default:
  2512. cnss_pr_err("Unknown dump type ID: %d\n", type);
  2513. return -EINVAL;
  2514. }
  2515. md_entry.phys_addr = pa;
  2516. md_entry.virt_addr = (uintptr_t)va;
  2517. md_entry.size = size;
  2518. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2519. cnss_pr_dbg("Mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  2520. md_entry.name, va, &pa, size);
  2521. ret = msm_minidump_add_region(&md_entry);
  2522. if (ret < 0)
  2523. cnss_pr_err("Failed to add mini dump region, err = %d\n", ret);
  2524. return ret;
  2525. }
  2526. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  2527. enum cnss_fw_dump_type type, int seg_no,
  2528. void *va, phys_addr_t pa, size_t size)
  2529. {
  2530. struct md_region md_entry;
  2531. int ret;
  2532. switch (type) {
  2533. case CNSS_FW_IMAGE:
  2534. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  2535. seg_no);
  2536. break;
  2537. case CNSS_FW_RDDM:
  2538. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  2539. seg_no);
  2540. break;
  2541. case CNSS_FW_REMOTE_HEAP:
  2542. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  2543. seg_no);
  2544. break;
  2545. default:
  2546. cnss_pr_err("Unknown dump type ID: %d\n", type);
  2547. return -EINVAL;
  2548. }
  2549. md_entry.phys_addr = pa;
  2550. md_entry.virt_addr = (uintptr_t)va;
  2551. md_entry.size = size;
  2552. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2553. cnss_pr_dbg("Remove mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  2554. md_entry.name, va, &pa, size);
  2555. ret = msm_minidump_remove_region(&md_entry);
  2556. if (ret)
  2557. cnss_pr_err("Failed to remove mini dump region, err = %d\n",
  2558. ret);
  2559. return ret;
  2560. }
  2561. #else
  2562. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  2563. phys_addr_t *pa, unsigned long attrs)
  2564. {
  2565. return 0;
  2566. }
  2567. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  2568. enum cnss_fw_dump_type type, int seg_no,
  2569. void *va, phys_addr_t pa, size_t size)
  2570. {
  2571. return 0;
  2572. }
  2573. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  2574. enum cnss_fw_dump_type type, int seg_no,
  2575. void *va, phys_addr_t pa, size_t size)
  2576. {
  2577. return 0;
  2578. }
  2579. #endif /* CONFIG_QCOM_MINIDUMP */
  2580. int cnss_request_firmware_direct(struct cnss_plat_data *plat_priv,
  2581. const struct firmware **fw_entry,
  2582. const char *filename)
  2583. {
  2584. if (IS_ENABLED(CONFIG_CNSS_REQ_FW_DIRECT))
  2585. return request_firmware_direct(fw_entry, filename,
  2586. &plat_priv->plat_dev->dev);
  2587. else
  2588. return firmware_request_nowarn(fw_entry, filename,
  2589. &plat_priv->plat_dev->dev);
  2590. }
  2591. #if IS_ENABLED(CONFIG_INTERCONNECT)
  2592. /**
  2593. * cnss_register_bus_scale() - Setup interconnect voting data
  2594. * @plat_priv: Platform data structure
  2595. *
  2596. * For different interconnect path configured in device tree setup voting data
  2597. * for list of bandwidth requirements.
  2598. *
  2599. * Result: 0 for success. -EINVAL if not configured
  2600. */
  2601. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  2602. {
  2603. int ret = -EINVAL;
  2604. u32 idx, i, j, cfg_arr_size, *cfg_arr = NULL;
  2605. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  2606. struct device *dev = &plat_priv->plat_dev->dev;
  2607. INIT_LIST_HEAD(&plat_priv->icc.list_head);
  2608. ret = of_property_read_u32(dev->of_node,
  2609. "qcom,icc-path-count",
  2610. &plat_priv->icc.path_count);
  2611. if (ret) {
  2612. cnss_pr_dbg("Platform Bus Interconnect path not configured\n");
  2613. return 0;
  2614. }
  2615. ret = of_property_read_u32(plat_priv->plat_dev->dev.of_node,
  2616. "qcom,bus-bw-cfg-count",
  2617. &plat_priv->icc.bus_bw_cfg_count);
  2618. if (ret) {
  2619. cnss_pr_err("Failed to get Bus BW Config table size\n");
  2620. goto cleanup;
  2621. }
  2622. cfg_arr_size = plat_priv->icc.path_count *
  2623. plat_priv->icc.bus_bw_cfg_count * CNSS_ICC_VOTE_MAX;
  2624. cfg_arr = kcalloc(cfg_arr_size, sizeof(*cfg_arr), GFP_KERNEL);
  2625. if (!cfg_arr) {
  2626. cnss_pr_err("Failed to alloc cfg table mem\n");
  2627. ret = -ENOMEM;
  2628. goto cleanup;
  2629. }
  2630. ret = of_property_read_u32_array(plat_priv->plat_dev->dev.of_node,
  2631. "qcom,bus-bw-cfg", cfg_arr,
  2632. cfg_arr_size);
  2633. if (ret) {
  2634. cnss_pr_err("Invalid Bus BW Config Table\n");
  2635. goto cleanup;
  2636. }
  2637. cnss_pr_dbg("ICC Path_Count: %d BW_CFG_Count: %d\n",
  2638. plat_priv->icc.path_count, plat_priv->icc.bus_bw_cfg_count);
  2639. for (idx = 0; idx < plat_priv->icc.path_count; idx++) {
  2640. bus_bw_info = devm_kzalloc(dev, sizeof(*bus_bw_info),
  2641. GFP_KERNEL);
  2642. if (!bus_bw_info) {
  2643. ret = -ENOMEM;
  2644. goto out;
  2645. }
  2646. ret = of_property_read_string_index(dev->of_node,
  2647. "interconnect-names", idx,
  2648. &bus_bw_info->icc_name);
  2649. if (ret)
  2650. goto out;
  2651. bus_bw_info->icc_path =
  2652. of_icc_get(&plat_priv->plat_dev->dev,
  2653. bus_bw_info->icc_name);
  2654. if (IS_ERR(bus_bw_info->icc_path)) {
  2655. ret = PTR_ERR(bus_bw_info->icc_path);
  2656. if (ret != -EPROBE_DEFER) {
  2657. cnss_pr_err("Failed to get Interconnect path for %s. Err: %d\n",
  2658. bus_bw_info->icc_name, ret);
  2659. goto out;
  2660. }
  2661. }
  2662. bus_bw_info->cfg_table =
  2663. devm_kcalloc(dev, plat_priv->icc.bus_bw_cfg_count,
  2664. sizeof(*bus_bw_info->cfg_table),
  2665. GFP_KERNEL);
  2666. if (!bus_bw_info->cfg_table) {
  2667. ret = -ENOMEM;
  2668. goto out;
  2669. }
  2670. cnss_pr_dbg("ICC Vote CFG for path: %s\n",
  2671. bus_bw_info->icc_name);
  2672. for (i = 0, j = (idx * plat_priv->icc.bus_bw_cfg_count *
  2673. CNSS_ICC_VOTE_MAX);
  2674. i < plat_priv->icc.bus_bw_cfg_count;
  2675. i++, j += 2) {
  2676. bus_bw_info->cfg_table[i].avg_bw = cfg_arr[j];
  2677. bus_bw_info->cfg_table[i].peak_bw = cfg_arr[j + 1];
  2678. cnss_pr_dbg("ICC Vote BW: %d avg: %d peak: %d\n",
  2679. i, bus_bw_info->cfg_table[i].avg_bw,
  2680. bus_bw_info->cfg_table[i].peak_bw);
  2681. }
  2682. list_add_tail(&bus_bw_info->list,
  2683. &plat_priv->icc.list_head);
  2684. }
  2685. kfree(cfg_arr);
  2686. return 0;
  2687. out:
  2688. list_for_each_entry_safe(bus_bw_info, tmp,
  2689. &plat_priv->icc.list_head, list) {
  2690. list_del(&bus_bw_info->list);
  2691. }
  2692. cleanup:
  2693. kfree(cfg_arr);
  2694. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  2695. return ret;
  2696. }
  2697. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv)
  2698. {
  2699. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  2700. list_for_each_entry_safe(bus_bw_info, tmp,
  2701. &plat_priv->icc.list_head, list) {
  2702. list_del(&bus_bw_info->list);
  2703. if (bus_bw_info->icc_path)
  2704. icc_put(bus_bw_info->icc_path);
  2705. }
  2706. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  2707. }
  2708. #else
  2709. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  2710. {
  2711. return 0;
  2712. }
  2713. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv) {}
  2714. #endif /* CONFIG_INTERCONNECT */
  2715. void cnss_daemon_connection_update_cb(void *cb_ctx, bool status)
  2716. {
  2717. struct cnss_plat_data *plat_priv = cb_ctx;
  2718. if (!plat_priv) {
  2719. cnss_pr_err("%s: Invalid context\n", __func__);
  2720. return;
  2721. }
  2722. if (status) {
  2723. cnss_pr_info("CNSS Daemon connected\n");
  2724. set_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  2725. complete(&plat_priv->daemon_connected);
  2726. } else {
  2727. cnss_pr_info("CNSS Daemon disconnected\n");
  2728. reinit_completion(&plat_priv->daemon_connected);
  2729. clear_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  2730. }
  2731. }
  2732. static ssize_t enable_hds_store(struct device *dev,
  2733. struct device_attribute *attr,
  2734. const char *buf, size_t count)
  2735. {
  2736. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2737. unsigned int enable_hds = 0;
  2738. if (!plat_priv)
  2739. return -ENODEV;
  2740. if (sscanf(buf, "%du", &enable_hds) != 1) {
  2741. cnss_pr_err("Invalid enable_hds sysfs command\n");
  2742. return -EINVAL;
  2743. }
  2744. if (enable_hds)
  2745. plat_priv->hds_enabled = true;
  2746. else
  2747. plat_priv->hds_enabled = false;
  2748. cnss_pr_dbg("%s HDS file download, count is %zu\n",
  2749. plat_priv->hds_enabled ? "Enable" : "Disable", count);
  2750. return count;
  2751. }
  2752. static ssize_t recovery_store(struct device *dev,
  2753. struct device_attribute *attr,
  2754. const char *buf, size_t count)
  2755. {
  2756. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2757. unsigned int recovery = 0;
  2758. if (!plat_priv)
  2759. return -ENODEV;
  2760. if (sscanf(buf, "%du", &recovery) != 1) {
  2761. cnss_pr_err("Invalid recovery sysfs command\n");
  2762. return -EINVAL;
  2763. }
  2764. if (recovery)
  2765. plat_priv->recovery_enabled = true;
  2766. else
  2767. plat_priv->recovery_enabled = false;
  2768. cnss_pr_dbg("%s WLAN recovery, count is %zu\n",
  2769. plat_priv->recovery_enabled ? "Enable" : "Disable", count);
  2770. return count;
  2771. }
  2772. static ssize_t shutdown_store(struct device *dev,
  2773. struct device_attribute *attr,
  2774. const char *buf, size_t count)
  2775. {
  2776. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2777. if (plat_priv) {
  2778. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  2779. del_timer(&plat_priv->fw_boot_timer);
  2780. complete_all(&plat_priv->power_up_complete);
  2781. complete_all(&plat_priv->cal_complete);
  2782. }
  2783. cnss_pr_dbg("Received shutdown notification\n");
  2784. return count;
  2785. }
  2786. static ssize_t fs_ready_store(struct device *dev,
  2787. struct device_attribute *attr,
  2788. const char *buf, size_t count)
  2789. {
  2790. int fs_ready = 0;
  2791. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2792. if (sscanf(buf, "%du", &fs_ready) != 1)
  2793. return -EINVAL;
  2794. cnss_pr_dbg("File system is ready, fs_ready is %d, count is %zu\n",
  2795. fs_ready, count);
  2796. if (!plat_priv) {
  2797. cnss_pr_err("plat_priv is NULL\n");
  2798. return count;
  2799. }
  2800. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks)) {
  2801. cnss_pr_dbg("QMI is bypassed\n");
  2802. return count;
  2803. }
  2804. switch (plat_priv->device_id) {
  2805. case QCA6290_DEVICE_ID:
  2806. case QCA6390_DEVICE_ID:
  2807. case QCA6490_DEVICE_ID:
  2808. case KIWI_DEVICE_ID:
  2809. break;
  2810. default:
  2811. cnss_pr_err("Not supported for device ID 0x%lx\n",
  2812. plat_priv->device_id);
  2813. return count;
  2814. }
  2815. if (fs_ready == FILE_SYSTEM_READY && plat_priv->cbc_enabled) {
  2816. cnss_driver_event_post(plat_priv,
  2817. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
  2818. 0, NULL);
  2819. }
  2820. return count;
  2821. }
  2822. static ssize_t qdss_trace_start_store(struct device *dev,
  2823. struct device_attribute *attr,
  2824. const char *buf, size_t count)
  2825. {
  2826. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2827. wlfw_qdss_trace_start(plat_priv);
  2828. cnss_pr_dbg("Received QDSS start command\n");
  2829. return count;
  2830. }
  2831. static ssize_t qdss_trace_stop_store(struct device *dev,
  2832. struct device_attribute *attr,
  2833. const char *buf, size_t count)
  2834. {
  2835. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2836. u32 option = 0;
  2837. if (sscanf(buf, "%du", &option) != 1)
  2838. return -EINVAL;
  2839. wlfw_qdss_trace_stop(plat_priv, option);
  2840. cnss_pr_dbg("Received QDSS stop command\n");
  2841. return count;
  2842. }
  2843. static ssize_t qdss_conf_download_store(struct device *dev,
  2844. struct device_attribute *attr,
  2845. const char *buf, size_t count)
  2846. {
  2847. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2848. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  2849. cnss_pr_dbg("Received QDSS download config command\n");
  2850. return count;
  2851. }
  2852. static ssize_t hw_trace_override_store(struct device *dev,
  2853. struct device_attribute *attr,
  2854. const char *buf, size_t count)
  2855. {
  2856. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2857. int tmp = 0;
  2858. if (sscanf(buf, "%du", &tmp) != 1)
  2859. return -EINVAL;
  2860. plat_priv->hw_trc_override = tmp;
  2861. cnss_pr_dbg("Received QDSS hw_trc_override indication\n");
  2862. return count;
  2863. }
  2864. static ssize_t charger_mode_store(struct device *dev,
  2865. struct device_attribute *attr,
  2866. const char *buf, size_t count)
  2867. {
  2868. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2869. int tmp = 0;
  2870. if (sscanf(buf, "%du", &tmp) != 1)
  2871. return -EINVAL;
  2872. plat_priv->charger_mode = tmp;
  2873. cnss_pr_dbg("Received Charger Mode: %d\n", tmp);
  2874. return count;
  2875. }
  2876. static DEVICE_ATTR_WO(fs_ready);
  2877. static DEVICE_ATTR_WO(shutdown);
  2878. static DEVICE_ATTR_WO(recovery);
  2879. static DEVICE_ATTR_WO(enable_hds);
  2880. static DEVICE_ATTR_WO(qdss_trace_start);
  2881. static DEVICE_ATTR_WO(qdss_trace_stop);
  2882. static DEVICE_ATTR_WO(qdss_conf_download);
  2883. static DEVICE_ATTR_WO(hw_trace_override);
  2884. static DEVICE_ATTR_WO(charger_mode);
  2885. static struct attribute *cnss_attrs[] = {
  2886. &dev_attr_fs_ready.attr,
  2887. &dev_attr_shutdown.attr,
  2888. &dev_attr_recovery.attr,
  2889. &dev_attr_enable_hds.attr,
  2890. &dev_attr_qdss_trace_start.attr,
  2891. &dev_attr_qdss_trace_stop.attr,
  2892. &dev_attr_qdss_conf_download.attr,
  2893. &dev_attr_hw_trace_override.attr,
  2894. &dev_attr_charger_mode.attr,
  2895. NULL,
  2896. };
  2897. static struct attribute_group cnss_attr_group = {
  2898. .attrs = cnss_attrs,
  2899. };
  2900. static int cnss_create_sysfs_link(struct cnss_plat_data *plat_priv)
  2901. {
  2902. struct device *dev = &plat_priv->plat_dev->dev;
  2903. int ret;
  2904. ret = sysfs_create_link(kernel_kobj, &dev->kobj, "cnss");
  2905. if (ret) {
  2906. cnss_pr_err("Failed to create cnss link, err = %d\n",
  2907. ret);
  2908. goto out;
  2909. }
  2910. /* This is only for backward compatibility. */
  2911. ret = sysfs_create_link(kernel_kobj, &dev->kobj, "shutdown_wlan");
  2912. if (ret) {
  2913. cnss_pr_err("Failed to create shutdown_wlan link, err = %d\n",
  2914. ret);
  2915. goto rm_cnss_link;
  2916. }
  2917. return 0;
  2918. rm_cnss_link:
  2919. sysfs_remove_link(kernel_kobj, "cnss");
  2920. out:
  2921. return ret;
  2922. }
  2923. static void cnss_remove_sysfs_link(struct cnss_plat_data *plat_priv)
  2924. {
  2925. sysfs_remove_link(kernel_kobj, "shutdown_wlan");
  2926. sysfs_remove_link(kernel_kobj, "cnss");
  2927. }
  2928. static int cnss_create_sysfs(struct cnss_plat_data *plat_priv)
  2929. {
  2930. int ret = 0;
  2931. ret = devm_device_add_group(&plat_priv->plat_dev->dev,
  2932. &cnss_attr_group);
  2933. if (ret) {
  2934. cnss_pr_err("Failed to create cnss device group, err = %d\n",
  2935. ret);
  2936. goto out;
  2937. }
  2938. cnss_create_sysfs_link(plat_priv);
  2939. return 0;
  2940. out:
  2941. return ret;
  2942. }
  2943. static void cnss_remove_sysfs(struct cnss_plat_data *plat_priv)
  2944. {
  2945. cnss_remove_sysfs_link(plat_priv);
  2946. devm_device_remove_group(&plat_priv->plat_dev->dev, &cnss_attr_group);
  2947. }
  2948. static int cnss_event_work_init(struct cnss_plat_data *plat_priv)
  2949. {
  2950. spin_lock_init(&plat_priv->event_lock);
  2951. plat_priv->event_wq = alloc_workqueue("cnss_driver_event",
  2952. WQ_UNBOUND, 1);
  2953. if (!plat_priv->event_wq) {
  2954. cnss_pr_err("Failed to create event workqueue!\n");
  2955. return -EFAULT;
  2956. }
  2957. INIT_WORK(&plat_priv->event_work, cnss_driver_event_work);
  2958. INIT_LIST_HEAD(&plat_priv->event_list);
  2959. return 0;
  2960. }
  2961. static void cnss_event_work_deinit(struct cnss_plat_data *plat_priv)
  2962. {
  2963. destroy_workqueue(plat_priv->event_wq);
  2964. }
  2965. static int cnss_reboot_notifier(struct notifier_block *nb,
  2966. unsigned long action,
  2967. void *data)
  2968. {
  2969. struct cnss_plat_data *plat_priv =
  2970. container_of(nb, struct cnss_plat_data, reboot_nb);
  2971. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  2972. del_timer(&plat_priv->fw_boot_timer);
  2973. complete_all(&plat_priv->power_up_complete);
  2974. complete_all(&plat_priv->cal_complete);
  2975. cnss_pr_dbg("Reboot is in progress with action %d\n", action);
  2976. return NOTIFY_DONE;
  2977. }
  2978. static int cnss_misc_init(struct cnss_plat_data *plat_priv)
  2979. {
  2980. int ret;
  2981. ret = cnss_init_sol_gpio(plat_priv);
  2982. if (ret)
  2983. return ret;
  2984. timer_setup(&plat_priv->fw_boot_timer,
  2985. cnss_bus_fw_boot_timeout_hdlr, 0);
  2986. ret = register_pm_notifier(&cnss_pm_notifier);
  2987. if (ret)
  2988. cnss_pr_err("Failed to register PM notifier, err = %d\n", ret);
  2989. plat_priv->reboot_nb.notifier_call = cnss_reboot_notifier;
  2990. ret = register_reboot_notifier(&plat_priv->reboot_nb);
  2991. if (ret)
  2992. cnss_pr_err("Failed to register reboot notifier, err = %d\n",
  2993. ret);
  2994. ret = device_init_wakeup(&plat_priv->plat_dev->dev, true);
  2995. if (ret)
  2996. cnss_pr_err("Failed to init platform device wakeup source, err = %d\n",
  2997. ret);
  2998. INIT_WORK(&plat_priv->recovery_work, cnss_recovery_work_handler);
  2999. init_completion(&plat_priv->power_up_complete);
  3000. init_completion(&plat_priv->cal_complete);
  3001. init_completion(&plat_priv->rddm_complete);
  3002. init_completion(&plat_priv->recovery_complete);
  3003. init_completion(&plat_priv->daemon_connected);
  3004. mutex_init(&plat_priv->dev_lock);
  3005. mutex_init(&plat_priv->driver_ops_lock);
  3006. plat_priv->recovery_ws =
  3007. wakeup_source_register(&plat_priv->plat_dev->dev,
  3008. "CNSS_FW_RECOVERY");
  3009. if (!plat_priv->recovery_ws)
  3010. cnss_pr_err("Failed to setup FW recovery wake source\n");
  3011. ret = cnss_plat_ipc_register(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  3012. cnss_daemon_connection_update_cb,
  3013. plat_priv);
  3014. if (ret)
  3015. cnss_pr_err("QMI IPC connection call back register failed, err = %d\n",
  3016. ret);
  3017. return 0;
  3018. }
  3019. static void cnss_misc_deinit(struct cnss_plat_data *plat_priv)
  3020. {
  3021. cnss_plat_ipc_unregister(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  3022. plat_priv);
  3023. complete_all(&plat_priv->recovery_complete);
  3024. complete_all(&plat_priv->rddm_complete);
  3025. complete_all(&plat_priv->cal_complete);
  3026. complete_all(&plat_priv->power_up_complete);
  3027. complete_all(&plat_priv->daemon_connected);
  3028. device_init_wakeup(&plat_priv->plat_dev->dev, false);
  3029. unregister_reboot_notifier(&plat_priv->reboot_nb);
  3030. unregister_pm_notifier(&cnss_pm_notifier);
  3031. del_timer(&plat_priv->fw_boot_timer);
  3032. wakeup_source_unregister(plat_priv->recovery_ws);
  3033. cnss_deinit_sol_gpio(plat_priv);
  3034. }
  3035. static void cnss_init_control_params(struct cnss_plat_data *plat_priv)
  3036. {
  3037. plat_priv->ctrl_params.quirks = CNSS_QUIRKS_DEFAULT;
  3038. plat_priv->cbc_enabled = !IS_ENABLED(CONFIG_CNSS_EMULATION) &&
  3039. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3040. "qcom,wlan-cbc-enabled");
  3041. plat_priv->ctrl_params.mhi_timeout = CNSS_MHI_TIMEOUT_DEFAULT;
  3042. plat_priv->ctrl_params.mhi_m2_timeout = CNSS_MHI_M2_TIMEOUT_DEFAULT;
  3043. plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT;
  3044. plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT;
  3045. plat_priv->ctrl_params.time_sync_period = CNSS_TIME_SYNC_PERIOD_DEFAULT;
  3046. /* Set adsp_pc_enabled default value to true as ADSP pc is always
  3047. * enabled by default
  3048. */
  3049. plat_priv->adsp_pc_enabled = true;
  3050. }
  3051. static void cnss_get_pm_domain_info(struct cnss_plat_data *plat_priv)
  3052. {
  3053. struct device *dev = &plat_priv->plat_dev->dev;
  3054. plat_priv->use_pm_domain =
  3055. of_property_read_bool(dev->of_node, "use-pm-domain");
  3056. cnss_pr_dbg("use-pm-domain is %d\n", plat_priv->use_pm_domain);
  3057. }
  3058. static void cnss_get_wlaon_pwr_ctrl_info(struct cnss_plat_data *plat_priv)
  3059. {
  3060. struct device *dev = &plat_priv->plat_dev->dev;
  3061. plat_priv->set_wlaon_pwr_ctrl =
  3062. of_property_read_bool(dev->of_node, "qcom,set-wlaon-pwr-ctrl");
  3063. cnss_pr_dbg("set_wlaon_pwr_ctrl is %d\n",
  3064. plat_priv->set_wlaon_pwr_ctrl);
  3065. }
  3066. static bool cnss_use_fw_path_with_prefix(struct cnss_plat_data *plat_priv)
  3067. {
  3068. return (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3069. "qcom,converged-dt") ||
  3070. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3071. "qcom,same-dt-multi-dev") ||
  3072. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3073. "qcom,multi-wlan-exchg"));
  3074. }
  3075. static const struct platform_device_id cnss_platform_id_table[] = {
  3076. { .name = "qca6174", .driver_data = QCA6174_DEVICE_ID, },
  3077. { .name = "qca6290", .driver_data = QCA6290_DEVICE_ID, },
  3078. { .name = "qca6390", .driver_data = QCA6390_DEVICE_ID, },
  3079. { .name = "qca6490", .driver_data = QCA6490_DEVICE_ID, },
  3080. { .name = "kiwi", .driver_data = KIWI_DEVICE_ID, },
  3081. { .name = "qcaconv", .driver_data = 0, },
  3082. { },
  3083. };
  3084. static const struct of_device_id cnss_of_match_table[] = {
  3085. {
  3086. .compatible = "qcom,cnss",
  3087. .data = (void *)&cnss_platform_id_table[0]},
  3088. {
  3089. .compatible = "qcom,cnss-qca6290",
  3090. .data = (void *)&cnss_platform_id_table[1]},
  3091. {
  3092. .compatible = "qcom,cnss-qca6390",
  3093. .data = (void *)&cnss_platform_id_table[2]},
  3094. {
  3095. .compatible = "qcom,cnss-qca6490",
  3096. .data = (void *)&cnss_platform_id_table[3]},
  3097. {
  3098. .compatible = "qcom,cnss-kiwi",
  3099. .data = (void *)&cnss_platform_id_table[4]},
  3100. {
  3101. .compatible = "qcom,cnss-qca-converged",
  3102. .data = (void *)&cnss_platform_id_table[5]},
  3103. { },
  3104. };
  3105. MODULE_DEVICE_TABLE(of, cnss_of_match_table);
  3106. static inline bool
  3107. cnss_use_nv_mac(struct cnss_plat_data *plat_priv)
  3108. {
  3109. return of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3110. "use-nv-mac");
  3111. }
  3112. static int cnss_get_dev_cfg_node(struct cnss_plat_data *plat_priv)
  3113. {
  3114. struct device_node *child;
  3115. u32 id, i;
  3116. int id_n, ret;
  3117. int wlan_sw_ctrl_gpio = plat_priv->pinctrl_info.wlan_sw_ctrl_gpio;
  3118. u8 gpio_value;
  3119. if (!plat_priv->is_converged_dt)
  3120. return 0;
  3121. gpio_value = gpio_get_value(wlan_sw_ctrl_gpio);
  3122. cnss_pr_dbg("Value of WLAN_SW_CTRL GPIO: %d\n", gpio_value);
  3123. for_each_available_child_of_node(plat_priv->plat_dev->dev.of_node,
  3124. child) {
  3125. if (strcmp(child->name, "chip_cfg"))
  3126. continue;
  3127. id_n = of_property_count_u32_elems(child, "supported-ids");
  3128. if (id_n <= 0) {
  3129. cnss_pr_err("Device id is NOT set\n");
  3130. return -EINVAL;
  3131. }
  3132. for (i = 0; i < id_n; i++) {
  3133. ret = of_property_read_u32_index(child,
  3134. "supported-ids",
  3135. i, &id);
  3136. if (ret) {
  3137. cnss_pr_err("Failed to read supported ids\n");
  3138. return -EINVAL;
  3139. }
  3140. if (gpio_value && id == QCA6490_DEVICE_ID) {
  3141. plat_priv->plat_dev->dev.of_node = child;
  3142. plat_priv->device_id = QCA6490_DEVICE_ID;
  3143. cnss_utils_update_device_type(CNSS_HSP_DEVICE_TYPE);
  3144. cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n",
  3145. child->name, i, id);
  3146. return 0;
  3147. } else if (!gpio_value && id == KIWI_DEVICE_ID) {
  3148. plat_priv->plat_dev->dev.of_node = child;
  3149. plat_priv->device_id = KIWI_DEVICE_ID;
  3150. cnss_utils_update_device_type(CNSS_HMT_DEVICE_TYPE);
  3151. cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n",
  3152. child->name, i, id);
  3153. return 0;
  3154. }
  3155. }
  3156. }
  3157. return -EINVAL;
  3158. }
  3159. static inline bool
  3160. cnss_is_converged_dt(struct cnss_plat_data *plat_priv)
  3161. {
  3162. return of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3163. "qcom,converged-dt");
  3164. }
  3165. static int cnss_probe(struct platform_device *plat_dev)
  3166. {
  3167. int ret = 0;
  3168. struct cnss_plat_data *plat_priv;
  3169. const struct of_device_id *of_id;
  3170. const struct platform_device_id *device_id;
  3171. int retry = 0;
  3172. if (cnss_get_plat_priv(plat_dev)) {
  3173. cnss_pr_err("Driver is already initialized!\n");
  3174. ret = -EEXIST;
  3175. goto out;
  3176. }
  3177. of_id = of_match_device(cnss_of_match_table, &plat_dev->dev);
  3178. if (!of_id || !of_id->data) {
  3179. cnss_pr_err("Failed to find of match device!\n");
  3180. ret = -ENODEV;
  3181. goto out;
  3182. }
  3183. device_id = of_id->data;
  3184. plat_priv = devm_kzalloc(&plat_dev->dev, sizeof(*plat_priv),
  3185. GFP_KERNEL);
  3186. if (!plat_priv) {
  3187. ret = -ENOMEM;
  3188. goto out;
  3189. }
  3190. plat_priv->plat_dev = plat_dev;
  3191. plat_priv->device_id = device_id->driver_data;
  3192. plat_priv->is_converged_dt = cnss_is_converged_dt(plat_priv);
  3193. plat_priv->use_fw_path_with_prefix =
  3194. cnss_use_fw_path_with_prefix(plat_priv);
  3195. cnss_get_wlan_sw_ctrl(plat_priv);
  3196. ret = cnss_get_dev_cfg_node(plat_priv);
  3197. if (ret) {
  3198. cnss_pr_err("Failed to get device cfg node, err = %d\n", ret);
  3199. goto reset_plat_dev;
  3200. }
  3201. plat_priv->bus_type = cnss_get_bus_type(plat_priv->device_id);
  3202. plat_priv->use_nv_mac = cnss_use_nv_mac(plat_priv);
  3203. cnss_set_plat_priv(plat_dev, plat_priv);
  3204. platform_set_drvdata(plat_dev, plat_priv);
  3205. INIT_LIST_HEAD(&plat_priv->vreg_list);
  3206. INIT_LIST_HEAD(&plat_priv->clk_list);
  3207. cnss_get_pm_domain_info(plat_priv);
  3208. cnss_get_wlaon_pwr_ctrl_info(plat_priv);
  3209. cnss_power_misc_params_init(plat_priv);
  3210. cnss_get_tcs_info(plat_priv);
  3211. cnss_get_cpr_info(plat_priv);
  3212. cnss_aop_mbox_init(plat_priv);
  3213. cnss_init_control_params(plat_priv);
  3214. ret = cnss_get_resources(plat_priv);
  3215. if (ret)
  3216. goto reset_ctx;
  3217. ret = cnss_register_esoc(plat_priv);
  3218. if (ret)
  3219. goto free_res;
  3220. ret = cnss_register_bus_scale(plat_priv);
  3221. if (ret)
  3222. goto unreg_esoc;
  3223. ret = cnss_create_sysfs(plat_priv);
  3224. if (ret)
  3225. goto unreg_bus_scale;
  3226. ret = cnss_event_work_init(plat_priv);
  3227. if (ret)
  3228. goto remove_sysfs;
  3229. ret = cnss_qmi_init(plat_priv);
  3230. if (ret)
  3231. goto deinit_event_work;
  3232. ret = cnss_dms_init(plat_priv);
  3233. if (ret)
  3234. goto deinit_qmi;
  3235. ret = cnss_debugfs_create(plat_priv);
  3236. if (ret)
  3237. goto deinit_dms;
  3238. ret = cnss_misc_init(plat_priv);
  3239. if (ret)
  3240. goto destroy_debugfs;
  3241. /* Make sure all platform related init are done before
  3242. * device power on and bus init.
  3243. */
  3244. if (!test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks)) {
  3245. retry:
  3246. ret = cnss_power_on_device(plat_priv);
  3247. if (ret)
  3248. goto deinit_misc;
  3249. ret = cnss_bus_init(plat_priv);
  3250. if (ret) {
  3251. if ((ret != -EPROBE_DEFER) &&
  3252. retry++ < POWER_ON_RETRY_MAX_TIMES) {
  3253. cnss_power_off_device(plat_priv);
  3254. cnss_pr_dbg("Retry cnss_bus_init #%d\n", retry);
  3255. msleep(POWER_ON_RETRY_DELAY_MS * retry);
  3256. goto retry;
  3257. }
  3258. goto power_off;
  3259. }
  3260. }
  3261. cnss_register_coex_service(plat_priv);
  3262. cnss_register_ims_service(plat_priv);
  3263. ret = cnss_genl_init();
  3264. if (ret < 0)
  3265. cnss_pr_err("CNSS genl init failed %d\n", ret);
  3266. cnss_pr_info("Platform driver probed successfully.\n");
  3267. return 0;
  3268. power_off:
  3269. if (!test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks))
  3270. cnss_power_off_device(plat_priv);
  3271. deinit_misc:
  3272. cnss_misc_deinit(plat_priv);
  3273. destroy_debugfs:
  3274. cnss_debugfs_destroy(plat_priv);
  3275. deinit_dms:
  3276. cnss_dms_deinit(plat_priv);
  3277. deinit_qmi:
  3278. cnss_qmi_deinit(plat_priv);
  3279. deinit_event_work:
  3280. cnss_event_work_deinit(plat_priv);
  3281. remove_sysfs:
  3282. cnss_remove_sysfs(plat_priv);
  3283. unreg_bus_scale:
  3284. cnss_unregister_bus_scale(plat_priv);
  3285. unreg_esoc:
  3286. cnss_unregister_esoc(plat_priv);
  3287. free_res:
  3288. cnss_put_resources(plat_priv);
  3289. reset_ctx:
  3290. platform_set_drvdata(plat_dev, NULL);
  3291. reset_plat_dev:
  3292. cnss_set_plat_priv(plat_dev, NULL);
  3293. out:
  3294. return ret;
  3295. }
  3296. static int cnss_remove(struct platform_device *plat_dev)
  3297. {
  3298. struct cnss_plat_data *plat_priv = platform_get_drvdata(plat_dev);
  3299. cnss_genl_exit();
  3300. cnss_unregister_ims_service(plat_priv);
  3301. cnss_unregister_coex_service(plat_priv);
  3302. cnss_bus_deinit(plat_priv);
  3303. cnss_misc_deinit(plat_priv);
  3304. cnss_debugfs_destroy(plat_priv);
  3305. cnss_dms_deinit(plat_priv);
  3306. cnss_qmi_deinit(plat_priv);
  3307. cnss_event_work_deinit(plat_priv);
  3308. cnss_remove_sysfs(plat_priv);
  3309. cnss_unregister_bus_scale(plat_priv);
  3310. cnss_unregister_esoc(plat_priv);
  3311. cnss_put_resources(plat_priv);
  3312. if (!IS_ERR_OR_NULL(plat_priv->mbox_chan))
  3313. mbox_free_channel(plat_priv->mbox_chan);
  3314. platform_set_drvdata(plat_dev, NULL);
  3315. plat_env = NULL;
  3316. return 0;
  3317. }
  3318. static struct platform_driver cnss_platform_driver = {
  3319. .probe = cnss_probe,
  3320. .remove = cnss_remove,
  3321. .driver = {
  3322. .name = "cnss2",
  3323. .of_match_table = cnss_of_match_table,
  3324. #ifdef CONFIG_CNSS_ASYNC
  3325. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  3326. #endif
  3327. },
  3328. };
  3329. /**
  3330. * cnss_is_valid_dt_node_found - Check if valid device tree node present
  3331. *
  3332. * Valid device tree node means a node with "compatible" property from the
  3333. * device match table and "status" property is not disabled.
  3334. *
  3335. * Return: true if valid device tree node found, false if not found
  3336. */
  3337. static bool cnss_is_valid_dt_node_found(void)
  3338. {
  3339. struct device_node *dn = NULL;
  3340. for_each_matching_node(dn, cnss_of_match_table) {
  3341. if (of_device_is_available(dn))
  3342. break;
  3343. }
  3344. if (dn)
  3345. return true;
  3346. return false;
  3347. }
  3348. static int __init cnss_initialize(void)
  3349. {
  3350. int ret = 0;
  3351. if (!cnss_is_valid_dt_node_found())
  3352. return -ENODEV;
  3353. cnss_debug_init();
  3354. ret = platform_driver_register(&cnss_platform_driver);
  3355. if (ret)
  3356. cnss_debug_deinit();
  3357. return ret;
  3358. }
  3359. static void __exit cnss_exit(void)
  3360. {
  3361. platform_driver_unregister(&cnss_platform_driver);
  3362. cnss_debug_deinit();
  3363. }
  3364. module_init(cnss_initialize);
  3365. module_exit(cnss_exit);
  3366. MODULE_LICENSE("GPL v2");
  3367. MODULE_DESCRIPTION("CNSS2 Platform Driver");