cam_mem_mgr.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/types.h>
  7. #include <linux/mutex.h>
  8. #include <linux/msm_ion.h>
  9. #include <linux/slab.h>
  10. #include <linux/ion_kernel.h>
  11. #include <linux/dma-buf.h>
  12. #include "cam_req_mgr_util.h"
  13. #include "cam_mem_mgr.h"
  14. #include "cam_smmu_api.h"
  15. #include "cam_debug_util.h"
  16. static struct cam_mem_table tbl;
  17. static atomic_t cam_mem_mgr_state = ATOMIC_INIT(CAM_MEM_MGR_UNINITIALIZED);
  18. static int cam_mem_util_get_dma_dir(uint32_t flags)
  19. {
  20. int rc = -EINVAL;
  21. if (flags & CAM_MEM_FLAG_HW_READ_ONLY)
  22. rc = DMA_TO_DEVICE;
  23. else if (flags & CAM_MEM_FLAG_HW_WRITE_ONLY)
  24. rc = DMA_FROM_DEVICE;
  25. else if (flags & CAM_MEM_FLAG_HW_READ_WRITE)
  26. rc = DMA_BIDIRECTIONAL;
  27. else if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  28. rc = DMA_BIDIRECTIONAL;
  29. return rc;
  30. }
  31. static int cam_mem_util_map_cpu_va(struct dma_buf *dmabuf,
  32. uintptr_t *vaddr,
  33. size_t *len)
  34. {
  35. int i, j, rc;
  36. void *addr;
  37. /*
  38. * dma_buf_begin_cpu_access() and dma_buf_end_cpu_access()
  39. * need to be called in pair to avoid stability issue.
  40. */
  41. rc = dma_buf_begin_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  42. if (rc) {
  43. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  44. return rc;
  45. }
  46. /*
  47. * Code could be simplified if ION support of dma_buf_vmap is
  48. * available. This workaround takes the avandaage that ion_alloc
  49. * returns a virtually contiguous memory region, so we just need
  50. * to _kmap each individual page and then only use the virtual
  51. * address returned from the first call to _kmap.
  52. */
  53. for (i = 0; i < PAGE_ALIGN(dmabuf->size) / PAGE_SIZE; i++) {
  54. addr = dma_buf_kmap(dmabuf, i);
  55. if (IS_ERR_OR_NULL(addr)) {
  56. CAM_ERR(CAM_MEM, "kernel map fail");
  57. for (j = 0; j < i; j++)
  58. dma_buf_kunmap(dmabuf,
  59. j,
  60. (void *)(*vaddr + (j * PAGE_SIZE)));
  61. *vaddr = 0;
  62. *len = 0;
  63. rc = -ENOSPC;
  64. goto fail;
  65. }
  66. if (i == 0)
  67. *vaddr = (uint64_t)addr;
  68. }
  69. *len = dmabuf->size;
  70. return 0;
  71. fail:
  72. dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  73. return rc;
  74. }
  75. static int cam_mem_util_unmap_cpu_va(struct dma_buf *dmabuf,
  76. uint64_t vaddr)
  77. {
  78. int i, rc = 0, page_num;
  79. if (!dmabuf || !vaddr) {
  80. CAM_ERR(CAM_MEM, "Invalid input args %pK %llX", dmabuf, vaddr);
  81. return -EINVAL;
  82. }
  83. page_num = PAGE_ALIGN(dmabuf->size) / PAGE_SIZE;
  84. for (i = 0; i < page_num; i++) {
  85. dma_buf_kunmap(dmabuf, i,
  86. (void *)(vaddr + (i * PAGE_SIZE)));
  87. }
  88. /*
  89. * dma_buf_begin_cpu_access() and
  90. * dma_buf_end_cpu_access() need to be called in pair
  91. * to avoid stability issue.
  92. */
  93. rc = dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  94. if (rc) {
  95. CAM_ERR(CAM_MEM, "Failed in end cpu access, dmabuf=%pK",
  96. dmabuf);
  97. return rc;
  98. }
  99. return rc;
  100. }
  101. int cam_mem_mgr_init(void)
  102. {
  103. int i;
  104. int bitmap_size;
  105. memset(tbl.bufq, 0, sizeof(tbl.bufq));
  106. bitmap_size = BITS_TO_LONGS(CAM_MEM_BUFQ_MAX) * sizeof(long);
  107. tbl.bitmap = kzalloc(bitmap_size, GFP_KERNEL);
  108. if (!tbl.bitmap)
  109. return -ENOMEM;
  110. tbl.bits = bitmap_size * BITS_PER_BYTE;
  111. bitmap_zero(tbl.bitmap, tbl.bits);
  112. /* We need to reserve slot 0 because 0 is invalid */
  113. set_bit(0, tbl.bitmap);
  114. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  115. tbl.bufq[i].fd = -1;
  116. tbl.bufq[i].buf_handle = -1;
  117. }
  118. mutex_init(&tbl.m_lock);
  119. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_INITIALIZED);
  120. return 0;
  121. }
  122. static int32_t cam_mem_get_slot(void)
  123. {
  124. int32_t idx;
  125. mutex_lock(&tbl.m_lock);
  126. idx = find_first_zero_bit(tbl.bitmap, tbl.bits);
  127. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  128. mutex_unlock(&tbl.m_lock);
  129. return -ENOMEM;
  130. }
  131. set_bit(idx, tbl.bitmap);
  132. tbl.bufq[idx].active = true;
  133. mutex_init(&tbl.bufq[idx].q_lock);
  134. mutex_unlock(&tbl.m_lock);
  135. return idx;
  136. }
  137. static void cam_mem_put_slot(int32_t idx)
  138. {
  139. mutex_lock(&tbl.m_lock);
  140. mutex_lock(&tbl.bufq[idx].q_lock);
  141. tbl.bufq[idx].active = false;
  142. mutex_unlock(&tbl.bufq[idx].q_lock);
  143. mutex_destroy(&tbl.bufq[idx].q_lock);
  144. clear_bit(idx, tbl.bitmap);
  145. mutex_unlock(&tbl.m_lock);
  146. }
  147. int cam_mem_get_io_buf(int32_t buf_handle, int32_t mmu_handle,
  148. uint64_t *iova_ptr, size_t *len_ptr)
  149. {
  150. int rc = 0, idx;
  151. *len_ptr = 0;
  152. if (!atomic_read(&cam_mem_mgr_state)) {
  153. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  154. return -EINVAL;
  155. }
  156. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  157. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  158. return -EINVAL;
  159. if (!tbl.bufq[idx].active)
  160. return -EINVAL;
  161. mutex_lock(&tbl.bufq[idx].q_lock);
  162. if (buf_handle != tbl.bufq[idx].buf_handle) {
  163. rc = -EINVAL;
  164. goto handle_mismatch;
  165. }
  166. if (CAM_MEM_MGR_IS_SECURE_HDL(buf_handle))
  167. rc = cam_smmu_get_stage2_iova(mmu_handle,
  168. tbl.bufq[idx].fd,
  169. iova_ptr,
  170. len_ptr);
  171. else
  172. rc = cam_smmu_get_iova(mmu_handle,
  173. tbl.bufq[idx].fd,
  174. iova_ptr,
  175. len_ptr);
  176. if (rc) {
  177. CAM_ERR(CAM_MEM,
  178. "fail to map buf_hdl:0x%x, mmu_hdl: 0x%x for fd:%d",
  179. buf_handle, mmu_handle, tbl.bufq[idx].fd);
  180. goto handle_mismatch;
  181. }
  182. CAM_DBG(CAM_MEM,
  183. "handle:0x%x fd:%d iova_ptr:%pK len_ptr:%llu",
  184. mmu_handle, tbl.bufq[idx].fd, iova_ptr, *len_ptr);
  185. handle_mismatch:
  186. mutex_unlock(&tbl.bufq[idx].q_lock);
  187. return rc;
  188. }
  189. EXPORT_SYMBOL(cam_mem_get_io_buf);
  190. int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len)
  191. {
  192. int idx;
  193. if (!atomic_read(&cam_mem_mgr_state)) {
  194. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  195. return -EINVAL;
  196. }
  197. if (!atomic_read(&cam_mem_mgr_state)) {
  198. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  199. return -EINVAL;
  200. }
  201. if (!buf_handle || !vaddr_ptr || !len)
  202. return -EINVAL;
  203. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  204. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  205. return -EINVAL;
  206. if (!tbl.bufq[idx].active)
  207. return -EPERM;
  208. if (buf_handle != tbl.bufq[idx].buf_handle)
  209. return -EINVAL;
  210. if (!(tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS))
  211. return -EINVAL;
  212. if (tbl.bufq[idx].kmdvaddr) {
  213. *vaddr_ptr = tbl.bufq[idx].kmdvaddr;
  214. *len = tbl.bufq[idx].len;
  215. } else {
  216. CAM_ERR(CAM_MEM, "No KMD access was requested for 0x%x handle",
  217. buf_handle);
  218. return -EINVAL;
  219. }
  220. return 0;
  221. }
  222. EXPORT_SYMBOL(cam_mem_get_cpu_buf);
  223. int cam_mem_mgr_cache_ops(struct cam_mem_cache_ops_cmd *cmd)
  224. {
  225. int rc = 0, idx;
  226. uint32_t cache_dir;
  227. unsigned long dmabuf_flag = 0;
  228. if (!atomic_read(&cam_mem_mgr_state)) {
  229. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  230. return -EINVAL;
  231. }
  232. if (!cmd)
  233. return -EINVAL;
  234. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  235. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  236. return -EINVAL;
  237. mutex_lock(&tbl.bufq[idx].q_lock);
  238. if (!tbl.bufq[idx].active) {
  239. rc = -EINVAL;
  240. goto end;
  241. }
  242. if (cmd->buf_handle != tbl.bufq[idx].buf_handle) {
  243. rc = -EINVAL;
  244. goto end;
  245. }
  246. rc = dma_buf_get_flags(tbl.bufq[idx].dma_buf, &dmabuf_flag);
  247. if (rc) {
  248. CAM_ERR(CAM_MEM, "cache get flags failed %d", rc);
  249. goto end;
  250. }
  251. if (dmabuf_flag & ION_FLAG_CACHED) {
  252. switch (cmd->mem_cache_ops) {
  253. case CAM_MEM_CLEAN_CACHE:
  254. cache_dir = DMA_TO_DEVICE;
  255. break;
  256. case CAM_MEM_INV_CACHE:
  257. cache_dir = DMA_FROM_DEVICE;
  258. break;
  259. case CAM_MEM_CLEAN_INV_CACHE:
  260. cache_dir = DMA_BIDIRECTIONAL;
  261. break;
  262. default:
  263. CAM_ERR(CAM_MEM,
  264. "invalid cache ops :%d", cmd->mem_cache_ops);
  265. rc = -EINVAL;
  266. goto end;
  267. }
  268. } else {
  269. CAM_DBG(CAM_MEM, "BUF is not cached");
  270. goto end;
  271. }
  272. rc = dma_buf_begin_cpu_access(tbl.bufq[idx].dma_buf,
  273. (cmd->mem_cache_ops == CAM_MEM_CLEAN_INV_CACHE) ?
  274. DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
  275. if (rc) {
  276. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  277. goto end;
  278. }
  279. rc = dma_buf_end_cpu_access(tbl.bufq[idx].dma_buf,
  280. cache_dir);
  281. if (rc) {
  282. CAM_ERR(CAM_MEM, "dma end access failed rc=%d", rc);
  283. goto end;
  284. }
  285. end:
  286. mutex_unlock(&tbl.bufq[idx].q_lock);
  287. return rc;
  288. }
  289. EXPORT_SYMBOL(cam_mem_mgr_cache_ops);
  290. static int cam_mem_util_get_dma_buf(size_t len,
  291. unsigned int heap_id_mask,
  292. unsigned int flags,
  293. struct dma_buf **buf)
  294. {
  295. int rc = 0;
  296. if (!buf) {
  297. CAM_ERR(CAM_MEM, "Invalid params");
  298. return -EINVAL;
  299. }
  300. *buf = ion_alloc(len, heap_id_mask, flags);
  301. if (IS_ERR_OR_NULL(*buf))
  302. return -ENOMEM;
  303. return rc;
  304. }
  305. static int cam_mem_util_get_dma_buf_fd(size_t len,
  306. size_t align,
  307. unsigned int heap_id_mask,
  308. unsigned int flags,
  309. struct dma_buf **buf,
  310. int *fd)
  311. {
  312. struct dma_buf *dmabuf = NULL;
  313. int rc = 0;
  314. if (!buf || !fd) {
  315. CAM_ERR(CAM_MEM, "Invalid params, buf=%pK, fd=%pK", buf, fd);
  316. return -EINVAL;
  317. }
  318. *buf = ion_alloc(len, heap_id_mask, flags);
  319. if (IS_ERR_OR_NULL(*buf))
  320. return -ENOMEM;
  321. *fd = dma_buf_fd(*buf, O_CLOEXEC);
  322. if (*fd < 0) {
  323. CAM_ERR(CAM_MEM, "get fd fail, *fd=%d", *fd);
  324. rc = -EINVAL;
  325. goto get_fd_fail;
  326. }
  327. /*
  328. * increment the ref count so that ref count becomes 2 here
  329. * when we close fd, refcount becomes 1 and when we do
  330. * dmap_put_buf, ref count becomes 0 and memory will be freed.
  331. */
  332. dmabuf = dma_buf_get(*fd);
  333. if (IS_ERR_OR_NULL(dmabuf)) {
  334. CAM_ERR(CAM_MEM, "dma_buf_get failed, *fd=%d", *fd);
  335. rc = -EINVAL;
  336. }
  337. return rc;
  338. get_fd_fail:
  339. dma_buf_put(*buf);
  340. return rc;
  341. }
  342. static int cam_mem_util_ion_alloc(struct cam_mem_mgr_alloc_cmd *cmd,
  343. struct dma_buf **dmabuf,
  344. int *fd)
  345. {
  346. uint32_t heap_id;
  347. uint32_t ion_flag = 0;
  348. int rc;
  349. if ((cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE) &&
  350. (cmd->flags & CAM_MEM_FLAG_CDSP_OUTPUT)) {
  351. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  352. ion_flag |=
  353. ION_FLAG_SECURE | ION_FLAG_CP_CAMERA | ION_FLAG_CP_CDSP;
  354. } else if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  355. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  356. ion_flag |= ION_FLAG_SECURE | ION_FLAG_CP_CAMERA;
  357. } else {
  358. heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) |
  359. ION_HEAP(ION_CAMERA_HEAP_ID);
  360. }
  361. if (cmd->flags & CAM_MEM_FLAG_CACHE)
  362. ion_flag |= ION_FLAG_CACHED;
  363. else
  364. ion_flag &= ~ION_FLAG_CACHED;
  365. rc = cam_mem_util_get_dma_buf_fd(cmd->len,
  366. cmd->align,
  367. heap_id,
  368. ion_flag,
  369. dmabuf,
  370. fd);
  371. return rc;
  372. }
  373. static int cam_mem_util_check_alloc_flags(struct cam_mem_mgr_alloc_cmd *cmd)
  374. {
  375. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  376. CAM_ERR(CAM_MEM, "Num of mmu hdl exceeded maximum(%d)",
  377. CAM_MEM_MMU_MAX_HANDLE);
  378. return -EINVAL;
  379. }
  380. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  381. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  382. CAM_ERR(CAM_MEM, "Kernel mapping in secure mode not allowed");
  383. return -EINVAL;
  384. }
  385. return 0;
  386. }
  387. static int cam_mem_util_check_map_flags(struct cam_mem_mgr_map_cmd *cmd)
  388. {
  389. if (!cmd->flags) {
  390. CAM_ERR(CAM_MEM, "Invalid flags");
  391. return -EINVAL;
  392. }
  393. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  394. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  395. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  396. return -EINVAL;
  397. }
  398. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  399. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  400. CAM_ERR(CAM_MEM,
  401. "Kernel mapping in secure mode not allowed, flags=0x%x",
  402. cmd->flags);
  403. return -EINVAL;
  404. }
  405. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  406. CAM_ERR(CAM_MEM,
  407. "Shared memory buffers are not allowed to be mapped");
  408. return -EINVAL;
  409. }
  410. return 0;
  411. }
  412. static int cam_mem_util_map_hw_va(uint32_t flags,
  413. int32_t *mmu_hdls,
  414. int32_t num_hdls,
  415. int fd,
  416. dma_addr_t *hw_vaddr,
  417. size_t *len,
  418. enum cam_smmu_region_id region)
  419. {
  420. int i;
  421. int rc = -1;
  422. int dir = cam_mem_util_get_dma_dir(flags);
  423. if (dir < 0) {
  424. CAM_ERR(CAM_MEM, "fail to map DMA direction, dir=%d", dir);
  425. return dir;
  426. }
  427. CAM_DBG(CAM_MEM,
  428. "map_hw_va : fd = %d, flags = 0x%x, dir=%d, num_hdls=%d",
  429. fd, flags, dir, num_hdls);
  430. if (flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  431. for (i = 0; i < num_hdls; i++) {
  432. rc = cam_smmu_map_stage2_iova(mmu_hdls[i],
  433. fd,
  434. dir,
  435. hw_vaddr,
  436. len);
  437. if (rc < 0) {
  438. CAM_ERR(CAM_MEM,
  439. "Failed to securely map to smmu, i=%d, fd=%d, dir=%d, mmu_hdl=%d, rc=%d",
  440. i, fd, dir, mmu_hdls[i], rc);
  441. goto multi_map_fail;
  442. }
  443. }
  444. } else {
  445. for (i = 0; i < num_hdls; i++) {
  446. rc = cam_smmu_map_user_iova(mmu_hdls[i],
  447. fd,
  448. dir,
  449. (dma_addr_t *)hw_vaddr,
  450. len,
  451. region);
  452. if (rc < 0) {
  453. CAM_ERR(CAM_MEM,
  454. "Failed to map to smmu, i=%d, fd=%d, dir=%d, mmu_hdl=%d, region=%d, rc=%d",
  455. i, fd, dir, mmu_hdls[i], region, rc);
  456. goto multi_map_fail;
  457. }
  458. }
  459. }
  460. return rc;
  461. multi_map_fail:
  462. if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  463. for (--i; i > 0; i--)
  464. cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd);
  465. else
  466. for (--i; i > 0; i--)
  467. cam_smmu_unmap_user_iova(mmu_hdls[i],
  468. fd,
  469. CAM_SMMU_REGION_IO);
  470. return rc;
  471. }
  472. int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd)
  473. {
  474. int rc;
  475. int32_t idx;
  476. struct dma_buf *dmabuf = NULL;
  477. int fd = -1;
  478. dma_addr_t hw_vaddr = 0;
  479. size_t len;
  480. uintptr_t kvaddr = 0;
  481. size_t klen;
  482. if (!atomic_read(&cam_mem_mgr_state)) {
  483. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  484. return -EINVAL;
  485. }
  486. if (!cmd) {
  487. CAM_ERR(CAM_MEM, " Invalid argument");
  488. return -EINVAL;
  489. }
  490. len = cmd->len;
  491. rc = cam_mem_util_check_alloc_flags(cmd);
  492. if (rc) {
  493. CAM_ERR(CAM_MEM, "Invalid flags: flags = 0x%X, rc=%d",
  494. cmd->flags, rc);
  495. return rc;
  496. }
  497. rc = cam_mem_util_ion_alloc(cmd,
  498. &dmabuf,
  499. &fd);
  500. if (rc) {
  501. CAM_ERR(CAM_MEM,
  502. "Ion Alloc failed, len=%llu, align=%llu, flags=0x%x, num_hdl=%d",
  503. cmd->len, cmd->align, cmd->flags, cmd->num_hdl);
  504. return rc;
  505. }
  506. idx = cam_mem_get_slot();
  507. if (idx < 0) {
  508. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  509. rc = -ENOMEM;
  510. goto slot_fail;
  511. }
  512. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  513. (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  514. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  515. enum cam_smmu_region_id region;
  516. if (cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  517. region = CAM_SMMU_REGION_IO;
  518. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  519. region = CAM_SMMU_REGION_SHARED;
  520. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  521. region = CAM_SMMU_REGION_SECHEAP;
  522. rc = cam_mem_util_map_hw_va(cmd->flags,
  523. cmd->mmu_hdls,
  524. cmd->num_hdl,
  525. fd,
  526. &hw_vaddr,
  527. &len,
  528. region);
  529. if (rc) {
  530. CAM_ERR(CAM_MEM,
  531. "Failed in map_hw_va, flags=0x%x, fd=%d, region=%d, num_hdl=%d, rc=%d",
  532. cmd->flags, fd, region, cmd->num_hdl, rc);
  533. goto map_hw_fail;
  534. }
  535. }
  536. mutex_lock(&tbl.bufq[idx].q_lock);
  537. tbl.bufq[idx].fd = fd;
  538. tbl.bufq[idx].dma_buf = NULL;
  539. tbl.bufq[idx].flags = cmd->flags;
  540. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, fd);
  541. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  542. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  543. if (cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  544. rc = cam_mem_util_map_cpu_va(dmabuf, &kvaddr, &klen);
  545. if (rc) {
  546. CAM_ERR(CAM_MEM, "dmabuf: %pK mapping failed: %d",
  547. dmabuf, rc);
  548. goto map_kernel_fail;
  549. }
  550. }
  551. tbl.bufq[idx].kmdvaddr = kvaddr;
  552. tbl.bufq[idx].vaddr = hw_vaddr;
  553. tbl.bufq[idx].dma_buf = dmabuf;
  554. tbl.bufq[idx].len = cmd->len;
  555. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  556. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  557. sizeof(int32_t) * cmd->num_hdl);
  558. tbl.bufq[idx].is_imported = false;
  559. mutex_unlock(&tbl.bufq[idx].q_lock);
  560. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  561. cmd->out.fd = tbl.bufq[idx].fd;
  562. cmd->out.vaddr = 0;
  563. CAM_DBG(CAM_MEM,
  564. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu",
  565. cmd->out.fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  566. tbl.bufq[idx].len);
  567. return rc;
  568. map_kernel_fail:
  569. mutex_unlock(&tbl.bufq[idx].q_lock);
  570. map_hw_fail:
  571. cam_mem_put_slot(idx);
  572. slot_fail:
  573. dma_buf_put(dmabuf);
  574. return rc;
  575. }
  576. int cam_mem_mgr_map(struct cam_mem_mgr_map_cmd *cmd)
  577. {
  578. int32_t idx;
  579. int rc;
  580. struct dma_buf *dmabuf;
  581. dma_addr_t hw_vaddr = 0;
  582. size_t len = 0;
  583. if (!atomic_read(&cam_mem_mgr_state)) {
  584. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  585. return -EINVAL;
  586. }
  587. if (!cmd || (cmd->fd < 0)) {
  588. CAM_ERR(CAM_MEM, "Invalid argument");
  589. return -EINVAL;
  590. }
  591. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  592. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  593. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  594. return -EINVAL;
  595. }
  596. rc = cam_mem_util_check_map_flags(cmd);
  597. if (rc) {
  598. CAM_ERR(CAM_MEM, "Invalid flags: flags = %X", cmd->flags);
  599. return rc;
  600. }
  601. dmabuf = dma_buf_get(cmd->fd);
  602. if (IS_ERR_OR_NULL((void *)(dmabuf))) {
  603. CAM_ERR(CAM_MEM, "Failed to import dma_buf fd");
  604. return -EINVAL;
  605. }
  606. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  607. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  608. rc = cam_mem_util_map_hw_va(cmd->flags,
  609. cmd->mmu_hdls,
  610. cmd->num_hdl,
  611. cmd->fd,
  612. &hw_vaddr,
  613. &len,
  614. CAM_SMMU_REGION_IO);
  615. if (rc) {
  616. CAM_ERR(CAM_MEM,
  617. "Failed in map_hw_va, flags=0x%x, fd=%d, region=%d, num_hdl=%d, rc=%d",
  618. cmd->flags, cmd->fd, CAM_SMMU_REGION_IO,
  619. cmd->num_hdl, rc);
  620. goto map_fail;
  621. }
  622. }
  623. idx = cam_mem_get_slot();
  624. if (idx < 0) {
  625. rc = -ENOMEM;
  626. goto map_fail;
  627. }
  628. mutex_lock(&tbl.bufq[idx].q_lock);
  629. tbl.bufq[idx].fd = cmd->fd;
  630. tbl.bufq[idx].dma_buf = NULL;
  631. tbl.bufq[idx].flags = cmd->flags;
  632. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, cmd->fd);
  633. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  634. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  635. tbl.bufq[idx].kmdvaddr = 0;
  636. if (cmd->num_hdl > 0)
  637. tbl.bufq[idx].vaddr = hw_vaddr;
  638. else
  639. tbl.bufq[idx].vaddr = 0;
  640. tbl.bufq[idx].dma_buf = dmabuf;
  641. tbl.bufq[idx].len = len;
  642. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  643. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  644. sizeof(int32_t) * cmd->num_hdl);
  645. tbl.bufq[idx].is_imported = true;
  646. mutex_unlock(&tbl.bufq[idx].q_lock);
  647. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  648. cmd->out.vaddr = 0;
  649. CAM_DBG(CAM_MEM,
  650. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu",
  651. cmd->fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  652. tbl.bufq[idx].len);
  653. return rc;
  654. map_fail:
  655. dma_buf_put(dmabuf);
  656. return rc;
  657. }
  658. static int cam_mem_util_unmap_hw_va(int32_t idx,
  659. enum cam_smmu_region_id region,
  660. enum cam_smmu_mapping_client client)
  661. {
  662. int i;
  663. uint32_t flags;
  664. int32_t *mmu_hdls;
  665. int num_hdls;
  666. int fd;
  667. int rc = 0;
  668. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  669. CAM_ERR(CAM_MEM, "Incorrect index");
  670. return -EINVAL;
  671. }
  672. flags = tbl.bufq[idx].flags;
  673. mmu_hdls = tbl.bufq[idx].hdls;
  674. num_hdls = tbl.bufq[idx].num_hdl;
  675. fd = tbl.bufq[idx].fd;
  676. CAM_DBG(CAM_MEM,
  677. "unmap_hw_va : idx=%d, fd=%x, flags=0x%x, num_hdls=%d, client=%d",
  678. idx, fd, flags, num_hdls, client);
  679. if (flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  680. for (i = 0; i < num_hdls; i++) {
  681. rc = cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd);
  682. if (rc < 0) {
  683. CAM_ERR(CAM_MEM,
  684. "Failed in secure unmap, i=%d, fd=%d, mmu_hdl=%d, rc=%d",
  685. i, fd, mmu_hdls[i], rc);
  686. goto unmap_end;
  687. }
  688. }
  689. } else {
  690. for (i = 0; i < num_hdls; i++) {
  691. if (client == CAM_SMMU_MAPPING_USER) {
  692. rc = cam_smmu_unmap_user_iova(mmu_hdls[i],
  693. fd, region);
  694. } else if (client == CAM_SMMU_MAPPING_KERNEL) {
  695. rc = cam_smmu_unmap_kernel_iova(mmu_hdls[i],
  696. tbl.bufq[idx].dma_buf, region);
  697. } else {
  698. CAM_ERR(CAM_MEM,
  699. "invalid caller for unmapping : %d",
  700. client);
  701. rc = -EINVAL;
  702. }
  703. if (rc < 0) {
  704. CAM_ERR(CAM_MEM,
  705. "Failed in unmap, i=%d, fd=%d, mmu_hdl=%d, region=%d, rc=%d",
  706. i, fd, mmu_hdls[i], region, rc);
  707. goto unmap_end;
  708. }
  709. }
  710. }
  711. return rc;
  712. unmap_end:
  713. CAM_ERR(CAM_MEM, "unmapping failed");
  714. return rc;
  715. }
  716. static void cam_mem_mgr_unmap_active_buf(int idx)
  717. {
  718. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  719. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  720. region = CAM_SMMU_REGION_SHARED;
  721. else if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  722. region = CAM_SMMU_REGION_IO;
  723. cam_mem_util_unmap_hw_va(idx, region, CAM_SMMU_MAPPING_USER);
  724. }
  725. static int cam_mem_mgr_cleanup_table(void)
  726. {
  727. int i;
  728. mutex_lock(&tbl.m_lock);
  729. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  730. if (!tbl.bufq[i].active) {
  731. CAM_DBG(CAM_MEM,
  732. "Buffer inactive at idx=%d, continuing", i);
  733. continue;
  734. } else {
  735. CAM_DBG(CAM_MEM,
  736. "Active buffer at idx=%d, possible leak needs unmapping",
  737. i);
  738. cam_mem_mgr_unmap_active_buf(i);
  739. }
  740. mutex_lock(&tbl.bufq[i].q_lock);
  741. if (tbl.bufq[i].dma_buf) {
  742. dma_buf_put(tbl.bufq[i].dma_buf);
  743. tbl.bufq[i].dma_buf = NULL;
  744. }
  745. tbl.bufq[i].fd = -1;
  746. tbl.bufq[i].flags = 0;
  747. tbl.bufq[i].buf_handle = -1;
  748. tbl.bufq[i].vaddr = 0;
  749. tbl.bufq[i].len = 0;
  750. memset(tbl.bufq[i].hdls, 0,
  751. sizeof(int32_t) * tbl.bufq[i].num_hdl);
  752. tbl.bufq[i].num_hdl = 0;
  753. tbl.bufq[i].dma_buf = NULL;
  754. tbl.bufq[i].active = false;
  755. mutex_unlock(&tbl.bufq[i].q_lock);
  756. mutex_destroy(&tbl.bufq[i].q_lock);
  757. }
  758. bitmap_zero(tbl.bitmap, tbl.bits);
  759. /* We need to reserve slot 0 because 0 is invalid */
  760. set_bit(0, tbl.bitmap);
  761. mutex_unlock(&tbl.m_lock);
  762. return 0;
  763. }
  764. void cam_mem_mgr_deinit(void)
  765. {
  766. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_UNINITIALIZED);
  767. cam_mem_mgr_cleanup_table();
  768. mutex_lock(&tbl.m_lock);
  769. bitmap_zero(tbl.bitmap, tbl.bits);
  770. kfree(tbl.bitmap);
  771. tbl.bitmap = NULL;
  772. mutex_unlock(&tbl.m_lock);
  773. mutex_destroy(&tbl.m_lock);
  774. }
  775. static int cam_mem_util_unmap(int32_t idx,
  776. enum cam_smmu_mapping_client client)
  777. {
  778. int rc = 0;
  779. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  780. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  781. CAM_ERR(CAM_MEM, "Incorrect index");
  782. return -EINVAL;
  783. }
  784. CAM_DBG(CAM_MEM, "Flags = %X idx %d", tbl.bufq[idx].flags, idx);
  785. mutex_lock(&tbl.m_lock);
  786. if ((!tbl.bufq[idx].active) &&
  787. (tbl.bufq[idx].vaddr) == 0) {
  788. CAM_WARN(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  789. idx);
  790. mutex_unlock(&tbl.m_lock);
  791. return 0;
  792. }
  793. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS) {
  794. if (tbl.bufq[idx].dma_buf && tbl.bufq[idx].kmdvaddr) {
  795. rc = cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf,
  796. tbl.bufq[idx].kmdvaddr);
  797. if (rc)
  798. CAM_ERR(CAM_MEM,
  799. "Failed, dmabuf=%pK, kmdvaddr=%pK",
  800. tbl.bufq[idx].dma_buf,
  801. (void *) tbl.bufq[idx].kmdvaddr);
  802. }
  803. }
  804. /* SHARED flag gets precedence, all other flags after it */
  805. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  806. region = CAM_SMMU_REGION_SHARED;
  807. } else {
  808. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  809. region = CAM_SMMU_REGION_IO;
  810. }
  811. if ((tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  812. (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  813. (tbl.bufq[idx].flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  814. if (cam_mem_util_unmap_hw_va(idx, region, client))
  815. CAM_ERR(CAM_MEM, "Failed, dmabuf=%pK",
  816. tbl.bufq[idx].dma_buf);
  817. if (client == CAM_SMMU_MAPPING_KERNEL)
  818. tbl.bufq[idx].dma_buf = NULL;
  819. }
  820. mutex_lock(&tbl.bufq[idx].q_lock);
  821. tbl.bufq[idx].flags = 0;
  822. tbl.bufq[idx].buf_handle = -1;
  823. tbl.bufq[idx].vaddr = 0;
  824. memset(tbl.bufq[idx].hdls, 0,
  825. sizeof(int32_t) * CAM_MEM_MMU_MAX_HANDLE);
  826. CAM_DBG(CAM_MEM,
  827. "Ion buf at idx = %d freeing fd = %d, imported %d, dma_buf %pK",
  828. idx, tbl.bufq[idx].fd,
  829. tbl.bufq[idx].is_imported,
  830. tbl.bufq[idx].dma_buf);
  831. if (tbl.bufq[idx].dma_buf)
  832. dma_buf_put(tbl.bufq[idx].dma_buf);
  833. tbl.bufq[idx].fd = -1;
  834. tbl.bufq[idx].dma_buf = NULL;
  835. tbl.bufq[idx].is_imported = false;
  836. tbl.bufq[idx].len = 0;
  837. tbl.bufq[idx].num_hdl = 0;
  838. tbl.bufq[idx].active = false;
  839. mutex_unlock(&tbl.bufq[idx].q_lock);
  840. mutex_destroy(&tbl.bufq[idx].q_lock);
  841. clear_bit(idx, tbl.bitmap);
  842. mutex_unlock(&tbl.m_lock);
  843. return rc;
  844. }
  845. int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd)
  846. {
  847. int idx;
  848. int rc;
  849. if (!atomic_read(&cam_mem_mgr_state)) {
  850. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  851. return -EINVAL;
  852. }
  853. if (!cmd) {
  854. CAM_ERR(CAM_MEM, "Invalid argument");
  855. return -EINVAL;
  856. }
  857. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  858. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  859. CAM_ERR(CAM_MEM, "Incorrect index %d extracted from mem handle",
  860. idx);
  861. return -EINVAL;
  862. }
  863. if (!tbl.bufq[idx].active) {
  864. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  865. return -EINVAL;
  866. }
  867. if (tbl.bufq[idx].buf_handle != cmd->buf_handle) {
  868. CAM_ERR(CAM_MEM,
  869. "Released buf handle %d not matching within table %d, idx=%d",
  870. cmd->buf_handle, tbl.bufq[idx].buf_handle, idx);
  871. return -EINVAL;
  872. }
  873. CAM_DBG(CAM_MEM, "Releasing hdl = %x, idx = %d", cmd->buf_handle, idx);
  874. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_USER);
  875. return rc;
  876. }
  877. int cam_mem_mgr_request_mem(struct cam_mem_mgr_request_desc *inp,
  878. struct cam_mem_mgr_memory_desc *out)
  879. {
  880. struct dma_buf *buf = NULL;
  881. int ion_fd = -1;
  882. int rc = 0;
  883. uint32_t heap_id;
  884. int32_t ion_flag = 0;
  885. uintptr_t kvaddr;
  886. dma_addr_t iova = 0;
  887. size_t request_len = 0;
  888. uint32_t mem_handle;
  889. int32_t idx;
  890. int32_t smmu_hdl = 0;
  891. int32_t num_hdl = 0;
  892. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  893. if (!atomic_read(&cam_mem_mgr_state)) {
  894. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  895. return -EINVAL;
  896. }
  897. if (!inp || !out) {
  898. CAM_ERR(CAM_MEM, "Invalid params");
  899. return -EINVAL;
  900. }
  901. if (!(inp->flags & CAM_MEM_FLAG_HW_READ_WRITE ||
  902. inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS ||
  903. inp->flags & CAM_MEM_FLAG_CACHE)) {
  904. CAM_ERR(CAM_MEM, "Invalid flags for request mem");
  905. return -EINVAL;
  906. }
  907. if (inp->flags & CAM_MEM_FLAG_CACHE)
  908. ion_flag |= ION_FLAG_CACHED;
  909. else
  910. ion_flag &= ~ION_FLAG_CACHED;
  911. heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) |
  912. ION_HEAP(ION_CAMERA_HEAP_ID);
  913. rc = cam_mem_util_get_dma_buf(inp->size,
  914. heap_id,
  915. ion_flag,
  916. &buf);
  917. if (rc) {
  918. CAM_ERR(CAM_MEM, "ION alloc failed for shared buffer");
  919. goto ion_fail;
  920. } else {
  921. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  922. }
  923. /*
  924. * we are mapping kva always here,
  925. * update flags so that we do unmap properly
  926. */
  927. inp->flags |= CAM_MEM_FLAG_KMD_ACCESS;
  928. rc = cam_mem_util_map_cpu_va(buf, &kvaddr, &request_len);
  929. if (rc) {
  930. CAM_ERR(CAM_MEM, "Failed to get kernel vaddr");
  931. goto map_fail;
  932. }
  933. if (!inp->smmu_hdl) {
  934. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  935. rc = -EINVAL;
  936. goto smmu_fail;
  937. }
  938. /* SHARED flag gets precedence, all other flags after it */
  939. if (inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  940. region = CAM_SMMU_REGION_SHARED;
  941. } else {
  942. if (inp->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  943. region = CAM_SMMU_REGION_IO;
  944. }
  945. rc = cam_smmu_map_kernel_iova(inp->smmu_hdl,
  946. buf,
  947. CAM_SMMU_MAP_RW,
  948. &iova,
  949. &request_len,
  950. region);
  951. if (rc < 0) {
  952. CAM_ERR(CAM_MEM, "SMMU mapping failed");
  953. goto smmu_fail;
  954. }
  955. smmu_hdl = inp->smmu_hdl;
  956. num_hdl = 1;
  957. idx = cam_mem_get_slot();
  958. if (idx < 0) {
  959. rc = -ENOMEM;
  960. goto slot_fail;
  961. }
  962. mutex_lock(&tbl.bufq[idx].q_lock);
  963. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  964. tbl.bufq[idx].dma_buf = buf;
  965. tbl.bufq[idx].fd = -1;
  966. tbl.bufq[idx].flags = inp->flags;
  967. tbl.bufq[idx].buf_handle = mem_handle;
  968. tbl.bufq[idx].kmdvaddr = kvaddr;
  969. tbl.bufq[idx].vaddr = iova;
  970. tbl.bufq[idx].len = inp->size;
  971. tbl.bufq[idx].num_hdl = num_hdl;
  972. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  973. sizeof(int32_t));
  974. tbl.bufq[idx].is_imported = false;
  975. mutex_unlock(&tbl.bufq[idx].q_lock);
  976. out->kva = kvaddr;
  977. out->iova = (uint32_t)iova;
  978. out->smmu_hdl = smmu_hdl;
  979. out->mem_handle = mem_handle;
  980. out->len = inp->size;
  981. out->region = region;
  982. return rc;
  983. slot_fail:
  984. cam_smmu_unmap_kernel_iova(inp->smmu_hdl,
  985. buf, region);
  986. smmu_fail:
  987. cam_mem_util_unmap_cpu_va(buf, kvaddr);
  988. map_fail:
  989. dma_buf_put(buf);
  990. ion_fail:
  991. return rc;
  992. }
  993. EXPORT_SYMBOL(cam_mem_mgr_request_mem);
  994. int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp)
  995. {
  996. int32_t idx;
  997. int rc;
  998. if (!atomic_read(&cam_mem_mgr_state)) {
  999. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1000. return -EINVAL;
  1001. }
  1002. if (!inp) {
  1003. CAM_ERR(CAM_MEM, "Invalid argument");
  1004. return -EINVAL;
  1005. }
  1006. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1007. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1008. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1009. return -EINVAL;
  1010. }
  1011. if (!tbl.bufq[idx].active) {
  1012. if (tbl.bufq[idx].vaddr == 0) {
  1013. CAM_ERR(CAM_MEM, "buffer is released already");
  1014. return 0;
  1015. }
  1016. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1017. return -EINVAL;
  1018. }
  1019. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1020. CAM_ERR(CAM_MEM,
  1021. "Released buf handle not matching within table");
  1022. return -EINVAL;
  1023. }
  1024. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1025. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1026. return rc;
  1027. }
  1028. EXPORT_SYMBOL(cam_mem_mgr_release_mem);
  1029. int cam_mem_mgr_reserve_memory_region(struct cam_mem_mgr_request_desc *inp,
  1030. enum cam_smmu_region_id region,
  1031. struct cam_mem_mgr_memory_desc *out)
  1032. {
  1033. struct dma_buf *buf = NULL;
  1034. int rc = 0;
  1035. int ion_fd = -1;
  1036. uint32_t heap_id;
  1037. dma_addr_t iova = 0;
  1038. size_t request_len = 0;
  1039. uint32_t mem_handle;
  1040. int32_t idx;
  1041. int32_t smmu_hdl = 0;
  1042. int32_t num_hdl = 0;
  1043. if (!atomic_read(&cam_mem_mgr_state)) {
  1044. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1045. return -EINVAL;
  1046. }
  1047. if (!inp || !out) {
  1048. CAM_ERR(CAM_MEM, "Invalid param(s)");
  1049. return -EINVAL;
  1050. }
  1051. if (!inp->smmu_hdl) {
  1052. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1053. return -EINVAL;
  1054. }
  1055. if (region != CAM_SMMU_REGION_SECHEAP) {
  1056. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1057. return -EINVAL;
  1058. }
  1059. heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) |
  1060. ION_HEAP(ION_CAMERA_HEAP_ID);
  1061. rc = cam_mem_util_get_dma_buf(inp->size,
  1062. heap_id,
  1063. 0,
  1064. &buf);
  1065. if (rc) {
  1066. CAM_ERR(CAM_MEM, "ION alloc failed for sec heap buffer");
  1067. goto ion_fail;
  1068. } else {
  1069. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1070. }
  1071. rc = cam_smmu_reserve_sec_heap(inp->smmu_hdl,
  1072. buf,
  1073. &iova,
  1074. &request_len);
  1075. if (rc) {
  1076. CAM_ERR(CAM_MEM, "Reserving secondary heap failed");
  1077. goto smmu_fail;
  1078. }
  1079. smmu_hdl = inp->smmu_hdl;
  1080. num_hdl = 1;
  1081. idx = cam_mem_get_slot();
  1082. if (idx < 0) {
  1083. rc = -ENOMEM;
  1084. goto slot_fail;
  1085. }
  1086. mutex_lock(&tbl.bufq[idx].q_lock);
  1087. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1088. tbl.bufq[idx].fd = -1;
  1089. tbl.bufq[idx].dma_buf = buf;
  1090. tbl.bufq[idx].flags = inp->flags;
  1091. tbl.bufq[idx].buf_handle = mem_handle;
  1092. tbl.bufq[idx].kmdvaddr = 0;
  1093. tbl.bufq[idx].vaddr = iova;
  1094. tbl.bufq[idx].len = request_len;
  1095. tbl.bufq[idx].num_hdl = num_hdl;
  1096. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1097. sizeof(int32_t));
  1098. tbl.bufq[idx].is_imported = false;
  1099. mutex_unlock(&tbl.bufq[idx].q_lock);
  1100. out->kva = 0;
  1101. out->iova = (uint32_t)iova;
  1102. out->smmu_hdl = smmu_hdl;
  1103. out->mem_handle = mem_handle;
  1104. out->len = request_len;
  1105. out->region = region;
  1106. return rc;
  1107. slot_fail:
  1108. cam_smmu_release_sec_heap(smmu_hdl);
  1109. smmu_fail:
  1110. dma_buf_put(buf);
  1111. ion_fail:
  1112. return rc;
  1113. }
  1114. EXPORT_SYMBOL(cam_mem_mgr_reserve_memory_region);
  1115. int cam_mem_mgr_free_memory_region(struct cam_mem_mgr_memory_desc *inp)
  1116. {
  1117. int32_t idx;
  1118. int rc;
  1119. int32_t smmu_hdl;
  1120. if (!atomic_read(&cam_mem_mgr_state)) {
  1121. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1122. return -EINVAL;
  1123. }
  1124. if (!inp) {
  1125. CAM_ERR(CAM_MEM, "Invalid argument");
  1126. return -EINVAL;
  1127. }
  1128. if (inp->region != CAM_SMMU_REGION_SECHEAP) {
  1129. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1130. return -EINVAL;
  1131. }
  1132. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1133. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1134. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1135. return -EINVAL;
  1136. }
  1137. if (!tbl.bufq[idx].active) {
  1138. if (tbl.bufq[idx].vaddr == 0) {
  1139. CAM_ERR(CAM_MEM, "buffer is released already");
  1140. return 0;
  1141. }
  1142. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1143. return -EINVAL;
  1144. }
  1145. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1146. CAM_ERR(CAM_MEM,
  1147. "Released buf handle not matching within table");
  1148. return -EINVAL;
  1149. }
  1150. if (tbl.bufq[idx].num_hdl != 1) {
  1151. CAM_ERR(CAM_MEM,
  1152. "Sec heap region should have only one smmu hdl");
  1153. return -ENODEV;
  1154. }
  1155. memcpy(&smmu_hdl, tbl.bufq[idx].hdls,
  1156. sizeof(int32_t));
  1157. if (inp->smmu_hdl != smmu_hdl) {
  1158. CAM_ERR(CAM_MEM,
  1159. "Passed SMMU handle doesn't match with internal hdl");
  1160. return -ENODEV;
  1161. }
  1162. rc = cam_smmu_release_sec_heap(inp->smmu_hdl);
  1163. if (rc) {
  1164. CAM_ERR(CAM_MEM,
  1165. "Sec heap region release failed");
  1166. return -ENODEV;
  1167. }
  1168. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1169. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1170. if (rc)
  1171. CAM_ERR(CAM_MEM, "unmapping secondary heap failed");
  1172. return rc;
  1173. }
  1174. EXPORT_SYMBOL(cam_mem_mgr_free_memory_region);