dsi_ctrl.c 109 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/of_device.h>
  6. #include <linux/err.h>
  7. #include <linux/regulator/consumer.h>
  8. #include <linux/clk.h>
  9. #include <linux/of_irq.h>
  10. #include <video/mipi_display.h>
  11. #include "msm_drv.h"
  12. #include "msm_kms.h"
  13. #include "msm_mmu.h"
  14. #include "dsi_ctrl.h"
  15. #include "dsi_ctrl_hw.h"
  16. #include "dsi_clk.h"
  17. #include "dsi_pwr.h"
  18. #include "dsi_catalog.h"
  19. #include "dsi_panel.h"
  20. #include "sde_dbg.h"
  21. #define DSI_CTRL_DEFAULT_LABEL "MDSS DSI CTRL"
  22. #define DSI_CTRL_TX_TO_MS 200
  23. #define TO_ON_OFF(x) ((x) ? "ON" : "OFF")
  24. #define CEIL(x, y) (((x) + ((y)-1)) / (y))
  25. #define TICKS_IN_MICRO_SECOND 1000000
  26. #define DSI_CTRL_DEBUG(c, fmt, ...) DRM_DEV_DEBUG(NULL, "[msm-dsi-debug]: %s: "\
  27. fmt, c ? c->name : "inv", ##__VA_ARGS__)
  28. #define DSI_CTRL_ERR(c, fmt, ...) DRM_DEV_ERROR(NULL, "[msm-dsi-error]: %s: "\
  29. fmt, c ? c->name : "inv", ##__VA_ARGS__)
  30. #define DSI_CTRL_INFO(c, fmt, ...) DRM_DEV_INFO(NULL, "[msm-dsi-info]: %s: "\
  31. fmt, c->name, ##__VA_ARGS__)
  32. #define DSI_CTRL_WARN(c, fmt, ...) DRM_WARN("[msm-dsi-warn]: %s: " fmt,\
  33. c ? c->name : "inv", ##__VA_ARGS__)
  34. struct dsi_ctrl_list_item {
  35. struct dsi_ctrl *ctrl;
  36. struct list_head list;
  37. };
  38. static LIST_HEAD(dsi_ctrl_list);
  39. static DEFINE_MUTEX(dsi_ctrl_list_lock);
  40. static const enum dsi_ctrl_version dsi_ctrl_v1_4 = DSI_CTRL_VERSION_1_4;
  41. static const enum dsi_ctrl_version dsi_ctrl_v2_0 = DSI_CTRL_VERSION_2_0;
  42. static const enum dsi_ctrl_version dsi_ctrl_v2_2 = DSI_CTRL_VERSION_2_2;
  43. static const enum dsi_ctrl_version dsi_ctrl_v2_3 = DSI_CTRL_VERSION_2_3;
  44. static const enum dsi_ctrl_version dsi_ctrl_v2_4 = DSI_CTRL_VERSION_2_4;
  45. static const enum dsi_ctrl_version dsi_ctrl_v2_5 = DSI_CTRL_VERSION_2_5;
  46. static const enum dsi_ctrl_version dsi_ctrl_v2_6 = DSI_CTRL_VERSION_2_6;
  47. static const struct of_device_id msm_dsi_of_match[] = {
  48. {
  49. .compatible = "qcom,dsi-ctrl-hw-v1.4",
  50. .data = &dsi_ctrl_v1_4,
  51. },
  52. {
  53. .compatible = "qcom,dsi-ctrl-hw-v2.0",
  54. .data = &dsi_ctrl_v2_0,
  55. },
  56. {
  57. .compatible = "qcom,dsi-ctrl-hw-v2.2",
  58. .data = &dsi_ctrl_v2_2,
  59. },
  60. {
  61. .compatible = "qcom,dsi-ctrl-hw-v2.3",
  62. .data = &dsi_ctrl_v2_3,
  63. },
  64. {
  65. .compatible = "qcom,dsi-ctrl-hw-v2.4",
  66. .data = &dsi_ctrl_v2_4,
  67. },
  68. {
  69. .compatible = "qcom,dsi-ctrl-hw-v2.5",
  70. .data = &dsi_ctrl_v2_5,
  71. },
  72. {
  73. .compatible = "qcom,dsi-ctrl-hw-v2.6",
  74. .data = &dsi_ctrl_v2_6,
  75. },
  76. {}
  77. };
  78. #ifdef CONFIG_DEBUG_FS
  79. static ssize_t debugfs_state_info_read(struct file *file,
  80. char __user *buff,
  81. size_t count,
  82. loff_t *ppos)
  83. {
  84. struct dsi_ctrl *dsi_ctrl = file->private_data;
  85. char *buf;
  86. u32 len = 0;
  87. if (!dsi_ctrl)
  88. return -ENODEV;
  89. if (*ppos)
  90. return 0;
  91. buf = kzalloc(SZ_4K, GFP_KERNEL);
  92. if (!buf)
  93. return -ENOMEM;
  94. /* Dump current state */
  95. len += snprintf((buf + len), (SZ_4K - len), "Current State:\n");
  96. len += snprintf((buf + len), (SZ_4K - len),
  97. "\tCTRL_ENGINE = %s\n",
  98. TO_ON_OFF(dsi_ctrl->current_state.controller_state));
  99. len += snprintf((buf + len), (SZ_4K - len),
  100. "\tVIDEO_ENGINE = %s\n\tCOMMAND_ENGINE = %s\n",
  101. TO_ON_OFF(dsi_ctrl->current_state.vid_engine_state),
  102. TO_ON_OFF(dsi_ctrl->current_state.cmd_engine_state));
  103. /* Dump clock information */
  104. len += snprintf((buf + len), (SZ_4K - len), "\nClock Info:\n");
  105. len += snprintf((buf + len), (SZ_4K - len),
  106. "\tBYTE_CLK = %u, PIXEL_CLK = %u, ESC_CLK = %u\n",
  107. dsi_ctrl->clk_freq.byte_clk_rate,
  108. dsi_ctrl->clk_freq.pix_clk_rate,
  109. dsi_ctrl->clk_freq.esc_clk_rate);
  110. if (len > count)
  111. len = count;
  112. len = min_t(size_t, len, SZ_4K);
  113. if (copy_to_user(buff, buf, len)) {
  114. kfree(buf);
  115. return -EFAULT;
  116. }
  117. *ppos += len;
  118. kfree(buf);
  119. return len;
  120. }
  121. static ssize_t debugfs_reg_dump_read(struct file *file,
  122. char __user *buff,
  123. size_t count,
  124. loff_t *ppos)
  125. {
  126. struct dsi_ctrl *dsi_ctrl = file->private_data;
  127. char *buf;
  128. u32 len = 0;
  129. struct dsi_clk_ctrl_info clk_info;
  130. int rc = 0;
  131. if (!dsi_ctrl)
  132. return -ENODEV;
  133. if (*ppos)
  134. return 0;
  135. buf = kzalloc(SZ_4K, GFP_KERNEL);
  136. if (!buf)
  137. return -ENOMEM;
  138. clk_info.client = DSI_CLK_REQ_DSI_CLIENT;
  139. clk_info.clk_type = DSI_CORE_CLK;
  140. clk_info.clk_state = DSI_CLK_ON;
  141. rc = dsi_ctrl->clk_cb.dsi_clk_cb(dsi_ctrl->clk_cb.priv, clk_info);
  142. if (rc) {
  143. DSI_CTRL_ERR(dsi_ctrl, "failed to enable DSI core clocks\n");
  144. kfree(buf);
  145. return rc;
  146. }
  147. if (dsi_ctrl->hw.ops.reg_dump_to_buffer)
  148. len = dsi_ctrl->hw.ops.reg_dump_to_buffer(&dsi_ctrl->hw,
  149. buf, SZ_4K);
  150. clk_info.clk_state = DSI_CLK_OFF;
  151. rc = dsi_ctrl->clk_cb.dsi_clk_cb(dsi_ctrl->clk_cb.priv, clk_info);
  152. if (rc) {
  153. DSI_CTRL_ERR(dsi_ctrl, "failed to disable DSI core clocks\n");
  154. kfree(buf);
  155. return rc;
  156. }
  157. if (len > count)
  158. len = count;
  159. len = min_t(size_t, len, SZ_4K);
  160. if (copy_to_user(buff, buf, len)) {
  161. kfree(buf);
  162. return -EFAULT;
  163. }
  164. *ppos += len;
  165. kfree(buf);
  166. return len;
  167. }
  168. static ssize_t debugfs_line_count_read(struct file *file,
  169. char __user *user_buf,
  170. size_t user_len,
  171. loff_t *ppos)
  172. {
  173. struct dsi_ctrl *dsi_ctrl = file->private_data;
  174. char *buf;
  175. int rc = 0;
  176. u32 len = 0;
  177. size_t max_len = min_t(size_t, user_len, SZ_4K);
  178. if (!dsi_ctrl)
  179. return -ENODEV;
  180. if (*ppos)
  181. return 0;
  182. buf = kzalloc(max_len, GFP_KERNEL);
  183. if (ZERO_OR_NULL_PTR(buf))
  184. return -ENOMEM;
  185. mutex_lock(&dsi_ctrl->ctrl_lock);
  186. len += scnprintf(buf, max_len, "Command triggered at line: %04x\n",
  187. dsi_ctrl->cmd_trigger_line);
  188. len += scnprintf((buf + len), max_len - len,
  189. "Command triggered at frame: %04x\n",
  190. dsi_ctrl->cmd_trigger_frame);
  191. len += scnprintf((buf + len), max_len - len,
  192. "Command successful at line: %04x\n",
  193. dsi_ctrl->cmd_success_line);
  194. len += scnprintf((buf + len), max_len - len,
  195. "Command successful at frame: %04x\n",
  196. dsi_ctrl->cmd_success_frame);
  197. mutex_unlock(&dsi_ctrl->ctrl_lock);
  198. if (len > max_len)
  199. len = max_len;
  200. if (copy_to_user(user_buf, buf, len)) {
  201. rc = -EFAULT;
  202. goto error;
  203. }
  204. *ppos += len;
  205. error:
  206. kfree(buf);
  207. return len;
  208. }
  209. static const struct file_operations state_info_fops = {
  210. .open = simple_open,
  211. .read = debugfs_state_info_read,
  212. };
  213. static const struct file_operations reg_dump_fops = {
  214. .open = simple_open,
  215. .read = debugfs_reg_dump_read,
  216. };
  217. static const struct file_operations cmd_dma_stats_fops = {
  218. .open = simple_open,
  219. .read = debugfs_line_count_read,
  220. };
  221. static int dsi_ctrl_debugfs_init(struct dsi_ctrl *dsi_ctrl,
  222. struct dentry *parent)
  223. {
  224. int rc = 0;
  225. struct dentry *dir, *state_file, *reg_dump, *cmd_dma_logs;
  226. if (!dsi_ctrl || !parent) {
  227. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  228. return -EINVAL;
  229. }
  230. dir = debugfs_create_dir(dsi_ctrl->name, parent);
  231. if (IS_ERR_OR_NULL(dir)) {
  232. rc = PTR_ERR(dir);
  233. DSI_CTRL_ERR(dsi_ctrl, "debugfs create dir failed, rc=%d\n",
  234. rc);
  235. goto error;
  236. }
  237. state_file = debugfs_create_file("state_info",
  238. 0444,
  239. dir,
  240. dsi_ctrl,
  241. &state_info_fops);
  242. if (IS_ERR_OR_NULL(state_file)) {
  243. rc = PTR_ERR(state_file);
  244. DSI_CTRL_ERR(dsi_ctrl, "state file failed, rc=%d\n", rc);
  245. goto error_remove_dir;
  246. }
  247. reg_dump = debugfs_create_file("reg_dump",
  248. 0444,
  249. dir,
  250. dsi_ctrl,
  251. &reg_dump_fops);
  252. if (IS_ERR_OR_NULL(reg_dump)) {
  253. rc = PTR_ERR(reg_dump);
  254. DSI_CTRL_ERR(dsi_ctrl, "reg dump file failed, rc=%d\n", rc);
  255. goto error_remove_dir;
  256. }
  257. cmd_dma_logs = debugfs_create_bool("enable_cmd_dma_stats",
  258. 0600,
  259. dir,
  260. &dsi_ctrl->enable_cmd_dma_stats);
  261. if (IS_ERR_OR_NULL(cmd_dma_logs)) {
  262. rc = PTR_ERR(cmd_dma_logs);
  263. DSI_CTRL_ERR(dsi_ctrl,
  264. "enable cmd dma stats failed, rc=%d\n",
  265. rc);
  266. goto error_remove_dir;
  267. }
  268. cmd_dma_logs = debugfs_create_file("cmd_dma_stats",
  269. 0444,
  270. dir,
  271. dsi_ctrl,
  272. &cmd_dma_stats_fops);
  273. if (IS_ERR_OR_NULL(cmd_dma_logs)) {
  274. rc = PTR_ERR(cmd_dma_logs);
  275. DSI_CTRL_ERR(dsi_ctrl, "Line count file failed, rc=%d\n",
  276. rc);
  277. goto error_remove_dir;
  278. }
  279. dsi_ctrl->debugfs_root = dir;
  280. return rc;
  281. error_remove_dir:
  282. debugfs_remove(dir);
  283. error:
  284. return rc;
  285. }
  286. static int dsi_ctrl_debugfs_deinit(struct dsi_ctrl *dsi_ctrl)
  287. {
  288. if (dsi_ctrl->debugfs_root) {
  289. debugfs_remove(dsi_ctrl->debugfs_root);
  290. dsi_ctrl->debugfs_root = NULL;
  291. }
  292. return 0;
  293. }
  294. #else
  295. static int dsi_ctrl_debugfs_init(struct dsi_ctrl *dsi_ctrl, struct dentry *parent)
  296. {
  297. return 0;
  298. }
  299. static int dsi_ctrl_debugfs_deinit(struct dsi_ctrl *dsi_ctrl)
  300. {
  301. return 0;
  302. }
  303. #endif /* CONFIG_DEBUG_FS */
  304. static inline struct msm_gem_address_space*
  305. dsi_ctrl_get_aspace(struct dsi_ctrl *dsi_ctrl,
  306. int domain)
  307. {
  308. if (!dsi_ctrl || !dsi_ctrl->drm_dev)
  309. return NULL;
  310. return msm_gem_smmu_address_space_get(dsi_ctrl->drm_dev, domain);
  311. }
  312. static void dsi_ctrl_dma_cmd_wait_for_done(struct dsi_ctrl *dsi_ctrl)
  313. {
  314. int ret = 0;
  315. u32 status;
  316. u32 mask = DSI_CMD_MODE_DMA_DONE;
  317. struct dsi_ctrl_hw_ops dsi_hw_ops;
  318. dsi_hw_ops = dsi_ctrl->hw.ops;
  319. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY);
  320. /*
  321. * This atomic state will be set if ISR has been triggered,
  322. * so the wait is not needed.
  323. */
  324. if (atomic_read(&dsi_ctrl->dma_irq_trig))
  325. return;
  326. ret = wait_for_completion_timeout(
  327. &dsi_ctrl->irq_info.cmd_dma_done,
  328. msecs_to_jiffies(DSI_CTRL_TX_TO_MS));
  329. if (ret == 0 && !atomic_read(&dsi_ctrl->dma_irq_trig)) {
  330. status = dsi_hw_ops.get_interrupt_status(&dsi_ctrl->hw);
  331. if (status & mask) {
  332. status |= (DSI_CMD_MODE_DMA_DONE | DSI_BTA_DONE);
  333. dsi_hw_ops.clear_interrupt_status(&dsi_ctrl->hw,
  334. status);
  335. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_CASE1);
  336. DSI_CTRL_WARN(dsi_ctrl,
  337. "dma_tx done but irq not triggered\n");
  338. } else {
  339. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_ERROR);
  340. DSI_CTRL_ERR(dsi_ctrl,
  341. "Command transfer failed\n");
  342. }
  343. dsi_ctrl_disable_status_interrupt(dsi_ctrl,
  344. DSI_SINT_CMD_MODE_DMA_DONE);
  345. }
  346. }
  347. static void dsi_ctrl_post_cmd_transfer(struct dsi_ctrl *dsi_ctrl)
  348. {
  349. int rc = 0;
  350. struct dsi_clk_ctrl_info clk_info;
  351. bool skip_wait_for_done = false;
  352. u32 mask = BIT(DSI_FIFO_OVERFLOW);
  353. mutex_lock(&dsi_ctrl->ctrl_lock);
  354. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, dsi_ctrl->cell_index, dsi_ctrl->pending_cmd_flags);
  355. /* In case of broadcast messages, we needn't wait on the slave controller */
  356. if ((dsi_ctrl->pending_cmd_flags & DSI_CTRL_CMD_BROADCAST) &&
  357. !(dsi_ctrl->pending_cmd_flags & DSI_CTRL_CMD_BROADCAST_MASTER))
  358. skip_wait_for_done = true;
  359. if (!skip_wait_for_done)
  360. dsi_ctrl_dma_cmd_wait_for_done(dsi_ctrl);
  361. /* Command engine disable, unmask overflow, remove vote on clocks and gdsc */
  362. rc = dsi_ctrl_set_cmd_engine_state(dsi_ctrl, DSI_CTRL_ENGINE_OFF, false);
  363. if (rc)
  364. DSI_CTRL_ERR(dsi_ctrl, "failed to disable command engine\n");
  365. if (dsi_ctrl->pending_cmd_flags & DSI_CTRL_CMD_READ)
  366. mask |= BIT(DSI_FIFO_UNDERFLOW);
  367. dsi_ctrl_mask_error_status_interrupts(dsi_ctrl, mask, false);
  368. mutex_unlock(&dsi_ctrl->ctrl_lock);
  369. clk_info.client = DSI_CLK_REQ_DSI_CLIENT;
  370. clk_info.clk_type = DSI_ALL_CLKS;
  371. clk_info.clk_state = DSI_CLK_OFF;
  372. rc = dsi_ctrl->clk_cb.dsi_clk_cb(dsi_ctrl->clk_cb.priv, clk_info);
  373. if (rc)
  374. DSI_CTRL_ERR(dsi_ctrl, "failed to disable clocks\n");
  375. (void)pm_runtime_put_sync(dsi_ctrl->drm_dev->dev);
  376. }
  377. static void dsi_ctrl_post_cmd_transfer_work(struct work_struct *work)
  378. {
  379. struct dsi_ctrl *dsi_ctrl = NULL;
  380. dsi_ctrl = container_of(work, struct dsi_ctrl, post_cmd_tx_work);
  381. dsi_ctrl_post_cmd_transfer(dsi_ctrl);
  382. dsi_ctrl->post_tx_queued = false;
  383. }
  384. static void dsi_ctrl_flush_cmd_dma_queue(struct dsi_ctrl *dsi_ctrl)
  385. {
  386. /*
  387. * If a command is triggered right after another command,
  388. * check if the previous command transfer is completed. If
  389. * transfer is done, cancel any work that has been
  390. * queued. Otherwise wait till the work is scheduled and
  391. * completed before triggering the next command by
  392. * flushing the workqueue.
  393. *
  394. * cancel_work_sync returns true if the work has not yet been scheduled, in that case as
  395. * we are cancelling the work we need to explicitly call the post_cmd_transfer API to
  396. * clean up the states.
  397. */
  398. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  399. if (atomic_read(&dsi_ctrl->dma_irq_trig)) {
  400. if (cancel_work_sync(&dsi_ctrl->post_cmd_tx_work)) {
  401. dsi_ctrl_post_cmd_transfer(dsi_ctrl);
  402. dsi_ctrl->post_tx_queued = false;
  403. }
  404. } else {
  405. flush_workqueue(dsi_ctrl->post_cmd_tx_workq);
  406. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2);
  407. }
  408. }
  409. static int dsi_ctrl_check_state(struct dsi_ctrl *dsi_ctrl,
  410. enum dsi_ctrl_driver_ops op,
  411. u32 op_state)
  412. {
  413. int rc = 0;
  414. struct dsi_ctrl_state_info *state = &dsi_ctrl->current_state;
  415. SDE_EVT32_VERBOSE(dsi_ctrl->cell_index, op, op_state);
  416. switch (op) {
  417. case DSI_CTRL_OP_POWER_STATE_CHANGE:
  418. if (state->power_state == op_state) {
  419. DSI_CTRL_ERR(dsi_ctrl, "No change in state, pwr_state=%d\n",
  420. op_state);
  421. rc = -EINVAL;
  422. } else if (state->power_state == DSI_CTRL_POWER_VREG_ON) {
  423. if (state->vid_engine_state == DSI_CTRL_ENGINE_ON) {
  424. DSI_CTRL_ERR(dsi_ctrl, "State error: op=%d: %d\n",
  425. op_state,
  426. state->vid_engine_state);
  427. rc = -EINVAL;
  428. }
  429. }
  430. break;
  431. case DSI_CTRL_OP_CMD_ENGINE:
  432. if (state->cmd_engine_state == op_state) {
  433. DSI_CTRL_ERR(dsi_ctrl, "No change in state, cmd_state=%d\n",
  434. op_state);
  435. rc = -EINVAL;
  436. } else if ((state->power_state != DSI_CTRL_POWER_VREG_ON) ||
  437. (state->controller_state != DSI_CTRL_ENGINE_ON)) {
  438. DSI_CTRL_ERR(dsi_ctrl, "State error: op=%d: %d, %d\n",
  439. op,
  440. state->power_state,
  441. state->controller_state);
  442. rc = -EINVAL;
  443. }
  444. break;
  445. case DSI_CTRL_OP_VID_ENGINE:
  446. if (state->vid_engine_state == op_state) {
  447. DSI_CTRL_ERR(dsi_ctrl, "No change in state, cmd_state=%d\n",
  448. op_state);
  449. rc = -EINVAL;
  450. } else if ((state->power_state != DSI_CTRL_POWER_VREG_ON) ||
  451. (state->controller_state != DSI_CTRL_ENGINE_ON)) {
  452. DSI_CTRL_ERR(dsi_ctrl, "State error: op=%d: %d, %d\n",
  453. op,
  454. state->power_state,
  455. state->controller_state);
  456. rc = -EINVAL;
  457. }
  458. break;
  459. case DSI_CTRL_OP_HOST_ENGINE:
  460. if (state->controller_state == op_state) {
  461. DSI_CTRL_ERR(dsi_ctrl, "No change in state, ctrl_state=%d\n",
  462. op_state);
  463. rc = -EINVAL;
  464. } else if (state->power_state != DSI_CTRL_POWER_VREG_ON) {
  465. DSI_CTRL_ERR(dsi_ctrl, "State error (link is off): op=%d:, %d\n",
  466. op_state,
  467. state->power_state);
  468. rc = -EINVAL;
  469. } else if ((op_state == DSI_CTRL_ENGINE_OFF) &&
  470. ((state->cmd_engine_state != DSI_CTRL_ENGINE_OFF) ||
  471. (state->vid_engine_state != DSI_CTRL_ENGINE_OFF))) {
  472. DSI_CTRL_ERR(dsi_ctrl, "State error (eng on): op=%d: %d, %d\n",
  473. op_state,
  474. state->cmd_engine_state,
  475. state->vid_engine_state);
  476. rc = -EINVAL;
  477. }
  478. break;
  479. case DSI_CTRL_OP_CMD_TX:
  480. if ((state->power_state != DSI_CTRL_POWER_VREG_ON) ||
  481. (!state->host_initialized) ||
  482. (state->cmd_engine_state != DSI_CTRL_ENGINE_ON)) {
  483. DSI_CTRL_ERR(dsi_ctrl, "State error: op=%d: %d, %d, %d\n",
  484. op,
  485. state->power_state,
  486. state->host_initialized,
  487. state->cmd_engine_state);
  488. rc = -EINVAL;
  489. }
  490. break;
  491. case DSI_CTRL_OP_HOST_INIT:
  492. if (state->host_initialized == op_state) {
  493. DSI_CTRL_ERR(dsi_ctrl, "No change in state, host_init=%d\n",
  494. op_state);
  495. rc = -EINVAL;
  496. } else if (state->power_state != DSI_CTRL_POWER_VREG_ON) {
  497. DSI_CTRL_ERR(dsi_ctrl, "State error: op=%d: %d\n",
  498. op, state->power_state);
  499. rc = -EINVAL;
  500. }
  501. break;
  502. case DSI_CTRL_OP_TPG:
  503. if (state->tpg_enabled == op_state) {
  504. DSI_CTRL_ERR(dsi_ctrl, "No change in state, tpg_enabled=%d\n",
  505. op_state);
  506. rc = -EINVAL;
  507. } else if ((state->power_state != DSI_CTRL_POWER_VREG_ON) ||
  508. (state->controller_state != DSI_CTRL_ENGINE_ON)) {
  509. DSI_CTRL_ERR(dsi_ctrl, "State error: op=%d: %d, %d\n",
  510. op,
  511. state->power_state,
  512. state->controller_state);
  513. rc = -EINVAL;
  514. }
  515. break;
  516. case DSI_CTRL_OP_PHY_SW_RESET:
  517. if (state->power_state != DSI_CTRL_POWER_VREG_ON) {
  518. DSI_CTRL_ERR(dsi_ctrl, "State error: op=%d: %d\n",
  519. op, state->power_state);
  520. rc = -EINVAL;
  521. }
  522. break;
  523. case DSI_CTRL_OP_ASYNC_TIMING:
  524. if (state->vid_engine_state != op_state) {
  525. DSI_CTRL_ERR(dsi_ctrl, "Unexpected engine state vid_state=%d\n",
  526. op_state);
  527. rc = -EINVAL;
  528. }
  529. break;
  530. default:
  531. rc = -ENOTSUPP;
  532. break;
  533. }
  534. return rc;
  535. }
  536. bool dsi_ctrl_validate_host_state(struct dsi_ctrl *dsi_ctrl)
  537. {
  538. struct dsi_ctrl_state_info *state = &dsi_ctrl->current_state;
  539. if (!state) {
  540. DSI_CTRL_ERR(dsi_ctrl, "Invalid host state for DSI controller\n");
  541. return -EINVAL;
  542. }
  543. if (!state->host_initialized)
  544. return false;
  545. return true;
  546. }
  547. static void dsi_ctrl_update_state(struct dsi_ctrl *dsi_ctrl,
  548. enum dsi_ctrl_driver_ops op,
  549. u32 op_state)
  550. {
  551. struct dsi_ctrl_state_info *state = &dsi_ctrl->current_state;
  552. switch (op) {
  553. case DSI_CTRL_OP_POWER_STATE_CHANGE:
  554. state->power_state = op_state;
  555. break;
  556. case DSI_CTRL_OP_CMD_ENGINE:
  557. state->cmd_engine_state = op_state;
  558. break;
  559. case DSI_CTRL_OP_VID_ENGINE:
  560. state->vid_engine_state = op_state;
  561. break;
  562. case DSI_CTRL_OP_HOST_ENGINE:
  563. state->controller_state = op_state;
  564. break;
  565. case DSI_CTRL_OP_HOST_INIT:
  566. state->host_initialized = (op_state == 1) ? true : false;
  567. break;
  568. case DSI_CTRL_OP_TPG:
  569. state->tpg_enabled = (op_state == 1) ? true : false;
  570. break;
  571. case DSI_CTRL_OP_CMD_TX:
  572. case DSI_CTRL_OP_PHY_SW_RESET:
  573. default:
  574. break;
  575. }
  576. }
  577. static int dsi_ctrl_init_regmap(struct platform_device *pdev,
  578. struct dsi_ctrl *ctrl)
  579. {
  580. int rc = 0;
  581. void __iomem *ptr;
  582. ptr = msm_ioremap(pdev, "dsi_ctrl", ctrl->name);
  583. if (IS_ERR(ptr)) {
  584. rc = PTR_ERR(ptr);
  585. return rc;
  586. }
  587. ctrl->hw.base = ptr;
  588. DSI_CTRL_DEBUG(ctrl, "map dsi_ctrl registers to %pK\n", ctrl->hw.base);
  589. switch (ctrl->version) {
  590. case DSI_CTRL_VERSION_1_4:
  591. case DSI_CTRL_VERSION_2_0:
  592. ptr = msm_ioremap(pdev, "mmss_misc", ctrl->name);
  593. if (IS_ERR(ptr)) {
  594. DSI_CTRL_ERR(ctrl, "mmss_misc base address not found\n");
  595. rc = PTR_ERR(ptr);
  596. return rc;
  597. }
  598. ctrl->hw.mmss_misc_base = ptr;
  599. ctrl->hw.disp_cc_base = NULL;
  600. ctrl->hw.mdp_intf_base = NULL;
  601. break;
  602. case DSI_CTRL_VERSION_2_2:
  603. case DSI_CTRL_VERSION_2_3:
  604. case DSI_CTRL_VERSION_2_4:
  605. case DSI_CTRL_VERSION_2_5:
  606. case DSI_CTRL_VERSION_2_6:
  607. ptr = msm_ioremap(pdev, "disp_cc_base", ctrl->name);
  608. if (IS_ERR(ptr)) {
  609. DSI_CTRL_ERR(ctrl, "disp_cc base address not found for\n");
  610. rc = PTR_ERR(ptr);
  611. return rc;
  612. }
  613. ctrl->hw.disp_cc_base = ptr;
  614. ctrl->hw.mmss_misc_base = NULL;
  615. ptr = msm_ioremap(pdev, "mdp_intf_base", ctrl->name);
  616. if (!IS_ERR(ptr))
  617. ctrl->hw.mdp_intf_base = ptr;
  618. break;
  619. default:
  620. break;
  621. }
  622. return rc;
  623. }
  624. static int dsi_ctrl_clocks_deinit(struct dsi_ctrl *ctrl)
  625. {
  626. struct dsi_core_clk_info *core = &ctrl->clk_info.core_clks;
  627. struct dsi_link_lp_clk_info *lp_link = &ctrl->clk_info.lp_link_clks;
  628. struct dsi_link_hs_clk_info *hs_link = &ctrl->clk_info.hs_link_clks;
  629. struct dsi_clk_link_set *rcg = &ctrl->clk_info.rcg_clks;
  630. if (core->mdp_core_clk)
  631. devm_clk_put(&ctrl->pdev->dev, core->mdp_core_clk);
  632. if (core->iface_clk)
  633. devm_clk_put(&ctrl->pdev->dev, core->iface_clk);
  634. if (core->core_mmss_clk)
  635. devm_clk_put(&ctrl->pdev->dev, core->core_mmss_clk);
  636. if (core->bus_clk)
  637. devm_clk_put(&ctrl->pdev->dev, core->bus_clk);
  638. if (core->mnoc_clk)
  639. devm_clk_put(&ctrl->pdev->dev, core->mnoc_clk);
  640. memset(core, 0x0, sizeof(*core));
  641. if (hs_link->byte_clk)
  642. devm_clk_put(&ctrl->pdev->dev, hs_link->byte_clk);
  643. if (hs_link->pixel_clk)
  644. devm_clk_put(&ctrl->pdev->dev, hs_link->pixel_clk);
  645. if (lp_link->esc_clk)
  646. devm_clk_put(&ctrl->pdev->dev, lp_link->esc_clk);
  647. if (hs_link->byte_intf_clk)
  648. devm_clk_put(&ctrl->pdev->dev, hs_link->byte_intf_clk);
  649. memset(hs_link, 0x0, sizeof(*hs_link));
  650. memset(lp_link, 0x0, sizeof(*lp_link));
  651. if (rcg->byte_clk)
  652. devm_clk_put(&ctrl->pdev->dev, rcg->byte_clk);
  653. if (rcg->pixel_clk)
  654. devm_clk_put(&ctrl->pdev->dev, rcg->pixel_clk);
  655. memset(rcg, 0x0, sizeof(*rcg));
  656. return 0;
  657. }
  658. static int dsi_ctrl_clocks_init(struct platform_device *pdev,
  659. struct dsi_ctrl *ctrl)
  660. {
  661. int rc = 0;
  662. struct dsi_core_clk_info *core = &ctrl->clk_info.core_clks;
  663. struct dsi_link_lp_clk_info *lp_link = &ctrl->clk_info.lp_link_clks;
  664. struct dsi_link_hs_clk_info *hs_link = &ctrl->clk_info.hs_link_clks;
  665. struct dsi_clk_link_set *rcg = &ctrl->clk_info.rcg_clks;
  666. struct dsi_clk_link_set *xo = &ctrl->clk_info.xo_clk;
  667. core->mdp_core_clk = devm_clk_get(&pdev->dev, "mdp_core_clk");
  668. if (IS_ERR(core->mdp_core_clk)) {
  669. core->mdp_core_clk = NULL;
  670. DSI_CTRL_DEBUG(ctrl, "failed to get mdp_core_clk, rc=%d\n", rc);
  671. }
  672. core->iface_clk = devm_clk_get(&pdev->dev, "iface_clk");
  673. if (IS_ERR(core->iface_clk)) {
  674. core->iface_clk = NULL;
  675. DSI_CTRL_DEBUG(ctrl, "failed to get iface_clk, rc=%d\n", rc);
  676. }
  677. core->core_mmss_clk = devm_clk_get(&pdev->dev, "core_mmss_clk");
  678. if (IS_ERR(core->core_mmss_clk)) {
  679. core->core_mmss_clk = NULL;
  680. DSI_CTRL_DEBUG(ctrl, "failed to get core_mmss_clk, rc=%d\n",
  681. rc);
  682. }
  683. core->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
  684. if (IS_ERR(core->bus_clk)) {
  685. core->bus_clk = NULL;
  686. DSI_CTRL_DEBUG(ctrl, "failed to get bus_clk, rc=%d\n", rc);
  687. }
  688. core->mnoc_clk = devm_clk_get(&pdev->dev, "mnoc_clk");
  689. if (IS_ERR(core->mnoc_clk)) {
  690. core->mnoc_clk = NULL;
  691. DSI_CTRL_DEBUG(ctrl, "can't get mnoc clock, rc=%d\n", rc);
  692. }
  693. hs_link->byte_clk = devm_clk_get(&pdev->dev, "byte_clk");
  694. if (IS_ERR(hs_link->byte_clk)) {
  695. rc = PTR_ERR(hs_link->byte_clk);
  696. DSI_CTRL_ERR(ctrl, "failed to get byte_clk, rc=%d\n", rc);
  697. goto fail;
  698. }
  699. hs_link->pixel_clk = devm_clk_get(&pdev->dev, "pixel_clk");
  700. if (IS_ERR(hs_link->pixel_clk)) {
  701. rc = PTR_ERR(hs_link->pixel_clk);
  702. DSI_CTRL_ERR(ctrl, "failed to get pixel_clk, rc=%d\n", rc);
  703. goto fail;
  704. }
  705. lp_link->esc_clk = devm_clk_get(&pdev->dev, "esc_clk");
  706. if (IS_ERR(lp_link->esc_clk)) {
  707. rc = PTR_ERR(lp_link->esc_clk);
  708. DSI_CTRL_ERR(ctrl, "failed to get esc_clk, rc=%d\n", rc);
  709. goto fail;
  710. }
  711. hs_link->byte_intf_clk = devm_clk_get(&pdev->dev, "byte_intf_clk");
  712. if (IS_ERR(hs_link->byte_intf_clk)) {
  713. hs_link->byte_intf_clk = NULL;
  714. DSI_CTRL_DEBUG(ctrl, "can't find byte intf clk, rc=%d\n", rc);
  715. }
  716. rcg->byte_clk = devm_clk_get(&pdev->dev, "byte_clk_rcg");
  717. if (IS_ERR(rcg->byte_clk)) {
  718. rc = PTR_ERR(rcg->byte_clk);
  719. DSI_CTRL_ERR(ctrl, "failed to get byte_clk_rcg, rc=%d\n", rc);
  720. goto fail;
  721. }
  722. rcg->pixel_clk = devm_clk_get(&pdev->dev, "pixel_clk_rcg");
  723. if (IS_ERR(rcg->pixel_clk)) {
  724. rc = PTR_ERR(rcg->pixel_clk);
  725. DSI_CTRL_ERR(ctrl, "failed to get pixel_clk_rcg, rc=%d\n", rc);
  726. goto fail;
  727. }
  728. xo->byte_clk = devm_clk_get(&pdev->dev, "xo");
  729. if (IS_ERR(xo->byte_clk)) {
  730. xo->byte_clk = NULL;
  731. DSI_CTRL_DEBUG(ctrl, "failed to get xo clk, rc=%d\n", rc);
  732. }
  733. xo->pixel_clk = xo->byte_clk;
  734. return 0;
  735. fail:
  736. dsi_ctrl_clocks_deinit(ctrl);
  737. return rc;
  738. }
  739. static int dsi_ctrl_supplies_deinit(struct dsi_ctrl *ctrl)
  740. {
  741. int i = 0;
  742. int rc = 0;
  743. struct dsi_regulator_info *regs;
  744. regs = &ctrl->pwr_info.digital;
  745. for (i = 0; i < regs->count; i++) {
  746. if (!regs->vregs[i].vreg)
  747. DSI_CTRL_ERR(ctrl,
  748. "vreg is NULL, should not reach here\n");
  749. else
  750. devm_regulator_put(regs->vregs[i].vreg);
  751. }
  752. regs = &ctrl->pwr_info.host_pwr;
  753. for (i = 0; i < regs->count; i++) {
  754. if (!regs->vregs[i].vreg)
  755. DSI_CTRL_ERR(ctrl,
  756. "vreg is NULL, should not reach here\n");
  757. else
  758. devm_regulator_put(regs->vregs[i].vreg);
  759. }
  760. if (!ctrl->pwr_info.host_pwr.vregs) {
  761. devm_kfree(&ctrl->pdev->dev, ctrl->pwr_info.host_pwr.vregs);
  762. ctrl->pwr_info.host_pwr.vregs = NULL;
  763. ctrl->pwr_info.host_pwr.count = 0;
  764. }
  765. if (!ctrl->pwr_info.digital.vregs) {
  766. devm_kfree(&ctrl->pdev->dev, ctrl->pwr_info.digital.vregs);
  767. ctrl->pwr_info.digital.vregs = NULL;
  768. ctrl->pwr_info.digital.count = 0;
  769. }
  770. return rc;
  771. }
  772. static int dsi_ctrl_supplies_init(struct platform_device *pdev,
  773. struct dsi_ctrl *ctrl)
  774. {
  775. int rc = 0;
  776. int i = 0;
  777. struct dsi_regulator_info *regs;
  778. struct regulator *vreg = NULL;
  779. rc = dsi_pwr_get_dt_vreg_data(&pdev->dev,
  780. &ctrl->pwr_info.digital,
  781. "qcom,core-supply-entries");
  782. if (rc)
  783. DSI_CTRL_DEBUG(ctrl,
  784. "failed to get digital supply, rc = %d\n", rc);
  785. rc = dsi_pwr_get_dt_vreg_data(&pdev->dev,
  786. &ctrl->pwr_info.host_pwr,
  787. "qcom,ctrl-supply-entries");
  788. if (rc) {
  789. DSI_CTRL_ERR(ctrl,
  790. "failed to get host power supplies, rc = %d\n", rc);
  791. goto error_digital;
  792. }
  793. regs = &ctrl->pwr_info.digital;
  794. for (i = 0; i < regs->count; i++) {
  795. vreg = devm_regulator_get(&pdev->dev, regs->vregs[i].vreg_name);
  796. if (IS_ERR(vreg)) {
  797. DSI_CTRL_ERR(ctrl, "failed to get %s regulator\n",
  798. regs->vregs[i].vreg_name);
  799. rc = PTR_ERR(vreg);
  800. goto error_host_pwr;
  801. }
  802. regs->vregs[i].vreg = vreg;
  803. }
  804. regs = &ctrl->pwr_info.host_pwr;
  805. for (i = 0; i < regs->count; i++) {
  806. vreg = devm_regulator_get(&pdev->dev, regs->vregs[i].vreg_name);
  807. if (IS_ERR(vreg)) {
  808. DSI_CTRL_ERR(ctrl, "failed to get %s regulator\n",
  809. regs->vregs[i].vreg_name);
  810. for (--i; i >= 0; i--)
  811. devm_regulator_put(regs->vregs[i].vreg);
  812. rc = PTR_ERR(vreg);
  813. goto error_digital_put;
  814. }
  815. regs->vregs[i].vreg = vreg;
  816. }
  817. return rc;
  818. error_digital_put:
  819. regs = &ctrl->pwr_info.digital;
  820. for (i = 0; i < regs->count; i++)
  821. devm_regulator_put(regs->vregs[i].vreg);
  822. error_host_pwr:
  823. devm_kfree(&pdev->dev, ctrl->pwr_info.host_pwr.vregs);
  824. ctrl->pwr_info.host_pwr.vregs = NULL;
  825. ctrl->pwr_info.host_pwr.count = 0;
  826. error_digital:
  827. if (ctrl->pwr_info.digital.vregs)
  828. devm_kfree(&pdev->dev, ctrl->pwr_info.digital.vregs);
  829. ctrl->pwr_info.digital.vregs = NULL;
  830. ctrl->pwr_info.digital.count = 0;
  831. return rc;
  832. }
  833. static int dsi_ctrl_validate_panel_info(struct dsi_ctrl *dsi_ctrl,
  834. struct dsi_host_config *config)
  835. {
  836. int rc = 0;
  837. struct dsi_host_common_cfg *host_cfg = &config->common_config;
  838. if (config->panel_mode >= DSI_OP_MODE_MAX) {
  839. DSI_CTRL_ERR(dsi_ctrl, "Invalid dsi operation mode (%d)\n",
  840. config->panel_mode);
  841. rc = -EINVAL;
  842. goto err;
  843. }
  844. if ((host_cfg->data_lanes & (DSI_CLOCK_LANE - 1)) == 0) {
  845. DSI_CTRL_ERR(dsi_ctrl, "No data lanes are enabled\n");
  846. rc = -EINVAL;
  847. goto err;
  848. }
  849. err:
  850. return rc;
  851. }
  852. /* Function returns number of bits per pxl */
  853. int dsi_ctrl_pixel_format_to_bpp(enum dsi_pixel_format dst_format)
  854. {
  855. u32 bpp = 0;
  856. switch (dst_format) {
  857. case DSI_PIXEL_FORMAT_RGB111:
  858. bpp = 3;
  859. break;
  860. case DSI_PIXEL_FORMAT_RGB332:
  861. bpp = 8;
  862. break;
  863. case DSI_PIXEL_FORMAT_RGB444:
  864. bpp = 12;
  865. break;
  866. case DSI_PIXEL_FORMAT_RGB565:
  867. bpp = 16;
  868. break;
  869. case DSI_PIXEL_FORMAT_RGB666:
  870. case DSI_PIXEL_FORMAT_RGB666_LOOSE:
  871. bpp = 18;
  872. break;
  873. case DSI_PIXEL_FORMAT_RGB888:
  874. bpp = 24;
  875. break;
  876. default:
  877. bpp = 24;
  878. break;
  879. }
  880. return bpp;
  881. }
  882. static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,
  883. struct dsi_host_config *config, void *clk_handle,
  884. struct dsi_display_mode *mode)
  885. {
  886. int rc = 0;
  887. u32 num_of_lanes = 0;
  888. u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
  889. u32 bpp, frame_time_us, byte_intf_clk_div;
  890. u64 h_period, v_period, bit_rate, pclk_rate, bit_rate_per_lane,
  891. byte_clk_rate, byte_intf_clk_rate;
  892. struct dsi_host_common_cfg *host_cfg = &config->common_config;
  893. struct dsi_split_link_config *split_link = &host_cfg->split_link;
  894. struct dsi_mode_info *timing = &config->video_timing;
  895. u64 dsi_transfer_time_us = mode->priv_info->dsi_transfer_time_us;
  896. u64 min_dsi_clk_hz = mode->priv_info->min_dsi_clk_hz;
  897. /* Get bits per pxl in destination format */
  898. bpp = dsi_ctrl_pixel_format_to_bpp(host_cfg->dst_format);
  899. frame_time_us = mult_frac(1000, 1000, (timing->refresh_rate));
  900. if (host_cfg->data_lanes & DSI_DATA_LANE_0)
  901. num_of_lanes++;
  902. if (host_cfg->data_lanes & DSI_DATA_LANE_1)
  903. num_of_lanes++;
  904. if (host_cfg->data_lanes & DSI_DATA_LANE_2)
  905. num_of_lanes++;
  906. if (host_cfg->data_lanes & DSI_DATA_LANE_3)
  907. num_of_lanes++;
  908. if (split_link->enabled)
  909. num_of_lanes = split_link->lanes_per_sublink;
  910. config->common_config.num_data_lanes = num_of_lanes;
  911. config->common_config.bpp = bpp;
  912. if (config->bit_clk_rate_hz_override != 0) {
  913. bit_rate = config->bit_clk_rate_hz_override * num_of_lanes;
  914. if (host_cfg->phy_type == DSI_PHY_TYPE_CPHY) {
  915. bit_rate *= bits_per_symbol;
  916. do_div(bit_rate, num_of_symbols);
  917. }
  918. } else if (config->panel_mode == DSI_OP_CMD_MODE) {
  919. /* Calculate the bit rate needed to match dsi transfer time */
  920. bit_rate = min_dsi_clk_hz * frame_time_us;
  921. do_div(bit_rate, dsi_transfer_time_us);
  922. bit_rate = bit_rate * num_of_lanes;
  923. } else {
  924. h_period = dsi_h_total_dce(timing);
  925. v_period = DSI_V_TOTAL(timing);
  926. bit_rate = h_period * v_period * timing->refresh_rate * bpp;
  927. }
  928. pclk_rate = bit_rate;
  929. do_div(pclk_rate, bpp);
  930. if (host_cfg->phy_type == DSI_PHY_TYPE_DPHY) {
  931. bit_rate_per_lane = bit_rate;
  932. do_div(bit_rate_per_lane, num_of_lanes);
  933. byte_clk_rate = bit_rate_per_lane;
  934. /**
  935. * Ensure that the byte clock rate is even to avoid failures
  936. * during set rate for byte intf clock. Round up to the nearest
  937. * even number for byte clk.
  938. */
  939. byte_clk_rate = DIV_ROUND_CLOSEST(byte_clk_rate, 8);
  940. byte_clk_rate = ((byte_clk_rate + 1) & ~BIT(0));
  941. byte_intf_clk_rate = byte_clk_rate;
  942. byte_intf_clk_div = host_cfg->byte_intf_clk_div;
  943. do_div(byte_intf_clk_rate, byte_intf_clk_div);
  944. config->bit_clk_rate_hz = byte_clk_rate * 8;
  945. } else {
  946. do_div(bit_rate, bits_per_symbol);
  947. bit_rate *= num_of_symbols;
  948. bit_rate_per_lane = bit_rate;
  949. do_div(bit_rate_per_lane, num_of_lanes);
  950. byte_clk_rate = bit_rate_per_lane;
  951. do_div(byte_clk_rate, 7);
  952. /* For CPHY, byte_intf_clk is same as byte_clk */
  953. byte_intf_clk_rate = byte_clk_rate;
  954. config->bit_clk_rate_hz = byte_clk_rate * 7;
  955. }
  956. DSI_CTRL_DEBUG(dsi_ctrl, "bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n",
  957. bit_rate, bit_rate_per_lane);
  958. DSI_CTRL_DEBUG(dsi_ctrl, "byte_clk_rate = %llu, byte_intf_clk = %llu\n",
  959. byte_clk_rate, byte_intf_clk_rate);
  960. DSI_CTRL_DEBUG(dsi_ctrl, "pclk_rate = %llu\n", pclk_rate);
  961. SDE_EVT32(dsi_ctrl->cell_index, bit_rate, byte_clk_rate, pclk_rate);
  962. dsi_ctrl->clk_freq.byte_clk_rate = byte_clk_rate;
  963. dsi_ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;
  964. dsi_ctrl->clk_freq.pix_clk_rate = pclk_rate;
  965. dsi_ctrl->clk_freq.esc_clk_rate = config->esc_clk_rate_hz;
  966. rc = dsi_clk_set_link_frequencies(clk_handle, dsi_ctrl->clk_freq,
  967. dsi_ctrl->cell_index);
  968. if (rc)
  969. DSI_CTRL_ERR(dsi_ctrl, "Failed to update link frequencies\n");
  970. return rc;
  971. }
  972. static int dsi_ctrl_enable_supplies(struct dsi_ctrl *dsi_ctrl, bool enable)
  973. {
  974. int rc = 0;
  975. if (enable) {
  976. rc = pm_runtime_get_sync(dsi_ctrl->drm_dev->dev);
  977. if (rc < 0) {
  978. DSI_CTRL_ERR(dsi_ctrl,
  979. "Power resource enable failed, rc=%d\n", rc);
  980. goto error;
  981. }
  982. if (!dsi_ctrl->current_state.host_initialized) {
  983. rc = dsi_pwr_enable_regulator(
  984. &dsi_ctrl->pwr_info.host_pwr, true);
  985. if (rc) {
  986. DSI_CTRL_ERR(dsi_ctrl, "failed to enable host power regs\n");
  987. goto error_get_sync;
  988. }
  989. }
  990. rc = dsi_pwr_enable_regulator(&dsi_ctrl->pwr_info.digital,
  991. true);
  992. if (rc) {
  993. DSI_CTRL_ERR(dsi_ctrl, "failed to enable gdsc, rc=%d\n",
  994. rc);
  995. (void)dsi_pwr_enable_regulator(
  996. &dsi_ctrl->pwr_info.host_pwr,
  997. false
  998. );
  999. goto error_get_sync;
  1000. }
  1001. return rc;
  1002. } else {
  1003. rc = dsi_pwr_enable_regulator(&dsi_ctrl->pwr_info.digital,
  1004. false);
  1005. if (rc) {
  1006. DSI_CTRL_ERR(dsi_ctrl, "failed to disable gdsc, rc=%d\n",
  1007. rc);
  1008. goto error;
  1009. }
  1010. if (!dsi_ctrl->current_state.host_initialized) {
  1011. rc = dsi_pwr_enable_regulator(
  1012. &dsi_ctrl->pwr_info.host_pwr, false);
  1013. if (rc) {
  1014. DSI_CTRL_ERR(dsi_ctrl, "failed to disable host power regs\n");
  1015. goto error;
  1016. }
  1017. }
  1018. pm_runtime_put_sync(dsi_ctrl->drm_dev->dev);
  1019. return rc;
  1020. }
  1021. error_get_sync:
  1022. pm_runtime_put_sync(dsi_ctrl->drm_dev->dev);
  1023. error:
  1024. return rc;
  1025. }
  1026. static int dsi_ctrl_copy_and_pad_cmd(struct dsi_ctrl *dsi_ctrl,
  1027. const struct mipi_dsi_packet *packet,
  1028. u8 **buffer,
  1029. u32 *size)
  1030. {
  1031. int rc = 0;
  1032. u8 *buf = NULL;
  1033. u32 len, i;
  1034. u8 cmd_type = 0;
  1035. len = packet->size;
  1036. len += 0x3; len &= ~0x03; /* Align to 32 bits */
  1037. buf = devm_kzalloc(&dsi_ctrl->pdev->dev, len * sizeof(u8), GFP_KERNEL);
  1038. if (!buf)
  1039. return -ENOMEM;
  1040. for (i = 0; i < len; i++) {
  1041. if (i >= packet->size)
  1042. buf[i] = 0xFF;
  1043. else if (i < sizeof(packet->header))
  1044. buf[i] = packet->header[i];
  1045. else
  1046. buf[i] = packet->payload[i - sizeof(packet->header)];
  1047. }
  1048. if (packet->payload_length > 0)
  1049. buf[3] |= BIT(6);
  1050. /* Swap BYTE order in the command buffer for MSM */
  1051. buf[0] = packet->header[1];
  1052. buf[1] = packet->header[2];
  1053. buf[2] = packet->header[0];
  1054. /* send embedded BTA for read commands */
  1055. cmd_type = buf[2] & 0x3f;
  1056. if ((cmd_type == MIPI_DSI_DCS_READ) ||
  1057. (cmd_type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) ||
  1058. (cmd_type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) ||
  1059. (cmd_type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM))
  1060. buf[3] |= BIT(5);
  1061. *buffer = buf;
  1062. *size = len;
  1063. return rc;
  1064. }
  1065. int dsi_ctrl_wait_for_cmd_mode_mdp_idle(struct dsi_ctrl *dsi_ctrl)
  1066. {
  1067. int rc = 0;
  1068. if (!dsi_ctrl) {
  1069. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  1070. return -EINVAL;
  1071. }
  1072. if (dsi_ctrl->host_config.panel_mode != DSI_OP_CMD_MODE)
  1073. return -EINVAL;
  1074. mutex_lock(&dsi_ctrl->ctrl_lock);
  1075. rc = dsi_ctrl->hw.ops.wait_for_cmd_mode_mdp_idle(&dsi_ctrl->hw);
  1076. mutex_unlock(&dsi_ctrl->ctrl_lock);
  1077. return rc;
  1078. }
  1079. static void dsi_ctrl_wait_for_video_done(struct dsi_ctrl *dsi_ctrl)
  1080. {
  1081. u32 v_total = 0, v_blank = 0, sleep_ms = 0, fps = 0, ret;
  1082. struct dsi_mode_info *timing;
  1083. /**
  1084. * No need to wait if the panel is not video mode or
  1085. * if DSI controller supports command DMA scheduling or
  1086. * if we are sending init commands.
  1087. */
  1088. if ((dsi_ctrl->host_config.panel_mode != DSI_OP_VIDEO_MODE) ||
  1089. (dsi_ctrl->version >= DSI_CTRL_VERSION_2_2) ||
  1090. (dsi_ctrl->current_state.vid_engine_state !=
  1091. DSI_CTRL_ENGINE_ON))
  1092. return;
  1093. dsi_ctrl->hw.ops.clear_interrupt_status(&dsi_ctrl->hw,
  1094. DSI_VIDEO_MODE_FRAME_DONE);
  1095. dsi_ctrl_enable_status_interrupt(dsi_ctrl,
  1096. DSI_SINT_VIDEO_MODE_FRAME_DONE, NULL);
  1097. reinit_completion(&dsi_ctrl->irq_info.vid_frame_done);
  1098. ret = wait_for_completion_timeout(
  1099. &dsi_ctrl->irq_info.vid_frame_done,
  1100. msecs_to_jiffies(DSI_CTRL_TX_TO_MS));
  1101. if (ret <= 0)
  1102. DSI_CTRL_DEBUG(dsi_ctrl, "wait for video done failed\n");
  1103. dsi_ctrl_disable_status_interrupt(dsi_ctrl,
  1104. DSI_SINT_VIDEO_MODE_FRAME_DONE);
  1105. timing = &(dsi_ctrl->host_config.video_timing);
  1106. v_total = timing->v_sync_width + timing->v_back_porch +
  1107. timing->v_front_porch + timing->v_active;
  1108. v_blank = timing->v_sync_width + timing->v_back_porch;
  1109. fps = timing->refresh_rate;
  1110. sleep_ms = CEIL((v_blank * 1000), (v_total * fps)) + 1;
  1111. udelay(sleep_ms * 1000);
  1112. }
  1113. int dsi_message_validate_tx_mode(struct dsi_ctrl *dsi_ctrl,
  1114. u32 cmd_len,
  1115. u32 *flags)
  1116. {
  1117. int rc = 0;
  1118. if (*flags & DSI_CTRL_CMD_FIFO_STORE) {
  1119. /* if command size plus header is greater than fifo size */
  1120. if ((cmd_len + 4) > DSI_CTRL_MAX_CMD_FIFO_STORE_SIZE) {
  1121. DSI_CTRL_ERR(dsi_ctrl, "Cannot transfer Cmd in FIFO config\n");
  1122. return -ENOTSUPP;
  1123. }
  1124. if (!dsi_ctrl->hw.ops.kickoff_fifo_command) {
  1125. DSI_CTRL_ERR(dsi_ctrl, "Cannot transfer command,ops not defined\n");
  1126. return -ENOTSUPP;
  1127. }
  1128. }
  1129. if (*flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) {
  1130. if (*flags & DSI_CTRL_CMD_BROADCAST) {
  1131. DSI_CTRL_ERR(dsi_ctrl, "Non embedded not supported with broadcast\n");
  1132. return -ENOTSUPP;
  1133. }
  1134. if (!dsi_ctrl->hw.ops.kickoff_command_non_embedded_mode) {
  1135. DSI_CTRL_ERR(dsi_ctrl, " Cannot transfer command,ops not defined\n");
  1136. return -ENOTSUPP;
  1137. }
  1138. if ((cmd_len + 4) > SZ_4K) {
  1139. DSI_CTRL_ERR(dsi_ctrl, "Cannot transfer,size is greater than 4096\n");
  1140. return -ENOTSUPP;
  1141. }
  1142. }
  1143. if (*flags & DSI_CTRL_CMD_FETCH_MEMORY) {
  1144. if ((dsi_ctrl->cmd_len + cmd_len + 4) > SZ_4K) {
  1145. DSI_CTRL_ERR(dsi_ctrl, "Cannot transfer,size is greater than 4096\n");
  1146. return -ENOTSUPP;
  1147. }
  1148. }
  1149. return rc;
  1150. }
  1151. static void dsi_configure_command_scheduling(struct dsi_ctrl *dsi_ctrl,
  1152. struct dsi_ctrl_cmd_dma_info *cmd_mem)
  1153. {
  1154. u32 line_no = 0, window = 0, sched_line_no = 0;
  1155. struct dsi_ctrl_hw_ops dsi_hw_ops = dsi_ctrl->hw.ops;
  1156. struct dsi_mode_info *timing = &(dsi_ctrl->host_config.video_timing);
  1157. line_no = dsi_ctrl->host_config.common_config.dma_sched_line;
  1158. window = dsi_ctrl->host_config.common_config.dma_sched_window;
  1159. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY, line_no, window);
  1160. /*
  1161. * In case of command scheduling in video mode, the line at which
  1162. * the command is scheduled can revert to the default value i.e. 1
  1163. * for the following cases:
  1164. * 1) No schedule line defined by the panel.
  1165. * 2) schedule line defined is greater than VFP.
  1166. */
  1167. if ((dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE) &&
  1168. dsi_hw_ops.schedule_dma_cmd &&
  1169. (dsi_ctrl->current_state.vid_engine_state ==
  1170. DSI_CTRL_ENGINE_ON)) {
  1171. sched_line_no = (line_no == 0) ? 1 : line_no;
  1172. if (timing) {
  1173. if (sched_line_no >= timing->v_front_porch)
  1174. sched_line_no = 1;
  1175. sched_line_no += timing->v_back_porch +
  1176. timing->v_sync_width + timing->v_active;
  1177. }
  1178. dsi_hw_ops.schedule_dma_cmd(&dsi_ctrl->hw, sched_line_no);
  1179. }
  1180. /*
  1181. * In case of command scheduling in command mode, set the maximum
  1182. * possible size of the DMA start window in case no schedule line and
  1183. * window size properties are defined by the panel.
  1184. */
  1185. if ((dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE) &&
  1186. dsi_hw_ops.configure_cmddma_window) {
  1187. sched_line_no = (line_no == 0) ? TEARCHECK_WINDOW_SIZE :
  1188. line_no;
  1189. window = (window == 0) ? timing->v_active : window;
  1190. sched_line_no += timing->v_active;
  1191. dsi_hw_ops.configure_cmddma_window(&dsi_ctrl->hw, cmd_mem,
  1192. sched_line_no, window);
  1193. }
  1194. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_EXIT,
  1195. sched_line_no, window);
  1196. }
  1197. static u32 calculate_schedule_line(struct dsi_ctrl *dsi_ctrl, u32 flags)
  1198. {
  1199. u32 line_no = 0x1;
  1200. struct dsi_mode_info *timing;
  1201. /* check if custom dma scheduling line needed */
  1202. if ((dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE) &&
  1203. (flags & DSI_CTRL_CMD_CUSTOM_DMA_SCHED))
  1204. line_no = dsi_ctrl->host_config.common_config.dma_sched_line;
  1205. timing = &(dsi_ctrl->host_config.video_timing);
  1206. if (timing)
  1207. line_no += timing->v_back_porch + timing->v_sync_width +
  1208. timing->v_active;
  1209. return line_no;
  1210. }
  1211. static void dsi_kickoff_msg_tx(struct dsi_ctrl *dsi_ctrl,
  1212. const struct mipi_dsi_msg *msg,
  1213. struct dsi_ctrl_cmd_dma_fifo_info *cmd,
  1214. struct dsi_ctrl_cmd_dma_info *cmd_mem,
  1215. u32 flags)
  1216. {
  1217. u32 hw_flags = 0;
  1218. struct dsi_ctrl_hw_ops dsi_hw_ops = dsi_ctrl->hw.ops;
  1219. struct dsi_split_link_config *split_link;
  1220. split_link = &(dsi_ctrl->host_config.common_config.split_link);
  1221. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY, flags,
  1222. msg->flags);
  1223. if (dsi_ctrl->hw.reset_trig_ctrl)
  1224. dsi_hw_ops.reset_trig_ctrl(&dsi_ctrl->hw,
  1225. &dsi_ctrl->host_config.common_config);
  1226. if (dsi_hw_ops.splitlink_cmd_setup && split_link->enabled)
  1227. dsi_hw_ops.splitlink_cmd_setup(&dsi_ctrl->hw,
  1228. &dsi_ctrl->host_config.common_config, flags);
  1229. /*
  1230. * Always enable DMA scheduling for video mode panel.
  1231. *
  1232. * In video mode panel, if the DMA is triggered very close to
  1233. * the beginning of the active window and the DMA transfer
  1234. * happens in the last line of VBP, then the HW state will
  1235. * stay in ‘wait’ and return to ‘idle’ in the first line of VFP.
  1236. * But somewhere in the middle of the active window, if SW
  1237. * disables DSI command mode engine while the HW is still
  1238. * waiting and re-enable after timing engine is OFF. So the
  1239. * HW never ‘sees’ another vblank line and hence it gets
  1240. * stuck in the ‘wait’ state.
  1241. */
  1242. if ((flags & DSI_CTRL_CMD_CUSTOM_DMA_SCHED) ||
  1243. (dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE))
  1244. dsi_configure_command_scheduling(dsi_ctrl, cmd_mem);
  1245. dsi_ctrl->cmd_mode = (dsi_ctrl->host_config.panel_mode ==
  1246. DSI_OP_CMD_MODE);
  1247. hw_flags |= (flags & DSI_CTRL_CMD_DEFER_TRIGGER) ?
  1248. DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER : 0;
  1249. if (flags & DSI_CTRL_CMD_LAST_COMMAND)
  1250. hw_flags |= DSI_CTRL_CMD_LAST_COMMAND;
  1251. if (flags & DSI_CTRL_CMD_DEFER_TRIGGER) {
  1252. if (flags & DSI_CTRL_CMD_FETCH_MEMORY) {
  1253. if (flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) {
  1254. dsi_hw_ops.kickoff_command_non_embedded_mode(
  1255. &dsi_ctrl->hw,
  1256. cmd_mem,
  1257. hw_flags);
  1258. } else {
  1259. dsi_hw_ops.kickoff_command(
  1260. &dsi_ctrl->hw,
  1261. cmd_mem,
  1262. hw_flags);
  1263. }
  1264. } else if (flags & DSI_CTRL_CMD_FIFO_STORE) {
  1265. dsi_hw_ops.kickoff_fifo_command(&dsi_ctrl->hw,
  1266. cmd,
  1267. hw_flags);
  1268. }
  1269. }
  1270. if (!(flags & DSI_CTRL_CMD_DEFER_TRIGGER)) {
  1271. dsi_ctrl_wait_for_video_done(dsi_ctrl);
  1272. atomic_set(&dsi_ctrl->dma_irq_trig, 0);
  1273. dsi_ctrl_enable_status_interrupt(dsi_ctrl,
  1274. DSI_SINT_CMD_MODE_DMA_DONE, NULL);
  1275. reinit_completion(&dsi_ctrl->irq_info.cmd_dma_done);
  1276. if (flags & DSI_CTRL_CMD_FETCH_MEMORY) {
  1277. if (flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) {
  1278. dsi_hw_ops.kickoff_command_non_embedded_mode(
  1279. &dsi_ctrl->hw,
  1280. cmd_mem,
  1281. hw_flags);
  1282. } else {
  1283. dsi_hw_ops.kickoff_command(
  1284. &dsi_ctrl->hw,
  1285. cmd_mem,
  1286. hw_flags);
  1287. }
  1288. } else if (flags & DSI_CTRL_CMD_FIFO_STORE) {
  1289. dsi_hw_ops.kickoff_fifo_command(&dsi_ctrl->hw,
  1290. cmd,
  1291. hw_flags);
  1292. }
  1293. if (dsi_ctrl->enable_cmd_dma_stats) {
  1294. u32 reg = dsi_hw_ops.log_line_count(&dsi_ctrl->hw,
  1295. dsi_ctrl->cmd_mode);
  1296. dsi_ctrl->cmd_trigger_line = (reg & 0xFFFF);
  1297. dsi_ctrl->cmd_trigger_frame = ((reg >> 16) & 0xFFFF);
  1298. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_CASE1,
  1299. dsi_ctrl->cmd_trigger_line,
  1300. dsi_ctrl->cmd_trigger_frame);
  1301. }
  1302. dsi_hw_ops.reset_cmd_fifo(&dsi_ctrl->hw);
  1303. /*
  1304. * DSI 2.2 needs a soft reset whenever we send non-embedded
  1305. * mode command followed by embedded mode. Otherwise it will
  1306. * result in smmu write faults with DSI as client.
  1307. */
  1308. if (flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) {
  1309. if (dsi_ctrl->version < DSI_CTRL_VERSION_2_4)
  1310. dsi_hw_ops.soft_reset(&dsi_ctrl->hw);
  1311. dsi_ctrl->cmd_len = 0;
  1312. }
  1313. }
  1314. }
  1315. static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, struct dsi_cmd_desc *cmd_desc)
  1316. {
  1317. int rc = 0;
  1318. struct mipi_dsi_packet packet;
  1319. struct dsi_ctrl_cmd_dma_fifo_info cmd;
  1320. struct dsi_ctrl_cmd_dma_info cmd_mem;
  1321. const struct mipi_dsi_msg *msg;
  1322. u32 length = 0;
  1323. u8 *buffer = NULL;
  1324. u32 cnt = 0;
  1325. u8 *cmdbuf;
  1326. u32 *flags;
  1327. msg = &cmd_desc->msg;
  1328. flags = &cmd_desc->ctrl_flags;
  1329. /* Validate the mode before sending the command */
  1330. rc = dsi_message_validate_tx_mode(dsi_ctrl, msg->tx_len, flags);
  1331. if (rc) {
  1332. DSI_CTRL_ERR(dsi_ctrl,
  1333. "Cmd tx validation failed, cannot transfer cmd\n");
  1334. rc = -ENOTSUPP;
  1335. goto error;
  1336. }
  1337. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY, *flags);
  1338. if (*flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) {
  1339. cmd_mem.offset = dsi_ctrl->cmd_buffer_iova;
  1340. cmd_mem.en_broadcast = (*flags & DSI_CTRL_CMD_BROADCAST) ?
  1341. true : false;
  1342. cmd_mem.is_master = (*flags & DSI_CTRL_CMD_BROADCAST_MASTER) ?
  1343. true : false;
  1344. cmd_mem.use_lpm = (msg->flags & MIPI_DSI_MSG_USE_LPM) ?
  1345. true : false;
  1346. cmd_mem.datatype = msg->type;
  1347. cmd_mem.length = msg->tx_len;
  1348. dsi_ctrl->cmd_len = msg->tx_len;
  1349. memcpy(dsi_ctrl->vaddr, msg->tx_buf, msg->tx_len);
  1350. DSI_CTRL_DEBUG(dsi_ctrl,
  1351. "non-embedded mode , size of command =%zd\n",
  1352. msg->tx_len);
  1353. goto kickoff;
  1354. }
  1355. rc = mipi_dsi_create_packet(&packet, msg);
  1356. if (rc) {
  1357. DSI_CTRL_ERR(dsi_ctrl, "Failed to create message packet, rc=%d\n",
  1358. rc);
  1359. goto error;
  1360. }
  1361. rc = dsi_ctrl_copy_and_pad_cmd(dsi_ctrl,
  1362. &packet,
  1363. &buffer,
  1364. &length);
  1365. if (rc) {
  1366. DSI_CTRL_ERR(dsi_ctrl, "failed to copy message, rc=%d\n", rc);
  1367. goto error;
  1368. }
  1369. /*
  1370. * In case of broadcast CMD length cannot be greater than 512 bytes
  1371. * as specified by HW limitations. Need to overwrite the flags to
  1372. * set the LAST_COMMAND flag to ensure no command transfer failures.
  1373. */
  1374. if ((*flags & DSI_CTRL_CMD_FETCH_MEMORY) && (*flags & DSI_CTRL_CMD_BROADCAST)) {
  1375. if (((dsi_ctrl->cmd_len + length) > 240) && !(*flags & DSI_CTRL_CMD_LAST_COMMAND)) {
  1376. *flags |= DSI_CTRL_CMD_LAST_COMMAND;
  1377. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_CASE1, *flags);
  1378. dsi_ctrl_transfer_prepare(dsi_ctrl, *flags);
  1379. }
  1380. }
  1381. if (*flags & DSI_CTRL_CMD_LAST_COMMAND)
  1382. buffer[3] |= BIT(7);//set the last cmd bit in header.
  1383. if (*flags & DSI_CTRL_CMD_FETCH_MEMORY) {
  1384. /* Embedded mode config is selected */
  1385. cmd_mem.offset = dsi_ctrl->cmd_buffer_iova;
  1386. cmd_mem.en_broadcast = (*flags & DSI_CTRL_CMD_BROADCAST) ?
  1387. true : false;
  1388. cmd_mem.is_master = (*flags & DSI_CTRL_CMD_BROADCAST_MASTER) ?
  1389. true : false;
  1390. cmd_mem.use_lpm = (msg->flags & MIPI_DSI_MSG_USE_LPM) ?
  1391. true : false;
  1392. cmdbuf = (u8 *)(dsi_ctrl->vaddr);
  1393. msm_gem_sync(dsi_ctrl->tx_cmd_buf);
  1394. for (cnt = 0; cnt < length; cnt++)
  1395. cmdbuf[dsi_ctrl->cmd_len + cnt] = buffer[cnt];
  1396. dsi_ctrl->cmd_len += length;
  1397. if (*flags & DSI_CTRL_CMD_LAST_COMMAND) {
  1398. cmd_mem.length = dsi_ctrl->cmd_len;
  1399. dsi_ctrl->cmd_len = 0;
  1400. } else {
  1401. goto error;
  1402. }
  1403. } else if (*flags & DSI_CTRL_CMD_FIFO_STORE) {
  1404. cmd.command = (u32 *)buffer;
  1405. cmd.size = length;
  1406. cmd.en_broadcast = (*flags & DSI_CTRL_CMD_BROADCAST) ?
  1407. true : false;
  1408. cmd.is_master = (*flags & DSI_CTRL_CMD_BROADCAST_MASTER) ?
  1409. true : false;
  1410. cmd.use_lpm = (msg->flags & MIPI_DSI_MSG_USE_LPM) ?
  1411. true : false;
  1412. }
  1413. kickoff:
  1414. dsi_kickoff_msg_tx(dsi_ctrl, msg, &cmd, &cmd_mem, *flags);
  1415. error:
  1416. if (buffer)
  1417. devm_kfree(&dsi_ctrl->pdev->dev, buffer);
  1418. return rc;
  1419. }
  1420. static int dsi_set_max_return_size(struct dsi_ctrl *dsi_ctrl, struct dsi_cmd_desc *rx_cmd, u32 size)
  1421. {
  1422. int rc = 0;
  1423. const struct mipi_dsi_msg *rx_msg = &rx_cmd->msg;
  1424. u8 tx[2] = { (u8)(size & 0xFF), (u8)(size >> 8) };
  1425. u16 dflags = rx_msg->flags;
  1426. struct dsi_cmd_desc cmd= {
  1427. .msg.channel = rx_msg->channel,
  1428. .msg.type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
  1429. .msg.tx_len = 2,
  1430. .msg.tx_buf = tx,
  1431. .msg.flags = rx_msg->flags,
  1432. };
  1433. /* remove last message flag to batch max packet cmd to read command */
  1434. dflags &= ~BIT(3);
  1435. cmd.msg.flags = dflags;
  1436. cmd.ctrl_flags = DSI_CTRL_CMD_FETCH_MEMORY;
  1437. rc = dsi_message_tx(dsi_ctrl, &cmd);
  1438. if (rc)
  1439. DSI_CTRL_ERR(dsi_ctrl, "failed to send max return size packet, rc=%d\n",
  1440. rc);
  1441. return rc;
  1442. }
  1443. /* Helper functions to support DCS read operation */
  1444. static int dsi_parse_short_read1_resp(const struct mipi_dsi_msg *msg,
  1445. unsigned char *buff)
  1446. {
  1447. u8 *data = msg->rx_buf;
  1448. int read_len = 1;
  1449. if (!data)
  1450. return 0;
  1451. /* remove dcs type */
  1452. if (msg->rx_len >= 1)
  1453. data[0] = buff[1];
  1454. else
  1455. read_len = 0;
  1456. return read_len;
  1457. }
  1458. static int dsi_parse_short_read2_resp(const struct mipi_dsi_msg *msg,
  1459. unsigned char *buff)
  1460. {
  1461. u8 *data = msg->rx_buf;
  1462. int read_len = 2;
  1463. if (!data)
  1464. return 0;
  1465. /* remove dcs type */
  1466. if (msg->rx_len >= 2) {
  1467. data[0] = buff[1];
  1468. data[1] = buff[2];
  1469. } else {
  1470. read_len = 0;
  1471. }
  1472. return read_len;
  1473. }
  1474. static int dsi_parse_long_read_resp(const struct mipi_dsi_msg *msg,
  1475. unsigned char *buff)
  1476. {
  1477. if (!msg->rx_buf)
  1478. return 0;
  1479. /* remove dcs type */
  1480. if (msg->rx_buf && msg->rx_len)
  1481. memcpy(msg->rx_buf, buff + 4, msg->rx_len);
  1482. return msg->rx_len;
  1483. }
  1484. static int dsi_message_rx(struct dsi_ctrl *dsi_ctrl, struct dsi_cmd_desc *cmd_desc)
  1485. {
  1486. int rc = 0;
  1487. u32 rd_pkt_size, total_read_len, hw_read_cnt;
  1488. u32 current_read_len = 0, total_bytes_read = 0;
  1489. bool short_resp = false;
  1490. bool read_done = false;
  1491. u32 dlen, diff, rlen;
  1492. unsigned char *buff;
  1493. char cmd;
  1494. const struct mipi_dsi_msg *msg;
  1495. if (!cmd_desc) {
  1496. DSI_CTRL_ERR(dsi_ctrl, "Invalid command\n");
  1497. rc = -EINVAL;
  1498. goto error;
  1499. }
  1500. msg = &cmd_desc->msg;
  1501. rlen = msg->rx_len;
  1502. if (msg->rx_len <= 2) {
  1503. short_resp = true;
  1504. rd_pkt_size = msg->rx_len;
  1505. total_read_len = 4;
  1506. } else {
  1507. short_resp = false;
  1508. current_read_len = 10;
  1509. if (msg->rx_len < current_read_len)
  1510. rd_pkt_size = msg->rx_len;
  1511. else
  1512. rd_pkt_size = current_read_len;
  1513. total_read_len = current_read_len + 6;
  1514. }
  1515. buff = msg->rx_buf;
  1516. while (!read_done) {
  1517. rc = dsi_set_max_return_size(dsi_ctrl, cmd_desc, rd_pkt_size);
  1518. if (rc) {
  1519. DSI_CTRL_ERR(dsi_ctrl, "Failed to set max return packet size, rc=%d\n",
  1520. rc);
  1521. goto error;
  1522. }
  1523. /* clear RDBK_DATA registers before proceeding */
  1524. dsi_ctrl->hw.ops.clear_rdbk_register(&dsi_ctrl->hw);
  1525. rc = dsi_message_tx(dsi_ctrl, cmd_desc);
  1526. if (rc) {
  1527. DSI_CTRL_ERR(dsi_ctrl, "Message transmission failed, rc=%d\n",
  1528. rc);
  1529. goto error;
  1530. }
  1531. /* Wait for read command transfer success */
  1532. dsi_ctrl_dma_cmd_wait_for_done(dsi_ctrl);
  1533. /*
  1534. * wait before reading rdbk_data register, if any delay is
  1535. * required after sending the read command.
  1536. */
  1537. if (cmd_desc->post_wait_ms)
  1538. usleep_range(cmd_desc->post_wait_ms * 1000,
  1539. ((cmd_desc->post_wait_ms * 1000) + 10));
  1540. dlen = dsi_ctrl->hw.ops.get_cmd_read_data(&dsi_ctrl->hw,
  1541. buff, total_bytes_read,
  1542. total_read_len, rd_pkt_size,
  1543. &hw_read_cnt);
  1544. if (!dlen)
  1545. goto error;
  1546. if (short_resp)
  1547. break;
  1548. if (rlen <= current_read_len) {
  1549. diff = current_read_len - rlen;
  1550. read_done = true;
  1551. } else {
  1552. diff = 0;
  1553. rlen -= current_read_len;
  1554. }
  1555. dlen -= 2; /* 2 bytes of CRC */
  1556. dlen -= diff;
  1557. buff += dlen;
  1558. total_bytes_read += dlen;
  1559. if (!read_done) {
  1560. current_read_len = 14; /* Not first read */
  1561. if (rlen < current_read_len)
  1562. rd_pkt_size += rlen;
  1563. else
  1564. rd_pkt_size += current_read_len;
  1565. }
  1566. }
  1567. if (hw_read_cnt < 16 && !short_resp)
  1568. buff = msg->rx_buf + (16 - hw_read_cnt);
  1569. else
  1570. buff = msg->rx_buf;
  1571. /* parse the data read from panel */
  1572. cmd = buff[0];
  1573. switch (cmd) {
  1574. case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
  1575. DSI_CTRL_ERR(dsi_ctrl, "Rx ACK_ERROR 0x%x\n", cmd);
  1576. rc = 0;
  1577. break;
  1578. case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
  1579. case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
  1580. rc = dsi_parse_short_read1_resp(msg, buff);
  1581. break;
  1582. case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
  1583. case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
  1584. rc = dsi_parse_short_read2_resp(msg, buff);
  1585. break;
  1586. case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
  1587. case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
  1588. rc = dsi_parse_long_read_resp(msg, buff);
  1589. break;
  1590. default:
  1591. DSI_CTRL_WARN(dsi_ctrl, "Invalid response: 0x%x\n", cmd);
  1592. rc = 0;
  1593. }
  1594. error:
  1595. return rc;
  1596. }
  1597. static int dsi_enable_ulps(struct dsi_ctrl *dsi_ctrl)
  1598. {
  1599. int rc = 0;
  1600. u32 lanes = 0;
  1601. u32 ulps_lanes;
  1602. lanes = dsi_ctrl->host_config.common_config.data_lanes;
  1603. rc = dsi_ctrl->hw.ops.wait_for_lane_idle(&dsi_ctrl->hw, lanes);
  1604. if (rc) {
  1605. DSI_CTRL_ERR(dsi_ctrl, "lanes not entering idle, skip ULPS\n");
  1606. return rc;
  1607. }
  1608. if (!dsi_ctrl->hw.ops.ulps_ops.ulps_request ||
  1609. !dsi_ctrl->hw.ops.ulps_ops.ulps_exit) {
  1610. DSI_CTRL_DEBUG(dsi_ctrl, "DSI controller ULPS ops not present\n");
  1611. return 0;
  1612. }
  1613. lanes |= DSI_CLOCK_LANE;
  1614. dsi_ctrl->hw.ops.ulps_ops.ulps_request(&dsi_ctrl->hw, lanes);
  1615. ulps_lanes = dsi_ctrl->hw.ops.ulps_ops.get_lanes_in_ulps(&dsi_ctrl->hw);
  1616. if ((lanes & ulps_lanes) != lanes) {
  1617. DSI_CTRL_ERR(dsi_ctrl, "Failed to enter ULPS, request=0x%x, actual=0x%x\n",
  1618. lanes, ulps_lanes);
  1619. rc = -EIO;
  1620. }
  1621. return rc;
  1622. }
  1623. static int dsi_disable_ulps(struct dsi_ctrl *dsi_ctrl)
  1624. {
  1625. int rc = 0;
  1626. u32 ulps_lanes, lanes = 0;
  1627. dsi_ctrl->hw.ops.clear_phy0_ln_err(&dsi_ctrl->hw);
  1628. if (!dsi_ctrl->hw.ops.ulps_ops.ulps_request ||
  1629. !dsi_ctrl->hw.ops.ulps_ops.ulps_exit) {
  1630. DSI_CTRL_DEBUG(dsi_ctrl, "DSI controller ULPS ops not present\n");
  1631. return 0;
  1632. }
  1633. lanes = dsi_ctrl->host_config.common_config.data_lanes;
  1634. lanes |= DSI_CLOCK_LANE;
  1635. ulps_lanes = dsi_ctrl->hw.ops.ulps_ops.get_lanes_in_ulps(&dsi_ctrl->hw);
  1636. if ((lanes & ulps_lanes) != lanes)
  1637. DSI_CTRL_ERR(dsi_ctrl, "Mismatch between lanes in ULPS\n");
  1638. lanes &= ulps_lanes;
  1639. dsi_ctrl->hw.ops.ulps_ops.ulps_exit(&dsi_ctrl->hw, lanes);
  1640. ulps_lanes = dsi_ctrl->hw.ops.ulps_ops.get_lanes_in_ulps(&dsi_ctrl->hw);
  1641. if (ulps_lanes & lanes) {
  1642. DSI_CTRL_ERR(dsi_ctrl, "Lanes (0x%x) stuck in ULPS\n",
  1643. ulps_lanes);
  1644. rc = -EIO;
  1645. }
  1646. return rc;
  1647. }
  1648. static void dsi_ctrl_enable_error_interrupts(struct dsi_ctrl *dsi_ctrl)
  1649. {
  1650. if (dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE &&
  1651. !dsi_ctrl->host_config.u.video_engine.bllp_lp11_en &&
  1652. !dsi_ctrl->host_config.u.video_engine.eof_bllp_lp11_en)
  1653. dsi_ctrl->hw.ops.enable_error_interrupts(&dsi_ctrl->hw,
  1654. 0xFF00A0);
  1655. else
  1656. dsi_ctrl->hw.ops.enable_error_interrupts(&dsi_ctrl->hw,
  1657. 0xFF00E0);
  1658. }
  1659. static int dsi_ctrl_drv_state_init(struct dsi_ctrl *dsi_ctrl)
  1660. {
  1661. int rc = 0;
  1662. bool splash_enabled = false;
  1663. struct dsi_ctrl_state_info *state = &dsi_ctrl->current_state;
  1664. if (!splash_enabled) {
  1665. state->power_state = DSI_CTRL_POWER_VREG_OFF;
  1666. state->cmd_engine_state = DSI_CTRL_ENGINE_OFF;
  1667. state->vid_engine_state = DSI_CTRL_ENGINE_OFF;
  1668. }
  1669. return rc;
  1670. }
  1671. static int dsi_ctrl_buffer_deinit(struct dsi_ctrl *dsi_ctrl)
  1672. {
  1673. struct msm_gem_address_space *aspace = NULL;
  1674. if (dsi_ctrl->tx_cmd_buf) {
  1675. aspace = dsi_ctrl_get_aspace(dsi_ctrl,
  1676. MSM_SMMU_DOMAIN_UNSECURE);
  1677. if (!aspace) {
  1678. DSI_CTRL_ERR(dsi_ctrl, "failed to get address space\n");
  1679. return -ENOMEM;
  1680. }
  1681. msm_gem_put_iova(dsi_ctrl->tx_cmd_buf, aspace);
  1682. mutex_lock(&dsi_ctrl->drm_dev->struct_mutex);
  1683. msm_gem_free_object(dsi_ctrl->tx_cmd_buf);
  1684. mutex_unlock(&dsi_ctrl->drm_dev->struct_mutex);
  1685. dsi_ctrl->tx_cmd_buf = NULL;
  1686. }
  1687. return 0;
  1688. }
  1689. int dsi_ctrl_buffer_init(struct dsi_ctrl *dsi_ctrl)
  1690. {
  1691. int rc = 0;
  1692. u64 iova = 0;
  1693. struct msm_gem_address_space *aspace = NULL;
  1694. aspace = dsi_ctrl_get_aspace(dsi_ctrl, MSM_SMMU_DOMAIN_UNSECURE);
  1695. if (!aspace) {
  1696. DSI_CTRL_ERR(dsi_ctrl, "failed to get address space\n");
  1697. return -ENOMEM;
  1698. }
  1699. dsi_ctrl->tx_cmd_buf = msm_gem_new(dsi_ctrl->drm_dev,
  1700. SZ_4K,
  1701. MSM_BO_UNCACHED);
  1702. if (IS_ERR(dsi_ctrl->tx_cmd_buf)) {
  1703. rc = PTR_ERR(dsi_ctrl->tx_cmd_buf);
  1704. DSI_CTRL_ERR(dsi_ctrl, "failed to allocate gem, rc=%d\n", rc);
  1705. dsi_ctrl->tx_cmd_buf = NULL;
  1706. goto error;
  1707. }
  1708. dsi_ctrl->cmd_buffer_size = SZ_4K;
  1709. rc = msm_gem_get_iova(dsi_ctrl->tx_cmd_buf, aspace, &iova);
  1710. if (rc) {
  1711. DSI_CTRL_ERR(dsi_ctrl, "failed to get iova, rc=%d\n", rc);
  1712. (void)dsi_ctrl_buffer_deinit(dsi_ctrl);
  1713. goto error;
  1714. }
  1715. if (iova & 0x07) {
  1716. DSI_CTRL_ERR(dsi_ctrl, "Tx command buffer is not 8 byte aligned\n");
  1717. rc = -ENOTSUPP;
  1718. (void)dsi_ctrl_buffer_deinit(dsi_ctrl);
  1719. goto error;
  1720. }
  1721. error:
  1722. return rc;
  1723. }
  1724. static int dsi_enable_io_clamp(struct dsi_ctrl *dsi_ctrl,
  1725. bool enable, bool ulps_enabled)
  1726. {
  1727. u32 lanes = 0;
  1728. if (dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE)
  1729. lanes = dsi_ctrl->host_config.common_config.data_lanes;
  1730. lanes |= DSI_CLOCK_LANE;
  1731. if (enable)
  1732. dsi_ctrl->hw.ops.clamp_enable(&dsi_ctrl->hw,
  1733. lanes, ulps_enabled);
  1734. else
  1735. dsi_ctrl->hw.ops.clamp_disable(&dsi_ctrl->hw,
  1736. lanes, ulps_enabled);
  1737. return 0;
  1738. }
  1739. static int dsi_ctrl_dts_parse(struct dsi_ctrl *dsi_ctrl,
  1740. struct device_node *of_node)
  1741. {
  1742. u32 index = 0, frame_threshold_time_us = 0;
  1743. int rc = 0;
  1744. if (!dsi_ctrl || !of_node) {
  1745. DSI_CTRL_ERR(dsi_ctrl, "invalid dsi_ctrl:%d or of_node:%d\n",
  1746. dsi_ctrl != NULL, of_node != NULL);
  1747. return -EINVAL;
  1748. }
  1749. rc = of_property_read_u32(of_node, "cell-index", &index);
  1750. if (rc) {
  1751. DSI_CTRL_DEBUG(dsi_ctrl, "cell index not set, default to 0\n");
  1752. index = 0;
  1753. }
  1754. dsi_ctrl->cell_index = index;
  1755. dsi_ctrl->name = of_get_property(of_node, "label", NULL);
  1756. if (!dsi_ctrl->name)
  1757. dsi_ctrl->name = DSI_CTRL_DEFAULT_LABEL;
  1758. dsi_ctrl->phy_isolation_enabled = of_property_read_bool(of_node,
  1759. "qcom,dsi-phy-isolation-enabled");
  1760. dsi_ctrl->null_insertion_enabled = of_property_read_bool(of_node,
  1761. "qcom,null-insertion-enabled");
  1762. dsi_ctrl->split_link_supported = of_property_read_bool(of_node,
  1763. "qcom,split-link-supported");
  1764. rc = of_property_read_u32(of_node, "frame-threshold-time-us",
  1765. &frame_threshold_time_us);
  1766. if (rc) {
  1767. DSI_CTRL_DEBUG(dsi_ctrl,
  1768. "frame-threshold-time not specified, defaulting\n");
  1769. frame_threshold_time_us = 2666;
  1770. }
  1771. dsi_ctrl->frame_threshold_time_us = frame_threshold_time_us;
  1772. return 0;
  1773. }
  1774. static int dsi_ctrl_dev_probe(struct platform_device *pdev)
  1775. {
  1776. struct dsi_ctrl *dsi_ctrl;
  1777. struct dsi_ctrl_list_item *item;
  1778. const struct of_device_id *id;
  1779. enum dsi_ctrl_version version;
  1780. int rc = 0;
  1781. id = of_match_node(msm_dsi_of_match, pdev->dev.of_node);
  1782. if (!id)
  1783. return -ENODEV;
  1784. version = *(enum dsi_ctrl_version *)id->data;
  1785. item = devm_kzalloc(&pdev->dev, sizeof(*item), GFP_KERNEL);
  1786. if (!item)
  1787. return -ENOMEM;
  1788. dsi_ctrl = devm_kzalloc(&pdev->dev, sizeof(*dsi_ctrl), GFP_KERNEL);
  1789. if (!dsi_ctrl)
  1790. return -ENOMEM;
  1791. dsi_ctrl->version = version;
  1792. dsi_ctrl->irq_info.irq_num = -1;
  1793. dsi_ctrl->irq_info.irq_stat_mask = 0x0;
  1794. INIT_WORK(&dsi_ctrl->post_cmd_tx_work, dsi_ctrl_post_cmd_transfer_work);
  1795. atomic_set(&dsi_ctrl->dma_irq_trig, 0);
  1796. spin_lock_init(&dsi_ctrl->irq_info.irq_lock);
  1797. rc = dsi_ctrl_dts_parse(dsi_ctrl, pdev->dev.of_node);
  1798. if (rc) {
  1799. DSI_CTRL_ERR(dsi_ctrl, "dts parse failed, rc = %d\n", rc);
  1800. goto fail;
  1801. }
  1802. rc = dsi_ctrl_init_regmap(pdev, dsi_ctrl);
  1803. if (rc) {
  1804. DSI_CTRL_ERR(dsi_ctrl, "Failed to parse register information, rc = %d\n",
  1805. rc);
  1806. goto fail;
  1807. }
  1808. rc = dsi_ctrl_supplies_init(pdev, dsi_ctrl);
  1809. if (rc) {
  1810. DSI_CTRL_ERR(dsi_ctrl, "Failed to parse voltage supplies, rc = %d\n",
  1811. rc);
  1812. goto fail;
  1813. }
  1814. rc = dsi_ctrl_clocks_init(pdev, dsi_ctrl);
  1815. if (rc) {
  1816. DSI_CTRL_ERR(dsi_ctrl, "Failed to parse clock information, rc = %d\n",
  1817. rc);
  1818. goto fail_supplies;
  1819. }
  1820. rc = dsi_catalog_ctrl_setup(&dsi_ctrl->hw, dsi_ctrl->version,
  1821. dsi_ctrl->cell_index, dsi_ctrl->phy_isolation_enabled,
  1822. dsi_ctrl->null_insertion_enabled);
  1823. if (rc) {
  1824. DSI_CTRL_ERR(dsi_ctrl, "Catalog does not support version (%d)\n",
  1825. dsi_ctrl->version);
  1826. goto fail_clks;
  1827. }
  1828. item->ctrl = dsi_ctrl;
  1829. sde_dbg_dsi_ctrl_register(dsi_ctrl->hw.base, dsi_ctrl->name);
  1830. mutex_lock(&dsi_ctrl_list_lock);
  1831. list_add(&item->list, &dsi_ctrl_list);
  1832. mutex_unlock(&dsi_ctrl_list_lock);
  1833. mutex_init(&dsi_ctrl->ctrl_lock);
  1834. dsi_ctrl->secure_mode = false;
  1835. dsi_ctrl->pdev = pdev;
  1836. platform_set_drvdata(pdev, dsi_ctrl);
  1837. DSI_CTRL_INFO(dsi_ctrl, "Probe successful\n");
  1838. return 0;
  1839. fail_clks:
  1840. (void)dsi_ctrl_clocks_deinit(dsi_ctrl);
  1841. fail_supplies:
  1842. (void)dsi_ctrl_supplies_deinit(dsi_ctrl);
  1843. fail:
  1844. return rc;
  1845. }
  1846. static int dsi_ctrl_dev_remove(struct platform_device *pdev)
  1847. {
  1848. int rc = 0;
  1849. struct dsi_ctrl *dsi_ctrl;
  1850. struct list_head *pos, *tmp;
  1851. dsi_ctrl = platform_get_drvdata(pdev);
  1852. mutex_lock(&dsi_ctrl_list_lock);
  1853. list_for_each_safe(pos, tmp, &dsi_ctrl_list) {
  1854. struct dsi_ctrl_list_item *n = list_entry(pos,
  1855. struct dsi_ctrl_list_item,
  1856. list);
  1857. if (n->ctrl == dsi_ctrl) {
  1858. list_del(&n->list);
  1859. break;
  1860. }
  1861. }
  1862. mutex_unlock(&dsi_ctrl_list_lock);
  1863. mutex_lock(&dsi_ctrl->ctrl_lock);
  1864. dsi_ctrl_isr_configure(dsi_ctrl, false);
  1865. rc = dsi_ctrl_supplies_deinit(dsi_ctrl);
  1866. if (rc)
  1867. DSI_CTRL_ERR(dsi_ctrl,
  1868. "failed to deinitialize voltage supplies, rc=%d\n",
  1869. rc);
  1870. rc = dsi_ctrl_clocks_deinit(dsi_ctrl);
  1871. if (rc)
  1872. DSI_CTRL_ERR(dsi_ctrl,
  1873. "failed to deinitialize clocks, rc=%d\n", rc);
  1874. atomic_set(&dsi_ctrl->dma_irq_trig, 0);
  1875. mutex_unlock(&dsi_ctrl->ctrl_lock);
  1876. mutex_destroy(&dsi_ctrl->ctrl_lock);
  1877. devm_kfree(&pdev->dev, dsi_ctrl);
  1878. platform_set_drvdata(pdev, NULL);
  1879. return 0;
  1880. }
  1881. static struct platform_driver dsi_ctrl_driver = {
  1882. .probe = dsi_ctrl_dev_probe,
  1883. .remove = dsi_ctrl_dev_remove,
  1884. .driver = {
  1885. .name = "drm_dsi_ctrl",
  1886. .of_match_table = msm_dsi_of_match,
  1887. .suppress_bind_attrs = true,
  1888. },
  1889. };
  1890. int dsi_ctrl_get_io_resources(struct msm_io_res *io_res)
  1891. {
  1892. int rc = 0;
  1893. struct dsi_ctrl_list_item *dsi_ctrl;
  1894. mutex_lock(&dsi_ctrl_list_lock);
  1895. list_for_each_entry(dsi_ctrl, &dsi_ctrl_list, list) {
  1896. rc = msm_dss_get_io_mem(dsi_ctrl->ctrl->pdev, &io_res->mem);
  1897. if (rc) {
  1898. DSI_CTRL_ERR(dsi_ctrl->ctrl,
  1899. "failed to get io mem, rc = %d\n", rc);
  1900. return rc;
  1901. }
  1902. }
  1903. mutex_unlock(&dsi_ctrl_list_lock);
  1904. return rc;
  1905. }
  1906. /**
  1907. * dsi_ctrl_check_resource() - check if DSI controller is probed
  1908. * @of_node: of_node of the DSI controller.
  1909. *
  1910. * Checks if the DSI controller has been probed and is available.
  1911. *
  1912. * Return: status of DSI controller
  1913. */
  1914. bool dsi_ctrl_check_resource(struct device_node *of_node)
  1915. {
  1916. struct list_head *pos, *tmp;
  1917. struct dsi_ctrl *ctrl = NULL;
  1918. mutex_lock(&dsi_ctrl_list_lock);
  1919. list_for_each_safe(pos, tmp, &dsi_ctrl_list) {
  1920. struct dsi_ctrl_list_item *n;
  1921. n = list_entry(pos, struct dsi_ctrl_list_item, list);
  1922. if (!n->ctrl || !n->ctrl->pdev)
  1923. break;
  1924. if (n->ctrl->pdev->dev.of_node == of_node) {
  1925. ctrl = n->ctrl;
  1926. break;
  1927. }
  1928. }
  1929. mutex_unlock(&dsi_ctrl_list_lock);
  1930. return ctrl ? true : false;
  1931. }
  1932. /**
  1933. * dsi_ctrl_get() - get a dsi_ctrl handle from an of_node
  1934. * @of_node: of_node of the DSI controller.
  1935. *
  1936. * Gets the DSI controller handle for the corresponding of_node. The ref count
  1937. * is incremented to one and all subsequent gets will fail until the original
  1938. * clients calls a put.
  1939. *
  1940. * Return: DSI Controller handle.
  1941. */
  1942. struct dsi_ctrl *dsi_ctrl_get(struct device_node *of_node)
  1943. {
  1944. struct list_head *pos, *tmp;
  1945. struct dsi_ctrl *ctrl = NULL;
  1946. mutex_lock(&dsi_ctrl_list_lock);
  1947. list_for_each_safe(pos, tmp, &dsi_ctrl_list) {
  1948. struct dsi_ctrl_list_item *n;
  1949. n = list_entry(pos, struct dsi_ctrl_list_item, list);
  1950. if (n->ctrl->pdev->dev.of_node == of_node) {
  1951. ctrl = n->ctrl;
  1952. break;
  1953. }
  1954. }
  1955. mutex_unlock(&dsi_ctrl_list_lock);
  1956. if (!ctrl) {
  1957. DSI_CTRL_ERR(ctrl, "Device with of node not found rc=%d\n",
  1958. -EPROBE_DEFER);
  1959. ctrl = ERR_PTR(-EPROBE_DEFER);
  1960. return ctrl;
  1961. }
  1962. mutex_lock(&ctrl->ctrl_lock);
  1963. if (ctrl->refcount == 1) {
  1964. DSI_CTRL_ERR(ctrl, "Device in use\n");
  1965. mutex_unlock(&ctrl->ctrl_lock);
  1966. ctrl = ERR_PTR(-EBUSY);
  1967. return ctrl;
  1968. }
  1969. ctrl->refcount++;
  1970. mutex_unlock(&ctrl->ctrl_lock);
  1971. return ctrl;
  1972. }
  1973. /**
  1974. * dsi_ctrl_put() - releases a dsi controller handle.
  1975. * @dsi_ctrl: DSI controller handle.
  1976. *
  1977. * Releases the DSI controller. Driver will clean up all resources and puts back
  1978. * the DSI controller into reset state.
  1979. */
  1980. void dsi_ctrl_put(struct dsi_ctrl *dsi_ctrl)
  1981. {
  1982. mutex_lock(&dsi_ctrl->ctrl_lock);
  1983. if (dsi_ctrl->refcount == 0)
  1984. DSI_CTRL_ERR(dsi_ctrl, "Unbalanced %s call\n", __func__);
  1985. else
  1986. dsi_ctrl->refcount--;
  1987. mutex_unlock(&dsi_ctrl->ctrl_lock);
  1988. }
  1989. /**
  1990. * dsi_ctrl_drv_init() - initialize dsi controller driver.
  1991. * @dsi_ctrl: DSI controller handle.
  1992. * @parent: Parent directory for debug fs.
  1993. *
  1994. * Initializes DSI controller driver. Driver should be initialized after
  1995. * dsi_ctrl_get() succeeds.
  1996. *
  1997. * Return: error code.
  1998. */
  1999. int dsi_ctrl_drv_init(struct dsi_ctrl *dsi_ctrl, struct dentry *parent)
  2000. {
  2001. char dbg_name[DSI_DEBUG_NAME_LEN];
  2002. int rc = 0;
  2003. if (!dsi_ctrl) {
  2004. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2005. return -EINVAL;
  2006. }
  2007. mutex_lock(&dsi_ctrl->ctrl_lock);
  2008. rc = dsi_ctrl_drv_state_init(dsi_ctrl);
  2009. if (rc) {
  2010. DSI_CTRL_ERR(dsi_ctrl, "Failed to initialize driver state, rc=%d\n",
  2011. rc);
  2012. goto error;
  2013. }
  2014. rc = dsi_ctrl_debugfs_init(dsi_ctrl, parent);
  2015. if (rc) {
  2016. DSI_CTRL_ERR(dsi_ctrl, "failed to init debug fs, rc=%d\n", rc);
  2017. goto error;
  2018. }
  2019. snprintf(dbg_name, DSI_DEBUG_NAME_LEN, "dsi%d_ctrl", dsi_ctrl->cell_index);
  2020. sde_dbg_reg_register_base(dbg_name, dsi_ctrl->hw.base,
  2021. msm_iomap_size(dsi_ctrl->pdev, "dsi_ctrl"),
  2022. msm_get_phys_addr(dsi_ctrl->pdev, "dsi_ctrl"), SDE_DBG_DSI);
  2023. error:
  2024. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2025. return rc;
  2026. }
  2027. /**
  2028. * dsi_ctrl_drv_deinit() - de-initializes dsi controller driver
  2029. * @dsi_ctrl: DSI controller handle.
  2030. *
  2031. * Releases all resources acquired by dsi_ctrl_drv_init().
  2032. *
  2033. * Return: error code.
  2034. */
  2035. int dsi_ctrl_drv_deinit(struct dsi_ctrl *dsi_ctrl)
  2036. {
  2037. int rc = 0;
  2038. if (!dsi_ctrl) {
  2039. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2040. return -EINVAL;
  2041. }
  2042. mutex_lock(&dsi_ctrl->ctrl_lock);
  2043. rc = dsi_ctrl_debugfs_deinit(dsi_ctrl);
  2044. if (rc)
  2045. DSI_CTRL_ERR(dsi_ctrl, "failed to release debugfs root, rc=%d\n",
  2046. rc);
  2047. rc = dsi_ctrl_buffer_deinit(dsi_ctrl);
  2048. if (rc)
  2049. DSI_CTRL_ERR(dsi_ctrl, "Failed to free cmd buffers, rc=%d\n",
  2050. rc);
  2051. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2052. return rc;
  2053. }
  2054. int dsi_ctrl_clk_cb_register(struct dsi_ctrl *dsi_ctrl,
  2055. struct clk_ctrl_cb *clk_cb)
  2056. {
  2057. if (!dsi_ctrl || !clk_cb) {
  2058. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2059. return -EINVAL;
  2060. }
  2061. dsi_ctrl->clk_cb.priv = clk_cb->priv;
  2062. dsi_ctrl->clk_cb.dsi_clk_cb = clk_cb->dsi_clk_cb;
  2063. return 0;
  2064. }
  2065. /**
  2066. * dsi_ctrl_phy_sw_reset() - perform a PHY software reset
  2067. * @dsi_ctrl: DSI controller handle.
  2068. *
  2069. * Performs a PHY software reset on the DSI controller. Reset should be done
  2070. * when the controller power state is DSI_CTRL_POWER_CORE_CLK_ON and the PHY is
  2071. * not enabled.
  2072. *
  2073. * This function will fail if driver is in any other state.
  2074. *
  2075. * Return: error code.
  2076. */
  2077. int dsi_ctrl_phy_sw_reset(struct dsi_ctrl *dsi_ctrl)
  2078. {
  2079. int rc = 0;
  2080. if (!dsi_ctrl) {
  2081. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2082. return -EINVAL;
  2083. }
  2084. mutex_lock(&dsi_ctrl->ctrl_lock);
  2085. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_PHY_SW_RESET, 0x0);
  2086. if (rc) {
  2087. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  2088. rc);
  2089. goto error;
  2090. }
  2091. dsi_ctrl->hw.ops.phy_sw_reset(&dsi_ctrl->hw);
  2092. DSI_CTRL_DEBUG(dsi_ctrl, "PHY soft reset done\n");
  2093. dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_PHY_SW_RESET, 0x0);
  2094. error:
  2095. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2096. return rc;
  2097. }
  2098. /**
  2099. * dsi_ctrl_seamless_timing_update() - update only controller timing
  2100. * @dsi_ctrl: DSI controller handle.
  2101. * @timing: New DSI timing info
  2102. *
  2103. * Updates host timing values to conduct a seamless transition to new timing
  2104. * For example, to update the porch values in a dynamic fps switch.
  2105. *
  2106. * Return: error code.
  2107. */
  2108. int dsi_ctrl_async_timing_update(struct dsi_ctrl *dsi_ctrl,
  2109. struct dsi_mode_info *timing)
  2110. {
  2111. struct dsi_mode_info *host_mode;
  2112. int rc = 0;
  2113. if (!dsi_ctrl || !timing) {
  2114. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2115. return -EINVAL;
  2116. }
  2117. mutex_lock(&dsi_ctrl->ctrl_lock);
  2118. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_ASYNC_TIMING,
  2119. DSI_CTRL_ENGINE_ON);
  2120. if (rc) {
  2121. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  2122. rc);
  2123. goto exit;
  2124. }
  2125. host_mode = &dsi_ctrl->host_config.video_timing;
  2126. memcpy(host_mode, timing, sizeof(*host_mode));
  2127. dsi_ctrl->hw.ops.set_timing_db(&dsi_ctrl->hw, true);
  2128. dsi_ctrl->hw.ops.set_video_timing(&dsi_ctrl->hw, host_mode);
  2129. exit:
  2130. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2131. return rc;
  2132. }
  2133. /**
  2134. * dsi_ctrl_timing_db_update() - update only controller Timing DB
  2135. * @dsi_ctrl: DSI controller handle.
  2136. * @enable: Enable/disable Timing DB register
  2137. *
  2138. * Update timing db register value during dfps usecases
  2139. *
  2140. * Return: error code.
  2141. */
  2142. int dsi_ctrl_timing_db_update(struct dsi_ctrl *dsi_ctrl,
  2143. bool enable)
  2144. {
  2145. int rc = 0;
  2146. if (!dsi_ctrl) {
  2147. DSI_CTRL_ERR(dsi_ctrl, "Invalid dsi_ctrl\n");
  2148. return -EINVAL;
  2149. }
  2150. mutex_lock(&dsi_ctrl->ctrl_lock);
  2151. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_ASYNC_TIMING,
  2152. DSI_CTRL_ENGINE_ON);
  2153. if (rc) {
  2154. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  2155. rc);
  2156. goto exit;
  2157. }
  2158. /*
  2159. * Add HW recommended delay for dfps feature.
  2160. * When prefetch is enabled, MDSS HW works on 2 vsync
  2161. * boundaries i.e. mdp_vsync and panel_vsync.
  2162. * In the current implementation we are only waiting
  2163. * for mdp_vsync. We need to make sure that interface
  2164. * flush is after panel_vsync. So, added the recommended
  2165. * delays after dfps update.
  2166. */
  2167. usleep_range(2000, 2010);
  2168. dsi_ctrl->hw.ops.set_timing_db(&dsi_ctrl->hw, enable);
  2169. exit:
  2170. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2171. return rc;
  2172. }
  2173. int dsi_ctrl_timing_setup(struct dsi_ctrl *dsi_ctrl)
  2174. {
  2175. int rc = 0;
  2176. if (!dsi_ctrl) {
  2177. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2178. return -EINVAL;
  2179. }
  2180. mutex_lock(&dsi_ctrl->ctrl_lock);
  2181. if (dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE) {
  2182. dsi_ctrl->hw.ops.cmd_engine_setup(&dsi_ctrl->hw,
  2183. &dsi_ctrl->host_config.common_config,
  2184. &dsi_ctrl->host_config.u.cmd_engine);
  2185. dsi_ctrl->hw.ops.setup_cmd_stream(&dsi_ctrl->hw,
  2186. &dsi_ctrl->host_config.video_timing,
  2187. &dsi_ctrl->host_config.common_config,
  2188. 0x0,
  2189. &dsi_ctrl->roi);
  2190. dsi_ctrl->hw.ops.cmd_engine_en(&dsi_ctrl->hw, true);
  2191. } else {
  2192. dsi_ctrl->hw.ops.video_engine_setup(&dsi_ctrl->hw,
  2193. &dsi_ctrl->host_config.common_config,
  2194. &dsi_ctrl->host_config.u.video_engine);
  2195. dsi_ctrl->hw.ops.set_video_timing(&dsi_ctrl->hw,
  2196. &dsi_ctrl->host_config.video_timing);
  2197. dsi_ctrl->hw.ops.video_engine_en(&dsi_ctrl->hw, true);
  2198. }
  2199. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2200. return rc;
  2201. }
  2202. int dsi_ctrl_setup(struct dsi_ctrl *dsi_ctrl)
  2203. {
  2204. int rc = 0;
  2205. rc = dsi_ctrl_timing_setup(dsi_ctrl);
  2206. if (rc)
  2207. return -EINVAL;
  2208. mutex_lock(&dsi_ctrl->ctrl_lock);
  2209. dsi_ctrl->hw.ops.setup_lane_map(&dsi_ctrl->hw,
  2210. &dsi_ctrl->host_config.lane_map);
  2211. dsi_ctrl->hw.ops.host_setup(&dsi_ctrl->hw,
  2212. &dsi_ctrl->host_config.common_config);
  2213. dsi_ctrl->hw.ops.enable_status_interrupts(&dsi_ctrl->hw, 0x0);
  2214. dsi_ctrl_enable_error_interrupts(dsi_ctrl);
  2215. dsi_ctrl->hw.ops.ctrl_en(&dsi_ctrl->hw, true);
  2216. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2217. return rc;
  2218. }
  2219. int dsi_ctrl_set_roi(struct dsi_ctrl *dsi_ctrl, struct dsi_rect *roi,
  2220. bool *changed)
  2221. {
  2222. int rc = 0;
  2223. if (!dsi_ctrl || !roi || !changed) {
  2224. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2225. return -EINVAL;
  2226. }
  2227. mutex_lock(&dsi_ctrl->ctrl_lock);
  2228. if ((!dsi_rect_is_equal(&dsi_ctrl->roi, roi)) ||
  2229. dsi_ctrl->modeupdated) {
  2230. *changed = true;
  2231. memcpy(&dsi_ctrl->roi, roi, sizeof(dsi_ctrl->roi));
  2232. dsi_ctrl->modeupdated = false;
  2233. } else
  2234. *changed = false;
  2235. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2236. return rc;
  2237. }
  2238. /**
  2239. * dsi_ctrl_config_clk_gating() - Enable/disable DSI PHY clk gating.
  2240. * @dsi_ctrl: DSI controller handle.
  2241. * @enable: Enable/disable DSI PHY clk gating
  2242. * @clk_selection: clock to enable/disable clock gating
  2243. *
  2244. * Return: error code.
  2245. */
  2246. int dsi_ctrl_config_clk_gating(struct dsi_ctrl *dsi_ctrl, bool enable,
  2247. enum dsi_clk_gate_type clk_selection)
  2248. {
  2249. if (!dsi_ctrl) {
  2250. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2251. return -EINVAL;
  2252. }
  2253. if (dsi_ctrl->hw.ops.config_clk_gating)
  2254. dsi_ctrl->hw.ops.config_clk_gating(&dsi_ctrl->hw, enable,
  2255. clk_selection);
  2256. return 0;
  2257. }
  2258. /**
  2259. * dsi_ctrl_phy_reset_config() - Mask/unmask propagation of ahb reset signal
  2260. * to DSI PHY hardware.
  2261. * @dsi_ctrl: DSI controller handle.
  2262. * @enable: Mask/unmask the PHY reset signal.
  2263. *
  2264. * Return: error code.
  2265. */
  2266. int dsi_ctrl_phy_reset_config(struct dsi_ctrl *dsi_ctrl, bool enable)
  2267. {
  2268. if (!dsi_ctrl) {
  2269. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2270. return -EINVAL;
  2271. }
  2272. if (dsi_ctrl->hw.ops.phy_reset_config)
  2273. dsi_ctrl->hw.ops.phy_reset_config(&dsi_ctrl->hw, enable);
  2274. return 0;
  2275. }
  2276. static bool dsi_ctrl_check_for_spurious_error_interrupts(
  2277. struct dsi_ctrl *dsi_ctrl)
  2278. {
  2279. const unsigned long intr_check_interval = msecs_to_jiffies(1000);
  2280. const unsigned int interrupt_threshold = 15;
  2281. unsigned long jiffies_now = jiffies;
  2282. if (!dsi_ctrl) {
  2283. DSI_CTRL_ERR(dsi_ctrl, "Invalid DSI controller structure\n");
  2284. return false;
  2285. }
  2286. if (dsi_ctrl->jiffies_start == 0)
  2287. dsi_ctrl->jiffies_start = jiffies;
  2288. dsi_ctrl->error_interrupt_count++;
  2289. if ((jiffies_now - dsi_ctrl->jiffies_start) < intr_check_interval) {
  2290. if (dsi_ctrl->error_interrupt_count > interrupt_threshold) {
  2291. SDE_EVT32_IRQ(dsi_ctrl->cell_index,
  2292. dsi_ctrl->error_interrupt_count,
  2293. interrupt_threshold);
  2294. return true;
  2295. }
  2296. } else {
  2297. dsi_ctrl->jiffies_start = jiffies;
  2298. dsi_ctrl->error_interrupt_count = 1;
  2299. }
  2300. return false;
  2301. }
  2302. static void dsi_ctrl_handle_error_status(struct dsi_ctrl *dsi_ctrl,
  2303. unsigned long error)
  2304. {
  2305. struct dsi_event_cb_info cb_info;
  2306. cb_info = dsi_ctrl->irq_info.irq_err_cb;
  2307. /* disable error interrupts */
  2308. if (dsi_ctrl->hw.ops.error_intr_ctrl)
  2309. dsi_ctrl->hw.ops.error_intr_ctrl(&dsi_ctrl->hw, false);
  2310. /* clear error interrupts first */
  2311. if (dsi_ctrl->hw.ops.clear_error_status)
  2312. dsi_ctrl->hw.ops.clear_error_status(&dsi_ctrl->hw,
  2313. error);
  2314. /* DTLN PHY error */
  2315. if (error & 0x3000E00)
  2316. DSI_CTRL_ERR(dsi_ctrl, "dsi PHY contention error: 0x%lx\n",
  2317. error);
  2318. /* ignore TX timeout if blpp_lp11 is disabled */
  2319. if (dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE &&
  2320. !dsi_ctrl->host_config.u.video_engine.bllp_lp11_en &&
  2321. !dsi_ctrl->host_config.u.video_engine.eof_bllp_lp11_en)
  2322. error &= ~DSI_HS_TX_TIMEOUT;
  2323. /* TX timeout error */
  2324. if (error & 0xE0) {
  2325. if (error & 0xA0) {
  2326. if (cb_info.event_cb) {
  2327. cb_info.event_idx = DSI_LP_Rx_TIMEOUT;
  2328. (void)cb_info.event_cb(cb_info.event_usr_ptr,
  2329. cb_info.event_idx,
  2330. dsi_ctrl->cell_index,
  2331. 0, 0, 0, 0);
  2332. }
  2333. }
  2334. }
  2335. /* DSI FIFO OVERFLOW error */
  2336. if (error & 0xF0000) {
  2337. u32 mask = 0;
  2338. if (dsi_ctrl->hw.ops.get_error_mask)
  2339. mask = dsi_ctrl->hw.ops.get_error_mask(&dsi_ctrl->hw);
  2340. /* no need to report FIFO overflow if already masked */
  2341. if (cb_info.event_cb && !(mask & 0xf0000)) {
  2342. cb_info.event_idx = DSI_FIFO_OVERFLOW;
  2343. (void)cb_info.event_cb(cb_info.event_usr_ptr,
  2344. cb_info.event_idx,
  2345. dsi_ctrl->cell_index,
  2346. 0, 0, 0, 0);
  2347. }
  2348. }
  2349. /* DSI FIFO UNDERFLOW error */
  2350. if (error & 0xF00000) {
  2351. if (cb_info.event_cb) {
  2352. cb_info.event_idx = DSI_FIFO_UNDERFLOW;
  2353. (void)cb_info.event_cb(cb_info.event_usr_ptr,
  2354. cb_info.event_idx,
  2355. dsi_ctrl->cell_index,
  2356. 0, 0, 0, 0);
  2357. }
  2358. }
  2359. /* DSI PLL UNLOCK error */
  2360. if (error & BIT(8))
  2361. DSI_CTRL_ERR(dsi_ctrl, "dsi PLL unlock error: 0x%lx\n", error);
  2362. /* ACK error */
  2363. if (error & 0xF)
  2364. DSI_CTRL_ERR(dsi_ctrl, "ack error: 0x%lx\n", error);
  2365. /*
  2366. * DSI Phy can go into bad state during ESD influence. This can
  2367. * manifest as various types of spurious error interrupts on
  2368. * DSI controller. This check will allow us to handle afore mentioned
  2369. * case and prevent us from re enabling interrupts until a full ESD
  2370. * recovery is completed.
  2371. */
  2372. if (dsi_ctrl_check_for_spurious_error_interrupts(dsi_ctrl) &&
  2373. dsi_ctrl->esd_check_underway) {
  2374. dsi_ctrl->hw.ops.soft_reset(&dsi_ctrl->hw);
  2375. return;
  2376. }
  2377. /* enable back DSI interrupts */
  2378. if (dsi_ctrl->hw.ops.error_intr_ctrl)
  2379. dsi_ctrl->hw.ops.error_intr_ctrl(&dsi_ctrl->hw, true);
  2380. }
  2381. /**
  2382. * dsi_ctrl_isr - interrupt service routine for DSI CTRL component
  2383. * @irq: Incoming IRQ number
  2384. * @ptr: Pointer to user data structure (struct dsi_ctrl)
  2385. * Returns: IRQ_HANDLED if no further action required
  2386. */
  2387. static irqreturn_t dsi_ctrl_isr(int irq, void *ptr)
  2388. {
  2389. struct dsi_ctrl *dsi_ctrl;
  2390. struct dsi_event_cb_info cb_info;
  2391. unsigned long flags;
  2392. uint32_t status = 0x0, i;
  2393. uint64_t errors = 0x0;
  2394. if (!ptr)
  2395. return IRQ_NONE;
  2396. dsi_ctrl = ptr;
  2397. /* check status interrupts */
  2398. if (dsi_ctrl->hw.ops.get_interrupt_status)
  2399. status = dsi_ctrl->hw.ops.get_interrupt_status(&dsi_ctrl->hw);
  2400. /* check error interrupts */
  2401. if (dsi_ctrl->hw.ops.get_error_status)
  2402. errors = dsi_ctrl->hw.ops.get_error_status(&dsi_ctrl->hw);
  2403. /* clear interrupts */
  2404. if (dsi_ctrl->hw.ops.clear_interrupt_status)
  2405. dsi_ctrl->hw.ops.clear_interrupt_status(&dsi_ctrl->hw, 0x0);
  2406. SDE_EVT32_IRQ(dsi_ctrl->cell_index, status, errors);
  2407. /* handle DSI error recovery */
  2408. if (status & DSI_ERROR)
  2409. dsi_ctrl_handle_error_status(dsi_ctrl, errors);
  2410. if (status & DSI_CMD_MODE_DMA_DONE) {
  2411. if (dsi_ctrl->enable_cmd_dma_stats) {
  2412. u32 reg = dsi_ctrl->hw.ops.log_line_count(&dsi_ctrl->hw,
  2413. dsi_ctrl->cmd_mode);
  2414. dsi_ctrl->cmd_success_line = (reg & 0xFFFF);
  2415. dsi_ctrl->cmd_success_frame = ((reg >> 16) & 0xFFFF);
  2416. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_CASE1,
  2417. dsi_ctrl->cmd_success_line,
  2418. dsi_ctrl->cmd_success_frame);
  2419. }
  2420. atomic_set(&dsi_ctrl->dma_irq_trig, 1);
  2421. dsi_ctrl_disable_status_interrupt(dsi_ctrl,
  2422. DSI_SINT_CMD_MODE_DMA_DONE);
  2423. complete_all(&dsi_ctrl->irq_info.cmd_dma_done);
  2424. }
  2425. if (status & DSI_CMD_FRAME_DONE) {
  2426. dsi_ctrl_disable_status_interrupt(dsi_ctrl,
  2427. DSI_SINT_CMD_FRAME_DONE);
  2428. complete_all(&dsi_ctrl->irq_info.cmd_frame_done);
  2429. }
  2430. if (status & DSI_VIDEO_MODE_FRAME_DONE) {
  2431. dsi_ctrl_disable_status_interrupt(dsi_ctrl,
  2432. DSI_SINT_VIDEO_MODE_FRAME_DONE);
  2433. complete_all(&dsi_ctrl->irq_info.vid_frame_done);
  2434. }
  2435. if (status & DSI_BTA_DONE) {
  2436. u32 fifo_overflow_mask = (DSI_DLN0_HS_FIFO_OVERFLOW |
  2437. DSI_DLN1_HS_FIFO_OVERFLOW |
  2438. DSI_DLN2_HS_FIFO_OVERFLOW |
  2439. DSI_DLN3_HS_FIFO_OVERFLOW);
  2440. dsi_ctrl_disable_status_interrupt(dsi_ctrl,
  2441. DSI_SINT_BTA_DONE);
  2442. complete_all(&dsi_ctrl->irq_info.bta_done);
  2443. if (dsi_ctrl->hw.ops.clear_error_status)
  2444. dsi_ctrl->hw.ops.clear_error_status(&dsi_ctrl->hw,
  2445. fifo_overflow_mask);
  2446. }
  2447. for (i = 0; status && i < DSI_STATUS_INTERRUPT_COUNT; ++i) {
  2448. if (status & 0x1) {
  2449. spin_lock_irqsave(&dsi_ctrl->irq_info.irq_lock, flags);
  2450. cb_info = dsi_ctrl->irq_info.irq_stat_cb[i];
  2451. spin_unlock_irqrestore(
  2452. &dsi_ctrl->irq_info.irq_lock, flags);
  2453. if (cb_info.event_cb)
  2454. (void)cb_info.event_cb(cb_info.event_usr_ptr,
  2455. cb_info.event_idx,
  2456. dsi_ctrl->cell_index,
  2457. irq, 0, 0, 0);
  2458. }
  2459. status >>= 1;
  2460. }
  2461. return IRQ_HANDLED;
  2462. }
  2463. /**
  2464. * _dsi_ctrl_setup_isr - register ISR handler
  2465. * @dsi_ctrl: Pointer to associated dsi_ctrl structure
  2466. * Returns: Zero on success
  2467. */
  2468. static int _dsi_ctrl_setup_isr(struct dsi_ctrl *dsi_ctrl)
  2469. {
  2470. int irq_num, rc;
  2471. if (!dsi_ctrl)
  2472. return -EINVAL;
  2473. if (dsi_ctrl->irq_info.irq_num != -1)
  2474. return 0;
  2475. init_completion(&dsi_ctrl->irq_info.cmd_dma_done);
  2476. init_completion(&dsi_ctrl->irq_info.vid_frame_done);
  2477. init_completion(&dsi_ctrl->irq_info.cmd_frame_done);
  2478. init_completion(&dsi_ctrl->irq_info.bta_done);
  2479. irq_num = platform_get_irq(dsi_ctrl->pdev, 0);
  2480. if (irq_num < 0) {
  2481. DSI_CTRL_ERR(dsi_ctrl, "Failed to get IRQ number, %d\n",
  2482. irq_num);
  2483. rc = irq_num;
  2484. } else {
  2485. rc = devm_request_threaded_irq(&dsi_ctrl->pdev->dev, irq_num,
  2486. dsi_ctrl_isr, NULL, 0, "dsi_ctrl", dsi_ctrl);
  2487. if (rc) {
  2488. DSI_CTRL_ERR(dsi_ctrl, "Failed to request IRQ, %d\n",
  2489. rc);
  2490. } else {
  2491. dsi_ctrl->irq_info.irq_num = irq_num;
  2492. disable_irq_nosync(irq_num);
  2493. DSI_CTRL_INFO(dsi_ctrl, "IRQ %d registered\n", irq_num);
  2494. }
  2495. }
  2496. return rc;
  2497. }
  2498. /**
  2499. * _dsi_ctrl_destroy_isr - unregister ISR handler
  2500. * @dsi_ctrl: Pointer to associated dsi_ctrl structure
  2501. */
  2502. static void _dsi_ctrl_destroy_isr(struct dsi_ctrl *dsi_ctrl)
  2503. {
  2504. if (!dsi_ctrl || !dsi_ctrl->pdev || dsi_ctrl->irq_info.irq_num < 0)
  2505. return;
  2506. if (dsi_ctrl->irq_info.irq_num != -1) {
  2507. devm_free_irq(&dsi_ctrl->pdev->dev,
  2508. dsi_ctrl->irq_info.irq_num, dsi_ctrl);
  2509. dsi_ctrl->irq_info.irq_num = -1;
  2510. }
  2511. }
  2512. void dsi_ctrl_enable_status_interrupt(struct dsi_ctrl *dsi_ctrl,
  2513. uint32_t intr_idx, struct dsi_event_cb_info *event_info)
  2514. {
  2515. unsigned long flags;
  2516. if (!dsi_ctrl || dsi_ctrl->irq_info.irq_num == -1 ||
  2517. intr_idx >= DSI_STATUS_INTERRUPT_COUNT)
  2518. return;
  2519. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY, intr_idx);
  2520. spin_lock_irqsave(&dsi_ctrl->irq_info.irq_lock, flags);
  2521. if (dsi_ctrl->irq_info.irq_stat_refcount[intr_idx] == 0) {
  2522. /* enable irq on first request */
  2523. if (dsi_ctrl->irq_info.irq_stat_mask == 0)
  2524. enable_irq(dsi_ctrl->irq_info.irq_num);
  2525. /* update hardware mask */
  2526. dsi_ctrl->irq_info.irq_stat_mask |= BIT(intr_idx);
  2527. dsi_ctrl->hw.ops.enable_status_interrupts(&dsi_ctrl->hw,
  2528. dsi_ctrl->irq_info.irq_stat_mask);
  2529. }
  2530. if (intr_idx == DSI_SINT_CMD_MODE_DMA_DONE)
  2531. dsi_ctrl->hw.ops.enable_status_interrupts(&dsi_ctrl->hw,
  2532. dsi_ctrl->irq_info.irq_stat_mask);
  2533. ++(dsi_ctrl->irq_info.irq_stat_refcount[intr_idx]);
  2534. if (event_info)
  2535. dsi_ctrl->irq_info.irq_stat_cb[intr_idx] = *event_info;
  2536. spin_unlock_irqrestore(&dsi_ctrl->irq_info.irq_lock, flags);
  2537. }
  2538. void dsi_ctrl_disable_status_interrupt(struct dsi_ctrl *dsi_ctrl,
  2539. uint32_t intr_idx)
  2540. {
  2541. unsigned long flags;
  2542. if (!dsi_ctrl || intr_idx >= DSI_STATUS_INTERRUPT_COUNT)
  2543. return;
  2544. SDE_EVT32_IRQ(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY, intr_idx);
  2545. spin_lock_irqsave(&dsi_ctrl->irq_info.irq_lock, flags);
  2546. if (dsi_ctrl->irq_info.irq_stat_refcount[intr_idx])
  2547. if (--(dsi_ctrl->irq_info.irq_stat_refcount[intr_idx]) == 0) {
  2548. dsi_ctrl->irq_info.irq_stat_mask &= ~BIT(intr_idx);
  2549. dsi_ctrl->hw.ops.enable_status_interrupts(&dsi_ctrl->hw,
  2550. dsi_ctrl->irq_info.irq_stat_mask);
  2551. /* don't need irq if no lines are enabled */
  2552. if (dsi_ctrl->irq_info.irq_stat_mask == 0 &&
  2553. dsi_ctrl->irq_info.irq_num != -1)
  2554. disable_irq_nosync(dsi_ctrl->irq_info.irq_num);
  2555. }
  2556. spin_unlock_irqrestore(&dsi_ctrl->irq_info.irq_lock, flags);
  2557. }
  2558. int dsi_ctrl_host_timing_update(struct dsi_ctrl *dsi_ctrl)
  2559. {
  2560. if (!dsi_ctrl) {
  2561. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2562. return -EINVAL;
  2563. }
  2564. if (dsi_ctrl->hw.ops.host_setup)
  2565. dsi_ctrl->hw.ops.host_setup(&dsi_ctrl->hw,
  2566. &dsi_ctrl->host_config.common_config);
  2567. if (dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE) {
  2568. if (dsi_ctrl->hw.ops.cmd_engine_setup)
  2569. dsi_ctrl->hw.ops.cmd_engine_setup(&dsi_ctrl->hw,
  2570. &dsi_ctrl->host_config.common_config,
  2571. &dsi_ctrl->host_config.u.cmd_engine);
  2572. if (dsi_ctrl->hw.ops.setup_cmd_stream)
  2573. dsi_ctrl->hw.ops.setup_cmd_stream(&dsi_ctrl->hw,
  2574. &dsi_ctrl->host_config.video_timing,
  2575. &dsi_ctrl->host_config.common_config,
  2576. 0x0, NULL);
  2577. } else {
  2578. DSI_CTRL_ERR(dsi_ctrl, "invalid panel mode for resolution switch\n");
  2579. return -EINVAL;
  2580. }
  2581. return 0;
  2582. }
  2583. /**
  2584. * dsi_ctrl_update_host_state() - Update the host initialization state.
  2585. * @dsi_ctrl: DSI controller handle.
  2586. * @op: ctrl driver ops
  2587. * @enable: boolean signifying host state.
  2588. *
  2589. * Update the host status only while exiting from ulps during suspend state.
  2590. *
  2591. * Return: error code.
  2592. */
  2593. int dsi_ctrl_update_host_state(struct dsi_ctrl *dsi_ctrl,
  2594. enum dsi_ctrl_driver_ops op, bool enable)
  2595. {
  2596. int rc = 0;
  2597. u32 state = enable ? 0x1 : 0x0;
  2598. if (!dsi_ctrl)
  2599. return rc;
  2600. mutex_lock(&dsi_ctrl->ctrl_lock);
  2601. rc = dsi_ctrl_check_state(dsi_ctrl, op, state);
  2602. if (rc) {
  2603. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  2604. rc);
  2605. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2606. return rc;
  2607. }
  2608. dsi_ctrl_update_state(dsi_ctrl, op, state);
  2609. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2610. return rc;
  2611. }
  2612. /**
  2613. * dsi_ctrl_host_init() - Initialize DSI host hardware.
  2614. * @dsi_ctrl: DSI controller handle.
  2615. * @skip_op: Boolean to indicate few operations can be skipped.
  2616. * Set during the cont-splash or trusted-vm enable case.
  2617. *
  2618. * Initializes DSI controller hardware with host configuration provided by
  2619. * dsi_ctrl_update_host_config(). Initialization can be performed only during
  2620. * DSI_CTRL_POWER_CORE_CLK_ON state and after the PHY SW reset has been
  2621. * performed.
  2622. *
  2623. * Return: error code.
  2624. */
  2625. int dsi_ctrl_host_init(struct dsi_ctrl *dsi_ctrl, bool skip_op)
  2626. {
  2627. int rc = 0;
  2628. if (!dsi_ctrl) {
  2629. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2630. return -EINVAL;
  2631. }
  2632. mutex_lock(&dsi_ctrl->ctrl_lock);
  2633. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_HOST_INIT, 0x1);
  2634. if (rc) {
  2635. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  2636. rc);
  2637. goto error;
  2638. }
  2639. /*
  2640. * For continuous splash/trusted vm usecases we omit hw operations
  2641. * as bootloader/primary vm takes care of them respectively
  2642. */
  2643. if (!skip_op) {
  2644. dsi_ctrl->hw.ops.setup_lane_map(&dsi_ctrl->hw,
  2645. &dsi_ctrl->host_config.lane_map);
  2646. dsi_ctrl->hw.ops.host_setup(&dsi_ctrl->hw,
  2647. &dsi_ctrl->host_config.common_config);
  2648. if (dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE) {
  2649. dsi_ctrl->hw.ops.cmd_engine_setup(&dsi_ctrl->hw,
  2650. &dsi_ctrl->host_config.common_config,
  2651. &dsi_ctrl->host_config.u.cmd_engine);
  2652. dsi_ctrl->hw.ops.setup_cmd_stream(&dsi_ctrl->hw,
  2653. &dsi_ctrl->host_config.video_timing,
  2654. &dsi_ctrl->host_config.common_config,
  2655. 0x0,
  2656. NULL);
  2657. } else {
  2658. dsi_ctrl->hw.ops.video_engine_setup(&dsi_ctrl->hw,
  2659. &dsi_ctrl->host_config.common_config,
  2660. &dsi_ctrl->host_config.u.video_engine);
  2661. dsi_ctrl->hw.ops.set_video_timing(&dsi_ctrl->hw,
  2662. &dsi_ctrl->host_config.video_timing);
  2663. }
  2664. }
  2665. dsi_ctrl->hw.ops.enable_status_interrupts(&dsi_ctrl->hw, 0x0);
  2666. dsi_ctrl_enable_error_interrupts(dsi_ctrl);
  2667. DSI_CTRL_DEBUG(dsi_ctrl, "Host initialization complete, skip op: %d\n",
  2668. skip_op);
  2669. dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_HOST_INIT, 0x1);
  2670. error:
  2671. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2672. return rc;
  2673. }
  2674. /**
  2675. * dsi_ctrl_isr_configure() - API to register/deregister dsi isr
  2676. * @dsi_ctrl: DSI controller handle.
  2677. * @enable: variable to control register/deregister isr
  2678. */
  2679. void dsi_ctrl_isr_configure(struct dsi_ctrl *dsi_ctrl, bool enable)
  2680. {
  2681. if (!dsi_ctrl)
  2682. return;
  2683. mutex_lock(&dsi_ctrl->ctrl_lock);
  2684. if (enable)
  2685. _dsi_ctrl_setup_isr(dsi_ctrl);
  2686. else
  2687. _dsi_ctrl_destroy_isr(dsi_ctrl);
  2688. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2689. }
  2690. void dsi_ctrl_hs_req_sel(struct dsi_ctrl *dsi_ctrl, bool sel_phy)
  2691. {
  2692. if (!dsi_ctrl)
  2693. return;
  2694. mutex_lock(&dsi_ctrl->ctrl_lock);
  2695. dsi_ctrl->hw.ops.hs_req_sel(&dsi_ctrl->hw, sel_phy);
  2696. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2697. }
  2698. void dsi_ctrl_set_continuous_clk(struct dsi_ctrl *dsi_ctrl, bool enable)
  2699. {
  2700. if (!dsi_ctrl)
  2701. return;
  2702. mutex_lock(&dsi_ctrl->ctrl_lock);
  2703. dsi_ctrl->hw.ops.set_continuous_clk(&dsi_ctrl->hw, enable);
  2704. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2705. }
  2706. int dsi_ctrl_soft_reset(struct dsi_ctrl *dsi_ctrl)
  2707. {
  2708. if (!dsi_ctrl)
  2709. return -EINVAL;
  2710. mutex_lock(&dsi_ctrl->ctrl_lock);
  2711. dsi_ctrl->hw.ops.soft_reset(&dsi_ctrl->hw);
  2712. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2713. DSI_CTRL_DEBUG(dsi_ctrl, "Soft reset complete\n");
  2714. return 0;
  2715. }
  2716. int dsi_ctrl_reset(struct dsi_ctrl *dsi_ctrl, int mask)
  2717. {
  2718. int rc = 0;
  2719. if (!dsi_ctrl)
  2720. return -EINVAL;
  2721. mutex_lock(&dsi_ctrl->ctrl_lock);
  2722. rc = dsi_ctrl->hw.ops.ctrl_reset(&dsi_ctrl->hw, mask);
  2723. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2724. return rc;
  2725. }
  2726. int dsi_ctrl_get_hw_version(struct dsi_ctrl *dsi_ctrl)
  2727. {
  2728. int rc = 0;
  2729. if (!dsi_ctrl)
  2730. return -EINVAL;
  2731. mutex_lock(&dsi_ctrl->ctrl_lock);
  2732. rc = dsi_ctrl->hw.ops.get_hw_version(&dsi_ctrl->hw);
  2733. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2734. return rc;
  2735. }
  2736. int dsi_ctrl_vid_engine_en(struct dsi_ctrl *dsi_ctrl, bool on)
  2737. {
  2738. int rc = 0;
  2739. if (!dsi_ctrl)
  2740. return -EINVAL;
  2741. mutex_lock(&dsi_ctrl->ctrl_lock);
  2742. dsi_ctrl->hw.ops.video_engine_en(&dsi_ctrl->hw, on);
  2743. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2744. return rc;
  2745. }
  2746. int dsi_ctrl_setup_avr(struct dsi_ctrl *dsi_ctrl, bool enable)
  2747. {
  2748. if (!dsi_ctrl)
  2749. return -EINVAL;
  2750. if (dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE) {
  2751. mutex_lock(&dsi_ctrl->ctrl_lock);
  2752. dsi_ctrl->hw.ops.setup_avr(&dsi_ctrl->hw, enable);
  2753. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2754. }
  2755. return 0;
  2756. }
  2757. /**
  2758. * dsi_ctrl_host_deinit() - De-Initialize DSI host hardware.
  2759. * @dsi_ctrl: DSI controller handle.
  2760. *
  2761. * De-initializes DSI controller hardware. It can be performed only during
  2762. * DSI_CTRL_POWER_CORE_CLK_ON state after LINK clocks have been turned off.
  2763. *
  2764. * Return: error code.
  2765. */
  2766. int dsi_ctrl_host_deinit(struct dsi_ctrl *dsi_ctrl)
  2767. {
  2768. int rc = 0;
  2769. if (!dsi_ctrl) {
  2770. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2771. return -EINVAL;
  2772. }
  2773. mutex_lock(&dsi_ctrl->ctrl_lock);
  2774. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_HOST_INIT, 0x0);
  2775. if (rc) {
  2776. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  2777. rc);
  2778. DSI_CTRL_ERR(dsi_ctrl, "driver state check failed, rc=%d\n",
  2779. rc);
  2780. goto error;
  2781. }
  2782. DSI_CTRL_DEBUG(dsi_ctrl, "Host deinitization complete\n");
  2783. dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_HOST_INIT, 0x0);
  2784. error:
  2785. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2786. return rc;
  2787. }
  2788. /**
  2789. * dsi_ctrl_update_host_config() - update dsi host configuration
  2790. * @dsi_ctrl: DSI controller handle.
  2791. * @config: DSI host configuration.
  2792. * @flags: dsi_mode_flags modifying the behavior
  2793. *
  2794. * Updates driver with new Host configuration to use for host initialization.
  2795. * This function call will only update the software context. The stored
  2796. * configuration information will be used when the host is initialized.
  2797. *
  2798. * Return: error code.
  2799. */
  2800. int dsi_ctrl_update_host_config(struct dsi_ctrl *ctrl,
  2801. struct dsi_host_config *config,
  2802. struct dsi_display_mode *mode, int flags,
  2803. void *clk_handle)
  2804. {
  2805. int rc = 0;
  2806. if (!ctrl || !config) {
  2807. DSI_CTRL_ERR(ctrl, "Invalid params\n");
  2808. return -EINVAL;
  2809. }
  2810. mutex_lock(&ctrl->ctrl_lock);
  2811. rc = dsi_ctrl_validate_panel_info(ctrl, config);
  2812. if (rc) {
  2813. DSI_CTRL_ERR(ctrl, "panel validation failed, rc=%d\n", rc);
  2814. goto error;
  2815. }
  2816. if (!(flags & (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  2817. DSI_MODE_FLAG_DYN_CLK))) {
  2818. /*
  2819. * for dynamic clk switch case link frequence would
  2820. * be updated dsi_display_dynamic_clk_switch().
  2821. */
  2822. rc = dsi_ctrl_update_link_freqs(ctrl, config, clk_handle,
  2823. mode);
  2824. if (rc) {
  2825. DSI_CTRL_ERR(ctrl, "failed to update link frequency, rc=%d\n",
  2826. rc);
  2827. goto error;
  2828. }
  2829. }
  2830. DSI_CTRL_DEBUG(ctrl, "Host config updated\n");
  2831. memcpy(&ctrl->host_config, config, sizeof(ctrl->host_config));
  2832. ctrl->mode_bounds.x = ctrl->host_config.video_timing.h_active *
  2833. ctrl->horiz_index;
  2834. ctrl->mode_bounds.y = 0;
  2835. ctrl->mode_bounds.w = ctrl->host_config.video_timing.h_active;
  2836. ctrl->mode_bounds.h = ctrl->host_config.video_timing.v_active;
  2837. memcpy(&ctrl->roi, &ctrl->mode_bounds, sizeof(ctrl->mode_bounds));
  2838. ctrl->modeupdated = true;
  2839. ctrl->roi.x = 0;
  2840. error:
  2841. mutex_unlock(&ctrl->ctrl_lock);
  2842. return rc;
  2843. }
  2844. /**
  2845. * dsi_ctrl_validate_timing() - validate a video timing configuration
  2846. * @dsi_ctrl: DSI controller handle.
  2847. * @timing: Pointer to timing data.
  2848. *
  2849. * Driver will validate if the timing configuration is supported on the
  2850. * controller hardware.
  2851. *
  2852. * Return: error code if timing is not supported.
  2853. */
  2854. int dsi_ctrl_validate_timing(struct dsi_ctrl *dsi_ctrl,
  2855. struct dsi_mode_info *mode)
  2856. {
  2857. int rc = 0;
  2858. if (!dsi_ctrl || !mode) {
  2859. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2860. return -EINVAL;
  2861. }
  2862. return rc;
  2863. }
  2864. /**
  2865. * dsi_ctrl_transfer_prepare() - Set up a command transfer
  2866. * @dsi_ctrl: DSI controller handle.
  2867. * @flags: Controller flags of the command.
  2868. *
  2869. * Command transfer requires command engine to be enabled, along with
  2870. * clock votes and masking the overflow bits.
  2871. *
  2872. * Return: error code.
  2873. */
  2874. int dsi_ctrl_transfer_prepare(struct dsi_ctrl *dsi_ctrl, u32 flags)
  2875. {
  2876. int rc = 0;
  2877. struct dsi_clk_ctrl_info clk_info;
  2878. u32 mask = BIT(DSI_FIFO_OVERFLOW);
  2879. if (!dsi_ctrl)
  2880. return -EINVAL;
  2881. if (!(flags & DSI_CTRL_CMD_LAST_COMMAND))
  2882. return rc;
  2883. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, dsi_ctrl->cell_index, flags);
  2884. /* Vote for clocks, gdsc, enable command engine, mask overflow */
  2885. rc = pm_runtime_get_sync(dsi_ctrl->drm_dev->dev);
  2886. if (rc < 0) {
  2887. DSI_CTRL_ERR(dsi_ctrl, "failed gdsc voting\n");
  2888. return rc;
  2889. }
  2890. clk_info.client = DSI_CLK_REQ_DSI_CLIENT;
  2891. clk_info.clk_type = DSI_ALL_CLKS;
  2892. clk_info.clk_state = DSI_CLK_ON;
  2893. rc = dsi_ctrl->clk_cb.dsi_clk_cb(dsi_ctrl->clk_cb.priv, clk_info);
  2894. if (rc) {
  2895. DSI_CTRL_ERR(dsi_ctrl, "failed to enable clocks\n");
  2896. goto error_disable_gdsc;
  2897. }
  2898. /* Wait till any previous ASYNC waits are scheduled and completed */
  2899. if (dsi_ctrl->post_tx_queued)
  2900. dsi_ctrl_flush_cmd_dma_queue(dsi_ctrl);
  2901. mutex_lock(&dsi_ctrl->ctrl_lock);
  2902. if (flags & DSI_CTRL_CMD_READ)
  2903. mask |= BIT(DSI_FIFO_UNDERFLOW);
  2904. dsi_ctrl_mask_error_status_interrupts(dsi_ctrl, mask, true);
  2905. rc = dsi_ctrl_set_cmd_engine_state(dsi_ctrl, DSI_CTRL_ENGINE_ON, false);
  2906. if (rc) {
  2907. DSI_CTRL_ERR(dsi_ctrl, "failed to enable command engine: %d\n", rc);
  2908. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2909. goto error_disable_clks;
  2910. }
  2911. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2912. return rc;
  2913. error_disable_clks:
  2914. clk_info.clk_state = DSI_CLK_OFF;
  2915. (void)dsi_ctrl->clk_cb.dsi_clk_cb(dsi_ctrl->clk_cb.priv, clk_info);
  2916. error_disable_gdsc:
  2917. (void)pm_runtime_put_sync(dsi_ctrl->drm_dev->dev);
  2918. return rc;
  2919. }
  2920. /**
  2921. * dsi_ctrl_cmd_transfer() - Transfer commands on DSI link
  2922. * @dsi_ctrl: DSI controller handle.
  2923. * @cmd: Command description to transfer on DSI link.
  2924. *
  2925. * Command transfer can be done only when command engine is enabled. The
  2926. * transfer API will block until either the command transfer finishes or
  2927. * the timeout value is reached. If the trigger is deferred, it will return
  2928. * without triggering the transfer. Command parameters are programmed to
  2929. * hardware.
  2930. *
  2931. * Return: error code.
  2932. */
  2933. int dsi_ctrl_cmd_transfer(struct dsi_ctrl *dsi_ctrl, struct dsi_cmd_desc *cmd)
  2934. {
  2935. int rc = 0;
  2936. if (!dsi_ctrl || !cmd) {
  2937. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2938. return -EINVAL;
  2939. }
  2940. mutex_lock(&dsi_ctrl->ctrl_lock);
  2941. if (cmd->ctrl_flags & DSI_CTRL_CMD_READ) {
  2942. rc = dsi_message_rx(dsi_ctrl, cmd);
  2943. if (rc <= 0)
  2944. DSI_CTRL_ERR(dsi_ctrl, "read message failed read length, rc=%d\n",
  2945. rc);
  2946. } else {
  2947. rc = dsi_message_tx(dsi_ctrl, cmd);
  2948. if (rc)
  2949. DSI_CTRL_ERR(dsi_ctrl, "command msg transfer failed, rc = %d\n",
  2950. rc);
  2951. }
  2952. dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_CMD_TX, 0x0);
  2953. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2954. return rc;
  2955. }
  2956. /**
  2957. * dsi_ctrl_transfer_unprepare() - Clean up post a command transfer
  2958. * @dsi_ctrl: DSI controller handle.
  2959. * @flags: Controller flags of the command
  2960. *
  2961. * After the DSI controller has been programmed to trigger a DCS command
  2962. * the post transfer API is used to check for success and clean up the
  2963. * resources. Depending on the controller flags, this check is either
  2964. * scheduled on the same thread or queued.
  2965. *
  2966. */
  2967. void dsi_ctrl_transfer_unprepare(struct dsi_ctrl *dsi_ctrl, u32 flags)
  2968. {
  2969. if (!dsi_ctrl)
  2970. return;
  2971. if (!(flags & DSI_CTRL_CMD_LAST_COMMAND))
  2972. return;
  2973. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, dsi_ctrl->cell_index, flags);
  2974. dsi_ctrl->pending_cmd_flags = flags;
  2975. if (flags & DSI_CTRL_CMD_ASYNC_WAIT) {
  2976. dsi_ctrl->post_tx_queued = true;
  2977. queue_work(dsi_ctrl->post_cmd_tx_workq, &dsi_ctrl->post_cmd_tx_work);
  2978. } else {
  2979. dsi_ctrl->post_tx_queued = false;
  2980. dsi_ctrl_post_cmd_transfer(dsi_ctrl);
  2981. }
  2982. }
  2983. /**
  2984. * dsi_ctrl_cmd_tx_trigger() - Trigger a deferred command.
  2985. * @dsi_ctrl: DSI controller handle.
  2986. * @flags: Modifiers.
  2987. *
  2988. * Return: error code.
  2989. */
  2990. int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags)
  2991. {
  2992. int rc = 0;
  2993. struct dsi_ctrl_hw_ops dsi_hw_ops;
  2994. u32 v_total = 0, fps = 0, cur_line = 0, mem_latency_us = 100;
  2995. u32 line_time = 0, schedule_line = 0x1, latency_by_line = 0;
  2996. struct dsi_mode_info *timing;
  2997. unsigned long flag;
  2998. if (!dsi_ctrl) {
  2999. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  3000. return -EINVAL;
  3001. }
  3002. dsi_hw_ops = dsi_ctrl->hw.ops;
  3003. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY, flags);
  3004. /* Dont trigger the command if this is not the last ocmmand */
  3005. if (!(flags & DSI_CTRL_CMD_LAST_COMMAND))
  3006. return rc;
  3007. mutex_lock(&dsi_ctrl->ctrl_lock);
  3008. timing = &(dsi_ctrl->host_config.video_timing);
  3009. if (timing &&
  3010. (dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE)) {
  3011. v_total = timing->v_sync_width + timing->v_back_porch +
  3012. timing->v_front_porch + timing->v_active;
  3013. fps = timing->refresh_rate;
  3014. schedule_line = calculate_schedule_line(dsi_ctrl, flags);
  3015. line_time = (1000000 / fps) / v_total;
  3016. latency_by_line = CEIL(mem_latency_us, line_time);
  3017. }
  3018. if (!(flags & DSI_CTRL_CMD_BROADCAST_MASTER)) {
  3019. dsi_hw_ops.trigger_command_dma(&dsi_ctrl->hw);
  3020. if (dsi_ctrl->enable_cmd_dma_stats) {
  3021. u32 reg = dsi_hw_ops.log_line_count(&dsi_ctrl->hw,
  3022. dsi_ctrl->cmd_mode);
  3023. dsi_ctrl->cmd_trigger_line = (reg & 0xFFFF);
  3024. dsi_ctrl->cmd_trigger_frame = ((reg >> 16) & 0xFFFF);
  3025. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_CASE1,
  3026. dsi_ctrl->cmd_trigger_line,
  3027. dsi_ctrl->cmd_trigger_frame);
  3028. }
  3029. }
  3030. if ((flags & DSI_CTRL_CMD_BROADCAST) &&
  3031. (flags & DSI_CTRL_CMD_BROADCAST_MASTER)) {
  3032. dsi_ctrl_wait_for_video_done(dsi_ctrl);
  3033. atomic_set(&dsi_ctrl->dma_irq_trig, 0);
  3034. dsi_ctrl_enable_status_interrupt(dsi_ctrl,
  3035. DSI_SINT_CMD_MODE_DMA_DONE, NULL);
  3036. reinit_completion(&dsi_ctrl->irq_info.cmd_dma_done);
  3037. /* trigger command */
  3038. if ((dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE) &&
  3039. dsi_hw_ops.schedule_dma_cmd &&
  3040. (dsi_ctrl->current_state.vid_engine_state ==
  3041. DSI_CTRL_ENGINE_ON)) {
  3042. /*
  3043. * This change reads the video line count from
  3044. * MDP_INTF_LINE_COUNT register and checks whether
  3045. * DMA trigger happens close to the schedule line.
  3046. * If it is not close to the schedule line, then DMA
  3047. * command transfer is triggered.
  3048. */
  3049. while (1) {
  3050. local_irq_save(flag);
  3051. cur_line =
  3052. dsi_hw_ops.log_line_count(&dsi_ctrl->hw,
  3053. dsi_ctrl->cmd_mode);
  3054. if (cur_line <
  3055. (schedule_line - latency_by_line) ||
  3056. cur_line > (schedule_line + 1)) {
  3057. dsi_hw_ops.trigger_command_dma(
  3058. &dsi_ctrl->hw);
  3059. local_irq_restore(flag);
  3060. break;
  3061. }
  3062. local_irq_restore(flag);
  3063. udelay(1000);
  3064. }
  3065. } else
  3066. dsi_hw_ops.trigger_command_dma(&dsi_ctrl->hw);
  3067. if (dsi_ctrl->enable_cmd_dma_stats) {
  3068. u32 reg = dsi_hw_ops.log_line_count(&dsi_ctrl->hw,
  3069. dsi_ctrl->cmd_mode);
  3070. dsi_ctrl->cmd_trigger_line = (reg & 0xFFFF);
  3071. dsi_ctrl->cmd_trigger_frame = ((reg >> 16) & 0xFFFF);
  3072. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_CASE1,
  3073. dsi_ctrl->cmd_trigger_line,
  3074. dsi_ctrl->cmd_trigger_frame);
  3075. }
  3076. if (flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) {
  3077. if (dsi_ctrl->version < DSI_CTRL_VERSION_2_4)
  3078. dsi_hw_ops.soft_reset(&dsi_ctrl->hw);
  3079. dsi_ctrl->cmd_len = 0;
  3080. }
  3081. }
  3082. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3083. return rc;
  3084. }
  3085. /**
  3086. * dsi_ctrl_cache_misr - Cache frame MISR value
  3087. * @dsi_ctrl: Pointer to associated dsi_ctrl structure
  3088. */
  3089. void dsi_ctrl_cache_misr(struct dsi_ctrl *dsi_ctrl)
  3090. {
  3091. u32 misr;
  3092. if (!dsi_ctrl || !dsi_ctrl->hw.ops.collect_misr)
  3093. return;
  3094. misr = dsi_ctrl->hw.ops.collect_misr(&dsi_ctrl->hw,
  3095. dsi_ctrl->host_config.panel_mode);
  3096. if (misr)
  3097. dsi_ctrl->misr_cache = misr;
  3098. DSI_CTRL_DEBUG(dsi_ctrl, "misr_cache = %x\n", dsi_ctrl->misr_cache);
  3099. }
  3100. /**
  3101. * dsi_ctrl_get_host_engine_init_state() - Return host init state
  3102. * @dsi_ctrl: DSI controller handle.
  3103. * @state: Controller initialization state
  3104. *
  3105. * Return: error code.
  3106. */
  3107. int dsi_ctrl_get_host_engine_init_state(struct dsi_ctrl *dsi_ctrl,
  3108. bool *state)
  3109. {
  3110. if (!dsi_ctrl || !state) {
  3111. DSI_CTRL_ERR(dsi_ctrl, "Invalid Params\n");
  3112. return -EINVAL;
  3113. }
  3114. mutex_lock(&dsi_ctrl->ctrl_lock);
  3115. *state = dsi_ctrl->current_state.host_initialized;
  3116. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3117. return 0;
  3118. }
  3119. /**
  3120. * dsi_ctrl_set_power_state() - set power state for dsi controller
  3121. * @dsi_ctrl: DSI controller handle.
  3122. * @state: Power state.
  3123. *
  3124. * Set power state for DSI controller. Power state can be changed only when
  3125. * Controller, Video and Command engines are turned off.
  3126. *
  3127. * Return: error code.
  3128. */
  3129. int dsi_ctrl_set_power_state(struct dsi_ctrl *dsi_ctrl,
  3130. enum dsi_power_state state)
  3131. {
  3132. int rc = 0;
  3133. if (!dsi_ctrl || (state >= DSI_CTRL_POWER_MAX)) {
  3134. DSI_CTRL_ERR(dsi_ctrl, "Invalid Params\n");
  3135. return -EINVAL;
  3136. }
  3137. mutex_lock(&dsi_ctrl->ctrl_lock);
  3138. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_POWER_STATE_CHANGE,
  3139. state);
  3140. if (rc) {
  3141. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  3142. rc);
  3143. goto error;
  3144. }
  3145. if (state == DSI_CTRL_POWER_VREG_ON) {
  3146. rc = dsi_ctrl_enable_supplies(dsi_ctrl, true);
  3147. if (rc) {
  3148. DSI_CTRL_ERR(dsi_ctrl, "failed to enable voltage supplies, rc=%d\n",
  3149. rc);
  3150. goto error;
  3151. }
  3152. } else if (state == DSI_CTRL_POWER_VREG_OFF) {
  3153. rc = dsi_ctrl_enable_supplies(dsi_ctrl, false);
  3154. if (rc) {
  3155. DSI_CTRL_ERR(dsi_ctrl, "failed to disable vreg supplies, rc=%d\n",
  3156. rc);
  3157. goto error;
  3158. }
  3159. }
  3160. DSI_CTRL_DEBUG(dsi_ctrl, "Power state updated to %d\n", state);
  3161. dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_POWER_STATE_CHANGE, state);
  3162. error:
  3163. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3164. return rc;
  3165. }
  3166. /**
  3167. * dsi_ctrl_set_tpg_state() - enable/disable test pattern on the controller
  3168. * @dsi_ctrl: DSI controller handle.
  3169. * @on: enable/disable test pattern.
  3170. *
  3171. * Test pattern can be enabled only after Video engine (for video mode panels)
  3172. * or command engine (for cmd mode panels) is enabled.
  3173. *
  3174. * Return: error code.
  3175. */
  3176. int dsi_ctrl_set_tpg_state(struct dsi_ctrl *dsi_ctrl, bool on)
  3177. {
  3178. int rc = 0;
  3179. if (!dsi_ctrl) {
  3180. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  3181. return -EINVAL;
  3182. }
  3183. mutex_lock(&dsi_ctrl->ctrl_lock);
  3184. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_TPG, on);
  3185. if (rc) {
  3186. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  3187. rc);
  3188. goto error;
  3189. }
  3190. if (on) {
  3191. if (dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE) {
  3192. dsi_ctrl->hw.ops.video_test_pattern_setup(&dsi_ctrl->hw,
  3193. DSI_TEST_PATTERN_INC,
  3194. 0xFFFF);
  3195. } else {
  3196. dsi_ctrl->hw.ops.cmd_test_pattern_setup(
  3197. &dsi_ctrl->hw,
  3198. DSI_TEST_PATTERN_INC,
  3199. 0xFFFF,
  3200. 0x0);
  3201. }
  3202. }
  3203. dsi_ctrl->hw.ops.test_pattern_enable(&dsi_ctrl->hw, on);
  3204. DSI_CTRL_DEBUG(dsi_ctrl, "Set test pattern state=%d\n", on);
  3205. dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_TPG, on);
  3206. error:
  3207. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3208. return rc;
  3209. }
  3210. /**
  3211. * dsi_ctrl_set_host_engine_state() - set host engine state
  3212. * @dsi_ctrl: DSI Controller handle.
  3213. * @state: Engine state.
  3214. * @skip_op: Boolean to indicate few operations can be skipped.
  3215. * Set during the cont-splash or trusted-vm enable case.
  3216. *
  3217. * Host engine state can be modified only when DSI controller power state is
  3218. * set to DSI_CTRL_POWER_LINK_CLK_ON and cmd, video engines are disabled.
  3219. *
  3220. * Return: error code.
  3221. */
  3222. int dsi_ctrl_set_host_engine_state(struct dsi_ctrl *dsi_ctrl,
  3223. enum dsi_engine_state state, bool skip_op)
  3224. {
  3225. int rc = 0;
  3226. if (!dsi_ctrl || (state >= DSI_CTRL_ENGINE_MAX)) {
  3227. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  3228. return -EINVAL;
  3229. }
  3230. mutex_lock(&dsi_ctrl->ctrl_lock);
  3231. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_HOST_ENGINE, state);
  3232. if (rc) {
  3233. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  3234. rc);
  3235. goto error;
  3236. }
  3237. if (!skip_op) {
  3238. if (state == DSI_CTRL_ENGINE_ON)
  3239. dsi_ctrl->hw.ops.ctrl_en(&dsi_ctrl->hw, true);
  3240. else
  3241. dsi_ctrl->hw.ops.ctrl_en(&dsi_ctrl->hw, false);
  3242. }
  3243. SDE_EVT32(dsi_ctrl->cell_index, state, skip_op);
  3244. DSI_CTRL_DEBUG(dsi_ctrl, "Set host engine state = %d\n", state);
  3245. dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_HOST_ENGINE, state);
  3246. error:
  3247. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3248. return rc;
  3249. }
  3250. /**
  3251. * dsi_ctrl_set_cmd_engine_state() - set command engine state
  3252. * @dsi_ctrl: DSI Controller handle.
  3253. * @state: Engine state.
  3254. * @skip_op: Boolean to indicate few operations can be skipped.
  3255. * Set during the cont-splash or trusted-vm enable case.
  3256. *
  3257. * Command engine state can be modified only when DSI controller power state is
  3258. * set to DSI_CTRL_POWER_LINK_CLK_ON.
  3259. *
  3260. * Return: error code.
  3261. */
  3262. int dsi_ctrl_set_cmd_engine_state(struct dsi_ctrl *dsi_ctrl,
  3263. enum dsi_engine_state state, bool skip_op)
  3264. {
  3265. int rc = 0;
  3266. if (!dsi_ctrl || (state >= DSI_CTRL_ENGINE_MAX)) {
  3267. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  3268. return -EINVAL;
  3269. }
  3270. if (state == DSI_CTRL_ENGINE_ON) {
  3271. if (dsi_ctrl->cmd_engine_refcount > 0) {
  3272. dsi_ctrl->cmd_engine_refcount++;
  3273. goto error;
  3274. }
  3275. } else {
  3276. if (dsi_ctrl->cmd_engine_refcount > 1) {
  3277. dsi_ctrl->cmd_engine_refcount--;
  3278. goto error;
  3279. }
  3280. }
  3281. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_CMD_ENGINE, state);
  3282. if (rc) {
  3283. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n", rc);
  3284. goto error;
  3285. }
  3286. if (!skip_op) {
  3287. if (state == DSI_CTRL_ENGINE_ON)
  3288. dsi_ctrl->hw.ops.cmd_engine_en(&dsi_ctrl->hw, true);
  3289. else
  3290. dsi_ctrl->hw.ops.cmd_engine_en(&dsi_ctrl->hw, false);
  3291. }
  3292. if (state == DSI_CTRL_ENGINE_ON)
  3293. dsi_ctrl->cmd_engine_refcount++;
  3294. else
  3295. dsi_ctrl->cmd_engine_refcount = 0;
  3296. SDE_EVT32(dsi_ctrl->cell_index, state, skip_op);
  3297. dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_CMD_ENGINE, state);
  3298. error:
  3299. DSI_CTRL_DEBUG(dsi_ctrl, "Set cmd engine state:%d, skip_op:%d, enable count: %d\n",
  3300. state, skip_op, dsi_ctrl->cmd_engine_refcount);
  3301. return rc;
  3302. }
  3303. /**
  3304. * dsi_ctrl_set_vid_engine_state() - set video engine state
  3305. * @dsi_ctrl: DSI Controller handle.
  3306. * @state: Engine state.
  3307. * @skip_op: Boolean to indicate few operations can be skipped.
  3308. * Set during the cont-splash or trusted-vm enable case.
  3309. *
  3310. * Video engine state can be modified only when DSI controller power state is
  3311. * set to DSI_CTRL_POWER_LINK_CLK_ON.
  3312. *
  3313. * Return: error code.
  3314. */
  3315. int dsi_ctrl_set_vid_engine_state(struct dsi_ctrl *dsi_ctrl,
  3316. enum dsi_engine_state state, bool skip_op)
  3317. {
  3318. int rc = 0;
  3319. bool on;
  3320. bool vid_eng_busy;
  3321. if (!dsi_ctrl || (state >= DSI_CTRL_ENGINE_MAX)) {
  3322. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  3323. return -EINVAL;
  3324. }
  3325. mutex_lock(&dsi_ctrl->ctrl_lock);
  3326. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_VID_ENGINE, state);
  3327. if (rc) {
  3328. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  3329. rc);
  3330. goto error;
  3331. }
  3332. if (!skip_op) {
  3333. on = (state == DSI_CTRL_ENGINE_ON) ? true : false;
  3334. dsi_ctrl->hw.ops.video_engine_en(&dsi_ctrl->hw, on);
  3335. vid_eng_busy = dsi_ctrl->hw.ops.vid_engine_busy(&dsi_ctrl->hw);
  3336. /*
  3337. * During ESD check failure, DSI video engine can get stuck
  3338. * sending data from display engine. In use cases where GDSC
  3339. * toggle does not happen like DP MST connected or secure video
  3340. * playback, display does not recover back after ESD failure.
  3341. * Perform a reset if video engine is stuck.
  3342. */
  3343. if (!on && (dsi_ctrl->version < DSI_CTRL_VERSION_1_3 ||
  3344. vid_eng_busy))
  3345. dsi_ctrl->hw.ops.soft_reset(&dsi_ctrl->hw);
  3346. }
  3347. SDE_EVT32(dsi_ctrl->cell_index, state, skip_op);
  3348. DSI_CTRL_DEBUG(dsi_ctrl, "Set video engine state:%d, skip_op:%d\n",
  3349. state, skip_op);
  3350. dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_VID_ENGINE, state);
  3351. error:
  3352. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3353. return rc;
  3354. }
  3355. /**
  3356. * dsi_ctrl_set_ulps() - set ULPS state for DSI lanes.
  3357. * @dsi_ctrl: DSI controller handle.
  3358. * @enable: enable/disable ULPS.
  3359. *
  3360. * ULPS can be enabled/disabled after DSI host engine is turned on.
  3361. *
  3362. * Return: error code.
  3363. */
  3364. int dsi_ctrl_set_ulps(struct dsi_ctrl *dsi_ctrl, bool enable)
  3365. {
  3366. int rc = 0;
  3367. if (!dsi_ctrl) {
  3368. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  3369. return -EINVAL;
  3370. }
  3371. mutex_lock(&dsi_ctrl->ctrl_lock);
  3372. if (enable)
  3373. rc = dsi_enable_ulps(dsi_ctrl);
  3374. else
  3375. rc = dsi_disable_ulps(dsi_ctrl);
  3376. if (rc) {
  3377. DSI_CTRL_ERR(dsi_ctrl, "Ulps state change(%d) failed, rc=%d\n",
  3378. enable, rc);
  3379. goto error;
  3380. }
  3381. DSI_CTRL_DEBUG(dsi_ctrl, "ULPS state = %d\n", enable);
  3382. error:
  3383. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3384. return rc;
  3385. }
  3386. /**
  3387. * dsi_ctrl_set_clamp_state() - set clamp state for DSI phy
  3388. * @dsi_ctrl: DSI controller handle.
  3389. * @enable: enable/disable clamping.
  3390. *
  3391. * Clamps can be enabled/disabled while DSI controller is still turned on.
  3392. *
  3393. * Return: error code.
  3394. */
  3395. int dsi_ctrl_set_clamp_state(struct dsi_ctrl *dsi_ctrl,
  3396. bool enable, bool ulps_enabled)
  3397. {
  3398. int rc = 0;
  3399. if (!dsi_ctrl) {
  3400. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  3401. return -EINVAL;
  3402. }
  3403. if (!dsi_ctrl->hw.ops.clamp_enable ||
  3404. !dsi_ctrl->hw.ops.clamp_disable) {
  3405. DSI_CTRL_DEBUG(dsi_ctrl, "No clamp control for DSI controller\n");
  3406. return 0;
  3407. }
  3408. mutex_lock(&dsi_ctrl->ctrl_lock);
  3409. rc = dsi_enable_io_clamp(dsi_ctrl, enable, ulps_enabled);
  3410. if (rc) {
  3411. DSI_CTRL_ERR(dsi_ctrl, "Failed to enable IO clamp\n");
  3412. goto error;
  3413. }
  3414. DSI_CTRL_DEBUG(dsi_ctrl, "Clamp state = %d\n", enable);
  3415. error:
  3416. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3417. return rc;
  3418. }
  3419. /**
  3420. * dsi_ctrl_set_clock_source() - set clock source fpr dsi link clocks
  3421. * @dsi_ctrl: DSI controller handle.
  3422. * @source_clks: Source clocks for DSI link clocks.
  3423. *
  3424. * Clock source should be changed while link clocks are disabled.
  3425. *
  3426. * Return: error code.
  3427. */
  3428. int dsi_ctrl_set_clock_source(struct dsi_ctrl *dsi_ctrl,
  3429. struct dsi_clk_link_set *source_clks)
  3430. {
  3431. int rc = 0;
  3432. if (!dsi_ctrl || !source_clks) {
  3433. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  3434. return -EINVAL;
  3435. }
  3436. mutex_lock(&dsi_ctrl->ctrl_lock);
  3437. rc = dsi_clk_update_parent(source_clks, &dsi_ctrl->clk_info.rcg_clks);
  3438. if (rc) {
  3439. DSI_CTRL_ERR(dsi_ctrl, "Failed to update link clk parent, rc=%d\n",
  3440. rc);
  3441. (void)dsi_clk_update_parent(&dsi_ctrl->clk_info.pll_op_clks,
  3442. &dsi_ctrl->clk_info.rcg_clks);
  3443. goto error;
  3444. }
  3445. dsi_ctrl->clk_info.pll_op_clks.byte_clk = source_clks->byte_clk;
  3446. dsi_ctrl->clk_info.pll_op_clks.pixel_clk = source_clks->pixel_clk;
  3447. DSI_CTRL_DEBUG(dsi_ctrl, "Source clocks are updated\n");
  3448. error:
  3449. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3450. return rc;
  3451. }
  3452. /**
  3453. * dsi_ctrl_setup_misr() - Setup frame MISR
  3454. * @dsi_ctrl: DSI controller handle.
  3455. * @enable: enable/disable MISR.
  3456. * @frame_count: Number of frames to accumulate MISR.
  3457. *
  3458. * Return: error code.
  3459. */
  3460. int dsi_ctrl_setup_misr(struct dsi_ctrl *dsi_ctrl,
  3461. bool enable,
  3462. u32 frame_count)
  3463. {
  3464. if (!dsi_ctrl) {
  3465. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  3466. return -EINVAL;
  3467. }
  3468. if (!dsi_ctrl->hw.ops.setup_misr)
  3469. return 0;
  3470. mutex_lock(&dsi_ctrl->ctrl_lock);
  3471. dsi_ctrl->misr_enable = enable;
  3472. dsi_ctrl->hw.ops.setup_misr(&dsi_ctrl->hw,
  3473. dsi_ctrl->host_config.panel_mode,
  3474. enable, frame_count);
  3475. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3476. return 0;
  3477. }
  3478. /**
  3479. * dsi_ctrl_collect_misr() - Read frame MISR
  3480. * @dsi_ctrl: DSI controller handle.
  3481. *
  3482. * Return: MISR value.
  3483. */
  3484. u32 dsi_ctrl_collect_misr(struct dsi_ctrl *dsi_ctrl)
  3485. {
  3486. u32 misr;
  3487. if (!dsi_ctrl || !dsi_ctrl->hw.ops.collect_misr)
  3488. return 0;
  3489. misr = dsi_ctrl->hw.ops.collect_misr(&dsi_ctrl->hw,
  3490. dsi_ctrl->host_config.panel_mode);
  3491. if (!misr)
  3492. misr = dsi_ctrl->misr_cache;
  3493. DSI_CTRL_DEBUG(dsi_ctrl, "cached misr = %x, final = %x\n",
  3494. dsi_ctrl->misr_cache, misr);
  3495. return misr;
  3496. }
  3497. void dsi_ctrl_mask_error_status_interrupts(struct dsi_ctrl *dsi_ctrl, u32 idx,
  3498. bool mask_enable)
  3499. {
  3500. if (!dsi_ctrl || !dsi_ctrl->hw.ops.error_intr_ctrl
  3501. || !dsi_ctrl->hw.ops.clear_error_status) {
  3502. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  3503. return;
  3504. }
  3505. /*
  3506. * Mask DSI error status interrupts and clear error status
  3507. * register
  3508. */
  3509. if (idx & BIT(DSI_ERR_INTR_ALL)) {
  3510. /*
  3511. * The behavior of mask_enable is different in ctrl register
  3512. * and mask register and hence mask_enable is manipulated for
  3513. * selective error interrupt masking vs total error interrupt
  3514. * masking.
  3515. */
  3516. dsi_ctrl->hw.ops.error_intr_ctrl(&dsi_ctrl->hw, !mask_enable);
  3517. dsi_ctrl->hw.ops.clear_error_status(&dsi_ctrl->hw,
  3518. DSI_ERROR_INTERRUPT_COUNT);
  3519. } else {
  3520. dsi_ctrl->hw.ops.mask_error_intr(&dsi_ctrl->hw, idx,
  3521. mask_enable);
  3522. dsi_ctrl->hw.ops.clear_error_status(&dsi_ctrl->hw,
  3523. DSI_ERROR_INTERRUPT_COUNT);
  3524. }
  3525. }
  3526. /**
  3527. * dsi_ctrl_irq_update() - Put a irq vote to process DSI error
  3528. * interrupts at any time.
  3529. * @dsi_ctrl: DSI controller handle.
  3530. * @enable: variable to enable/disable irq
  3531. */
  3532. void dsi_ctrl_irq_update(struct dsi_ctrl *dsi_ctrl, bool enable)
  3533. {
  3534. if (!dsi_ctrl)
  3535. return;
  3536. mutex_lock(&dsi_ctrl->ctrl_lock);
  3537. if (enable)
  3538. dsi_ctrl_enable_status_interrupt(dsi_ctrl,
  3539. DSI_SINT_ERROR, NULL);
  3540. else
  3541. dsi_ctrl_disable_status_interrupt(dsi_ctrl,
  3542. DSI_SINT_ERROR);
  3543. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3544. }
  3545. /**
  3546. * dsi_ctrl_wait4dynamic_refresh_done() - Poll for dynamci refresh
  3547. * done interrupt.
  3548. * @dsi_ctrl: DSI controller handle.
  3549. */
  3550. int dsi_ctrl_wait4dynamic_refresh_done(struct dsi_ctrl *ctrl)
  3551. {
  3552. int rc = 0;
  3553. if (!ctrl)
  3554. return 0;
  3555. mutex_lock(&ctrl->ctrl_lock);
  3556. if (ctrl->hw.ops.wait4dynamic_refresh_done)
  3557. rc = ctrl->hw.ops.wait4dynamic_refresh_done(&ctrl->hw);
  3558. mutex_unlock(&ctrl->ctrl_lock);
  3559. return rc;
  3560. }
  3561. /**
  3562. * dsi_ctrl_drv_register() - register platform driver for dsi controller
  3563. */
  3564. void dsi_ctrl_drv_register(void)
  3565. {
  3566. platform_driver_register(&dsi_ctrl_driver);
  3567. }
  3568. /**
  3569. * dsi_ctrl_drv_unregister() - unregister platform driver
  3570. */
  3571. void dsi_ctrl_drv_unregister(void)
  3572. {
  3573. platform_driver_unregister(&dsi_ctrl_driver);
  3574. }