sde_plane.c 140 KB

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  1. /*
  2. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  3. * Copyright (C) 2014-2021 The Linux Foundation. All rights reserved.
  4. * Copyright (C) 2013 Red Hat
  5. * Author: Rob Clark <[email protected]>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  20. #include <linux/debugfs.h>
  21. #include <linux/dma-buf.h>
  22. #include <drm/sde_drm.h>
  23. #include <drm/msm_drm_pp.h>
  24. #include <linux/version.h>
  25. #include "msm_prop.h"
  26. #include "msm_drv.h"
  27. #include "sde_kms.h"
  28. #include "sde_fence.h"
  29. #include "sde_formats.h"
  30. #include "sde_hw_sspp.h"
  31. #include "sde_hw_catalog_format.h"
  32. #include "sde_trace.h"
  33. #include "sde_crtc.h"
  34. #include "sde_vbif.h"
  35. #include "sde_plane.h"
  36. #include "sde_color_processing.h"
  37. #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
  38. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  39. #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
  40. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  41. #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
  42. #define PHASE_STEP_SHIFT 21
  43. #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
  44. #define PHASE_RESIDUAL 15
  45. #define SHARP_STRENGTH_DEFAULT 32
  46. #define SHARP_EDGE_THR_DEFAULT 112
  47. #define SHARP_SMOOTH_THR_DEFAULT 8
  48. #define SHARP_NOISE_THR_DEFAULT 2
  49. #define SDE_NAME_SIZE 12
  50. #define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
  51. #define TIME_MULTIPLEX_RECT(r0, r1, buffer_lines) \
  52. ((r0).y >= ((r1).y + (r1).h + buffer_lines))
  53. #define SDE_QSEED_DEFAULT_DYN_EXP 0x0
  54. /**
  55. * enum sde_plane_qos - Different qos configurations for each pipe
  56. *
  57. * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
  58. * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
  59. * this configuration is mutually exclusive from VBLANK_CTRL.
  60. * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
  61. */
  62. enum sde_plane_qos {
  63. SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
  64. SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
  65. SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
  66. };
  67. struct sde_plane {
  68. struct drm_plane base;
  69. struct mutex lock;
  70. enum sde_sspp pipe;
  71. uint64_t features; /* capabilities from catalog */
  72. uint32_t perf_features; /* perf capabilities from catalog */
  73. uint32_t nformats;
  74. uint32_t formats[64];
  75. struct sde_hw_pipe *pipe_hw;
  76. struct sde_hw_pipe_cfg pipe_cfg;
  77. struct sde_hw_sharp_cfg sharp_cfg;
  78. struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
  79. uint32_t color_fill;
  80. bool is_error;
  81. bool is_rt_pipe;
  82. enum sde_wb_usage_type wb_usage_type;
  83. bool is_virtual;
  84. struct list_head mplane_list;
  85. struct sde_mdss_cfg *catalog;
  86. bool revalidate;
  87. bool xin_halt_forced_clk;
  88. struct sde_csc_cfg csc_cfg;
  89. struct sde_csc_cfg *csc_usr_ptr;
  90. struct sde_csc_cfg *csc_ptr;
  91. uint32_t cached_lut_flag;
  92. struct sde_hw_scaler3_cfg scaler3_cfg;
  93. struct sde_hw_pixel_ext pixel_ext;
  94. const struct sde_sspp_sub_blks *pipe_sblk;
  95. char pipe_name[SDE_NAME_SIZE];
  96. struct msm_property_info property_info;
  97. struct msm_property_data property_data[PLANE_PROP_COUNT];
  98. struct drm_property_blob *blob_info;
  99. struct drm_property_blob *blob_rot_caps;
  100. /* debugfs related stuff */
  101. struct dentry *debugfs_root;
  102. bool debugfs_default_scale;
  103. };
  104. #define to_sde_plane(x) container_of(x, struct sde_plane, base)
  105. static int plane_prop_array[PLANE_PROP_COUNT] = {SDE_PLANE_DIRTY_ALL};
  106. static struct sde_kms *_sde_plane_get_kms(struct drm_plane *plane)
  107. {
  108. struct msm_drm_private *priv;
  109. if (!plane || !plane->dev)
  110. return NULL;
  111. priv = plane->dev->dev_private;
  112. if (!priv)
  113. return NULL;
  114. return to_sde_kms(priv->kms);
  115. }
  116. static struct sde_hw_ctl *_sde_plane_get_hw_ctl(const struct drm_plane *plane)
  117. {
  118. struct drm_plane_state *pstate = NULL;
  119. struct drm_crtc *drm_crtc = NULL;
  120. struct sde_crtc *sde_crtc = NULL;
  121. struct sde_crtc_mixer *mixer = NULL;
  122. struct sde_hw_ctl *ctl = NULL;
  123. if (!plane) {
  124. DRM_ERROR("Invalid plane %pK\n", plane);
  125. return NULL;
  126. }
  127. pstate = plane->state;
  128. if (!pstate) {
  129. DRM_ERROR("Invalid plane state %pK\n", pstate);
  130. return NULL;
  131. }
  132. drm_crtc = pstate->crtc;
  133. if (!drm_crtc) {
  134. DRM_ERROR("Invalid drm_crtc %pK\n", drm_crtc);
  135. return NULL;
  136. }
  137. sde_crtc = to_sde_crtc(drm_crtc);
  138. if (!sde_crtc) {
  139. DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
  140. return NULL;
  141. }
  142. /* it will always return the first mixer and single CTL */
  143. mixer = sde_crtc->mixers;
  144. if (!mixer) {
  145. DRM_ERROR("invalid mixer %pK\n", mixer);
  146. return NULL;
  147. }
  148. ctl = mixer->hw_ctl;
  149. if (!mixer) {
  150. DRM_ERROR("invalid ctl %pK\n", ctl);
  151. return NULL;
  152. }
  153. return ctl;
  154. }
  155. static bool sde_plane_enabled(const struct drm_plane_state *state)
  156. {
  157. return state && state->fb && state->crtc;
  158. }
  159. bool sde_plane_is_sec_ui_allowed(struct drm_plane *plane)
  160. {
  161. struct sde_plane *psde;
  162. if (!plane)
  163. return false;
  164. psde = to_sde_plane(plane);
  165. return !(psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI));
  166. }
  167. void sde_plane_setup_src_split_order(struct drm_plane *plane,
  168. enum sde_sspp_multirect_index rect_mode, bool enable)
  169. {
  170. struct sde_plane *psde;
  171. if (!plane)
  172. return;
  173. psde = to_sde_plane(plane);
  174. if (psde->pipe_hw->ops.set_src_split_order)
  175. psde->pipe_hw->ops.set_src_split_order(psde->pipe_hw,
  176. rect_mode, enable);
  177. }
  178. void sde_plane_set_sid(struct drm_plane *plane, u32 vm)
  179. {
  180. struct sde_plane *psde;
  181. struct sde_kms *sde_kms;
  182. struct msm_drm_private *priv;
  183. if (!plane || !plane->dev) {
  184. SDE_ERROR("invalid plane\n");
  185. return;
  186. }
  187. priv = plane->dev->dev_private;
  188. if (!priv || !priv->kms) {
  189. SDE_ERROR("invalid KMS reference\n");
  190. return;
  191. }
  192. sde_kms = to_sde_kms(priv->kms);
  193. psde = to_sde_plane(plane);
  194. sde_hw_set_sspp_sid(sde_kms->hw_sid, psde->pipe, vm, sde_kms->catalog);
  195. }
  196. static void _sde_plane_set_qos_lut(struct drm_plane *plane,
  197. struct drm_crtc *crtc,
  198. struct drm_framebuffer *fb)
  199. {
  200. struct sde_plane *psde;
  201. const struct sde_format *fmt = NULL;
  202. u32 frame_rate, qos_count, fps_index = 0, lut_index, creq_lut_index, ds_lut_index;
  203. struct sde_perf_cfg *perf;
  204. struct sde_plane_state *pstate;
  205. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  206. bool inline_rot = false, landscape = false;
  207. struct drm_display_mode *mode;
  208. u32 fl_require0 = 0;
  209. if (!plane || !fb) {
  210. SDE_ERROR("invalid arguments\n");
  211. return;
  212. }
  213. psde = to_sde_plane(plane);
  214. pstate = to_sde_plane_state(plane->state);
  215. if (!psde->pipe_hw || !psde->pipe_sblk || !psde->catalog) {
  216. SDE_ERROR("invalid arguments\n");
  217. return;
  218. } else if (!psde->pipe_hw->ops.setup_qos_lut) {
  219. return;
  220. }
  221. mode = &crtc->state->adjusted_mode;
  222. landscape = mode->hdisplay > mode->vdisplay ? true : false;
  223. frame_rate = drm_mode_vrefresh(&crtc->mode);
  224. perf = &psde->catalog->perf;
  225. qos_count = perf->qos_refresh_count;
  226. while ((fps_index < qos_count) && perf->qos_refresh_rate) {
  227. if ((frame_rate <= perf->qos_refresh_rate[fps_index]) ||
  228. (fps_index == qos_count - 1))
  229. break;
  230. fps_index++;
  231. }
  232. if (psde->is_rt_pipe) {
  233. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  234. inline_rot = (pstate->rotation & DRM_MODE_ROTATE_90);
  235. if (inline_rot && SDE_IS_IN_ROT_RESTRICTED_FMT(psde->catalog, fmt))
  236. lut_index = SDE_QOS_LUT_USAGE_INLINE_RESTRICTED_FMTS;
  237. else if (inline_rot)
  238. lut_index = SDE_QOS_LUT_USAGE_INLINE;
  239. else if (fmt && SDE_FORMAT_IS_LINEAR(fmt))
  240. lut_index = SDE_QOS_LUT_USAGE_LINEAR;
  241. else
  242. lut_index = SDE_QOS_LUT_USAGE_MACROTILE;
  243. } else {
  244. lut_index = (psde->wb_usage_type == WB_USAGE_OFFLINE_WB) ?
  245. SDE_QOS_LUT_USAGE_OFFLINE_WB : SDE_QOS_LUT_USAGE_NRT;
  246. }
  247. creq_lut_index = lut_index * SDE_CREQ_LUT_TYPE_MAX;
  248. if (psde->scaler3_cfg.enable)
  249. creq_lut_index += SDE_CREQ_LUT_TYPE_QSEED;
  250. creq_lut_index += (fps_index * SDE_QOS_LUT_USAGE_MAX * SDE_CREQ_LUT_TYPE_MAX);
  251. psde->pipe_qos_cfg.creq_lut = perf->creq_lut[creq_lut_index];
  252. ds_lut_index = lut_index * SDE_DANGER_SAFE_LUT_TYPE_MAX;
  253. if (landscape) {
  254. if (psde->catalog->qos_target_time_ns && sde_crtc->line_time_in_ns)
  255. fl_require0 = psde->catalog->qos_target_time_ns /
  256. (sde_crtc->line_time_in_ns * 2);
  257. if (!fl_require0 || fl_require0 < 4.5)
  258. ds_lut_index += SDE_DANGER_SAFE_LUT_TYPE_LANDSCAPE;
  259. }
  260. ds_lut_index += (fps_index * SDE_QOS_LUT_USAGE_MAX * SDE_DANGER_SAFE_LUT_TYPE_MAX);
  261. psde->pipe_qos_cfg.danger_lut = perf->danger_lut[ds_lut_index];
  262. psde->pipe_qos_cfg.safe_lut = perf->safe_lut[ds_lut_index];
  263. trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0, (fmt) ? fmt->base.pixel_format : 0,
  264. (fmt) ? fmt->fetch_mode : 0, psde->pipe_qos_cfg.danger_lut,
  265. psde->pipe_qos_cfg.safe_lut, psde->pipe_qos_cfg.creq_lut);
  266. SDE_DEBUG("plane%u: pnum:%d fmt:%4.4s fps:%d mode:%d lut[0x%x,0x%x 0x%llx] rt:%d type:%d\n",
  267. plane->base.id, psde->pipe - SSPP_VIG0,
  268. fmt ? (char *)&fmt->base.pixel_format : NULL, frame_rate,
  269. fmt ? fmt->fetch_mode : -1, psde->pipe_qos_cfg.danger_lut,
  270. psde->pipe_qos_cfg.safe_lut, psde->pipe_qos_cfg.creq_lut,
  271. psde->is_rt_pipe, psde->wb_usage_type);
  272. psde->pipe_hw->ops.setup_qos_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
  273. }
  274. /**
  275. * _sde_plane_set_qos_ctrl - set QoS control of the given plane
  276. * @plane: Pointer to drm plane
  277. * @enable: true to enable QoS control
  278. * @flags: QoS control mode (enum sde_plane_qos)
  279. */
  280. static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
  281. bool enable, u32 flags)
  282. {
  283. struct sde_plane *psde;
  284. if (!plane) {
  285. SDE_ERROR("invalid arguments\n");
  286. return;
  287. }
  288. psde = to_sde_plane(plane);
  289. if (!psde->pipe_hw || !psde->pipe_sblk) {
  290. SDE_ERROR("invalid arguments\n");
  291. return;
  292. } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
  293. return;
  294. }
  295. if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
  296. psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
  297. psde->pipe_qos_cfg.danger_vblank =
  298. psde->pipe_sblk->danger_vblank;
  299. psde->pipe_qos_cfg.vblank_en = enable;
  300. }
  301. if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
  302. /* this feature overrules previous VBLANK_CTRL */
  303. psde->pipe_qos_cfg.vblank_en = false;
  304. psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
  305. psde->pipe_qos_cfg.danger_vblank = 0;
  306. }
  307. if (flags & SDE_PLANE_QOS_PANIC_CTRL)
  308. psde->pipe_qos_cfg.danger_safe_en = enable;
  309. if (!psde->is_rt_pipe) {
  310. psde->pipe_qos_cfg.vblank_en = false;
  311. psde->pipe_qos_cfg.danger_safe_en = false;
  312. }
  313. SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
  314. plane->base.id,
  315. psde->pipe - SSPP_VIG0,
  316. psde->pipe_qos_cfg.danger_safe_en,
  317. psde->pipe_qos_cfg.vblank_en,
  318. psde->pipe_qos_cfg.creq_vblank,
  319. psde->pipe_qos_cfg.danger_vblank,
  320. psde->is_rt_pipe);
  321. psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
  322. &psde->pipe_qos_cfg);
  323. }
  324. void sde_plane_set_revalidate(struct drm_plane *plane, bool enable)
  325. {
  326. struct sde_plane *psde;
  327. if (!plane)
  328. return;
  329. psde = to_sde_plane(plane);
  330. psde->revalidate = enable;
  331. }
  332. int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
  333. {
  334. struct sde_plane *psde;
  335. int rc;
  336. if (!plane) {
  337. SDE_ERROR("invalid arguments\n");
  338. return -EINVAL;
  339. }
  340. psde = to_sde_plane(plane);
  341. if (!psde->is_rt_pipe)
  342. goto end;
  343. rc = pm_runtime_resume_and_get(plane->dev->dev);
  344. if (rc < 0) {
  345. SDE_ERROR("failed to enable power resource %d\n", rc);
  346. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  347. return rc;
  348. }
  349. _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
  350. pm_runtime_put_sync(plane->dev->dev);
  351. end:
  352. return 0;
  353. }
  354. /**
  355. * _sde_plane_set_ot_limit - set OT limit for the given plane
  356. * @plane: Pointer to drm plane
  357. * @crtc: Pointer to drm crtc
  358. */
  359. static void _sde_plane_set_ot_limit(struct drm_plane *plane,
  360. struct drm_crtc *crtc)
  361. {
  362. struct sde_plane *psde;
  363. struct sde_vbif_set_ot_params ot_params;
  364. struct msm_drm_private *priv;
  365. struct sde_kms *sde_kms;
  366. if (!plane || !plane->dev || !crtc) {
  367. SDE_ERROR("invalid arguments plane %d crtc %d\n",
  368. !plane, !crtc);
  369. return;
  370. }
  371. priv = plane->dev->dev_private;
  372. if (!priv || !priv->kms) {
  373. SDE_ERROR("invalid KMS reference\n");
  374. return;
  375. }
  376. sde_kms = to_sde_kms(priv->kms);
  377. psde = to_sde_plane(plane);
  378. if (!psde->pipe_hw) {
  379. SDE_ERROR("invalid pipe reference\n");
  380. return;
  381. }
  382. memset(&ot_params, 0, sizeof(ot_params));
  383. ot_params.xin_id = psde->pipe_hw->cap->xin_id;
  384. ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
  385. ot_params.width = psde->pipe_cfg.src_rect.w;
  386. ot_params.height = psde->pipe_cfg.src_rect.h;
  387. ot_params.is_wfd = ((psde->is_rt_pipe)
  388. || (psde->wb_usage_type == WB_USAGE_OFFLINE_WB)) ? false : true;
  389. ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
  390. ot_params.vbif_idx = VBIF_RT;
  391. ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  392. ot_params.rd = true;
  393. sde_vbif_set_ot_limit(sde_kms, &ot_params);
  394. }
  395. /**
  396. * _sde_plane_set_vbif_qos - set vbif QoS for the given plane
  397. * @plane: Pointer to drm plane
  398. */
  399. static void _sde_plane_set_qos_remap(struct drm_plane *plane)
  400. {
  401. struct sde_plane *psde;
  402. struct sde_vbif_set_qos_params qos_params;
  403. struct msm_drm_private *priv;
  404. struct sde_kms *sde_kms;
  405. if (!plane || !plane->dev) {
  406. SDE_ERROR("invalid arguments\n");
  407. return;
  408. }
  409. priv = plane->dev->dev_private;
  410. if (!priv || !priv->kms) {
  411. SDE_ERROR("invalid KMS reference\n");
  412. return;
  413. }
  414. sde_kms = to_sde_kms(priv->kms);
  415. psde = to_sde_plane(plane);
  416. if (!psde->pipe_hw) {
  417. SDE_ERROR("invalid pipe reference\n");
  418. return;
  419. }
  420. memset(&qos_params, 0, sizeof(qos_params));
  421. qos_params.vbif_idx = VBIF_RT;
  422. qos_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  423. qos_params.xin_id = psde->pipe_hw->cap->xin_id;
  424. qos_params.num = psde->pipe_hw->idx - SSPP_VIG0;
  425. if (psde->is_rt_pipe)
  426. qos_params.client_type = VBIF_RT_CLIENT;
  427. else
  428. qos_params.client_type = (psde->wb_usage_type == WB_USAGE_OFFLINE_WB) ?
  429. VBIF_OFFLINE_WB_CLIENT : VBIF_NRT_CLIENT;
  430. SDE_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
  431. plane->base.id, qos_params.num,
  432. qos_params.vbif_idx,
  433. qos_params.xin_id, qos_params.client_type,
  434. qos_params.clk_ctrl);
  435. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  436. }
  437. /**
  438. * _sde_plane_set_ts_prefill - set prefill with traffic shaper
  439. * @plane: Pointer to drm plane
  440. * @pstate: Pointer to sde plane state
  441. */
  442. static void _sde_plane_set_ts_prefill(struct drm_plane *plane,
  443. struct sde_plane_state *pstate)
  444. {
  445. struct sde_plane *psde;
  446. struct sde_hw_pipe_ts_cfg cfg;
  447. struct msm_drm_private *priv;
  448. struct sde_kms *sde_kms;
  449. if (!plane || !plane->dev) {
  450. SDE_ERROR("invalid arguments");
  451. return;
  452. }
  453. priv = plane->dev->dev_private;
  454. if (!priv || !priv->kms) {
  455. SDE_ERROR("invalid KMS reference\n");
  456. return;
  457. }
  458. sde_kms = to_sde_kms(priv->kms);
  459. psde = to_sde_plane(plane);
  460. if (!psde->pipe_hw) {
  461. SDE_ERROR("invalid pipe reference\n");
  462. return;
  463. }
  464. if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_ts_prefill)
  465. return;
  466. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_VBLANK_AMORTIZE);
  467. memset(&cfg, 0, sizeof(cfg));
  468. cfg.size = sde_plane_get_property(pstate,
  469. PLANE_PROP_PREFILL_SIZE);
  470. cfg.time = sde_plane_get_property(pstate,
  471. PLANE_PROP_PREFILL_TIME);
  472. SDE_DEBUG("plane%d size:%llu time:%llu\n",
  473. plane->base.id, cfg.size, cfg.time);
  474. SDE_EVT32_VERBOSE(DRMID(plane), cfg.size, cfg.time);
  475. psde->pipe_hw->ops.setup_ts_prefill(psde->pipe_hw, &cfg,
  476. pstate->multirect_index);
  477. }
  478. /* helper to update a state's input fence pointer from the property */
  479. static void _sde_plane_set_input_fence(struct sde_plane *psde,
  480. struct sde_plane_state *pstate, uint64_t fd)
  481. {
  482. if (!psde || !pstate) {
  483. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  484. !psde, !pstate);
  485. return;
  486. }
  487. /* clear previous reference */
  488. if (pstate->input_fence)
  489. sde_sync_put(pstate->input_fence);
  490. /* get fence pointer for later */
  491. if (fd == 0)
  492. pstate->input_fence = NULL;
  493. else
  494. pstate->input_fence = sde_sync_get(fd);
  495. SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
  496. }
  497. int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
  498. {
  499. struct sde_plane *psde;
  500. struct sde_plane_state *pstate;
  501. uint32_t prefix;
  502. void *input_fence;
  503. int ret = -EINVAL;
  504. signed long rc;
  505. if (!plane) {
  506. SDE_ERROR("invalid plane\n");
  507. } else if (!plane->state) {
  508. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  509. } else {
  510. psde = to_sde_plane(plane);
  511. pstate = to_sde_plane_state(plane->state);
  512. input_fence = pstate->input_fence;
  513. if (input_fence) {
  514. prefix = sde_sync_get_name_prefix(input_fence);
  515. rc = sde_sync_wait(input_fence, wait_ms);
  516. switch (rc) {
  517. case 0:
  518. SDE_ERROR_PLANE(psde, "%ums timeout on %08X fd %lld\n",
  519. wait_ms, prefix, sde_plane_get_property(pstate,
  520. PLANE_PROP_INPUT_FENCE));
  521. psde->is_error = true;
  522. sde_kms_timeline_status(plane->dev);
  523. ret = -ETIMEDOUT;
  524. break;
  525. case -ERESTARTSYS:
  526. SDE_ERROR_PLANE(psde,
  527. "%ums wait interrupted on %08X\n",
  528. wait_ms, prefix);
  529. psde->is_error = true;
  530. ret = -ERESTARTSYS;
  531. break;
  532. case -EINVAL:
  533. SDE_ERROR_PLANE(psde,
  534. "invalid fence param for %08X\n",
  535. prefix);
  536. psde->is_error = true;
  537. ret = -EINVAL;
  538. break;
  539. case -EBADF:
  540. SDE_INFO("plane%d spec fd signaled on bind failure fd %lld\n",
  541. plane->base.id,
  542. sde_plane_get_property(pstate, PLANE_PROP_INPUT_FENCE));
  543. psde->is_error = true;
  544. ret = 0;
  545. break;
  546. default:
  547. SDE_DEBUG_PLANE(psde, "signaled\n");
  548. ret = 0;
  549. break;
  550. }
  551. SDE_EVT32_VERBOSE(DRMID(plane), -ret, prefix);
  552. } else {
  553. ret = 0;
  554. }
  555. }
  556. return ret;
  557. }
  558. /**
  559. * _sde_plane_get_aspace: gets the address space based on the
  560. * fb_translation mode property
  561. */
  562. static int _sde_plane_get_aspace(
  563. struct sde_plane *psde,
  564. struct sde_plane_state *pstate,
  565. struct msm_gem_address_space **aspace)
  566. {
  567. struct sde_kms *kms;
  568. int mode;
  569. if (!psde || !pstate || !aspace) {
  570. SDE_ERROR("invalid parameters\n");
  571. return -EINVAL;
  572. }
  573. kms = _sde_plane_get_kms(&psde->base);
  574. if (!kms) {
  575. SDE_ERROR("invalid kms\n");
  576. return -EINVAL;
  577. }
  578. mode = sde_plane_get_property(pstate,
  579. PLANE_PROP_FB_TRANSLATION_MODE);
  580. switch (mode) {
  581. case SDE_DRM_FB_NON_SEC:
  582. *aspace = kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  583. if (!aspace)
  584. return -EINVAL;
  585. break;
  586. case SDE_DRM_FB_SEC:
  587. *aspace = kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  588. if (!aspace)
  589. return -EINVAL;
  590. break;
  591. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  592. case SDE_DRM_FB_SEC_DIR_TRANS:
  593. *aspace = NULL;
  594. break;
  595. default:
  596. SDE_ERROR("invalid fb_translation mode:%d\n", mode);
  597. return -EFAULT;
  598. }
  599. return 0;
  600. }
  601. static inline void _sde_plane_set_scanout(struct drm_plane *plane,
  602. struct sde_plane_state *pstate,
  603. struct sde_hw_pipe_cfg *pipe_cfg,
  604. struct drm_framebuffer *fb)
  605. {
  606. struct sde_plane *psde;
  607. struct msm_gem_address_space *aspace = NULL;
  608. int ret, mode;
  609. bool secure = false;
  610. if (!plane || !pstate || !pipe_cfg || !fb) {
  611. SDE_ERROR(
  612. "invalid arg(s), plane %d state %d cfg %d fb %d\n",
  613. !plane, !pstate, !pipe_cfg, !fb);
  614. return;
  615. }
  616. psde = to_sde_plane(plane);
  617. if (!psde->pipe_hw) {
  618. SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
  619. return;
  620. }
  621. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  622. if (ret) {
  623. SDE_ERROR_PLANE(psde, "Failed to get aspace %d\n", ret);
  624. return;
  625. }
  626. /*
  627. * framebuffer prepare is deferred for prepare_fb calls that
  628. * happen during the transition from secure to non-secure.
  629. * Handle the prepare at this point for such cases. This can be
  630. * expected for one or two frames during the transition.
  631. */
  632. if (aspace && pstate->defer_prepare_fb) {
  633. SDE_EVT32(DRMID(plane), psde->pipe, aspace->domain_attached);
  634. ret = msm_framebuffer_prepare(fb, pstate->aspace);
  635. if (ret) {
  636. SDE_ERROR_PLANE(psde,
  637. "failed to prepare framebuffer %d\n", ret);
  638. return;
  639. }
  640. pstate->defer_prepare_fb = false;
  641. }
  642. mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);
  643. if ((mode == SDE_DRM_FB_SEC) || (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  644. secure = true;
  645. ret = sde_format_populate_layout(aspace, fb, &pipe_cfg->layout);
  646. if (ret == -EAGAIN)
  647. SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
  648. else if (ret) {
  649. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  650. /*
  651. * Force solid fill color on error. This is to prevent
  652. * smmu faults during secure session transition.
  653. */
  654. psde->is_error = true;
  655. } else if (psde->pipe_hw->ops.setup_sourceaddress) {
  656. SDE_EVT32_VERBOSE(psde->pipe_hw->idx,
  657. pipe_cfg->layout.width,
  658. pipe_cfg->layout.height,
  659. pipe_cfg->layout.plane_addr[0],
  660. pipe_cfg->layout.plane_size[0],
  661. pipe_cfg->layout.plane_addr[1],
  662. pipe_cfg->layout.plane_size[1],
  663. pipe_cfg->layout.plane_addr[2],
  664. pipe_cfg->layout.plane_size[2],
  665. pipe_cfg->layout.plane_addr[3],
  666. pipe_cfg->layout.plane_size[3],
  667. pstate->multirect_index,
  668. secure);
  669. psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
  670. pstate->multirect_index);
  671. }
  672. }
  673. static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
  674. struct sde_plane_state *pstate)
  675. {
  676. struct sde_hw_scaler3_cfg *cfg;
  677. int ret = 0;
  678. if (!psde || !pstate) {
  679. SDE_ERROR("invalid args\n");
  680. return -EINVAL;
  681. }
  682. cfg = &psde->scaler3_cfg;
  683. cfg->dir_lut = msm_property_get_blob(
  684. &psde->property_info,
  685. &pstate->property_state, &cfg->dir_len,
  686. PLANE_PROP_SCALER_LUT_ED);
  687. cfg->cir_lut = msm_property_get_blob(
  688. &psde->property_info,
  689. &pstate->property_state, &cfg->cir_len,
  690. PLANE_PROP_SCALER_LUT_CIR);
  691. cfg->sep_lut = msm_property_get_blob(
  692. &psde->property_info,
  693. &pstate->property_state, &cfg->sep_len,
  694. PLANE_PROP_SCALER_LUT_SEP);
  695. if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
  696. ret = -ENODATA;
  697. return ret;
  698. }
  699. static int _sde_plane_setup_scaler3lite_lut(struct sde_plane *psde,
  700. struct sde_plane_state *pstate)
  701. {
  702. struct sde_hw_scaler3_cfg *cfg;
  703. cfg = &psde->scaler3_cfg;
  704. cfg->sep_lut = msm_property_get_blob(
  705. &psde->property_info,
  706. &pstate->property_state, &cfg->sep_len,
  707. PLANE_PROP_SCALER_LUT_SEP);
  708. return cfg->sep_lut ? 0 : -ENODATA;
  709. }
  710. static void _sde_plane_setup_scaler3(struct sde_plane *psde,
  711. struct sde_plane_state *pstate, const struct sde_format *fmt,
  712. uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
  713. {
  714. uint32_t decimated, i, src_w, src_h, dst_w, dst_h, src_h_pre_down;
  715. struct sde_hw_scaler3_cfg *scale_cfg;
  716. bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  717. bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
  718. if (!fmt || !chroma_subsmpl_h || !chroma_subsmpl_v) {
  719. SDE_ERROR("fmt %d smp_h %d smp_v %d\n", !fmt,
  720. chroma_subsmpl_h, chroma_subsmpl_v);
  721. return;
  722. }
  723. scale_cfg = &psde->scaler3_cfg;
  724. src_w = psde->pipe_cfg.src_rect.w;
  725. src_h = psde->pipe_cfg.src_rect.h;
  726. dst_w = psde->pipe_cfg.dst_rect.w;
  727. dst_h = psde->pipe_cfg.dst_rect.h;
  728. memset(scale_cfg, 0, sizeof(*scale_cfg));
  729. memset(&psde->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));
  730. /*
  731. * For inline rotation cases, scaler config is post-rotation,
  732. * so swap the dimensions here. However, pixel extension will
  733. * need pre-rotation settings, this will be corrected below
  734. * when calculating pixel extension settings.
  735. */
  736. if (inline_rotation)
  737. swap(src_w, src_h);
  738. decimated = DECIMATED_DIMENSION(src_w,
  739. psde->pipe_cfg.horz_decimation);
  740. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
  741. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
  742. decimated = DECIMATED_DIMENSION(src_h,
  743. psde->pipe_cfg.vert_decimation);
  744. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
  745. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
  746. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
  747. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
  748. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
  749. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
  750. scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
  751. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
  752. scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
  753. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
  754. scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
  755. scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
  756. scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
  757. scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
  758. for (i = 0; i < SDE_MAX_PLANES; i++) {
  759. /*
  760. * For inline rotation cases with pre-downscaling enabled
  761. * set x pre-downscale value if required. Only x direction
  762. * is currently supported. Use src_h as values have been swapped
  763. * and x direction corresponds to height value.
  764. */
  765. src_h_pre_down = src_h;
  766. if (pre_down_supported && inline_rotation) {
  767. if (i == 0 && (src_h > mult_frac(dst_h, 11, 5)))
  768. src_h_pre_down = src_h / 2;
  769. }
  770. scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
  771. psde->pipe_cfg.horz_decimation);
  772. scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h_pre_down,
  773. psde->pipe_cfg.vert_decimation);
  774. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
  775. scale_cfg->src_width[i] /= chroma_subsmpl_h;
  776. scale_cfg->src_height[i] /= chroma_subsmpl_v;
  777. }
  778. scale_cfg->preload_x[i] = psde->pipe_sblk->scaler_blk.h_preload;
  779. scale_cfg->preload_y[i] = psde->pipe_sblk->scaler_blk.v_preload;
  780. /* For pixel extension we need the pre-rotated orientation */
  781. if (inline_rotation) {
  782. psde->pixel_ext.num_ext_pxls_top[i] =
  783. scale_cfg->src_width[i];
  784. psde->pixel_ext.num_ext_pxls_left[i] =
  785. scale_cfg->src_height[i];
  786. } else {
  787. psde->pixel_ext.num_ext_pxls_top[i] =
  788. scale_cfg->src_height[i];
  789. psde->pixel_ext.num_ext_pxls_left[i] =
  790. scale_cfg->src_width[i];
  791. }
  792. }
  793. if ((!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
  794. && (src_w == dst_w) && !inline_rotation) ||
  795. pstate->multirect_mode)
  796. return;
  797. SDE_DEBUG_PLANE(psde,
  798. "setting bilinear: src:%dx%d dst:%dx%d chroma:%dx%d fmt:%x\n",
  799. src_w, src_h, dst_w, dst_h,
  800. chroma_subsmpl_v, chroma_subsmpl_h,
  801. fmt->base.pixel_format);
  802. scale_cfg->dst_width = dst_w;
  803. scale_cfg->dst_height = dst_h;
  804. scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
  805. scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
  806. scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
  807. scale_cfg->lut_flag = 0;
  808. scale_cfg->blend_cfg = 1;
  809. scale_cfg->enable = 1;
  810. scale_cfg->dyn_exp_disabled = SDE_QSEED_DEFAULT_DYN_EXP;
  811. }
  812. /**
  813. * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
  814. * @psde: Pointer to SDE plane object
  815. * @src: Source size
  816. * @dst: Destination size
  817. * @phase_steps: Pointer to output array for phase steps
  818. * @filter: Pointer to output array for filter type
  819. * @fmt: Pointer to format definition
  820. * @chroma_subsampling: Subsampling amount for chroma channel
  821. *
  822. * Returns: 0 on success
  823. */
  824. static int _sde_plane_setup_scaler2(struct sde_plane *psde,
  825. uint32_t src, uint32_t dst, uint32_t *phase_steps,
  826. enum sde_hw_filter *filter, const struct sde_format *fmt,
  827. uint32_t chroma_subsampling)
  828. {
  829. if (!psde || !phase_steps || !filter || !fmt) {
  830. SDE_ERROR(
  831. "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
  832. !psde, !phase_steps, !filter, !fmt);
  833. return -EINVAL;
  834. }
  835. /* calculate phase steps, leave init phase as zero */
  836. phase_steps[SDE_SSPP_COMP_0] =
  837. mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
  838. phase_steps[SDE_SSPP_COMP_1_2] =
  839. phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
  840. phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
  841. phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
  842. /* calculate scaler config, if necessary */
  843. if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
  844. filter[SDE_SSPP_COMP_3] =
  845. (src <= dst) ? SDE_SCALE_FILTER_BIL :
  846. SDE_SCALE_FILTER_PCMN;
  847. if (SDE_FORMAT_IS_YUV(fmt)) {
  848. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
  849. filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
  850. } else {
  851. filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
  852. filter[SDE_SSPP_COMP_1_2] =
  853. SDE_SCALE_FILTER_NEAREST;
  854. }
  855. } else {
  856. /* disable scaler */
  857. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
  858. filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
  859. filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
  860. }
  861. return 0;
  862. }
  863. /**
  864. * _sde_plane_setup_pixel_ext - determine default pixel extension values
  865. * @psde: Pointer to SDE plane object
  866. * @src: Source size
  867. * @dst: Destination size
  868. * @decimated_src: Source size after decimation, if any
  869. * @phase_steps: Pointer to output array for phase steps
  870. * @out_src: Output array for pixel extension values
  871. * @out_edge1: Output array for pixel extension first edge
  872. * @out_edge2: Output array for pixel extension second edge
  873. * @filter: Pointer to array for filter type
  874. * @fmt: Pointer to format definition
  875. * @chroma_subsampling: Subsampling amount for chroma channel
  876. * @post_compare: Whether to chroma subsampled source size for comparisions
  877. */
  878. static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
  879. uint32_t src, uint32_t dst, uint32_t decimated_src,
  880. uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
  881. int *out_edge2, enum sde_hw_filter *filter,
  882. const struct sde_format *fmt, uint32_t chroma_subsampling,
  883. bool post_compare)
  884. {
  885. int64_t edge1, edge2, caf;
  886. uint32_t src_work;
  887. int i, tmp;
  888. if (psde && phase_steps && out_src && out_edge1 &&
  889. out_edge2 && filter && fmt) {
  890. /* handle CAF for YUV formats */
  891. if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
  892. caf = PHASE_STEP_UNIT_SCALE;
  893. else
  894. caf = 0;
  895. for (i = 0; i < SDE_MAX_PLANES; i++) {
  896. src_work = decimated_src;
  897. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
  898. src_work /= chroma_subsampling;
  899. if (post_compare)
  900. src = src_work;
  901. if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
  902. /* unity */
  903. edge1 = 0;
  904. edge2 = 0;
  905. } else if (dst >= src) {
  906. /* upscale */
  907. edge1 = (1 << PHASE_RESIDUAL);
  908. edge1 -= caf;
  909. edge2 = (1 << PHASE_RESIDUAL);
  910. edge2 += (dst - 1) * *(phase_steps + i);
  911. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  912. edge2 += caf;
  913. edge2 = -(edge2);
  914. } else {
  915. /* downscale */
  916. edge1 = 0;
  917. edge2 = (dst - 1) * *(phase_steps + i);
  918. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  919. edge2 += *(phase_steps + i);
  920. edge2 = -(edge2);
  921. }
  922. /* only enable CAF for luma plane */
  923. caf = 0;
  924. /* populate output arrays */
  925. *(out_src + i) = src_work;
  926. /* edge updates taken from __pxl_extn_helper */
  927. if (edge1 >= 0) {
  928. tmp = (uint32_t)edge1;
  929. tmp >>= PHASE_STEP_SHIFT;
  930. *(out_edge1 + i) = -tmp;
  931. } else {
  932. tmp = (uint32_t)(-edge1);
  933. *(out_edge1 + i) =
  934. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  935. PHASE_STEP_SHIFT;
  936. }
  937. if (edge2 >= 0) {
  938. tmp = (uint32_t)edge2;
  939. tmp >>= PHASE_STEP_SHIFT;
  940. *(out_edge2 + i) = -tmp;
  941. } else {
  942. tmp = (uint32_t)(-edge2);
  943. *(out_edge2 + i) =
  944. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  945. PHASE_STEP_SHIFT;
  946. }
  947. }
  948. }
  949. }
  950. static inline void _sde_plane_setup_csc(struct sde_plane *psde)
  951. {
  952. static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
  953. {
  954. /* S15.16 format */
  955. 0x00012A00, 0x00000000, 0x00019880,
  956. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  957. 0x00012A00, 0x00020480, 0x00000000,
  958. },
  959. /* signed bias */
  960. { 0xfff0, 0xff80, 0xff80,},
  961. { 0x0, 0x0, 0x0,},
  962. /* unsigned clamp */
  963. { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
  964. { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
  965. };
  966. static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
  967. {
  968. /* S15.16 format */
  969. 0x00012A00, 0x00000000, 0x00019880,
  970. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  971. 0x00012A00, 0x00020480, 0x00000000,
  972. },
  973. /* signed bias */
  974. { 0xffc0, 0xfe00, 0xfe00,},
  975. { 0x0, 0x0, 0x0,},
  976. /* unsigned clamp */
  977. { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
  978. { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
  979. };
  980. if (!psde) {
  981. SDE_ERROR("invalid plane\n");
  982. return;
  983. }
  984. /* revert to kernel default if override not available */
  985. if (psde->csc_usr_ptr)
  986. psde->csc_ptr = psde->csc_usr_ptr;
  987. else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
  988. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
  989. else
  990. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
  991. SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
  992. psde->csc_ptr->csc_mv[0],
  993. psde->csc_ptr->csc_mv[1],
  994. psde->csc_ptr->csc_mv[2]);
  995. }
  996. static void sde_color_process_plane_setup(struct drm_plane *plane)
  997. {
  998. struct sde_plane *psde;
  999. struct sde_plane_state *pstate;
  1000. uint32_t hue, saturation, value, contrast;
  1001. struct drm_msm_memcol *memcol = NULL;
  1002. struct drm_msm_3d_gamut *vig_gamut = NULL;
  1003. struct drm_msm_igc_lut *igc = NULL;
  1004. struct drm_msm_pgc_lut *gc = NULL;
  1005. size_t memcol_sz = 0, size = 0;
  1006. struct sde_hw_cp_cfg hw_cfg = {};
  1007. struct sde_hw_ctl *ctl = _sde_plane_get_hw_ctl(plane);
  1008. bool fp16_igc, fp16_unmult;
  1009. struct drm_msm_fp16_gc *fp16_gc = NULL;
  1010. struct drm_msm_fp16_csc *fp16_csc = NULL;
  1011. psde = to_sde_plane(plane);
  1012. pstate = to_sde_plane_state(plane->state);
  1013. hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
  1014. if (psde->pipe_hw->ops.setup_pa_hue)
  1015. psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
  1016. saturation = (uint32_t) sde_plane_get_property(pstate,
  1017. PLANE_PROP_SATURATION_ADJUST);
  1018. if (psde->pipe_hw->ops.setup_pa_sat)
  1019. psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
  1020. value = (uint32_t) sde_plane_get_property(pstate,
  1021. PLANE_PROP_VALUE_ADJUST);
  1022. if (psde->pipe_hw->ops.setup_pa_val)
  1023. psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
  1024. contrast = (uint32_t) sde_plane_get_property(pstate,
  1025. PLANE_PROP_CONTRAST_ADJUST);
  1026. if (psde->pipe_hw->ops.setup_pa_cont)
  1027. psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
  1028. if (psde->pipe_hw->ops.setup_pa_memcolor) {
  1029. /* Skin memory color setup */
  1030. memcol = msm_property_get_blob(&psde->property_info,
  1031. &pstate->property_state,
  1032. &memcol_sz,
  1033. PLANE_PROP_SKIN_COLOR);
  1034. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1035. MEMCOLOR_SKIN, memcol);
  1036. /* Sky memory color setup */
  1037. memcol = msm_property_get_blob(&psde->property_info,
  1038. &pstate->property_state,
  1039. &memcol_sz,
  1040. PLANE_PROP_SKY_COLOR);
  1041. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1042. MEMCOLOR_SKY, memcol);
  1043. /* Foliage memory color setup */
  1044. memcol = msm_property_get_blob(&psde->property_info,
  1045. &pstate->property_state,
  1046. &memcol_sz,
  1047. PLANE_PROP_FOLIAGE_COLOR);
  1048. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1049. MEMCOLOR_FOLIAGE, memcol);
  1050. }
  1051. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_GAMUT &&
  1052. psde->pipe_hw->ops.setup_vig_gamut) {
  1053. vig_gamut = msm_property_get_blob(&psde->property_info,
  1054. &pstate->property_state,
  1055. &size,
  1056. PLANE_PROP_VIG_GAMUT);
  1057. hw_cfg.last_feature = 0;
  1058. hw_cfg.ctl = ctl;
  1059. hw_cfg.len = size;
  1060. hw_cfg.payload = vig_gamut;
  1061. psde->pipe_hw->ops.setup_vig_gamut(psde->pipe_hw, &hw_cfg);
  1062. }
  1063. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_IGC &&
  1064. psde->pipe_hw->ops.setup_vig_igc) {
  1065. igc = msm_property_get_blob(&psde->property_info,
  1066. &pstate->property_state,
  1067. &size,
  1068. PLANE_PROP_VIG_IGC);
  1069. hw_cfg.last_feature = 0;
  1070. hw_cfg.ctl = ctl;
  1071. hw_cfg.len = size;
  1072. hw_cfg.payload = igc;
  1073. psde->pipe_hw->ops.setup_vig_igc(psde->pipe_hw, &hw_cfg);
  1074. }
  1075. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_IGC &&
  1076. psde->pipe_hw->ops.setup_dma_igc) {
  1077. igc = msm_property_get_blob(&psde->property_info,
  1078. &pstate->property_state,
  1079. &size,
  1080. PLANE_PROP_DMA_IGC);
  1081. hw_cfg.last_feature = 0;
  1082. hw_cfg.ctl = ctl;
  1083. hw_cfg.len = size;
  1084. hw_cfg.payload = igc;
  1085. psde->pipe_hw->ops.setup_dma_igc(psde->pipe_hw, &hw_cfg,
  1086. pstate->multirect_index);
  1087. }
  1088. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_GC &&
  1089. psde->pipe_hw->ops.setup_dma_gc) {
  1090. gc = msm_property_get_blob(&psde->property_info,
  1091. &pstate->property_state,
  1092. &size,
  1093. PLANE_PROP_DMA_GC);
  1094. hw_cfg.last_feature = 0;
  1095. hw_cfg.ctl = ctl;
  1096. hw_cfg.len = size;
  1097. hw_cfg.payload = gc;
  1098. psde->pipe_hw->ops.setup_dma_gc(psde->pipe_hw, &hw_cfg,
  1099. pstate->multirect_index);
  1100. }
  1101. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_IGC &&
  1102. psde->pipe_hw->ops.setup_fp16_igc) {
  1103. fp16_igc = !!sde_plane_get_property(pstate,
  1104. PLANE_PROP_FP16_IGC);
  1105. hw_cfg.last_feature = 0;
  1106. hw_cfg.ctl = ctl;
  1107. hw_cfg.len = sizeof(bool);
  1108. hw_cfg.payload = &fp16_igc;
  1109. psde->pipe_hw->ops.setup_fp16_igc(psde->pipe_hw,
  1110. pstate->multirect_index, &hw_cfg);
  1111. }
  1112. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_GC &&
  1113. psde->pipe_hw->ops.setup_fp16_gc) {
  1114. fp16_gc = msm_property_get_blob(&psde->property_info,
  1115. &pstate->property_state,
  1116. &size,
  1117. PLANE_PROP_FP16_GC);
  1118. hw_cfg.last_feature = 0;
  1119. hw_cfg.ctl = ctl;
  1120. hw_cfg.len = size;
  1121. hw_cfg.payload = fp16_gc;
  1122. psde->pipe_hw->ops.setup_fp16_gc(psde->pipe_hw,
  1123. pstate->multirect_index, &hw_cfg);
  1124. }
  1125. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_CSC &&
  1126. psde->pipe_hw->ops.setup_fp16_csc) {
  1127. fp16_csc = msm_property_get_blob(&psde->property_info,
  1128. &pstate->property_state,
  1129. &size,
  1130. PLANE_PROP_FP16_CSC);
  1131. hw_cfg.last_feature = 0;
  1132. hw_cfg.ctl = ctl;
  1133. hw_cfg.len = size;
  1134. hw_cfg.payload = fp16_csc;
  1135. psde->pipe_hw->ops.setup_fp16_csc(psde->pipe_hw,
  1136. pstate->multirect_index, &hw_cfg);
  1137. }
  1138. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_UNMULT &&
  1139. psde->pipe_hw->ops.setup_fp16_unmult) {
  1140. fp16_unmult = !!sde_plane_get_property(pstate,
  1141. PLANE_PROP_FP16_UNMULT);
  1142. hw_cfg.last_feature = 0;
  1143. hw_cfg.ctl = ctl;
  1144. hw_cfg.len = sizeof(bool);
  1145. hw_cfg.payload = &fp16_unmult;
  1146. psde->pipe_hw->ops.setup_fp16_unmult(psde->pipe_hw,
  1147. pstate->multirect_index, &hw_cfg);
  1148. }
  1149. }
  1150. static void _sde_plane_setup_scaler(struct sde_plane *psde,
  1151. struct sde_plane_state *pstate,
  1152. const struct sde_format *fmt, bool color_fill)
  1153. {
  1154. struct sde_hw_pixel_ext *pe;
  1155. uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
  1156. const struct drm_format_info *info = NULL;
  1157. if (!psde || !fmt || !pstate) {
  1158. SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
  1159. !psde, !fmt, !pstate);
  1160. return;
  1161. }
  1162. memcpy(&psde->scaler3_cfg, &pstate->scaler3_cfg,
  1163. sizeof(psde->scaler3_cfg));
  1164. memcpy(&psde->pixel_ext, &pstate->pixel_ext,
  1165. sizeof(psde->pixel_ext));
  1166. info = drm_format_info(fmt->base.pixel_format);
  1167. pe = &psde->pixel_ext;
  1168. psde->pipe_cfg.horz_decimation =
  1169. sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  1170. psde->pipe_cfg.vert_decimation =
  1171. sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  1172. /* don't chroma subsample if decimating */
  1173. chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : info->hsub;
  1174. chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : info->vsub;
  1175. /* update scaler */
  1176. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  1177. (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE))) {
  1178. int rc = -EINVAL;
  1179. if (!color_fill && !psde->debugfs_default_scale)
  1180. rc = is_qseed3_rev_qseed3lite(psde->pipe_hw->catalog) ?
  1181. _sde_plane_setup_scaler3lite_lut(psde, pstate) :
  1182. _sde_plane_setup_scaler3_lut(psde, pstate);
  1183. if (rc || pstate->scaler_check_state !=
  1184. SDE_PLANE_SCLCHECK_SCALER_V2) {
  1185. SDE_EVT32_VERBOSE(DRMID(&psde->base), color_fill,
  1186. pstate->scaler_check_state,
  1187. psde->debugfs_default_scale, rc,
  1188. psde->pipe_cfg.src_rect.w,
  1189. psde->pipe_cfg.src_rect.h,
  1190. psde->pipe_cfg.dst_rect.w,
  1191. psde->pipe_cfg.dst_rect.h,
  1192. pstate->multirect_mode);
  1193. /* calculate default config for QSEED3 */
  1194. _sde_plane_setup_scaler3(psde, pstate, fmt,
  1195. chroma_subsmpl_h, chroma_subsmpl_v);
  1196. }
  1197. } else if (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V1 ||
  1198. color_fill || psde->debugfs_default_scale) {
  1199. uint32_t deci_dim, i;
  1200. /* calculate default configuration for QSEED2 */
  1201. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  1202. SDE_DEBUG_PLANE(psde, "default config\n");
  1203. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
  1204. psde->pipe_cfg.horz_decimation);
  1205. _sde_plane_setup_scaler2(psde,
  1206. deci_dim,
  1207. psde->pipe_cfg.dst_rect.w,
  1208. pe->phase_step_x,
  1209. pe->horz_filter, fmt, chroma_subsmpl_h);
  1210. if (SDE_FORMAT_IS_YUV(fmt))
  1211. deci_dim &= ~0x1;
  1212. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
  1213. psde->pipe_cfg.dst_rect.w, deci_dim,
  1214. pe->phase_step_x,
  1215. pe->roi_w,
  1216. pe->num_ext_pxls_left,
  1217. pe->num_ext_pxls_right, pe->horz_filter, fmt,
  1218. chroma_subsmpl_h, 0);
  1219. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
  1220. psde->pipe_cfg.vert_decimation);
  1221. _sde_plane_setup_scaler2(psde,
  1222. deci_dim,
  1223. psde->pipe_cfg.dst_rect.h,
  1224. pe->phase_step_y,
  1225. pe->vert_filter, fmt, chroma_subsmpl_v);
  1226. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
  1227. psde->pipe_cfg.dst_rect.h, deci_dim,
  1228. pe->phase_step_y,
  1229. pe->roi_h,
  1230. pe->num_ext_pxls_top,
  1231. pe->num_ext_pxls_btm, pe->vert_filter, fmt,
  1232. chroma_subsmpl_v, 1);
  1233. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1234. if (pe->num_ext_pxls_left[i] >= 0)
  1235. pe->left_rpt[i] = pe->num_ext_pxls_left[i];
  1236. else
  1237. pe->left_ftch[i] = pe->num_ext_pxls_left[i];
  1238. if (pe->num_ext_pxls_right[i] >= 0)
  1239. pe->right_rpt[i] = pe->num_ext_pxls_right[i];
  1240. else
  1241. pe->right_ftch[i] = pe->num_ext_pxls_right[i];
  1242. if (pe->num_ext_pxls_top[i] >= 0)
  1243. pe->top_rpt[i] = pe->num_ext_pxls_top[i];
  1244. else
  1245. pe->top_ftch[i] = pe->num_ext_pxls_top[i];
  1246. if (pe->num_ext_pxls_btm[i] >= 0)
  1247. pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
  1248. else
  1249. pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
  1250. }
  1251. }
  1252. if (psde->pipe_hw->ops.setup_pre_downscale)
  1253. psde->pipe_hw->ops.setup_pre_downscale(psde->pipe_hw,
  1254. &pstate->pre_down);
  1255. }
  1256. /**
  1257. * _sde_plane_color_fill - enables color fill on plane
  1258. * @psde: Pointer to SDE plane object
  1259. * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
  1260. * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
  1261. * Returns: 0 on success
  1262. */
  1263. static int _sde_plane_color_fill(struct sde_plane *psde,
  1264. uint32_t color, uint32_t alpha)
  1265. {
  1266. const struct sde_format *fmt;
  1267. const struct drm_plane *plane;
  1268. struct sde_plane_state *pstate;
  1269. bool blend_enable = true;
  1270. if (!psde || !psde->base.state) {
  1271. SDE_ERROR("invalid plane\n");
  1272. return -EINVAL;
  1273. }
  1274. if (!psde->pipe_hw) {
  1275. SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
  1276. return -EINVAL;
  1277. }
  1278. plane = &psde->base;
  1279. pstate = to_sde_plane_state(plane->state);
  1280. SDE_DEBUG_PLANE(psde, "\n");
  1281. /*
  1282. * select fill format to match user property expectation,
  1283. * h/w only supports RGB variants
  1284. */
  1285. fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
  1286. blend_enable = (SDE_DRM_BLEND_OP_OPAQUE !=
  1287. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP));
  1288. /* update sspp */
  1289. if (fmt && psde->pipe_hw->ops.setup_solidfill) {
  1290. psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
  1291. (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
  1292. pstate->multirect_index);
  1293. /* override scaler/decimation if solid fill */
  1294. psde->pipe_cfg.src_rect.x = 0;
  1295. psde->pipe_cfg.src_rect.y = 0;
  1296. psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
  1297. psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
  1298. _sde_plane_setup_scaler(psde, pstate, fmt, true);
  1299. if (psde->pipe_hw->ops.setup_format)
  1300. psde->pipe_hw->ops.setup_format(psde->pipe_hw,
  1301. fmt, blend_enable,
  1302. SDE_SSPP_SOLID_FILL,
  1303. pstate->multirect_index);
  1304. if (psde->pipe_hw->ops.setup_rects)
  1305. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  1306. &psde->pipe_cfg,
  1307. pstate->multirect_index);
  1308. if (psde->pipe_hw->ops.setup_pe)
  1309. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  1310. &psde->pixel_ext);
  1311. if (psde->pipe_hw->ops.setup_scaler &&
  1312. pstate->multirect_index != SDE_SSPP_RECT_1) {
  1313. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  1314. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  1315. &psde->pipe_cfg, &psde->pixel_ext,
  1316. &psde->scaler3_cfg);
  1317. }
  1318. }
  1319. return 0;
  1320. }
  1321. /**
  1322. * sde_plane_rot_atomic_check - verify rotator update of the given state
  1323. * @plane: Pointer to drm plane
  1324. * @state: Pointer to drm plane state to be validated
  1325. * return: 0 if success; error code otherwise
  1326. */
  1327. static int sde_plane_rot_atomic_check(struct drm_plane *plane,
  1328. struct drm_plane_state *state)
  1329. {
  1330. struct sde_plane *psde;
  1331. struct sde_plane_state *pstate, *old_pstate;
  1332. int ret = 0;
  1333. u32 rotation;
  1334. if (!plane || !state) {
  1335. SDE_ERROR("invalid plane/state\n");
  1336. return -EINVAL;
  1337. }
  1338. psde = to_sde_plane(plane);
  1339. pstate = to_sde_plane_state(state);
  1340. old_pstate = to_sde_plane_state(plane->state);
  1341. /* check inline rotation and simplify the transform */
  1342. rotation = drm_rotation_simplify(
  1343. state->rotation,
  1344. DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1345. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1346. if ((rotation & DRM_MODE_ROTATE_180) ||
  1347. (rotation & DRM_MODE_ROTATE_270)) {
  1348. SDE_ERROR_PLANE(psde,
  1349. "invalid rotation transform must be simplified 0x%x\n",
  1350. rotation);
  1351. ret = -EINVAL;
  1352. goto exit;
  1353. }
  1354. if (rotation & DRM_MODE_ROTATE_90) {
  1355. struct msm_drm_private *priv = plane->dev->dev_private;
  1356. struct sde_kms *sde_kms;
  1357. const struct msm_format *msm_fmt;
  1358. const struct sde_format *fmt;
  1359. struct sde_rect src;
  1360. bool q16_data = true;
  1361. POPULATE_RECT(&src, state->src_x, state->src_y,
  1362. state->src_w, state->src_h, q16_data);
  1363. /*
  1364. * DRM framework expects rotation flag in counter-clockwise
  1365. * direction and the HW expects in clockwise direction.
  1366. * Flip the flags to match with HW.
  1367. */
  1368. rotation ^= (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1369. if (!psde->pipe_sblk->in_rot_maxdwnscale_rt_num ||
  1370. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom ||
  1371. !psde->pipe_sblk->in_rot_maxdwnscale_nrt ||
  1372. !psde->pipe_sblk->in_rot_maxheight ||
  1373. !psde->pipe_sblk->in_rot_format_list ||
  1374. !(psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))) {
  1375. SDE_ERROR_PLANE(psde,
  1376. "wrong config rt:%d/%d nrt:%d fmt:%d h:%d 0x%x\n",
  1377. !psde->pipe_sblk->in_rot_maxdwnscale_rt_num,
  1378. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom,
  1379. !psde->pipe_sblk->in_rot_maxdwnscale_nrt,
  1380. !psde->pipe_sblk->in_rot_format_list,
  1381. !psde->pipe_sblk->in_rot_maxheight,
  1382. psde->features);
  1383. ret = -EINVAL;
  1384. goto exit;
  1385. }
  1386. /* check for valid height */
  1387. if (src.h > psde->pipe_sblk->in_rot_maxheight) {
  1388. SDE_ERROR_PLANE(psde,
  1389. "invalid height for inline rot:%d max:%d\n",
  1390. src.h, psde->pipe_sblk->in_rot_maxheight);
  1391. ret = -EINVAL;
  1392. goto exit;
  1393. }
  1394. if (!sde_plane_enabled(state))
  1395. goto exit;
  1396. /* check for valid formats supported by inline rot */
  1397. sde_kms = to_sde_kms(priv->kms);
  1398. msm_fmt = msm_framebuffer_format(state->fb);
  1399. fmt = to_sde_format(msm_fmt);
  1400. ret = sde_format_validate_fmt(&sde_kms->base, fmt,
  1401. psde->pipe_sblk->in_rot_format_list);
  1402. }
  1403. exit:
  1404. pstate->rotation = rotation;
  1405. return ret;
  1406. }
  1407. static bool _sde_plane_halt_requests(struct drm_plane *plane,
  1408. uint32_t xin_id, bool halt_forced_clk, bool enable)
  1409. {
  1410. struct sde_plane *psde;
  1411. struct msm_drm_private *priv;
  1412. struct sde_vbif_set_xin_halt_params halt_params;
  1413. if (!plane || !plane->dev) {
  1414. SDE_ERROR("invalid arguments\n");
  1415. return false;
  1416. }
  1417. psde = to_sde_plane(plane);
  1418. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1419. SDE_ERROR("invalid pipe reference\n");
  1420. return false;
  1421. }
  1422. priv = plane->dev->dev_private;
  1423. if (!priv || !priv->kms) {
  1424. SDE_ERROR("invalid KMS reference\n");
  1425. return false;
  1426. }
  1427. memset(&halt_params, 0, sizeof(halt_params));
  1428. halt_params.vbif_idx = VBIF_RT;
  1429. halt_params.xin_id = xin_id;
  1430. halt_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  1431. halt_params.forced_on = halt_forced_clk;
  1432. halt_params.enable = enable;
  1433. return sde_vbif_set_xin_halt(to_sde_kms(priv->kms), &halt_params);
  1434. }
  1435. void sde_plane_halt_requests(struct drm_plane *plane, bool enable)
  1436. {
  1437. struct sde_plane *psde;
  1438. if (!plane) {
  1439. SDE_ERROR("invalid plane\n");
  1440. return;
  1441. }
  1442. psde = to_sde_plane(plane);
  1443. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1444. SDE_ERROR("invalid pipe reference\n");
  1445. return;
  1446. }
  1447. SDE_EVT32(DRMID(plane), psde->xin_halt_forced_clk, enable);
  1448. psde->xin_halt_forced_clk =
  1449. _sde_plane_halt_requests(plane, psde->pipe_hw->cap->xin_id,
  1450. psde->xin_halt_forced_clk, enable);
  1451. }
  1452. void sde_plane_secure_ctrl_xin_client(struct drm_plane *plane,
  1453. struct drm_crtc *crtc)
  1454. {
  1455. struct sde_plane *psde;
  1456. if (!plane || !crtc) {
  1457. SDE_ERROR("invalid plane/crtc\n");
  1458. return;
  1459. }
  1460. psde = to_sde_plane(plane);
  1461. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  1462. return;
  1463. /* do all VBIF programming for the sec-ui allowed SSPP */
  1464. _sde_plane_set_qos_remap(plane);
  1465. _sde_plane_set_ot_limit(plane, crtc);
  1466. }
  1467. /**
  1468. * sde_plane_rot_install_properties - install plane rotator properties
  1469. * @plane: Pointer to drm plane
  1470. * @catalog: Pointer to mdss configuration
  1471. * return: none
  1472. */
  1473. static void sde_plane_rot_install_properties(struct drm_plane *plane,
  1474. struct sde_mdss_cfg *catalog)
  1475. {
  1476. struct sde_plane *psde = to_sde_plane(plane);
  1477. unsigned int supported_rotations = DRM_MODE_ROTATE_0 |
  1478. DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
  1479. int ret = 0;
  1480. if (!plane || !psde) {
  1481. SDE_ERROR("invalid plane\n");
  1482. return;
  1483. } else if (!catalog) {
  1484. SDE_ERROR("invalid catalog\n");
  1485. return;
  1486. }
  1487. if (!psde->is_virtual && psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))
  1488. supported_rotations |= DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270;
  1489. ret = drm_plane_create_rotation_property(plane,
  1490. DRM_MODE_ROTATE_0, supported_rotations);
  1491. if (ret) {
  1492. DRM_ERROR("create rotation property failed: %d\n", ret);
  1493. return;
  1494. }
  1495. }
  1496. void sde_plane_clear_multirect(const struct drm_plane_state *drm_state)
  1497. {
  1498. struct sde_plane_state *pstate;
  1499. if (!drm_state)
  1500. return;
  1501. pstate = to_sde_plane_state(drm_state);
  1502. pstate->multirect_index = SDE_SSPP_RECT_SOLO;
  1503. pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
  1504. }
  1505. /**
  1506. * multi_rect validate API allows to validate only R0 and R1 RECT
  1507. * passing for each plane. Client of this API must not pass multiple
  1508. * plane which are not sharing same XIN client. Such calls will fail
  1509. * even though kernel client is passing valid multirect configuration.
  1510. */
  1511. int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
  1512. {
  1513. struct sde_plane_state *pstate[R_MAX];
  1514. const struct drm_plane_state *drm_state[R_MAX];
  1515. struct sde_rect src[R_MAX], dst[R_MAX];
  1516. struct sde_plane *sde_plane[R_MAX];
  1517. const struct sde_format *fmt[R_MAX];
  1518. int xin_id[R_MAX];
  1519. bool q16_data = true;
  1520. int i, j, buffer_lines, width_threshold[R_MAX];
  1521. unsigned int max_tile_height = 1;
  1522. bool parallel_fetch_qualified = true;
  1523. enum sde_sspp_multirect_mode mode = SDE_SSPP_MULTIRECT_NONE;
  1524. const struct msm_format *msm_fmt;
  1525. bool const_alpha_enable = true;
  1526. for (i = 0; i < R_MAX; i++) {
  1527. drm_state[i] = i ? plane->r1 : plane->r0;
  1528. if (!drm_state[i]) {
  1529. SDE_ERROR("drm plane state is NULL\n");
  1530. return -EINVAL;
  1531. }
  1532. pstate[i] = to_sde_plane_state(drm_state[i]);
  1533. sde_plane[i] = to_sde_plane(drm_state[i]->plane);
  1534. xin_id[i] = sde_plane[i]->pipe_hw->cap->xin_id;
  1535. for (j = 0; j < i; j++) {
  1536. if (xin_id[i] != xin_id[j]) {
  1537. SDE_ERROR_PLANE(sde_plane[i],
  1538. "invalid multirect validate call base:%d xin_id:%d curr:%d xin:%d\n",
  1539. j, xin_id[j], i, xin_id[i]);
  1540. return -EINVAL;
  1541. }
  1542. }
  1543. msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
  1544. if (!msm_fmt) {
  1545. SDE_ERROR_PLANE(sde_plane[i], "null fb\n");
  1546. return -EINVAL;
  1547. }
  1548. fmt[i] = to_sde_format(msm_fmt);
  1549. if (SDE_FORMAT_IS_UBWC(fmt[i]) &&
  1550. (fmt[i]->tile_height > max_tile_height))
  1551. max_tile_height = fmt[i]->tile_height;
  1552. POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
  1553. drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
  1554. POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
  1555. drm_state[i]->crtc_y, drm_state[i]->crtc_w,
  1556. drm_state[i]->crtc_h, !q16_data);
  1557. if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
  1558. SDE_ERROR_PLANE(sde_plane[i],
  1559. "scaling is not supported in multirect mode\n");
  1560. return -EINVAL;
  1561. }
  1562. if (pstate[i]->rotation & DRM_MODE_ROTATE_90) {
  1563. SDE_ERROR_PLANE(sde_plane[i],
  1564. "inline rotation is not supported in mulirect mode\n");
  1565. return -EINVAL;
  1566. }
  1567. if (SDE_FORMAT_IS_YUV(fmt[i])) {
  1568. SDE_ERROR_PLANE(sde_plane[i],
  1569. "Unsupported format for multirect mode\n");
  1570. return -EINVAL;
  1571. }
  1572. /**
  1573. * SSPP PD_MEM is split half - one for each RECT.
  1574. * Tiled formats need 5 lines of buffering while fetching
  1575. * whereas linear formats need only 2 lines.
  1576. * So we cannot support more than half of the supported SSPP
  1577. * width for tiled formats.
  1578. */
  1579. width_threshold[i] = sde_plane[i]->pipe_sblk->maxlinewidth;
  1580. if (SDE_FORMAT_IS_UBWC(fmt[i]))
  1581. width_threshold[i] /= 2;
  1582. if (parallel_fetch_qualified && src[i].w > width_threshold[i])
  1583. parallel_fetch_qualified = false;
  1584. if (sde_plane[i]->is_virtual)
  1585. mode = sde_plane_get_property(pstate[i],
  1586. PLANE_PROP_MULTIRECT_MODE);
  1587. if (pstate[i]->const_alpha_en != const_alpha_enable)
  1588. const_alpha_enable = false;
  1589. }
  1590. buffer_lines = 2 * max_tile_height;
  1591. /**
  1592. * fallback to driver mode selection logic if client is using
  1593. * multirect plane without setting property.
  1594. *
  1595. * validate multirect mode configuration based on rectangle
  1596. */
  1597. switch (mode) {
  1598. case SDE_SSPP_MULTIRECT_NONE:
  1599. if (parallel_fetch_qualified)
  1600. mode = SDE_SSPP_MULTIRECT_PARALLEL;
  1601. else if (TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) ||
  1602. TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines))
  1603. mode = SDE_SSPP_MULTIRECT_TIME_MX;
  1604. else
  1605. SDE_ERROR(
  1606. "planes(%d - %d) multirect mode selection fail\n",
  1607. drm_state[R0]->plane->base.id,
  1608. drm_state[R1]->plane->base.id);
  1609. break;
  1610. case SDE_SSPP_MULTIRECT_PARALLEL:
  1611. if (!parallel_fetch_qualified) {
  1612. SDE_ERROR("R0 plane:%d width_threshold:%d src_w:%d\n",
  1613. drm_state[R0]->plane->base.id,
  1614. width_threshold[R0], src[R0].w);
  1615. SDE_ERROR("R1 plane:%d width_threshold:%d src_w:%d\n",
  1616. drm_state[R1]->plane->base.id,
  1617. width_threshold[R1], src[R1].w);
  1618. SDE_ERROR("parallel fetch not qualified\n");
  1619. mode = SDE_SSPP_MULTIRECT_NONE;
  1620. }
  1621. break;
  1622. case SDE_SSPP_MULTIRECT_TIME_MX:
  1623. if (!TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) &&
  1624. !TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines)) {
  1625. SDE_ERROR(
  1626. "buffer_lines:%d R0 plane:%d dst_y:%d dst_h:%d\n",
  1627. buffer_lines, drm_state[R0]->plane->base.id,
  1628. dst[R0].y, dst[R0].h);
  1629. SDE_ERROR(
  1630. "buffer_lines:%d R1 plane:%d dst_y:%d dst_h:%d\n",
  1631. buffer_lines, drm_state[R1]->plane->base.id,
  1632. dst[R1].y, dst[R1].h);
  1633. SDE_ERROR("time multiplexed fetch not qualified\n");
  1634. mode = SDE_SSPP_MULTIRECT_NONE;
  1635. }
  1636. break;
  1637. default:
  1638. SDE_ERROR("bad mode:%d selection\n", mode);
  1639. mode = SDE_SSPP_MULTIRECT_NONE;
  1640. break;
  1641. }
  1642. for (i = 0; i < R_MAX; i++) {
  1643. pstate[i]->multirect_mode = mode;
  1644. pstate[i]->const_alpha_en = const_alpha_enable;
  1645. }
  1646. if (mode == SDE_SSPP_MULTIRECT_NONE)
  1647. return -EINVAL;
  1648. if (sde_plane[R0]->is_virtual) {
  1649. pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
  1650. pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
  1651. } else {
  1652. pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
  1653. pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
  1654. }
  1655. SDE_DEBUG_PLANE(sde_plane[R0], "R0: %d - %d\n",
  1656. pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
  1657. SDE_DEBUG_PLANE(sde_plane[R1], "R1: %d - %d\n",
  1658. pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
  1659. return 0;
  1660. }
  1661. /**
  1662. * sde_plane_ctl_flush - set/clear control flush bitmask for the given plane
  1663. * @plane: Pointer to drm plane structure
  1664. * @ctl: Pointer to hardware control driver
  1665. * @set: set if true else clear
  1666. */
  1667. void sde_plane_ctl_flush(struct drm_plane *plane, struct sde_hw_ctl *ctl,
  1668. bool set)
  1669. {
  1670. if (!plane || !ctl) {
  1671. SDE_ERROR("invalid parameters\n");
  1672. return;
  1673. }
  1674. if (!ctl->ops.update_bitmask_sspp) {
  1675. SDE_ERROR("invalid ops\n");
  1676. return;
  1677. }
  1678. ctl->ops.update_bitmask_sspp(ctl, sde_plane_pipe(plane), set);
  1679. }
  1680. static int sde_plane_prepare_fb(struct drm_plane *plane,
  1681. struct drm_plane_state *new_state)
  1682. {
  1683. struct drm_framebuffer *fb = new_state->fb;
  1684. struct sde_plane *psde = to_sde_plane(plane);
  1685. struct sde_plane_state *pstate = to_sde_plane_state(new_state);
  1686. struct sde_hw_fmt_layout layout;
  1687. struct msm_gem_address_space *aspace;
  1688. int ret;
  1689. if (!fb)
  1690. return 0;
  1691. SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
  1692. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  1693. if (ret) {
  1694. SDE_ERROR_PLANE(psde, "Failed to get aspace\n");
  1695. return ret;
  1696. }
  1697. /* cache aspace */
  1698. pstate->aspace = aspace;
  1699. /*
  1700. * when transitioning from secure to non-secure,
  1701. * plane->prepare_fb happens before the commit. In such case,
  1702. * defer the prepare_fb and handled it late, during the commit
  1703. * after attaching the domains as part of the transition
  1704. */
  1705. pstate->defer_prepare_fb = (aspace && !aspace->domain_attached) ?
  1706. true : false;
  1707. if (pstate->defer_prepare_fb) {
  1708. SDE_EVT32(DRMID(plane), psde->pipe);
  1709. SDE_DEBUG_PLANE(psde,
  1710. "domain not attached, prepare_fb handled later\n");
  1711. return 0;
  1712. }
  1713. if (pstate->aspace && fb) {
  1714. ret = msm_framebuffer_prepare(fb,
  1715. pstate->aspace);
  1716. if (ret) {
  1717. SDE_ERROR("failed to prepare framebuffer fb:%d plane:%d pipe:%d ret:%d\n",
  1718. fb->base.id, plane->base.id, psde->pipe, ret);
  1719. SDE_EVT32(fb->base.id, plane->base.id, psde->pipe, ret, SDE_EVTLOG_ERROR);
  1720. return ret;
  1721. }
  1722. }
  1723. /* validate framebuffer layout before commit */
  1724. ret = sde_format_populate_layout(pstate->aspace,
  1725. fb, &layout);
  1726. if (ret) {
  1727. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  1728. return ret;
  1729. }
  1730. return 0;
  1731. }
  1732. static void sde_plane_cleanup_fb(struct drm_plane *plane,
  1733. struct drm_plane_state *old_state)
  1734. {
  1735. struct sde_plane *psde = to_sde_plane(plane);
  1736. struct sde_plane_state *old_pstate;
  1737. if (!old_state || !old_state->fb || !plane)
  1738. return;
  1739. old_pstate = to_sde_plane_state(old_state);
  1740. SDE_DEBUG_PLANE(psde, "FB[%u]\n", old_state->fb->base.id);
  1741. msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
  1742. }
  1743. static void _sde_plane_sspp_atomic_check_mode_changed(struct sde_plane *psde,
  1744. struct drm_plane_state *state,
  1745. struct drm_plane_state *old_state)
  1746. {
  1747. struct sde_plane_state *pstate = to_sde_plane_state(state);
  1748. struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
  1749. struct drm_framebuffer *fb, *old_fb;
  1750. /* no need to check it again */
  1751. if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
  1752. return;
  1753. if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
  1754. || psde->is_error) {
  1755. SDE_DEBUG_PLANE(psde,
  1756. "enabling/disabling full modeset required\n");
  1757. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1758. } else if (to_sde_plane_state(old_state)->pending) {
  1759. SDE_DEBUG_PLANE(psde, "still pending\n");
  1760. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1761. } else if (pstate->multirect_index != old_pstate->multirect_index ||
  1762. pstate->multirect_mode != old_pstate->multirect_mode) {
  1763. SDE_DEBUG_PLANE(psde, "multirect config updated\n");
  1764. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1765. } else if (state->src_w != old_state->src_w ||
  1766. state->src_h != old_state->src_h ||
  1767. state->src_x != old_state->src_x ||
  1768. state->src_y != old_state->src_y) {
  1769. SDE_DEBUG_PLANE(psde, "src rect updated\n");
  1770. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1771. } else if (state->crtc_w != old_state->crtc_w ||
  1772. state->crtc_h != old_state->crtc_h ||
  1773. state->crtc_x != old_state->crtc_x ||
  1774. state->crtc_y != old_state->crtc_y) {
  1775. SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
  1776. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1777. } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
  1778. pstate->excl_rect.h != old_pstate->excl_rect.h ||
  1779. pstate->excl_rect.x != old_pstate->excl_rect.x ||
  1780. pstate->excl_rect.y != old_pstate->excl_rect.y) {
  1781. SDE_DEBUG_PLANE(psde, "excl_rect updated\n");
  1782. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1783. } else if (pstate->rotation != old_pstate->rotation) {
  1784. SDE_DEBUG_PLANE(psde, "rotation updated 0x%x->0x%x\n",
  1785. pstate->rotation, old_pstate->rotation);
  1786. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
  1787. }
  1788. fb = state->fb;
  1789. old_fb = old_state->fb;
  1790. if (!fb || !old_fb) {
  1791. SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
  1792. } else if ((fb->format->format != old_fb->format->format) ||
  1793. pstate->const_alpha_en != old_pstate->const_alpha_en) {
  1794. SDE_DEBUG_PLANE(psde, "format change\n");
  1795. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
  1796. } else {
  1797. uint64_t new_mod = fb->modifier;
  1798. uint64_t old_mod = old_fb->modifier;
  1799. uint32_t *new_pitches = fb->pitches;
  1800. uint32_t *old_pitches = old_fb->pitches;
  1801. uint32_t *new_offset = fb->offsets;
  1802. uint32_t *old_offset = old_fb->offsets;
  1803. int i;
  1804. if (new_mod != old_mod) {
  1805. SDE_DEBUG_PLANE(psde,
  1806. "format modifiers change new_mode:%llu old_mode:%llu\n",
  1807. new_mod, old_mod);
  1808. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1809. SDE_PLANE_DIRTY_RECTS;
  1810. }
  1811. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
  1812. if (new_pitches[i] != old_pitches[i]) {
  1813. SDE_DEBUG_PLANE(psde,
  1814. "pitches change plane:%d old_pitches:%u new_pitches:%u\n",
  1815. i, old_pitches[i], new_pitches[i]);
  1816. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1817. break;
  1818. }
  1819. }
  1820. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
  1821. if (new_offset[i] != old_offset[i]) {
  1822. SDE_DEBUG_PLANE(psde,
  1823. "offset change plane:%d old_offset:%u new_offset:%u\n",
  1824. i, old_offset[i], new_offset[i]);
  1825. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1826. SDE_PLANE_DIRTY_RECTS;
  1827. break;
  1828. }
  1829. }
  1830. }
  1831. }
  1832. int sde_plane_validate_src_addr(struct drm_plane *plane,
  1833. unsigned long base_addr, u32 size)
  1834. {
  1835. int ret = -EINVAL;
  1836. u32 addr;
  1837. struct sde_plane *psde = to_sde_plane(plane);
  1838. if (!psde || !base_addr || !size) {
  1839. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1840. return ret;
  1841. }
  1842. if (psde->pipe_hw && psde->pipe_hw->ops.get_sourceaddress) {
  1843. addr = psde->pipe_hw->ops.get_sourceaddress(psde->pipe_hw,
  1844. is_sde_plane_virtual(plane));
  1845. if ((addr >= base_addr) && (addr < (base_addr + size)))
  1846. ret = 0;
  1847. }
  1848. return ret;
  1849. }
  1850. static inline bool _sde_plane_is_pre_downscale_enabled(
  1851. struct sde_hw_inline_pre_downscale_cfg *pre_down)
  1852. {
  1853. return pre_down->pre_downscale_x_0 || pre_down->pre_downscale_y_0;
  1854. }
  1855. static int _sde_plane_validate_scaler_v2(struct sde_plane *psde,
  1856. struct sde_plane_state *pstate,
  1857. const struct sde_format *fmt,
  1858. uint32_t img_w, uint32_t img_h,
  1859. uint32_t src_w, uint32_t src_h,
  1860. uint32_t deci_w, uint32_t deci_h)
  1861. {
  1862. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  1863. bool pre_down_en;
  1864. int i;
  1865. if (!psde || !pstate || !fmt) {
  1866. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1867. return -EINVAL;
  1868. }
  1869. if (psde->debugfs_default_scale ||
  1870. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1871. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK))
  1872. return 0;
  1873. pd_cfg = &pstate->pre_down;
  1874. pre_down_en = _sde_plane_is_pre_downscale_enabled(pd_cfg);
  1875. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_INVALID;
  1876. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1877. uint32_t hor_req_pixels, hor_fetch_pixels;
  1878. uint32_t vert_req_pixels, vert_fetch_pixels;
  1879. uint32_t src_w_tmp, src_h_tmp;
  1880. uint32_t scaler_w, scaler_h;
  1881. uint32_t pre_down_ratio_x = 1, pre_down_ratio_y = 1;
  1882. bool rot;
  1883. /* re-use color plane 1's config for plane 2 */
  1884. if (i == 2)
  1885. continue;
  1886. if (pre_down_en) {
  1887. if (i == 0 && pd_cfg->pre_downscale_x_0)
  1888. pre_down_ratio_x = pd_cfg->pre_downscale_x_0;
  1889. if (i == 0 && pd_cfg->pre_downscale_y_0)
  1890. pre_down_ratio_y = pd_cfg->pre_downscale_y_0;
  1891. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_x_1)
  1892. pre_down_ratio_x = pd_cfg->pre_downscale_x_1;
  1893. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_y_1)
  1894. pre_down_ratio_y = pd_cfg->pre_downscale_y_1;
  1895. SDE_DEBUG_PLANE(psde, "pre_down[%d]: x:%d, y:%d\n",
  1896. i, pre_down_ratio_x, pre_down_ratio_y);
  1897. }
  1898. src_w_tmp = src_w;
  1899. src_h_tmp = src_h;
  1900. /*
  1901. * For chroma plane, width is half for the following sub sampled
  1902. * formats. Except in case of decimation, where hardware avoids
  1903. * 1 line of decimation instead of downsampling.
  1904. */
  1905. if (i == 1) {
  1906. if (!deci_w &&
  1907. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1908. fmt->chroma_sample == SDE_CHROMA_H2V1))
  1909. src_w_tmp >>= 1;
  1910. if (!deci_h &&
  1911. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1912. fmt->chroma_sample == SDE_CHROMA_H1V2))
  1913. src_h_tmp >>= 1;
  1914. }
  1915. hor_req_pixels = pstate->pixel_ext.roi_w[i];
  1916. vert_req_pixels = pstate->pixel_ext.roi_h[i];
  1917. hor_fetch_pixels = DECIMATED_DIMENSION(src_w_tmp +
  1918. (int8_t)(pstate->pixel_ext.left_ftch[i] & 0xFF) +
  1919. (int8_t)(pstate->pixel_ext.right_ftch[i] & 0xFF),
  1920. deci_w);
  1921. vert_fetch_pixels = DECIMATED_DIMENSION(src_h_tmp +
  1922. (int8_t)(pstate->pixel_ext.top_ftch[i] & 0xFF) +
  1923. (int8_t)(pstate->pixel_ext.btm_ftch[i] & 0xFF),
  1924. deci_h);
  1925. if ((hor_req_pixels != hor_fetch_pixels) ||
  1926. (hor_fetch_pixels > img_w) ||
  1927. (vert_req_pixels != vert_fetch_pixels) ||
  1928. (vert_fetch_pixels > img_h)) {
  1929. SDE_ERROR_PLANE(psde,
  1930. "req %d/%d, fetch %d/%d, src %dx%d\n",
  1931. hor_req_pixels, vert_req_pixels,
  1932. hor_fetch_pixels, vert_fetch_pixels,
  1933. img_w, img_h);
  1934. return -EINVAL;
  1935. }
  1936. /*
  1937. * swap the scaler src width & height for inline-rotation 90
  1938. * comparison with Pixel-Extension, as PE is based on
  1939. * pre-rotation and QSEED is based on post-rotation
  1940. */
  1941. rot = pstate->rotation & DRM_MODE_ROTATE_90;
  1942. scaler_w = rot ? pstate->scaler3_cfg.src_height[i]
  1943. : pstate->scaler3_cfg.src_width[i];
  1944. scaler_h = rot ? pstate->scaler3_cfg.src_width[i]
  1945. : pstate->scaler3_cfg.src_height[i];
  1946. /*
  1947. * Alpha plane can only be scaled using bilinear or pixel
  1948. * repeat/drop, src_width and src_height are only specified
  1949. * for Y and UV plane
  1950. */
  1951. if (i != 3 && (hor_req_pixels / pre_down_ratio_x != scaler_w ||
  1952. vert_req_pixels / pre_down_ratio_y !=
  1953. scaler_h)) {
  1954. SDE_ERROR_PLANE(psde,
  1955. "roi[%d] roi:%dx%d scaler:%dx%d src:%dx%d rot:%d pd:%d/%d\n",
  1956. i, pstate->pixel_ext.roi_w[i],
  1957. pstate->pixel_ext.roi_h[i], scaler_w, scaler_h,
  1958. src_w, src_h, rot, pre_down_ratio_x, pre_down_ratio_y);
  1959. return -EINVAL;
  1960. }
  1961. /*
  1962. * SSPP fetch , unpack output and QSEED3 input lines need
  1963. * to match for Y plane
  1964. */
  1965. if (i == 0 &&
  1966. (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  1967. BIT(SDE_DRM_DEINTERLACE)) &&
  1968. ((pstate->scaler3_cfg.src_height[i] != (src_h/2)) ||
  1969. (pstate->pixel_ext.roi_h[i] != (src_h/2)))) {
  1970. SDE_ERROR_PLANE(psde,
  1971. "de-interlace fail roi[%d] %d/%d, src %dx%d, src %dx%d\n",
  1972. i, pstate->pixel_ext.roi_w[i],
  1973. pstate->pixel_ext.roi_h[i],
  1974. pstate->scaler3_cfg.src_width[i],
  1975. pstate->scaler3_cfg.src_height[i],
  1976. src_w, src_h);
  1977. return -EINVAL;
  1978. }
  1979. }
  1980. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2;
  1981. return 0;
  1982. }
  1983. static inline bool _sde_plane_has_pre_downscale(struct sde_plane *psde)
  1984. {
  1985. return (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  1986. }
  1987. static int _sde_atomic_check_pre_downscale(struct sde_plane *psde,
  1988. struct sde_plane_state *pstate, struct sde_rect *dst,
  1989. u32 src_w, u32 src_h)
  1990. {
  1991. int ret = 0;
  1992. u32 min_ratio_numer, min_ratio_denom;
  1993. struct sde_hw_inline_pre_downscale_cfg *pd_cfg = &pstate->pre_down;
  1994. bool pd_x;
  1995. bool pd_y;
  1996. if (!_sde_plane_is_pre_downscale_enabled(pd_cfg))
  1997. return ret;
  1998. pd_x = pd_cfg->pre_downscale_x_0 > 1;
  1999. pd_y = pd_cfg->pre_downscale_y_0 > 1;
  2000. min_ratio_numer = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_num;
  2001. min_ratio_denom = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2002. if (pd_x && !_sde_plane_has_pre_downscale(psde)) {
  2003. SDE_ERROR_PLANE(psde,
  2004. "hw does not support pre-downscale X: 0x%x\n",
  2005. psde->features);
  2006. ret = -EINVAL;
  2007. } else if (pd_y && !(psde->features & BIT(SDE_SSPP_PREDOWNSCALE_Y))) {
  2008. SDE_ERROR_PLANE(psde,
  2009. "hw does not support pre-downscale Y: 0x%x\n",
  2010. psde->features);
  2011. ret = -EINVAL;
  2012. } else if (!min_ratio_numer || !min_ratio_denom) {
  2013. SDE_ERROR_PLANE(psde,
  2014. "min downscale ratio not set! %u / %u\n",
  2015. min_ratio_numer, min_ratio_denom);
  2016. ret = -EINVAL;
  2017. /* compare pre-rotated src w/h with post-rotated dst h/w resp. */
  2018. } else if (pd_x && (src_w < mult_frac(dst->h, min_ratio_numer,
  2019. min_ratio_denom))) {
  2020. SDE_ERROR_PLANE(psde,
  2021. "failed min downscale-x check %u->%u, %u/%u\n",
  2022. src_w, dst->h, min_ratio_numer, min_ratio_denom);
  2023. ret = -EINVAL;
  2024. } else if (pd_y && (src_h < mult_frac(dst->w, min_ratio_numer,
  2025. min_ratio_denom))) {
  2026. SDE_ERROR_PLANE(psde,
  2027. "failed min downscale-y check %u->%u, %u/%u\n",
  2028. src_h, dst->w, min_ratio_numer, min_ratio_denom);
  2029. ret = -EINVAL;
  2030. }
  2031. return ret;
  2032. }
  2033. static void _sde_plane_get_max_downscale_limits(struct sde_plane *psde,
  2034. struct sde_plane_state *pstate, bool rt_client, u32 dst_h,
  2035. u32 src_h, u32 *max_numer_w, u32 *max_denom_w,
  2036. u32 *max_numer_h, u32 *max_denom_h)
  2037. {
  2038. bool rotated, has_predown, default_scale;
  2039. const struct sde_sspp_sub_blks *sblk;
  2040. struct sde_hw_inline_pre_downscale_cfg *pd = NULL;
  2041. rotated = pstate->rotation & DRM_MODE_ROTATE_90;
  2042. sblk = psde->pipe_sblk;
  2043. *max_numer_w = sblk->maxdwnscale;
  2044. *max_denom_w = 1;
  2045. *max_numer_h = sblk->maxdwnscale;
  2046. *max_denom_h = 1;
  2047. has_predown = _sde_plane_has_pre_downscale(psde);
  2048. if (has_predown)
  2049. pd = &pstate->pre_down;
  2050. default_scale = psde->debugfs_default_scale ||
  2051. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  2052. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK);
  2053. /**
  2054. * Inline rotation has different max vertical downscaling limits since
  2055. * the source-width becomes the scaler's pre-downscaled source-height.
  2056. **/
  2057. if (rotated) {
  2058. if (pd != NULL && rt_client && has_predown) {
  2059. if (default_scale)
  2060. pd->pre_downscale_x_0 = (src_h >
  2061. mult_frac(dst_h, 11, 5)) ? 2 : 0;
  2062. *max_numer_h = pd->pre_downscale_x_0 ?
  2063. sblk->in_rot_maxdwnscale_rt_num :
  2064. sblk->in_rot_maxdwnscale_rt_nopd_num;
  2065. *max_denom_h = pd->pre_downscale_x_0 ?
  2066. sblk->in_rot_maxdwnscale_rt_denom :
  2067. sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2068. } else if (rt_client) {
  2069. *max_numer_h = sblk->in_rot_maxdwnscale_rt_num;
  2070. *max_denom_h = sblk->in_rot_maxdwnscale_rt_denom;
  2071. } else {
  2072. *max_numer_h = sblk->in_rot_maxdwnscale_nrt;
  2073. }
  2074. }
  2075. }
  2076. static int _sde_atomic_check_decimation_scaler(struct drm_plane_state *state,
  2077. struct sde_plane *psde, const struct sde_format *fmt,
  2078. struct sde_plane_state *pstate, struct sde_rect *src,
  2079. struct sde_rect *dst, u32 width, u32 height)
  2080. {
  2081. int ret = 0;
  2082. uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
  2083. uint32_t scaler_src_w, scaler_src_h;
  2084. uint32_t max_downscale_num_w, max_downscale_denom_w;
  2085. uint32_t max_downscale_num_h, max_downscale_denom_h;
  2086. uint32_t max_upscale, max_linewidth;
  2087. bool inline_rotation, rt_client;
  2088. struct drm_crtc *crtc;
  2089. struct drm_crtc_state *new_cstate;
  2090. const struct sde_sspp_sub_blks *sblk;
  2091. if (!state || !state->state || !state->crtc) {
  2092. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  2093. return -EINVAL;
  2094. }
  2095. deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  2096. deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  2097. src_deci_w = DECIMATED_DIMENSION(src->w, deci_w);
  2098. src_deci_h = DECIMATED_DIMENSION(src->h, deci_h);
  2099. /* with inline rotator, the source of the scaler is post-rotated */
  2100. inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90 ? true : false;
  2101. if (inline_rotation) {
  2102. scaler_src_w = src_deci_h;
  2103. scaler_src_h = src_deci_w;
  2104. } else {
  2105. scaler_src_w = src_deci_w;
  2106. scaler_src_h = src_deci_h;
  2107. }
  2108. sblk = psde->pipe_sblk;
  2109. max_upscale = sblk->maxupscale;
  2110. if (inline_rotation)
  2111. max_linewidth = sblk->in_rot_maxheight;
  2112. else if (scaler_src_w != state->crtc_w || scaler_src_h != state->crtc_h)
  2113. max_linewidth = sblk->scaling_linewidth;
  2114. else
  2115. max_linewidth = sblk->maxlinewidth;
  2116. crtc = state->crtc;
  2117. new_cstate = drm_atomic_get_new_crtc_state(state->state, crtc);
  2118. rt_client = sde_crtc_is_rt_client(crtc, new_cstate);
  2119. _sde_plane_get_max_downscale_limits(psde, pstate, rt_client, dst->h,
  2120. scaler_src_h, &max_downscale_num_w, &max_downscale_denom_w,
  2121. &max_downscale_num_h, &max_downscale_denom_h);
  2122. /* decimation validation */
  2123. if ((deci_w || deci_h)
  2124. && ((deci_w > sblk->maxhdeciexp)
  2125. || (deci_h > sblk->maxvdeciexp))) {
  2126. SDE_ERROR_PLANE(psde, "too much decimation requested\n");
  2127. ret = -EINVAL;
  2128. } else if ((deci_w || deci_h)
  2129. && (fmt->fetch_mode != SDE_FETCH_LINEAR)) {
  2130. SDE_ERROR_PLANE(psde, "decimation requires linear fetch\n");
  2131. ret = -EINVAL;
  2132. } else if (!(psde->features & SDE_SSPP_SCALER) &&
  2133. ((src->w != dst->w) || (src->h != dst->h))) {
  2134. SDE_ERROR_PLANE(psde,
  2135. "pipe doesn't support scaling %ux%u->%ux%u\n",
  2136. src->w, src->h, dst->w, dst->h);
  2137. ret = -EINVAL;
  2138. /* check scaler source width */
  2139. } else if (scaler_src_w > max_linewidth) {
  2140. SDE_ERROR_PLANE(psde,
  2141. "invalid src w:%u, scaler w:%u, line w:%u, rot: %d\n",
  2142. src->w, scaler_src_w, max_linewidth, inline_rotation);
  2143. ret = -E2BIG;
  2144. /* check max scaler capability */
  2145. } else if (((scaler_src_w * max_upscale) < dst->w) ||
  2146. ((scaler_src_h * max_upscale) < dst->h) ||
  2147. (mult_frac(dst->w, max_downscale_num_w, max_downscale_denom_w)
  2148. < scaler_src_w) ||
  2149. (mult_frac(dst->h, max_downscale_num_h, max_downscale_denom_h)
  2150. < scaler_src_h)) {
  2151. SDE_ERROR_PLANE(psde,
  2152. "too much scaling %ux%u->%ux%u rot:%d dwn:%d/%d %d/%d\n",
  2153. scaler_src_w, scaler_src_h, dst->w, dst->h,
  2154. inline_rotation, max_downscale_num_w,
  2155. max_downscale_denom_w, max_downscale_num_h,
  2156. max_downscale_denom_h);
  2157. ret = -E2BIG;
  2158. /* check inline pre-downscale support */
  2159. } else if (inline_rotation && _sde_atomic_check_pre_downscale(psde,
  2160. pstate, dst, src_deci_w, src_deci_h)) {
  2161. ret = -EINVAL;
  2162. /* QSEED validation */
  2163. } else if (_sde_plane_validate_scaler_v2(psde, pstate, fmt,
  2164. width, height, src->w, src->h,
  2165. deci_w, deci_h)) {
  2166. ret = -EINVAL;
  2167. }
  2168. return ret;
  2169. }
  2170. static int _sde_atomic_check_excl_rect(struct sde_plane *psde,
  2171. struct sde_plane_state *pstate, struct sde_rect *src,
  2172. const struct sde_format *fmt, int ret)
  2173. {
  2174. /* check excl rect configs */
  2175. if (!ret && pstate->excl_rect.w && pstate->excl_rect.h) {
  2176. struct sde_rect intersect;
  2177. /*
  2178. * Check exclusion rect against src rect.
  2179. * it must intersect with source rect.
  2180. */
  2181. sde_kms_rect_intersect(src, &pstate->excl_rect, &intersect);
  2182. if (intersect.w != pstate->excl_rect.w ||
  2183. intersect.h != pstate->excl_rect.h ||
  2184. SDE_FORMAT_IS_YUV(fmt)) {
  2185. SDE_ERROR_PLANE(psde,
  2186. "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt: %4.4s\n",
  2187. pstate->excl_rect.x, pstate->excl_rect.y,
  2188. pstate->excl_rect.w, pstate->excl_rect.h,
  2189. src->x, src->y, src->w, src->h,
  2190. (char *)&fmt->base.pixel_format);
  2191. ret = -EINVAL;
  2192. }
  2193. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  2194. pstate->excl_rect.x, pstate->excl_rect.y,
  2195. pstate->excl_rect.w, pstate->excl_rect.h);
  2196. }
  2197. return ret;
  2198. }
  2199. static int _sde_plane_validate_shared_crtc(struct sde_plane *psde,
  2200. struct drm_plane_state *state)
  2201. {
  2202. struct sde_kms *sde_kms;
  2203. struct sde_splash_display *splash_display;
  2204. int i;
  2205. sde_kms = _sde_plane_get_kms(&psde->base);
  2206. if (!sde_kms || !state->crtc)
  2207. return 0;
  2208. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2209. splash_display = &sde_kms->splash_data.splash_display[i];
  2210. if (splash_display && splash_display->cont_splash_enabled &&
  2211. splash_display->encoder &&
  2212. state->crtc != splash_display->encoder->crtc) {
  2213. struct sde_sspp_index_info *pipe_info = &splash_display->pipe_info;
  2214. if (test_bit(psde->pipe, pipe_info->pipes) ||
  2215. test_bit(psde->pipe, pipe_info->virt_pipes)) {
  2216. SDE_ERROR_PLANE(psde, "pipe:%d used in cont-splash on crtc:%d\n",
  2217. psde->pipe,
  2218. splash_display->encoder->crtc->base.id);
  2219. return -EINVAL;
  2220. }
  2221. }
  2222. }
  2223. return 0;
  2224. }
  2225. static int _sde_plane_sspp_atomic_check_helper(struct sde_plane *psde,
  2226. const struct sde_format *fmt,
  2227. struct sde_rect src, struct sde_rect dst,
  2228. u32 width, u32 height)
  2229. {
  2230. int ret = 0;
  2231. u32 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
  2232. if (SDE_FORMAT_IS_YUV(fmt) &&
  2233. (!(psde->features & SDE_SSPP_SCALER) ||
  2234. !(psde->features & (BIT(SDE_SSPP_CSC)
  2235. | BIT(SDE_SSPP_CSC_10BIT))))) {
  2236. SDE_ERROR_PLANE(psde,
  2237. "plane doesn't have scaler/csc for yuv\n");
  2238. ret = -EINVAL;
  2239. /* check src bounds */
  2240. } else if (width > MAX_IMG_WIDTH || height > MAX_IMG_HEIGHT ||
  2241. src.w < min_src_size || src.h < min_src_size ||
  2242. CHECK_LAYER_BOUNDS(src.x, src.w, width) ||
  2243. CHECK_LAYER_BOUNDS(src.y, src.h, height)) {
  2244. SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
  2245. src.x, src.y, src.w, src.h);
  2246. ret = -E2BIG;
  2247. /* valid yuv image */
  2248. } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
  2249. (src.w & 0x1) || (src.h & 0x1))) {
  2250. SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
  2251. src.x, src.y, src.w, src.h);
  2252. ret = -EINVAL;
  2253. /* min dst support */
  2254. } else if (dst.w < 0x1 || dst.h < 0x1) {
  2255. SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
  2256. dst.x, dst.y, dst.w, dst.h);
  2257. ret = -EINVAL;
  2258. } else if (SDE_FORMAT_IS_UBWC(fmt) &&
  2259. !psde->catalog->ubwc_rev) {
  2260. SDE_ERROR_PLANE(psde, "ubwc not supported\n");
  2261. ret = -EINVAL;
  2262. }
  2263. return ret;
  2264. }
  2265. static int sde_plane_sspp_atomic_check(struct drm_plane *plane,
  2266. struct drm_plane_state *state)
  2267. {
  2268. int ret = 0;
  2269. struct sde_plane *psde;
  2270. struct sde_plane_state *pstate;
  2271. const struct msm_format *msm_fmt;
  2272. const struct sde_format *fmt;
  2273. struct sde_rect src, dst;
  2274. bool q16_data = true;
  2275. struct drm_framebuffer *fb;
  2276. u32 width;
  2277. u32 height;
  2278. psde = to_sde_plane(plane);
  2279. pstate = to_sde_plane_state(state);
  2280. if (!psde->pipe_sblk) {
  2281. SDE_ERROR_PLANE(psde, "invalid catalog\n");
  2282. return -EINVAL;
  2283. }
  2284. /* src values are in Q16 fixed point, convert to integer */
  2285. POPULATE_RECT(&src, state->src_x, state->src_y,
  2286. state->src_w, state->src_h, q16_data);
  2287. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
  2288. state->crtc_h, !q16_data);
  2289. SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
  2290. sde_plane_enabled(plane->state), sde_plane_enabled(state));
  2291. if (!sde_plane_enabled(state))
  2292. goto modeset_update;
  2293. fb = state->fb;
  2294. width = fb ? state->fb->width : 0x0;
  2295. height = fb ? state->fb->height : 0x0;
  2296. SDE_DEBUG("plane%d sspp:%x/%dx%d/%4.4s/%llx\n",
  2297. plane->base.id,
  2298. pstate->rotation,
  2299. width, height,
  2300. fb ? (char *) &state->fb->format->format : 0x0,
  2301. fb ? state->fb->modifier : 0x0);
  2302. SDE_DEBUG("src:%dx%d %d,%d crtc:%dx%d+%d+%d\n",
  2303. state->src_w >> 16, state->src_h >> 16,
  2304. state->src_x >> 16, state->src_y >> 16,
  2305. state->crtc_w, state->crtc_h,
  2306. state->crtc_x, state->crtc_y);
  2307. msm_fmt = msm_framebuffer_format(fb);
  2308. fmt = to_sde_format(msm_fmt);
  2309. ret = _sde_plane_sspp_atomic_check_helper(psde, fmt, src, dst, width,
  2310. height);
  2311. if (ret)
  2312. return ret;
  2313. ret = _sde_atomic_check_decimation_scaler(state, psde, fmt, pstate,
  2314. &src, &dst, width, height);
  2315. if (ret)
  2316. return ret;
  2317. ret = _sde_atomic_check_excl_rect(psde, pstate,
  2318. &src, fmt, ret);
  2319. if (ret)
  2320. return ret;
  2321. ret = _sde_plane_validate_shared_crtc(psde, state);
  2322. if (ret)
  2323. return ret;
  2324. pstate->const_alpha_en = fmt->alpha_enable &&
  2325. (SDE_DRM_BLEND_OP_OPAQUE !=
  2326. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP)) &&
  2327. (pstate->stage != SDE_STAGE_0);
  2328. modeset_update:
  2329. if (!ret)
  2330. _sde_plane_sspp_atomic_check_mode_changed(psde,
  2331. state, plane->state);
  2332. return ret;
  2333. }
  2334. static int _sde_plane_atomic_check(struct drm_plane *plane,
  2335. struct drm_plane_state *state)
  2336. {
  2337. int ret = 0;
  2338. struct sde_plane *psde;
  2339. struct sde_plane_state *pstate;
  2340. psde = to_sde_plane(plane);
  2341. pstate = to_sde_plane_state(state);
  2342. SDE_DEBUG_PLANE(psde, "\n");
  2343. ret = sde_plane_rot_atomic_check(plane, state);
  2344. if (ret)
  2345. goto exit;
  2346. ret = sde_plane_sspp_atomic_check(plane, state);
  2347. exit:
  2348. return ret;
  2349. }
  2350. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2351. static int sde_plane_atomic_check(struct drm_plane *plane,
  2352. struct drm_atomic_state *atomic_state)
  2353. {
  2354. struct drm_plane_state *state = NULL;
  2355. if (!plane || !atomic_state) {
  2356. SDE_ERROR("invalid arg(s), plane %d atomic_state %d\n",
  2357. !plane, !atomic_state);
  2358. return -EINVAL;
  2359. }
  2360. state = drm_atomic_get_new_plane_state(atomic_state, plane);
  2361. return _sde_plane_atomic_check(plane, state);
  2362. }
  2363. #else
  2364. static int sde_plane_atomic_check(struct drm_plane *plane,
  2365. struct drm_plane_state *state)
  2366. {
  2367. if (!plane || !state) {
  2368. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  2369. !plane, !state);
  2370. return -EINVAL;
  2371. }
  2372. return _sde_plane_atomic_check(plane, state);
  2373. }
  2374. #endif
  2375. void sde_plane_flush(struct drm_plane *plane)
  2376. {
  2377. struct sde_plane *psde;
  2378. struct sde_plane_state *pstate;
  2379. if (!plane || !plane->state) {
  2380. SDE_ERROR("invalid plane\n");
  2381. return;
  2382. }
  2383. psde = to_sde_plane(plane);
  2384. pstate = to_sde_plane_state(plane->state);
  2385. /*
  2386. * These updates have to be done immediately before the plane flush
  2387. * timing, and may not be moved to the atomic_update/mode_set functions.
  2388. */
  2389. if (psde->is_error)
  2390. /* force white frame with 100% alpha pipe output on error */
  2391. _sde_plane_color_fill(psde, 0xFFFFFF, 0xFF);
  2392. else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
  2393. /* force 100% alpha */
  2394. _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
  2395. else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
  2396. psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
  2397. /* flag h/w flush complete */
  2398. if (plane->state)
  2399. pstate->pending = false;
  2400. }
  2401. /**
  2402. * sde_plane_set_error: enable/disable error condition
  2403. * @plane: pointer to drm_plane structure
  2404. */
  2405. void sde_plane_set_error(struct drm_plane *plane, bool error)
  2406. {
  2407. struct sde_plane *psde;
  2408. if (!plane)
  2409. return;
  2410. psde = to_sde_plane(plane);
  2411. psde->is_error = error;
  2412. }
  2413. static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,
  2414. struct sde_plane_state *pstate)
  2415. {
  2416. struct drm_plane_state *state = psde->base.state;
  2417. struct sde_sc_cfg *sc_cfg = psde->catalog->sc_cfg;
  2418. struct sde_hw_pipe_sc_cfg *cfg = &pstate->sc_cfg;
  2419. bool prev_rd_en = cfg->rd_en;
  2420. u32 fb_cache_flag, fb_cache_type;
  2421. msm_framebuffer_get_cache_hint(state->fb, &fb_cache_flag, &fb_cache_type);
  2422. cfg->rd_en = false;
  2423. cfg->rd_scid = 0x0;
  2424. cfg->flags = SYS_CACHE_EN_FLAG | SYS_CACHE_SCID;
  2425. cfg->type = SDE_SYS_CACHE_NONE;
  2426. if ((sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache)
  2427. && ((pstate->static_cache_state == CACHE_STATE_FRAME_WRITE)
  2428. || (pstate->static_cache_state == CACHE_STATE_FRAME_READ))) {
  2429. cfg->rd_en = true;
  2430. cfg->rd_scid = sc_cfg[SDE_SYS_CACHE_DISP].llcc_scid;
  2431. cfg->rd_noallocate = (pstate->static_cache_state == CACHE_STATE_FRAME_READ);
  2432. cfg->flags |= SYS_CACHE_NO_ALLOC;
  2433. cfg->type = SDE_SYS_CACHE_DISP;
  2434. } else if ((sc_cfg[fb_cache_type].has_sys_cache)
  2435. && (fb_cache_flag & MSM_FB_CACHE_WRITE_EN)) {
  2436. cfg->rd_en = true;
  2437. cfg->rd_scid = sc_cfg[fb_cache_type].llcc_scid;
  2438. cfg->rd_noallocate = true;
  2439. cfg->flags |= SYS_CACHE_NO_ALLOC;
  2440. cfg->type = fb_cache_type;
  2441. msm_framebuffer_set_cache_hint(state->fb, MSM_FB_CACHE_READ_EN, fb_cache_type);
  2442. }
  2443. if (!cfg->rd_en && !prev_rd_en)
  2444. return;
  2445. SDE_EVT32(DRMID(&psde->base), cfg->rd_scid, cfg->rd_en, cfg->rd_noallocate, cfg->flags,
  2446. fb_cache_flag, fb_cache_type);
  2447. psde->pipe_hw->ops.setup_sys_cache(psde->pipe_hw, cfg);
  2448. }
  2449. void sde_plane_static_img_control(struct drm_plane *plane,
  2450. enum sde_sys_cache_state state)
  2451. {
  2452. struct sde_plane *psde;
  2453. struct sde_plane_state *pstate;
  2454. if (!plane || !plane->state) {
  2455. SDE_ERROR("invalid plane\n");
  2456. return;
  2457. }
  2458. psde = to_sde_plane(plane);
  2459. pstate = to_sde_plane_state(plane->state);
  2460. pstate->static_cache_state = state;
  2461. if (state == CACHE_STATE_FRAME_WRITE || state == CACHE_STATE_FRAME_READ)
  2462. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2463. }
  2464. static void _sde_plane_map_prop_to_dirty_bits(void)
  2465. {
  2466. plane_prop_array[PLANE_PROP_SCALER_V1] =
  2467. plane_prop_array[PLANE_PROP_SCALER_V2] =
  2468. plane_prop_array[PLANE_PROP_SCALER_LUT_ED] =
  2469. plane_prop_array[PLANE_PROP_SCALER_LUT_CIR] =
  2470. plane_prop_array[PLANE_PROP_SCALER_LUT_SEP] =
  2471. plane_prop_array[PLANE_PROP_H_DECIMATE] =
  2472. plane_prop_array[PLANE_PROP_V_DECIMATE] =
  2473. plane_prop_array[PLANE_PROP_SRC_CONFIG] =
  2474. plane_prop_array[PLANE_PROP_ZPOS] =
  2475. plane_prop_array[PLANE_PROP_EXCL_RECT_V1] =
  2476. plane_prop_array[PLANE_PROP_UBWC_STATS_ROI] =
  2477. SDE_PLANE_DIRTY_RECTS;
  2478. plane_prop_array[PLANE_PROP_CSC_V1] =
  2479. plane_prop_array[PLANE_PROP_CSC_DMA_V1] =
  2480. plane_prop_array[PLANE_PROP_INVERSE_PMA] =
  2481. SDE_PLANE_DIRTY_FORMAT;
  2482. plane_prop_array[PLANE_PROP_MULTIRECT_MODE] =
  2483. plane_prop_array[PLANE_PROP_COLOR_FILL] =
  2484. SDE_PLANE_DIRTY_ALL;
  2485. /* no special action required */
  2486. plane_prop_array[PLANE_PROP_INFO] =
  2487. plane_prop_array[PLANE_PROP_ALPHA] =
  2488. plane_prop_array[PLANE_PROP_INPUT_FENCE] =
  2489. plane_prop_array[PLANE_PROP_BLEND_OP] = 0;
  2490. plane_prop_array[PLANE_PROP_FB_TRANSLATION_MODE] =
  2491. SDE_PLANE_DIRTY_FB_TRANSLATION_MODE;
  2492. plane_prop_array[PLANE_PROP_PREFILL_SIZE] =
  2493. plane_prop_array[PLANE_PROP_PREFILL_TIME] =
  2494. SDE_PLANE_DIRTY_PERF;
  2495. plane_prop_array[PLANE_PROP_VIG_GAMUT] = SDE_PLANE_DIRTY_VIG_GAMUT;
  2496. plane_prop_array[PLANE_PROP_VIG_IGC] = SDE_PLANE_DIRTY_VIG_IGC;
  2497. plane_prop_array[PLANE_PROP_DMA_IGC] = SDE_PLANE_DIRTY_DMA_IGC;
  2498. plane_prop_array[PLANE_PROP_DMA_GC] = SDE_PLANE_DIRTY_DMA_GC;
  2499. plane_prop_array[PLANE_PROP_SKIN_COLOR] =
  2500. plane_prop_array[PLANE_PROP_SKY_COLOR] =
  2501. plane_prop_array[PLANE_PROP_FOLIAGE_COLOR] =
  2502. plane_prop_array[PLANE_PROP_HUE_ADJUST] =
  2503. plane_prop_array[PLANE_PROP_SATURATION_ADJUST] =
  2504. plane_prop_array[PLANE_PROP_VALUE_ADJUST] =
  2505. plane_prop_array[PLANE_PROP_CONTRAST_ADJUST] =
  2506. SDE_PLANE_DIRTY_ALL;
  2507. plane_prop_array[PLANE_PROP_FP16_IGC] = SDE_PLANE_DIRTY_FP16_IGC;
  2508. plane_prop_array[PLANE_PROP_FP16_GC] = SDE_PLANE_DIRTY_FP16_GC;
  2509. plane_prop_array[PLANE_PROP_FP16_CSC] = SDE_PLANE_DIRTY_FP16_CSC;
  2510. plane_prop_array[PLANE_PROP_FP16_UNMULT] = SDE_PLANE_DIRTY_FP16_UNMULT;
  2511. }
  2512. static inline bool _sde_plane_allow_uidle(struct sde_plane *psde,
  2513. struct sde_rect *src, struct sde_rect *dst)
  2514. {
  2515. u32 max_downscale = psde->catalog->uidle_cfg.max_dwnscale;
  2516. u32 downscale = (src->h * 1000)/dst->h;
  2517. return (downscale > max_downscale) ? false : true;
  2518. }
  2519. static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
  2520. struct sde_plane *psde, struct sde_plane_state *pstate,
  2521. struct sde_rect *src, struct sde_rect *dst)
  2522. {
  2523. struct sde_hw_pipe_uidle_cfg cfg;
  2524. u32 line_time = sde_crtc_get_line_time(crtc);
  2525. u32 fal1_target_idle_time_ns =
  2526. psde->catalog->uidle_cfg.fal1_target_idle_time * 1000; /* nS */
  2527. u32 fal10_target_idle_time_ns =
  2528. psde->catalog->uidle_cfg.fal10_target_idle_time * 1000; /* nS */
  2529. u32 fal10_threshold =
  2530. psde->catalog->uidle_cfg.fal10_threshold; /* uS */
  2531. if (line_time && fal10_threshold && fal10_target_idle_time_ns &&
  2532. fal1_target_idle_time_ns) {
  2533. cfg.enable = _sde_plane_allow_uidle(psde, src, dst);
  2534. cfg.fal10_threshold = fal10_threshold;
  2535. cfg.fal10_exit_threshold = fal10_threshold + 2;
  2536. cfg.fal1_threshold = min(1 +
  2537. (fal1_target_idle_time_ns*1000/line_time*2)/1000,
  2538. psde->catalog->uidle_cfg.fal1_max_threshold);
  2539. cfg.fal_allowed_threshold = fal10_threshold +
  2540. (fal10_target_idle_time_ns*1000/line_time*2)/1000;
  2541. cfg.fill_level_scale = 0;
  2542. /*
  2543. * if uidle fill scale is supported, determing the scale value
  2544. * and adjust fal10 thresholds to their scaled values.
  2545. * fal1 thresholds and fal_allowed are not scaled.
  2546. */
  2547. if (psde->pipe_hw->ops.setup_uidle_fill_scale) {
  2548. u32 fl_require0 = psde->catalog->qos_target_time_ns / line_time * 2;
  2549. u32 fl_require = max(fal10_threshold * 1000, fl_require0);
  2550. u32 fl_scale = fl_require / fal10_threshold;
  2551. u32 fal10_threshold_noscale;
  2552. cfg.fill_level_scale = (fl_scale <= 1) ? 0 : (32 / fl_scale);
  2553. if (cfg.fill_level_scale) {
  2554. fal10_threshold_noscale = fal10_threshold *
  2555. 32/cfg.fill_level_scale;
  2556. cfg.fal_allowed_threshold = fal10_threshold_noscale +
  2557. (fal10_target_idle_time_ns * 1000 / line_time * 2) / 1000;
  2558. }
  2559. }
  2560. } else {
  2561. SDE_ERROR("invalid settings, will disable UIDLE %d %d %d %d\n",
  2562. line_time, fal10_threshold, fal10_target_idle_time_ns,
  2563. fal1_target_idle_time_ns);
  2564. memset(&cfg, 0, sizeof(struct sde_hw_pipe_uidle_cfg));
  2565. }
  2566. SDE_DEBUG_PLANE(psde,
  2567. "tholds: fal10=%d fal10_exit=%d fal1=%d fal_allowed=%d fill_scale=%d\n",
  2568. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2569. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2570. cfg.fill_level_scale);
  2571. SDE_DEBUG_PLANE(psde,
  2572. "times: line:%d fal1_idle:%d fal10_idle:%d dwnscale:%d\n",
  2573. line_time, fal1_target_idle_time_ns,
  2574. fal10_target_idle_time_ns,
  2575. psde->catalog->uidle_cfg.max_dwnscale);
  2576. SDE_EVT32_VERBOSE(cfg.enable,
  2577. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2578. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2579. cfg.fill_level_scale, psde->catalog->uidle_cfg.max_dwnscale);
  2580. if (psde->pipe_hw->ops.setup_uidle_fill_scale)
  2581. psde->pipe_hw->ops.setup_uidle_fill_scale(psde->pipe_hw, &cfg);
  2582. psde->pipe_hw->ops.setup_uidle(
  2583. psde->pipe_hw, &cfg,
  2584. pstate->multirect_index);
  2585. }
  2586. static void _sde_plane_update_secure_session(struct sde_plane *psde,
  2587. struct sde_plane_state *pstate)
  2588. {
  2589. bool enable = false;
  2590. int mode = sde_plane_get_property(pstate,
  2591. PLANE_PROP_FB_TRANSLATION_MODE);
  2592. if ((mode == SDE_DRM_FB_SEC) ||
  2593. (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  2594. enable = true;
  2595. /* update secure session flag */
  2596. psde->pipe_hw->ops.setup_secure_address(psde->pipe_hw,
  2597. pstate->multirect_index,
  2598. enable);
  2599. }
  2600. static void _sde_plane_update_roi_config(struct drm_plane *plane,
  2601. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2602. {
  2603. const struct sde_format *fmt;
  2604. const struct msm_format *msm_fmt;
  2605. struct sde_plane *psde;
  2606. struct drm_plane_state *state;
  2607. struct sde_plane_state *pstate;
  2608. struct sde_rect src, dst;
  2609. const struct sde_rect *crtc_roi;
  2610. bool q16_data = true;
  2611. int idx;
  2612. psde = to_sde_plane(plane);
  2613. state = plane->state;
  2614. pstate = to_sde_plane_state(state);
  2615. msm_fmt = msm_framebuffer_format(fb);
  2616. if (!msm_fmt) {
  2617. SDE_ERROR("crtc%d plane%d: null format\n",
  2618. DRMID(crtc), DRMID(plane));
  2619. return;
  2620. }
  2621. fmt = to_sde_format(msm_fmt);
  2622. POPULATE_RECT(&src, state->src_x, state->src_y,
  2623. state->src_w, state->src_h, q16_data);
  2624. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
  2625. state->crtc_w, state->crtc_h, !q16_data);
  2626. SDE_DEBUG_PLANE(psde,
  2627. "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
  2628. fb->base.id, src.x, src.y, src.w, src.h,
  2629. crtc->base.id, dst.x, dst.y, dst.w, dst.h,
  2630. (char *)&fmt->base.pixel_format,
  2631. SDE_FORMAT_IS_UBWC(fmt));
  2632. if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2633. BIT(SDE_DRM_DEINTERLACE)) {
  2634. SDE_DEBUG_PLANE(psde, "deinterlace\n");
  2635. for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
  2636. psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
  2637. src.h /= 2;
  2638. src.y = DIV_ROUND_UP(src.y, 2);
  2639. src.y &= ~0x1;
  2640. }
  2641. /*
  2642. * adjust layer mixer position of the sspp in the presence
  2643. * of a partial update to the active lm origin
  2644. */
  2645. sde_crtc_get_crtc_roi(crtc->state, &crtc_roi);
  2646. dst.x -= crtc_roi->x;
  2647. dst.y -= crtc_roi->y;
  2648. /* check for UIDLE */
  2649. if (psde->pipe_hw->ops.setup_uidle)
  2650. _sde_plane_setup_uidle(crtc, psde, pstate, &src, &dst);
  2651. psde->pipe_cfg.src_rect = src;
  2652. psde->pipe_cfg.dst_rect = dst;
  2653. _sde_plane_setup_scaler(psde, pstate, fmt, false);
  2654. /* check for color fill */
  2655. psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
  2656. PLANE_PROP_COLOR_FILL);
  2657. if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
  2658. /* skip remaining processing on color fill */
  2659. pstate->dirty = 0x0;
  2660. } else if (psde->pipe_hw->ops.setup_rects) {
  2661. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  2662. &psde->pipe_cfg,
  2663. pstate->multirect_index);
  2664. }
  2665. if (psde->pipe_hw->ops.setup_pe &&
  2666. (pstate->multirect_index != SDE_SSPP_RECT_1))
  2667. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  2668. &psde->pixel_ext);
  2669. /**
  2670. * when programmed in multirect mode, scalar block will be
  2671. * bypassed. Still we need to update alpha and bitwidth
  2672. * ONLY for RECT0
  2673. */
  2674. if (psde->pipe_hw->ops.setup_scaler &&
  2675. pstate->multirect_index != SDE_SSPP_RECT_1) {
  2676. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  2677. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  2678. &psde->pipe_cfg, &psde->pixel_ext,
  2679. &psde->scaler3_cfg);
  2680. }
  2681. /* update excl rect */
  2682. if (psde->pipe_hw->ops.setup_excl_rect)
  2683. psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
  2684. &pstate->excl_rect,
  2685. pstate->multirect_index);
  2686. /* enable multirect config of corresponding rect */
  2687. if (psde->pipe_hw->ops.update_multirect)
  2688. psde->pipe_hw->ops.update_multirect(
  2689. psde->pipe_hw,
  2690. true,
  2691. pstate->multirect_index,
  2692. pstate->multirect_mode);
  2693. }
  2694. static void _sde_plane_update_format_and_rects(struct sde_plane *psde,
  2695. struct sde_plane_state *pstate, const struct sde_format *fmt)
  2696. {
  2697. uint32_t src_flags = 0;
  2698. SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", pstate->rotation);
  2699. if (pstate->rotation & DRM_MODE_REFLECT_X)
  2700. src_flags |= SDE_SSPP_FLIP_LR;
  2701. if (pstate->rotation & DRM_MODE_REFLECT_Y)
  2702. src_flags |= SDE_SSPP_FLIP_UD;
  2703. if (pstate->rotation & DRM_MODE_ROTATE_90)
  2704. src_flags |= SDE_SSPP_ROT_90;
  2705. /* update format */
  2706. psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt,
  2707. pstate->const_alpha_en, src_flags,
  2708. pstate->multirect_index);
  2709. if (psde->pipe_hw->ops.setup_cdp) {
  2710. struct sde_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
  2711. memset(cdp_cfg, 0, sizeof(struct sde_hw_pipe_cdp_cfg));
  2712. cdp_cfg->enable = psde->catalog->perf.cdp_cfg
  2713. [SDE_PERF_CDP_USAGE_RT].rd_enable;
  2714. cdp_cfg->ubwc_meta_enable =
  2715. SDE_FORMAT_IS_UBWC(fmt);
  2716. cdp_cfg->tile_amortize_enable =
  2717. SDE_FORMAT_IS_UBWC(fmt) ||
  2718. SDE_FORMAT_IS_TILE(fmt);
  2719. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  2720. psde->pipe_hw->ops.setup_cdp(psde->pipe_hw, cdp_cfg,
  2721. pstate->multirect_index);
  2722. }
  2723. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2724. /* update csc */
  2725. if (SDE_FORMAT_IS_YUV(fmt))
  2726. _sde_plane_setup_csc(psde);
  2727. else
  2728. psde->csc_ptr = 0;
  2729. if (psde->pipe_hw->ops.setup_inverse_pma) {
  2730. uint32_t pma_mode = 0;
  2731. if (fmt->alpha_enable)
  2732. pma_mode = (uint32_t) sde_plane_get_property(
  2733. pstate, PLANE_PROP_INVERSE_PMA);
  2734. psde->pipe_hw->ops.setup_inverse_pma(psde->pipe_hw,
  2735. pstate->multirect_index, pma_mode);
  2736. }
  2737. if (psde->pipe_hw->ops.setup_dgm_csc)
  2738. psde->pipe_hw->ops.setup_dgm_csc(psde->pipe_hw,
  2739. pstate->multirect_index, psde->csc_usr_ptr);
  2740. if (psde->pipe_hw->ops.set_ubwc_stats_roi) {
  2741. if (SDE_FORMAT_IS_UBWC(fmt) && !SDE_FORMAT_IS_YUV(fmt))
  2742. psde->pipe_hw->ops.set_ubwc_stats_roi(psde->pipe_hw,
  2743. pstate->multirect_index, &pstate->ubwc_stats_roi);
  2744. else
  2745. psde->pipe_hw->ops.set_ubwc_stats_roi(psde->pipe_hw,
  2746. pstate->multirect_index, NULL);
  2747. }
  2748. }
  2749. static void _sde_plane_update_sharpening(struct sde_plane *psde)
  2750. {
  2751. psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
  2752. psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
  2753. psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
  2754. psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
  2755. psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
  2756. &psde->sharp_cfg);
  2757. }
  2758. static void _sde_plane_update_properties(struct drm_plane *plane,
  2759. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2760. {
  2761. uint32_t nplanes;
  2762. const struct msm_format *msm_fmt;
  2763. const struct sde_format *fmt;
  2764. struct sde_plane *psde;
  2765. struct drm_plane_state *state;
  2766. struct sde_plane_state *pstate;
  2767. psde = to_sde_plane(plane);
  2768. state = plane->state;
  2769. pstate = to_sde_plane_state(state);
  2770. if (!pstate) {
  2771. SDE_ERROR("invalid plane state for plane%d\n", DRMID(plane));
  2772. return;
  2773. }
  2774. msm_fmt = msm_framebuffer_format(fb);
  2775. if (!msm_fmt) {
  2776. SDE_ERROR("crtc%d plane%d: null format\n",
  2777. DRMID(crtc), DRMID(plane));
  2778. return;
  2779. }
  2780. fmt = to_sde_format(msm_fmt);
  2781. nplanes = fmt->num_planes;
  2782. /* update secure session flag */
  2783. if (pstate->dirty & SDE_PLANE_DIRTY_FB_TRANSLATION_MODE)
  2784. _sde_plane_update_secure_session(psde, pstate);
  2785. /* update roi config */
  2786. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2787. _sde_plane_update_roi_config(plane, crtc, fb);
  2788. if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT ||
  2789. pstate->dirty & SDE_PLANE_DIRTY_RECTS) &&
  2790. psde->pipe_hw->ops.setup_format)
  2791. _sde_plane_update_format_and_rects(psde, pstate, fmt);
  2792. sde_color_process_plane_setup(plane);
  2793. /* update sharpening */
  2794. if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
  2795. psde->pipe_hw->ops.setup_sharpening)
  2796. _sde_plane_update_sharpening(psde);
  2797. if (pstate->dirty & (SDE_PLANE_DIRTY_QOS | SDE_PLANE_DIRTY_RECTS |
  2798. SDE_PLANE_DIRTY_FORMAT))
  2799. _sde_plane_set_qos_lut(plane, crtc, fb);
  2800. _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
  2801. _sde_plane_set_ot_limit(plane, crtc);
  2802. if (pstate->dirty & SDE_PLANE_DIRTY_PERF)
  2803. _sde_plane_set_ts_prefill(plane, pstate);
  2804. if (pstate->dirty & SDE_PLANE_DIRTY_QOS)
  2805. _sde_plane_set_qos_remap(plane);
  2806. /* clear dirty */
  2807. pstate->dirty = 0x0;
  2808. }
  2809. static void _sde_plane_check_lut_dirty(struct sde_plane *psde,
  2810. struct sde_plane_state *pstate)
  2811. {
  2812. /**
  2813. * Valid configuration if scaler is not enabled or
  2814. * lut flag is set
  2815. */
  2816. if (pstate->scaler3_cfg.lut_flag || !pstate->scaler3_cfg.enable)
  2817. return;
  2818. pstate->scaler3_cfg.lut_flag = psde->cached_lut_flag;
  2819. SDE_EVT32(DRMID(&psde->base), pstate->scaler3_cfg.lut_flag, SDE_EVTLOG_ERROR);
  2820. }
  2821. static int sde_plane_sspp_atomic_update(struct drm_plane *plane,
  2822. struct drm_plane_state *old_state)
  2823. {
  2824. struct sde_plane *psde;
  2825. struct drm_plane_state *state;
  2826. struct sde_plane_state *pstate;
  2827. struct sde_plane_state *old_pstate;
  2828. struct drm_crtc *crtc;
  2829. struct drm_framebuffer *fb;
  2830. int idx;
  2831. int dirty_prop_flag;
  2832. bool is_rt;
  2833. if (!plane) {
  2834. SDE_ERROR("invalid plane\n");
  2835. return -EINVAL;
  2836. } else if (!plane->state) {
  2837. SDE_ERROR("invalid plane state\n");
  2838. return -EINVAL;
  2839. } else if (!old_state) {
  2840. SDE_ERROR("invalid old state\n");
  2841. return -EINVAL;
  2842. }
  2843. psde = to_sde_plane(plane);
  2844. state = plane->state;
  2845. pstate = to_sde_plane_state(state);
  2846. old_pstate = to_sde_plane_state(old_state);
  2847. crtc = state->crtc;
  2848. fb = state->fb;
  2849. if (!crtc || !fb) {
  2850. SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
  2851. !crtc, !fb);
  2852. return -EINVAL;
  2853. }
  2854. SDE_DEBUG(
  2855. "plane%d sspp:%dx%d/%4.4s/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
  2856. plane->base.id,
  2857. state->fb->width, state->fb->height,
  2858. (char *) &state->fb->format->format,
  2859. state->fb->modifier,
  2860. state->src_w >> 16, state->src_h >> 16,
  2861. state->src_x >> 16, state->src_y >> 16,
  2862. pstate->rotation,
  2863. state->crtc_w, state->crtc_h,
  2864. state->crtc_x, state->crtc_y);
  2865. /* Caching the valid lut flag in sde plane */
  2866. if (pstate->scaler3_cfg.enable && pstate->scaler3_cfg.lut_flag)
  2867. psde->cached_lut_flag = pstate->scaler3_cfg.lut_flag;
  2868. /* force reprogramming of all the parameters, if the flag is set */
  2869. if (psde->revalidate) {
  2870. SDE_DEBUG("plane:%d - reconfigure all the parameters\n",
  2871. plane->base.id);
  2872. _sde_plane_check_lut_dirty(psde, pstate);
  2873. pstate->dirty = SDE_PLANE_DIRTY_ALL | SDE_PLANE_DIRTY_CP;
  2874. psde->revalidate = false;
  2875. }
  2876. /* determine what needs to be refreshed */
  2877. mutex_lock(&psde->property_info.property_lock);
  2878. while ((idx = msm_property_pop_dirty(&psde->property_info,
  2879. &pstate->property_state)) >= 0) {
  2880. dirty_prop_flag = plane_prop_array[idx];
  2881. pstate->dirty |= dirty_prop_flag;
  2882. }
  2883. mutex_unlock(&psde->property_info.property_lock);
  2884. /**
  2885. * since plane_atomic_check is invoked before crtc_atomic_check
  2886. * in the commit sequence, all the parameters for updating the
  2887. * plane dirty flag will not be available during
  2888. * plane_atomic_check as some features params are updated
  2889. * in crtc_atomic_check (eg.:sDMA). So check for mode_change
  2890. * before sspp update.
  2891. */
  2892. _sde_plane_sspp_atomic_check_mode_changed(psde, state,
  2893. old_state);
  2894. /* re-program the output rects always if partial update roi changed */
  2895. if (sde_crtc_is_crtc_roi_dirty(crtc->state))
  2896. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  2897. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2898. memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
  2899. _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
  2900. is_rt = sde_crtc_is_rt_client(crtc, crtc->state);
  2901. if (is_rt != psde->is_rt_pipe || crtc->state->mode_changed) {
  2902. psde->is_rt_pipe = is_rt;
  2903. psde->wb_usage_type = psde->is_rt_pipe ? 0 : sde_crtc_get_wb_usage_type(crtc);
  2904. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  2905. }
  2906. /* early out if nothing dirty */
  2907. if (!pstate->dirty)
  2908. return 0;
  2909. pstate->pending = true;
  2910. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  2911. _sde_plane_update_properties(plane, crtc, fb);
  2912. return 0;
  2913. }
  2914. static void _sde_plane_atomic_disable(struct drm_plane *plane,
  2915. struct drm_plane_state *old_state)
  2916. {
  2917. struct sde_plane *psde;
  2918. struct drm_plane_state *state;
  2919. struct sde_plane_state *pstate;
  2920. u32 multirect_index = SDE_SSPP_RECT_0;
  2921. struct sde_cp_crtc_skip_blend_plane skip_blend_plane;
  2922. u32 blend_type;
  2923. if (!plane) {
  2924. SDE_ERROR("invalid plane\n");
  2925. return;
  2926. } else if (!plane->state) {
  2927. SDE_ERROR("invalid plane state\n");
  2928. return;
  2929. } else if (!old_state) {
  2930. SDE_ERROR("invalid old state\n");
  2931. return;
  2932. }
  2933. psde = to_sde_plane(plane);
  2934. state = plane->state;
  2935. pstate = to_sde_plane_state(state);
  2936. blend_type = sde_plane_get_property(pstate,
  2937. PLANE_PROP_BLEND_OP);
  2938. /* some of the color features are dependent on plane with skip blend.
  2939. * if skip blend plane is being disabled, we need to disable color properties.
  2940. */
  2941. if (blend_type == SDE_DRM_BLEND_OP_SKIP && old_state->crtc) {
  2942. skip_blend_plane.valid_plane = false;
  2943. skip_blend_plane.plane = SSPP_NONE;
  2944. sde_cp_set_skip_blend_plane_info(old_state->crtc, &skip_blend_plane);
  2945. sde_crtc_disable_cp_features(old_state->crtc);
  2946. }
  2947. SDE_EVT32(DRMID(plane), is_sde_plane_virtual(plane),
  2948. pstate->multirect_mode);
  2949. pstate->pending = true;
  2950. if (is_sde_plane_virtual(plane))
  2951. multirect_index = SDE_SSPP_RECT_1;
  2952. /* disable multirect config of corresponding rect */
  2953. if (psde->pipe_hw && psde->pipe_hw->ops.update_multirect)
  2954. psde->pipe_hw->ops.update_multirect(psde->pipe_hw, false,
  2955. multirect_index, SDE_SSPP_MULTIRECT_TIME_MX);
  2956. }
  2957. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2958. static void _sde_plane_atomic_update(struct drm_plane *plane,
  2959. struct drm_plane_state *old_state)
  2960. #else
  2961. static void sde_plane_atomic_update(struct drm_plane *plane,
  2962. struct drm_plane_state *old_state)
  2963. #endif
  2964. {
  2965. struct sde_plane *psde;
  2966. struct drm_plane_state *state;
  2967. if (!plane) {
  2968. SDE_ERROR("invalid plane\n");
  2969. return;
  2970. } else if (!plane->state) {
  2971. SDE_ERROR("invalid plane state\n");
  2972. return;
  2973. }
  2974. psde = to_sde_plane(plane);
  2975. psde->is_error = false;
  2976. state = plane->state;
  2977. SDE_DEBUG_PLANE(psde, "\n");
  2978. if (!sde_plane_enabled(state)) {
  2979. _sde_plane_atomic_disable(plane, old_state);
  2980. } else {
  2981. int ret;
  2982. ret = sde_plane_sspp_atomic_update(plane, old_state);
  2983. /* atomic_check should have ensured that this doesn't fail */
  2984. WARN_ON(ret < 0);
  2985. }
  2986. }
  2987. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2988. static void sde_plane_atomic_update(struct drm_plane *plane,
  2989. struct drm_atomic_state *atomic_state)
  2990. {
  2991. struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(atomic_state, plane);
  2992. _sde_plane_atomic_update(plane, old_state);
  2993. }
  2994. #endif
  2995. void sde_plane_restore(struct drm_plane *plane)
  2996. {
  2997. struct sde_plane *psde;
  2998. if (!plane || !plane->state) {
  2999. SDE_ERROR("invalid plane\n");
  3000. return;
  3001. }
  3002. psde = to_sde_plane(plane);
  3003. /*
  3004. * Revalidate is only true here if idle PC occurred and
  3005. * there is no plane state update in current commit cycle.
  3006. */
  3007. if (!psde->revalidate)
  3008. return;
  3009. SDE_DEBUG_PLANE(psde, "\n");
  3010. /* last plane state is same as current state */
  3011. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3012. _sde_plane_atomic_update(plane, plane->state);
  3013. #else
  3014. sde_plane_atomic_update(plane, plane->state);
  3015. #endif
  3016. }
  3017. bool sde_plane_is_cache_required(struct drm_plane *plane,
  3018. enum sde_sys_cache_type type)
  3019. {
  3020. struct sde_plane_state *pstate;
  3021. if (!plane || !plane->state) {
  3022. SDE_ERROR("invalid plane\n");
  3023. return false;
  3024. }
  3025. pstate = to_sde_plane_state(plane->state);
  3026. /* check if llcc is required for the plane */
  3027. if (pstate->sc_cfg.rd_en && (pstate->sc_cfg.type == type))
  3028. return true;
  3029. else
  3030. return false;
  3031. }
  3032. static void _sde_plane_install_master_only_properties(struct sde_plane *psde)
  3033. {
  3034. char feature_name[256];
  3035. if (psde->pipe_sblk->maxhdeciexp) {
  3036. msm_property_install_range(&psde->property_info,
  3037. "h_decimate", 0x0, 0,
  3038. psde->pipe_sblk->maxhdeciexp, 0,
  3039. PLANE_PROP_H_DECIMATE);
  3040. }
  3041. if (psde->pipe_sblk->maxvdeciexp) {
  3042. msm_property_install_range(&psde->property_info,
  3043. "v_decimate", 0x0, 0,
  3044. psde->pipe_sblk->maxvdeciexp, 0,
  3045. PLANE_PROP_V_DECIMATE);
  3046. }
  3047. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  3048. msm_property_install_range(
  3049. &psde->property_info, "scaler_v2",
  3050. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  3051. msm_property_install_blob(&psde->property_info,
  3052. "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
  3053. msm_property_install_blob(&psde->property_info,
  3054. "lut_cir", 0,
  3055. PLANE_PROP_SCALER_LUT_CIR);
  3056. msm_property_install_blob(&psde->property_info,
  3057. "lut_sep", 0,
  3058. PLANE_PROP_SCALER_LUT_SEP);
  3059. } else if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  3060. msm_property_install_range(
  3061. &psde->property_info, "scaler_v2",
  3062. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  3063. msm_property_install_blob(&psde->property_info,
  3064. "lut_sep", 0,
  3065. PLANE_PROP_SCALER_LUT_SEP);
  3066. } else if (psde->features & SDE_SSPP_SCALER) {
  3067. msm_property_install_range(
  3068. &psde->property_info, "scaler_v1", 0x0,
  3069. 0, ~0, 0, PLANE_PROP_SCALER_V1);
  3070. }
  3071. if (psde->features & BIT(SDE_SSPP_CSC) ||
  3072. psde->features & BIT(SDE_SSPP_CSC_10BIT))
  3073. msm_property_install_volatile_range(
  3074. &psde->property_info, "csc_v1", 0x0,
  3075. 0, ~0, 0, PLANE_PROP_CSC_V1);
  3076. if (psde->features & BIT(SDE_SSPP_HSIC)) {
  3077. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3078. "SDE_SSPP_HUE_V",
  3079. psde->pipe_sblk->hsic_blk.version >> 16);
  3080. msm_property_install_range(&psde->property_info,
  3081. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3082. PLANE_PROP_HUE_ADJUST);
  3083. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3084. "SDE_SSPP_SATURATION_V",
  3085. psde->pipe_sblk->hsic_blk.version >> 16);
  3086. msm_property_install_range(&psde->property_info,
  3087. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3088. PLANE_PROP_SATURATION_ADJUST);
  3089. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3090. "SDE_SSPP_VALUE_V",
  3091. psde->pipe_sblk->hsic_blk.version >> 16);
  3092. msm_property_install_range(&psde->property_info,
  3093. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3094. PLANE_PROP_VALUE_ADJUST);
  3095. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3096. "SDE_SSPP_CONTRAST_V",
  3097. psde->pipe_sblk->hsic_blk.version >> 16);
  3098. msm_property_install_range(&psde->property_info,
  3099. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3100. PLANE_PROP_CONTRAST_ADJUST);
  3101. }
  3102. }
  3103. static void _sde_plane_install_colorproc_properties(struct sde_plane *psde,
  3104. struct sde_kms_info *info)
  3105. {
  3106. char feature_name[256];
  3107. bool is_master = !psde->is_virtual;
  3108. if ((is_master &&
  3109. (psde->features & BIT(SDE_SSPP_INVERSE_PMA))) ||
  3110. (psde->features & BIT(SDE_SSPP_DGM_INVERSE_PMA))) {
  3111. msm_property_install_range(&psde->property_info,
  3112. "inverse_pma", 0x0, 0, 1, 0, PLANE_PROP_INVERSE_PMA);
  3113. sde_kms_info_add_keyint(info, "inverse_pma", 1);
  3114. }
  3115. if (psde->features & BIT(SDE_SSPP_DGM_CSC)) {
  3116. msm_property_install_volatile_range(
  3117. &psde->property_info, "csc_dma_v1", 0x0,
  3118. 0, ~0, 0, PLANE_PROP_CSC_DMA_V1);
  3119. sde_kms_info_add_keyint(info, "csc_dma_v1", 1);
  3120. }
  3121. if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
  3122. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3123. "SDE_SSPP_SKIN_COLOR_V",
  3124. psde->pipe_sblk->memcolor_blk.version >> 16);
  3125. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3126. PLANE_PROP_SKIN_COLOR);
  3127. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3128. "SDE_SSPP_SKY_COLOR_V",
  3129. psde->pipe_sblk->memcolor_blk.version >> 16);
  3130. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3131. PLANE_PROP_SKY_COLOR);
  3132. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3133. "SDE_SSPP_FOLIAGE_COLOR_V",
  3134. psde->pipe_sblk->memcolor_blk.version >> 16);
  3135. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3136. PLANE_PROP_FOLIAGE_COLOR);
  3137. }
  3138. if (psde->features & BIT(SDE_SSPP_VIG_GAMUT)) {
  3139. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3140. "SDE_VIG_3D_LUT_GAMUT_V",
  3141. psde->pipe_sblk->gamut_blk.version >> 16);
  3142. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3143. PLANE_PROP_VIG_GAMUT);
  3144. }
  3145. if (psde->features & BIT(SDE_SSPP_VIG_IGC)) {
  3146. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3147. "SDE_VIG_1D_LUT_IGC_V",
  3148. psde->pipe_sblk->igc_blk[0].version >> 16);
  3149. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3150. PLANE_PROP_VIG_IGC);
  3151. }
  3152. if (psde->features & BIT(SDE_SSPP_DMA_IGC)) {
  3153. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3154. "SDE_DGM_1D_LUT_IGC_V",
  3155. psde->pipe_sblk->igc_blk[0].version >> 16);
  3156. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3157. PLANE_PROP_DMA_IGC);
  3158. }
  3159. if (psde->features & BIT(SDE_SSPP_DMA_GC)) {
  3160. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3161. "SDE_DGM_1D_LUT_GC_V",
  3162. psde->pipe_sblk->gc_blk[0].version >> 16);
  3163. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3164. PLANE_PROP_DMA_GC);
  3165. }
  3166. if (psde->features & BIT(SDE_SSPP_FP16_IGC)) {
  3167. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3168. "SDE_SSPP_FP16_IGC_V",
  3169. psde->pipe_sblk->fp16_igc_blk[0].version >> 16);
  3170. msm_property_install_range(&psde->property_info, feature_name,
  3171. 0x0, 0, 1, 0, PLANE_PROP_FP16_IGC);
  3172. }
  3173. if (psde->features & BIT(SDE_SSPP_FP16_GC)) {
  3174. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3175. "SDE_SSPP_FP16_GC_V",
  3176. psde->pipe_sblk->fp16_gc_blk[0].version >> 16);
  3177. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3178. PLANE_PROP_FP16_GC);
  3179. }
  3180. if (psde->features & BIT(SDE_SSPP_FP16_CSC)) {
  3181. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3182. "SDE_SSPP_FP16_CSC_V",
  3183. psde->pipe_sblk->fp16_csc_blk[0].version >> 16);
  3184. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3185. PLANE_PROP_FP16_CSC);
  3186. }
  3187. if (psde->features & BIT(SDE_SSPP_FP16_UNMULT)) {
  3188. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3189. "SDE_SSPP_FP16_UNMULT_V",
  3190. psde->pipe_sblk->fp16_unmult_blk[0].version >> 16);
  3191. msm_property_install_range(&psde->property_info, feature_name,
  3192. 0x0, 0, 1, 0, PLANE_PROP_FP16_UNMULT);
  3193. }
  3194. }
  3195. static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
  3196. u32 master_plane_id, struct sde_kms_info *info,
  3197. struct sde_mdss_cfg *catalog)
  3198. {
  3199. bool is_master = !psde->is_virtual;
  3200. const struct sde_format_extended *format_list;
  3201. u32 index;
  3202. int pipe_id;
  3203. if (is_master) {
  3204. format_list = psde->pipe_sblk->format_list;
  3205. } else {
  3206. format_list = psde->pipe_sblk->virt_format_list;
  3207. sde_kms_info_add_keyint(info, "primary_smart_plane_id",
  3208. master_plane_id);
  3209. }
  3210. if (format_list) {
  3211. sde_kms_info_start(info, "pixel_formats");
  3212. while (format_list->fourcc_format) {
  3213. sde_kms_info_append_format(info,
  3214. format_list->fourcc_format,
  3215. format_list->modifier);
  3216. ++format_list;
  3217. }
  3218. sde_kms_info_stop(info);
  3219. }
  3220. if (psde->pipe_hw && catalog->qseed_hw_rev)
  3221. sde_kms_info_add_keyint(info, "scaler_step_ver", catalog->qseed_hw_rev);
  3222. sde_kms_info_add_keyint(info, "max_linewidth",
  3223. psde->pipe_sblk->maxlinewidth);
  3224. sde_kms_info_add_keyint(info, "max_upscale",
  3225. psde->pipe_sblk->maxupscale);
  3226. sde_kms_info_add_keyint(info, "max_downscale",
  3227. psde->pipe_sblk->maxdwnscale);
  3228. sde_kms_info_add_keyint(info, "max_horizontal_deci",
  3229. psde->pipe_sblk->maxhdeciexp);
  3230. sde_kms_info_add_keyint(info, "max_vertical_deci",
  3231. psde->pipe_sblk->maxvdeciexp);
  3232. sde_kms_info_add_keyint(info, "max_per_pipe_bw",
  3233. psde->pipe_sblk->max_per_pipe_bw * 1000LL);
  3234. sde_kms_info_add_keyint(info, "max_per_pipe_bw_high",
  3235. psde->pipe_sblk->max_per_pipe_bw_high * 1000LL);
  3236. if (SDE_SSPP_VALID_VIG(psde->pipe))
  3237. pipe_id = psde->pipe - SSPP_VIG0;
  3238. else if (SDE_SSPP_VALID_DMA(psde->pipe))
  3239. pipe_id = psde->pipe - SSPP_DMA0;
  3240. else
  3241. pipe_id = -1;
  3242. sde_kms_info_add_keyint(info, "pipe_idx", pipe_id);
  3243. index = (master_plane_id == 0) ? 0 : 1;
  3244. if (test_bit(SDE_FEATURE_DEMURA, catalog->features) &&
  3245. catalog->demura_supported[psde->pipe][index] != ~0x0)
  3246. sde_kms_info_add_keyint(info, "demura_block", index);
  3247. if (psde->features & BIT(SDE_SSPP_SEC_UI_ALLOWED))
  3248. sde_kms_info_add_keyint(info, "sec_ui_allowed", 1);
  3249. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  3250. sde_kms_info_add_keyint(info, "block_sec_ui", 1);
  3251. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3252. const struct sde_format_extended *inline_rot_fmt_list;
  3253. sde_kms_info_add_keyint(info, "true_inline_rot_rev",
  3254. catalog->true_inline_rot_rev);
  3255. sde_kms_info_add_keyint(info,
  3256. "true_inline_dwnscale_rt",
  3257. (int) (psde->pipe_sblk->in_rot_maxdwnscale_rt_num /
  3258. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom));
  3259. sde_kms_info_add_keyint(info,
  3260. "true_inline_dwnscale_rt_numerator",
  3261. psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3262. sde_kms_info_add_keyint(info,
  3263. "true_inline_dwnscale_rt_denominator",
  3264. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3265. sde_kms_info_add_keyint(info, "true_inline_dwnscale_nrt",
  3266. psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3267. sde_kms_info_add_keyint(info, "true_inline_max_height",
  3268. psde->pipe_sblk->in_rot_maxheight);
  3269. inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list;
  3270. if (inline_rot_fmt_list) {
  3271. sde_kms_info_start(info, "inline_rot_pixel_formats");
  3272. while (inline_rot_fmt_list->fourcc_format) {
  3273. sde_kms_info_append_format(info,
  3274. inline_rot_fmt_list->fourcc_format,
  3275. inline_rot_fmt_list->modifier);
  3276. ++inline_rot_fmt_list;
  3277. }
  3278. sde_kms_info_stop(info);
  3279. }
  3280. }
  3281. }
  3282. /* helper to install properties which are common to planes and crtcs */
  3283. static void _sde_plane_install_properties(struct drm_plane *plane,
  3284. struct sde_mdss_cfg *catalog, u32 master_plane_id)
  3285. {
  3286. static const struct drm_prop_enum_list e_blend_op[] = {
  3287. {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
  3288. {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
  3289. {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
  3290. {SDE_DRM_BLEND_OP_COVERAGE, "coverage"},
  3291. {SDE_DRM_BLEND_OP_SKIP, "skip_blending"},
  3292. };
  3293. static const struct drm_prop_enum_list e_src_config[] = {
  3294. {SDE_DRM_DEINTERLACE, "deinterlace"}
  3295. };
  3296. static const struct drm_prop_enum_list e_fb_translation_mode[] = {
  3297. {SDE_DRM_FB_NON_SEC, "non_sec"},
  3298. {SDE_DRM_FB_SEC, "sec"},
  3299. {SDE_DRM_FB_NON_SEC_DIR_TRANS, "non_sec_direct_translation"},
  3300. {SDE_DRM_FB_SEC_DIR_TRANS, "sec_direct_translation"},
  3301. };
  3302. static const struct drm_prop_enum_list e_multirect_mode[] = {
  3303. {SDE_SSPP_MULTIRECT_NONE, "none"},
  3304. {SDE_SSPP_MULTIRECT_PARALLEL, "parallel"},
  3305. {SDE_SSPP_MULTIRECT_TIME_MX, "serial"},
  3306. };
  3307. struct sde_kms_info *info;
  3308. struct sde_plane *psde = to_sde_plane(plane);
  3309. bool is_master;
  3310. int zpos_max = 255;
  3311. int zpos_def = 0;
  3312. if (!plane || !psde) {
  3313. SDE_ERROR("invalid plane\n");
  3314. return;
  3315. } else if (!psde->pipe_hw || !psde->pipe_sblk) {
  3316. SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
  3317. !psde->pipe_hw, !psde->pipe_sblk);
  3318. return;
  3319. } else if (!catalog) {
  3320. SDE_ERROR("invalid catalog\n");
  3321. return;
  3322. }
  3323. psde->catalog = catalog;
  3324. is_master = !psde->is_virtual;
  3325. info = vzalloc(sizeof(struct sde_kms_info));
  3326. if (!info) {
  3327. SDE_ERROR("failed to allocate info memory\n");
  3328. return;
  3329. }
  3330. if (sde_is_custom_client()) {
  3331. if (catalog->mixer_count &&
  3332. catalog->mixer[0].sblk->maxblendstages) {
  3333. zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
  3334. if (test_bit(SDE_FEATURE_BASE_LAYER, catalog->features) &&
  3335. (zpos_max > SDE_STAGE_MAX - 1))
  3336. zpos_max = SDE_STAGE_MAX - 1;
  3337. else if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
  3338. zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
  3339. }
  3340. } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
  3341. /* reserve zpos == 0 for primary planes */
  3342. zpos_def = drm_plane_index(plane) + 1;
  3343. }
  3344. msm_property_install_range(&psde->property_info, "zpos",
  3345. 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
  3346. msm_property_install_range(&psde->property_info, "alpha",
  3347. 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
  3348. /* linux default file descriptor range on each process */
  3349. msm_property_install_range(&psde->property_info, "input_fence",
  3350. 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
  3351. if (is_master)
  3352. _sde_plane_install_master_only_properties(psde);
  3353. else
  3354. msm_property_install_enum(&psde->property_info,
  3355. "multirect_mode", 0x0, 0, e_multirect_mode,
  3356. ARRAY_SIZE(e_multirect_mode), 0,
  3357. PLANE_PROP_MULTIRECT_MODE);
  3358. if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
  3359. msm_property_install_volatile_range(&psde->property_info,
  3360. "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
  3361. sde_plane_rot_install_properties(plane, catalog);
  3362. msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
  3363. e_blend_op, ARRAY_SIZE(e_blend_op), 0, PLANE_PROP_BLEND_OP);
  3364. msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
  3365. e_src_config, ARRAY_SIZE(e_src_config), 0,
  3366. PLANE_PROP_SRC_CONFIG);
  3367. if (psde->pipe_hw->ops.setup_solidfill)
  3368. msm_property_install_range(&psde->property_info, "color_fill",
  3369. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
  3370. msm_property_install_range(&psde->property_info, "prefill_size", 0x0,
  3371. 0, ~0, 0, PLANE_PROP_PREFILL_SIZE);
  3372. msm_property_install_range(&psde->property_info, "prefill_time", 0x0,
  3373. 0, ~0, 0, PLANE_PROP_PREFILL_TIME);
  3374. msm_property_install_blob(&psde->property_info, "capabilities",
  3375. DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
  3376. sde_kms_info_reset(info);
  3377. _sde_plane_setup_capabilities_blob(psde, master_plane_id, info,
  3378. catalog);
  3379. _sde_plane_install_colorproc_properties(psde, info);
  3380. msm_property_set_blob(&psde->property_info, &psde->blob_info,
  3381. info->data, SDE_KMS_INFO_DATALEN(info),
  3382. PLANE_PROP_INFO);
  3383. msm_property_install_enum(&psde->property_info, "fb_translation_mode",
  3384. 0x0, 0, e_fb_translation_mode,
  3385. ARRAY_SIZE(e_fb_translation_mode), 0,
  3386. PLANE_PROP_FB_TRANSLATION_MODE);
  3387. if (psde->pipe_hw->ops.set_ubwc_stats_roi)
  3388. msm_property_install_range(&psde->property_info, "ubwc_stats_roi",
  3389. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_UBWC_STATS_ROI);
  3390. vfree(info);
  3391. }
  3392. static inline void _sde_plane_set_csc_v1(struct sde_plane *psde,
  3393. void __user *usr_ptr)
  3394. {
  3395. struct sde_drm_csc_v1 csc_v1;
  3396. int i;
  3397. if (!psde) {
  3398. SDE_ERROR("invalid plane\n");
  3399. return;
  3400. }
  3401. psde->csc_usr_ptr = NULL;
  3402. if (!usr_ptr) {
  3403. SDE_DEBUG_PLANE(psde, "csc data removed\n");
  3404. return;
  3405. }
  3406. if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
  3407. SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
  3408. return;
  3409. }
  3410. /* populate from user space */
  3411. for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
  3412. psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
  3413. for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
  3414. psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
  3415. psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
  3416. }
  3417. for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
  3418. psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
  3419. psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
  3420. }
  3421. psde->csc_usr_ptr = &psde->csc_cfg;
  3422. }
  3423. static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde,
  3424. struct sde_plane_state *pstate, void __user *usr)
  3425. {
  3426. struct sde_drm_scaler_v1 scale_v1;
  3427. struct sde_hw_pixel_ext *pe;
  3428. int i;
  3429. if (!psde || !pstate) {
  3430. SDE_ERROR("invalid argument(s)\n");
  3431. return;
  3432. }
  3433. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3434. if (!usr) {
  3435. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3436. return;
  3437. }
  3438. if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
  3439. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3440. return;
  3441. }
  3442. /* force property to be dirty, even if the pointer didn't change */
  3443. msm_property_set_dirty(&psde->property_info,
  3444. &pstate->property_state, PLANE_PROP_SCALER_V1);
  3445. /* populate from user space */
  3446. pe = &pstate->pixel_ext;
  3447. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3448. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3449. pe->init_phase_x[i] = scale_v1.init_phase_x[i];
  3450. pe->phase_step_x[i] = scale_v1.phase_step_x[i];
  3451. pe->init_phase_y[i] = scale_v1.init_phase_y[i];
  3452. pe->phase_step_y[i] = scale_v1.phase_step_y[i];
  3453. pe->horz_filter[i] = scale_v1.horz_filter[i];
  3454. pe->vert_filter[i] = scale_v1.vert_filter[i];
  3455. }
  3456. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3457. pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
  3458. pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
  3459. pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
  3460. pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
  3461. pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
  3462. pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
  3463. pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
  3464. pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
  3465. pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
  3466. pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
  3467. }
  3468. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V1;
  3469. SDE_EVT32_VERBOSE(DRMID(&psde->base));
  3470. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3471. }
  3472. static void _sde_plane_clear_predownscale_settings(
  3473. struct sde_plane_state *pstate)
  3474. {
  3475. pstate->pre_down.pre_downscale_x_0 = 0;
  3476. pstate->pre_down.pre_downscale_x_1 = 0;
  3477. pstate->pre_down.pre_downscale_y_0 = 0;
  3478. pstate->pre_down.pre_downscale_y_1 = 0;
  3479. }
  3480. static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
  3481. struct sde_plane_state *pstate, void __user *usr)
  3482. {
  3483. struct sde_drm_scaler_v2 scale_v2;
  3484. struct sde_hw_pixel_ext *pe;
  3485. int i;
  3486. struct sde_hw_scaler3_cfg *cfg;
  3487. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  3488. if (!psde || !pstate) {
  3489. SDE_ERROR("invalid argument(s)\n");
  3490. return;
  3491. }
  3492. cfg = &pstate->scaler3_cfg;
  3493. pd_cfg = &pstate->pre_down;
  3494. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3495. if (!usr) {
  3496. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3497. cfg->enable = 0;
  3498. _sde_plane_clear_predownscale_settings(pstate);
  3499. goto end;
  3500. }
  3501. if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
  3502. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3503. return;
  3504. }
  3505. /* detach/ignore user data if 'disabled' */
  3506. if (!scale_v2.enable) {
  3507. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3508. cfg->enable = 0;
  3509. _sde_plane_clear_predownscale_settings(pstate);
  3510. goto end;
  3511. }
  3512. /* populate from user space */
  3513. sde_set_scaler_v2(cfg, &scale_v2);
  3514. if (_sde_plane_has_pre_downscale(psde)) {
  3515. pd_cfg->pre_downscale_x_0 = scale_v2.pre_downscale_x_0;
  3516. pd_cfg->pre_downscale_x_1 = scale_v2.pre_downscale_x_1;
  3517. pd_cfg->pre_downscale_y_0 = scale_v2.pre_downscale_y_0;
  3518. pd_cfg->pre_downscale_y_1 = scale_v2.pre_downscale_y_1;
  3519. }
  3520. pe = &pstate->pixel_ext;
  3521. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3522. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3523. pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
  3524. pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
  3525. pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
  3526. pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
  3527. pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
  3528. pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
  3529. pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
  3530. pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
  3531. pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
  3532. pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
  3533. }
  3534. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2_CHECK;
  3535. end:
  3536. /* force property to be dirty, even if the pointer didn't change */
  3537. msm_property_set_dirty(&psde->property_info,
  3538. &pstate->property_state, PLANE_PROP_SCALER_V2);
  3539. SDE_EVT32_VERBOSE(DRMID(&psde->base), cfg->enable, cfg->de.enable,
  3540. cfg->src_width[0], cfg->src_height[0],
  3541. cfg->dst_width, cfg->dst_height);
  3542. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3543. }
  3544. static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
  3545. struct sde_plane_state *pstate, void __user *usr_ptr)
  3546. {
  3547. struct drm_clip_rect excl_rect_v1;
  3548. if (!psde || !pstate) {
  3549. SDE_ERROR("invalid argument(s)\n");
  3550. return;
  3551. }
  3552. if (!usr_ptr) {
  3553. memset(&pstate->excl_rect, 0, sizeof(pstate->excl_rect));
  3554. SDE_DEBUG_PLANE(psde, "excl_rect data cleared\n");
  3555. return;
  3556. }
  3557. if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
  3558. SDE_ERROR_PLANE(psde, "failed to copy excl_rect data\n");
  3559. return;
  3560. }
  3561. /* populate from user space */
  3562. pstate->excl_rect.x = excl_rect_v1.x1;
  3563. pstate->excl_rect.y = excl_rect_v1.y1;
  3564. pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1;
  3565. pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1;
  3566. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  3567. pstate->excl_rect.x, pstate->excl_rect.y,
  3568. pstate->excl_rect.w, pstate->excl_rect.h);
  3569. }
  3570. static void _sde_plane_set_ubwc_stats_roi(struct sde_plane *psde,
  3571. struct sde_plane_state *pstate, void __user *usr_ptr)
  3572. {
  3573. struct sde_drm_ubwc_stats_roi roi = {0};
  3574. if (!psde || !pstate) {
  3575. SDE_ERROR("invalid argument(s)\n");
  3576. return;
  3577. }
  3578. if (!usr_ptr) {
  3579. SDE_DEBUG_PLANE(psde, "ubwc roi disabled");
  3580. goto end;
  3581. }
  3582. if (copy_from_user(&roi, usr_ptr, sizeof(roi))) {
  3583. SDE_ERROR_PLANE(psde, "failed to copy ubwc stats roi");
  3584. return;
  3585. }
  3586. if (roi.y_coord0 > psde->pipe_cfg.src_rect.h || roi.y_coord1 > psde->pipe_cfg.src_rect.h) {
  3587. SDE_ERROR_PLANE(psde, "invalid ubwc roi y0 0x%x, y1 0x%x, src height 0x%x",
  3588. roi.y_coord0, roi.y_coord1, psde->pipe_cfg.src_rect.h);
  3589. memset(&roi, 0, sizeof(roi));
  3590. }
  3591. end:
  3592. SDE_EVT32(psde, roi.y_coord0, roi.y_coord1);
  3593. memcpy(&pstate->ubwc_stats_roi, &roi, sizeof(struct sde_drm_ubwc_stats_roi));
  3594. }
  3595. static int sde_plane_atomic_set_property(struct drm_plane *plane,
  3596. struct drm_plane_state *state, struct drm_property *property,
  3597. uint64_t val)
  3598. {
  3599. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3600. struct sde_plane_state *pstate;
  3601. int idx, ret = -EINVAL;
  3602. SDE_DEBUG_PLANE(psde, "\n");
  3603. if (!plane) {
  3604. SDE_ERROR("invalid plane\n");
  3605. } else if (!state) {
  3606. SDE_ERROR_PLANE(psde, "invalid state\n");
  3607. } else {
  3608. pstate = to_sde_plane_state(state);
  3609. ret = msm_property_atomic_set(&psde->property_info,
  3610. &pstate->property_state, property, val);
  3611. if (!ret) {
  3612. idx = msm_property_index(&psde->property_info,
  3613. property);
  3614. switch (idx) {
  3615. case PLANE_PROP_INPUT_FENCE:
  3616. _sde_plane_set_input_fence(psde, pstate, val);
  3617. break;
  3618. case PLANE_PROP_CSC_V1:
  3619. case PLANE_PROP_CSC_DMA_V1:
  3620. _sde_plane_set_csc_v1(psde, (void __user *)val);
  3621. break;
  3622. case PLANE_PROP_SCALER_V1:
  3623. _sde_plane_set_scaler_v1(psde, pstate,
  3624. (void *)(uintptr_t)val);
  3625. break;
  3626. case PLANE_PROP_SCALER_V2:
  3627. _sde_plane_set_scaler_v2(psde, pstate,
  3628. (void *)(uintptr_t)val);
  3629. break;
  3630. case PLANE_PROP_EXCL_RECT_V1:
  3631. _sde_plane_set_excl_rect_v1(psde, pstate,
  3632. (void *)(uintptr_t)val);
  3633. break;
  3634. case PLANE_PROP_UBWC_STATS_ROI:
  3635. _sde_plane_set_ubwc_stats_roi(psde, pstate,
  3636. (void __user *)(uintptr_t)val);
  3637. break;
  3638. default:
  3639. /* nothing to do */
  3640. break;
  3641. }
  3642. }
  3643. }
  3644. SDE_DEBUG_PLANE(psde, "%s[%d] <= 0x%llx ret=%d\n",
  3645. property->name, property->base.id, val, ret);
  3646. return ret;
  3647. }
  3648. static int sde_plane_atomic_get_property(struct drm_plane *plane,
  3649. const struct drm_plane_state *state,
  3650. struct drm_property *property, uint64_t *val)
  3651. {
  3652. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3653. struct sde_plane_state *pstate;
  3654. int ret = -EINVAL;
  3655. if (!plane) {
  3656. SDE_ERROR("invalid plane\n");
  3657. } else if (!state) {
  3658. SDE_ERROR("invalid state\n");
  3659. } else {
  3660. SDE_DEBUG_PLANE(psde, "\n");
  3661. pstate = to_sde_plane_state(state);
  3662. ret = msm_property_atomic_get(&psde->property_info,
  3663. &pstate->property_state, property, val);
  3664. }
  3665. return ret;
  3666. }
  3667. int sde_plane_helper_reset_custom_properties(struct drm_plane *plane,
  3668. struct drm_plane_state *plane_state)
  3669. {
  3670. struct sde_plane *psde;
  3671. struct sde_plane_state *pstate;
  3672. struct drm_property *drm_prop;
  3673. enum msm_mdp_plane_property prop_idx;
  3674. if (!plane || !plane_state) {
  3675. SDE_ERROR("invalid params\n");
  3676. return -EINVAL;
  3677. }
  3678. psde = to_sde_plane(plane);
  3679. pstate = to_sde_plane_state(plane_state);
  3680. for (prop_idx = 0; prop_idx < PLANE_PROP_COUNT; prop_idx++) {
  3681. uint64_t val = pstate->property_values[prop_idx].value;
  3682. uint64_t def;
  3683. int ret;
  3684. drm_prop = msm_property_index_to_drm_property(
  3685. &psde->property_info, prop_idx);
  3686. if (!drm_prop) {
  3687. /* not all props will be installed, based on caps */
  3688. SDE_DEBUG_PLANE(psde, "invalid property index %d\n",
  3689. prop_idx);
  3690. continue;
  3691. }
  3692. def = msm_property_get_default(&psde->property_info, prop_idx);
  3693. if (val == def)
  3694. continue;
  3695. SDE_DEBUG_PLANE(psde, "set prop %s idx %d from %llu to %llu\n",
  3696. drm_prop->name, prop_idx, val, def);
  3697. ret = sde_plane_atomic_set_property(plane, plane_state,
  3698. drm_prop, def);
  3699. if (ret) {
  3700. SDE_ERROR_PLANE(psde,
  3701. "set property failed, idx %d ret %d\n",
  3702. prop_idx, ret);
  3703. continue;
  3704. }
  3705. }
  3706. return 0;
  3707. }
  3708. static void sde_plane_destroy(struct drm_plane *plane)
  3709. {
  3710. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3711. SDE_DEBUG_PLANE(psde, "\n");
  3712. if (psde) {
  3713. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3714. if (psde->blob_info)
  3715. drm_property_blob_put(psde->blob_info);
  3716. msm_property_destroy(&psde->property_info);
  3717. mutex_destroy(&psde->lock);
  3718. /* this will destroy the states as well */
  3719. drm_plane_cleanup(plane);
  3720. if (psde->pipe_hw)
  3721. sde_hw_sspp_destroy(psde->pipe_hw);
  3722. kfree(psde);
  3723. }
  3724. }
  3725. void sde_plane_destroy_fb(struct drm_plane_state *state)
  3726. {
  3727. struct sde_plane_state *pstate;
  3728. if (!state) {
  3729. SDE_ERROR("invalid arg state %d\n", !state);
  3730. return;
  3731. }
  3732. pstate = to_sde_plane_state(state);
  3733. if (sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE) ==
  3734. SDE_DRM_FB_SEC) {
  3735. /* remove ref count for frame buffers */
  3736. if (state->fb) {
  3737. drm_framebuffer_put(state->fb);
  3738. state->fb = NULL;
  3739. }
  3740. }
  3741. }
  3742. static void sde_plane_destroy_state(struct drm_plane *plane,
  3743. struct drm_plane_state *state)
  3744. {
  3745. struct sde_plane *psde;
  3746. struct sde_plane_state *pstate;
  3747. if (!plane || !state) {
  3748. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  3749. !plane, !state);
  3750. return;
  3751. }
  3752. psde = to_sde_plane(plane);
  3753. pstate = to_sde_plane_state(state);
  3754. SDE_DEBUG_PLANE(psde, "\n");
  3755. /* remove ref count for frame buffers */
  3756. if (state->fb)
  3757. drm_framebuffer_put(state->fb);
  3758. /* remove ref count for fence */
  3759. if (pstate->input_fence)
  3760. sde_sync_put(pstate->input_fence);
  3761. pstate->input_fence = 0;
  3762. /* destroy value helper */
  3763. msm_property_destroy_state(&psde->property_info, pstate,
  3764. &pstate->property_state);
  3765. }
  3766. static struct drm_plane_state *
  3767. sde_plane_duplicate_state(struct drm_plane *plane)
  3768. {
  3769. struct sde_plane *psde;
  3770. struct sde_plane_state *pstate;
  3771. struct sde_plane_state *old_state;
  3772. struct drm_property *drm_prop;
  3773. uint64_t input_fence_default;
  3774. if (!plane) {
  3775. SDE_ERROR("invalid plane\n");
  3776. return NULL;
  3777. } else if (!plane->state) {
  3778. SDE_ERROR("invalid plane state\n");
  3779. return NULL;
  3780. }
  3781. old_state = to_sde_plane_state(plane->state);
  3782. psde = to_sde_plane(plane);
  3783. if (old_state->cont_splash_populated) {
  3784. plane->state->crtc = NULL;
  3785. old_state->cont_splash_populated = false;
  3786. }
  3787. pstate = msm_property_alloc_state(&psde->property_info);
  3788. if (!pstate) {
  3789. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3790. return NULL;
  3791. }
  3792. SDE_DEBUG_PLANE(psde, "\n");
  3793. /* duplicate value helper */
  3794. msm_property_duplicate_state(&psde->property_info, old_state, pstate,
  3795. &pstate->property_state, pstate->property_values);
  3796. /* clear out any input fence */
  3797. pstate->input_fence = 0;
  3798. input_fence_default = msm_property_get_default(
  3799. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3800. drm_prop = msm_property_index_to_drm_property(
  3801. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3802. if (msm_property_atomic_set(&psde->property_info,
  3803. &pstate->property_state, drm_prop,
  3804. input_fence_default))
  3805. SDE_DEBUG_PLANE(psde,
  3806. "error clearing duplicated input fence\n");
  3807. pstate->dirty = 0x0;
  3808. pstate->pending = false;
  3809. __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
  3810. /* reset layout offset */
  3811. if (pstate->layout_offset) {
  3812. if (pstate->layout_offset > 0)
  3813. pstate->base.crtc_x += pstate->layout_offset;
  3814. pstate->layout = SDE_LAYOUT_NONE;
  3815. pstate->layout_offset = 0;
  3816. }
  3817. return &pstate->base;
  3818. }
  3819. static void sde_plane_reset(struct drm_plane *plane)
  3820. {
  3821. struct sde_plane *psde;
  3822. struct sde_plane_state *pstate;
  3823. if (!plane) {
  3824. SDE_ERROR("invalid plane\n");
  3825. return;
  3826. }
  3827. psde = to_sde_plane(plane);
  3828. SDE_DEBUG_PLANE(psde, "\n");
  3829. if (plane->state && !sde_crtc_is_reset_required(plane->state->crtc)) {
  3830. SDE_DEBUG_PLANE(psde, "avoid reset for plane\n");
  3831. return;
  3832. }
  3833. /* remove previous state, if present */
  3834. if (plane->state) {
  3835. sde_plane_destroy_state(plane, plane->state);
  3836. plane->state = 0;
  3837. }
  3838. pstate = msm_property_alloc_state(&psde->property_info);
  3839. if (!pstate) {
  3840. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3841. return;
  3842. }
  3843. /* reset value helper */
  3844. msm_property_reset_state(&psde->property_info, pstate,
  3845. &pstate->property_state,
  3846. pstate->property_values);
  3847. pstate->base.plane = plane;
  3848. plane->state = &pstate->base;
  3849. }
  3850. void sde_plane_get_frame_data(struct drm_plane *plane,
  3851. struct sde_drm_plane_frame_data *data)
  3852. {
  3853. struct sde_plane *psde;
  3854. struct sde_plane_state *pstate;
  3855. struct sde_drm_ubwc_stats_data *ubwc_stats;
  3856. if (!plane) {
  3857. SDE_ERROR("invalid plane\n");
  3858. return;
  3859. }
  3860. psde = to_sde_plane(plane);
  3861. pstate = to_sde_plane_state(plane->state);
  3862. ubwc_stats = &data->ubwc_stats;
  3863. data->plane_id = DRMID(plane);
  3864. if (psde->pipe_hw->ops.get_ubwc_stats_data) {
  3865. memcpy(&ubwc_stats->roi, &pstate->ubwc_stats_roi,
  3866. sizeof(struct sde_drm_ubwc_stats_roi));
  3867. psde->pipe_hw->ops.get_ubwc_stats_data(psde->pipe_hw,
  3868. pstate->multirect_index, ubwc_stats);
  3869. }
  3870. if (psde->pipe_hw->ops.get_ubwc_error)
  3871. ubwc_stats->error = psde->pipe_hw->ops.get_ubwc_error(psde->pipe_hw,
  3872. pstate->multirect_index);
  3873. if (psde->pipe_hw->ops.clear_ubwc_error && ubwc_stats->error)
  3874. psde->pipe_hw->ops.clear_ubwc_error(psde->pipe_hw, pstate->multirect_index);
  3875. if (psde->pipe_hw->ops.get_meta_error)
  3876. ubwc_stats->meta_error = psde->pipe_hw->ops.get_meta_error(psde->pipe_hw,
  3877. pstate->multirect_index);
  3878. if (psde->pipe_hw->ops.clear_meta_error && ubwc_stats->meta_error)
  3879. psde->pipe_hw->ops.clear_meta_error(psde->pipe_hw, pstate->multirect_index);
  3880. if (ubwc_stats->error || ubwc_stats->meta_error) {
  3881. SDE_EVT32(DRMID(plane), ubwc_stats->error, ubwc_stats->meta_error,
  3882. SDE_EVTLOG_ERROR);
  3883. SDE_DEBUG_PLANE(psde, "plane%d ubwc_error %d meta_error %d\n",
  3884. ubwc_stats->error, ubwc_stats->meta_error);
  3885. }
  3886. }
  3887. #if IS_ENABLED(CONFIG_DEBUG_FS)
  3888. static ssize_t _sde_plane_danger_read(struct file *file,
  3889. char __user *buff, size_t count, loff_t *ppos)
  3890. {
  3891. struct sde_kms *kms = file->private_data;
  3892. struct sde_mdss_cfg *cfg = kms->catalog;
  3893. int len = 0;
  3894. char buf[40] = {'\0'};
  3895. if (!cfg)
  3896. return -ENODEV;
  3897. if (*ppos)
  3898. return 0; /* the end */
  3899. len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
  3900. if (len < 0 || len >= sizeof(buf))
  3901. return 0;
  3902. if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
  3903. return -EFAULT;
  3904. *ppos += len; /* increase offset */
  3905. return len;
  3906. }
  3907. static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
  3908. {
  3909. struct drm_plane *plane;
  3910. drm_for_each_plane(plane, kms->dev) {
  3911. if (plane->fb && plane->state) {
  3912. sde_plane_danger_signal_ctrl(plane, enable);
  3913. SDE_DEBUG("plane:%d img:%dx%d ",
  3914. plane->base.id, plane->fb->width,
  3915. plane->fb->height);
  3916. SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
  3917. plane->state->src_x >> 16,
  3918. plane->state->src_y >> 16,
  3919. plane->state->src_w >> 16,
  3920. plane->state->src_h >> 16,
  3921. plane->state->crtc_x, plane->state->crtc_y,
  3922. plane->state->crtc_w, plane->state->crtc_h);
  3923. } else {
  3924. SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
  3925. }
  3926. }
  3927. }
  3928. static ssize_t _sde_plane_danger_write(struct file *file,
  3929. const char __user *user_buf, size_t count, loff_t *ppos)
  3930. {
  3931. struct sde_kms *kms = file->private_data;
  3932. struct sde_mdss_cfg *cfg = kms->catalog;
  3933. int disable_panic;
  3934. char buf[10];
  3935. if (!cfg)
  3936. return -EFAULT;
  3937. if (count >= sizeof(buf))
  3938. return -EFAULT;
  3939. if (copy_from_user(buf, user_buf, count))
  3940. return -EFAULT;
  3941. buf[count] = 0; /* end of string */
  3942. if (kstrtoint(buf, 0, &disable_panic))
  3943. return -EFAULT;
  3944. if (disable_panic) {
  3945. /* Disable panic signal for all active pipes */
  3946. SDE_DEBUG("Disabling danger:\n");
  3947. _sde_plane_set_danger_state(kms, false);
  3948. kms->has_danger_ctrl = false;
  3949. } else {
  3950. /* Enable panic signal for all active pipes */
  3951. SDE_DEBUG("Enabling danger:\n");
  3952. kms->has_danger_ctrl = true;
  3953. _sde_plane_set_danger_state(kms, true);
  3954. }
  3955. return count;
  3956. }
  3957. static const struct file_operations sde_plane_danger_enable = {
  3958. .open = simple_open,
  3959. .read = _sde_plane_danger_read,
  3960. .write = _sde_plane_danger_write,
  3961. };
  3962. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3963. {
  3964. struct sde_plane *psde;
  3965. struct sde_kms *kms;
  3966. struct msm_drm_private *priv;
  3967. const struct sde_sspp_sub_blks *sblk = 0;
  3968. const struct sde_sspp_cfg *cfg = 0;
  3969. if (!plane || !plane->dev) {
  3970. SDE_ERROR("invalid arguments\n");
  3971. return -EINVAL;
  3972. }
  3973. priv = plane->dev->dev_private;
  3974. if (!priv || !priv->kms) {
  3975. SDE_ERROR("invalid KMS reference\n");
  3976. return -EINVAL;
  3977. }
  3978. kms = to_sde_kms(priv->kms);
  3979. psde = to_sde_plane(plane);
  3980. if (psde && psde->pipe_hw)
  3981. cfg = psde->pipe_hw->cap;
  3982. if (cfg)
  3983. sblk = cfg->sblk;
  3984. if (!sblk)
  3985. return 0;
  3986. /* create overall sub-directory for the pipe */
  3987. psde->debugfs_root =
  3988. debugfs_create_dir(psde->pipe_name,
  3989. plane->dev->primary->debugfs_root);
  3990. if (!psde->debugfs_root)
  3991. return -ENOMEM;
  3992. /* don't error check these */
  3993. debugfs_create_x64("features", 0400,
  3994. psde->debugfs_root, &psde->features);
  3995. if (cfg->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  3996. cfg->features & BIT(SDE_SSPP_SCALER_QSEED3LITE) ||
  3997. cfg->features & BIT(SDE_SSPP_SCALER_QSEED2))
  3998. debugfs_create_bool("default_scaling",
  3999. 0600,
  4000. psde->debugfs_root,
  4001. &psde->debugfs_default_scale);
  4002. if (cfg->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  4003. debugfs_create_u32("in_rot_max_downscale_rt_num",
  4004. 0600,
  4005. psde->debugfs_root,
  4006. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  4007. debugfs_create_u32("in_rot_max_downscale_rt_denom",
  4008. 0600,
  4009. psde->debugfs_root,
  4010. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  4011. debugfs_create_u32("in_rot_max_downscale_nrt",
  4012. 0600,
  4013. psde->debugfs_root,
  4014. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  4015. debugfs_create_u32("in_rot_max_height",
  4016. 0600,
  4017. psde->debugfs_root,
  4018. (u32 *) &psde->pipe_sblk->in_rot_maxheight);
  4019. }
  4020. debugfs_create_u32("xin_id",
  4021. 0400,
  4022. psde->debugfs_root,
  4023. (u32 *) &cfg->xin_id);
  4024. debugfs_create_x32("creq_vblank",
  4025. 0600,
  4026. psde->debugfs_root,
  4027. (u32 *) &sblk->creq_vblank);
  4028. debugfs_create_x32("danger_vblank",
  4029. 0600,
  4030. psde->debugfs_root,
  4031. (u32 *) &sblk->danger_vblank);
  4032. debugfs_create_file("disable_danger",
  4033. 0600,
  4034. psde->debugfs_root,
  4035. kms, &sde_plane_danger_enable);
  4036. return 0;
  4037. }
  4038. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  4039. {
  4040. struct sde_plane *psde;
  4041. if (!plane)
  4042. return;
  4043. psde = to_sde_plane(plane);
  4044. debugfs_remove_recursive(psde->debugfs_root);
  4045. }
  4046. #else
  4047. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  4048. {
  4049. return 0;
  4050. }
  4051. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  4052. {
  4053. }
  4054. #endif /* CONFIG_DEBUG_FS */
  4055. static int sde_plane_late_register(struct drm_plane *plane)
  4056. {
  4057. return _sde_plane_init_debugfs(plane);
  4058. }
  4059. static void sde_plane_early_unregister(struct drm_plane *plane)
  4060. {
  4061. _sde_plane_destroy_debugfs(plane);
  4062. }
  4063. static const struct drm_plane_funcs sde_plane_funcs = {
  4064. .update_plane = drm_atomic_helper_update_plane,
  4065. .disable_plane = drm_atomic_helper_disable_plane,
  4066. .destroy = sde_plane_destroy,
  4067. .atomic_set_property = sde_plane_atomic_set_property,
  4068. .atomic_get_property = sde_plane_atomic_get_property,
  4069. .reset = sde_plane_reset,
  4070. .atomic_duplicate_state = sde_plane_duplicate_state,
  4071. .atomic_destroy_state = sde_plane_destroy_state,
  4072. .late_register = sde_plane_late_register,
  4073. .early_unregister = sde_plane_early_unregister,
  4074. };
  4075. static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
  4076. .prepare_fb = sde_plane_prepare_fb,
  4077. .cleanup_fb = sde_plane_cleanup_fb,
  4078. .atomic_check = sde_plane_atomic_check,
  4079. .atomic_update = sde_plane_atomic_update,
  4080. };
  4081. enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
  4082. {
  4083. return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
  4084. }
  4085. bool is_sde_plane_virtual(struct drm_plane *plane)
  4086. {
  4087. return plane ? to_sde_plane(plane)->is_virtual : false;
  4088. }
  4089. /* initialize plane */
  4090. struct drm_plane *sde_plane_init(struct drm_device *dev,
  4091. uint32_t pipe, bool primary_plane,
  4092. unsigned long possible_crtcs, u32 master_plane_id)
  4093. {
  4094. struct drm_plane *plane = NULL, *master_plane = NULL;
  4095. const struct sde_format_extended *format_list;
  4096. struct sde_plane *psde;
  4097. struct msm_drm_private *priv;
  4098. struct sde_kms *kms;
  4099. enum drm_plane_type type;
  4100. struct sde_vbif_clk_client clk_client;
  4101. int ret = -EINVAL;
  4102. if (!dev) {
  4103. SDE_ERROR("[%u]device is NULL\n", pipe);
  4104. goto exit;
  4105. }
  4106. priv = dev->dev_private;
  4107. if (!priv) {
  4108. SDE_ERROR("[%u]private data is NULL\n", pipe);
  4109. goto exit;
  4110. }
  4111. if (!priv->kms) {
  4112. SDE_ERROR("[%u]invalid KMS reference\n", pipe);
  4113. goto exit;
  4114. }
  4115. kms = to_sde_kms(priv->kms);
  4116. if (!kms->catalog) {
  4117. SDE_ERROR("[%u]invalid catalog reference\n", pipe);
  4118. goto exit;
  4119. }
  4120. /* create and zero local structure */
  4121. psde = kzalloc(sizeof(*psde), GFP_KERNEL);
  4122. if (!psde) {
  4123. SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
  4124. ret = -ENOMEM;
  4125. goto exit;
  4126. }
  4127. /* cache local stuff for later */
  4128. plane = &psde->base;
  4129. psde->pipe = pipe;
  4130. psde->is_virtual = (master_plane_id != 0);
  4131. INIT_LIST_HEAD(&psde->mplane_list);
  4132. master_plane = drm_plane_find(dev, NULL, master_plane_id);
  4133. if (master_plane) {
  4134. struct sde_plane *mpsde = to_sde_plane(master_plane);
  4135. list_add_tail(&psde->mplane_list, &mpsde->mplane_list);
  4136. }
  4137. /* initialize underlying h/w driver */
  4138. psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog, psde->is_virtual,
  4139. &clk_client);
  4140. if (IS_ERR(psde->pipe_hw)) {
  4141. SDE_ERROR("[%u]SSPP init failed\n", pipe);
  4142. ret = PTR_ERR(psde->pipe_hw);
  4143. goto clean_plane;
  4144. } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
  4145. SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
  4146. goto clean_sspp;
  4147. }
  4148. if (test_bit(SDE_FEATURE_VBIF_CLK_SPLIT, kms->catalog->features)) {
  4149. ret = sde_vbif_clk_register(kms, &clk_client);
  4150. if (ret) {
  4151. SDE_ERROR("failed to register vbif client %d\n",
  4152. clk_client.clk_ctrl);
  4153. goto clean_sspp;
  4154. }
  4155. }
  4156. /* cache features mask for later */
  4157. psde->features = psde->pipe_hw->cap->features_ext;
  4158. psde->perf_features = psde->pipe_hw->cap->perf_features;
  4159. psde->pipe_sblk = psde->pipe_hw->cap->sblk;
  4160. if (!psde->pipe_sblk) {
  4161. SDE_ERROR("[%u]invalid sblk\n", pipe);
  4162. goto clean_sspp;
  4163. }
  4164. if (psde->is_virtual)
  4165. format_list = psde->pipe_sblk->virt_format_list;
  4166. else
  4167. format_list = psde->pipe_sblk->format_list;
  4168. psde->nformats = sde_populate_formats(format_list,
  4169. psde->formats,
  4170. 0,
  4171. ARRAY_SIZE(psde->formats));
  4172. if (!psde->nformats) {
  4173. SDE_ERROR("[%u]no valid formats for plane\n", pipe);
  4174. goto clean_sspp;
  4175. }
  4176. if (primary_plane)
  4177. type = DRM_PLANE_TYPE_PRIMARY;
  4178. else
  4179. type = DRM_PLANE_TYPE_OVERLAY;
  4180. ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
  4181. psde->formats, psde->nformats,
  4182. NULL, type, NULL);
  4183. if (ret)
  4184. goto clean_sspp;
  4185. /* Populate static array of plane property flags */
  4186. _sde_plane_map_prop_to_dirty_bits();
  4187. /* success! finalize initialization */
  4188. drm_plane_helper_add(plane, &sde_plane_helper_funcs);
  4189. msm_property_init(&psde->property_info, &plane->base, dev,
  4190. priv->plane_property, psde->property_data,
  4191. PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
  4192. sizeof(struct sde_plane_state));
  4193. _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
  4194. /* save user friendly pipe name for later */
  4195. snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
  4196. mutex_init(&psde->lock);
  4197. SDE_DEBUG("%s created for pipe:%u id:%u master:%u\n", psde->pipe_name,
  4198. pipe, plane->base.id, master_plane_id);
  4199. return plane;
  4200. clean_sspp:
  4201. if (psde && psde->pipe_hw)
  4202. sde_hw_sspp_destroy(psde->pipe_hw);
  4203. clean_plane:
  4204. kfree(psde);
  4205. exit:
  4206. return ERR_PTR(ret);
  4207. }
  4208. void sde_plane_add_data_to_minidump_va(struct drm_plane *plane)
  4209. {
  4210. struct sde_plane *sde_plane;
  4211. struct sde_plane_state *pstate;
  4212. sde_plane = to_sde_plane(plane);
  4213. pstate = to_sde_plane_state(plane->state);
  4214. sde_mini_dump_add_va_region("sde_plane", sizeof(*sde_plane), sde_plane);
  4215. sde_mini_dump_add_va_region("plane_state", sizeof(*pstate), pstate);
  4216. }