kona.c 232 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/gpio.h>
  8. #include <linux/of_gpio.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/soc/qcom/fsa4480-i2c.h>
  16. #include <sound/core.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/info.h>
  22. #include <soc/snd_event.h>
  23. #include <dsp/audio_notifier.h>
  24. #include <soc/swr-common.h>
  25. #include <dsp/q6afe-v2.h>
  26. #include <dsp/q6core.h>
  27. #include "device_event.h"
  28. #include "msm-pcm-routing-v2.h"
  29. #include "asoc/msm-cdc-pinctrl.h"
  30. #include "asoc/wcd-mbhc-v2.h"
  31. #include "codecs/wcd938x/wcd938x-mbhc.h"
  32. #include "codecs/wsa881x.h"
  33. #include "codecs/wcd938x/wcd938x.h"
  34. #include "codecs/bolero/bolero-cdc.h"
  35. #include <dt-bindings/sound/audio-codec-port-types.h>
  36. #include "codecs/bolero/wsa-macro.h"
  37. #include "kona-port-config.h"
  38. #define DRV_NAME "kona-asoc-snd"
  39. #define __CHIPSET__ "KONA "
  40. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  41. #define SAMPLING_RATE_8KHZ 8000
  42. #define SAMPLING_RATE_11P025KHZ 11025
  43. #define SAMPLING_RATE_16KHZ 16000
  44. #define SAMPLING_RATE_22P05KHZ 22050
  45. #define SAMPLING_RATE_32KHZ 32000
  46. #define SAMPLING_RATE_44P1KHZ 44100
  47. #define SAMPLING_RATE_48KHZ 48000
  48. #define SAMPLING_RATE_88P2KHZ 88200
  49. #define SAMPLING_RATE_96KHZ 96000
  50. #define SAMPLING_RATE_176P4KHZ 176400
  51. #define SAMPLING_RATE_192KHZ 192000
  52. #define SAMPLING_RATE_352P8KHZ 352800
  53. #define SAMPLING_RATE_384KHZ 384000
  54. #define WCD9XXX_MBHC_DEF_RLOADS 5
  55. #define WCD9XXX_MBHC_DEF_BUTTONS 8
  56. #define CODEC_EXT_CLK_RATE 9600000
  57. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  58. #define DEV_NAME_STR_LEN 32
  59. #define WCD_MBHC_HS_V_MAX 1600
  60. #define TDM_CHANNEL_MAX 8
  61. #define DEV_NAME_STR_LEN 32
  62. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  63. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  64. #define WSA8810_NAME_1 "wsa881x.20170211"
  65. #define WSA8810_NAME_2 "wsa881x.20170212"
  66. #define WCN_CDC_SLIM_RX_CH_MAX 2
  67. #define WCN_CDC_SLIM_TX_CH_MAX 2
  68. #define WCN_CDC_SLIM_TX_CH_MAX_LITO 3
  69. enum {
  70. RX_PATH = 0,
  71. TX_PATH,
  72. MAX_PATH,
  73. };
  74. enum {
  75. TDM_0 = 0,
  76. TDM_1,
  77. TDM_2,
  78. TDM_3,
  79. TDM_4,
  80. TDM_5,
  81. TDM_6,
  82. TDM_7,
  83. TDM_PORT_MAX,
  84. };
  85. #define TDM_MAX_SLOTS 8
  86. #define TDM_SLOT_WIDTH_BITS 32
  87. enum {
  88. TDM_PRI = 0,
  89. TDM_SEC,
  90. TDM_TERT,
  91. TDM_QUAT,
  92. TDM_QUIN,
  93. TDM_SEN,
  94. TDM_INTERFACE_MAX,
  95. };
  96. enum {
  97. PRIM_AUX_PCM = 0,
  98. SEC_AUX_PCM,
  99. TERT_AUX_PCM,
  100. QUAT_AUX_PCM,
  101. QUIN_AUX_PCM,
  102. SEN_AUX_PCM,
  103. AUX_PCM_MAX,
  104. };
  105. enum {
  106. PRIM_MI2S = 0,
  107. SEC_MI2S,
  108. TERT_MI2S,
  109. QUAT_MI2S,
  110. QUIN_MI2S,
  111. SEN_MI2S,
  112. MI2S_MAX,
  113. };
  114. enum {
  115. WSA_CDC_DMA_RX_0 = 0,
  116. WSA_CDC_DMA_RX_1,
  117. RX_CDC_DMA_RX_0,
  118. RX_CDC_DMA_RX_1,
  119. RX_CDC_DMA_RX_2,
  120. RX_CDC_DMA_RX_3,
  121. RX_CDC_DMA_RX_5,
  122. CDC_DMA_RX_MAX,
  123. };
  124. enum {
  125. WSA_CDC_DMA_TX_0 = 0,
  126. WSA_CDC_DMA_TX_1,
  127. WSA_CDC_DMA_TX_2,
  128. TX_CDC_DMA_TX_0,
  129. TX_CDC_DMA_TX_3,
  130. TX_CDC_DMA_TX_4,
  131. VA_CDC_DMA_TX_0,
  132. VA_CDC_DMA_TX_1,
  133. VA_CDC_DMA_TX_2,
  134. CDC_DMA_TX_MAX,
  135. };
  136. enum {
  137. SLIM_RX_7 = 0,
  138. SLIM_RX_MAX,
  139. };
  140. enum {
  141. SLIM_TX_7 = 0,
  142. SLIM_TX_8,
  143. SLIM_TX_MAX,
  144. };
  145. enum {
  146. AFE_LOOPBACK_TX_IDX = 0,
  147. AFE_LOOPBACK_TX_IDX_MAX,
  148. };
  149. struct msm_asoc_mach_data {
  150. struct snd_info_entry *codec_root;
  151. int usbc_en2_gpio; /* used by gpio driver API */
  152. int lito_v2_enabled;
  153. struct device_node *dmic01_gpio_p; /* used by pinctrl API */
  154. struct device_node *dmic23_gpio_p; /* used by pinctrl API */
  155. struct device_node *dmic45_gpio_p; /* used by pinctrl API */
  156. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  157. atomic_t mi2s_gpio_ref_count[MI2S_MAX]; /* used by pinctrl API */
  158. struct device_node *us_euro_gpio_p; /* used by pinctrl API */
  159. struct pinctrl *usbc_en2_gpio_p; /* used by pinctrl API */
  160. struct device_node *hph_en1_gpio_p; /* used by pinctrl API */
  161. struct device_node *hph_en0_gpio_p; /* used by pinctrl API */
  162. bool is_afe_config_done;
  163. struct device_node *fsa_handle;
  164. };
  165. struct tdm_port {
  166. u32 mode;
  167. u32 channel;
  168. };
  169. struct tdm_dev_config {
  170. unsigned int tdm_slot_offset[TDM_MAX_SLOTS];
  171. };
  172. enum {
  173. EXT_DISP_RX_IDX_DP = 0,
  174. EXT_DISP_RX_IDX_DP1,
  175. EXT_DISP_RX_IDX_MAX,
  176. };
  177. struct msm_wsa881x_dev_info {
  178. struct device_node *of_node;
  179. u32 index;
  180. };
  181. struct aux_codec_dev_info {
  182. struct device_node *of_node;
  183. u32 index;
  184. };
  185. struct dev_config {
  186. u32 sample_rate;
  187. u32 bit_format;
  188. u32 channels;
  189. };
  190. /* Default configuration of slimbus channels */
  191. static struct dev_config slim_rx_cfg[] = {
  192. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  193. };
  194. static struct dev_config slim_tx_cfg[] = {
  195. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  196. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  197. };
  198. /* Default configuration of external display BE */
  199. static struct dev_config ext_disp_rx_cfg[] = {
  200. [EXT_DISP_RX_IDX_DP] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  201. [EXT_DISP_RX_IDX_DP1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  202. };
  203. static struct dev_config usb_rx_cfg = {
  204. .sample_rate = SAMPLING_RATE_48KHZ,
  205. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  206. .channels = 2,
  207. };
  208. static struct dev_config usb_tx_cfg = {
  209. .sample_rate = SAMPLING_RATE_48KHZ,
  210. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  211. .channels = 1,
  212. };
  213. static struct dev_config proxy_rx_cfg = {
  214. .sample_rate = SAMPLING_RATE_48KHZ,
  215. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  216. .channels = 2,
  217. };
  218. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  219. {
  220. AFE_API_VERSION_I2S_CONFIG,
  221. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  222. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  223. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  224. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  225. 0,
  226. },
  227. {
  228. AFE_API_VERSION_I2S_CONFIG,
  229. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  230. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  231. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  232. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  233. 0,
  234. },
  235. {
  236. AFE_API_VERSION_I2S_CONFIG,
  237. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  238. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  239. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  240. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  241. 0,
  242. },
  243. {
  244. AFE_API_VERSION_I2S_CONFIG,
  245. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  246. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  247. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  248. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  249. 0,
  250. },
  251. {
  252. AFE_API_VERSION_I2S_CONFIG,
  253. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  254. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  255. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  256. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  257. 0,
  258. },
  259. {
  260. AFE_API_VERSION_I2S_CONFIG,
  261. Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT,
  262. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  263. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  264. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  265. 0,
  266. },
  267. };
  268. struct mi2s_conf {
  269. struct mutex lock;
  270. u32 ref_cnt;
  271. u32 msm_is_mi2s_master;
  272. };
  273. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  274. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  275. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  276. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  277. };
  278. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  279. /* Default configuration of TDM channels */
  280. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  281. { /* PRI TDM */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  290. },
  291. { /* SEC TDM */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  300. },
  301. { /* TERT TDM */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  305. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  306. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  307. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  308. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  309. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  310. },
  311. { /* QUAT TDM */
  312. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  313. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  314. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  315. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  316. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  317. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  318. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  319. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  320. },
  321. { /* QUIN TDM */
  322. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  323. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  324. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  325. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  326. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  327. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  328. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  329. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  330. },
  331. { /* SEN TDM */
  332. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  333. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  334. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  335. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  336. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  337. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  338. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  339. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  340. },
  341. };
  342. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  343. { /* PRI TDM */
  344. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  345. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  346. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  347. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  348. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  349. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  350. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  351. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  352. },
  353. { /* SEC TDM */
  354. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  355. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  356. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  357. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  358. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  359. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  360. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  361. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  362. },
  363. { /* TERT TDM */
  364. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  365. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  366. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  367. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  368. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  369. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  370. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  371. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  372. },
  373. { /* QUAT TDM */
  374. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  375. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  376. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  377. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  378. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  379. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  380. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  381. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  382. },
  383. { /* QUIN TDM */
  384. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  385. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  386. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  387. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  388. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  389. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  390. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  391. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  392. },
  393. { /* SEN TDM */
  394. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  395. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  396. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  397. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  398. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  399. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  400. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  401. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  402. },
  403. };
  404. /* Default configuration of AUX PCM channels */
  405. static struct dev_config aux_pcm_rx_cfg[] = {
  406. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  407. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  408. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  409. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  410. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  411. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  412. };
  413. static struct dev_config aux_pcm_tx_cfg[] = {
  414. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  415. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  416. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  417. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  418. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  419. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  420. };
  421. /* Default configuration of MI2S channels */
  422. static struct dev_config mi2s_rx_cfg[] = {
  423. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  424. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  425. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  426. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  427. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  428. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  429. };
  430. static struct dev_config mi2s_tx_cfg[] = {
  431. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  432. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  433. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  434. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  435. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  436. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  437. };
  438. static struct tdm_dev_config pri_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  439. { /* PRI TDM */
  440. { {0, 4, 0xFFFF} }, /* RX_0 */
  441. { {8, 12, 0xFFFF} }, /* RX_1 */
  442. { {16, 20, 0xFFFF} }, /* RX_2 */
  443. { {24, 28, 0xFFFF} }, /* RX_3 */
  444. { {0xFFFF} }, /* RX_4 */
  445. { {0xFFFF} }, /* RX_5 */
  446. { {0xFFFF} }, /* RX_6 */
  447. { {0xFFFF} }, /* RX_7 */
  448. },
  449. {
  450. { {0, 4, 8, 12, 0xFFFF} }, /* TX_0 */
  451. { {8, 12, 0xFFFF} }, /* TX_1 */
  452. { {16, 20, 0xFFFF} }, /* TX_2 */
  453. { {24, 28, 0xFFFF} }, /* TX_3 */
  454. { {0xFFFF} }, /* TX_4 */
  455. { {0xFFFF} }, /* TX_5 */
  456. { {0xFFFF} }, /* TX_6 */
  457. { {0xFFFF} }, /* TX_7 */
  458. },
  459. };
  460. static struct tdm_dev_config sec_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  461. { /* SEC TDM */
  462. { {0, 4, 0xFFFF} }, /* RX_0 */
  463. { {8, 12, 0xFFFF} }, /* RX_1 */
  464. { {16, 20, 0xFFFF} }, /* RX_2 */
  465. { {24, 28, 0xFFFF} }, /* RX_3 */
  466. { {0xFFFF} }, /* RX_4 */
  467. { {0xFFFF} }, /* RX_5 */
  468. { {0xFFFF} }, /* RX_6 */
  469. { {0xFFFF} }, /* RX_7 */
  470. },
  471. {
  472. { {0, 4, 0xFFFF} }, /* TX_0 */
  473. { {8, 12, 0xFFFF} }, /* TX_1 */
  474. { {16, 20, 0xFFFF} }, /* TX_2 */
  475. { {24, 28, 0xFFFF} }, /* TX_3 */
  476. { {0xFFFF} }, /* TX_4 */
  477. { {0xFFFF} }, /* TX_5 */
  478. { {0xFFFF} }, /* TX_6 */
  479. { {0xFFFF} }, /* TX_7 */
  480. },
  481. };
  482. static struct tdm_dev_config tert_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  483. { /* TERT TDM */
  484. { {0, 4, 0xFFFF} }, /* RX_0 */
  485. { {8, 12, 0xFFFF} }, /* RX_1 */
  486. { {16, 20, 0xFFFF} }, /* RX_2 */
  487. { {24, 28, 0xFFFF} }, /* RX_3 */
  488. { {0xFFFF} }, /* RX_4 */
  489. { {0xFFFF} }, /* RX_5 */
  490. { {0xFFFF} }, /* RX_6 */
  491. { {0xFFFF} }, /* RX_7 */
  492. },
  493. {
  494. { {0, 4, 0xFFFF} }, /* TX_0 */
  495. { {8, 12, 0xFFFF} }, /* TX_1 */
  496. { {16, 20, 0xFFFF} }, /* TX_2 */
  497. { {24, 28, 0xFFFF} }, /* TX_3 */
  498. { {0xFFFF} }, /* TX_4 */
  499. { {0xFFFF} }, /* TX_5 */
  500. { {0xFFFF} }, /* TX_6 */
  501. { {0xFFFF} }, /* TX_7 */
  502. },
  503. };
  504. static struct tdm_dev_config quat_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  505. { /* QUAT TDM */
  506. { {0, 4, 0xFFFF} }, /* RX_0 */
  507. { {8, 12, 0xFFFF} }, /* RX_1 */
  508. { {16, 20, 0xFFFF} }, /* RX_2 */
  509. { {24, 28, 0xFFFF} }, /* RX_3 */
  510. { {0xFFFF} }, /* RX_4 */
  511. { {0xFFFF} }, /* RX_5 */
  512. { {0xFFFF} }, /* RX_6 */
  513. { {0xFFFF} }, /* RX_7 */
  514. },
  515. {
  516. { {0, 4, 0xFFFF} }, /* TX_0 */
  517. { {8, 12, 0xFFFF} }, /* TX_1 */
  518. { {16, 20, 0xFFFF} }, /* TX_2 */
  519. { {24, 28, 0xFFFF} }, /* TX_3 */
  520. { {0xFFFF} }, /* TX_4 */
  521. { {0xFFFF} }, /* TX_5 */
  522. { {0xFFFF} }, /* TX_6 */
  523. { {0xFFFF} }, /* TX_7 */
  524. },
  525. };
  526. static struct tdm_dev_config quin_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  527. { /* QUIN TDM */
  528. { {0, 4, 0xFFFF} }, /* RX_0 */
  529. { {8, 12, 0xFFFF} }, /* RX_1 */
  530. { {16, 20, 0xFFFF} }, /* RX_2 */
  531. { {24, 28, 0xFFFF} }, /* RX_3 */
  532. { {0xFFFF} }, /* RX_4 */
  533. { {0xFFFF} }, /* RX_5 */
  534. { {0xFFFF} }, /* RX_6 */
  535. { {0xFFFF} }, /* RX_7 */
  536. },
  537. {
  538. { {0, 4, 0xFFFF} }, /* TX_0 */
  539. { {8, 12, 0xFFFF} }, /* TX_1 */
  540. { {16, 20, 0xFFFF} }, /* TX_2 */
  541. { {24, 28, 0xFFFF} }, /* TX_3 */
  542. { {0xFFFF} }, /* TX_4 */
  543. { {0xFFFF} }, /* TX_5 */
  544. { {0xFFFF} }, /* TX_6 */
  545. { {0xFFFF} }, /* TX_7 */
  546. },
  547. };
  548. static struct tdm_dev_config sen_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  549. { /* SEN TDM */
  550. { {0, 4, 0xFFFF} }, /* RX_0 */
  551. { {8, 12, 0xFFFF} }, /* RX_1 */
  552. { {16, 20, 0xFFFF} }, /* RX_2 */
  553. { {24, 28, 0xFFFF} }, /* RX_3 */
  554. { {0xFFFF} }, /* RX_4 */
  555. { {0xFFFF} }, /* RX_5 */
  556. { {0xFFFF} }, /* RX_6 */
  557. { {0xFFFF} }, /* RX_7 */
  558. },
  559. {
  560. { {0, 4, 0xFFFF} }, /* TX_0 */
  561. { {8, 12, 0xFFFF} }, /* TX_1 */
  562. { {16, 20, 0xFFFF} }, /* TX_2 */
  563. { {24, 28, 0xFFFF} }, /* TX_3 */
  564. { {0xFFFF} }, /* TX_4 */
  565. { {0xFFFF} }, /* TX_5 */
  566. { {0xFFFF} }, /* TX_6 */
  567. { {0xFFFF} }, /* TX_7 */
  568. },
  569. };
  570. static void *tdm_cfg[TDM_INTERFACE_MAX] = {
  571. pri_tdm_dev_config,
  572. sec_tdm_dev_config,
  573. tert_tdm_dev_config,
  574. quat_tdm_dev_config,
  575. quin_tdm_dev_config,
  576. sen_tdm_dev_config,
  577. };
  578. /* Default configuration of Codec DMA Interface RX */
  579. static struct dev_config cdc_dma_rx_cfg[] = {
  580. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  581. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  582. [RX_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  583. [RX_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  584. [RX_CDC_DMA_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  585. [RX_CDC_DMA_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  586. [RX_CDC_DMA_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  587. };
  588. /* Default configuration of Codec DMA Interface TX */
  589. static struct dev_config cdc_dma_tx_cfg[] = {
  590. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  591. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  592. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  593. [TX_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  594. [TX_CDC_DMA_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  595. [TX_CDC_DMA_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  596. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  597. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  598. [VA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  599. };
  600. static struct dev_config afe_loopback_tx_cfg[] = {
  601. [AFE_LOOPBACK_TX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  602. };
  603. static int msm_vi_feed_tx_ch = 2;
  604. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  605. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  606. "S32_LE"};
  607. static char const *cdc80_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"};
  608. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  609. "Six", "Seven", "Eight"};
  610. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  611. "KHZ_16", "KHZ_22P05",
  612. "KHZ_32", "KHZ_44P1", "KHZ_48",
  613. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  614. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  615. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  616. "Five", "Six", "Seven",
  617. "Eight"};
  618. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  619. "KHZ_48", "KHZ_176P4",
  620. "KHZ_352P8"};
  621. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  622. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  623. "Five", "Six", "Seven", "Eight"};
  624. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  625. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  626. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  627. "KHZ_48", "KHZ_96", "KHZ_192"};
  628. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  629. "Five", "Six", "Seven",
  630. "Eight"};
  631. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  632. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  633. "Five", "Six", "Seven",
  634. "Eight"};
  635. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  636. "KHZ_16", "KHZ_22P05",
  637. "KHZ_32", "KHZ_44P1", "KHZ_48",
  638. "KHZ_88P2", "KHZ_96",
  639. "KHZ_176P4", "KHZ_192",
  640. "KHZ_352P8", "KHZ_384"};
  641. static char const *cdc80_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  642. "KHZ_16", "KHZ_22P05",
  643. "KHZ_32", "KHZ_44P1", "KHZ_48",
  644. "KHZ_88P2", "KHZ_96",
  645. "KHZ_176P4", "KHZ_192"};
  646. static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE",
  647. "S24_3LE"};
  648. static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
  649. "KHZ_192", "KHZ_32", "KHZ_44P1",
  650. "KHZ_88P2", "KHZ_176P4"};
  651. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  652. "KHZ_44P1", "KHZ_48",
  653. "KHZ_88P2", "KHZ_96"};
  654. static char const *bt_sample_rate_rx_text[] = {"KHZ_8", "KHZ_16",
  655. "KHZ_44P1", "KHZ_48",
  656. "KHZ_88P2", "KHZ_96"};
  657. static char const *bt_sample_rate_tx_text[] = {"KHZ_8", "KHZ_16",
  658. "KHZ_44P1", "KHZ_48",
  659. "KHZ_88P2", "KHZ_96"};
  660. static const char *const afe_loopback_tx_ch_text[] = {"One", "Two"};
  661. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  662. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  663. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  664. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  665. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  666. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  667. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  668. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  669. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  670. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  671. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  672. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  673. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  674. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  675. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  676. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  677. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  678. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  679. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  680. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  681. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  682. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  683. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  684. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  685. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  686. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  687. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  688. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  689. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  690. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  691. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  692. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  693. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  694. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_sample_rate, mi2s_rate_text);
  695. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  696. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  697. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  698. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  699. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  700. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_sample_rate, mi2s_rate_text);
  701. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  702. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  703. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  704. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  705. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  706. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  707. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  708. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_chs, mi2s_ch_text);
  709. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  710. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  711. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  712. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  713. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  714. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_chs, mi2s_ch_text);
  715. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  716. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  717. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  718. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  719. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_chs, cdc_dma_rx_ch_text);
  720. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_chs, cdc_dma_rx_ch_text);
  721. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_chs, cdc_dma_rx_ch_text);
  722. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  723. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  724. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  725. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  726. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_chs, cdc_dma_tx_ch_text);
  727. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_chs, cdc_dma_tx_ch_text);
  728. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  729. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  730. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  731. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  732. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  733. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  734. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  735. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_format, bit_format_text);
  736. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_format, bit_format_text);
  737. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_format, bit_format_text);
  738. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  739. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  740. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_format, bit_format_text);
  741. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  742. cdc_dma_sample_rate_text);
  743. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  744. cdc_dma_sample_rate_text);
  745. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  746. cdc_dma_sample_rate_text);
  747. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  748. cdc_dma_sample_rate_text);
  749. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  750. cdc_dma_sample_rate_text);
  751. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_sample_rate,
  752. cdc_dma_sample_rate_text);
  753. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_sample_rate,
  754. cdc_dma_sample_rate_text);
  755. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_sample_rate,
  756. cdc_dma_sample_rate_text);
  757. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  758. cdc_dma_sample_rate_text);
  759. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  760. cdc_dma_sample_rate_text);
  761. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_sample_rate,
  762. cdc_dma_sample_rate_text);
  763. /* WCD9380 */
  764. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_0_format, cdc80_bit_format_text);
  765. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_1_format, cdc80_bit_format_text);
  766. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_2_format, cdc80_bit_format_text);
  767. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_3_format, cdc80_bit_format_text);
  768. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_5_format, cdc80_bit_format_text);
  769. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_0_sample_rate,
  770. cdc80_dma_sample_rate_text);
  771. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_1_sample_rate,
  772. cdc80_dma_sample_rate_text);
  773. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_2_sample_rate,
  774. cdc80_dma_sample_rate_text);
  775. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_3_sample_rate,
  776. cdc80_dma_sample_rate_text);
  777. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_5_sample_rate,
  778. cdc80_dma_sample_rate_text);
  779. /* WCD9385 */
  780. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_0_format, bit_format_text);
  781. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_1_format, bit_format_text);
  782. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_2_format, bit_format_text);
  783. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_3_format, bit_format_text);
  784. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_5_format, bit_format_text);
  785. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_0_sample_rate,
  786. cdc_dma_sample_rate_text);
  787. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_1_sample_rate,
  788. cdc_dma_sample_rate_text);
  789. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_2_sample_rate,
  790. cdc_dma_sample_rate_text);
  791. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_3_sample_rate,
  792. cdc_dma_sample_rate_text);
  793. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_5_sample_rate,
  794. cdc_dma_sample_rate_text);
  795. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
  796. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
  797. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
  798. ext_disp_sample_rate_text);
  799. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  800. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_rx, bt_sample_rate_rx_text);
  801. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_tx, bt_sample_rate_tx_text);
  802. static SOC_ENUM_SINGLE_EXT_DECL(afe_loopback_tx_chs, afe_loopback_tx_ch_text);
  803. static bool is_initial_boot;
  804. static bool codec_reg_done;
  805. static struct snd_soc_aux_dev *msm_aux_dev;
  806. static struct snd_soc_codec_conf *msm_codec_conf;
  807. static struct snd_soc_card snd_soc_card_kona_msm;
  808. static int dmic_0_1_gpio_cnt;
  809. static int dmic_2_3_gpio_cnt;
  810. static int dmic_4_5_gpio_cnt;
  811. static void *def_wcd_mbhc_cal(void);
  812. /*
  813. * Need to report LINEIN
  814. * if R/L channel impedance is larger than 5K ohm
  815. */
  816. static struct wcd_mbhc_config wcd_mbhc_cfg = {
  817. .read_fw_bin = false,
  818. .calibration = NULL,
  819. .detect_extn_cable = true,
  820. .mono_stero_detection = false,
  821. .swap_gnd_mic = NULL,
  822. .hs_ext_micbias = true,
  823. .key_code[0] = KEY_MEDIA,
  824. .key_code[1] = KEY_VOICECOMMAND,
  825. .key_code[2] = KEY_VOLUMEUP,
  826. .key_code[3] = KEY_VOLUMEDOWN,
  827. .key_code[4] = 0,
  828. .key_code[5] = 0,
  829. .key_code[6] = 0,
  830. .key_code[7] = 0,
  831. .linein_th = 5000,
  832. .moisture_en = false,
  833. .mbhc_micbias = MIC_BIAS_2,
  834. .anc_micbias = MIC_BIAS_2,
  835. .enable_anc_mic_detect = false,
  836. .moisture_duty_cycle_en = true,
  837. };
  838. static inline int param_is_mask(int p)
  839. {
  840. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  841. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  842. }
  843. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  844. int n)
  845. {
  846. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  847. }
  848. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  849. unsigned int bit)
  850. {
  851. if (bit >= SNDRV_MASK_MAX)
  852. return;
  853. if (param_is_mask(n)) {
  854. struct snd_mask *m = param_to_mask(p, n);
  855. m->bits[0] = 0;
  856. m->bits[1] = 0;
  857. m->bits[bit >> 5] |= (1 << (bit & 31));
  858. }
  859. }
  860. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  861. struct snd_ctl_elem_value *ucontrol)
  862. {
  863. int sample_rate_val = 0;
  864. switch (usb_rx_cfg.sample_rate) {
  865. case SAMPLING_RATE_384KHZ:
  866. sample_rate_val = 12;
  867. break;
  868. case SAMPLING_RATE_352P8KHZ:
  869. sample_rate_val = 11;
  870. break;
  871. case SAMPLING_RATE_192KHZ:
  872. sample_rate_val = 10;
  873. break;
  874. case SAMPLING_RATE_176P4KHZ:
  875. sample_rate_val = 9;
  876. break;
  877. case SAMPLING_RATE_96KHZ:
  878. sample_rate_val = 8;
  879. break;
  880. case SAMPLING_RATE_88P2KHZ:
  881. sample_rate_val = 7;
  882. break;
  883. case SAMPLING_RATE_48KHZ:
  884. sample_rate_val = 6;
  885. break;
  886. case SAMPLING_RATE_44P1KHZ:
  887. sample_rate_val = 5;
  888. break;
  889. case SAMPLING_RATE_32KHZ:
  890. sample_rate_val = 4;
  891. break;
  892. case SAMPLING_RATE_22P05KHZ:
  893. sample_rate_val = 3;
  894. break;
  895. case SAMPLING_RATE_16KHZ:
  896. sample_rate_val = 2;
  897. break;
  898. case SAMPLING_RATE_11P025KHZ:
  899. sample_rate_val = 1;
  900. break;
  901. case SAMPLING_RATE_8KHZ:
  902. default:
  903. sample_rate_val = 0;
  904. break;
  905. }
  906. ucontrol->value.integer.value[0] = sample_rate_val;
  907. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  908. usb_rx_cfg.sample_rate);
  909. return 0;
  910. }
  911. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  912. struct snd_ctl_elem_value *ucontrol)
  913. {
  914. switch (ucontrol->value.integer.value[0]) {
  915. case 12:
  916. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  917. break;
  918. case 11:
  919. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  920. break;
  921. case 10:
  922. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  923. break;
  924. case 9:
  925. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  926. break;
  927. case 8:
  928. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  929. break;
  930. case 7:
  931. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  932. break;
  933. case 6:
  934. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  935. break;
  936. case 5:
  937. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  938. break;
  939. case 4:
  940. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  941. break;
  942. case 3:
  943. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  944. break;
  945. case 2:
  946. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  947. break;
  948. case 1:
  949. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  950. break;
  951. case 0:
  952. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  953. break;
  954. default:
  955. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  956. break;
  957. }
  958. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  959. __func__, ucontrol->value.integer.value[0],
  960. usb_rx_cfg.sample_rate);
  961. return 0;
  962. }
  963. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  964. struct snd_ctl_elem_value *ucontrol)
  965. {
  966. int sample_rate_val = 0;
  967. switch (usb_tx_cfg.sample_rate) {
  968. case SAMPLING_RATE_384KHZ:
  969. sample_rate_val = 12;
  970. break;
  971. case SAMPLING_RATE_352P8KHZ:
  972. sample_rate_val = 11;
  973. break;
  974. case SAMPLING_RATE_192KHZ:
  975. sample_rate_val = 10;
  976. break;
  977. case SAMPLING_RATE_176P4KHZ:
  978. sample_rate_val = 9;
  979. break;
  980. case SAMPLING_RATE_96KHZ:
  981. sample_rate_val = 8;
  982. break;
  983. case SAMPLING_RATE_88P2KHZ:
  984. sample_rate_val = 7;
  985. break;
  986. case SAMPLING_RATE_48KHZ:
  987. sample_rate_val = 6;
  988. break;
  989. case SAMPLING_RATE_44P1KHZ:
  990. sample_rate_val = 5;
  991. break;
  992. case SAMPLING_RATE_32KHZ:
  993. sample_rate_val = 4;
  994. break;
  995. case SAMPLING_RATE_22P05KHZ:
  996. sample_rate_val = 3;
  997. break;
  998. case SAMPLING_RATE_16KHZ:
  999. sample_rate_val = 2;
  1000. break;
  1001. case SAMPLING_RATE_11P025KHZ:
  1002. sample_rate_val = 1;
  1003. break;
  1004. case SAMPLING_RATE_8KHZ:
  1005. sample_rate_val = 0;
  1006. break;
  1007. default:
  1008. sample_rate_val = 6;
  1009. break;
  1010. }
  1011. ucontrol->value.integer.value[0] = sample_rate_val;
  1012. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1013. usb_tx_cfg.sample_rate);
  1014. return 0;
  1015. }
  1016. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1017. struct snd_ctl_elem_value *ucontrol)
  1018. {
  1019. switch (ucontrol->value.integer.value[0]) {
  1020. case 12:
  1021. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1022. break;
  1023. case 11:
  1024. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1025. break;
  1026. case 10:
  1027. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1028. break;
  1029. case 9:
  1030. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1031. break;
  1032. case 8:
  1033. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1034. break;
  1035. case 7:
  1036. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1037. break;
  1038. case 6:
  1039. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1040. break;
  1041. case 5:
  1042. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1043. break;
  1044. case 4:
  1045. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1046. break;
  1047. case 3:
  1048. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1049. break;
  1050. case 2:
  1051. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1052. break;
  1053. case 1:
  1054. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1055. break;
  1056. case 0:
  1057. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1058. break;
  1059. default:
  1060. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1061. break;
  1062. }
  1063. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1064. __func__, ucontrol->value.integer.value[0],
  1065. usb_tx_cfg.sample_rate);
  1066. return 0;
  1067. }
  1068. static int afe_loopback_tx_ch_get(struct snd_kcontrol *kcontrol,
  1069. struct snd_ctl_elem_value *ucontrol)
  1070. {
  1071. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  1072. afe_loopback_tx_cfg[0].channels);
  1073. ucontrol->value.enumerated.item[0] =
  1074. afe_loopback_tx_cfg[0].channels - 1;
  1075. return 0;
  1076. }
  1077. static int afe_loopback_tx_ch_put(struct snd_kcontrol *kcontrol,
  1078. struct snd_ctl_elem_value *ucontrol)
  1079. {
  1080. afe_loopback_tx_cfg[0].channels =
  1081. ucontrol->value.enumerated.item[0] + 1;
  1082. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  1083. afe_loopback_tx_cfg[0].channels);
  1084. return 1;
  1085. }
  1086. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1087. struct snd_ctl_elem_value *ucontrol)
  1088. {
  1089. switch (usb_rx_cfg.bit_format) {
  1090. case SNDRV_PCM_FORMAT_S32_LE:
  1091. ucontrol->value.integer.value[0] = 3;
  1092. break;
  1093. case SNDRV_PCM_FORMAT_S24_3LE:
  1094. ucontrol->value.integer.value[0] = 2;
  1095. break;
  1096. case SNDRV_PCM_FORMAT_S24_LE:
  1097. ucontrol->value.integer.value[0] = 1;
  1098. break;
  1099. case SNDRV_PCM_FORMAT_S16_LE:
  1100. default:
  1101. ucontrol->value.integer.value[0] = 0;
  1102. break;
  1103. }
  1104. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1105. __func__, usb_rx_cfg.bit_format,
  1106. ucontrol->value.integer.value[0]);
  1107. return 0;
  1108. }
  1109. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1110. struct snd_ctl_elem_value *ucontrol)
  1111. {
  1112. int rc = 0;
  1113. switch (ucontrol->value.integer.value[0]) {
  1114. case 3:
  1115. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1116. break;
  1117. case 2:
  1118. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1119. break;
  1120. case 1:
  1121. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1122. break;
  1123. case 0:
  1124. default:
  1125. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1126. break;
  1127. }
  1128. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1129. __func__, usb_rx_cfg.bit_format,
  1130. ucontrol->value.integer.value[0]);
  1131. return rc;
  1132. }
  1133. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1134. struct snd_ctl_elem_value *ucontrol)
  1135. {
  1136. switch (usb_tx_cfg.bit_format) {
  1137. case SNDRV_PCM_FORMAT_S32_LE:
  1138. ucontrol->value.integer.value[0] = 3;
  1139. break;
  1140. case SNDRV_PCM_FORMAT_S24_3LE:
  1141. ucontrol->value.integer.value[0] = 2;
  1142. break;
  1143. case SNDRV_PCM_FORMAT_S24_LE:
  1144. ucontrol->value.integer.value[0] = 1;
  1145. break;
  1146. case SNDRV_PCM_FORMAT_S16_LE:
  1147. default:
  1148. ucontrol->value.integer.value[0] = 0;
  1149. break;
  1150. }
  1151. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1152. __func__, usb_tx_cfg.bit_format,
  1153. ucontrol->value.integer.value[0]);
  1154. return 0;
  1155. }
  1156. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1157. struct snd_ctl_elem_value *ucontrol)
  1158. {
  1159. int rc = 0;
  1160. switch (ucontrol->value.integer.value[0]) {
  1161. case 3:
  1162. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1163. break;
  1164. case 2:
  1165. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1166. break;
  1167. case 1:
  1168. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1169. break;
  1170. case 0:
  1171. default:
  1172. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1173. break;
  1174. }
  1175. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1176. __func__, usb_tx_cfg.bit_format,
  1177. ucontrol->value.integer.value[0]);
  1178. return rc;
  1179. }
  1180. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1181. struct snd_ctl_elem_value *ucontrol)
  1182. {
  1183. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1184. usb_rx_cfg.channels);
  1185. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1186. return 0;
  1187. }
  1188. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1189. struct snd_ctl_elem_value *ucontrol)
  1190. {
  1191. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1192. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1193. return 1;
  1194. }
  1195. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1196. struct snd_ctl_elem_value *ucontrol)
  1197. {
  1198. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1199. usb_tx_cfg.channels);
  1200. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1201. return 0;
  1202. }
  1203. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1204. struct snd_ctl_elem_value *ucontrol)
  1205. {
  1206. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1207. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1208. return 1;
  1209. }
  1210. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  1211. struct snd_ctl_elem_value *ucontrol)
  1212. {
  1213. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  1214. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  1215. ucontrol->value.integer.value[0]);
  1216. return 0;
  1217. }
  1218. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  1219. struct snd_ctl_elem_value *ucontrol)
  1220. {
  1221. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  1222. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  1223. return 1;
  1224. }
  1225. static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
  1226. {
  1227. int idx = 0;
  1228. if (strnstr(kcontrol->id.name, "Display Port RX",
  1229. sizeof("Display Port RX"))) {
  1230. idx = EXT_DISP_RX_IDX_DP;
  1231. } else if (strnstr(kcontrol->id.name, "Display Port1 RX",
  1232. sizeof("Display Port1 RX"))) {
  1233. idx = EXT_DISP_RX_IDX_DP1;
  1234. } else {
  1235. pr_err("%s: unsupported BE: %s\n",
  1236. __func__, kcontrol->id.name);
  1237. idx = -EINVAL;
  1238. }
  1239. return idx;
  1240. }
  1241. static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
  1242. struct snd_ctl_elem_value *ucontrol)
  1243. {
  1244. int idx = ext_disp_get_port_idx(kcontrol);
  1245. if (idx < 0)
  1246. return idx;
  1247. switch (ext_disp_rx_cfg[idx].bit_format) {
  1248. case SNDRV_PCM_FORMAT_S24_3LE:
  1249. ucontrol->value.integer.value[0] = 2;
  1250. break;
  1251. case SNDRV_PCM_FORMAT_S24_LE:
  1252. ucontrol->value.integer.value[0] = 1;
  1253. break;
  1254. case SNDRV_PCM_FORMAT_S16_LE:
  1255. default:
  1256. ucontrol->value.integer.value[0] = 0;
  1257. break;
  1258. }
  1259. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1260. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1261. ucontrol->value.integer.value[0]);
  1262. return 0;
  1263. }
  1264. static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
  1265. struct snd_ctl_elem_value *ucontrol)
  1266. {
  1267. int idx = ext_disp_get_port_idx(kcontrol);
  1268. if (idx < 0)
  1269. return idx;
  1270. switch (ucontrol->value.integer.value[0]) {
  1271. case 2:
  1272. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1273. break;
  1274. case 1:
  1275. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1276. break;
  1277. case 0:
  1278. default:
  1279. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1280. break;
  1281. }
  1282. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1283. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1284. ucontrol->value.integer.value[0]);
  1285. return 0;
  1286. }
  1287. static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
  1288. struct snd_ctl_elem_value *ucontrol)
  1289. {
  1290. int idx = ext_disp_get_port_idx(kcontrol);
  1291. if (idx < 0)
  1292. return idx;
  1293. ucontrol->value.integer.value[0] =
  1294. ext_disp_rx_cfg[idx].channels - 2;
  1295. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1296. idx, ext_disp_rx_cfg[idx].channels);
  1297. return 0;
  1298. }
  1299. static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
  1300. struct snd_ctl_elem_value *ucontrol)
  1301. {
  1302. int idx = ext_disp_get_port_idx(kcontrol);
  1303. if (idx < 0)
  1304. return idx;
  1305. ext_disp_rx_cfg[idx].channels =
  1306. ucontrol->value.integer.value[0] + 2;
  1307. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1308. idx, ext_disp_rx_cfg[idx].channels);
  1309. return 1;
  1310. }
  1311. static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1312. struct snd_ctl_elem_value *ucontrol)
  1313. {
  1314. int sample_rate_val;
  1315. int idx = ext_disp_get_port_idx(kcontrol);
  1316. if (idx < 0)
  1317. return idx;
  1318. switch (ext_disp_rx_cfg[idx].sample_rate) {
  1319. case SAMPLING_RATE_176P4KHZ:
  1320. sample_rate_val = 6;
  1321. break;
  1322. case SAMPLING_RATE_88P2KHZ:
  1323. sample_rate_val = 5;
  1324. break;
  1325. case SAMPLING_RATE_44P1KHZ:
  1326. sample_rate_val = 4;
  1327. break;
  1328. case SAMPLING_RATE_32KHZ:
  1329. sample_rate_val = 3;
  1330. break;
  1331. case SAMPLING_RATE_192KHZ:
  1332. sample_rate_val = 2;
  1333. break;
  1334. case SAMPLING_RATE_96KHZ:
  1335. sample_rate_val = 1;
  1336. break;
  1337. case SAMPLING_RATE_48KHZ:
  1338. default:
  1339. sample_rate_val = 0;
  1340. break;
  1341. }
  1342. ucontrol->value.integer.value[0] = sample_rate_val;
  1343. pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
  1344. idx, ext_disp_rx_cfg[idx].sample_rate);
  1345. return 0;
  1346. }
  1347. static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1348. struct snd_ctl_elem_value *ucontrol)
  1349. {
  1350. int idx = ext_disp_get_port_idx(kcontrol);
  1351. if (idx < 0)
  1352. return idx;
  1353. switch (ucontrol->value.integer.value[0]) {
  1354. case 6:
  1355. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_176P4KHZ;
  1356. break;
  1357. case 5:
  1358. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_88P2KHZ;
  1359. break;
  1360. case 4:
  1361. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_44P1KHZ;
  1362. break;
  1363. case 3:
  1364. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_32KHZ;
  1365. break;
  1366. case 2:
  1367. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
  1368. break;
  1369. case 1:
  1370. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
  1371. break;
  1372. case 0:
  1373. default:
  1374. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
  1375. break;
  1376. }
  1377. pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
  1378. __func__, ucontrol->value.integer.value[0], idx,
  1379. ext_disp_rx_cfg[idx].sample_rate);
  1380. return 0;
  1381. }
  1382. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1383. struct snd_ctl_elem_value *ucontrol)
  1384. {
  1385. pr_debug("%s: proxy_rx channels = %d\n",
  1386. __func__, proxy_rx_cfg.channels);
  1387. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1388. return 0;
  1389. }
  1390. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1391. struct snd_ctl_elem_value *ucontrol)
  1392. {
  1393. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1394. pr_debug("%s: proxy_rx channels = %d\n",
  1395. __func__, proxy_rx_cfg.channels);
  1396. return 1;
  1397. }
  1398. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1399. struct tdm_port *port)
  1400. {
  1401. if (port) {
  1402. if (strnstr(kcontrol->id.name, "PRI",
  1403. sizeof(kcontrol->id.name))) {
  1404. port->mode = TDM_PRI;
  1405. } else if (strnstr(kcontrol->id.name, "SEC",
  1406. sizeof(kcontrol->id.name))) {
  1407. port->mode = TDM_SEC;
  1408. } else if (strnstr(kcontrol->id.name, "TERT",
  1409. sizeof(kcontrol->id.name))) {
  1410. port->mode = TDM_TERT;
  1411. } else if (strnstr(kcontrol->id.name, "QUAT",
  1412. sizeof(kcontrol->id.name))) {
  1413. port->mode = TDM_QUAT;
  1414. } else if (strnstr(kcontrol->id.name, "QUIN",
  1415. sizeof(kcontrol->id.name))) {
  1416. port->mode = TDM_QUIN;
  1417. } else if (strnstr(kcontrol->id.name, "SEN",
  1418. sizeof(kcontrol->id.name))) {
  1419. port->mode = TDM_SEN;
  1420. } else {
  1421. pr_err("%s: unsupported mode in: %s\n",
  1422. __func__, kcontrol->id.name);
  1423. return -EINVAL;
  1424. }
  1425. if (strnstr(kcontrol->id.name, "RX_0",
  1426. sizeof(kcontrol->id.name)) ||
  1427. strnstr(kcontrol->id.name, "TX_0",
  1428. sizeof(kcontrol->id.name))) {
  1429. port->channel = TDM_0;
  1430. } else if (strnstr(kcontrol->id.name, "RX_1",
  1431. sizeof(kcontrol->id.name)) ||
  1432. strnstr(kcontrol->id.name, "TX_1",
  1433. sizeof(kcontrol->id.name))) {
  1434. port->channel = TDM_1;
  1435. } else if (strnstr(kcontrol->id.name, "RX_2",
  1436. sizeof(kcontrol->id.name)) ||
  1437. strnstr(kcontrol->id.name, "TX_2",
  1438. sizeof(kcontrol->id.name))) {
  1439. port->channel = TDM_2;
  1440. } else if (strnstr(kcontrol->id.name, "RX_3",
  1441. sizeof(kcontrol->id.name)) ||
  1442. strnstr(kcontrol->id.name, "TX_3",
  1443. sizeof(kcontrol->id.name))) {
  1444. port->channel = TDM_3;
  1445. } else if (strnstr(kcontrol->id.name, "RX_4",
  1446. sizeof(kcontrol->id.name)) ||
  1447. strnstr(kcontrol->id.name, "TX_4",
  1448. sizeof(kcontrol->id.name))) {
  1449. port->channel = TDM_4;
  1450. } else if (strnstr(kcontrol->id.name, "RX_5",
  1451. sizeof(kcontrol->id.name)) ||
  1452. strnstr(kcontrol->id.name, "TX_5",
  1453. sizeof(kcontrol->id.name))) {
  1454. port->channel = TDM_5;
  1455. } else if (strnstr(kcontrol->id.name, "RX_6",
  1456. sizeof(kcontrol->id.name)) ||
  1457. strnstr(kcontrol->id.name, "TX_6",
  1458. sizeof(kcontrol->id.name))) {
  1459. port->channel = TDM_6;
  1460. } else if (strnstr(kcontrol->id.name, "RX_7",
  1461. sizeof(kcontrol->id.name)) ||
  1462. strnstr(kcontrol->id.name, "TX_7",
  1463. sizeof(kcontrol->id.name))) {
  1464. port->channel = TDM_7;
  1465. } else {
  1466. pr_err("%s: unsupported channel in: %s\n",
  1467. __func__, kcontrol->id.name);
  1468. return -EINVAL;
  1469. }
  1470. } else {
  1471. return -EINVAL;
  1472. }
  1473. return 0;
  1474. }
  1475. static int tdm_get_sample_rate(int value)
  1476. {
  1477. int sample_rate = 0;
  1478. switch (value) {
  1479. case 0:
  1480. sample_rate = SAMPLING_RATE_8KHZ;
  1481. break;
  1482. case 1:
  1483. sample_rate = SAMPLING_RATE_16KHZ;
  1484. break;
  1485. case 2:
  1486. sample_rate = SAMPLING_RATE_32KHZ;
  1487. break;
  1488. case 3:
  1489. sample_rate = SAMPLING_RATE_48KHZ;
  1490. break;
  1491. case 4:
  1492. sample_rate = SAMPLING_RATE_176P4KHZ;
  1493. break;
  1494. case 5:
  1495. sample_rate = SAMPLING_RATE_352P8KHZ;
  1496. break;
  1497. default:
  1498. sample_rate = SAMPLING_RATE_48KHZ;
  1499. break;
  1500. }
  1501. return sample_rate;
  1502. }
  1503. static int tdm_get_sample_rate_val(int sample_rate)
  1504. {
  1505. int sample_rate_val = 0;
  1506. switch (sample_rate) {
  1507. case SAMPLING_RATE_8KHZ:
  1508. sample_rate_val = 0;
  1509. break;
  1510. case SAMPLING_RATE_16KHZ:
  1511. sample_rate_val = 1;
  1512. break;
  1513. case SAMPLING_RATE_32KHZ:
  1514. sample_rate_val = 2;
  1515. break;
  1516. case SAMPLING_RATE_48KHZ:
  1517. sample_rate_val = 3;
  1518. break;
  1519. case SAMPLING_RATE_176P4KHZ:
  1520. sample_rate_val = 4;
  1521. break;
  1522. case SAMPLING_RATE_352P8KHZ:
  1523. sample_rate_val = 5;
  1524. break;
  1525. default:
  1526. sample_rate_val = 3;
  1527. break;
  1528. }
  1529. return sample_rate_val;
  1530. }
  1531. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1532. struct snd_ctl_elem_value *ucontrol)
  1533. {
  1534. struct tdm_port port;
  1535. int ret = tdm_get_port_idx(kcontrol, &port);
  1536. if (ret) {
  1537. pr_err("%s: unsupported control: %s\n",
  1538. __func__, kcontrol->id.name);
  1539. } else {
  1540. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1541. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1542. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1543. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1544. ucontrol->value.enumerated.item[0]);
  1545. }
  1546. return ret;
  1547. }
  1548. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1549. struct snd_ctl_elem_value *ucontrol)
  1550. {
  1551. struct tdm_port port;
  1552. int ret = tdm_get_port_idx(kcontrol, &port);
  1553. if (ret) {
  1554. pr_err("%s: unsupported control: %s\n",
  1555. __func__, kcontrol->id.name);
  1556. } else {
  1557. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1558. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1559. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1560. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1561. ucontrol->value.enumerated.item[0]);
  1562. }
  1563. return ret;
  1564. }
  1565. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1566. struct snd_ctl_elem_value *ucontrol)
  1567. {
  1568. struct tdm_port port;
  1569. int ret = tdm_get_port_idx(kcontrol, &port);
  1570. if (ret) {
  1571. pr_err("%s: unsupported control: %s\n",
  1572. __func__, kcontrol->id.name);
  1573. } else {
  1574. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1575. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1576. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1577. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1578. ucontrol->value.enumerated.item[0]);
  1579. }
  1580. return ret;
  1581. }
  1582. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1583. struct snd_ctl_elem_value *ucontrol)
  1584. {
  1585. struct tdm_port port;
  1586. int ret = tdm_get_port_idx(kcontrol, &port);
  1587. if (ret) {
  1588. pr_err("%s: unsupported control: %s\n",
  1589. __func__, kcontrol->id.name);
  1590. } else {
  1591. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1592. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1593. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1594. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1595. ucontrol->value.enumerated.item[0]);
  1596. }
  1597. return ret;
  1598. }
  1599. static int tdm_get_format(int value)
  1600. {
  1601. int format = 0;
  1602. switch (value) {
  1603. case 0:
  1604. format = SNDRV_PCM_FORMAT_S16_LE;
  1605. break;
  1606. case 1:
  1607. format = SNDRV_PCM_FORMAT_S24_LE;
  1608. break;
  1609. case 2:
  1610. format = SNDRV_PCM_FORMAT_S32_LE;
  1611. break;
  1612. default:
  1613. format = SNDRV_PCM_FORMAT_S16_LE;
  1614. break;
  1615. }
  1616. return format;
  1617. }
  1618. static int tdm_get_format_val(int format)
  1619. {
  1620. int value = 0;
  1621. switch (format) {
  1622. case SNDRV_PCM_FORMAT_S16_LE:
  1623. value = 0;
  1624. break;
  1625. case SNDRV_PCM_FORMAT_S24_LE:
  1626. value = 1;
  1627. break;
  1628. case SNDRV_PCM_FORMAT_S32_LE:
  1629. value = 2;
  1630. break;
  1631. default:
  1632. value = 0;
  1633. break;
  1634. }
  1635. return value;
  1636. }
  1637. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1638. struct snd_ctl_elem_value *ucontrol)
  1639. {
  1640. struct tdm_port port;
  1641. int ret = tdm_get_port_idx(kcontrol, &port);
  1642. if (ret) {
  1643. pr_err("%s: unsupported control: %s\n",
  1644. __func__, kcontrol->id.name);
  1645. } else {
  1646. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1647. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1648. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1649. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1650. ucontrol->value.enumerated.item[0]);
  1651. }
  1652. return ret;
  1653. }
  1654. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1655. struct snd_ctl_elem_value *ucontrol)
  1656. {
  1657. struct tdm_port port;
  1658. int ret = tdm_get_port_idx(kcontrol, &port);
  1659. if (ret) {
  1660. pr_err("%s: unsupported control: %s\n",
  1661. __func__, kcontrol->id.name);
  1662. } else {
  1663. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1664. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1665. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1666. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1667. ucontrol->value.enumerated.item[0]);
  1668. }
  1669. return ret;
  1670. }
  1671. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  1672. struct snd_ctl_elem_value *ucontrol)
  1673. {
  1674. struct tdm_port port;
  1675. int ret = tdm_get_port_idx(kcontrol, &port);
  1676. if (ret) {
  1677. pr_err("%s: unsupported control: %s\n",
  1678. __func__, kcontrol->id.name);
  1679. } else {
  1680. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1681. tdm_tx_cfg[port.mode][port.channel].bit_format);
  1682. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1683. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1684. ucontrol->value.enumerated.item[0]);
  1685. }
  1686. return ret;
  1687. }
  1688. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  1689. struct snd_ctl_elem_value *ucontrol)
  1690. {
  1691. struct tdm_port port;
  1692. int ret = tdm_get_port_idx(kcontrol, &port);
  1693. if (ret) {
  1694. pr_err("%s: unsupported control: %s\n",
  1695. __func__, kcontrol->id.name);
  1696. } else {
  1697. tdm_tx_cfg[port.mode][port.channel].bit_format =
  1698. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1699. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1700. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1701. ucontrol->value.enumerated.item[0]);
  1702. }
  1703. return ret;
  1704. }
  1705. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  1706. struct snd_ctl_elem_value *ucontrol)
  1707. {
  1708. struct tdm_port port;
  1709. int ret = tdm_get_port_idx(kcontrol, &port);
  1710. if (ret) {
  1711. pr_err("%s: unsupported control: %s\n",
  1712. __func__, kcontrol->id.name);
  1713. } else {
  1714. ucontrol->value.enumerated.item[0] =
  1715. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  1716. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1717. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  1718. ucontrol->value.enumerated.item[0]);
  1719. }
  1720. return ret;
  1721. }
  1722. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  1723. struct snd_ctl_elem_value *ucontrol)
  1724. {
  1725. struct tdm_port port;
  1726. int ret = tdm_get_port_idx(kcontrol, &port);
  1727. if (ret) {
  1728. pr_err("%s: unsupported control: %s\n",
  1729. __func__, kcontrol->id.name);
  1730. } else {
  1731. tdm_rx_cfg[port.mode][port.channel].channels =
  1732. ucontrol->value.enumerated.item[0] + 1;
  1733. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1734. tdm_rx_cfg[port.mode][port.channel].channels,
  1735. ucontrol->value.enumerated.item[0] + 1);
  1736. }
  1737. return ret;
  1738. }
  1739. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  1740. struct snd_ctl_elem_value *ucontrol)
  1741. {
  1742. struct tdm_port port;
  1743. int ret = tdm_get_port_idx(kcontrol, &port);
  1744. if (ret) {
  1745. pr_err("%s: unsupported control: %s\n",
  1746. __func__, kcontrol->id.name);
  1747. } else {
  1748. ucontrol->value.enumerated.item[0] =
  1749. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  1750. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1751. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  1752. ucontrol->value.enumerated.item[0]);
  1753. }
  1754. return ret;
  1755. }
  1756. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  1757. struct snd_ctl_elem_value *ucontrol)
  1758. {
  1759. struct tdm_port port;
  1760. int ret = tdm_get_port_idx(kcontrol, &port);
  1761. if (ret) {
  1762. pr_err("%s: unsupported control: %s\n",
  1763. __func__, kcontrol->id.name);
  1764. } else {
  1765. tdm_tx_cfg[port.mode][port.channel].channels =
  1766. ucontrol->value.enumerated.item[0] + 1;
  1767. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1768. tdm_tx_cfg[port.mode][port.channel].channels,
  1769. ucontrol->value.enumerated.item[0] + 1);
  1770. }
  1771. return ret;
  1772. }
  1773. static int tdm_slot_map_put(struct snd_kcontrol *kcontrol,
  1774. struct snd_ctl_elem_value *ucontrol)
  1775. {
  1776. int slot_index = 0;
  1777. int interface = ucontrol->value.integer.value[0];
  1778. int channel = ucontrol->value.integer.value[1];
  1779. unsigned int offset_val = 0;
  1780. unsigned int *slot_offset = NULL;
  1781. struct tdm_dev_config *config = NULL;
  1782. if (interface < 0 || interface >= (TDM_INTERFACE_MAX * MAX_PATH)) {
  1783. pr_err("%s: incorrect interface = %d\n", __func__, interface);
  1784. return -EINVAL;
  1785. }
  1786. if (channel < 0 || channel >= TDM_PORT_MAX) {
  1787. pr_err("%s: incorrect channel = %d\n", __func__, channel);
  1788. return -EINVAL;
  1789. }
  1790. pr_debug("%s: interface = %d, channel = %d\n", __func__,
  1791. interface, channel);
  1792. config = ((struct tdm_dev_config *) tdm_cfg[interface / MAX_PATH]) +
  1793. ((interface % MAX_PATH) * TDM_PORT_MAX) + channel;
  1794. slot_offset = config->tdm_slot_offset;
  1795. for (slot_index = 0; slot_index < TDM_MAX_SLOTS; slot_index++) {
  1796. offset_val = ucontrol->value.integer.value[MAX_PATH +
  1797. slot_index];
  1798. /* Offset value can only be 0, 4, 8, ..28 */
  1799. if (offset_val % 4 == 0 && offset_val <= 28)
  1800. slot_offset[slot_index] = offset_val;
  1801. pr_debug("%s: slot offset[%d] = %d\n", __func__,
  1802. slot_index, slot_offset[slot_index]);
  1803. }
  1804. return 0;
  1805. }
  1806. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  1807. {
  1808. int idx = 0;
  1809. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  1810. sizeof("PRIM_AUX_PCM"))) {
  1811. idx = PRIM_AUX_PCM;
  1812. } else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  1813. sizeof("SEC_AUX_PCM"))) {
  1814. idx = SEC_AUX_PCM;
  1815. } else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  1816. sizeof("TERT_AUX_PCM"))) {
  1817. idx = TERT_AUX_PCM;
  1818. } else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  1819. sizeof("QUAT_AUX_PCM"))) {
  1820. idx = QUAT_AUX_PCM;
  1821. } else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  1822. sizeof("QUIN_AUX_PCM"))) {
  1823. idx = QUIN_AUX_PCM;
  1824. } else if (strnstr(kcontrol->id.name, "SEN_AUX_PCM",
  1825. sizeof("SEN_AUX_PCM"))) {
  1826. idx = SEN_AUX_PCM;
  1827. } else {
  1828. pr_err("%s: unsupported port: %s\n",
  1829. __func__, kcontrol->id.name);
  1830. idx = -EINVAL;
  1831. }
  1832. return idx;
  1833. }
  1834. static int aux_pcm_get_sample_rate(int value)
  1835. {
  1836. int sample_rate = 0;
  1837. switch (value) {
  1838. case 1:
  1839. sample_rate = SAMPLING_RATE_16KHZ;
  1840. break;
  1841. case 0:
  1842. default:
  1843. sample_rate = SAMPLING_RATE_8KHZ;
  1844. break;
  1845. }
  1846. return sample_rate;
  1847. }
  1848. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1849. {
  1850. int sample_rate_val = 0;
  1851. switch (sample_rate) {
  1852. case SAMPLING_RATE_16KHZ:
  1853. sample_rate_val = 1;
  1854. break;
  1855. case SAMPLING_RATE_8KHZ:
  1856. default:
  1857. sample_rate_val = 0;
  1858. break;
  1859. }
  1860. return sample_rate_val;
  1861. }
  1862. static int mi2s_auxpcm_get_format(int value)
  1863. {
  1864. int format = 0;
  1865. switch (value) {
  1866. case 0:
  1867. format = SNDRV_PCM_FORMAT_S16_LE;
  1868. break;
  1869. case 1:
  1870. format = SNDRV_PCM_FORMAT_S24_LE;
  1871. break;
  1872. case 2:
  1873. format = SNDRV_PCM_FORMAT_S24_3LE;
  1874. break;
  1875. case 3:
  1876. format = SNDRV_PCM_FORMAT_S32_LE;
  1877. break;
  1878. default:
  1879. format = SNDRV_PCM_FORMAT_S16_LE;
  1880. break;
  1881. }
  1882. return format;
  1883. }
  1884. static int mi2s_auxpcm_get_format_value(int format)
  1885. {
  1886. int value = 0;
  1887. switch (format) {
  1888. case SNDRV_PCM_FORMAT_S16_LE:
  1889. value = 0;
  1890. break;
  1891. case SNDRV_PCM_FORMAT_S24_LE:
  1892. value = 1;
  1893. break;
  1894. case SNDRV_PCM_FORMAT_S24_3LE:
  1895. value = 2;
  1896. break;
  1897. case SNDRV_PCM_FORMAT_S32_LE:
  1898. value = 3;
  1899. break;
  1900. default:
  1901. value = 0;
  1902. break;
  1903. }
  1904. return value;
  1905. }
  1906. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1907. struct snd_ctl_elem_value *ucontrol)
  1908. {
  1909. int idx = aux_pcm_get_port_idx(kcontrol);
  1910. if (idx < 0)
  1911. return idx;
  1912. ucontrol->value.enumerated.item[0] =
  1913. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  1914. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1915. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1916. ucontrol->value.enumerated.item[0]);
  1917. return 0;
  1918. }
  1919. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1920. struct snd_ctl_elem_value *ucontrol)
  1921. {
  1922. int idx = aux_pcm_get_port_idx(kcontrol);
  1923. if (idx < 0)
  1924. return idx;
  1925. aux_pcm_rx_cfg[idx].sample_rate =
  1926. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1927. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1928. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1929. ucontrol->value.enumerated.item[0]);
  1930. return 0;
  1931. }
  1932. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1933. struct snd_ctl_elem_value *ucontrol)
  1934. {
  1935. int idx = aux_pcm_get_port_idx(kcontrol);
  1936. if (idx < 0)
  1937. return idx;
  1938. ucontrol->value.enumerated.item[0] =
  1939. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  1940. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1941. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1942. ucontrol->value.enumerated.item[0]);
  1943. return 0;
  1944. }
  1945. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1946. struct snd_ctl_elem_value *ucontrol)
  1947. {
  1948. int idx = aux_pcm_get_port_idx(kcontrol);
  1949. if (idx < 0)
  1950. return idx;
  1951. aux_pcm_tx_cfg[idx].sample_rate =
  1952. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1953. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1954. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1955. ucontrol->value.enumerated.item[0]);
  1956. return 0;
  1957. }
  1958. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  1959. struct snd_ctl_elem_value *ucontrol)
  1960. {
  1961. int idx = aux_pcm_get_port_idx(kcontrol);
  1962. if (idx < 0)
  1963. return idx;
  1964. ucontrol->value.enumerated.item[0] =
  1965. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  1966. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1967. idx, aux_pcm_rx_cfg[idx].bit_format,
  1968. ucontrol->value.enumerated.item[0]);
  1969. return 0;
  1970. }
  1971. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  1972. struct snd_ctl_elem_value *ucontrol)
  1973. {
  1974. int idx = aux_pcm_get_port_idx(kcontrol);
  1975. if (idx < 0)
  1976. return idx;
  1977. aux_pcm_rx_cfg[idx].bit_format =
  1978. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1979. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1980. idx, aux_pcm_rx_cfg[idx].bit_format,
  1981. ucontrol->value.enumerated.item[0]);
  1982. return 0;
  1983. }
  1984. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  1985. struct snd_ctl_elem_value *ucontrol)
  1986. {
  1987. int idx = aux_pcm_get_port_idx(kcontrol);
  1988. if (idx < 0)
  1989. return idx;
  1990. ucontrol->value.enumerated.item[0] =
  1991. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  1992. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1993. idx, aux_pcm_tx_cfg[idx].bit_format,
  1994. ucontrol->value.enumerated.item[0]);
  1995. return 0;
  1996. }
  1997. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  1998. struct snd_ctl_elem_value *ucontrol)
  1999. {
  2000. int idx = aux_pcm_get_port_idx(kcontrol);
  2001. if (idx < 0)
  2002. return idx;
  2003. aux_pcm_tx_cfg[idx].bit_format =
  2004. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2005. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2006. idx, aux_pcm_tx_cfg[idx].bit_format,
  2007. ucontrol->value.enumerated.item[0]);
  2008. return 0;
  2009. }
  2010. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2011. {
  2012. int idx = 0;
  2013. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2014. sizeof("PRIM_MI2S_RX"))) {
  2015. idx = PRIM_MI2S;
  2016. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2017. sizeof("SEC_MI2S_RX"))) {
  2018. idx = SEC_MI2S;
  2019. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2020. sizeof("TERT_MI2S_RX"))) {
  2021. idx = TERT_MI2S;
  2022. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2023. sizeof("QUAT_MI2S_RX"))) {
  2024. idx = QUAT_MI2S;
  2025. } else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2026. sizeof("QUIN_MI2S_RX"))) {
  2027. idx = QUIN_MI2S;
  2028. } else if (strnstr(kcontrol->id.name, "SEN_MI2S_RX",
  2029. sizeof("SEN_MI2S_RX"))) {
  2030. idx = SEN_MI2S;
  2031. } else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2032. sizeof("PRIM_MI2S_TX"))) {
  2033. idx = PRIM_MI2S;
  2034. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2035. sizeof("SEC_MI2S_TX"))) {
  2036. idx = SEC_MI2S;
  2037. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2038. sizeof("TERT_MI2S_TX"))) {
  2039. idx = TERT_MI2S;
  2040. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2041. sizeof("QUAT_MI2S_TX"))) {
  2042. idx = QUAT_MI2S;
  2043. } else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2044. sizeof("QUIN_MI2S_TX"))) {
  2045. idx = QUIN_MI2S;
  2046. } else if (strnstr(kcontrol->id.name, "SEN_MI2S_TX",
  2047. sizeof("SEN_MI2S_TX"))) {
  2048. idx = SEN_MI2S;
  2049. } else {
  2050. pr_err("%s: unsupported channel: %s\n",
  2051. __func__, kcontrol->id.name);
  2052. idx = -EINVAL;
  2053. }
  2054. return idx;
  2055. }
  2056. static int mi2s_get_sample_rate(int value)
  2057. {
  2058. int sample_rate = 0;
  2059. switch (value) {
  2060. case 0:
  2061. sample_rate = SAMPLING_RATE_8KHZ;
  2062. break;
  2063. case 1:
  2064. sample_rate = SAMPLING_RATE_11P025KHZ;
  2065. break;
  2066. case 2:
  2067. sample_rate = SAMPLING_RATE_16KHZ;
  2068. break;
  2069. case 3:
  2070. sample_rate = SAMPLING_RATE_22P05KHZ;
  2071. break;
  2072. case 4:
  2073. sample_rate = SAMPLING_RATE_32KHZ;
  2074. break;
  2075. case 5:
  2076. sample_rate = SAMPLING_RATE_44P1KHZ;
  2077. break;
  2078. case 6:
  2079. sample_rate = SAMPLING_RATE_48KHZ;
  2080. break;
  2081. case 7:
  2082. sample_rate = SAMPLING_RATE_96KHZ;
  2083. break;
  2084. case 8:
  2085. sample_rate = SAMPLING_RATE_192KHZ;
  2086. break;
  2087. default:
  2088. sample_rate = SAMPLING_RATE_48KHZ;
  2089. break;
  2090. }
  2091. return sample_rate;
  2092. }
  2093. static int mi2s_get_sample_rate_val(int sample_rate)
  2094. {
  2095. int sample_rate_val = 0;
  2096. switch (sample_rate) {
  2097. case SAMPLING_RATE_8KHZ:
  2098. sample_rate_val = 0;
  2099. break;
  2100. case SAMPLING_RATE_11P025KHZ:
  2101. sample_rate_val = 1;
  2102. break;
  2103. case SAMPLING_RATE_16KHZ:
  2104. sample_rate_val = 2;
  2105. break;
  2106. case SAMPLING_RATE_22P05KHZ:
  2107. sample_rate_val = 3;
  2108. break;
  2109. case SAMPLING_RATE_32KHZ:
  2110. sample_rate_val = 4;
  2111. break;
  2112. case SAMPLING_RATE_44P1KHZ:
  2113. sample_rate_val = 5;
  2114. break;
  2115. case SAMPLING_RATE_48KHZ:
  2116. sample_rate_val = 6;
  2117. break;
  2118. case SAMPLING_RATE_96KHZ:
  2119. sample_rate_val = 7;
  2120. break;
  2121. case SAMPLING_RATE_192KHZ:
  2122. sample_rate_val = 8;
  2123. break;
  2124. default:
  2125. sample_rate_val = 6;
  2126. break;
  2127. }
  2128. return sample_rate_val;
  2129. }
  2130. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2131. struct snd_ctl_elem_value *ucontrol)
  2132. {
  2133. int idx = mi2s_get_port_idx(kcontrol);
  2134. if (idx < 0)
  2135. return idx;
  2136. ucontrol->value.enumerated.item[0] =
  2137. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2138. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2139. idx, mi2s_rx_cfg[idx].sample_rate,
  2140. ucontrol->value.enumerated.item[0]);
  2141. return 0;
  2142. }
  2143. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2144. struct snd_ctl_elem_value *ucontrol)
  2145. {
  2146. int idx = mi2s_get_port_idx(kcontrol);
  2147. if (idx < 0)
  2148. return idx;
  2149. mi2s_rx_cfg[idx].sample_rate =
  2150. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2151. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2152. idx, mi2s_rx_cfg[idx].sample_rate,
  2153. ucontrol->value.enumerated.item[0]);
  2154. return 0;
  2155. }
  2156. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2157. struct snd_ctl_elem_value *ucontrol)
  2158. {
  2159. int idx = mi2s_get_port_idx(kcontrol);
  2160. if (idx < 0)
  2161. return idx;
  2162. ucontrol->value.enumerated.item[0] =
  2163. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2164. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2165. idx, mi2s_tx_cfg[idx].sample_rate,
  2166. ucontrol->value.enumerated.item[0]);
  2167. return 0;
  2168. }
  2169. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2170. struct snd_ctl_elem_value *ucontrol)
  2171. {
  2172. int idx = mi2s_get_port_idx(kcontrol);
  2173. if (idx < 0)
  2174. return idx;
  2175. mi2s_tx_cfg[idx].sample_rate =
  2176. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2177. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2178. idx, mi2s_tx_cfg[idx].sample_rate,
  2179. ucontrol->value.enumerated.item[0]);
  2180. return 0;
  2181. }
  2182. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2183. struct snd_ctl_elem_value *ucontrol)
  2184. {
  2185. int idx = mi2s_get_port_idx(kcontrol);
  2186. if (idx < 0)
  2187. return idx;
  2188. ucontrol->value.enumerated.item[0] =
  2189. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2190. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2191. idx, mi2s_rx_cfg[idx].bit_format,
  2192. ucontrol->value.enumerated.item[0]);
  2193. return 0;
  2194. }
  2195. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2196. struct snd_ctl_elem_value *ucontrol)
  2197. {
  2198. int idx = mi2s_get_port_idx(kcontrol);
  2199. if (idx < 0)
  2200. return idx;
  2201. mi2s_rx_cfg[idx].bit_format =
  2202. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2203. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2204. idx, mi2s_rx_cfg[idx].bit_format,
  2205. ucontrol->value.enumerated.item[0]);
  2206. return 0;
  2207. }
  2208. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2209. struct snd_ctl_elem_value *ucontrol)
  2210. {
  2211. int idx = mi2s_get_port_idx(kcontrol);
  2212. if (idx < 0)
  2213. return idx;
  2214. ucontrol->value.enumerated.item[0] =
  2215. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2216. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2217. idx, mi2s_tx_cfg[idx].bit_format,
  2218. ucontrol->value.enumerated.item[0]);
  2219. return 0;
  2220. }
  2221. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2222. struct snd_ctl_elem_value *ucontrol)
  2223. {
  2224. int idx = mi2s_get_port_idx(kcontrol);
  2225. if (idx < 0)
  2226. return idx;
  2227. mi2s_tx_cfg[idx].bit_format =
  2228. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2229. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2230. idx, mi2s_tx_cfg[idx].bit_format,
  2231. ucontrol->value.enumerated.item[0]);
  2232. return 0;
  2233. }
  2234. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2235. struct snd_ctl_elem_value *ucontrol)
  2236. {
  2237. int idx = mi2s_get_port_idx(kcontrol);
  2238. if (idx < 0)
  2239. return idx;
  2240. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2241. idx, mi2s_rx_cfg[idx].channels);
  2242. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2243. return 0;
  2244. }
  2245. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2246. struct snd_ctl_elem_value *ucontrol)
  2247. {
  2248. int idx = mi2s_get_port_idx(kcontrol);
  2249. if (idx < 0)
  2250. return idx;
  2251. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2252. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2253. idx, mi2s_rx_cfg[idx].channels);
  2254. return 1;
  2255. }
  2256. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2257. struct snd_ctl_elem_value *ucontrol)
  2258. {
  2259. int idx = mi2s_get_port_idx(kcontrol);
  2260. if (idx < 0)
  2261. return idx;
  2262. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2263. idx, mi2s_tx_cfg[idx].channels);
  2264. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2265. return 0;
  2266. }
  2267. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2268. struct snd_ctl_elem_value *ucontrol)
  2269. {
  2270. int idx = mi2s_get_port_idx(kcontrol);
  2271. if (idx < 0)
  2272. return idx;
  2273. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2274. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2275. idx, mi2s_tx_cfg[idx].channels);
  2276. return 1;
  2277. }
  2278. static int msm_get_port_id(int be_id)
  2279. {
  2280. int afe_port_id = 0;
  2281. switch (be_id) {
  2282. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  2283. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  2284. break;
  2285. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  2286. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  2287. break;
  2288. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  2289. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  2290. break;
  2291. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  2292. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  2293. break;
  2294. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  2295. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  2296. break;
  2297. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  2298. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  2299. break;
  2300. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  2301. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  2302. break;
  2303. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  2304. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  2305. break;
  2306. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  2307. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  2308. break;
  2309. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  2310. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  2311. break;
  2312. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  2313. afe_port_id = AFE_PORT_ID_SENARY_MI2S_RX;
  2314. break;
  2315. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  2316. afe_port_id = AFE_PORT_ID_SENARY_MI2S_TX;
  2317. break;
  2318. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2319. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  2320. break;
  2321. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2322. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_1;
  2323. break;
  2324. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2325. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_2;
  2326. break;
  2327. default:
  2328. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  2329. afe_port_id = -EINVAL;
  2330. }
  2331. return afe_port_id;
  2332. }
  2333. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  2334. {
  2335. u32 bit_per_sample = 0;
  2336. switch (bit_format) {
  2337. case SNDRV_PCM_FORMAT_S32_LE:
  2338. case SNDRV_PCM_FORMAT_S24_3LE:
  2339. case SNDRV_PCM_FORMAT_S24_LE:
  2340. bit_per_sample = 32;
  2341. break;
  2342. case SNDRV_PCM_FORMAT_S16_LE:
  2343. default:
  2344. bit_per_sample = 16;
  2345. break;
  2346. }
  2347. return bit_per_sample;
  2348. }
  2349. static void update_mi2s_clk_val(int dai_id, int stream)
  2350. {
  2351. u32 bit_per_sample = 0;
  2352. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  2353. bit_per_sample =
  2354. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  2355. mi2s_clk[dai_id].clk_freq_in_hz =
  2356. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2357. } else {
  2358. bit_per_sample =
  2359. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  2360. mi2s_clk[dai_id].clk_freq_in_hz =
  2361. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2362. }
  2363. }
  2364. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  2365. {
  2366. int ret = 0;
  2367. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2368. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  2369. int port_id = 0;
  2370. int index = cpu_dai->id;
  2371. port_id = msm_get_port_id(rtd->dai_link->id);
  2372. if (port_id < 0) {
  2373. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  2374. ret = port_id;
  2375. goto err;
  2376. }
  2377. if (enable) {
  2378. update_mi2s_clk_val(index, substream->stream);
  2379. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  2380. mi2s_clk[index].clk_freq_in_hz);
  2381. }
  2382. mi2s_clk[index].enable = enable;
  2383. ret = afe_set_lpass_clock_v2(port_id,
  2384. &mi2s_clk[index]);
  2385. if (ret < 0) {
  2386. dev_err(rtd->card->dev,
  2387. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  2388. __func__, port_id, ret);
  2389. goto err;
  2390. }
  2391. err:
  2392. return ret;
  2393. }
  2394. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  2395. {
  2396. int idx = 0;
  2397. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  2398. sizeof("WSA_CDC_DMA_RX_0")))
  2399. idx = WSA_CDC_DMA_RX_0;
  2400. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  2401. sizeof("WSA_CDC_DMA_RX_0")))
  2402. idx = WSA_CDC_DMA_RX_1;
  2403. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_0",
  2404. sizeof("RX_CDC_DMA_RX_0")))
  2405. idx = RX_CDC_DMA_RX_0;
  2406. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_1",
  2407. sizeof("RX_CDC_DMA_RX_1")))
  2408. idx = RX_CDC_DMA_RX_1;
  2409. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_2",
  2410. sizeof("RX_CDC_DMA_RX_2")))
  2411. idx = RX_CDC_DMA_RX_2;
  2412. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_3",
  2413. sizeof("RX_CDC_DMA_RX_3")))
  2414. idx = RX_CDC_DMA_RX_3;
  2415. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_5",
  2416. sizeof("RX_CDC_DMA_RX_5")))
  2417. idx = RX_CDC_DMA_RX_5;
  2418. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  2419. sizeof("WSA_CDC_DMA_TX_0")))
  2420. idx = WSA_CDC_DMA_TX_0;
  2421. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  2422. sizeof("WSA_CDC_DMA_TX_1")))
  2423. idx = WSA_CDC_DMA_TX_1;
  2424. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  2425. sizeof("WSA_CDC_DMA_TX_2")))
  2426. idx = WSA_CDC_DMA_TX_2;
  2427. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_0",
  2428. sizeof("TX_CDC_DMA_TX_0")))
  2429. idx = TX_CDC_DMA_TX_0;
  2430. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_3",
  2431. sizeof("TX_CDC_DMA_TX_3")))
  2432. idx = TX_CDC_DMA_TX_3;
  2433. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_4",
  2434. sizeof("TX_CDC_DMA_TX_4")))
  2435. idx = TX_CDC_DMA_TX_4;
  2436. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  2437. sizeof("VA_CDC_DMA_TX_0")))
  2438. idx = VA_CDC_DMA_TX_0;
  2439. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  2440. sizeof("VA_CDC_DMA_TX_1")))
  2441. idx = VA_CDC_DMA_TX_1;
  2442. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_2",
  2443. sizeof("VA_CDC_DMA_TX_2")))
  2444. idx = VA_CDC_DMA_TX_2;
  2445. else {
  2446. pr_err("%s: unsupported channel: %s\n",
  2447. __func__, kcontrol->id.name);
  2448. return -EINVAL;
  2449. }
  2450. return idx;
  2451. }
  2452. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  2453. struct snd_ctl_elem_value *ucontrol)
  2454. {
  2455. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2456. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2457. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2458. return ch_num;
  2459. }
  2460. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2461. cdc_dma_rx_cfg[ch_num].channels - 1);
  2462. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  2463. return 0;
  2464. }
  2465. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  2466. struct snd_ctl_elem_value *ucontrol)
  2467. {
  2468. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2469. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2470. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2471. return ch_num;
  2472. }
  2473. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2474. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2475. cdc_dma_rx_cfg[ch_num].channels);
  2476. return 1;
  2477. }
  2478. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  2479. struct snd_ctl_elem_value *ucontrol)
  2480. {
  2481. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2482. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2483. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2484. return ch_num;
  2485. }
  2486. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  2487. case SNDRV_PCM_FORMAT_S32_LE:
  2488. ucontrol->value.integer.value[0] = 3;
  2489. break;
  2490. case SNDRV_PCM_FORMAT_S24_3LE:
  2491. ucontrol->value.integer.value[0] = 2;
  2492. break;
  2493. case SNDRV_PCM_FORMAT_S24_LE:
  2494. ucontrol->value.integer.value[0] = 1;
  2495. break;
  2496. case SNDRV_PCM_FORMAT_S16_LE:
  2497. default:
  2498. ucontrol->value.integer.value[0] = 0;
  2499. break;
  2500. }
  2501. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2502. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2503. ucontrol->value.integer.value[0]);
  2504. return 0;
  2505. }
  2506. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  2507. struct snd_ctl_elem_value *ucontrol)
  2508. {
  2509. int rc = 0;
  2510. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2511. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2512. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2513. return ch_num;
  2514. }
  2515. switch (ucontrol->value.integer.value[0]) {
  2516. case 3:
  2517. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2518. break;
  2519. case 2:
  2520. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2521. break;
  2522. case 1:
  2523. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2524. break;
  2525. case 0:
  2526. default:
  2527. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2528. break;
  2529. }
  2530. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2531. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2532. ucontrol->value.integer.value[0]);
  2533. return rc;
  2534. }
  2535. static int cdc_dma_get_sample_rate_val(int sample_rate)
  2536. {
  2537. int sample_rate_val = 0;
  2538. switch (sample_rate) {
  2539. case SAMPLING_RATE_8KHZ:
  2540. sample_rate_val = 0;
  2541. break;
  2542. case SAMPLING_RATE_11P025KHZ:
  2543. sample_rate_val = 1;
  2544. break;
  2545. case SAMPLING_RATE_16KHZ:
  2546. sample_rate_val = 2;
  2547. break;
  2548. case SAMPLING_RATE_22P05KHZ:
  2549. sample_rate_val = 3;
  2550. break;
  2551. case SAMPLING_RATE_32KHZ:
  2552. sample_rate_val = 4;
  2553. break;
  2554. case SAMPLING_RATE_44P1KHZ:
  2555. sample_rate_val = 5;
  2556. break;
  2557. case SAMPLING_RATE_48KHZ:
  2558. sample_rate_val = 6;
  2559. break;
  2560. case SAMPLING_RATE_88P2KHZ:
  2561. sample_rate_val = 7;
  2562. break;
  2563. case SAMPLING_RATE_96KHZ:
  2564. sample_rate_val = 8;
  2565. break;
  2566. case SAMPLING_RATE_176P4KHZ:
  2567. sample_rate_val = 9;
  2568. break;
  2569. case SAMPLING_RATE_192KHZ:
  2570. sample_rate_val = 10;
  2571. break;
  2572. case SAMPLING_RATE_352P8KHZ:
  2573. sample_rate_val = 11;
  2574. break;
  2575. case SAMPLING_RATE_384KHZ:
  2576. sample_rate_val = 12;
  2577. break;
  2578. default:
  2579. sample_rate_val = 6;
  2580. break;
  2581. }
  2582. return sample_rate_val;
  2583. }
  2584. static int cdc_dma_get_sample_rate(int value)
  2585. {
  2586. int sample_rate = 0;
  2587. switch (value) {
  2588. case 0:
  2589. sample_rate = SAMPLING_RATE_8KHZ;
  2590. break;
  2591. case 1:
  2592. sample_rate = SAMPLING_RATE_11P025KHZ;
  2593. break;
  2594. case 2:
  2595. sample_rate = SAMPLING_RATE_16KHZ;
  2596. break;
  2597. case 3:
  2598. sample_rate = SAMPLING_RATE_22P05KHZ;
  2599. break;
  2600. case 4:
  2601. sample_rate = SAMPLING_RATE_32KHZ;
  2602. break;
  2603. case 5:
  2604. sample_rate = SAMPLING_RATE_44P1KHZ;
  2605. break;
  2606. case 6:
  2607. sample_rate = SAMPLING_RATE_48KHZ;
  2608. break;
  2609. case 7:
  2610. sample_rate = SAMPLING_RATE_88P2KHZ;
  2611. break;
  2612. case 8:
  2613. sample_rate = SAMPLING_RATE_96KHZ;
  2614. break;
  2615. case 9:
  2616. sample_rate = SAMPLING_RATE_176P4KHZ;
  2617. break;
  2618. case 10:
  2619. sample_rate = SAMPLING_RATE_192KHZ;
  2620. break;
  2621. case 11:
  2622. sample_rate = SAMPLING_RATE_352P8KHZ;
  2623. break;
  2624. case 12:
  2625. sample_rate = SAMPLING_RATE_384KHZ;
  2626. break;
  2627. default:
  2628. sample_rate = SAMPLING_RATE_48KHZ;
  2629. break;
  2630. }
  2631. return sample_rate;
  2632. }
  2633. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2634. struct snd_ctl_elem_value *ucontrol)
  2635. {
  2636. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2637. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2638. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2639. return ch_num;
  2640. }
  2641. ucontrol->value.enumerated.item[0] =
  2642. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  2643. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  2644. cdc_dma_rx_cfg[ch_num].sample_rate);
  2645. return 0;
  2646. }
  2647. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2648. struct snd_ctl_elem_value *ucontrol)
  2649. {
  2650. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2651. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2652. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2653. return ch_num;
  2654. }
  2655. cdc_dma_rx_cfg[ch_num].sample_rate =
  2656. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2657. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  2658. __func__, ucontrol->value.enumerated.item[0],
  2659. cdc_dma_rx_cfg[ch_num].sample_rate);
  2660. return 0;
  2661. }
  2662. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  2663. struct snd_ctl_elem_value *ucontrol)
  2664. {
  2665. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2666. if (ch_num < 0) {
  2667. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2668. return ch_num;
  2669. }
  2670. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2671. cdc_dma_tx_cfg[ch_num].channels);
  2672. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  2673. return 0;
  2674. }
  2675. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  2676. struct snd_ctl_elem_value *ucontrol)
  2677. {
  2678. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2679. if (ch_num < 0) {
  2680. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2681. return ch_num;
  2682. }
  2683. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2684. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2685. cdc_dma_tx_cfg[ch_num].channels);
  2686. return 1;
  2687. }
  2688. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2689. struct snd_ctl_elem_value *ucontrol)
  2690. {
  2691. int sample_rate_val;
  2692. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2693. if (ch_num < 0) {
  2694. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2695. return ch_num;
  2696. }
  2697. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  2698. case SAMPLING_RATE_384KHZ:
  2699. sample_rate_val = 12;
  2700. break;
  2701. case SAMPLING_RATE_352P8KHZ:
  2702. sample_rate_val = 11;
  2703. break;
  2704. case SAMPLING_RATE_192KHZ:
  2705. sample_rate_val = 10;
  2706. break;
  2707. case SAMPLING_RATE_176P4KHZ:
  2708. sample_rate_val = 9;
  2709. break;
  2710. case SAMPLING_RATE_96KHZ:
  2711. sample_rate_val = 8;
  2712. break;
  2713. case SAMPLING_RATE_88P2KHZ:
  2714. sample_rate_val = 7;
  2715. break;
  2716. case SAMPLING_RATE_48KHZ:
  2717. sample_rate_val = 6;
  2718. break;
  2719. case SAMPLING_RATE_44P1KHZ:
  2720. sample_rate_val = 5;
  2721. break;
  2722. case SAMPLING_RATE_32KHZ:
  2723. sample_rate_val = 4;
  2724. break;
  2725. case SAMPLING_RATE_22P05KHZ:
  2726. sample_rate_val = 3;
  2727. break;
  2728. case SAMPLING_RATE_16KHZ:
  2729. sample_rate_val = 2;
  2730. break;
  2731. case SAMPLING_RATE_11P025KHZ:
  2732. sample_rate_val = 1;
  2733. break;
  2734. case SAMPLING_RATE_8KHZ:
  2735. sample_rate_val = 0;
  2736. break;
  2737. default:
  2738. sample_rate_val = 6;
  2739. break;
  2740. }
  2741. ucontrol->value.integer.value[0] = sample_rate_val;
  2742. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  2743. cdc_dma_tx_cfg[ch_num].sample_rate);
  2744. return 0;
  2745. }
  2746. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2747. struct snd_ctl_elem_value *ucontrol)
  2748. {
  2749. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2750. if (ch_num < 0) {
  2751. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2752. return ch_num;
  2753. }
  2754. switch (ucontrol->value.integer.value[0]) {
  2755. case 12:
  2756. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  2757. break;
  2758. case 11:
  2759. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  2760. break;
  2761. case 10:
  2762. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  2763. break;
  2764. case 9:
  2765. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  2766. break;
  2767. case 8:
  2768. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  2769. break;
  2770. case 7:
  2771. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  2772. break;
  2773. case 6:
  2774. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2775. break;
  2776. case 5:
  2777. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  2778. break;
  2779. case 4:
  2780. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  2781. break;
  2782. case 3:
  2783. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  2784. break;
  2785. case 2:
  2786. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  2787. break;
  2788. case 1:
  2789. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  2790. break;
  2791. case 0:
  2792. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  2793. break;
  2794. default:
  2795. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2796. break;
  2797. }
  2798. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  2799. __func__, ucontrol->value.integer.value[0],
  2800. cdc_dma_tx_cfg[ch_num].sample_rate);
  2801. return 0;
  2802. }
  2803. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  2804. struct snd_ctl_elem_value *ucontrol)
  2805. {
  2806. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2807. if (ch_num < 0) {
  2808. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2809. return ch_num;
  2810. }
  2811. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  2812. case SNDRV_PCM_FORMAT_S32_LE:
  2813. ucontrol->value.integer.value[0] = 3;
  2814. break;
  2815. case SNDRV_PCM_FORMAT_S24_3LE:
  2816. ucontrol->value.integer.value[0] = 2;
  2817. break;
  2818. case SNDRV_PCM_FORMAT_S24_LE:
  2819. ucontrol->value.integer.value[0] = 1;
  2820. break;
  2821. case SNDRV_PCM_FORMAT_S16_LE:
  2822. default:
  2823. ucontrol->value.integer.value[0] = 0;
  2824. break;
  2825. }
  2826. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2827. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2828. ucontrol->value.integer.value[0]);
  2829. return 0;
  2830. }
  2831. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  2832. struct snd_ctl_elem_value *ucontrol)
  2833. {
  2834. int rc = 0;
  2835. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2836. if (ch_num < 0) {
  2837. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2838. return ch_num;
  2839. }
  2840. switch (ucontrol->value.integer.value[0]) {
  2841. case 3:
  2842. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2843. break;
  2844. case 2:
  2845. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2846. break;
  2847. case 1:
  2848. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2849. break;
  2850. case 0:
  2851. default:
  2852. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2853. break;
  2854. }
  2855. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2856. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2857. ucontrol->value.integer.value[0]);
  2858. return rc;
  2859. }
  2860. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  2861. {
  2862. int idx = 0;
  2863. switch (be_id) {
  2864. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  2865. idx = WSA_CDC_DMA_RX_0;
  2866. break;
  2867. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  2868. idx = WSA_CDC_DMA_TX_0;
  2869. break;
  2870. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  2871. idx = WSA_CDC_DMA_RX_1;
  2872. break;
  2873. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  2874. idx = WSA_CDC_DMA_TX_1;
  2875. break;
  2876. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  2877. idx = WSA_CDC_DMA_TX_2;
  2878. break;
  2879. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  2880. idx = RX_CDC_DMA_RX_0;
  2881. break;
  2882. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  2883. idx = RX_CDC_DMA_RX_1;
  2884. break;
  2885. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  2886. idx = RX_CDC_DMA_RX_2;
  2887. break;
  2888. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  2889. idx = RX_CDC_DMA_RX_3;
  2890. break;
  2891. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  2892. idx = RX_CDC_DMA_RX_5;
  2893. break;
  2894. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  2895. idx = TX_CDC_DMA_TX_0;
  2896. break;
  2897. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  2898. idx = TX_CDC_DMA_TX_3;
  2899. break;
  2900. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  2901. idx = TX_CDC_DMA_TX_4;
  2902. break;
  2903. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2904. idx = VA_CDC_DMA_TX_0;
  2905. break;
  2906. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2907. idx = VA_CDC_DMA_TX_1;
  2908. break;
  2909. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2910. idx = VA_CDC_DMA_TX_2;
  2911. break;
  2912. default:
  2913. idx = RX_CDC_DMA_RX_0;
  2914. break;
  2915. }
  2916. return idx;
  2917. }
  2918. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  2919. struct snd_ctl_elem_value *ucontrol)
  2920. {
  2921. /*
  2922. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  2923. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  2924. * value.
  2925. */
  2926. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2927. case SAMPLING_RATE_96KHZ:
  2928. ucontrol->value.integer.value[0] = 5;
  2929. break;
  2930. case SAMPLING_RATE_88P2KHZ:
  2931. ucontrol->value.integer.value[0] = 4;
  2932. break;
  2933. case SAMPLING_RATE_48KHZ:
  2934. ucontrol->value.integer.value[0] = 3;
  2935. break;
  2936. case SAMPLING_RATE_44P1KHZ:
  2937. ucontrol->value.integer.value[0] = 2;
  2938. break;
  2939. case SAMPLING_RATE_16KHZ:
  2940. ucontrol->value.integer.value[0] = 1;
  2941. break;
  2942. case SAMPLING_RATE_8KHZ:
  2943. default:
  2944. ucontrol->value.integer.value[0] = 0;
  2945. break;
  2946. }
  2947. pr_debug("%s: sample rate = %d\n", __func__,
  2948. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2949. return 0;
  2950. }
  2951. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  2952. struct snd_ctl_elem_value *ucontrol)
  2953. {
  2954. switch (ucontrol->value.integer.value[0]) {
  2955. case 1:
  2956. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2957. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2958. break;
  2959. case 2:
  2960. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2961. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2962. break;
  2963. case 3:
  2964. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2965. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2966. break;
  2967. case 4:
  2968. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2969. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2970. break;
  2971. case 5:
  2972. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2973. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2974. break;
  2975. case 0:
  2976. default:
  2977. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2978. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2979. break;
  2980. }
  2981. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  2982. __func__,
  2983. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2984. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2985. ucontrol->value.enumerated.item[0]);
  2986. return 0;
  2987. }
  2988. static int msm_bt_sample_rate_rx_get(struct snd_kcontrol *kcontrol,
  2989. struct snd_ctl_elem_value *ucontrol)
  2990. {
  2991. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2992. case SAMPLING_RATE_96KHZ:
  2993. ucontrol->value.integer.value[0] = 5;
  2994. break;
  2995. case SAMPLING_RATE_88P2KHZ:
  2996. ucontrol->value.integer.value[0] = 4;
  2997. break;
  2998. case SAMPLING_RATE_48KHZ:
  2999. ucontrol->value.integer.value[0] = 3;
  3000. break;
  3001. case SAMPLING_RATE_44P1KHZ:
  3002. ucontrol->value.integer.value[0] = 2;
  3003. break;
  3004. case SAMPLING_RATE_16KHZ:
  3005. ucontrol->value.integer.value[0] = 1;
  3006. break;
  3007. case SAMPLING_RATE_8KHZ:
  3008. default:
  3009. ucontrol->value.integer.value[0] = 0;
  3010. break;
  3011. }
  3012. pr_debug("%s: sample rate rx = %d\n", __func__,
  3013. slim_rx_cfg[SLIM_RX_7].sample_rate);
  3014. return 0;
  3015. }
  3016. static int msm_bt_sample_rate_rx_put(struct snd_kcontrol *kcontrol,
  3017. struct snd_ctl_elem_value *ucontrol)
  3018. {
  3019. switch (ucontrol->value.integer.value[0]) {
  3020. case 1:
  3021. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  3022. break;
  3023. case 2:
  3024. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  3025. break;
  3026. case 3:
  3027. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  3028. break;
  3029. case 4:
  3030. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  3031. break;
  3032. case 5:
  3033. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  3034. break;
  3035. case 0:
  3036. default:
  3037. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  3038. break;
  3039. }
  3040. pr_debug("%s: sample rate: slim7_rx = %d, value = %d\n",
  3041. __func__,
  3042. slim_rx_cfg[SLIM_RX_7].sample_rate,
  3043. ucontrol->value.enumerated.item[0]);
  3044. return 0;
  3045. }
  3046. static int msm_bt_sample_rate_tx_get(struct snd_kcontrol *kcontrol,
  3047. struct snd_ctl_elem_value *ucontrol)
  3048. {
  3049. switch (slim_tx_cfg[SLIM_TX_7].sample_rate) {
  3050. case SAMPLING_RATE_96KHZ:
  3051. ucontrol->value.integer.value[0] = 5;
  3052. break;
  3053. case SAMPLING_RATE_88P2KHZ:
  3054. ucontrol->value.integer.value[0] = 4;
  3055. break;
  3056. case SAMPLING_RATE_48KHZ:
  3057. ucontrol->value.integer.value[0] = 3;
  3058. break;
  3059. case SAMPLING_RATE_44P1KHZ:
  3060. ucontrol->value.integer.value[0] = 2;
  3061. break;
  3062. case SAMPLING_RATE_16KHZ:
  3063. ucontrol->value.integer.value[0] = 1;
  3064. break;
  3065. case SAMPLING_RATE_8KHZ:
  3066. default:
  3067. ucontrol->value.integer.value[0] = 0;
  3068. break;
  3069. }
  3070. pr_debug("%s: sample rate tx = %d\n", __func__,
  3071. slim_tx_cfg[SLIM_TX_7].sample_rate);
  3072. return 0;
  3073. }
  3074. static int msm_bt_sample_rate_tx_put(struct snd_kcontrol *kcontrol,
  3075. struct snd_ctl_elem_value *ucontrol)
  3076. {
  3077. switch (ucontrol->value.integer.value[0]) {
  3078. case 1:
  3079. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  3080. break;
  3081. case 2:
  3082. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  3083. break;
  3084. case 3:
  3085. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  3086. break;
  3087. case 4:
  3088. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  3089. break;
  3090. case 5:
  3091. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  3092. break;
  3093. case 0:
  3094. default:
  3095. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  3096. break;
  3097. }
  3098. pr_debug("%s: sample rate: slim7_tx = %d, value = %d\n",
  3099. __func__,
  3100. slim_tx_cfg[SLIM_TX_7].sample_rate,
  3101. ucontrol->value.enumerated.item[0]);
  3102. return 0;
  3103. }
  3104. static const struct snd_kcontrol_new msm_int_snd_controls[] = {
  3105. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  3106. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3107. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  3108. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3109. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Channels", rx_cdc_dma_rx_0_chs,
  3110. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3111. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Channels", rx_cdc_dma_rx_1_chs,
  3112. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3113. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Channels", rx_cdc_dma_rx_2_chs,
  3114. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3115. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Channels", rx_cdc_dma_rx_3_chs,
  3116. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3117. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Channels", rx_cdc_dma_rx_5_chs,
  3118. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3119. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  3120. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3121. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  3122. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3123. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  3124. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3125. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Channels", tx_cdc_dma_tx_0_chs,
  3126. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3127. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Channels", tx_cdc_dma_tx_3_chs,
  3128. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3129. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Channels", tx_cdc_dma_tx_4_chs,
  3130. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3131. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  3132. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3133. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  3134. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3135. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Channels", va_cdc_dma_tx_2_chs,
  3136. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3137. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  3138. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3139. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  3140. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3141. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  3142. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3143. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  3144. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3145. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Format", tx_cdc_dma_tx_0_format,
  3146. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3147. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Format", tx_cdc_dma_tx_3_format,
  3148. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3149. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Format", tx_cdc_dma_tx_4_format,
  3150. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3151. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  3152. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3153. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  3154. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3155. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Format", va_cdc_dma_tx_2_format,
  3156. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3157. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  3158. wsa_cdc_dma_rx_0_sample_rate,
  3159. cdc_dma_rx_sample_rate_get,
  3160. cdc_dma_rx_sample_rate_put),
  3161. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  3162. wsa_cdc_dma_rx_1_sample_rate,
  3163. cdc_dma_rx_sample_rate_get,
  3164. cdc_dma_rx_sample_rate_put),
  3165. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  3166. wsa_cdc_dma_tx_0_sample_rate,
  3167. cdc_dma_tx_sample_rate_get,
  3168. cdc_dma_tx_sample_rate_put),
  3169. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  3170. wsa_cdc_dma_tx_1_sample_rate,
  3171. cdc_dma_tx_sample_rate_get,
  3172. cdc_dma_tx_sample_rate_put),
  3173. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  3174. wsa_cdc_dma_tx_2_sample_rate,
  3175. cdc_dma_tx_sample_rate_get,
  3176. cdc_dma_tx_sample_rate_put),
  3177. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 SampleRate",
  3178. tx_cdc_dma_tx_0_sample_rate,
  3179. cdc_dma_tx_sample_rate_get,
  3180. cdc_dma_tx_sample_rate_put),
  3181. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 SampleRate",
  3182. tx_cdc_dma_tx_3_sample_rate,
  3183. cdc_dma_tx_sample_rate_get,
  3184. cdc_dma_tx_sample_rate_put),
  3185. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 SampleRate",
  3186. tx_cdc_dma_tx_4_sample_rate,
  3187. cdc_dma_tx_sample_rate_get,
  3188. cdc_dma_tx_sample_rate_put),
  3189. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  3190. va_cdc_dma_tx_0_sample_rate,
  3191. cdc_dma_tx_sample_rate_get,
  3192. cdc_dma_tx_sample_rate_put),
  3193. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  3194. va_cdc_dma_tx_1_sample_rate,
  3195. cdc_dma_tx_sample_rate_get,
  3196. cdc_dma_tx_sample_rate_put),
  3197. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 SampleRate",
  3198. va_cdc_dma_tx_2_sample_rate,
  3199. cdc_dma_tx_sample_rate_get,
  3200. cdc_dma_tx_sample_rate_put),
  3201. };
  3202. static const struct snd_kcontrol_new msm_int_wcd9380_snd_controls[] = {
  3203. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc80_dma_rx_0_format,
  3204. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3205. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc80_dma_rx_1_format,
  3206. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3207. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc80_dma_rx_2_format,
  3208. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3209. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc80_dma_rx_3_format,
  3210. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3211. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc80_dma_rx_5_format,
  3212. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3213. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  3214. rx_cdc80_dma_rx_0_sample_rate,
  3215. cdc_dma_rx_sample_rate_get,
  3216. cdc_dma_rx_sample_rate_put),
  3217. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  3218. rx_cdc80_dma_rx_1_sample_rate,
  3219. cdc_dma_rx_sample_rate_get,
  3220. cdc_dma_rx_sample_rate_put),
  3221. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  3222. rx_cdc80_dma_rx_2_sample_rate,
  3223. cdc_dma_rx_sample_rate_get,
  3224. cdc_dma_rx_sample_rate_put),
  3225. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  3226. rx_cdc80_dma_rx_3_sample_rate,
  3227. cdc_dma_rx_sample_rate_get,
  3228. cdc_dma_rx_sample_rate_put),
  3229. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  3230. rx_cdc80_dma_rx_5_sample_rate,
  3231. cdc_dma_rx_sample_rate_get,
  3232. cdc_dma_rx_sample_rate_put),
  3233. };
  3234. static const struct snd_kcontrol_new msm_int_wcd9385_snd_controls[] = {
  3235. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc85_dma_rx_0_format,
  3236. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3237. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc85_dma_rx_1_format,
  3238. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3239. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc85_dma_rx_2_format,
  3240. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3241. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc85_dma_rx_3_format,
  3242. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3243. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc85_dma_rx_5_format,
  3244. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3245. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  3246. rx_cdc85_dma_rx_0_sample_rate,
  3247. cdc_dma_rx_sample_rate_get,
  3248. cdc_dma_rx_sample_rate_put),
  3249. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  3250. rx_cdc85_dma_rx_1_sample_rate,
  3251. cdc_dma_rx_sample_rate_get,
  3252. cdc_dma_rx_sample_rate_put),
  3253. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  3254. rx_cdc85_dma_rx_2_sample_rate,
  3255. cdc_dma_rx_sample_rate_get,
  3256. cdc_dma_rx_sample_rate_put),
  3257. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  3258. rx_cdc85_dma_rx_3_sample_rate,
  3259. cdc_dma_rx_sample_rate_get,
  3260. cdc_dma_rx_sample_rate_put),
  3261. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  3262. rx_cdc85_dma_rx_5_sample_rate,
  3263. cdc_dma_rx_sample_rate_get,
  3264. cdc_dma_rx_sample_rate_put),
  3265. };
  3266. static const struct snd_kcontrol_new msm_common_snd_controls[] = {
  3267. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  3268. usb_audio_rx_sample_rate_get,
  3269. usb_audio_rx_sample_rate_put),
  3270. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  3271. usb_audio_tx_sample_rate_get,
  3272. usb_audio_tx_sample_rate_put),
  3273. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3274. tdm_rx_sample_rate_get,
  3275. tdm_rx_sample_rate_put),
  3276. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3277. tdm_rx_sample_rate_get,
  3278. tdm_rx_sample_rate_put),
  3279. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3280. tdm_rx_sample_rate_get,
  3281. tdm_rx_sample_rate_put),
  3282. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3283. tdm_rx_sample_rate_get,
  3284. tdm_rx_sample_rate_put),
  3285. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3286. tdm_rx_sample_rate_get,
  3287. tdm_rx_sample_rate_put),
  3288. SOC_ENUM_EXT("SEN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3289. tdm_rx_sample_rate_get,
  3290. tdm_rx_sample_rate_put),
  3291. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3292. tdm_tx_sample_rate_get,
  3293. tdm_tx_sample_rate_put),
  3294. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3295. tdm_tx_sample_rate_get,
  3296. tdm_tx_sample_rate_put),
  3297. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3298. tdm_tx_sample_rate_get,
  3299. tdm_tx_sample_rate_put),
  3300. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3301. tdm_tx_sample_rate_get,
  3302. tdm_tx_sample_rate_put),
  3303. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3304. tdm_tx_sample_rate_get,
  3305. tdm_tx_sample_rate_put),
  3306. SOC_ENUM_EXT("SEN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3307. tdm_tx_sample_rate_get,
  3308. tdm_tx_sample_rate_put),
  3309. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3310. aux_pcm_rx_sample_rate_get,
  3311. aux_pcm_rx_sample_rate_put),
  3312. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3313. aux_pcm_rx_sample_rate_get,
  3314. aux_pcm_rx_sample_rate_put),
  3315. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3316. aux_pcm_rx_sample_rate_get,
  3317. aux_pcm_rx_sample_rate_put),
  3318. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3319. aux_pcm_rx_sample_rate_get,
  3320. aux_pcm_rx_sample_rate_put),
  3321. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3322. aux_pcm_rx_sample_rate_get,
  3323. aux_pcm_rx_sample_rate_put),
  3324. SOC_ENUM_EXT("SEN_AUX_PCM_RX SampleRate", sen_aux_pcm_rx_sample_rate,
  3325. aux_pcm_rx_sample_rate_get,
  3326. aux_pcm_rx_sample_rate_put),
  3327. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3328. aux_pcm_tx_sample_rate_get,
  3329. aux_pcm_tx_sample_rate_put),
  3330. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3331. aux_pcm_tx_sample_rate_get,
  3332. aux_pcm_tx_sample_rate_put),
  3333. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3334. aux_pcm_tx_sample_rate_get,
  3335. aux_pcm_tx_sample_rate_put),
  3336. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3337. aux_pcm_tx_sample_rate_get,
  3338. aux_pcm_tx_sample_rate_put),
  3339. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3340. aux_pcm_tx_sample_rate_get,
  3341. aux_pcm_tx_sample_rate_put),
  3342. SOC_ENUM_EXT("SEN_AUX_PCM_TX SampleRate", sen_aux_pcm_tx_sample_rate,
  3343. aux_pcm_tx_sample_rate_get,
  3344. aux_pcm_tx_sample_rate_put),
  3345. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3346. mi2s_rx_sample_rate_get,
  3347. mi2s_rx_sample_rate_put),
  3348. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3349. mi2s_rx_sample_rate_get,
  3350. mi2s_rx_sample_rate_put),
  3351. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3352. mi2s_rx_sample_rate_get,
  3353. mi2s_rx_sample_rate_put),
  3354. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3355. mi2s_rx_sample_rate_get,
  3356. mi2s_rx_sample_rate_put),
  3357. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3358. mi2s_rx_sample_rate_get,
  3359. mi2s_rx_sample_rate_put),
  3360. SOC_ENUM_EXT("SEN_MI2S_RX SampleRate", sen_mi2s_rx_sample_rate,
  3361. mi2s_rx_sample_rate_get,
  3362. mi2s_rx_sample_rate_put),
  3363. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3364. mi2s_tx_sample_rate_get,
  3365. mi2s_tx_sample_rate_put),
  3366. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3367. mi2s_tx_sample_rate_get,
  3368. mi2s_tx_sample_rate_put),
  3369. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3370. mi2s_tx_sample_rate_get,
  3371. mi2s_tx_sample_rate_put),
  3372. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3373. mi2s_tx_sample_rate_get,
  3374. mi2s_tx_sample_rate_put),
  3375. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3376. mi2s_tx_sample_rate_get,
  3377. mi2s_tx_sample_rate_put),
  3378. SOC_ENUM_EXT("SEN_MI2S_TX SampleRate", sen_mi2s_tx_sample_rate,
  3379. mi2s_tx_sample_rate_get,
  3380. mi2s_tx_sample_rate_put),
  3381. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  3382. usb_audio_rx_format_get, usb_audio_rx_format_put),
  3383. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  3384. usb_audio_tx_format_get, usb_audio_tx_format_put),
  3385. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  3386. tdm_rx_format_get,
  3387. tdm_rx_format_put),
  3388. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  3389. tdm_rx_format_get,
  3390. tdm_rx_format_put),
  3391. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3392. tdm_rx_format_get,
  3393. tdm_rx_format_put),
  3394. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3395. tdm_rx_format_get,
  3396. tdm_rx_format_put),
  3397. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3398. tdm_rx_format_get,
  3399. tdm_rx_format_put),
  3400. SOC_ENUM_EXT("SEN_TDM_RX_0 Format", tdm_rx_format,
  3401. tdm_rx_format_get,
  3402. tdm_rx_format_put),
  3403. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  3404. tdm_tx_format_get,
  3405. tdm_tx_format_put),
  3406. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  3407. tdm_tx_format_get,
  3408. tdm_tx_format_put),
  3409. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3410. tdm_tx_format_get,
  3411. tdm_tx_format_put),
  3412. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3413. tdm_tx_format_get,
  3414. tdm_tx_format_put),
  3415. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3416. tdm_tx_format_get,
  3417. tdm_tx_format_put),
  3418. SOC_ENUM_EXT("SEN_TDM_TX_0 Format", tdm_tx_format,
  3419. tdm_tx_format_get,
  3420. tdm_tx_format_put),
  3421. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3422. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3423. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3424. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3425. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3426. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3427. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3428. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3429. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3430. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3431. SOC_ENUM_EXT("SEN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3432. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3433. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3434. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3435. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3436. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3437. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3438. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3439. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3440. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3441. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3442. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3443. SOC_ENUM_EXT("SEN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3444. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3445. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3446. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3447. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3448. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3449. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3450. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3451. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3452. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3453. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3454. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3455. SOC_ENUM_EXT("SEN_MI2S_RX Format", mi2s_rx_format,
  3456. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3457. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3458. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3459. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3460. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3461. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3462. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3463. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3464. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3465. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3466. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3467. SOC_ENUM_EXT("SEN_MI2S_TX Format", mi2s_tx_format,
  3468. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3469. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  3470. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  3471. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  3472. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  3473. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  3474. proxy_rx_ch_get, proxy_rx_ch_put),
  3475. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  3476. tdm_rx_ch_get,
  3477. tdm_rx_ch_put),
  3478. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  3479. tdm_rx_ch_get,
  3480. tdm_rx_ch_put),
  3481. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3482. tdm_rx_ch_get,
  3483. tdm_rx_ch_put),
  3484. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3485. tdm_rx_ch_get,
  3486. tdm_rx_ch_put),
  3487. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3488. tdm_rx_ch_get,
  3489. tdm_rx_ch_put),
  3490. SOC_ENUM_EXT("SEN_TDM_RX_0 Channels", tdm_rx_chs,
  3491. tdm_rx_ch_get,
  3492. tdm_rx_ch_put),
  3493. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  3494. tdm_tx_ch_get,
  3495. tdm_tx_ch_put),
  3496. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3497. tdm_tx_ch_get,
  3498. tdm_tx_ch_put),
  3499. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3500. tdm_tx_ch_get,
  3501. tdm_tx_ch_put),
  3502. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3503. tdm_tx_ch_get,
  3504. tdm_tx_ch_put),
  3505. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3506. tdm_tx_ch_get,
  3507. tdm_tx_ch_put),
  3508. SOC_ENUM_EXT("SEN_TDM_TX_0 Channels", tdm_tx_chs,
  3509. tdm_tx_ch_get,
  3510. tdm_tx_ch_put),
  3511. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3512. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3513. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3514. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3515. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3516. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3517. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3518. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3519. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3520. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3521. SOC_ENUM_EXT("SEN_MI2S_RX Channels", sen_mi2s_rx_chs,
  3522. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3523. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3524. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3525. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3526. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3527. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3528. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3529. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3530. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3531. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3532. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3533. SOC_ENUM_EXT("SEN_MI2S_TX Channels", sen_mi2s_tx_chs,
  3534. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3535. SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
  3536. ext_disp_rx_ch_get, ext_disp_rx_ch_put),
  3537. SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
  3538. ext_disp_rx_format_get, ext_disp_rx_format_put),
  3539. SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
  3540. ext_disp_rx_sample_rate_get,
  3541. ext_disp_rx_sample_rate_put),
  3542. SOC_ENUM_EXT("Display Port1 RX Channels", ext_disp_rx_chs,
  3543. ext_disp_rx_ch_get, ext_disp_rx_ch_put),
  3544. SOC_ENUM_EXT("Display Port1 RX Bit Format", ext_disp_rx_format,
  3545. ext_disp_rx_format_get, ext_disp_rx_format_put),
  3546. SOC_ENUM_EXT("Display Port1 RX SampleRate", ext_disp_rx_sample_rate,
  3547. ext_disp_rx_sample_rate_get,
  3548. ext_disp_rx_sample_rate_put),
  3549. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  3550. msm_bt_sample_rate_get,
  3551. msm_bt_sample_rate_put),
  3552. SOC_ENUM_EXT("BT SampleRate RX", bt_sample_rate_rx,
  3553. msm_bt_sample_rate_rx_get,
  3554. msm_bt_sample_rate_rx_put),
  3555. SOC_ENUM_EXT("BT SampleRate TX", bt_sample_rate_tx,
  3556. msm_bt_sample_rate_tx_get,
  3557. msm_bt_sample_rate_tx_put),
  3558. SOC_ENUM_EXT("AFE_LOOPBACK_TX Channels", afe_loopback_tx_chs,
  3559. afe_loopback_tx_ch_get, afe_loopback_tx_ch_put),
  3560. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  3561. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  3562. SOC_SINGLE_MULTI_EXT("TDM Slot Map", SND_SOC_NOPM, 0, 255, 0,
  3563. TDM_MAX_SLOTS + MAX_PATH, NULL, tdm_slot_map_put),
  3564. };
  3565. static const struct snd_kcontrol_new msm_snd_controls[] = {
  3566. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3567. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3568. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3569. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3570. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3571. aux_pcm_rx_sample_rate_get,
  3572. aux_pcm_rx_sample_rate_put),
  3573. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3574. aux_pcm_tx_sample_rate_get,
  3575. aux_pcm_tx_sample_rate_put),
  3576. };
  3577. static int msm_ext_disp_get_idx_from_beid(int32_t be_id)
  3578. {
  3579. int idx;
  3580. switch (be_id) {
  3581. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  3582. idx = EXT_DISP_RX_IDX_DP;
  3583. break;
  3584. case MSM_BACKEND_DAI_DISPLAY_PORT_RX_1:
  3585. idx = EXT_DISP_RX_IDX_DP1;
  3586. break;
  3587. default:
  3588. pr_err("%s: Incorrect ext_disp BE id %d\n", __func__, be_id);
  3589. idx = -EINVAL;
  3590. break;
  3591. }
  3592. return idx;
  3593. }
  3594. static int kona_send_island_va_config(int32_t be_id)
  3595. {
  3596. int rc = 0;
  3597. int port_id = 0xFFFF;
  3598. port_id = msm_get_port_id(be_id);
  3599. if (port_id < 0) {
  3600. pr_err("%s: Invalid island interface, be_id: %d\n",
  3601. __func__, be_id);
  3602. rc = -EINVAL;
  3603. } else {
  3604. /*
  3605. * send island mode config
  3606. * This should be the first configuration
  3607. */
  3608. rc = afe_send_port_island_mode(port_id);
  3609. if (rc)
  3610. pr_err("%s: afe send island mode failed %d\n",
  3611. __func__, rc);
  3612. }
  3613. return rc;
  3614. }
  3615. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3616. struct snd_pcm_hw_params *params)
  3617. {
  3618. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3619. struct snd_interval *rate = hw_param_interval(params,
  3620. SNDRV_PCM_HW_PARAM_RATE);
  3621. struct snd_interval *channels = hw_param_interval(params,
  3622. SNDRV_PCM_HW_PARAM_CHANNELS);
  3623. int idx = 0, rc = 0;
  3624. pr_debug("%s: dai_id= %d, format = %d, rate = %d\n",
  3625. __func__, dai_link->id, params_format(params),
  3626. params_rate(params));
  3627. switch (dai_link->id) {
  3628. case MSM_BACKEND_DAI_USB_RX:
  3629. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3630. usb_rx_cfg.bit_format);
  3631. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3632. channels->min = channels->max = usb_rx_cfg.channels;
  3633. break;
  3634. case MSM_BACKEND_DAI_USB_TX:
  3635. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3636. usb_tx_cfg.bit_format);
  3637. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3638. channels->min = channels->max = usb_tx_cfg.channels;
  3639. break;
  3640. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  3641. case MSM_BACKEND_DAI_DISPLAY_PORT_RX_1:
  3642. idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
  3643. if (idx < 0) {
  3644. pr_err("%s: Incorrect ext disp idx %d\n",
  3645. __func__, idx);
  3646. rc = idx;
  3647. goto done;
  3648. }
  3649. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3650. ext_disp_rx_cfg[idx].bit_format);
  3651. rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
  3652. channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
  3653. break;
  3654. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3655. channels->min = channels->max = proxy_rx_cfg.channels;
  3656. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3657. break;
  3658. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3659. channels->min = channels->max =
  3660. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3661. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3662. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3663. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3664. break;
  3665. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3666. channels->min = channels->max =
  3667. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3668. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3669. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3670. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3671. break;
  3672. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3673. channels->min = channels->max =
  3674. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3675. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3676. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3677. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3678. break;
  3679. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3680. channels->min = channels->max =
  3681. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3682. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3683. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3684. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3685. break;
  3686. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3687. channels->min = channels->max =
  3688. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3689. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3690. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3691. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3692. break;
  3693. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3694. channels->min = channels->max =
  3695. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3696. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3697. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3698. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3699. break;
  3700. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3701. channels->min = channels->max =
  3702. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3703. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3704. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3705. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3706. break;
  3707. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3708. channels->min = channels->max =
  3709. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3710. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3711. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3712. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3713. break;
  3714. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3715. channels->min = channels->max =
  3716. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3717. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3718. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3719. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3720. break;
  3721. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3722. channels->min = channels->max =
  3723. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3724. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3725. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3726. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3727. break;
  3728. case MSM_BACKEND_DAI_SEN_TDM_RX_0:
  3729. channels->min = channels->max =
  3730. tdm_rx_cfg[TDM_SEN][TDM_0].channels;
  3731. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3732. tdm_rx_cfg[TDM_SEN][TDM_0].bit_format);
  3733. rate->min = rate->max = tdm_rx_cfg[TDM_SEN][TDM_0].sample_rate;
  3734. break;
  3735. case MSM_BACKEND_DAI_SEN_TDM_TX_0:
  3736. channels->min = channels->max =
  3737. tdm_tx_cfg[TDM_SEN][TDM_0].channels;
  3738. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3739. tdm_tx_cfg[TDM_SEN][TDM_0].bit_format);
  3740. rate->min = rate->max = tdm_tx_cfg[TDM_SEN][TDM_0].sample_rate;
  3741. break;
  3742. case MSM_BACKEND_DAI_AUXPCM_RX:
  3743. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3744. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3745. rate->min = rate->max =
  3746. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3747. channels->min = channels->max =
  3748. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3749. break;
  3750. case MSM_BACKEND_DAI_AUXPCM_TX:
  3751. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3752. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3753. rate->min = rate->max =
  3754. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3755. channels->min = channels->max =
  3756. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3757. break;
  3758. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3759. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3760. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3761. rate->min = rate->max =
  3762. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3763. channels->min = channels->max =
  3764. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3765. break;
  3766. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3767. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3768. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3769. rate->min = rate->max =
  3770. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3771. channels->min = channels->max =
  3772. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3773. break;
  3774. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3775. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3776. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3777. rate->min = rate->max =
  3778. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3779. channels->min = channels->max =
  3780. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3781. break;
  3782. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3783. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3784. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3785. rate->min = rate->max =
  3786. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3787. channels->min = channels->max =
  3788. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3789. break;
  3790. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3791. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3792. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3793. rate->min = rate->max =
  3794. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3795. channels->min = channels->max =
  3796. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3797. break;
  3798. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3799. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3800. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3801. rate->min = rate->max =
  3802. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3803. channels->min = channels->max =
  3804. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3805. break;
  3806. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3807. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3808. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3809. rate->min = rate->max =
  3810. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3811. channels->min = channels->max =
  3812. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3813. break;
  3814. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3815. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3816. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3817. rate->min = rate->max =
  3818. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3819. channels->min = channels->max =
  3820. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3821. break;
  3822. case MSM_BACKEND_DAI_SEN_AUXPCM_RX:
  3823. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3824. aux_pcm_rx_cfg[SEN_AUX_PCM].bit_format);
  3825. rate->min = rate->max =
  3826. aux_pcm_rx_cfg[SEN_AUX_PCM].sample_rate;
  3827. channels->min = channels->max =
  3828. aux_pcm_rx_cfg[SEN_AUX_PCM].channels;
  3829. break;
  3830. case MSM_BACKEND_DAI_SEN_AUXPCM_TX:
  3831. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3832. aux_pcm_tx_cfg[SEN_AUX_PCM].bit_format);
  3833. rate->min = rate->max =
  3834. aux_pcm_tx_cfg[SEN_AUX_PCM].sample_rate;
  3835. channels->min = channels->max =
  3836. aux_pcm_tx_cfg[SEN_AUX_PCM].channels;
  3837. break;
  3838. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3839. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3840. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3841. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3842. channels->min = channels->max =
  3843. mi2s_rx_cfg[PRIM_MI2S].channels;
  3844. break;
  3845. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3846. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3847. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3848. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3849. channels->min = channels->max =
  3850. mi2s_tx_cfg[PRIM_MI2S].channels;
  3851. break;
  3852. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3853. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3854. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3855. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3856. channels->min = channels->max =
  3857. mi2s_rx_cfg[SEC_MI2S].channels;
  3858. break;
  3859. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3860. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3861. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3862. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3863. channels->min = channels->max =
  3864. mi2s_tx_cfg[SEC_MI2S].channels;
  3865. break;
  3866. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3867. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3868. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3869. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3870. channels->min = channels->max =
  3871. mi2s_rx_cfg[TERT_MI2S].channels;
  3872. break;
  3873. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3874. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3875. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3876. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3877. channels->min = channels->max =
  3878. mi2s_tx_cfg[TERT_MI2S].channels;
  3879. break;
  3880. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3881. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3882. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3883. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3884. channels->min = channels->max =
  3885. mi2s_rx_cfg[QUAT_MI2S].channels;
  3886. break;
  3887. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3888. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3889. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3890. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3891. channels->min = channels->max =
  3892. mi2s_tx_cfg[QUAT_MI2S].channels;
  3893. break;
  3894. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3895. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3896. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3897. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3898. channels->min = channels->max =
  3899. mi2s_rx_cfg[QUIN_MI2S].channels;
  3900. break;
  3901. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3902. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3903. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3904. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3905. channels->min = channels->max =
  3906. mi2s_tx_cfg[QUIN_MI2S].channels;
  3907. break;
  3908. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  3909. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3910. mi2s_rx_cfg[SEN_MI2S].bit_format);
  3911. rate->min = rate->max = mi2s_rx_cfg[SEN_MI2S].sample_rate;
  3912. channels->min = channels->max =
  3913. mi2s_rx_cfg[SEN_MI2S].channels;
  3914. break;
  3915. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  3916. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3917. mi2s_tx_cfg[SEN_MI2S].bit_format);
  3918. rate->min = rate->max = mi2s_tx_cfg[SEN_MI2S].sample_rate;
  3919. channels->min = channels->max =
  3920. mi2s_tx_cfg[SEN_MI2S].channels;
  3921. break;
  3922. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3923. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3924. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3925. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3926. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3927. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3928. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3929. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3930. cdc_dma_rx_cfg[idx].bit_format);
  3931. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3932. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3933. break;
  3934. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3935. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3936. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3937. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3938. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3939. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3940. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3941. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3942. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3943. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3944. cdc_dma_tx_cfg[idx].bit_format);
  3945. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3946. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3947. break;
  3948. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3949. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3950. SNDRV_PCM_FORMAT_S32_LE);
  3951. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3952. channels->min = channels->max = msm_vi_feed_tx_ch;
  3953. break;
  3954. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3955. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3956. slim_rx_cfg[SLIM_RX_7].bit_format);
  3957. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3958. channels->min = channels->max =
  3959. slim_rx_cfg[SLIM_RX_7].channels;
  3960. break;
  3961. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3962. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3963. channels->min = channels->max =
  3964. slim_tx_cfg[SLIM_TX_7].channels;
  3965. break;
  3966. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3967. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3968. channels->min = channels->max =
  3969. slim_tx_cfg[SLIM_TX_8].channels;
  3970. break;
  3971. case MSM_BACKEND_DAI_AFE_LOOPBACK_TX:
  3972. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3973. afe_loopback_tx_cfg[idx].bit_format);
  3974. rate->min = rate->max = afe_loopback_tx_cfg[idx].sample_rate;
  3975. channels->min = channels->max =
  3976. afe_loopback_tx_cfg[idx].channels;
  3977. break;
  3978. default:
  3979. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3980. break;
  3981. }
  3982. done:
  3983. return rc;
  3984. }
  3985. static bool msm_usbc_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3986. {
  3987. struct snd_soc_card *card = component->card;
  3988. struct msm_asoc_mach_data *pdata =
  3989. snd_soc_card_get_drvdata(card);
  3990. if (!pdata->fsa_handle)
  3991. return false;
  3992. return fsa4480_switch_event(pdata->fsa_handle, FSA_MIC_GND_SWAP);
  3993. }
  3994. static bool msm_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3995. {
  3996. int value = 0;
  3997. bool ret = false;
  3998. struct snd_soc_card *card;
  3999. struct msm_asoc_mach_data *pdata;
  4000. if (!component) {
  4001. pr_err("%s component is NULL\n", __func__);
  4002. return false;
  4003. }
  4004. card = component->card;
  4005. pdata = snd_soc_card_get_drvdata(card);
  4006. if (!pdata)
  4007. return false;
  4008. if (wcd_mbhc_cfg.enable_usbc_analog)
  4009. return msm_usbc_swap_gnd_mic(component, active);
  4010. /* if usbc is not defined, swap using us_euro_gpio_p */
  4011. if (pdata->us_euro_gpio_p) {
  4012. value = msm_cdc_pinctrl_get_state(
  4013. pdata->us_euro_gpio_p);
  4014. if (value)
  4015. msm_cdc_pinctrl_select_sleep_state(
  4016. pdata->us_euro_gpio_p);
  4017. else
  4018. msm_cdc_pinctrl_select_active_state(
  4019. pdata->us_euro_gpio_p);
  4020. dev_dbg(component->dev, "%s: swap select switch %d to %d\n",
  4021. __func__, value, !value);
  4022. ret = true;
  4023. }
  4024. return ret;
  4025. }
  4026. static int kona_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4027. struct snd_pcm_hw_params *params)
  4028. {
  4029. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4030. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4031. int ret = 0;
  4032. int slot_width = TDM_SLOT_WIDTH_BITS;
  4033. int channels, slots = TDM_MAX_SLOTS;
  4034. unsigned int slot_mask, rate, clk_freq;
  4035. unsigned int *slot_offset;
  4036. struct tdm_dev_config *config;
  4037. unsigned int path_dir = 0, interface = 0, channel_interface = 0;
  4038. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4039. if (cpu_dai->id < AFE_PORT_ID_TDM_PORT_RANGE_START) {
  4040. pr_err("%s: dai id 0x%x not supported\n",
  4041. __func__, cpu_dai->id);
  4042. return -EINVAL;
  4043. }
  4044. /* RX or TX */
  4045. path_dir = cpu_dai->id % MAX_PATH;
  4046. /* PRI, SEC, TERT, QUAT, QUIN, ... */
  4047. interface = (cpu_dai->id - AFE_PORT_ID_TDM_PORT_RANGE_START)
  4048. / (MAX_PATH * TDM_PORT_MAX);
  4049. /* 0, 1, 2, .. 7 */
  4050. channel_interface =
  4051. ((cpu_dai->id - AFE_PORT_ID_TDM_PORT_RANGE_START) / MAX_PATH)
  4052. % TDM_PORT_MAX;
  4053. pr_debug("%s: path dir: %u, interface %u, channel interface %u\n",
  4054. __func__, path_dir, interface, channel_interface);
  4055. config = ((struct tdm_dev_config *) tdm_cfg[interface]) +
  4056. (path_dir * TDM_PORT_MAX) + channel_interface;
  4057. slot_offset = config->tdm_slot_offset;
  4058. if (path_dir)
  4059. channels = tdm_tx_cfg[interface][channel_interface].channels;
  4060. else
  4061. channels = tdm_rx_cfg[interface][channel_interface].channels;
  4062. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4063. /*2 slot config - bits 0 and 1 set for the first two slots */
  4064. slot_mask = 0x0000FFFF >> (16 - slots);
  4065. pr_debug("%s: tdm rx slot_width %d slots %d slot_mask %x\n",
  4066. __func__, slot_width, slots, slot_mask);
  4067. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4068. slots, slot_width);
  4069. if (ret < 0) {
  4070. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4071. __func__, ret);
  4072. goto end;
  4073. }
  4074. pr_debug("%s: tdm rx channels: %d\n", __func__, channels);
  4075. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4076. 0, NULL, channels, slot_offset);
  4077. if (ret < 0) {
  4078. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4079. __func__, ret);
  4080. goto end;
  4081. }
  4082. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4083. /*2 slot config - bits 0 and 1 set for the first two slots */
  4084. slot_mask = 0x0000FFFF >> (16 - slots);
  4085. pr_debug("%s: tdm tx slot_width %d slots %d slot_mask %x\n",
  4086. __func__, slot_width, slots, slot_mask);
  4087. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4088. slots, slot_width);
  4089. if (ret < 0) {
  4090. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4091. __func__, ret);
  4092. goto end;
  4093. }
  4094. pr_debug("%s: tdm tx channels: %d\n", __func__, channels);
  4095. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4096. channels, slot_offset, 0, NULL);
  4097. if (ret < 0) {
  4098. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4099. __func__, ret);
  4100. goto end;
  4101. }
  4102. } else {
  4103. ret = -EINVAL;
  4104. pr_err("%s: invalid use case, err:%d\n",
  4105. __func__, ret);
  4106. goto end;
  4107. }
  4108. rate = params_rate(params);
  4109. clk_freq = rate * slot_width * slots;
  4110. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4111. if (ret < 0)
  4112. pr_err("%s: failed to set tdm clk, err:%d\n",
  4113. __func__, ret);
  4114. end:
  4115. return ret;
  4116. }
  4117. static int msm_get_tdm_mode(u32 port_id)
  4118. {
  4119. int tdm_mode;
  4120. switch (port_id) {
  4121. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4122. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4123. tdm_mode = TDM_PRI;
  4124. break;
  4125. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4126. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4127. tdm_mode = TDM_SEC;
  4128. break;
  4129. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4130. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4131. tdm_mode = TDM_TERT;
  4132. break;
  4133. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4134. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4135. tdm_mode = TDM_QUAT;
  4136. break;
  4137. case AFE_PORT_ID_QUINARY_TDM_RX:
  4138. case AFE_PORT_ID_QUINARY_TDM_TX:
  4139. tdm_mode = TDM_QUIN;
  4140. break;
  4141. case AFE_PORT_ID_SENARY_TDM_RX:
  4142. case AFE_PORT_ID_SENARY_TDM_TX:
  4143. tdm_mode = TDM_SEN;
  4144. break;
  4145. default:
  4146. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  4147. tdm_mode = -EINVAL;
  4148. }
  4149. return tdm_mode;
  4150. }
  4151. static int kona_tdm_snd_startup(struct snd_pcm_substream *substream)
  4152. {
  4153. int ret = 0;
  4154. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4155. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4156. struct snd_soc_card *card = rtd->card;
  4157. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4158. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4159. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  4160. ret = -EINVAL;
  4161. pr_err("%s: Invalid TDM interface %d\n",
  4162. __func__, ret);
  4163. return ret;
  4164. }
  4165. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4166. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  4167. == 0) {
  4168. ret = msm_cdc_pinctrl_select_active_state(
  4169. pdata->mi2s_gpio_p[tdm_mode]);
  4170. if (ret) {
  4171. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  4172. __func__, ret);
  4173. goto done;
  4174. }
  4175. }
  4176. atomic_inc(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  4177. }
  4178. done:
  4179. return ret;
  4180. }
  4181. static void kona_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4182. {
  4183. int ret = 0;
  4184. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4185. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4186. struct snd_soc_card *card = rtd->card;
  4187. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4188. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4189. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  4190. ret = -EINVAL;
  4191. pr_err("%s: Invalid TDM interface %d\n",
  4192. __func__, ret);
  4193. return;
  4194. }
  4195. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4196. atomic_dec(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  4197. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  4198. == 0) {
  4199. ret = msm_cdc_pinctrl_select_sleep_state(
  4200. pdata->mi2s_gpio_p[tdm_mode]);
  4201. if (ret)
  4202. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  4203. __func__, ret);
  4204. }
  4205. }
  4206. }
  4207. static int kona_aux_snd_startup(struct snd_pcm_substream *substream)
  4208. {
  4209. int ret = 0;
  4210. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4211. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4212. struct snd_soc_card *card = rtd->card;
  4213. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4214. u32 aux_mode = cpu_dai->id - 1;
  4215. if (aux_mode >= AUX_PCM_MAX) {
  4216. ret = -EINVAL;
  4217. pr_err("%s: Invalid AUX interface %d\n",
  4218. __func__, ret);
  4219. return ret;
  4220. }
  4221. if (pdata->mi2s_gpio_p[aux_mode]) {
  4222. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  4223. == 0) {
  4224. ret = msm_cdc_pinctrl_select_active_state(
  4225. pdata->mi2s_gpio_p[aux_mode]);
  4226. if (ret) {
  4227. pr_err("%s: AUX GPIO pinctrl set active failed with %d\n",
  4228. __func__, ret);
  4229. goto done;
  4230. }
  4231. }
  4232. atomic_inc(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  4233. }
  4234. done:
  4235. return ret;
  4236. }
  4237. static void kona_aux_snd_shutdown(struct snd_pcm_substream *substream)
  4238. {
  4239. int ret = 0;
  4240. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4241. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4242. struct snd_soc_card *card = rtd->card;
  4243. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4244. u32 aux_mode = cpu_dai->id - 1;
  4245. if (aux_mode >= AUX_PCM_MAX) {
  4246. pr_err("%s: Invalid AUX interface %d\n",
  4247. __func__, ret);
  4248. return;
  4249. }
  4250. if (pdata->mi2s_gpio_p[aux_mode]) {
  4251. atomic_dec(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  4252. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  4253. == 0) {
  4254. ret = msm_cdc_pinctrl_select_sleep_state(
  4255. pdata->mi2s_gpio_p[aux_mode]);
  4256. if (ret)
  4257. pr_err("%s: AUX GPIO pinctrl set sleep failed with %d\n",
  4258. __func__, ret);
  4259. }
  4260. }
  4261. }
  4262. static int msm_snd_cdc_dma_startup(struct snd_pcm_substream *substream)
  4263. {
  4264. int ret = 0;
  4265. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4266. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4267. switch (dai_link->id) {
  4268. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4269. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4270. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  4271. ret = kona_send_island_va_config(dai_link->id);
  4272. if (ret)
  4273. pr_err("%s: send island va cfg failed, err: %d\n",
  4274. __func__, ret);
  4275. break;
  4276. }
  4277. return ret;
  4278. }
  4279. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4280. struct snd_pcm_hw_params *params)
  4281. {
  4282. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4283. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4284. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4285. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4286. int ret = 0;
  4287. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4288. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4289. u32 user_set_tx_ch = 0;
  4290. u32 user_set_rx_ch = 0;
  4291. u32 ch_id;
  4292. ret = snd_soc_dai_get_channel_map(codec_dai,
  4293. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4294. &rx_ch_cdc_dma);
  4295. if (ret < 0) {
  4296. pr_err("%s: failed to get codec chan map, err:%d\n",
  4297. __func__, ret);
  4298. goto err;
  4299. }
  4300. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4301. switch (dai_link->id) {
  4302. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4303. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4304. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  4305. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  4306. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  4307. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  4308. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_4:
  4309. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  4310. {
  4311. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4312. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4313. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4314. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4315. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4316. user_set_rx_ch, &rx_ch_cdc_dma);
  4317. if (ret < 0) {
  4318. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4319. __func__, ret);
  4320. goto err;
  4321. }
  4322. }
  4323. break;
  4324. }
  4325. } else {
  4326. switch (dai_link->id) {
  4327. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4328. {
  4329. user_set_tx_ch = msm_vi_feed_tx_ch;
  4330. }
  4331. break;
  4332. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4333. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4334. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  4335. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  4336. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  4337. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4338. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4339. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  4340. {
  4341. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4342. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4343. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4344. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4345. }
  4346. break;
  4347. }
  4348. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4349. &tx_ch_cdc_dma, 0, 0);
  4350. if (ret < 0) {
  4351. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4352. __func__, ret);
  4353. goto err;
  4354. }
  4355. }
  4356. err:
  4357. return ret;
  4358. }
  4359. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4360. {
  4361. cpumask_t mask;
  4362. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4363. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4364. cpumask_clear(&mask);
  4365. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4366. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4367. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4368. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4369. pm_qos_add_request(&substream->latency_pm_qos_req,
  4370. PM_QOS_CPU_DMA_LATENCY,
  4371. MSM_LL_QOS_VALUE);
  4372. return 0;
  4373. }
  4374. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4375. {
  4376. int ret = 0;
  4377. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4378. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4379. int index = cpu_dai->id;
  4380. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4381. struct snd_soc_card *card = rtd->card;
  4382. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4383. dev_dbg(rtd->card->dev,
  4384. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4385. __func__, substream->name, substream->stream,
  4386. cpu_dai->name, cpu_dai->id);
  4387. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4388. ret = -EINVAL;
  4389. dev_err(rtd->card->dev,
  4390. "%s: CPU DAI id (%d) out of range\n",
  4391. __func__, cpu_dai->id);
  4392. goto err;
  4393. }
  4394. /*
  4395. * Mutex protection in case the same MI2S
  4396. * interface using for both TX and RX so
  4397. * that the same clock won't be enable twice.
  4398. */
  4399. mutex_lock(&mi2s_intf_conf[index].lock);
  4400. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4401. /* Check if msm needs to provide the clock to the interface */
  4402. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4403. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4404. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4405. }
  4406. ret = msm_mi2s_set_sclk(substream, true);
  4407. if (ret < 0) {
  4408. dev_err(rtd->card->dev,
  4409. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4410. __func__, ret);
  4411. goto clean_up;
  4412. }
  4413. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4414. if (ret < 0) {
  4415. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4416. __func__, index, ret);
  4417. goto clk_off;
  4418. }
  4419. if (pdata->mi2s_gpio_p[index]) {
  4420. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  4421. == 0) {
  4422. ret = msm_cdc_pinctrl_select_active_state(
  4423. pdata->mi2s_gpio_p[index]);
  4424. if (ret) {
  4425. pr_err("%s: MI2S GPIO pinctrl set active failed with %d\n",
  4426. __func__, ret);
  4427. goto clk_off;
  4428. }
  4429. }
  4430. atomic_inc(&(pdata->mi2s_gpio_ref_count[index]));
  4431. }
  4432. }
  4433. clk_off:
  4434. if (ret < 0)
  4435. msm_mi2s_set_sclk(substream, false);
  4436. clean_up:
  4437. if (ret < 0)
  4438. mi2s_intf_conf[index].ref_cnt--;
  4439. mutex_unlock(&mi2s_intf_conf[index].lock);
  4440. err:
  4441. return ret;
  4442. }
  4443. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4444. {
  4445. int ret = 0;
  4446. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4447. int index = rtd->cpu_dai->id;
  4448. struct snd_soc_card *card = rtd->card;
  4449. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4450. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4451. substream->name, substream->stream);
  4452. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4453. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4454. return;
  4455. }
  4456. mutex_lock(&mi2s_intf_conf[index].lock);
  4457. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4458. if (pdata->mi2s_gpio_p[index]) {
  4459. atomic_dec(&(pdata->mi2s_gpio_ref_count[index]));
  4460. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  4461. == 0) {
  4462. ret = msm_cdc_pinctrl_select_sleep_state(
  4463. pdata->mi2s_gpio_p[index]);
  4464. if (ret)
  4465. pr_err("%s: MI2S GPIO pinctrl set sleep failed with %d\n",
  4466. __func__, ret);
  4467. }
  4468. }
  4469. ret = msm_mi2s_set_sclk(substream, false);
  4470. if (ret < 0)
  4471. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4472. __func__, index, ret);
  4473. }
  4474. mutex_unlock(&mi2s_intf_conf[index].lock);
  4475. }
  4476. static int msm_wcn_hw_params_lito(struct snd_pcm_substream *substream,
  4477. struct snd_pcm_hw_params *params)
  4478. {
  4479. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4480. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4481. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4482. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4483. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO];
  4484. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4485. int ret = 0;
  4486. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4487. codec_dai->name, codec_dai->id);
  4488. ret = snd_soc_dai_get_channel_map(codec_dai,
  4489. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4490. if (ret) {
  4491. dev_err(rtd->dev,
  4492. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4493. __func__, ret);
  4494. goto err;
  4495. }
  4496. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4497. __func__, tx_ch_cnt, dai_link->id);
  4498. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4499. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4500. if (ret)
  4501. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4502. __func__, ret);
  4503. err:
  4504. return ret;
  4505. }
  4506. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4507. struct snd_pcm_hw_params *params)
  4508. {
  4509. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4510. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4511. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4512. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4513. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4514. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4515. int ret = 0;
  4516. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4517. codec_dai->name, codec_dai->id);
  4518. ret = snd_soc_dai_get_channel_map(codec_dai,
  4519. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4520. if (ret) {
  4521. dev_err(rtd->dev,
  4522. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4523. __func__, ret);
  4524. goto err;
  4525. }
  4526. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4527. __func__, tx_ch_cnt, dai_link->id);
  4528. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4529. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4530. if (ret)
  4531. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4532. __func__, ret);
  4533. err:
  4534. return ret;
  4535. }
  4536. static struct snd_soc_ops kona_aux_be_ops = {
  4537. .startup = kona_aux_snd_startup,
  4538. .shutdown = kona_aux_snd_shutdown
  4539. };
  4540. static struct snd_soc_ops kona_tdm_be_ops = {
  4541. .hw_params = kona_tdm_snd_hw_params,
  4542. .startup = kona_tdm_snd_startup,
  4543. .shutdown = kona_tdm_snd_shutdown
  4544. };
  4545. static struct snd_soc_ops msm_mi2s_be_ops = {
  4546. .startup = msm_mi2s_snd_startup,
  4547. .shutdown = msm_mi2s_snd_shutdown,
  4548. };
  4549. static struct snd_soc_ops msm_fe_qos_ops = {
  4550. .prepare = msm_fe_qos_prepare,
  4551. };
  4552. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  4553. .startup = msm_snd_cdc_dma_startup,
  4554. .hw_params = msm_snd_cdc_dma_hw_params,
  4555. };
  4556. static struct snd_soc_ops msm_wcn_ops = {
  4557. .hw_params = msm_wcn_hw_params,
  4558. };
  4559. static struct snd_soc_ops msm_wcn_ops_lito = {
  4560. .hw_params = msm_wcn_hw_params_lito,
  4561. };
  4562. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  4563. struct snd_kcontrol *kcontrol, int event)
  4564. {
  4565. struct msm_asoc_mach_data *pdata = NULL;
  4566. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  4567. int ret = 0;
  4568. u32 dmic_idx;
  4569. int *dmic_gpio_cnt;
  4570. struct device_node *dmic_gpio;
  4571. char *wname;
  4572. wname = strpbrk(w->name, "012345");
  4573. if (!wname) {
  4574. dev_err(component->dev, "%s: widget not found\n", __func__);
  4575. return -EINVAL;
  4576. }
  4577. ret = kstrtouint(wname, 10, &dmic_idx);
  4578. if (ret < 0) {
  4579. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  4580. __func__);
  4581. return -EINVAL;
  4582. }
  4583. pdata = snd_soc_card_get_drvdata(component->card);
  4584. switch (dmic_idx) {
  4585. case 0:
  4586. case 1:
  4587. dmic_gpio_cnt = &dmic_0_1_gpio_cnt;
  4588. dmic_gpio = pdata->dmic01_gpio_p;
  4589. break;
  4590. case 2:
  4591. case 3:
  4592. dmic_gpio_cnt = &dmic_2_3_gpio_cnt;
  4593. dmic_gpio = pdata->dmic23_gpio_p;
  4594. break;
  4595. case 4:
  4596. case 5:
  4597. dmic_gpio_cnt = &dmic_4_5_gpio_cnt;
  4598. dmic_gpio = pdata->dmic45_gpio_p;
  4599. break;
  4600. default:
  4601. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  4602. __func__);
  4603. return -EINVAL;
  4604. }
  4605. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  4606. __func__, event, dmic_idx, *dmic_gpio_cnt);
  4607. switch (event) {
  4608. case SND_SOC_DAPM_PRE_PMU:
  4609. (*dmic_gpio_cnt)++;
  4610. if (*dmic_gpio_cnt == 1) {
  4611. ret = msm_cdc_pinctrl_select_active_state(
  4612. dmic_gpio);
  4613. if (ret < 0) {
  4614. pr_err("%s: gpio set cannot be activated %sd",
  4615. __func__, "dmic_gpio");
  4616. return ret;
  4617. }
  4618. }
  4619. break;
  4620. case SND_SOC_DAPM_POST_PMD:
  4621. (*dmic_gpio_cnt)--;
  4622. if (*dmic_gpio_cnt == 0) {
  4623. ret = msm_cdc_pinctrl_select_sleep_state(
  4624. dmic_gpio);
  4625. if (ret < 0) {
  4626. pr_err("%s: gpio set cannot be de-activated %sd",
  4627. __func__, "dmic_gpio");
  4628. return ret;
  4629. }
  4630. }
  4631. break;
  4632. default:
  4633. pr_err("%s: invalid DAPM event %d\n", __func__, event);
  4634. return -EINVAL;
  4635. }
  4636. return 0;
  4637. }
  4638. static const struct snd_soc_dapm_widget msm_int_dapm_widgets[] = {
  4639. SND_SOC_DAPM_MIC("Analog Mic1", NULL),
  4640. SND_SOC_DAPM_MIC("Analog Mic2", NULL),
  4641. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  4642. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  4643. SND_SOC_DAPM_MIC("Analog Mic5", NULL),
  4644. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  4645. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  4646. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  4647. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  4648. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  4649. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  4650. SND_SOC_DAPM_MIC("Digital Mic6", NULL),
  4651. SND_SOC_DAPM_MIC("Digital Mic7", NULL),
  4652. };
  4653. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4654. {
  4655. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4656. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160};
  4657. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4658. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4659. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4660. }
  4661. static int msm_wcn_init_lito(struct snd_soc_pcm_runtime *rtd)
  4662. {
  4663. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4664. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO] = {159, 160, 161};
  4665. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4666. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4667. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4668. }
  4669. static int msm_int_audrx_init(struct snd_soc_pcm_runtime *rtd)
  4670. {
  4671. int ret = -EINVAL;
  4672. struct snd_soc_component *component;
  4673. struct snd_soc_dapm_context *dapm;
  4674. struct snd_card *card;
  4675. struct snd_info_entry *entry;
  4676. struct snd_soc_component *aux_comp;
  4677. struct msm_asoc_mach_data *pdata =
  4678. snd_soc_card_get_drvdata(rtd->card);
  4679. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  4680. if (!component) {
  4681. pr_err("%s: could not find component for bolero_codec\n",
  4682. __func__);
  4683. return ret;
  4684. }
  4685. dapm = snd_soc_component_get_dapm(component);
  4686. ret = snd_soc_add_component_controls(component, msm_int_snd_controls,
  4687. ARRAY_SIZE(msm_int_snd_controls));
  4688. if (ret < 0) {
  4689. pr_err("%s: add_component_controls failed: %d\n",
  4690. __func__, ret);
  4691. return ret;
  4692. }
  4693. ret = snd_soc_add_component_controls(component, msm_common_snd_controls,
  4694. ARRAY_SIZE(msm_common_snd_controls));
  4695. if (ret < 0) {
  4696. pr_err("%s: add common snd controls failed: %d\n",
  4697. __func__, ret);
  4698. return ret;
  4699. }
  4700. snd_soc_dapm_new_controls(dapm, msm_int_dapm_widgets,
  4701. ARRAY_SIZE(msm_int_dapm_widgets));
  4702. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4703. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4704. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4705. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4706. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4707. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4708. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  4709. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  4710. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic1");
  4711. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic2");
  4712. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4713. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4714. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic5");
  4715. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4716. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4717. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4718. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4719. snd_soc_dapm_sync(dapm);
  4720. /*
  4721. * Send speaker configuration only for WSA8810.
  4722. * Default configuration is for WSA8815.
  4723. */
  4724. dev_dbg(component->dev, "%s: Number of aux devices: %d\n",
  4725. __func__, rtd->card->num_aux_devs);
  4726. if (rtd->card->num_aux_devs &&
  4727. !list_empty(&rtd->card->component_dev_list)) {
  4728. list_for_each_entry(aux_comp,
  4729. &rtd->card->aux_comp_list,
  4730. card_aux_list) {
  4731. if (aux_comp->name != NULL && (
  4732. !strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4733. !strcmp(aux_comp->name, WSA8810_NAME_2))) {
  4734. wsa_macro_set_spkr_mode(component,
  4735. WSA_MACRO_SPKR_MODE_1);
  4736. wsa_macro_set_spkr_gain_offset(component,
  4737. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4738. }
  4739. }
  4740. if (pdata->lito_v2_enabled) {
  4741. /*
  4742. * Enable tx data line3 for saipan version v2 amd
  4743. * write corresponding lpi register.
  4744. */
  4745. bolero_set_port_map(component, ARRAY_SIZE(sm_port_map_v2),
  4746. sm_port_map_v2);
  4747. } else {
  4748. bolero_set_port_map(component, ARRAY_SIZE(sm_port_map),
  4749. sm_port_map);
  4750. }
  4751. }
  4752. card = rtd->card->snd_card;
  4753. if (!pdata->codec_root) {
  4754. entry = snd_info_create_subdir(card->module, "codecs",
  4755. card->proc_root);
  4756. if (!entry) {
  4757. pr_debug("%s: Cannot create codecs module entry\n",
  4758. __func__);
  4759. ret = 0;
  4760. goto err;
  4761. }
  4762. pdata->codec_root = entry;
  4763. }
  4764. bolero_info_create_codec_entry(pdata->codec_root, component);
  4765. bolero_register_wake_irq(component, false);
  4766. codec_reg_done = true;
  4767. return 0;
  4768. err:
  4769. return ret;
  4770. }
  4771. static void *def_wcd_mbhc_cal(void)
  4772. {
  4773. void *wcd_mbhc_cal;
  4774. struct wcd_mbhc_btn_detect_cfg *btn_cfg;
  4775. u16 *btn_high;
  4776. wcd_mbhc_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS,
  4777. WCD9XXX_MBHC_DEF_RLOADS), GFP_KERNEL);
  4778. if (!wcd_mbhc_cal)
  4779. return NULL;
  4780. WCD_MBHC_CAL_PLUG_TYPE_PTR(wcd_mbhc_cal)->v_hs_max = WCD_MBHC_HS_V_MAX;
  4781. WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal)->num_btn = WCD_MBHC_DEF_BUTTONS;
  4782. btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal);
  4783. btn_high = ((void *)&btn_cfg->_v_btn_low) +
  4784. (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn);
  4785. btn_high[0] = 75;
  4786. btn_high[1] = 150;
  4787. btn_high[2] = 237;
  4788. btn_high[3] = 500;
  4789. btn_high[4] = 500;
  4790. btn_high[5] = 500;
  4791. btn_high[6] = 500;
  4792. btn_high[7] = 500;
  4793. return wcd_mbhc_cal;
  4794. }
  4795. /* Digital audio interface glue - connects codec <---> CPU */
  4796. static struct snd_soc_dai_link msm_common_dai_links[] = {
  4797. /* FrontEnd DAI Links */
  4798. {/* hw:x,0 */
  4799. .name = MSM_DAILINK_NAME(Media1),
  4800. .stream_name = "MultiMedia1",
  4801. .cpu_dai_name = "MultiMedia1",
  4802. .platform_name = "msm-pcm-dsp.0",
  4803. .dynamic = 1,
  4804. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4805. .dpcm_playback = 1,
  4806. .dpcm_capture = 1,
  4807. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4808. SND_SOC_DPCM_TRIGGER_POST},
  4809. .codec_dai_name = "snd-soc-dummy-dai",
  4810. .codec_name = "snd-soc-dummy",
  4811. .ignore_suspend = 1,
  4812. /* this dainlink has playback support */
  4813. .ignore_pmdown_time = 1,
  4814. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  4815. },
  4816. {/* hw:x,1 */
  4817. .name = MSM_DAILINK_NAME(Media2),
  4818. .stream_name = "MultiMedia2",
  4819. .cpu_dai_name = "MultiMedia2",
  4820. .platform_name = "msm-pcm-dsp.0",
  4821. .dynamic = 1,
  4822. .dpcm_playback = 1,
  4823. .dpcm_capture = 1,
  4824. .codec_dai_name = "snd-soc-dummy-dai",
  4825. .codec_name = "snd-soc-dummy",
  4826. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4827. SND_SOC_DPCM_TRIGGER_POST},
  4828. .ignore_suspend = 1,
  4829. /* this dainlink has playback support */
  4830. .ignore_pmdown_time = 1,
  4831. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  4832. },
  4833. {/* hw:x,2 */
  4834. .name = "VoiceMMode1",
  4835. .stream_name = "VoiceMMode1",
  4836. .cpu_dai_name = "VoiceMMode1",
  4837. .platform_name = "msm-pcm-voice",
  4838. .dynamic = 1,
  4839. .dpcm_playback = 1,
  4840. .dpcm_capture = 1,
  4841. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4842. SND_SOC_DPCM_TRIGGER_POST},
  4843. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4844. .ignore_suspend = 1,
  4845. .ignore_pmdown_time = 1,
  4846. .codec_dai_name = "snd-soc-dummy-dai",
  4847. .codec_name = "snd-soc-dummy",
  4848. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  4849. },
  4850. {/* hw:x,3 */
  4851. .name = "MSM VoIP",
  4852. .stream_name = "VoIP",
  4853. .cpu_dai_name = "VoIP",
  4854. .platform_name = "msm-voip-dsp",
  4855. .dynamic = 1,
  4856. .dpcm_playback = 1,
  4857. .dpcm_capture = 1,
  4858. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4859. SND_SOC_DPCM_TRIGGER_POST},
  4860. .codec_dai_name = "snd-soc-dummy-dai",
  4861. .codec_name = "snd-soc-dummy",
  4862. .ignore_suspend = 1,
  4863. /* this dainlink has playback support */
  4864. .ignore_pmdown_time = 1,
  4865. .id = MSM_FRONTEND_DAI_VOIP,
  4866. },
  4867. {/* hw:x,4 */
  4868. .name = MSM_DAILINK_NAME(ULL),
  4869. .stream_name = "MultiMedia3",
  4870. .cpu_dai_name = "MultiMedia3",
  4871. .platform_name = "msm-pcm-dsp.2",
  4872. .dynamic = 1,
  4873. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4874. .dpcm_playback = 1,
  4875. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4876. SND_SOC_DPCM_TRIGGER_POST},
  4877. .codec_dai_name = "snd-soc-dummy-dai",
  4878. .codec_name = "snd-soc-dummy",
  4879. .ignore_suspend = 1,
  4880. /* this dainlink has playback support */
  4881. .ignore_pmdown_time = 1,
  4882. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  4883. },
  4884. {/* hw:x,5 */
  4885. .name = "MSM AFE-PCM RX",
  4886. .stream_name = "AFE-PROXY RX",
  4887. .cpu_dai_name = "msm-dai-q6-dev.241",
  4888. .codec_name = "msm-stub-codec.1",
  4889. .codec_dai_name = "msm-stub-rx",
  4890. .platform_name = "msm-pcm-afe",
  4891. .dpcm_playback = 1,
  4892. .ignore_suspend = 1,
  4893. /* this dainlink has playback support */
  4894. .ignore_pmdown_time = 1,
  4895. },
  4896. {/* hw:x,6 */
  4897. .name = "MSM AFE-PCM TX",
  4898. .stream_name = "AFE-PROXY TX",
  4899. .cpu_dai_name = "msm-dai-q6-dev.240",
  4900. .codec_name = "msm-stub-codec.1",
  4901. .codec_dai_name = "msm-stub-tx",
  4902. .platform_name = "msm-pcm-afe",
  4903. .dpcm_capture = 1,
  4904. .ignore_suspend = 1,
  4905. },
  4906. {/* hw:x,7 */
  4907. .name = MSM_DAILINK_NAME(Compress1),
  4908. .stream_name = "Compress1",
  4909. .cpu_dai_name = "MultiMedia4",
  4910. .platform_name = "msm-compress-dsp",
  4911. .dynamic = 1,
  4912. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  4913. .dpcm_playback = 1,
  4914. .dpcm_capture = 1,
  4915. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4916. SND_SOC_DPCM_TRIGGER_POST},
  4917. .codec_dai_name = "snd-soc-dummy-dai",
  4918. .codec_name = "snd-soc-dummy",
  4919. .ignore_suspend = 1,
  4920. .ignore_pmdown_time = 1,
  4921. /* this dainlink has playback support */
  4922. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  4923. },
  4924. /* Hostless PCM purpose */
  4925. {/* hw:x,8 */
  4926. .name = "AUXPCM Hostless",
  4927. .stream_name = "AUXPCM Hostless",
  4928. .cpu_dai_name = "AUXPCM_HOSTLESS",
  4929. .platform_name = "msm-pcm-hostless",
  4930. .dynamic = 1,
  4931. .dpcm_playback = 1,
  4932. .dpcm_capture = 1,
  4933. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4934. SND_SOC_DPCM_TRIGGER_POST},
  4935. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4936. .ignore_suspend = 1,
  4937. /* this dainlink has playback support */
  4938. .ignore_pmdown_time = 1,
  4939. .codec_dai_name = "snd-soc-dummy-dai",
  4940. .codec_name = "snd-soc-dummy",
  4941. },
  4942. {/* hw:x,9 */
  4943. .name = MSM_DAILINK_NAME(LowLatency),
  4944. .stream_name = "MultiMedia5",
  4945. .cpu_dai_name = "MultiMedia5",
  4946. .platform_name = "msm-pcm-dsp.1",
  4947. .dynamic = 1,
  4948. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4949. .dpcm_playback = 1,
  4950. .dpcm_capture = 1,
  4951. .codec_dai_name = "snd-soc-dummy-dai",
  4952. .codec_name = "snd-soc-dummy",
  4953. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4954. SND_SOC_DPCM_TRIGGER_POST},
  4955. .ignore_suspend = 1,
  4956. /* this dainlink has playback support */
  4957. .ignore_pmdown_time = 1,
  4958. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  4959. .ops = &msm_fe_qos_ops,
  4960. },
  4961. {/* hw:x,10 */
  4962. .name = "Listen 1 Audio Service",
  4963. .stream_name = "Listen 1 Audio Service",
  4964. .cpu_dai_name = "LSM1",
  4965. .platform_name = "msm-lsm-client",
  4966. .dynamic = 1,
  4967. .dpcm_capture = 1,
  4968. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4969. SND_SOC_DPCM_TRIGGER_POST },
  4970. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4971. .ignore_suspend = 1,
  4972. .codec_dai_name = "snd-soc-dummy-dai",
  4973. .codec_name = "snd-soc-dummy",
  4974. .id = MSM_FRONTEND_DAI_LSM1,
  4975. },
  4976. /* Multiple Tunnel instances */
  4977. {/* hw:x,11 */
  4978. .name = MSM_DAILINK_NAME(Compress2),
  4979. .stream_name = "Compress2",
  4980. .cpu_dai_name = "MultiMedia7",
  4981. .platform_name = "msm-compress-dsp",
  4982. .dynamic = 1,
  4983. .dpcm_playback = 1,
  4984. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4985. SND_SOC_DPCM_TRIGGER_POST},
  4986. .codec_dai_name = "snd-soc-dummy-dai",
  4987. .codec_name = "snd-soc-dummy",
  4988. .ignore_suspend = 1,
  4989. .ignore_pmdown_time = 1,
  4990. /* this dainlink has playback support */
  4991. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4992. },
  4993. {/* hw:x,12 */
  4994. .name = MSM_DAILINK_NAME(MultiMedia10),
  4995. .stream_name = "MultiMedia10",
  4996. .cpu_dai_name = "MultiMedia10",
  4997. .platform_name = "msm-pcm-dsp.1",
  4998. .dynamic = 1,
  4999. .dpcm_playback = 1,
  5000. .dpcm_capture = 1,
  5001. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5002. SND_SOC_DPCM_TRIGGER_POST},
  5003. .codec_dai_name = "snd-soc-dummy-dai",
  5004. .codec_name = "snd-soc-dummy",
  5005. .ignore_suspend = 1,
  5006. .ignore_pmdown_time = 1,
  5007. /* this dainlink has playback support */
  5008. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  5009. },
  5010. {/* hw:x,13 */
  5011. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  5012. .stream_name = "MM_NOIRQ",
  5013. .cpu_dai_name = "MultiMedia8",
  5014. .platform_name = "msm-pcm-dsp-noirq",
  5015. .dynamic = 1,
  5016. .dpcm_playback = 1,
  5017. .dpcm_capture = 1,
  5018. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5019. SND_SOC_DPCM_TRIGGER_POST},
  5020. .codec_dai_name = "snd-soc-dummy-dai",
  5021. .codec_name = "snd-soc-dummy",
  5022. .ignore_suspend = 1,
  5023. .ignore_pmdown_time = 1,
  5024. /* this dainlink has playback support */
  5025. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  5026. .ops = &msm_fe_qos_ops,
  5027. },
  5028. /* HDMI Hostless */
  5029. {/* hw:x,14 */
  5030. .name = "HDMI_RX_HOSTLESS",
  5031. .stream_name = "HDMI_RX_HOSTLESS",
  5032. .cpu_dai_name = "HDMI_HOSTLESS",
  5033. .platform_name = "msm-pcm-hostless",
  5034. .dynamic = 1,
  5035. .dpcm_playback = 1,
  5036. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5037. SND_SOC_DPCM_TRIGGER_POST},
  5038. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5039. .ignore_suspend = 1,
  5040. .ignore_pmdown_time = 1,
  5041. .codec_dai_name = "snd-soc-dummy-dai",
  5042. .codec_name = "snd-soc-dummy",
  5043. },
  5044. {/* hw:x,15 */
  5045. .name = "VoiceMMode2",
  5046. .stream_name = "VoiceMMode2",
  5047. .cpu_dai_name = "VoiceMMode2",
  5048. .platform_name = "msm-pcm-voice",
  5049. .dynamic = 1,
  5050. .dpcm_playback = 1,
  5051. .dpcm_capture = 1,
  5052. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5053. SND_SOC_DPCM_TRIGGER_POST},
  5054. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5055. .ignore_suspend = 1,
  5056. .ignore_pmdown_time = 1,
  5057. .codec_dai_name = "snd-soc-dummy-dai",
  5058. .codec_name = "snd-soc-dummy",
  5059. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  5060. },
  5061. /* LSM FE */
  5062. {/* hw:x,16 */
  5063. .name = "Listen 2 Audio Service",
  5064. .stream_name = "Listen 2 Audio Service",
  5065. .cpu_dai_name = "LSM2",
  5066. .platform_name = "msm-lsm-client",
  5067. .dynamic = 1,
  5068. .dpcm_capture = 1,
  5069. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5070. SND_SOC_DPCM_TRIGGER_POST },
  5071. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5072. .ignore_suspend = 1,
  5073. .codec_dai_name = "snd-soc-dummy-dai",
  5074. .codec_name = "snd-soc-dummy",
  5075. .id = MSM_FRONTEND_DAI_LSM2,
  5076. },
  5077. {/* hw:x,17 */
  5078. .name = "Listen 3 Audio Service",
  5079. .stream_name = "Listen 3 Audio Service",
  5080. .cpu_dai_name = "LSM3",
  5081. .platform_name = "msm-lsm-client",
  5082. .dynamic = 1,
  5083. .dpcm_capture = 1,
  5084. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5085. SND_SOC_DPCM_TRIGGER_POST },
  5086. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5087. .ignore_suspend = 1,
  5088. .codec_dai_name = "snd-soc-dummy-dai",
  5089. .codec_name = "snd-soc-dummy",
  5090. .id = MSM_FRONTEND_DAI_LSM3,
  5091. },
  5092. {/* hw:x,18 */
  5093. .name = "Listen 4 Audio Service",
  5094. .stream_name = "Listen 4 Audio Service",
  5095. .cpu_dai_name = "LSM4",
  5096. .platform_name = "msm-lsm-client",
  5097. .dynamic = 1,
  5098. .dpcm_capture = 1,
  5099. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5100. SND_SOC_DPCM_TRIGGER_POST },
  5101. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5102. .ignore_suspend = 1,
  5103. .codec_dai_name = "snd-soc-dummy-dai",
  5104. .codec_name = "snd-soc-dummy",
  5105. .id = MSM_FRONTEND_DAI_LSM4,
  5106. },
  5107. {/* hw:x,19 */
  5108. .name = "Listen 5 Audio Service",
  5109. .stream_name = "Listen 5 Audio Service",
  5110. .cpu_dai_name = "LSM5",
  5111. .platform_name = "msm-lsm-client",
  5112. .dynamic = 1,
  5113. .dpcm_capture = 1,
  5114. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5115. SND_SOC_DPCM_TRIGGER_POST },
  5116. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5117. .ignore_suspend = 1,
  5118. .codec_dai_name = "snd-soc-dummy-dai",
  5119. .codec_name = "snd-soc-dummy",
  5120. .id = MSM_FRONTEND_DAI_LSM5,
  5121. },
  5122. {/* hw:x,20 */
  5123. .name = "Listen 6 Audio Service",
  5124. .stream_name = "Listen 6 Audio Service",
  5125. .cpu_dai_name = "LSM6",
  5126. .platform_name = "msm-lsm-client",
  5127. .dynamic = 1,
  5128. .dpcm_capture = 1,
  5129. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5130. SND_SOC_DPCM_TRIGGER_POST },
  5131. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5132. .ignore_suspend = 1,
  5133. .codec_dai_name = "snd-soc-dummy-dai",
  5134. .codec_name = "snd-soc-dummy",
  5135. .id = MSM_FRONTEND_DAI_LSM6,
  5136. },
  5137. {/* hw:x,21 */
  5138. .name = "Listen 7 Audio Service",
  5139. .stream_name = "Listen 7 Audio Service",
  5140. .cpu_dai_name = "LSM7",
  5141. .platform_name = "msm-lsm-client",
  5142. .dynamic = 1,
  5143. .dpcm_capture = 1,
  5144. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5145. SND_SOC_DPCM_TRIGGER_POST },
  5146. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5147. .ignore_suspend = 1,
  5148. .codec_dai_name = "snd-soc-dummy-dai",
  5149. .codec_name = "snd-soc-dummy",
  5150. .id = MSM_FRONTEND_DAI_LSM7,
  5151. },
  5152. {/* hw:x,22 */
  5153. .name = "Listen 8 Audio Service",
  5154. .stream_name = "Listen 8 Audio Service",
  5155. .cpu_dai_name = "LSM8",
  5156. .platform_name = "msm-lsm-client",
  5157. .dynamic = 1,
  5158. .dpcm_capture = 1,
  5159. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5160. SND_SOC_DPCM_TRIGGER_POST },
  5161. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5162. .ignore_suspend = 1,
  5163. .codec_dai_name = "snd-soc-dummy-dai",
  5164. .codec_name = "snd-soc-dummy",
  5165. .id = MSM_FRONTEND_DAI_LSM8,
  5166. },
  5167. {/* hw:x,23 */
  5168. .name = MSM_DAILINK_NAME(Media9),
  5169. .stream_name = "MultiMedia9",
  5170. .cpu_dai_name = "MultiMedia9",
  5171. .platform_name = "msm-pcm-dsp.0",
  5172. .dynamic = 1,
  5173. .dpcm_playback = 1,
  5174. .dpcm_capture = 1,
  5175. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5176. SND_SOC_DPCM_TRIGGER_POST},
  5177. .codec_dai_name = "snd-soc-dummy-dai",
  5178. .codec_name = "snd-soc-dummy",
  5179. .ignore_suspend = 1,
  5180. /* this dainlink has playback support */
  5181. .ignore_pmdown_time = 1,
  5182. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  5183. },
  5184. {/* hw:x,24 */
  5185. .name = MSM_DAILINK_NAME(Compress4),
  5186. .stream_name = "Compress4",
  5187. .cpu_dai_name = "MultiMedia11",
  5188. .platform_name = "msm-compress-dsp",
  5189. .dynamic = 1,
  5190. .dpcm_playback = 1,
  5191. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5192. SND_SOC_DPCM_TRIGGER_POST},
  5193. .codec_dai_name = "snd-soc-dummy-dai",
  5194. .codec_name = "snd-soc-dummy",
  5195. .ignore_suspend = 1,
  5196. .ignore_pmdown_time = 1,
  5197. /* this dainlink has playback support */
  5198. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5199. },
  5200. {/* hw:x,25 */
  5201. .name = MSM_DAILINK_NAME(Compress5),
  5202. .stream_name = "Compress5",
  5203. .cpu_dai_name = "MultiMedia12",
  5204. .platform_name = "msm-compress-dsp",
  5205. .dynamic = 1,
  5206. .dpcm_playback = 1,
  5207. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5208. SND_SOC_DPCM_TRIGGER_POST},
  5209. .codec_dai_name = "snd-soc-dummy-dai",
  5210. .codec_name = "snd-soc-dummy",
  5211. .ignore_suspend = 1,
  5212. .ignore_pmdown_time = 1,
  5213. /* this dainlink has playback support */
  5214. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5215. },
  5216. {/* hw:x,26 */
  5217. .name = MSM_DAILINK_NAME(Compress6),
  5218. .stream_name = "Compress6",
  5219. .cpu_dai_name = "MultiMedia13",
  5220. .platform_name = "msm-compress-dsp",
  5221. .dynamic = 1,
  5222. .dpcm_playback = 1,
  5223. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5224. SND_SOC_DPCM_TRIGGER_POST},
  5225. .codec_dai_name = "snd-soc-dummy-dai",
  5226. .codec_name = "snd-soc-dummy",
  5227. .ignore_suspend = 1,
  5228. .ignore_pmdown_time = 1,
  5229. /* this dainlink has playback support */
  5230. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5231. },
  5232. {/* hw:x,27 */
  5233. .name = MSM_DAILINK_NAME(Compress7),
  5234. .stream_name = "Compress7",
  5235. .cpu_dai_name = "MultiMedia14",
  5236. .platform_name = "msm-compress-dsp",
  5237. .dynamic = 1,
  5238. .dpcm_playback = 1,
  5239. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5240. SND_SOC_DPCM_TRIGGER_POST},
  5241. .codec_dai_name = "snd-soc-dummy-dai",
  5242. .codec_name = "snd-soc-dummy",
  5243. .ignore_suspend = 1,
  5244. .ignore_pmdown_time = 1,
  5245. /* this dainlink has playback support */
  5246. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5247. },
  5248. {/* hw:x,28 */
  5249. .name = MSM_DAILINK_NAME(Compress8),
  5250. .stream_name = "Compress8",
  5251. .cpu_dai_name = "MultiMedia15",
  5252. .platform_name = "msm-compress-dsp",
  5253. .dynamic = 1,
  5254. .dpcm_playback = 1,
  5255. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5256. SND_SOC_DPCM_TRIGGER_POST},
  5257. .codec_dai_name = "snd-soc-dummy-dai",
  5258. .codec_name = "snd-soc-dummy",
  5259. .ignore_suspend = 1,
  5260. .ignore_pmdown_time = 1,
  5261. /* this dainlink has playback support */
  5262. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5263. },
  5264. {/* hw:x,29 */
  5265. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5266. .stream_name = "MM_NOIRQ_2",
  5267. .cpu_dai_name = "MultiMedia16",
  5268. .platform_name = "msm-pcm-dsp-noirq",
  5269. .dynamic = 1,
  5270. .dpcm_playback = 1,
  5271. .dpcm_capture = 1,
  5272. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5273. SND_SOC_DPCM_TRIGGER_POST},
  5274. .codec_dai_name = "snd-soc-dummy-dai",
  5275. .codec_name = "snd-soc-dummy",
  5276. .ignore_suspend = 1,
  5277. .ignore_pmdown_time = 1,
  5278. /* this dainlink has playback support */
  5279. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5280. .ops = &msm_fe_qos_ops,
  5281. },
  5282. {/* hw:x,30 */
  5283. .name = "CDC_DMA Hostless",
  5284. .stream_name = "CDC_DMA Hostless",
  5285. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5286. .platform_name = "msm-pcm-hostless",
  5287. .dynamic = 1,
  5288. .dpcm_playback = 1,
  5289. .dpcm_capture = 1,
  5290. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5291. SND_SOC_DPCM_TRIGGER_POST},
  5292. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5293. .ignore_suspend = 1,
  5294. /* this dailink has playback support */
  5295. .ignore_pmdown_time = 1,
  5296. .codec_dai_name = "snd-soc-dummy-dai",
  5297. .codec_name = "snd-soc-dummy",
  5298. },
  5299. {/* hw:x,31 */
  5300. .name = "TX3_CDC_DMA Hostless",
  5301. .stream_name = "TX3_CDC_DMA Hostless",
  5302. .cpu_dai_name = "TX3_CDC_DMA_HOSTLESS",
  5303. .platform_name = "msm-pcm-hostless",
  5304. .dynamic = 1,
  5305. .dpcm_capture = 1,
  5306. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5307. SND_SOC_DPCM_TRIGGER_POST},
  5308. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5309. .ignore_suspend = 1,
  5310. .codec_dai_name = "snd-soc-dummy-dai",
  5311. .codec_name = "snd-soc-dummy",
  5312. },
  5313. {/* hw:x,32 */
  5314. .name = "Tertiary MI2S TX_Hostless",
  5315. .stream_name = "Tertiary MI2S_TX Hostless Capture",
  5316. .cpu_dai_name = "TERT_MI2S_TX_HOSTLESS",
  5317. .platform_name = "msm-pcm-hostless",
  5318. .dynamic = 1,
  5319. .dpcm_capture = 1,
  5320. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5321. SND_SOC_DPCM_TRIGGER_POST},
  5322. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5323. .ignore_suspend = 1,
  5324. .ignore_pmdown_time = 1,
  5325. .codec_dai_name = "snd-soc-dummy-dai",
  5326. .codec_name = "snd-soc-dummy",
  5327. },
  5328. };
  5329. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5330. {/* hw:x,33 */
  5331. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5332. .stream_name = "WSA CDC DMA0 Capture",
  5333. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  5334. .platform_name = "msm-pcm-hostless",
  5335. .codec_name = "bolero_codec",
  5336. .codec_dai_name = "wsa_macro_vifeedback",
  5337. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5338. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5339. .ignore_suspend = 1,
  5340. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5341. .ops = &msm_cdc_dma_be_ops,
  5342. },
  5343. };
  5344. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5345. {/* hw:x,34 */
  5346. .name = MSM_DAILINK_NAME(ASM Loopback),
  5347. .stream_name = "MultiMedia6",
  5348. .cpu_dai_name = "MultiMedia6",
  5349. .platform_name = "msm-pcm-loopback",
  5350. .dynamic = 1,
  5351. .dpcm_playback = 1,
  5352. .dpcm_capture = 1,
  5353. .codec_dai_name = "snd-soc-dummy-dai",
  5354. .codec_name = "snd-soc-dummy",
  5355. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5356. SND_SOC_DPCM_TRIGGER_POST},
  5357. .ignore_suspend = 1,
  5358. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5359. .ignore_pmdown_time = 1,
  5360. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5361. },
  5362. {/* hw:x,35 */
  5363. .name = "USB Audio Hostless",
  5364. .stream_name = "USB Audio Hostless",
  5365. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5366. .platform_name = "msm-pcm-hostless",
  5367. .dynamic = 1,
  5368. .dpcm_playback = 1,
  5369. .dpcm_capture = 1,
  5370. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5371. SND_SOC_DPCM_TRIGGER_POST},
  5372. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5373. .ignore_suspend = 1,
  5374. .ignore_pmdown_time = 1,
  5375. .codec_dai_name = "snd-soc-dummy-dai",
  5376. .codec_name = "snd-soc-dummy",
  5377. },
  5378. {/* hw:x,36 */
  5379. .name = "SLIMBUS_7 Hostless",
  5380. .stream_name = "SLIMBUS_7 Hostless",
  5381. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5382. .platform_name = "msm-pcm-hostless",
  5383. .dynamic = 1,
  5384. .dpcm_capture = 1,
  5385. .dpcm_playback = 1,
  5386. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5387. SND_SOC_DPCM_TRIGGER_POST},
  5388. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5389. .ignore_suspend = 1,
  5390. .ignore_pmdown_time = 1,
  5391. .codec_dai_name = "snd-soc-dummy-dai",
  5392. .codec_name = "snd-soc-dummy",
  5393. },
  5394. {/* hw:x,37 */
  5395. .name = "Compress Capture",
  5396. .stream_name = "Compress9",
  5397. .cpu_dai_name = "MultiMedia17",
  5398. .platform_name = "msm-compress-dsp",
  5399. .dynamic = 1,
  5400. .dpcm_capture = 1,
  5401. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5402. SND_SOC_DPCM_TRIGGER_POST},
  5403. .codec_dai_name = "snd-soc-dummy-dai",
  5404. .codec_name = "snd-soc-dummy",
  5405. .ignore_suspend = 1,
  5406. .ignore_pmdown_time = 1,
  5407. .id = MSM_FRONTEND_DAI_MULTIMEDIA17,
  5408. },
  5409. {/* hw:x,38 */
  5410. .name = "SLIMBUS_8 Hostless",
  5411. .stream_name = "SLIMBUS_8 Hostless",
  5412. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5413. .platform_name = "msm-pcm-hostless",
  5414. .dynamic = 1,
  5415. .dpcm_capture = 1,
  5416. .dpcm_playback = 1,
  5417. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5418. SND_SOC_DPCM_TRIGGER_POST},
  5419. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5420. .ignore_suspend = 1,
  5421. .ignore_pmdown_time = 1,
  5422. .codec_dai_name = "snd-soc-dummy-dai",
  5423. .codec_name = "snd-soc-dummy",
  5424. },
  5425. {/* hw:x,39 */
  5426. .name = LPASS_BE_TX_CDC_DMA_TX_5,
  5427. .stream_name = "TX CDC DMA5 Capture",
  5428. .cpu_dai_name = "msm-dai-cdc-dma-dev.45115",
  5429. .platform_name = "msm-pcm-hostless",
  5430. .codec_name = "bolero_codec",
  5431. .codec_dai_name = "tx_macro_tx3",
  5432. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_5,
  5433. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5434. .ignore_suspend = 1,
  5435. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5436. .ops = &msm_cdc_dma_be_ops,
  5437. },
  5438. };
  5439. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5440. /* Backend AFE DAI Links */
  5441. {
  5442. .name = LPASS_BE_AFE_PCM_RX,
  5443. .stream_name = "AFE Playback",
  5444. .cpu_dai_name = "msm-dai-q6-dev.224",
  5445. .platform_name = "msm-pcm-routing",
  5446. .codec_name = "msm-stub-codec.1",
  5447. .codec_dai_name = "msm-stub-rx",
  5448. .no_pcm = 1,
  5449. .dpcm_playback = 1,
  5450. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5451. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5452. /* this dainlink has playback support */
  5453. .ignore_pmdown_time = 1,
  5454. .ignore_suspend = 1,
  5455. },
  5456. {
  5457. .name = LPASS_BE_AFE_PCM_TX,
  5458. .stream_name = "AFE Capture",
  5459. .cpu_dai_name = "msm-dai-q6-dev.225",
  5460. .platform_name = "msm-pcm-routing",
  5461. .codec_name = "msm-stub-codec.1",
  5462. .codec_dai_name = "msm-stub-tx",
  5463. .no_pcm = 1,
  5464. .dpcm_capture = 1,
  5465. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5466. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5467. .ignore_suspend = 1,
  5468. },
  5469. /* Incall Record Uplink BACK END DAI Link */
  5470. {
  5471. .name = LPASS_BE_INCALL_RECORD_TX,
  5472. .stream_name = "Voice Uplink Capture",
  5473. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5474. .platform_name = "msm-pcm-routing",
  5475. .codec_name = "msm-stub-codec.1",
  5476. .codec_dai_name = "msm-stub-tx",
  5477. .no_pcm = 1,
  5478. .dpcm_capture = 1,
  5479. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5480. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5481. .ignore_suspend = 1,
  5482. },
  5483. /* Incall Record Downlink BACK END DAI Link */
  5484. {
  5485. .name = LPASS_BE_INCALL_RECORD_RX,
  5486. .stream_name = "Voice Downlink Capture",
  5487. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5488. .platform_name = "msm-pcm-routing",
  5489. .codec_name = "msm-stub-codec.1",
  5490. .codec_dai_name = "msm-stub-tx",
  5491. .no_pcm = 1,
  5492. .dpcm_capture = 1,
  5493. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5494. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5495. .ignore_suspend = 1,
  5496. },
  5497. /* Incall Music BACK END DAI Link */
  5498. {
  5499. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5500. .stream_name = "Voice Farend Playback",
  5501. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5502. .platform_name = "msm-pcm-routing",
  5503. .codec_name = "msm-stub-codec.1",
  5504. .codec_dai_name = "msm-stub-rx",
  5505. .no_pcm = 1,
  5506. .dpcm_playback = 1,
  5507. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5508. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5509. .ignore_suspend = 1,
  5510. .ignore_pmdown_time = 1,
  5511. },
  5512. /* Incall Music 2 BACK END DAI Link */
  5513. {
  5514. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5515. .stream_name = "Voice2 Farend Playback",
  5516. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5517. .platform_name = "msm-pcm-routing",
  5518. .codec_name = "msm-stub-codec.1",
  5519. .codec_dai_name = "msm-stub-rx",
  5520. .no_pcm = 1,
  5521. .dpcm_playback = 1,
  5522. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5523. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5524. .ignore_suspend = 1,
  5525. .ignore_pmdown_time = 1,
  5526. },
  5527. {
  5528. .name = LPASS_BE_USB_AUDIO_RX,
  5529. .stream_name = "USB Audio Playback",
  5530. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5531. .platform_name = "msm-pcm-routing",
  5532. .codec_name = "msm-stub-codec.1",
  5533. .codec_dai_name = "msm-stub-rx",
  5534. .dynamic_be = 1,
  5535. .no_pcm = 1,
  5536. .dpcm_playback = 1,
  5537. .id = MSM_BACKEND_DAI_USB_RX,
  5538. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5539. .ignore_pmdown_time = 1,
  5540. .ignore_suspend = 1,
  5541. },
  5542. {
  5543. .name = LPASS_BE_USB_AUDIO_TX,
  5544. .stream_name = "USB Audio Capture",
  5545. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5546. .platform_name = "msm-pcm-routing",
  5547. .codec_name = "msm-stub-codec.1",
  5548. .codec_dai_name = "msm-stub-tx",
  5549. .no_pcm = 1,
  5550. .dpcm_capture = 1,
  5551. .id = MSM_BACKEND_DAI_USB_TX,
  5552. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5553. .ignore_suspend = 1,
  5554. },
  5555. {
  5556. .name = LPASS_BE_PRI_TDM_RX_0,
  5557. .stream_name = "Primary TDM0 Playback",
  5558. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5559. .platform_name = "msm-pcm-routing",
  5560. .codec_name = "msm-stub-codec.1",
  5561. .codec_dai_name = "msm-stub-rx",
  5562. .no_pcm = 1,
  5563. .dpcm_playback = 1,
  5564. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5565. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5566. .ops = &kona_tdm_be_ops,
  5567. .ignore_suspend = 1,
  5568. .ignore_pmdown_time = 1,
  5569. },
  5570. {
  5571. .name = LPASS_BE_PRI_TDM_TX_0,
  5572. .stream_name = "Primary TDM0 Capture",
  5573. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5574. .platform_name = "msm-pcm-routing",
  5575. .codec_name = "msm-stub-codec.1",
  5576. .codec_dai_name = "msm-stub-tx",
  5577. .no_pcm = 1,
  5578. .dpcm_capture = 1,
  5579. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5580. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5581. .ops = &kona_tdm_be_ops,
  5582. .ignore_suspend = 1,
  5583. },
  5584. {
  5585. .name = LPASS_BE_SEC_TDM_RX_0,
  5586. .stream_name = "Secondary TDM0 Playback",
  5587. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5588. .platform_name = "msm-pcm-routing",
  5589. .codec_name = "msm-stub-codec.1",
  5590. .codec_dai_name = "msm-stub-rx",
  5591. .no_pcm = 1,
  5592. .dpcm_playback = 1,
  5593. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5594. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5595. .ops = &kona_tdm_be_ops,
  5596. .ignore_suspend = 1,
  5597. .ignore_pmdown_time = 1,
  5598. },
  5599. {
  5600. .name = LPASS_BE_SEC_TDM_TX_0,
  5601. .stream_name = "Secondary TDM0 Capture",
  5602. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5603. .platform_name = "msm-pcm-routing",
  5604. .codec_name = "msm-stub-codec.1",
  5605. .codec_dai_name = "msm-stub-tx",
  5606. .no_pcm = 1,
  5607. .dpcm_capture = 1,
  5608. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5609. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5610. .ops = &kona_tdm_be_ops,
  5611. .ignore_suspend = 1,
  5612. },
  5613. {
  5614. .name = LPASS_BE_TERT_TDM_RX_0,
  5615. .stream_name = "Tertiary TDM0 Playback",
  5616. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5617. .platform_name = "msm-pcm-routing",
  5618. .codec_name = "msm-stub-codec.1",
  5619. .codec_dai_name = "msm-stub-rx",
  5620. .no_pcm = 1,
  5621. .dpcm_playback = 1,
  5622. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5623. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5624. .ops = &kona_tdm_be_ops,
  5625. .ignore_suspend = 1,
  5626. .ignore_pmdown_time = 1,
  5627. },
  5628. {
  5629. .name = LPASS_BE_TERT_TDM_TX_0,
  5630. .stream_name = "Tertiary TDM0 Capture",
  5631. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5632. .platform_name = "msm-pcm-routing",
  5633. .codec_name = "msm-stub-codec.1",
  5634. .codec_dai_name = "msm-stub-tx",
  5635. .no_pcm = 1,
  5636. .dpcm_capture = 1,
  5637. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5638. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5639. .ops = &kona_tdm_be_ops,
  5640. .ignore_suspend = 1,
  5641. },
  5642. {
  5643. .name = LPASS_BE_QUAT_TDM_RX_0,
  5644. .stream_name = "Quaternary TDM0 Playback",
  5645. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5646. .platform_name = "msm-pcm-routing",
  5647. .codec_name = "msm-stub-codec.1",
  5648. .codec_dai_name = "msm-stub-rx",
  5649. .no_pcm = 1,
  5650. .dpcm_playback = 1,
  5651. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5652. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5653. .ops = &kona_tdm_be_ops,
  5654. .ignore_suspend = 1,
  5655. .ignore_pmdown_time = 1,
  5656. },
  5657. {
  5658. .name = LPASS_BE_QUAT_TDM_TX_0,
  5659. .stream_name = "Quaternary TDM0 Capture",
  5660. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5661. .platform_name = "msm-pcm-routing",
  5662. .codec_name = "msm-stub-codec.1",
  5663. .codec_dai_name = "msm-stub-tx",
  5664. .no_pcm = 1,
  5665. .dpcm_capture = 1,
  5666. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5667. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5668. .ops = &kona_tdm_be_ops,
  5669. .ignore_suspend = 1,
  5670. },
  5671. {
  5672. .name = LPASS_BE_QUIN_TDM_RX_0,
  5673. .stream_name = "Quinary TDM0 Playback",
  5674. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  5675. .platform_name = "msm-pcm-routing",
  5676. .codec_name = "msm-stub-codec.1",
  5677. .codec_dai_name = "msm-stub-rx",
  5678. .no_pcm = 1,
  5679. .dpcm_playback = 1,
  5680. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  5681. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5682. .ops = &kona_tdm_be_ops,
  5683. .ignore_suspend = 1,
  5684. .ignore_pmdown_time = 1,
  5685. },
  5686. {
  5687. .name = LPASS_BE_QUIN_TDM_TX_0,
  5688. .stream_name = "Quinary TDM0 Capture",
  5689. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  5690. .platform_name = "msm-pcm-routing",
  5691. .codec_name = "msm-stub-codec.1",
  5692. .codec_dai_name = "msm-stub-tx",
  5693. .no_pcm = 1,
  5694. .dpcm_capture = 1,
  5695. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  5696. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5697. .ops = &kona_tdm_be_ops,
  5698. .ignore_suspend = 1,
  5699. },
  5700. {
  5701. .name = LPASS_BE_SEN_TDM_RX_0,
  5702. .stream_name = "Senary TDM0 Playback",
  5703. .cpu_dai_name = "msm-dai-q6-tdm.36944",
  5704. .platform_name = "msm-pcm-routing",
  5705. .codec_name = "msm-stub-codec.1",
  5706. .codec_dai_name = "msm-stub-rx",
  5707. .no_pcm = 1,
  5708. .dpcm_playback = 1,
  5709. .id = MSM_BACKEND_DAI_SEN_TDM_RX_0,
  5710. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5711. .ops = &kona_tdm_be_ops,
  5712. .ignore_suspend = 1,
  5713. .ignore_pmdown_time = 1,
  5714. },
  5715. {
  5716. .name = LPASS_BE_SEN_TDM_TX_0,
  5717. .stream_name = "Senary TDM0 Capture",
  5718. .cpu_dai_name = "msm-dai-q6-tdm.36945",
  5719. .platform_name = "msm-pcm-routing",
  5720. .codec_name = "msm-stub-codec.1",
  5721. .codec_dai_name = "msm-stub-tx",
  5722. .no_pcm = 1,
  5723. .dpcm_capture = 1,
  5724. .id = MSM_BACKEND_DAI_SEN_TDM_TX_0,
  5725. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5726. .ops = &kona_tdm_be_ops,
  5727. .ignore_suspend = 1,
  5728. },
  5729. };
  5730. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  5731. {
  5732. .name = LPASS_BE_SLIMBUS_7_RX,
  5733. .stream_name = "Slimbus7 Playback",
  5734. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5735. .platform_name = "msm-pcm-routing",
  5736. .codec_name = "btfmslim_slave",
  5737. /* BT codec driver determines capabilities based on
  5738. * dai name, bt codecdai name should always contains
  5739. * supported usecase information
  5740. */
  5741. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5742. .no_pcm = 1,
  5743. .dpcm_playback = 1,
  5744. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5745. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5746. .init = &msm_wcn_init,
  5747. .ops = &msm_wcn_ops,
  5748. /* dai link has playback support */
  5749. .ignore_pmdown_time = 1,
  5750. .ignore_suspend = 1,
  5751. },
  5752. {
  5753. .name = LPASS_BE_SLIMBUS_7_TX,
  5754. .stream_name = "Slimbus7 Capture",
  5755. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5756. .platform_name = "msm-pcm-routing",
  5757. .codec_name = "btfmslim_slave",
  5758. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5759. .no_pcm = 1,
  5760. .dpcm_capture = 1,
  5761. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5762. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5763. .ops = &msm_wcn_ops,
  5764. .ignore_suspend = 1,
  5765. },
  5766. };
  5767. static struct snd_soc_dai_link msm_wcn_btfm_be_dai_links[] = {
  5768. {
  5769. .name = LPASS_BE_SLIMBUS_7_RX,
  5770. .stream_name = "Slimbus7 Playback",
  5771. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5772. .platform_name = "msm-pcm-routing",
  5773. .codec_name = "btfmslim_slave",
  5774. /* BT codec driver determines capabilities based on
  5775. * dai name, bt codecdai name should always contains
  5776. * supported usecase information
  5777. */
  5778. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5779. .no_pcm = 1,
  5780. .dpcm_playback = 1,
  5781. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5782. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5783. .init = &msm_wcn_init_lito,
  5784. .ops = &msm_wcn_ops_lito,
  5785. /* dai link has playback support */
  5786. .ignore_pmdown_time = 1,
  5787. .ignore_suspend = 1,
  5788. },
  5789. {
  5790. .name = LPASS_BE_SLIMBUS_7_TX,
  5791. .stream_name = "Slimbus7 Capture",
  5792. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5793. .platform_name = "msm-pcm-routing",
  5794. .codec_name = "btfmslim_slave",
  5795. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5796. .no_pcm = 1,
  5797. .dpcm_capture = 1,
  5798. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5799. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5800. .ops = &msm_wcn_ops_lito,
  5801. .ignore_suspend = 1,
  5802. },
  5803. {
  5804. .name = LPASS_BE_SLIMBUS_8_TX,
  5805. .stream_name = "Slimbus8 Capture",
  5806. .cpu_dai_name = "msm-dai-q6-dev.16401",
  5807. .platform_name = "msm-pcm-routing",
  5808. .codec_name = "btfmslim_slave",
  5809. .codec_dai_name = "btfm_fm_slim_tx",
  5810. .no_pcm = 1,
  5811. .dpcm_capture = 1,
  5812. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  5813. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5814. .ops = &msm_wcn_ops_lito,
  5815. .ignore_suspend = 1,
  5816. },
  5817. };
  5818. static struct snd_soc_dai_link ext_disp_be_dai_link[] = {
  5819. /* DISP PORT BACK END DAI Link */
  5820. {
  5821. .name = LPASS_BE_DISPLAY_PORT,
  5822. .stream_name = "Display Port Playback",
  5823. .cpu_dai_name = "msm-dai-q6-dp.0",
  5824. .platform_name = "msm-pcm-routing",
  5825. .codec_name = "msm-ext-disp-audio-codec-rx",
  5826. .codec_dai_name = "msm_dp_audio_codec_rx_dai",
  5827. .no_pcm = 1,
  5828. .dpcm_playback = 1,
  5829. .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX,
  5830. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5831. .ignore_pmdown_time = 1,
  5832. .ignore_suspend = 1,
  5833. },
  5834. /* DISP PORT 1 BACK END DAI Link */
  5835. {
  5836. .name = LPASS_BE_DISPLAY_PORT1,
  5837. .stream_name = "Display Port1 Playback",
  5838. .cpu_dai_name = "msm-dai-q6-dp.1",
  5839. .platform_name = "msm-pcm-routing",
  5840. .codec_name = "msm-ext-disp-audio-codec-rx",
  5841. .codec_dai_name = "msm_dp_audio_codec_rx1_dai",
  5842. .no_pcm = 1,
  5843. .dpcm_playback = 1,
  5844. .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX_1,
  5845. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5846. .ignore_pmdown_time = 1,
  5847. .ignore_suspend = 1,
  5848. },
  5849. };
  5850. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  5851. {
  5852. .name = LPASS_BE_PRI_MI2S_RX,
  5853. .stream_name = "Primary MI2S Playback",
  5854. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5855. .platform_name = "msm-pcm-routing",
  5856. .codec_name = "msm-stub-codec.1",
  5857. .codec_dai_name = "msm-stub-rx",
  5858. .no_pcm = 1,
  5859. .dpcm_playback = 1,
  5860. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  5861. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5862. .ops = &msm_mi2s_be_ops,
  5863. .ignore_suspend = 1,
  5864. .ignore_pmdown_time = 1,
  5865. },
  5866. {
  5867. .name = LPASS_BE_PRI_MI2S_TX,
  5868. .stream_name = "Primary MI2S Capture",
  5869. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5870. .platform_name = "msm-pcm-routing",
  5871. .codec_name = "msm-stub-codec.1",
  5872. .codec_dai_name = "msm-stub-tx",
  5873. .no_pcm = 1,
  5874. .dpcm_capture = 1,
  5875. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  5876. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5877. .ops = &msm_mi2s_be_ops,
  5878. .ignore_suspend = 1,
  5879. },
  5880. {
  5881. .name = LPASS_BE_SEC_MI2S_RX,
  5882. .stream_name = "Secondary MI2S Playback",
  5883. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5884. .platform_name = "msm-pcm-routing",
  5885. .codec_name = "msm-stub-codec.1",
  5886. .codec_dai_name = "msm-stub-rx",
  5887. .no_pcm = 1,
  5888. .dpcm_playback = 1,
  5889. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  5890. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5891. .ops = &msm_mi2s_be_ops,
  5892. .ignore_suspend = 1,
  5893. .ignore_pmdown_time = 1,
  5894. },
  5895. {
  5896. .name = LPASS_BE_SEC_MI2S_TX,
  5897. .stream_name = "Secondary MI2S Capture",
  5898. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5899. .platform_name = "msm-pcm-routing",
  5900. .codec_name = "msm-stub-codec.1",
  5901. .codec_dai_name = "msm-stub-tx",
  5902. .no_pcm = 1,
  5903. .dpcm_capture = 1,
  5904. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  5905. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5906. .ops = &msm_mi2s_be_ops,
  5907. .ignore_suspend = 1,
  5908. },
  5909. {
  5910. .name = LPASS_BE_TERT_MI2S_RX,
  5911. .stream_name = "Tertiary MI2S Playback",
  5912. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5913. .platform_name = "msm-pcm-routing",
  5914. .codec_name = "msm-stub-codec.1",
  5915. .codec_dai_name = "msm-stub-rx",
  5916. .no_pcm = 1,
  5917. .dpcm_playback = 1,
  5918. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  5919. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5920. .ops = &msm_mi2s_be_ops,
  5921. .ignore_suspend = 1,
  5922. .ignore_pmdown_time = 1,
  5923. },
  5924. {
  5925. .name = LPASS_BE_TERT_MI2S_TX,
  5926. .stream_name = "Tertiary MI2S Capture",
  5927. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5928. .platform_name = "msm-pcm-routing",
  5929. .codec_name = "msm-stub-codec.1",
  5930. .codec_dai_name = "msm-stub-tx",
  5931. .no_pcm = 1,
  5932. .dpcm_capture = 1,
  5933. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  5934. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5935. .ops = &msm_mi2s_be_ops,
  5936. .ignore_suspend = 1,
  5937. },
  5938. {
  5939. .name = LPASS_BE_QUAT_MI2S_RX,
  5940. .stream_name = "Quaternary MI2S Playback",
  5941. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5942. .platform_name = "msm-pcm-routing",
  5943. .codec_name = "msm-stub-codec.1",
  5944. .codec_dai_name = "msm-stub-rx",
  5945. .no_pcm = 1,
  5946. .dpcm_playback = 1,
  5947. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  5948. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5949. .ops = &msm_mi2s_be_ops,
  5950. .ignore_suspend = 1,
  5951. .ignore_pmdown_time = 1,
  5952. },
  5953. {
  5954. .name = LPASS_BE_QUAT_MI2S_TX,
  5955. .stream_name = "Quaternary MI2S Capture",
  5956. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5957. .platform_name = "msm-pcm-routing",
  5958. .codec_name = "msm-stub-codec.1",
  5959. .codec_dai_name = "msm-stub-tx",
  5960. .no_pcm = 1,
  5961. .dpcm_capture = 1,
  5962. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  5963. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5964. .ops = &msm_mi2s_be_ops,
  5965. .ignore_suspend = 1,
  5966. },
  5967. {
  5968. .name = LPASS_BE_QUIN_MI2S_RX,
  5969. .stream_name = "Quinary MI2S Playback",
  5970. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5971. .platform_name = "msm-pcm-routing",
  5972. .codec_name = "msm-stub-codec.1",
  5973. .codec_dai_name = "msm-stub-rx",
  5974. .no_pcm = 1,
  5975. .dpcm_playback = 1,
  5976. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  5977. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5978. .ops = &msm_mi2s_be_ops,
  5979. .ignore_suspend = 1,
  5980. .ignore_pmdown_time = 1,
  5981. },
  5982. {
  5983. .name = LPASS_BE_QUIN_MI2S_TX,
  5984. .stream_name = "Quinary MI2S Capture",
  5985. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5986. .platform_name = "msm-pcm-routing",
  5987. .codec_name = "msm-stub-codec.1",
  5988. .codec_dai_name = "msm-stub-tx",
  5989. .no_pcm = 1,
  5990. .dpcm_capture = 1,
  5991. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  5992. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5993. .ops = &msm_mi2s_be_ops,
  5994. .ignore_suspend = 1,
  5995. },
  5996. {
  5997. .name = LPASS_BE_SENARY_MI2S_RX,
  5998. .stream_name = "Senary MI2S Playback",
  5999. .cpu_dai_name = "msm-dai-q6-mi2s.5",
  6000. .platform_name = "msm-pcm-routing",
  6001. .codec_name = "msm-stub-codec.1",
  6002. .codec_dai_name = "msm-stub-rx",
  6003. .no_pcm = 1,
  6004. .dpcm_playback = 1,
  6005. .id = MSM_BACKEND_DAI_SENARY_MI2S_RX,
  6006. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6007. .ops = &msm_mi2s_be_ops,
  6008. .ignore_suspend = 1,
  6009. .ignore_pmdown_time = 1,
  6010. },
  6011. {
  6012. .name = LPASS_BE_SENARY_MI2S_TX,
  6013. .stream_name = "Senary MI2S Capture",
  6014. .cpu_dai_name = "msm-dai-q6-mi2s.5",
  6015. .platform_name = "msm-pcm-routing",
  6016. .codec_name = "msm-stub-codec.1",
  6017. .codec_dai_name = "msm-stub-tx",
  6018. .no_pcm = 1,
  6019. .dpcm_capture = 1,
  6020. .id = MSM_BACKEND_DAI_SENARY_MI2S_TX,
  6021. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6022. .ops = &msm_mi2s_be_ops,
  6023. .ignore_suspend = 1,
  6024. },
  6025. };
  6026. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  6027. /* Primary AUX PCM Backend DAI Links */
  6028. {
  6029. .name = LPASS_BE_AUXPCM_RX,
  6030. .stream_name = "AUX PCM Playback",
  6031. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6032. .platform_name = "msm-pcm-routing",
  6033. .codec_name = "msm-stub-codec.1",
  6034. .codec_dai_name = "msm-stub-rx",
  6035. .no_pcm = 1,
  6036. .dpcm_playback = 1,
  6037. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6038. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6039. .ops = &kona_aux_be_ops,
  6040. .ignore_pmdown_time = 1,
  6041. .ignore_suspend = 1,
  6042. },
  6043. {
  6044. .name = LPASS_BE_AUXPCM_TX,
  6045. .stream_name = "AUX PCM Capture",
  6046. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6047. .platform_name = "msm-pcm-routing",
  6048. .codec_name = "msm-stub-codec.1",
  6049. .codec_dai_name = "msm-stub-tx",
  6050. .no_pcm = 1,
  6051. .dpcm_capture = 1,
  6052. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6053. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6054. .ops = &kona_aux_be_ops,
  6055. .ignore_suspend = 1,
  6056. },
  6057. /* Secondary AUX PCM Backend DAI Links */
  6058. {
  6059. .name = LPASS_BE_SEC_AUXPCM_RX,
  6060. .stream_name = "Sec AUX PCM Playback",
  6061. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6062. .platform_name = "msm-pcm-routing",
  6063. .codec_name = "msm-stub-codec.1",
  6064. .codec_dai_name = "msm-stub-rx",
  6065. .no_pcm = 1,
  6066. .dpcm_playback = 1,
  6067. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  6068. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6069. .ops = &kona_aux_be_ops,
  6070. .ignore_pmdown_time = 1,
  6071. .ignore_suspend = 1,
  6072. },
  6073. {
  6074. .name = LPASS_BE_SEC_AUXPCM_TX,
  6075. .stream_name = "Sec AUX PCM Capture",
  6076. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6077. .platform_name = "msm-pcm-routing",
  6078. .codec_name = "msm-stub-codec.1",
  6079. .codec_dai_name = "msm-stub-tx",
  6080. .no_pcm = 1,
  6081. .dpcm_capture = 1,
  6082. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  6083. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6084. .ops = &kona_aux_be_ops,
  6085. .ignore_suspend = 1,
  6086. },
  6087. /* Tertiary AUX PCM Backend DAI Links */
  6088. {
  6089. .name = LPASS_BE_TERT_AUXPCM_RX,
  6090. .stream_name = "Tert AUX PCM Playback",
  6091. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6092. .platform_name = "msm-pcm-routing",
  6093. .codec_name = "msm-stub-codec.1",
  6094. .codec_dai_name = "msm-stub-rx",
  6095. .no_pcm = 1,
  6096. .dpcm_playback = 1,
  6097. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  6098. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6099. .ops = &kona_aux_be_ops,
  6100. .ignore_suspend = 1,
  6101. },
  6102. {
  6103. .name = LPASS_BE_TERT_AUXPCM_TX,
  6104. .stream_name = "Tert AUX PCM Capture",
  6105. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6106. .platform_name = "msm-pcm-routing",
  6107. .codec_name = "msm-stub-codec.1",
  6108. .codec_dai_name = "msm-stub-tx",
  6109. .no_pcm = 1,
  6110. .dpcm_capture = 1,
  6111. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  6112. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6113. .ops = &kona_aux_be_ops,
  6114. .ignore_suspend = 1,
  6115. },
  6116. /* Quaternary AUX PCM Backend DAI Links */
  6117. {
  6118. .name = LPASS_BE_QUAT_AUXPCM_RX,
  6119. .stream_name = "Quat AUX PCM Playback",
  6120. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6121. .platform_name = "msm-pcm-routing",
  6122. .codec_name = "msm-stub-codec.1",
  6123. .codec_dai_name = "msm-stub-rx",
  6124. .no_pcm = 1,
  6125. .dpcm_playback = 1,
  6126. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  6127. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6128. .ops = &kona_aux_be_ops,
  6129. .ignore_suspend = 1,
  6130. },
  6131. {
  6132. .name = LPASS_BE_QUAT_AUXPCM_TX,
  6133. .stream_name = "Quat AUX PCM Capture",
  6134. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6135. .platform_name = "msm-pcm-routing",
  6136. .codec_name = "msm-stub-codec.1",
  6137. .codec_dai_name = "msm-stub-tx",
  6138. .no_pcm = 1,
  6139. .dpcm_capture = 1,
  6140. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  6141. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6142. .ops = &kona_aux_be_ops,
  6143. .ignore_suspend = 1,
  6144. },
  6145. /* Quinary AUX PCM Backend DAI Links */
  6146. {
  6147. .name = LPASS_BE_QUIN_AUXPCM_RX,
  6148. .stream_name = "Quin AUX PCM Playback",
  6149. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6150. .platform_name = "msm-pcm-routing",
  6151. .codec_name = "msm-stub-codec.1",
  6152. .codec_dai_name = "msm-stub-rx",
  6153. .no_pcm = 1,
  6154. .dpcm_playback = 1,
  6155. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  6156. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6157. .ops = &kona_aux_be_ops,
  6158. .ignore_suspend = 1,
  6159. },
  6160. {
  6161. .name = LPASS_BE_QUIN_AUXPCM_TX,
  6162. .stream_name = "Quin AUX PCM Capture",
  6163. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6164. .platform_name = "msm-pcm-routing",
  6165. .codec_name = "msm-stub-codec.1",
  6166. .codec_dai_name = "msm-stub-tx",
  6167. .no_pcm = 1,
  6168. .dpcm_capture = 1,
  6169. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  6170. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6171. .ops = &kona_aux_be_ops,
  6172. .ignore_suspend = 1,
  6173. },
  6174. /* Senary AUX PCM Backend DAI Links */
  6175. {
  6176. .name = LPASS_BE_SEN_AUXPCM_RX,
  6177. .stream_name = "Sen AUX PCM Playback",
  6178. .cpu_dai_name = "msm-dai-q6-auxpcm.6",
  6179. .platform_name = "msm-pcm-routing",
  6180. .codec_name = "msm-stub-codec.1",
  6181. .codec_dai_name = "msm-stub-rx",
  6182. .no_pcm = 1,
  6183. .dpcm_playback = 1,
  6184. .id = MSM_BACKEND_DAI_SEN_AUXPCM_RX,
  6185. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6186. .ops = &kona_aux_be_ops,
  6187. .ignore_suspend = 1,
  6188. },
  6189. {
  6190. .name = LPASS_BE_SEN_AUXPCM_TX,
  6191. .stream_name = "Sen AUX PCM Capture",
  6192. .cpu_dai_name = "msm-dai-q6-auxpcm.6",
  6193. .platform_name = "msm-pcm-routing",
  6194. .codec_name = "msm-stub-codec.1",
  6195. .codec_dai_name = "msm-stub-tx",
  6196. .no_pcm = 1,
  6197. .dpcm_capture = 1,
  6198. .id = MSM_BACKEND_DAI_SEN_AUXPCM_TX,
  6199. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6200. .ops = &kona_aux_be_ops,
  6201. .ignore_suspend = 1,
  6202. },
  6203. };
  6204. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  6205. /* WSA CDC DMA Backend DAI Links */
  6206. {
  6207. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  6208. .stream_name = "WSA CDC DMA0 Playback",
  6209. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  6210. .platform_name = "msm-pcm-routing",
  6211. .codec_name = "bolero_codec",
  6212. .codec_dai_name = "wsa_macro_rx1",
  6213. .no_pcm = 1,
  6214. .dpcm_playback = 1,
  6215. .init = &msm_int_audrx_init,
  6216. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  6217. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6218. .ignore_pmdown_time = 1,
  6219. .ignore_suspend = 1,
  6220. .ops = &msm_cdc_dma_be_ops,
  6221. },
  6222. {
  6223. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  6224. .stream_name = "WSA CDC DMA1 Playback",
  6225. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  6226. .platform_name = "msm-pcm-routing",
  6227. .codec_name = "bolero_codec",
  6228. .codec_dai_name = "wsa_macro_rx_mix",
  6229. .no_pcm = 1,
  6230. .dpcm_playback = 1,
  6231. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  6232. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6233. .ignore_pmdown_time = 1,
  6234. .ignore_suspend = 1,
  6235. .ops = &msm_cdc_dma_be_ops,
  6236. },
  6237. {
  6238. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  6239. .stream_name = "WSA CDC DMA1 Capture",
  6240. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  6241. .platform_name = "msm-pcm-routing",
  6242. .codec_name = "bolero_codec",
  6243. .codec_dai_name = "wsa_macro_echo",
  6244. .no_pcm = 1,
  6245. .dpcm_capture = 1,
  6246. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  6247. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6248. .ignore_suspend = 1,
  6249. .ops = &msm_cdc_dma_be_ops,
  6250. },
  6251. };
  6252. static struct snd_soc_dai_link msm_rx_tx_cdc_dma_be_dai_links[] = {
  6253. /* RX CDC DMA Backend DAI Links */
  6254. {
  6255. .name = LPASS_BE_RX_CDC_DMA_RX_0,
  6256. .stream_name = "RX CDC DMA0 Playback",
  6257. .cpu_dai_name = "msm-dai-cdc-dma-dev.45104",
  6258. .platform_name = "msm-pcm-routing",
  6259. .codec_name = "bolero_codec",
  6260. .codec_dai_name = "rx_macro_rx1",
  6261. .dynamic_be = 1,
  6262. .no_pcm = 1,
  6263. .dpcm_playback = 1,
  6264. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_0,
  6265. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6266. .ignore_pmdown_time = 1,
  6267. .ignore_suspend = 1,
  6268. .ops = &msm_cdc_dma_be_ops,
  6269. },
  6270. {
  6271. .name = LPASS_BE_RX_CDC_DMA_RX_1,
  6272. .stream_name = "RX CDC DMA1 Playback",
  6273. .cpu_dai_name = "msm-dai-cdc-dma-dev.45106",
  6274. .platform_name = "msm-pcm-routing",
  6275. .codec_name = "bolero_codec",
  6276. .codec_dai_name = "rx_macro_rx2",
  6277. .dynamic_be = 1,
  6278. .no_pcm = 1,
  6279. .dpcm_playback = 1,
  6280. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_1,
  6281. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6282. .ignore_pmdown_time = 1,
  6283. .ignore_suspend = 1,
  6284. .ops = &msm_cdc_dma_be_ops,
  6285. },
  6286. {
  6287. .name = LPASS_BE_RX_CDC_DMA_RX_2,
  6288. .stream_name = "RX CDC DMA2 Playback",
  6289. .cpu_dai_name = "msm-dai-cdc-dma-dev.45108",
  6290. .platform_name = "msm-pcm-routing",
  6291. .codec_name = "bolero_codec",
  6292. .codec_dai_name = "rx_macro_rx3",
  6293. .dynamic_be = 1,
  6294. .no_pcm = 1,
  6295. .dpcm_playback = 1,
  6296. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_2,
  6297. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6298. .ignore_pmdown_time = 1,
  6299. .ignore_suspend = 1,
  6300. .ops = &msm_cdc_dma_be_ops,
  6301. },
  6302. {
  6303. .name = LPASS_BE_RX_CDC_DMA_RX_3,
  6304. .stream_name = "RX CDC DMA3 Playback",
  6305. .cpu_dai_name = "msm-dai-cdc-dma-dev.45110",
  6306. .platform_name = "msm-pcm-routing",
  6307. .codec_name = "bolero_codec",
  6308. .codec_dai_name = "rx_macro_rx4",
  6309. .dynamic_be = 1,
  6310. .no_pcm = 1,
  6311. .dpcm_playback = 1,
  6312. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_3,
  6313. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6314. .ignore_pmdown_time = 1,
  6315. .ignore_suspend = 1,
  6316. .ops = &msm_cdc_dma_be_ops,
  6317. },
  6318. /* TX CDC DMA Backend DAI Links */
  6319. {
  6320. .name = LPASS_BE_TX_CDC_DMA_TX_3,
  6321. .stream_name = "TX CDC DMA3 Capture",
  6322. .cpu_dai_name = "msm-dai-cdc-dma-dev.45111",
  6323. .platform_name = "msm-pcm-routing",
  6324. .codec_name = "bolero_codec",
  6325. .codec_dai_name = "tx_macro_tx1",
  6326. .no_pcm = 1,
  6327. .dpcm_capture = 1,
  6328. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_3,
  6329. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6330. .ignore_suspend = 1,
  6331. .ops = &msm_cdc_dma_be_ops,
  6332. },
  6333. {
  6334. .name = LPASS_BE_TX_CDC_DMA_TX_4,
  6335. .stream_name = "TX CDC DMA4 Capture",
  6336. .cpu_dai_name = "msm-dai-cdc-dma-dev.45113",
  6337. .platform_name = "msm-pcm-routing",
  6338. .codec_name = "bolero_codec",
  6339. .codec_dai_name = "tx_macro_tx2",
  6340. .no_pcm = 1,
  6341. .dpcm_capture = 1,
  6342. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_4,
  6343. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6344. .ignore_suspend = 1,
  6345. .ops = &msm_cdc_dma_be_ops,
  6346. },
  6347. };
  6348. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6349. {
  6350. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6351. .stream_name = "VA CDC DMA0 Capture",
  6352. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6353. .platform_name = "msm-pcm-routing",
  6354. .codec_name = "bolero_codec",
  6355. .codec_dai_name = "va_macro_tx1",
  6356. .no_pcm = 1,
  6357. .dpcm_capture = 1,
  6358. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6359. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6360. .ignore_suspend = 1,
  6361. .ops = &msm_cdc_dma_be_ops,
  6362. },
  6363. {
  6364. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6365. .stream_name = "VA CDC DMA1 Capture",
  6366. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6367. .platform_name = "msm-pcm-routing",
  6368. .codec_name = "bolero_codec",
  6369. .codec_dai_name = "va_macro_tx2",
  6370. .no_pcm = 1,
  6371. .dpcm_capture = 1,
  6372. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6373. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6374. .ignore_suspend = 1,
  6375. .ops = &msm_cdc_dma_be_ops,
  6376. },
  6377. {
  6378. .name = LPASS_BE_VA_CDC_DMA_TX_2,
  6379. .stream_name = "VA CDC DMA2 Capture",
  6380. .cpu_dai_name = "msm-dai-cdc-dma-dev.45093",
  6381. .platform_name = "msm-pcm-routing",
  6382. .codec_name = "bolero_codec",
  6383. .codec_dai_name = "va_macro_tx3",
  6384. .no_pcm = 1,
  6385. .dpcm_capture = 1,
  6386. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_2,
  6387. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6388. .ignore_suspend = 1,
  6389. .ops = &msm_cdc_dma_be_ops,
  6390. },
  6391. };
  6392. static struct snd_soc_dai_link msm_afe_rxtx_lb_be_dai_link[] = {
  6393. {
  6394. .name = LPASS_BE_AFE_LOOPBACK_TX,
  6395. .stream_name = "AFE Loopback Capture",
  6396. .cpu_dai_name = "msm-dai-q6-dev.24577",
  6397. .platform_name = "msm-pcm-routing",
  6398. .codec_name = "msm-stub-codec.1",
  6399. .codec_dai_name = "msm-stub-tx",
  6400. .no_pcm = 1,
  6401. .dpcm_capture = 1,
  6402. .id = MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
  6403. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6404. .ignore_pmdown_time = 1,
  6405. .ignore_suspend = 1,
  6406. },
  6407. };
  6408. static struct snd_soc_dai_link msm_kona_dai_links[
  6409. ARRAY_SIZE(msm_common_dai_links) +
  6410. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  6411. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6412. ARRAY_SIZE(msm_common_be_dai_links) +
  6413. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6414. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6415. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  6416. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links) +
  6417. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6418. ARRAY_SIZE(ext_disp_be_dai_link) +
  6419. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6420. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link) +
  6421. ARRAY_SIZE(msm_wcn_btfm_be_dai_links)];
  6422. static int msm_populate_dai_link_component_of_node(
  6423. struct snd_soc_card *card)
  6424. {
  6425. int i, index, ret = 0;
  6426. struct device *cdev = card->dev;
  6427. struct snd_soc_dai_link *dai_link = card->dai_link;
  6428. struct device_node *np;
  6429. if (!cdev) {
  6430. dev_err(cdev, "%s: Sound card device memory NULL\n", __func__);
  6431. return -ENODEV;
  6432. }
  6433. for (i = 0; i < card->num_links; i++) {
  6434. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6435. continue;
  6436. /* populate platform_of_node for snd card dai links */
  6437. if (dai_link[i].platform_name &&
  6438. !dai_link[i].platform_of_node) {
  6439. index = of_property_match_string(cdev->of_node,
  6440. "asoc-platform-names",
  6441. dai_link[i].platform_name);
  6442. if (index < 0) {
  6443. dev_err(cdev, "%s: No match found for platform name: %s\n",
  6444. __func__, dai_link[i].platform_name);
  6445. ret = index;
  6446. goto err;
  6447. }
  6448. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6449. index);
  6450. if (!np) {
  6451. dev_err(cdev, "%s: retrieving phandle for platform %s, index %d failed\n",
  6452. __func__, dai_link[i].platform_name,
  6453. index);
  6454. ret = -ENODEV;
  6455. goto err;
  6456. }
  6457. dai_link[i].platform_of_node = np;
  6458. dai_link[i].platform_name = NULL;
  6459. }
  6460. /* populate cpu_of_node for snd card dai links */
  6461. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6462. index = of_property_match_string(cdev->of_node,
  6463. "asoc-cpu-names",
  6464. dai_link[i].cpu_dai_name);
  6465. if (index >= 0) {
  6466. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6467. index);
  6468. if (!np) {
  6469. dev_err(cdev, "%s: retrieving phandle for cpu dai %s failed\n",
  6470. __func__,
  6471. dai_link[i].cpu_dai_name);
  6472. ret = -ENODEV;
  6473. goto err;
  6474. }
  6475. dai_link[i].cpu_of_node = np;
  6476. dai_link[i].cpu_dai_name = NULL;
  6477. }
  6478. }
  6479. /* populate codec_of_node for snd card dai links */
  6480. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6481. index = of_property_match_string(cdev->of_node,
  6482. "asoc-codec-names",
  6483. dai_link[i].codec_name);
  6484. if (index < 0)
  6485. continue;
  6486. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6487. index);
  6488. if (!np) {
  6489. dev_err(cdev, "%s: retrieving phandle for codec %s failed\n",
  6490. __func__, dai_link[i].codec_name);
  6491. ret = -ENODEV;
  6492. goto err;
  6493. }
  6494. dai_link[i].codec_of_node = np;
  6495. dai_link[i].codec_name = NULL;
  6496. }
  6497. }
  6498. err:
  6499. return ret;
  6500. }
  6501. static int msm_audrx_stub_init(struct snd_soc_pcm_runtime *rtd)
  6502. {
  6503. int ret = -EINVAL;
  6504. struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, "msm-stub-codec");
  6505. if (!component) {
  6506. pr_err("* %s: No match for msm-stub-codec component\n", __func__);
  6507. return ret;
  6508. }
  6509. ret = snd_soc_add_component_controls(component, msm_snd_controls,
  6510. ARRAY_SIZE(msm_snd_controls));
  6511. if (ret < 0) {
  6512. dev_err(component->dev,
  6513. "%s: add_codec_controls failed, err = %d\n",
  6514. __func__, ret);
  6515. return ret;
  6516. }
  6517. return ret;
  6518. }
  6519. static int msm_snd_stub_hw_params(struct snd_pcm_substream *substream,
  6520. struct snd_pcm_hw_params *params)
  6521. {
  6522. return 0;
  6523. }
  6524. static struct snd_soc_ops msm_stub_be_ops = {
  6525. .hw_params = msm_snd_stub_hw_params,
  6526. };
  6527. struct snd_soc_card snd_soc_card_stub_msm = {
  6528. .name = "kona-stub-snd-card",
  6529. };
  6530. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6531. /* FrontEnd DAI Links */
  6532. {
  6533. .name = "MSMSTUB Media1",
  6534. .stream_name = "MultiMedia1",
  6535. .cpu_dai_name = "MultiMedia1",
  6536. .platform_name = "msm-pcm-dsp.0",
  6537. .dynamic = 1,
  6538. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6539. .dpcm_playback = 1,
  6540. .dpcm_capture = 1,
  6541. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6542. SND_SOC_DPCM_TRIGGER_POST},
  6543. .codec_dai_name = "snd-soc-dummy-dai",
  6544. .codec_name = "snd-soc-dummy",
  6545. .ignore_suspend = 1,
  6546. /* this dainlink has playback support */
  6547. .ignore_pmdown_time = 1,
  6548. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6549. },
  6550. };
  6551. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6552. /* Backend DAI Links */
  6553. {
  6554. .name = LPASS_BE_AUXPCM_RX,
  6555. .stream_name = "AUX PCM Playback",
  6556. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6557. .platform_name = "msm-pcm-routing",
  6558. .codec_name = "msm-stub-codec.1",
  6559. .codec_dai_name = "msm-stub-rx",
  6560. .no_pcm = 1,
  6561. .dpcm_playback = 1,
  6562. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6563. .init = &msm_audrx_stub_init,
  6564. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6565. .ignore_pmdown_time = 1,
  6566. .ignore_suspend = 1,
  6567. .ops = &msm_stub_be_ops,
  6568. },
  6569. {
  6570. .name = LPASS_BE_AUXPCM_TX,
  6571. .stream_name = "AUX PCM Capture",
  6572. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6573. .platform_name = "msm-pcm-routing",
  6574. .codec_name = "msm-stub-codec.1",
  6575. .codec_dai_name = "msm-stub-tx",
  6576. .no_pcm = 1,
  6577. .dpcm_capture = 1,
  6578. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6579. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6580. .ignore_suspend = 1,
  6581. .ops = &msm_stub_be_ops,
  6582. },
  6583. };
  6584. static struct snd_soc_dai_link msm_stub_dai_links[
  6585. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6586. ARRAY_SIZE(msm_stub_be_dai_links)];
  6587. static const struct of_device_id kona_asoc_machine_of_match[] = {
  6588. { .compatible = "qcom,kona-asoc-snd",
  6589. .data = "codec"},
  6590. { .compatible = "qcom,kona-asoc-snd-stub",
  6591. .data = "stub_codec"},
  6592. {},
  6593. };
  6594. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6595. {
  6596. struct snd_soc_card *card = NULL;
  6597. struct snd_soc_dai_link *dailink = NULL;
  6598. int len_1 = 0;
  6599. int len_2 = 0;
  6600. int total_links = 0;
  6601. int rc = 0;
  6602. u32 mi2s_audio_intf = 0;
  6603. u32 auxpcm_audio_intf = 0;
  6604. u32 val = 0;
  6605. u32 wcn_btfm_intf = 0;
  6606. const struct of_device_id *match;
  6607. match = of_match_node(kona_asoc_machine_of_match, dev->of_node);
  6608. if (!match) {
  6609. dev_err(dev, "%s: No DT match found for sound card\n",
  6610. __func__);
  6611. return NULL;
  6612. }
  6613. if (!strcmp(match->data, "codec")) {
  6614. card = &snd_soc_card_kona_msm;
  6615. memcpy(msm_kona_dai_links + total_links,
  6616. msm_common_dai_links,
  6617. sizeof(msm_common_dai_links));
  6618. total_links += ARRAY_SIZE(msm_common_dai_links);
  6619. memcpy(msm_kona_dai_links + total_links,
  6620. msm_bolero_fe_dai_links,
  6621. sizeof(msm_bolero_fe_dai_links));
  6622. total_links +=
  6623. ARRAY_SIZE(msm_bolero_fe_dai_links);
  6624. memcpy(msm_kona_dai_links + total_links,
  6625. msm_common_misc_fe_dai_links,
  6626. sizeof(msm_common_misc_fe_dai_links));
  6627. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6628. memcpy(msm_kona_dai_links + total_links,
  6629. msm_common_be_dai_links,
  6630. sizeof(msm_common_be_dai_links));
  6631. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6632. memcpy(msm_kona_dai_links + total_links,
  6633. msm_wsa_cdc_dma_be_dai_links,
  6634. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6635. total_links +=
  6636. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6637. memcpy(msm_kona_dai_links + total_links,
  6638. msm_rx_tx_cdc_dma_be_dai_links,
  6639. sizeof(msm_rx_tx_cdc_dma_be_dai_links));
  6640. total_links +=
  6641. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links);
  6642. memcpy(msm_kona_dai_links + total_links,
  6643. msm_va_cdc_dma_be_dai_links,
  6644. sizeof(msm_va_cdc_dma_be_dai_links));
  6645. total_links +=
  6646. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6647. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6648. &mi2s_audio_intf);
  6649. if (rc) {
  6650. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6651. __func__);
  6652. } else {
  6653. if (mi2s_audio_intf) {
  6654. memcpy(msm_kona_dai_links + total_links,
  6655. msm_mi2s_be_dai_links,
  6656. sizeof(msm_mi2s_be_dai_links));
  6657. total_links +=
  6658. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6659. }
  6660. }
  6661. rc = of_property_read_u32(dev->of_node,
  6662. "qcom,auxpcm-audio-intf",
  6663. &auxpcm_audio_intf);
  6664. if (rc) {
  6665. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6666. __func__);
  6667. } else {
  6668. if (auxpcm_audio_intf) {
  6669. memcpy(msm_kona_dai_links + total_links,
  6670. msm_auxpcm_be_dai_links,
  6671. sizeof(msm_auxpcm_be_dai_links));
  6672. total_links +=
  6673. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6674. }
  6675. }
  6676. rc = of_property_read_u32(dev->of_node,
  6677. "qcom,ext-disp-audio-rx", &val);
  6678. if (!rc && val) {
  6679. dev_dbg(dev, "%s(): ext disp audio support present\n",
  6680. __func__);
  6681. memcpy(msm_kona_dai_links + total_links,
  6682. ext_disp_be_dai_link,
  6683. sizeof(ext_disp_be_dai_link));
  6684. total_links += ARRAY_SIZE(ext_disp_be_dai_link);
  6685. }
  6686. rc = of_property_read_u32(dev->of_node, "qcom,wcn-bt", &val);
  6687. if (!rc && val) {
  6688. dev_dbg(dev, "%s(): WCN BT support present\n",
  6689. __func__);
  6690. memcpy(msm_kona_dai_links + total_links,
  6691. msm_wcn_be_dai_links,
  6692. sizeof(msm_wcn_be_dai_links));
  6693. total_links += ARRAY_SIZE(msm_wcn_be_dai_links);
  6694. }
  6695. rc = of_property_read_u32(dev->of_node, "qcom,afe-rxtx-lb",
  6696. &val);
  6697. if (!rc && val) {
  6698. memcpy(msm_kona_dai_links + total_links,
  6699. msm_afe_rxtx_lb_be_dai_link,
  6700. sizeof(msm_afe_rxtx_lb_be_dai_link));
  6701. total_links +=
  6702. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link);
  6703. }
  6704. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  6705. &wcn_btfm_intf);
  6706. if (rc) {
  6707. dev_dbg(dev, "%s: No DT match wcn btfm interface\n",
  6708. __func__);
  6709. } else {
  6710. if (wcn_btfm_intf) {
  6711. memcpy(msm_kona_dai_links + total_links,
  6712. msm_wcn_btfm_be_dai_links,
  6713. sizeof(msm_wcn_btfm_be_dai_links));
  6714. total_links +=
  6715. ARRAY_SIZE(msm_wcn_btfm_be_dai_links);
  6716. }
  6717. }
  6718. dailink = msm_kona_dai_links;
  6719. } else if(!strcmp(match->data, "stub_codec")) {
  6720. card = &snd_soc_card_stub_msm;
  6721. len_1 = ARRAY_SIZE(msm_stub_fe_dai_links);
  6722. len_2 = len_1 + ARRAY_SIZE(msm_stub_be_dai_links);
  6723. memcpy(msm_stub_dai_links,
  6724. msm_stub_fe_dai_links,
  6725. sizeof(msm_stub_fe_dai_links));
  6726. memcpy(msm_stub_dai_links + len_1,
  6727. msm_stub_be_dai_links,
  6728. sizeof(msm_stub_be_dai_links));
  6729. dailink = msm_stub_dai_links;
  6730. total_links = len_2;
  6731. }
  6732. if (card) {
  6733. card->dai_link = dailink;
  6734. card->num_links = total_links;
  6735. }
  6736. return card;
  6737. }
  6738. static int msm_wsa881x_init(struct snd_soc_component *component)
  6739. {
  6740. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6741. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6742. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  6743. SPKR_L_BOOST, SPKR_L_VI};
  6744. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  6745. SPKR_R_BOOST, SPKR_R_VI};
  6746. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  6747. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  6748. struct msm_asoc_mach_data *pdata;
  6749. struct snd_soc_dapm_context *dapm;
  6750. struct snd_card *card;
  6751. struct snd_info_entry *entry;
  6752. int ret = 0;
  6753. if (!component) {
  6754. pr_err("%s component is NULL\n", __func__);
  6755. return -EINVAL;
  6756. }
  6757. card = component->card->snd_card;
  6758. dapm = snd_soc_component_get_dapm(component);
  6759. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  6760. dev_dbg(component->dev, "%s: setting left ch map to codec %s\n",
  6761. __func__, component->name);
  6762. wsa881x_set_channel_map(component, &spkleft_ports[0],
  6763. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6764. &ch_rate[0], &spkleft_port_types[0]);
  6765. if (dapm->component) {
  6766. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  6767. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  6768. }
  6769. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  6770. dev_dbg(component->dev, "%s: setting right ch map to codec %s\n",
  6771. __func__, component->name);
  6772. wsa881x_set_channel_map(component, &spkright_ports[0],
  6773. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6774. &ch_rate[0], &spkright_port_types[0]);
  6775. if (dapm->component) {
  6776. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  6777. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  6778. }
  6779. } else {
  6780. dev_err(component->dev, "%s: wrong codec name %s\n", __func__,
  6781. component->name);
  6782. ret = -EINVAL;
  6783. goto err;
  6784. }
  6785. pdata = snd_soc_card_get_drvdata(component->card);
  6786. if (!pdata->codec_root) {
  6787. entry = snd_info_create_subdir(card->module, "codecs",
  6788. card->proc_root);
  6789. if (!entry) {
  6790. pr_err("%s: Cannot create codecs module entry\n",
  6791. __func__);
  6792. ret = 0;
  6793. goto err;
  6794. }
  6795. pdata->codec_root = entry;
  6796. }
  6797. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  6798. component);
  6799. err:
  6800. return ret;
  6801. }
  6802. static int msm_aux_codec_init(struct snd_soc_component *component)
  6803. {
  6804. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  6805. int ret = 0;
  6806. int codec_variant = -1;
  6807. void *mbhc_calibration;
  6808. struct snd_info_entry *entry;
  6809. struct snd_card *card = component->card->snd_card;
  6810. struct msm_asoc_mach_data *pdata;
  6811. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  6812. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  6813. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  6814. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  6815. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  6816. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  6817. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  6818. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  6819. snd_soc_dapm_sync(dapm);
  6820. pdata = snd_soc_card_get_drvdata(component->card);
  6821. if (!pdata->codec_root) {
  6822. entry = snd_info_create_subdir(card->module, "codecs",
  6823. card->proc_root);
  6824. if (!entry) {
  6825. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  6826. __func__);
  6827. ret = 0;
  6828. goto mbhc_cfg_cal;
  6829. }
  6830. pdata->codec_root = entry;
  6831. }
  6832. wcd938x_info_create_codec_entry(pdata->codec_root, component);
  6833. codec_variant = wcd938x_get_codec_variant(component);
  6834. dev_dbg(component->dev, "%s: variant %d\n", __func__, codec_variant);
  6835. if (codec_variant == WCD9380)
  6836. ret = snd_soc_add_component_controls(component,
  6837. msm_int_wcd9380_snd_controls,
  6838. ARRAY_SIZE(msm_int_wcd9380_snd_controls));
  6839. else if (codec_variant == WCD9385)
  6840. ret = snd_soc_add_component_controls(component,
  6841. msm_int_wcd9385_snd_controls,
  6842. ARRAY_SIZE(msm_int_wcd9385_snd_controls));
  6843. if (ret < 0) {
  6844. dev_err(component->dev, "%s: add codec specific snd controls failed: %d\n",
  6845. __func__, ret);
  6846. return ret;
  6847. }
  6848. mbhc_cfg_cal:
  6849. mbhc_calibration = def_wcd_mbhc_cal();
  6850. if (!mbhc_calibration)
  6851. return -ENOMEM;
  6852. wcd_mbhc_cfg.calibration = mbhc_calibration;
  6853. ret = wcd938x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
  6854. if (ret) {
  6855. dev_err(component->dev, "%s: mbhc hs detect failed, err:%d\n",
  6856. __func__, ret);
  6857. goto err_hs_detect;
  6858. }
  6859. return 0;
  6860. err_hs_detect:
  6861. kfree(mbhc_calibration);
  6862. return ret;
  6863. }
  6864. static int msm_init_aux_dev(struct platform_device *pdev,
  6865. struct snd_soc_card *card)
  6866. {
  6867. struct device_node *wsa_of_node;
  6868. struct device_node *aux_codec_of_node;
  6869. u32 wsa_max_devs;
  6870. u32 wsa_dev_cnt;
  6871. u32 codec_max_aux_devs = 0;
  6872. u32 codec_aux_dev_cnt = 0;
  6873. int i;
  6874. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  6875. struct aux_codec_dev_info *aux_cdc_dev_info;
  6876. const char *auxdev_name_prefix[1];
  6877. char *dev_name_str = NULL;
  6878. int found = 0;
  6879. int codecs_found = 0;
  6880. int ret = 0;
  6881. /* Get maximum WSA device count for this platform */
  6882. ret = of_property_read_u32(pdev->dev.of_node,
  6883. "qcom,wsa-max-devs", &wsa_max_devs);
  6884. if (ret) {
  6885. dev_info(&pdev->dev,
  6886. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  6887. __func__, pdev->dev.of_node->full_name, ret);
  6888. wsa_max_devs = 0;
  6889. goto codec_aux_dev;
  6890. }
  6891. if (wsa_max_devs == 0) {
  6892. dev_warn(&pdev->dev,
  6893. "%s: Max WSA devices is 0 for this target?\n",
  6894. __func__);
  6895. goto codec_aux_dev;
  6896. }
  6897. /* Get count of WSA device phandles for this platform */
  6898. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6899. "qcom,wsa-devs", NULL);
  6900. if (wsa_dev_cnt == -ENOENT) {
  6901. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  6902. __func__);
  6903. goto err;
  6904. } else if (wsa_dev_cnt <= 0) {
  6905. dev_err(&pdev->dev,
  6906. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  6907. __func__, wsa_dev_cnt);
  6908. ret = -EINVAL;
  6909. goto err;
  6910. }
  6911. /*
  6912. * Expect total phandles count to be NOT less than maximum possible
  6913. * WSA count. However, if it is less, then assign same value to
  6914. * max count as well.
  6915. */
  6916. if (wsa_dev_cnt < wsa_max_devs) {
  6917. dev_dbg(&pdev->dev,
  6918. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  6919. __func__, wsa_max_devs, wsa_dev_cnt);
  6920. wsa_max_devs = wsa_dev_cnt;
  6921. }
  6922. /* Make sure prefix string passed for each WSA device */
  6923. ret = of_property_count_strings(pdev->dev.of_node,
  6924. "qcom,wsa-aux-dev-prefix");
  6925. if (ret != wsa_dev_cnt) {
  6926. dev_err(&pdev->dev,
  6927. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  6928. __func__, wsa_dev_cnt, ret);
  6929. ret = -EINVAL;
  6930. goto err;
  6931. }
  6932. /*
  6933. * Alloc mem to store phandle and index info of WSA device, if already
  6934. * registered with ALSA core
  6935. */
  6936. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  6937. sizeof(struct msm_wsa881x_dev_info),
  6938. GFP_KERNEL);
  6939. if (!wsa881x_dev_info) {
  6940. ret = -ENOMEM;
  6941. goto err;
  6942. }
  6943. /*
  6944. * search and check whether all WSA devices are already
  6945. * registered with ALSA core or not. If found a node, store
  6946. * the node and the index in a local array of struct for later
  6947. * use.
  6948. */
  6949. for (i = 0; i < wsa_dev_cnt; i++) {
  6950. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  6951. "qcom,wsa-devs", i);
  6952. if (unlikely(!wsa_of_node)) {
  6953. /* we should not be here */
  6954. dev_err(&pdev->dev,
  6955. "%s: wsa dev node is not present\n",
  6956. __func__);
  6957. ret = -EINVAL;
  6958. goto err;
  6959. }
  6960. if (soc_find_component(wsa_of_node, NULL)) {
  6961. /* WSA device registered with ALSA core */
  6962. wsa881x_dev_info[found].of_node = wsa_of_node;
  6963. wsa881x_dev_info[found].index = i;
  6964. found++;
  6965. if (found == wsa_max_devs)
  6966. break;
  6967. }
  6968. }
  6969. if (found < wsa_max_devs) {
  6970. dev_dbg(&pdev->dev,
  6971. "%s: failed to find %d components. Found only %d\n",
  6972. __func__, wsa_max_devs, found);
  6973. return -EPROBE_DEFER;
  6974. }
  6975. dev_info(&pdev->dev,
  6976. "%s: found %d wsa881x devices registered with ALSA core\n",
  6977. __func__, found);
  6978. codec_aux_dev:
  6979. /* Get maximum aux codec device count for this platform */
  6980. ret = of_property_read_u32(pdev->dev.of_node,
  6981. "qcom,codec-max-aux-devs",
  6982. &codec_max_aux_devs);
  6983. if (ret) {
  6984. dev_err(&pdev->dev,
  6985. "%s: codec-max-aux-devs property missing in DT %s, ret = %d\n",
  6986. __func__, pdev->dev.of_node->full_name, ret);
  6987. codec_max_aux_devs = 0;
  6988. goto aux_dev_register;
  6989. }
  6990. if (codec_max_aux_devs == 0) {
  6991. dev_dbg(&pdev->dev,
  6992. "%s: Max aux codec devices is 0 for this target?\n",
  6993. __func__);
  6994. goto aux_dev_register;
  6995. }
  6996. /* Get count of aux codec device phandles for this platform */
  6997. codec_aux_dev_cnt = of_count_phandle_with_args(
  6998. pdev->dev.of_node,
  6999. "qcom,codec-aux-devs", NULL);
  7000. if (codec_aux_dev_cnt == -ENOENT) {
  7001. dev_warn(&pdev->dev, "%s: No aux codec defined in DT.\n",
  7002. __func__);
  7003. goto err;
  7004. } else if (codec_aux_dev_cnt <= 0) {
  7005. dev_err(&pdev->dev,
  7006. "%s: Error reading aux codec device from DT, dev_cnt=%d\n",
  7007. __func__, codec_aux_dev_cnt);
  7008. ret = -EINVAL;
  7009. goto err;
  7010. }
  7011. /*
  7012. * Expect total phandles count to be NOT less than maximum possible
  7013. * AUX device count. However, if it is less, then assign same value to
  7014. * max count as well.
  7015. */
  7016. if (codec_aux_dev_cnt < codec_max_aux_devs) {
  7017. dev_dbg(&pdev->dev,
  7018. "%s: codec_max_aux_devs = %d cannot exceed codec_aux_dev_cnt = %d\n",
  7019. __func__, codec_max_aux_devs,
  7020. codec_aux_dev_cnt);
  7021. codec_max_aux_devs = codec_aux_dev_cnt;
  7022. }
  7023. /*
  7024. * Alloc mem to store phandle and index info of aux codec
  7025. * if already registered with ALSA core
  7026. */
  7027. aux_cdc_dev_info = devm_kcalloc(&pdev->dev, codec_aux_dev_cnt,
  7028. sizeof(struct aux_codec_dev_info),
  7029. GFP_KERNEL);
  7030. if (!aux_cdc_dev_info) {
  7031. ret = -ENOMEM;
  7032. goto err;
  7033. }
  7034. /*
  7035. * search and check whether all aux codecs are already
  7036. * registered with ALSA core or not. If found a node, store
  7037. * the node and the index in a local array of struct for later
  7038. * use.
  7039. */
  7040. for (i = 0; i < codec_aux_dev_cnt; i++) {
  7041. aux_codec_of_node = of_parse_phandle(pdev->dev.of_node,
  7042. "qcom,codec-aux-devs", i);
  7043. if (unlikely(!aux_codec_of_node)) {
  7044. /* we should not be here */
  7045. dev_err(&pdev->dev,
  7046. "%s: aux codec dev node is not present\n",
  7047. __func__);
  7048. ret = -EINVAL;
  7049. goto err;
  7050. }
  7051. if (soc_find_component(aux_codec_of_node, NULL)) {
  7052. /* AUX codec registered with ALSA core */
  7053. aux_cdc_dev_info[codecs_found].of_node =
  7054. aux_codec_of_node;
  7055. aux_cdc_dev_info[codecs_found].index = i;
  7056. codecs_found++;
  7057. }
  7058. }
  7059. if (codecs_found < codec_aux_dev_cnt) {
  7060. dev_dbg(&pdev->dev,
  7061. "%s: failed to find %d components. Found only %d\n",
  7062. __func__, codec_aux_dev_cnt, codecs_found);
  7063. return -EPROBE_DEFER;
  7064. }
  7065. dev_info(&pdev->dev,
  7066. "%s: found %d AUX codecs registered with ALSA core\n",
  7067. __func__, codecs_found);
  7068. aux_dev_register:
  7069. card->num_aux_devs = wsa_max_devs + codec_aux_dev_cnt;
  7070. card->num_configs = wsa_max_devs + codec_aux_dev_cnt;
  7071. /* Alloc array of AUX devs struct */
  7072. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7073. sizeof(struct snd_soc_aux_dev),
  7074. GFP_KERNEL);
  7075. if (!msm_aux_dev) {
  7076. ret = -ENOMEM;
  7077. goto err;
  7078. }
  7079. /* Alloc array of codec conf struct */
  7080. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_configs,
  7081. sizeof(struct snd_soc_codec_conf),
  7082. GFP_KERNEL);
  7083. if (!msm_codec_conf) {
  7084. ret = -ENOMEM;
  7085. goto err;
  7086. }
  7087. for (i = 0; i < wsa_max_devs; i++) {
  7088. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7089. GFP_KERNEL);
  7090. if (!dev_name_str) {
  7091. ret = -ENOMEM;
  7092. goto err;
  7093. }
  7094. ret = of_property_read_string_index(pdev->dev.of_node,
  7095. "qcom,wsa-aux-dev-prefix",
  7096. wsa881x_dev_info[i].index,
  7097. auxdev_name_prefix);
  7098. if (ret) {
  7099. dev_err(&pdev->dev,
  7100. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  7101. __func__, ret);
  7102. ret = -EINVAL;
  7103. goto err;
  7104. }
  7105. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  7106. msm_aux_dev[i].name = dev_name_str;
  7107. msm_aux_dev[i].codec_name = NULL;
  7108. msm_aux_dev[i].codec_of_node =
  7109. wsa881x_dev_info[i].of_node;
  7110. msm_aux_dev[i].init = msm_wsa881x_init;
  7111. msm_codec_conf[i].dev_name = NULL;
  7112. msm_codec_conf[i].name_prefix = auxdev_name_prefix[0];
  7113. msm_codec_conf[i].of_node =
  7114. wsa881x_dev_info[i].of_node;
  7115. }
  7116. for (i = 0; i < codec_aux_dev_cnt; i++) {
  7117. msm_aux_dev[wsa_max_devs + i].name = NULL;
  7118. msm_aux_dev[wsa_max_devs + i].codec_name = NULL;
  7119. msm_aux_dev[wsa_max_devs + i].codec_of_node =
  7120. aux_cdc_dev_info[i].of_node;
  7121. msm_aux_dev[wsa_max_devs + i].init = msm_aux_codec_init;
  7122. msm_codec_conf[wsa_max_devs + i].dev_name = NULL;
  7123. msm_codec_conf[wsa_max_devs + i].name_prefix =
  7124. NULL;
  7125. msm_codec_conf[wsa_max_devs + i].of_node =
  7126. aux_cdc_dev_info[i].of_node;
  7127. }
  7128. card->codec_conf = msm_codec_conf;
  7129. card->aux_dev = msm_aux_dev;
  7130. err:
  7131. return ret;
  7132. }
  7133. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  7134. {
  7135. int count = 0;
  7136. u32 mi2s_master_slave[MI2S_MAX];
  7137. int ret = 0;
  7138. for (count = 0; count < MI2S_MAX; count++) {
  7139. mutex_init(&mi2s_intf_conf[count].lock);
  7140. mi2s_intf_conf[count].ref_cnt = 0;
  7141. }
  7142. ret = of_property_read_u32_array(pdev->dev.of_node,
  7143. "qcom,msm-mi2s-master",
  7144. mi2s_master_slave, MI2S_MAX);
  7145. if (ret) {
  7146. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  7147. __func__);
  7148. } else {
  7149. for (count = 0; count < MI2S_MAX; count++) {
  7150. mi2s_intf_conf[count].msm_is_mi2s_master =
  7151. mi2s_master_slave[count];
  7152. }
  7153. }
  7154. }
  7155. static void msm_i2s_auxpcm_deinit(void)
  7156. {
  7157. int count = 0;
  7158. for (count = 0; count < MI2S_MAX; count++) {
  7159. mutex_destroy(&mi2s_intf_conf[count].lock);
  7160. mi2s_intf_conf[count].ref_cnt = 0;
  7161. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  7162. }
  7163. }
  7164. static int kona_ssr_enable(struct device *dev, void *data)
  7165. {
  7166. struct platform_device *pdev = to_platform_device(dev);
  7167. struct snd_soc_card *card = platform_get_drvdata(pdev);
  7168. int ret = 0;
  7169. if (!card) {
  7170. dev_err(dev, "%s: card is NULL\n", __func__);
  7171. ret = -EINVAL;
  7172. goto err;
  7173. }
  7174. if (!strcmp(card->name, "kona-stub-snd-card")) {
  7175. /* TODO */
  7176. dev_dbg(dev, "%s: TODO \n", __func__);
  7177. }
  7178. snd_soc_card_change_online_state(card, 1);
  7179. dev_dbg(dev, "%s: setting snd_card to ONLINE\n", __func__);
  7180. err:
  7181. return ret;
  7182. }
  7183. static void kona_ssr_disable(struct device *dev, void *data)
  7184. {
  7185. struct platform_device *pdev = to_platform_device(dev);
  7186. struct snd_soc_card *card = platform_get_drvdata(pdev);
  7187. if (!card) {
  7188. dev_err(dev, "%s: card is NULL\n", __func__);
  7189. return;
  7190. }
  7191. dev_dbg(dev, "%s: setting snd_card to OFFLINE\n", __func__);
  7192. snd_soc_card_change_online_state(card, 0);
  7193. if (!strcmp(card->name, "kona-stub-snd-card")) {
  7194. /* TODO */
  7195. dev_dbg(dev, "%s: TODO \n", __func__);
  7196. }
  7197. }
  7198. static const struct snd_event_ops kona_ssr_ops = {
  7199. .enable = kona_ssr_enable,
  7200. .disable = kona_ssr_disable,
  7201. };
  7202. static int msm_audio_ssr_compare(struct device *dev, void *data)
  7203. {
  7204. struct device_node *node = data;
  7205. dev_dbg(dev, "%s: dev->of_node = 0x%p, node = 0x%p\n",
  7206. __func__, dev->of_node, node);
  7207. return (dev->of_node && dev->of_node == node);
  7208. }
  7209. static int msm_audio_ssr_register(struct device *dev)
  7210. {
  7211. struct device_node *np = dev->of_node;
  7212. struct snd_event_clients *ssr_clients = NULL;
  7213. struct device_node *node = NULL;
  7214. int ret = 0;
  7215. int i = 0;
  7216. for (i = 0; ; i++) {
  7217. node = of_parse_phandle(np, "qcom,msm_audio_ssr_devs", i);
  7218. if (!node)
  7219. break;
  7220. snd_event_mstr_add_client(&ssr_clients,
  7221. msm_audio_ssr_compare, node);
  7222. }
  7223. ret = snd_event_master_register(dev, &kona_ssr_ops,
  7224. ssr_clients, NULL);
  7225. if (!ret)
  7226. snd_event_notify(dev, SND_EVENT_UP);
  7227. return ret;
  7228. }
  7229. static int msm_asoc_machine_probe(struct platform_device *pdev)
  7230. {
  7231. struct snd_soc_card *card = NULL;
  7232. struct msm_asoc_mach_data *pdata = NULL;
  7233. const char *mbhc_audio_jack_type = NULL;
  7234. int ret = 0;
  7235. uint index = 0;
  7236. if (!pdev->dev.of_node) {
  7237. dev_err(&pdev->dev, "%s: No platform supplied from device tree\n", __func__);
  7238. return -EINVAL;
  7239. }
  7240. pdata = devm_kzalloc(&pdev->dev,
  7241. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  7242. if (!pdata)
  7243. return -ENOMEM;
  7244. of_property_read_u32(pdev->dev.of_node,
  7245. "qcom,lito-is-v2-enabled",
  7246. &pdata->lito_v2_enabled);
  7247. card = populate_snd_card_dailinks(&pdev->dev);
  7248. if (!card) {
  7249. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  7250. ret = -EINVAL;
  7251. goto err;
  7252. }
  7253. card->dev = &pdev->dev;
  7254. platform_set_drvdata(pdev, card);
  7255. snd_soc_card_set_drvdata(card, pdata);
  7256. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  7257. if (ret) {
  7258. dev_err(&pdev->dev, "%s: parse card name failed, err:%d\n",
  7259. __func__, ret);
  7260. goto err;
  7261. }
  7262. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  7263. if (ret) {
  7264. dev_err(&pdev->dev, "%s: parse audio routing failed, err:%d\n",
  7265. __func__, ret);
  7266. goto err;
  7267. }
  7268. ret = msm_populate_dai_link_component_of_node(card);
  7269. if (ret) {
  7270. ret = -EPROBE_DEFER;
  7271. goto err;
  7272. }
  7273. ret = msm_init_aux_dev(pdev, card);
  7274. if (ret)
  7275. goto err;
  7276. ret = devm_snd_soc_register_card(&pdev->dev, card);
  7277. if (ret == -EPROBE_DEFER) {
  7278. if (codec_reg_done)
  7279. ret = -EINVAL;
  7280. goto err;
  7281. } else if (ret) {
  7282. dev_err(&pdev->dev, "%s: snd_soc_register_card failed (%d)\n",
  7283. __func__, ret);
  7284. goto err;
  7285. }
  7286. dev_info(&pdev->dev, "%s: Sound card %s registered\n",
  7287. __func__, card->name);
  7288. pdata->hph_en1_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7289. "qcom,hph-en1-gpio", 0);
  7290. if (!pdata->hph_en1_gpio_p) {
  7291. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  7292. __func__, "qcom,hph-en1-gpio",
  7293. pdev->dev.of_node->full_name);
  7294. }
  7295. pdata->hph_en0_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7296. "qcom,hph-en0-gpio", 0);
  7297. if (!pdata->hph_en0_gpio_p) {
  7298. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  7299. __func__, "qcom,hph-en0-gpio",
  7300. pdev->dev.of_node->full_name);
  7301. }
  7302. ret = of_property_read_string(pdev->dev.of_node,
  7303. "qcom,mbhc-audio-jack-type", &mbhc_audio_jack_type);
  7304. if (ret) {
  7305. dev_dbg(&pdev->dev, "%s: Looking up %s property in node %s failed\n",
  7306. __func__, "qcom,mbhc-audio-jack-type",
  7307. pdev->dev.of_node->full_name);
  7308. dev_dbg(&pdev->dev, "Jack type properties set to default\n");
  7309. } else {
  7310. if (!strcmp(mbhc_audio_jack_type, "4-pole-jack")) {
  7311. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  7312. dev_dbg(&pdev->dev, "This hardware has 4 pole jack");
  7313. } else if (!strcmp(mbhc_audio_jack_type, "5-pole-jack")) {
  7314. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  7315. dev_dbg(&pdev->dev, "This hardware has 5 pole jack");
  7316. } else if (!strcmp(mbhc_audio_jack_type, "6-pole-jack")) {
  7317. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  7318. dev_dbg(&pdev->dev, "This hardware has 6 pole jack");
  7319. } else {
  7320. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  7321. dev_dbg(&pdev->dev, "Unknown value, set to default\n");
  7322. }
  7323. }
  7324. /*
  7325. * Parse US-Euro gpio info from DT. Report no error if us-euro
  7326. * entry is not found in DT file as some targets do not support
  7327. * US-Euro detection
  7328. */
  7329. pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7330. "qcom,us-euro-gpios", 0);
  7331. if (!pdata->us_euro_gpio_p) {
  7332. dev_dbg(&pdev->dev, "property %s not detected in node %s",
  7333. "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
  7334. } else {
  7335. dev_dbg(&pdev->dev, "%s detected\n",
  7336. "qcom,us-euro-gpios");
  7337. wcd_mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
  7338. }
  7339. if (wcd_mbhc_cfg.enable_usbc_analog)
  7340. wcd_mbhc_cfg.swap_gnd_mic = msm_usbc_swap_gnd_mic;
  7341. pdata->fsa_handle = of_parse_phandle(pdev->dev.of_node,
  7342. "fsa4480-i2c-handle", 0);
  7343. if (!pdata->fsa_handle)
  7344. dev_dbg(&pdev->dev, "property %s not detected in node %s\n",
  7345. "fsa4480-i2c-handle", pdev->dev.of_node->full_name);
  7346. msm_i2s_auxpcm_init(pdev);
  7347. pdata->dmic01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7348. "qcom,cdc-dmic01-gpios",
  7349. 0);
  7350. pdata->dmic23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7351. "qcom,cdc-dmic23-gpios",
  7352. 0);
  7353. pdata->dmic45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7354. "qcom,cdc-dmic45-gpios",
  7355. 0);
  7356. if (pdata->dmic01_gpio_p)
  7357. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic01_gpio_p, false);
  7358. if (pdata->dmic23_gpio_p)
  7359. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic23_gpio_p, false);
  7360. if (pdata->dmic45_gpio_p)
  7361. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic45_gpio_p, false);
  7362. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7363. "qcom,pri-mi2s-gpios", 0);
  7364. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7365. "qcom,sec-mi2s-gpios", 0);
  7366. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7367. "qcom,tert-mi2s-gpios", 0);
  7368. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7369. "qcom,quat-mi2s-gpios", 0);
  7370. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7371. "qcom,quin-mi2s-gpios", 0);
  7372. pdata->mi2s_gpio_p[SEN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7373. "qcom,sen-mi2s-gpios", 0);
  7374. for (index = PRIM_MI2S; index < MI2S_MAX; index++)
  7375. atomic_set(&(pdata->mi2s_gpio_ref_count[index]), 0);
  7376. ret = msm_audio_ssr_register(&pdev->dev);
  7377. if (ret)
  7378. pr_err("%s: Registration with SND event FWK failed ret = %d\n",
  7379. __func__, ret);
  7380. is_initial_boot = true;
  7381. return 0;
  7382. err:
  7383. devm_kfree(&pdev->dev, pdata);
  7384. return ret;
  7385. }
  7386. static int msm_asoc_machine_remove(struct platform_device *pdev)
  7387. {
  7388. struct snd_soc_card *card = platform_get_drvdata(pdev);
  7389. snd_event_master_deregister(&pdev->dev);
  7390. snd_soc_unregister_card(card);
  7391. msm_i2s_auxpcm_deinit();
  7392. return 0;
  7393. }
  7394. static struct platform_driver kona_asoc_machine_driver = {
  7395. .driver = {
  7396. .name = DRV_NAME,
  7397. .owner = THIS_MODULE,
  7398. .pm = &snd_soc_pm_ops,
  7399. .of_match_table = kona_asoc_machine_of_match,
  7400. .suppress_bind_attrs = true,
  7401. },
  7402. .probe = msm_asoc_machine_probe,
  7403. .remove = msm_asoc_machine_remove,
  7404. };
  7405. module_platform_driver(kona_asoc_machine_driver);
  7406. MODULE_DESCRIPTION("ALSA SoC msm");
  7407. MODULE_LICENSE("GPL v2");
  7408. MODULE_ALIAS("platform:" DRV_NAME);
  7409. MODULE_DEVICE_TABLE(of, kona_asoc_machine_of_match);