wcd938x.c 102 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "internal.h"
  23. #include "wcd938x-registers.h"
  24. #include "wcd938x.h"
  25. #define WCD938X_DRV_NAME "wcd938x_codec"
  26. #define NUM_SWRS_DT_PARAMS 5
  27. #define WCD938X_VARIANT_ENTRY_SIZE 32
  28. #define WCD938X_VERSION_1_0 1
  29. #define WCD938X_VERSION_ENTRY_SIZE 32
  30. #define EAR_RX_PATH_AUX 1
  31. #define ADC_MODE_VAL_HIFI 0x01
  32. #define ADC_MODE_VAL_LO_HIF 0x02
  33. #define ADC_MODE_VAL_NORMAL 0x03
  34. #define ADC_MODE_VAL_LP 0x05
  35. #define ADC_MODE_VAL_ULP1 0x09
  36. #define ADC_MODE_VAL_ULP2 0x0B
  37. enum {
  38. CODEC_TX = 0,
  39. CODEC_RX,
  40. };
  41. enum {
  42. WCD_ADC1 = 0,
  43. WCD_ADC2,
  44. WCD_ADC3,
  45. WCD_ADC4,
  46. ALLOW_BUCK_DISABLE,
  47. HPH_COMP_DELAY,
  48. HPH_PA_DELAY,
  49. AMIC2_BCS_ENABLE,
  50. };
  51. enum {
  52. ADC_MODE_INVALID = 0,
  53. ADC_MODE_HIFI,
  54. ADC_MODE_LO_HIF,
  55. ADC_MODE_NORMAL,
  56. ADC_MODE_LP,
  57. ADC_MODE_ULP1,
  58. ADC_MODE_ULP2,
  59. };
  60. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  61. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  62. static int wcd938x_handle_post_irq(void *data);
  63. static int wcd938x_reset(struct device *dev);
  64. static int wcd938x_reset_low(struct device *dev);
  65. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  66. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  67. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  68. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  69. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  70. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  71. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  72. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  73. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  74. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  75. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  76. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  77. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  78. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  79. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  80. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  81. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  82. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  83. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  84. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  85. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  86. };
  87. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  88. .name = "wcd938x",
  89. .irqs = wcd938x_irqs,
  90. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  91. .num_regs = 3,
  92. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  93. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  94. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  95. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  96. .use_ack = 1,
  97. .runtime_pm = false,
  98. .handle_post_irq = wcd938x_handle_post_irq,
  99. .irq_drv_data = NULL,
  100. };
  101. static int wcd938x_handle_post_irq(void *data)
  102. {
  103. struct wcd938x_priv *wcd938x = data;
  104. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  105. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  106. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  107. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  108. wcd938x->tx_swr_dev->slave_irq_pending =
  109. ((sts1 || sts2 || sts3) ? true : false);
  110. return IRQ_HANDLED;
  111. }
  112. static int wcd938x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  113. {
  114. int ret = 0;
  115. int bank = 0;
  116. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  117. if (ret)
  118. return -EINVAL;
  119. return ((bank & 0x40) ? 1: 0);
  120. }
  121. static int wcd938x_swr_slv_set_host_clk_div2(struct swr_device *dev,
  122. u8 devnum, int bank)
  123. {
  124. u8 val = (bank ? 1 : 0);
  125. return (swr_write(dev, devnum,
  126. (SWR_SCP_HOST_CLK_DIV2_CTL_BANK + (0x10 * bank)), &val));
  127. }
  128. static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
  129. int mode, int bank)
  130. {
  131. u8 mask = (bank ? 0xF0 : 0x0F);
  132. u8 val = 0;
  133. if ((mode == ADC_MODE_ULP1) || (mode == ADC_MODE_ULP2))
  134. val = (bank ? 0x60 : 0x06);
  135. else
  136. val = 0x00;
  137. snd_soc_component_update_bits(component,
  138. WCD938X_DIGITAL_SWR_TX_CLK_RATE,
  139. mask, val);
  140. return 0;
  141. }
  142. static int wcd938x_init_reg(struct snd_soc_component *component)
  143. {
  144. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  145. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  146. /* 1 msec delay as per HW requirement */
  147. usleep_range(1000, 1010);
  148. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  149. /* 1 msec delay as per HW requirement */
  150. usleep_range(1000, 1010);
  151. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  152. 0x10, 0x00);
  153. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  154. 0xF0, 0x80);
  155. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  156. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  157. /* 10 msec delay as per HW requirement */
  158. usleep_range(10000, 10010);
  159. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  160. snd_soc_component_update_bits(component,
  161. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  162. 0xF0, 0x00);
  163. snd_soc_component_update_bits(component,
  164. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  165. 0x1F, 0x15);
  166. snd_soc_component_update_bits(component,
  167. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  168. 0x1F, 0x15);
  169. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  170. 0xC0, 0x80);
  171. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  172. 0x02, 0x02);
  173. snd_soc_component_update_bits(component,
  174. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  175. 0xFF, 0x14);
  176. snd_soc_component_update_bits(component,
  177. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  178. 0x1F, 0x08);
  179. snd_soc_component_update_bits(component,
  180. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  181. snd_soc_component_update_bits(component,
  182. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  183. snd_soc_component_update_bits(component,
  184. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  185. snd_soc_component_update_bits(component,
  186. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  187. snd_soc_component_update_bits(component,
  188. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  189. snd_soc_component_update_bits(component,
  190. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  191. snd_soc_component_update_bits(component,
  192. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  193. snd_soc_component_update_bits(component,
  194. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  195. snd_soc_component_update_bits(component,
  196. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  197. snd_soc_component_update_bits(component,
  198. WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
  199. return 0;
  200. }
  201. static int wcd938x_set_port_params(struct snd_soc_component *component,
  202. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  203. u8 *ch_mask, u32 *ch_rate,
  204. u8 *port_type, u8 path)
  205. {
  206. int i, j;
  207. u8 num_ports = 0;
  208. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  209. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  210. switch (path) {
  211. case CODEC_RX:
  212. map = &wcd938x->rx_port_mapping;
  213. num_ports = wcd938x->num_rx_ports;
  214. break;
  215. case CODEC_TX:
  216. map = &wcd938x->tx_port_mapping;
  217. num_ports = wcd938x->num_tx_ports;
  218. break;
  219. default:
  220. dev_err(component->dev, "%s Invalid path selected %u\n",
  221. __func__, path);
  222. return -EINVAL;
  223. }
  224. for (i = 0; i <= num_ports; i++) {
  225. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  226. if ((*map)[i][j].slave_port_type == slv_prt_type)
  227. goto found;
  228. }
  229. }
  230. found:
  231. if (i > num_ports || j == MAX_CH_PER_PORT) {
  232. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  233. __func__, slv_prt_type);
  234. return -EINVAL;
  235. }
  236. *port_id = i;
  237. *num_ch = (*map)[i][j].num_ch;
  238. *ch_mask = (*map)[i][j].ch_mask;
  239. *ch_rate = (*map)[i][j].ch_rate;
  240. *port_type = (*map)[i][j].master_port_type;
  241. return 0;
  242. }
  243. static int wcd938x_parse_port_mapping(struct device *dev,
  244. char *prop, u8 path)
  245. {
  246. u32 *dt_array, map_size, map_length;
  247. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  248. u32 slave_port_type, master_port_type;
  249. u32 i, ch_iter = 0;
  250. int ret = 0;
  251. u8 *num_ports = NULL;
  252. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  253. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  254. switch (path) {
  255. case CODEC_RX:
  256. map = &wcd938x->rx_port_mapping;
  257. num_ports = &wcd938x->num_rx_ports;
  258. break;
  259. case CODEC_TX:
  260. map = &wcd938x->tx_port_mapping;
  261. num_ports = &wcd938x->num_tx_ports;
  262. break;
  263. default:
  264. dev_err(dev, "%s Invalid path selected %u\n",
  265. __func__, path);
  266. return -EINVAL;
  267. }
  268. if (!of_find_property(dev->of_node, prop,
  269. &map_size)) {
  270. dev_err(dev, "missing port mapping prop %s\n", prop);
  271. ret = -EINVAL;
  272. goto err_port_map;
  273. }
  274. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  275. dt_array = kzalloc(map_size, GFP_KERNEL);
  276. if (!dt_array) {
  277. ret = -ENOMEM;
  278. goto err_alloc;
  279. }
  280. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  281. NUM_SWRS_DT_PARAMS * map_length);
  282. if (ret) {
  283. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  284. __func__, prop);
  285. goto err_pdata_fail;
  286. }
  287. for (i = 0; i < map_length; i++) {
  288. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  289. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  290. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  291. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  292. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  293. if (port_num != old_port_num)
  294. ch_iter = 0;
  295. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  296. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  297. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  298. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  299. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  300. old_port_num = port_num;
  301. }
  302. *num_ports = port_num;
  303. kfree(dt_array);
  304. return 0;
  305. err_pdata_fail:
  306. kfree(dt_array);
  307. err_alloc:
  308. err_port_map:
  309. return ret;
  310. }
  311. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  312. u8 slv_port_type, u8 enable)
  313. {
  314. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  315. u8 port_id, num_ch, ch_mask, port_type;
  316. u32 ch_rate;
  317. u8 num_port = 1;
  318. int ret = 0;
  319. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  320. &num_ch, &ch_mask, &ch_rate,
  321. &port_type, CODEC_TX);
  322. if (ret)
  323. return ret;
  324. if (enable)
  325. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  326. num_port, &ch_mask, &ch_rate,
  327. &num_ch, &port_type);
  328. else
  329. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  330. num_port, &ch_mask, &port_type);
  331. return ret;
  332. }
  333. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  334. u8 slv_port_type, u8 enable)
  335. {
  336. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  337. u8 port_id, num_ch, ch_mask, port_type;
  338. u32 ch_rate;
  339. u8 num_port = 1;
  340. int ret = 0;
  341. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  342. &num_ch, &ch_mask, &ch_rate,
  343. &port_type, CODEC_RX);
  344. if (ret)
  345. return ret;
  346. if (enable)
  347. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  348. num_port, &ch_mask, &ch_rate,
  349. &num_ch, &port_type);
  350. else
  351. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  352. num_port, &ch_mask, &port_type);
  353. return ret;
  354. }
  355. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  356. {
  357. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  358. if (wcd938x->rx_clk_cnt == 0) {
  359. snd_soc_component_update_bits(component,
  360. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  361. snd_soc_component_update_bits(component,
  362. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  363. snd_soc_component_update_bits(component,
  364. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  365. snd_soc_component_update_bits(component,
  366. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  367. snd_soc_component_update_bits(component,
  368. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  369. snd_soc_component_update_bits(component,
  370. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  371. snd_soc_component_update_bits(component,
  372. WCD938X_AUX_AUXPA, 0x10, 0x10);
  373. }
  374. wcd938x->rx_clk_cnt++;
  375. return 0;
  376. }
  377. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  378. {
  379. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  380. wcd938x->rx_clk_cnt--;
  381. if (wcd938x->rx_clk_cnt == 0) {
  382. snd_soc_component_update_bits(component,
  383. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  384. snd_soc_component_update_bits(component,
  385. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  386. snd_soc_component_update_bits(component,
  387. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  388. snd_soc_component_update_bits(component,
  389. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  390. snd_soc_component_update_bits(component,
  391. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  392. }
  393. return 0;
  394. }
  395. /*
  396. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  397. * @component: handle to snd_soc_component *
  398. *
  399. * return wcd938x_mbhc handle or error code in case of failure
  400. */
  401. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  402. {
  403. struct wcd938x_priv *wcd938x;
  404. if (!component) {
  405. pr_err("%s: Invalid params, NULL component\n", __func__);
  406. return NULL;
  407. }
  408. wcd938x = snd_soc_component_get_drvdata(component);
  409. if (!wcd938x) {
  410. pr_err("%s: wcd938x is NULL\n", __func__);
  411. return NULL;
  412. }
  413. return wcd938x->mbhc;
  414. }
  415. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  416. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  417. struct snd_kcontrol *kcontrol,
  418. int event)
  419. {
  420. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  421. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  422. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  423. w->name, event);
  424. switch (event) {
  425. case SND_SOC_DAPM_PRE_PMU:
  426. wcd938x_rx_clk_enable(component);
  427. snd_soc_component_update_bits(component,
  428. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  429. snd_soc_component_update_bits(component,
  430. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  431. snd_soc_component_update_bits(component,
  432. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  433. break;
  434. case SND_SOC_DAPM_POST_PMU:
  435. snd_soc_component_update_bits(component,
  436. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  437. if (wcd938x->comp1_enable) {
  438. snd_soc_component_update_bits(component,
  439. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  440. /* 5msec compander delay as per HW requirement */
  441. if (!wcd938x->comp2_enable ||
  442. (snd_soc_component_read32(component,
  443. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  444. usleep_range(5000, 5010);
  445. snd_soc_component_update_bits(component,
  446. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  447. } else {
  448. snd_soc_component_update_bits(component,
  449. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  450. 0x02, 0x00);
  451. snd_soc_component_update_bits(component,
  452. WCD938X_HPH_L_EN, 0x20, 0x20);
  453. }
  454. break;
  455. case SND_SOC_DAPM_POST_PMD:
  456. snd_soc_component_update_bits(component,
  457. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  458. 0x0F, 0x01);
  459. break;
  460. }
  461. return 0;
  462. }
  463. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  464. struct snd_kcontrol *kcontrol,
  465. int event)
  466. {
  467. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  468. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  469. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  470. w->name, event);
  471. switch (event) {
  472. case SND_SOC_DAPM_PRE_PMU:
  473. wcd938x_rx_clk_enable(component);
  474. snd_soc_component_update_bits(component,
  475. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  476. snd_soc_component_update_bits(component,
  477. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  478. snd_soc_component_update_bits(component,
  479. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  480. break;
  481. case SND_SOC_DAPM_POST_PMU:
  482. snd_soc_component_update_bits(component,
  483. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  484. if (wcd938x->comp2_enable) {
  485. snd_soc_component_update_bits(component,
  486. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  487. /* 5msec compander delay as per HW requirement */
  488. if (!wcd938x->comp1_enable ||
  489. (snd_soc_component_read32(component,
  490. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  491. usleep_range(5000, 5010);
  492. snd_soc_component_update_bits(component,
  493. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  494. } else {
  495. snd_soc_component_update_bits(component,
  496. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  497. 0x01, 0x00);
  498. snd_soc_component_update_bits(component,
  499. WCD938X_HPH_R_EN, 0x20, 0x20);
  500. }
  501. break;
  502. case SND_SOC_DAPM_POST_PMD:
  503. snd_soc_component_update_bits(component,
  504. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  505. 0x0F, 0x01);
  506. break;
  507. }
  508. return 0;
  509. }
  510. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  511. struct snd_kcontrol *kcontrol,
  512. int event)
  513. {
  514. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  515. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  516. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  517. w->name, event);
  518. switch (event) {
  519. case SND_SOC_DAPM_PRE_PMU:
  520. wcd938x_rx_clk_enable(component);
  521. wcd938x->ear_rx_path =
  522. snd_soc_component_read32(
  523. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  524. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  525. snd_soc_component_update_bits(component,
  526. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x00);
  527. snd_soc_component_update_bits(component,
  528. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  529. snd_soc_component_update_bits(component,
  530. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  531. snd_soc_component_update_bits(component,
  532. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  533. } else {
  534. snd_soc_component_update_bits(component,
  535. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  536. snd_soc_component_update_bits(component,
  537. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  538. snd_soc_component_update_bits(component,
  539. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  540. }
  541. /* 5 msec delay as per HW requirement */
  542. usleep_range(5000, 5010);
  543. if (wcd938x->flyback_cur_det_disable == 0)
  544. snd_soc_component_update_bits(component,
  545. WCD938X_FLYBACK_EN,
  546. 0x04, 0x00);
  547. wcd938x->flyback_cur_det_disable++;
  548. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  549. WCD_CLSH_EVENT_PRE_DAC,
  550. WCD_CLSH_STATE_EAR,
  551. wcd938x->hph_mode);
  552. break;
  553. case SND_SOC_DAPM_POST_PMD:
  554. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  555. snd_soc_component_update_bits(component,
  556. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x00);
  557. }
  558. snd_soc_component_update_bits(component,
  559. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  560. snd_soc_component_update_bits(component,
  561. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x80);
  562. break;
  563. };
  564. return 0;
  565. }
  566. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  567. struct snd_kcontrol *kcontrol,
  568. int event)
  569. {
  570. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  571. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  572. int ret = 0;
  573. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  574. w->name, event);
  575. switch (event) {
  576. case SND_SOC_DAPM_PRE_PMU:
  577. wcd938x_rx_clk_enable(component);
  578. snd_soc_component_update_bits(component,
  579. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  580. snd_soc_component_update_bits(component,
  581. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  582. snd_soc_component_update_bits(component,
  583. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  584. if (wcd938x->flyback_cur_det_disable == 0)
  585. snd_soc_component_update_bits(component,
  586. WCD938X_FLYBACK_EN,
  587. 0x04, 0x00);
  588. wcd938x->flyback_cur_det_disable++;
  589. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  590. WCD_CLSH_EVENT_PRE_DAC,
  591. WCD_CLSH_STATE_AUX,
  592. wcd938x->hph_mode);
  593. break;
  594. case SND_SOC_DAPM_POST_PMD:
  595. snd_soc_component_update_bits(component,
  596. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  597. break;
  598. };
  599. return ret;
  600. }
  601. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  602. struct snd_kcontrol *kcontrol,
  603. int event)
  604. {
  605. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  606. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  607. int ret = 0;
  608. int hph_mode = wcd938x->hph_mode;
  609. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  610. w->name, event);
  611. switch (event) {
  612. case SND_SOC_DAPM_PRE_PMU:
  613. if (wcd938x->ldoh)
  614. snd_soc_component_update_bits(component,
  615. WCD938X_LDOH_MODE,
  616. 0x80, 0x80);
  617. if (wcd938x->update_wcd_event)
  618. wcd938x->update_wcd_event(wcd938x->handle,
  619. WCD_BOLERO_EVT_RX_MUTE,
  620. (WCD_RX2 << 0x10 | 0x1));
  621. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  622. wcd938x->rx_swr_dev->dev_num,
  623. true);
  624. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  625. WCD_CLSH_EVENT_PRE_DAC,
  626. WCD_CLSH_STATE_HPHR,
  627. hph_mode);
  628. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  629. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  630. 0x10, 0x10);
  631. wcd_clsh_set_hph_mode(component, hph_mode);
  632. /* 100 usec delay as per HW requirement */
  633. usleep_range(100, 110);
  634. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  635. snd_soc_component_update_bits(component,
  636. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  637. break;
  638. case SND_SOC_DAPM_POST_PMU:
  639. /*
  640. * 7ms sleep is required if compander is enabled as per
  641. * HW requirement. If compander is disabled, then
  642. * 20ms delay is required.
  643. */
  644. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  645. if (!wcd938x->comp2_enable)
  646. usleep_range(20000, 20100);
  647. else
  648. usleep_range(7000, 7100);
  649. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  650. }
  651. snd_soc_component_update_bits(component,
  652. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  653. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  654. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  655. snd_soc_component_update_bits(component,
  656. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  657. if (wcd938x->update_wcd_event)
  658. wcd938x->update_wcd_event(wcd938x->handle,
  659. WCD_BOLERO_EVT_RX_MUTE,
  660. (WCD_RX2 << 0x10));
  661. wcd_enable_irq(&wcd938x->irq_info,
  662. WCD938X_IRQ_HPHR_PDM_WD_INT);
  663. break;
  664. case SND_SOC_DAPM_PRE_PMD:
  665. if (wcd938x->update_wcd_event)
  666. wcd938x->update_wcd_event(wcd938x->handle,
  667. WCD_BOLERO_EVT_RX_MUTE,
  668. (WCD_RX2 << 0x10 | 0x1));
  669. wcd_disable_irq(&wcd938x->irq_info,
  670. WCD938X_IRQ_HPHR_PDM_WD_INT);
  671. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  672. wcd938x->update_wcd_event(wcd938x->handle,
  673. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  674. (WCD_RX2 << 0x10));
  675. /*
  676. * 7ms sleep is required if compander is enabled as per
  677. * HW requirement. If compander is disabled, then
  678. * 20ms delay is required.
  679. */
  680. if (!wcd938x->comp2_enable)
  681. usleep_range(20000, 20100);
  682. else
  683. usleep_range(7000, 7100);
  684. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  685. 0x40, 0x00);
  686. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  687. WCD_EVENT_PRE_HPHR_PA_OFF,
  688. &wcd938x->mbhc->wcd_mbhc);
  689. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  690. break;
  691. case SND_SOC_DAPM_POST_PMD:
  692. /*
  693. * 7ms sleep is required if compander is enabled as per
  694. * HW requirement. If compander is disabled, then
  695. * 20ms delay is required.
  696. */
  697. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  698. if (!wcd938x->comp2_enable)
  699. usleep_range(20000, 20100);
  700. else
  701. usleep_range(7000, 7100);
  702. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  703. }
  704. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  705. WCD_EVENT_POST_HPHR_PA_OFF,
  706. &wcd938x->mbhc->wcd_mbhc);
  707. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  708. 0x10, 0x00);
  709. snd_soc_component_update_bits(component,
  710. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  711. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  712. WCD_CLSH_EVENT_POST_PA,
  713. WCD_CLSH_STATE_HPHR,
  714. hph_mode);
  715. if (wcd938x->ldoh)
  716. snd_soc_component_update_bits(component,
  717. WCD938X_LDOH_MODE,
  718. 0x80, 0x00);
  719. break;
  720. };
  721. return ret;
  722. }
  723. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  724. struct snd_kcontrol *kcontrol,
  725. int event)
  726. {
  727. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  728. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  729. int ret = 0;
  730. int hph_mode = wcd938x->hph_mode;
  731. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  732. w->name, event);
  733. switch (event) {
  734. case SND_SOC_DAPM_PRE_PMU:
  735. if (wcd938x->ldoh)
  736. snd_soc_component_update_bits(component,
  737. WCD938X_LDOH_MODE,
  738. 0x80, 0x80);
  739. if (wcd938x->update_wcd_event)
  740. wcd938x->update_wcd_event(wcd938x->handle,
  741. WCD_BOLERO_EVT_RX_MUTE,
  742. (WCD_RX1 << 0x10 | 0x01));
  743. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  744. wcd938x->rx_swr_dev->dev_num,
  745. true);
  746. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  747. WCD_CLSH_EVENT_PRE_DAC,
  748. WCD_CLSH_STATE_HPHL,
  749. hph_mode);
  750. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  751. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  752. 0x20, 0x20);
  753. wcd_clsh_set_hph_mode(component, hph_mode);
  754. /* 100 usec delay as per HW requirement */
  755. usleep_range(100, 110);
  756. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  757. snd_soc_component_update_bits(component,
  758. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  759. break;
  760. case SND_SOC_DAPM_POST_PMU:
  761. /*
  762. * 7ms sleep is required if compander is enabled as per
  763. * HW requirement. If compander is disabled, then
  764. * 20ms delay is required.
  765. */
  766. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  767. if (!wcd938x->comp1_enable)
  768. usleep_range(20000, 20100);
  769. else
  770. usleep_range(7000, 7100);
  771. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  772. }
  773. snd_soc_component_update_bits(component,
  774. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  775. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  776. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  777. snd_soc_component_update_bits(component,
  778. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  779. if (wcd938x->update_wcd_event)
  780. wcd938x->update_wcd_event(wcd938x->handle,
  781. WCD_BOLERO_EVT_RX_MUTE,
  782. (WCD_RX1 << 0x10));
  783. wcd_enable_irq(&wcd938x->irq_info,
  784. WCD938X_IRQ_HPHL_PDM_WD_INT);
  785. break;
  786. case SND_SOC_DAPM_PRE_PMD:
  787. if (wcd938x->update_wcd_event)
  788. wcd938x->update_wcd_event(wcd938x->handle,
  789. WCD_BOLERO_EVT_RX_MUTE,
  790. (WCD_RX1 << 0x10 | 0x1));
  791. wcd_disable_irq(&wcd938x->irq_info,
  792. WCD938X_IRQ_HPHL_PDM_WD_INT);
  793. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  794. wcd938x->update_wcd_event(wcd938x->handle,
  795. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  796. (WCD_RX1 << 0x10));
  797. /*
  798. * 7ms sleep is required if compander is enabled as per
  799. * HW requirement. If compander is disabled, then
  800. * 20ms delay is required.
  801. */
  802. if (!wcd938x->comp1_enable)
  803. usleep_range(20000, 20100);
  804. else
  805. usleep_range(7000, 7100);
  806. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  807. 0x80, 0x00);
  808. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  809. WCD_EVENT_PRE_HPHL_PA_OFF,
  810. &wcd938x->mbhc->wcd_mbhc);
  811. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  812. break;
  813. case SND_SOC_DAPM_POST_PMD:
  814. /*
  815. * 7ms sleep is required if compander is enabled as per
  816. * HW requirement. If compander is disabled, then
  817. * 20ms delay is required.
  818. */
  819. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  820. if (!wcd938x->comp1_enable)
  821. usleep_range(21000, 21100);
  822. else
  823. usleep_range(7000, 7100);
  824. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  825. }
  826. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  827. WCD_EVENT_POST_HPHL_PA_OFF,
  828. &wcd938x->mbhc->wcd_mbhc);
  829. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  830. 0x20, 0x00);
  831. snd_soc_component_update_bits(component,
  832. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  833. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  834. WCD_CLSH_EVENT_POST_PA,
  835. WCD_CLSH_STATE_HPHL,
  836. hph_mode);
  837. if (wcd938x->ldoh)
  838. snd_soc_component_update_bits(component,
  839. WCD938X_LDOH_MODE,
  840. 0x80, 0x00);
  841. break;
  842. };
  843. return ret;
  844. }
  845. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  846. struct snd_kcontrol *kcontrol,
  847. int event)
  848. {
  849. struct snd_soc_component *component =
  850. snd_soc_dapm_to_component(w->dapm);
  851. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  852. int hph_mode = wcd938x->hph_mode;
  853. int ret = 0;
  854. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  855. w->name, event);
  856. switch (event) {
  857. case SND_SOC_DAPM_PRE_PMU:
  858. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  859. wcd938x->rx_swr_dev->dev_num,
  860. true);
  861. snd_soc_component_update_bits(component,
  862. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  863. break;
  864. case SND_SOC_DAPM_POST_PMU:
  865. /* 1 msec delay as per HW requirement */
  866. usleep_range(1000, 1010);
  867. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  868. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  869. snd_soc_component_update_bits(component,
  870. WCD938X_ANA_RX_SUPPLIES,
  871. 0x02, 0x02);
  872. if (wcd938x->update_wcd_event)
  873. wcd938x->update_wcd_event(wcd938x->handle,
  874. WCD_BOLERO_EVT_RX_MUTE,
  875. (WCD_RX3 << 0x10));
  876. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  877. break;
  878. case SND_SOC_DAPM_PRE_PMD:
  879. wcd_disable_irq(&wcd938x->irq_info,
  880. WCD938X_IRQ_AUX_PDM_WD_INT);
  881. if (wcd938x->update_wcd_event)
  882. wcd938x->update_wcd_event(wcd938x->handle,
  883. WCD_BOLERO_EVT_RX_MUTE,
  884. (WCD_RX3 << 0x10 | 0x1));
  885. break;
  886. case SND_SOC_DAPM_POST_PMD:
  887. /* 1 msec delay as per HW requirement */
  888. usleep_range(1000, 1010);
  889. snd_soc_component_update_bits(component,
  890. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  891. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  892. WCD_CLSH_EVENT_POST_PA,
  893. WCD_CLSH_STATE_AUX,
  894. hph_mode);
  895. wcd938x->flyback_cur_det_disable--;
  896. if (wcd938x->flyback_cur_det_disable == 0)
  897. snd_soc_component_update_bits(component,
  898. WCD938X_FLYBACK_EN,
  899. 0x04, 0x04);
  900. break;
  901. };
  902. return ret;
  903. }
  904. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  905. struct snd_kcontrol *kcontrol,
  906. int event)
  907. {
  908. struct snd_soc_component *component =
  909. snd_soc_dapm_to_component(w->dapm);
  910. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  911. int hph_mode = wcd938x->hph_mode;
  912. int ret = 0;
  913. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  914. w->name, event);
  915. switch (event) {
  916. case SND_SOC_DAPM_PRE_PMU:
  917. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  918. wcd938x->rx_swr_dev->dev_num,
  919. true);
  920. /*
  921. * Enable watchdog interrupt for HPHL or AUX
  922. * depending on mux value
  923. */
  924. wcd938x->ear_rx_path =
  925. snd_soc_component_read32(
  926. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  927. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  928. snd_soc_component_update_bits(component,
  929. WCD938X_DIGITAL_PDM_WD_CTL2,
  930. 0x05, 0x05);
  931. else
  932. snd_soc_component_update_bits(component,
  933. WCD938X_DIGITAL_PDM_WD_CTL0,
  934. 0x17, 0x13);
  935. break;
  936. case SND_SOC_DAPM_POST_PMU:
  937. /* 6 msec delay as per HW requirement */
  938. usleep_range(6000, 6010);
  939. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  940. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  941. snd_soc_component_update_bits(component,
  942. WCD938X_ANA_RX_SUPPLIES,
  943. 0x02, 0x02);
  944. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  945. if (wcd938x->update_wcd_event)
  946. wcd938x->update_wcd_event(wcd938x->handle,
  947. WCD_BOLERO_EVT_RX_MUTE,
  948. (WCD_RX3 << 0x10));
  949. wcd_enable_irq(&wcd938x->irq_info,
  950. WCD938X_IRQ_AUX_PDM_WD_INT);
  951. } else {
  952. if (wcd938x->update_wcd_event)
  953. wcd938x->update_wcd_event(wcd938x->handle,
  954. WCD_BOLERO_EVT_RX_MUTE,
  955. (WCD_RX1 << 0x10));
  956. wcd_enable_irq(&wcd938x->irq_info,
  957. WCD938X_IRQ_HPHL_PDM_WD_INT);
  958. }
  959. break;
  960. case SND_SOC_DAPM_PRE_PMD:
  961. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  962. wcd_disable_irq(&wcd938x->irq_info,
  963. WCD938X_IRQ_AUX_PDM_WD_INT);
  964. else
  965. wcd_disable_irq(&wcd938x->irq_info,
  966. WCD938X_IRQ_HPHL_PDM_WD_INT);
  967. if (wcd938x->update_wcd_event)
  968. wcd938x->update_wcd_event(wcd938x->handle,
  969. WCD_BOLERO_EVT_RX_MUTE,
  970. (WCD_RX1 << 0x10 | 0x1));
  971. break;
  972. case SND_SOC_DAPM_POST_PMD:
  973. /* 7 msec delay as per HW requirement */
  974. usleep_range(7000, 7010);
  975. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  976. snd_soc_component_update_bits(component,
  977. WCD938X_DIGITAL_PDM_WD_CTL2,
  978. 0x05, 0x00);
  979. else
  980. snd_soc_component_update_bits(component,
  981. WCD938X_DIGITAL_PDM_WD_CTL0,
  982. 0x17, 0x00);
  983. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  984. WCD_CLSH_EVENT_POST_PA,
  985. WCD_CLSH_STATE_EAR,
  986. hph_mode);
  987. wcd938x->flyback_cur_det_disable--;
  988. if (wcd938x->flyback_cur_det_disable == 0)
  989. snd_soc_component_update_bits(component,
  990. WCD938X_FLYBACK_EN,
  991. 0x04, 0x04);
  992. break;
  993. };
  994. return ret;
  995. }
  996. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  997. struct snd_kcontrol *kcontrol,
  998. int event)
  999. {
  1000. struct snd_soc_component *component =
  1001. snd_soc_dapm_to_component(w->dapm);
  1002. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1003. int mode = wcd938x->hph_mode;
  1004. int ret = 0;
  1005. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1006. w->name, event);
  1007. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1008. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1009. wcd938x_rx_connect_port(component, CLSH,
  1010. SND_SOC_DAPM_EVENT_ON(event));
  1011. }
  1012. if (SND_SOC_DAPM_EVENT_OFF(event))
  1013. ret = swr_slvdev_datapath_control(
  1014. wcd938x->rx_swr_dev,
  1015. wcd938x->rx_swr_dev->dev_num,
  1016. false);
  1017. return ret;
  1018. }
  1019. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  1020. struct snd_kcontrol *kcontrol,
  1021. int event)
  1022. {
  1023. struct snd_soc_component *component =
  1024. snd_soc_dapm_to_component(w->dapm);
  1025. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1026. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1027. w->name, event);
  1028. switch (event) {
  1029. case SND_SOC_DAPM_PRE_PMU:
  1030. wcd938x_rx_connect_port(component, HPH_L, true);
  1031. if (wcd938x->comp1_enable)
  1032. wcd938x_rx_connect_port(component, COMP_L, true);
  1033. break;
  1034. case SND_SOC_DAPM_POST_PMD:
  1035. wcd938x_rx_connect_port(component, HPH_L, false);
  1036. if (wcd938x->comp1_enable)
  1037. wcd938x_rx_connect_port(component, COMP_L, false);
  1038. wcd938x_rx_clk_disable(component);
  1039. snd_soc_component_update_bits(component,
  1040. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1041. 0x01, 0x00);
  1042. break;
  1043. };
  1044. return 0;
  1045. }
  1046. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  1047. struct snd_kcontrol *kcontrol, int event)
  1048. {
  1049. struct snd_soc_component *component =
  1050. snd_soc_dapm_to_component(w->dapm);
  1051. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1052. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1053. w->name, event);
  1054. switch (event) {
  1055. case SND_SOC_DAPM_PRE_PMU:
  1056. wcd938x_rx_connect_port(component, HPH_R, true);
  1057. if (wcd938x->comp2_enable)
  1058. wcd938x_rx_connect_port(component, COMP_R, true);
  1059. break;
  1060. case SND_SOC_DAPM_POST_PMD:
  1061. wcd938x_rx_connect_port(component, HPH_R, false);
  1062. if (wcd938x->comp2_enable)
  1063. wcd938x_rx_connect_port(component, COMP_R, false);
  1064. wcd938x_rx_clk_disable(component);
  1065. snd_soc_component_update_bits(component,
  1066. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1067. 0x02, 0x00);
  1068. break;
  1069. };
  1070. return 0;
  1071. }
  1072. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1073. struct snd_kcontrol *kcontrol,
  1074. int event)
  1075. {
  1076. struct snd_soc_component *component =
  1077. snd_soc_dapm_to_component(w->dapm);
  1078. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1079. w->name, event);
  1080. switch (event) {
  1081. case SND_SOC_DAPM_PRE_PMU:
  1082. wcd938x_rx_connect_port(component, LO, true);
  1083. break;
  1084. case SND_SOC_DAPM_POST_PMD:
  1085. wcd938x_rx_connect_port(component, LO, false);
  1086. /* 6 msec delay as per HW requirement */
  1087. usleep_range(6000, 6010);
  1088. wcd938x_rx_clk_disable(component);
  1089. snd_soc_component_update_bits(component,
  1090. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1091. break;
  1092. }
  1093. return 0;
  1094. }
  1095. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1096. struct snd_kcontrol *kcontrol,
  1097. int event)
  1098. {
  1099. struct snd_soc_component *component =
  1100. snd_soc_dapm_to_component(w->dapm);
  1101. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1102. u16 dmic_clk_reg, dmic_clk_en_reg;
  1103. s32 *dmic_clk_cnt;
  1104. u8 dmic_ctl_shift = 0;
  1105. u8 dmic_clk_shift = 0;
  1106. u8 dmic_clk_mask = 0;
  1107. u16 dmic2_left_en = 0;
  1108. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1109. w->name, event);
  1110. switch (w->shift) {
  1111. case 0:
  1112. case 1:
  1113. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1114. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1115. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1116. dmic_clk_mask = 0x0F;
  1117. dmic_clk_shift = 0x00;
  1118. dmic_ctl_shift = 0x00;
  1119. break;
  1120. case 2:
  1121. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1122. case 3:
  1123. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1124. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1125. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1126. dmic_clk_mask = 0xF0;
  1127. dmic_clk_shift = 0x04;
  1128. dmic_ctl_shift = 0x01;
  1129. break;
  1130. case 4:
  1131. case 5:
  1132. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1133. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1134. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1135. dmic_clk_mask = 0x0F;
  1136. dmic_clk_shift = 0x00;
  1137. dmic_ctl_shift = 0x02;
  1138. break;
  1139. case 6:
  1140. case 7:
  1141. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1142. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1143. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1144. dmic_clk_mask = 0xF0;
  1145. dmic_clk_shift = 0x04;
  1146. dmic_ctl_shift = 0x03;
  1147. break;
  1148. default:
  1149. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1150. __func__);
  1151. return -EINVAL;
  1152. };
  1153. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1154. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1155. switch (event) {
  1156. case SND_SOC_DAPM_PRE_PMU:
  1157. snd_soc_component_update_bits(component,
  1158. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1159. (0x01 << dmic_ctl_shift), 0x00);
  1160. /* 250us sleep as per HW requirement */
  1161. usleep_range(250, 260);
  1162. if (dmic2_left_en)
  1163. snd_soc_component_update_bits(component,
  1164. dmic2_left_en, 0x80, 0x80);
  1165. /* Setting DMIC clock rate to 2.4MHz */
  1166. snd_soc_component_update_bits(component,
  1167. dmic_clk_reg, dmic_clk_mask,
  1168. (0x03 << dmic_clk_shift));
  1169. snd_soc_component_update_bits(component,
  1170. dmic_clk_en_reg, 0x08, 0x08);
  1171. /* enable clock scaling */
  1172. snd_soc_component_update_bits(component,
  1173. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1174. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1175. break;
  1176. case SND_SOC_DAPM_POST_PMD:
  1177. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1178. snd_soc_component_update_bits(component,
  1179. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1180. (0x01 << dmic_ctl_shift),
  1181. (0x01 << dmic_ctl_shift));
  1182. if (dmic2_left_en)
  1183. snd_soc_component_update_bits(component,
  1184. dmic2_left_en, 0x80, 0x00);
  1185. snd_soc_component_update_bits(component,
  1186. dmic_clk_en_reg, 0x08, 0x00);
  1187. break;
  1188. };
  1189. return 0;
  1190. }
  1191. /*
  1192. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1193. * @micb_mv: micbias in mv
  1194. *
  1195. * return register value converted
  1196. */
  1197. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1198. {
  1199. /* min micbias voltage is 1V and maximum is 2.85V */
  1200. if (micb_mv < 1000 || micb_mv > 2850) {
  1201. pr_err("%s: unsupported micbias voltage\n", __func__);
  1202. return -EINVAL;
  1203. }
  1204. return (micb_mv - 1000) / 50;
  1205. }
  1206. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1207. /*
  1208. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1209. * @component: handle to snd_soc_component *
  1210. * @req_volt: micbias voltage to be set
  1211. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1212. *
  1213. * return 0 if adjustment is success or error code in case of failure
  1214. */
  1215. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1216. int req_volt, int micb_num)
  1217. {
  1218. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1219. int cur_vout_ctl, req_vout_ctl;
  1220. int micb_reg, micb_val, micb_en;
  1221. int ret = 0;
  1222. switch (micb_num) {
  1223. case MIC_BIAS_1:
  1224. micb_reg = WCD938X_ANA_MICB1;
  1225. break;
  1226. case MIC_BIAS_2:
  1227. micb_reg = WCD938X_ANA_MICB2;
  1228. break;
  1229. case MIC_BIAS_3:
  1230. micb_reg = WCD938X_ANA_MICB3;
  1231. break;
  1232. case MIC_BIAS_4:
  1233. micb_reg = WCD938X_ANA_MICB4;
  1234. break;
  1235. default:
  1236. return -EINVAL;
  1237. }
  1238. mutex_lock(&wcd938x->micb_lock);
  1239. /*
  1240. * If requested micbias voltage is same as current micbias
  1241. * voltage, then just return. Otherwise, adjust voltage as
  1242. * per requested value. If micbias is already enabled, then
  1243. * to avoid slow micbias ramp-up or down enable pull-up
  1244. * momentarily, change the micbias value and then re-enable
  1245. * micbias.
  1246. */
  1247. micb_val = snd_soc_component_read32(component, micb_reg);
  1248. micb_en = (micb_val & 0xC0) >> 6;
  1249. cur_vout_ctl = micb_val & 0x3F;
  1250. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1251. if (req_vout_ctl < 0) {
  1252. ret = -EINVAL;
  1253. goto exit;
  1254. }
  1255. if (cur_vout_ctl == req_vout_ctl) {
  1256. ret = 0;
  1257. goto exit;
  1258. }
  1259. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1260. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1261. req_volt, micb_en);
  1262. if (micb_en == 0x1)
  1263. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1264. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1265. if (micb_en == 0x1) {
  1266. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1267. /*
  1268. * Add 2ms delay as per HW requirement after enabling
  1269. * micbias
  1270. */
  1271. usleep_range(2000, 2100);
  1272. }
  1273. exit:
  1274. mutex_unlock(&wcd938x->micb_lock);
  1275. return ret;
  1276. }
  1277. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1278. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1279. struct snd_kcontrol *kcontrol,
  1280. int event)
  1281. {
  1282. struct snd_soc_component *component =
  1283. snd_soc_dapm_to_component(w->dapm);
  1284. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1285. int ret = 0;
  1286. int bank = 0;
  1287. int mode = 0;
  1288. bank = wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1289. wcd938x->tx_swr_dev->dev_num);
  1290. wcd938x_swr_slv_set_host_clk_div2(wcd938x->tx_swr_dev,
  1291. wcd938x->tx_swr_dev->dev_num, bank);
  1292. switch (event) {
  1293. case SND_SOC_DAPM_PRE_PMU:
  1294. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1295. wcd938x->tx_swr_dev->dev_num,
  1296. true);
  1297. if (test_bit(WCD_ADC1, &wcd938x->status_mask))
  1298. mode |= wcd938x->tx_mode[WCD_ADC1];
  1299. if (test_bit(WCD_ADC2, &wcd938x->status_mask))
  1300. mode |= wcd938x->tx_mode[WCD_ADC2];
  1301. if (test_bit(WCD_ADC3, &wcd938x->status_mask))
  1302. mode |= wcd938x->tx_mode[WCD_ADC3];
  1303. if (test_bit(WCD_ADC4, &wcd938x->status_mask))
  1304. mode |= wcd938x->tx_mode[WCD_ADC4];
  1305. wcd938x_set_swr_clk_rate(component, mode, bank);
  1306. break;
  1307. case SND_SOC_DAPM_POST_PMD:
  1308. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1309. wcd938x->tx_swr_dev->dev_num,
  1310. false);
  1311. wcd938x_set_swr_clk_rate(component, ADC_MODE_INVALID, bank);
  1312. break;
  1313. };
  1314. return ret;
  1315. }
  1316. static int wcd938x_get_adc_mode(int val)
  1317. {
  1318. int ret = 0;
  1319. switch (val) {
  1320. case ADC_MODE_INVALID:
  1321. ret = ADC_MODE_VAL_NORMAL;
  1322. break;
  1323. case ADC_MODE_HIFI:
  1324. ret = ADC_MODE_VAL_HIFI;
  1325. break;
  1326. case ADC_MODE_LO_HIF:
  1327. ret = ADC_MODE_VAL_LO_HIF;
  1328. break;
  1329. case ADC_MODE_NORMAL:
  1330. ret = ADC_MODE_VAL_NORMAL;
  1331. break;
  1332. case ADC_MODE_LP:
  1333. ret = ADC_MODE_VAL_LP;
  1334. break;
  1335. case ADC_MODE_ULP1:
  1336. ret = ADC_MODE_VAL_ULP1;
  1337. break;
  1338. case ADC_MODE_ULP2:
  1339. ret = ADC_MODE_VAL_ULP2;
  1340. break;
  1341. default:
  1342. ret = -EINVAL;
  1343. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1344. break;
  1345. }
  1346. return ret;
  1347. }
  1348. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1349. struct snd_kcontrol *kcontrol,
  1350. int event){
  1351. struct snd_soc_component *component =
  1352. snd_soc_dapm_to_component(w->dapm);
  1353. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1354. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1355. w->name, event);
  1356. switch (event) {
  1357. case SND_SOC_DAPM_PRE_PMU:
  1358. snd_soc_component_update_bits(component,
  1359. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1360. snd_soc_component_update_bits(component,
  1361. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1362. set_bit(w->shift, &wcd938x->status_mask);
  1363. /* Enable BCS for Headset mic */
  1364. if (w->shift == 1 && !(snd_soc_component_read32(component,
  1365. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1366. wcd938x_tx_connect_port(component, MBHC, true);
  1367. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1368. }
  1369. wcd938x_tx_connect_port(component, ADC1 + (w->shift), true);
  1370. break;
  1371. case SND_SOC_DAPM_POST_PMD:
  1372. wcd938x_tx_connect_port(component, ADC1 + (w->shift), false);
  1373. if (w->shift == 1 &&
  1374. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1375. wcd938x_tx_connect_port(component, MBHC, false);
  1376. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1377. }
  1378. snd_soc_component_update_bits(component,
  1379. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1380. clear_bit(w->shift, &wcd938x->status_mask);
  1381. break;
  1382. };
  1383. return 0;
  1384. }
  1385. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1386. int channel, int mode)
  1387. {
  1388. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1389. int ret = 0;
  1390. switch (channel) {
  1391. case 0:
  1392. reg = WCD938X_ANA_TX_CH2;
  1393. mask = 0x40;
  1394. break;
  1395. case 1:
  1396. reg = WCD938X_ANA_TX_CH2;
  1397. mask = 0x20;
  1398. break;
  1399. case 2:
  1400. reg = WCD938X_ANA_TX_CH4;
  1401. mask = 0x40;
  1402. break;
  1403. case 3:
  1404. reg = WCD938X_ANA_TX_CH4;
  1405. mask = 0x20;
  1406. break;
  1407. default:
  1408. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1409. ret = -EINVAL;
  1410. break;
  1411. }
  1412. if (!mode)
  1413. val = 0x00;
  1414. else
  1415. val = mask;
  1416. if (!ret)
  1417. snd_soc_component_update_bits(component, reg, mask, val);
  1418. return ret;
  1419. }
  1420. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1421. struct snd_kcontrol *kcontrol, int event)
  1422. {
  1423. struct snd_soc_component *component =
  1424. snd_soc_dapm_to_component(w->dapm);
  1425. int mode;
  1426. int ret = 0;
  1427. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1428. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1429. w->name, event);
  1430. switch (event) {
  1431. case SND_SOC_DAPM_PRE_PMU:
  1432. snd_soc_component_update_bits(component,
  1433. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1434. snd_soc_component_update_bits(component,
  1435. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1436. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1437. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1438. if (mode < 0) {
  1439. dev_info(component->dev,
  1440. "%s: invalid mode, setting to normal mode\n",
  1441. __func__);
  1442. mode = ADC_MODE_VAL_NORMAL;
  1443. }
  1444. switch (w->shift) {
  1445. case 0:
  1446. snd_soc_component_update_bits(component,
  1447. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1448. mode);
  1449. snd_soc_component_update_bits(component,
  1450. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1451. break;
  1452. case 1:
  1453. snd_soc_component_update_bits(component,
  1454. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1455. mode << 4);
  1456. snd_soc_component_update_bits(component,
  1457. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1458. break;
  1459. case 2:
  1460. snd_soc_component_update_bits(component,
  1461. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1462. mode);
  1463. snd_soc_component_update_bits(component,
  1464. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1465. break;
  1466. case 3:
  1467. snd_soc_component_update_bits(component,
  1468. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1469. mode << 4);
  1470. snd_soc_component_update_bits(component,
  1471. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1472. break;
  1473. default:
  1474. break;
  1475. }
  1476. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1477. break;
  1478. case SND_SOC_DAPM_POST_PMD:
  1479. switch (w->shift) {
  1480. case 0:
  1481. snd_soc_component_update_bits(component,
  1482. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1483. break;
  1484. case 1:
  1485. snd_soc_component_update_bits(component,
  1486. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1487. break;
  1488. case 2:
  1489. snd_soc_component_update_bits(component,
  1490. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1491. break;
  1492. case 3:
  1493. snd_soc_component_update_bits(component,
  1494. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1495. break;
  1496. default:
  1497. break;
  1498. }
  1499. snd_soc_component_update_bits(component,
  1500. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1501. break;
  1502. };
  1503. return ret;
  1504. }
  1505. int wcd938x_micbias_control(struct snd_soc_component *component,
  1506. int micb_num, int req, bool is_dapm)
  1507. {
  1508. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1509. int micb_index = micb_num - 1;
  1510. u16 micb_reg;
  1511. int pre_off_event = 0, post_off_event = 0;
  1512. int post_on_event = 0, post_dapm_off = 0;
  1513. int post_dapm_on = 0;
  1514. int ret = 0;
  1515. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1516. dev_err(component->dev,
  1517. "%s: Invalid micbias index, micb_ind:%d\n",
  1518. __func__, micb_index);
  1519. return -EINVAL;
  1520. }
  1521. if (NULL == wcd938x) {
  1522. dev_err(component->dev,
  1523. "%s: wcd938x private data is NULL\n", __func__);
  1524. return -EINVAL;
  1525. }
  1526. switch (micb_num) {
  1527. case MIC_BIAS_1:
  1528. micb_reg = WCD938X_ANA_MICB1;
  1529. break;
  1530. case MIC_BIAS_2:
  1531. micb_reg = WCD938X_ANA_MICB2;
  1532. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1533. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1534. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1535. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1536. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1537. break;
  1538. case MIC_BIAS_3:
  1539. micb_reg = WCD938X_ANA_MICB3;
  1540. break;
  1541. case MIC_BIAS_4:
  1542. micb_reg = WCD938X_ANA_MICB4;
  1543. break;
  1544. default:
  1545. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1546. __func__, micb_num);
  1547. return -EINVAL;
  1548. };
  1549. mutex_lock(&wcd938x->micb_lock);
  1550. switch (req) {
  1551. case MICB_PULLUP_ENABLE:
  1552. if (!wcd938x->dev_up) {
  1553. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1554. __func__, req);
  1555. ret = -ENODEV;
  1556. goto done;
  1557. }
  1558. wcd938x->pullup_ref[micb_index]++;
  1559. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1560. (wcd938x->micb_ref[micb_index] == 0))
  1561. snd_soc_component_update_bits(component, micb_reg,
  1562. 0xC0, 0x80);
  1563. break;
  1564. case MICB_PULLUP_DISABLE:
  1565. if (wcd938x->pullup_ref[micb_index] > 0)
  1566. wcd938x->pullup_ref[micb_index]--;
  1567. if (!wcd938x->dev_up) {
  1568. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1569. __func__, req);
  1570. ret = -ENODEV;
  1571. goto done;
  1572. }
  1573. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1574. (wcd938x->micb_ref[micb_index] == 0))
  1575. snd_soc_component_update_bits(component, micb_reg,
  1576. 0xC0, 0x00);
  1577. break;
  1578. case MICB_ENABLE:
  1579. if (!wcd938x->dev_up) {
  1580. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1581. __func__, req);
  1582. ret = -ENODEV;
  1583. goto done;
  1584. }
  1585. wcd938x->micb_ref[micb_index]++;
  1586. if (wcd938x->micb_ref[micb_index] == 1) {
  1587. snd_soc_component_update_bits(component,
  1588. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1589. snd_soc_component_update_bits(component,
  1590. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1591. snd_soc_component_update_bits(component,
  1592. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1593. snd_soc_component_update_bits(component,
  1594. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1595. snd_soc_component_update_bits(component,
  1596. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1597. snd_soc_component_update_bits(component,
  1598. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1599. snd_soc_component_update_bits(component,
  1600. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1601. snd_soc_component_update_bits(component,
  1602. micb_reg, 0xC0, 0x40);
  1603. if (post_on_event)
  1604. blocking_notifier_call_chain(
  1605. &wcd938x->mbhc->notifier,
  1606. post_on_event,
  1607. &wcd938x->mbhc->wcd_mbhc);
  1608. }
  1609. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1610. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1611. post_dapm_on,
  1612. &wcd938x->mbhc->wcd_mbhc);
  1613. break;
  1614. case MICB_DISABLE:
  1615. if (wcd938x->micb_ref[micb_index] > 0)
  1616. wcd938x->micb_ref[micb_index]--;
  1617. if (!wcd938x->dev_up) {
  1618. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1619. __func__, req);
  1620. ret = -ENODEV;
  1621. goto done;
  1622. }
  1623. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1624. (wcd938x->pullup_ref[micb_index] > 0))
  1625. snd_soc_component_update_bits(component, micb_reg,
  1626. 0xC0, 0x80);
  1627. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1628. (wcd938x->pullup_ref[micb_index] == 0)) {
  1629. if (pre_off_event && wcd938x->mbhc)
  1630. blocking_notifier_call_chain(
  1631. &wcd938x->mbhc->notifier,
  1632. pre_off_event,
  1633. &wcd938x->mbhc->wcd_mbhc);
  1634. snd_soc_component_update_bits(component, micb_reg,
  1635. 0xC0, 0x00);
  1636. if (post_off_event && wcd938x->mbhc)
  1637. blocking_notifier_call_chain(
  1638. &wcd938x->mbhc->notifier,
  1639. post_off_event,
  1640. &wcd938x->mbhc->wcd_mbhc);
  1641. }
  1642. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1643. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1644. post_dapm_off,
  1645. &wcd938x->mbhc->wcd_mbhc);
  1646. break;
  1647. };
  1648. dev_dbg(component->dev,
  1649. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1650. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1651. wcd938x->pullup_ref[micb_index]);
  1652. done:
  1653. mutex_unlock(&wcd938x->micb_lock);
  1654. return ret;
  1655. }
  1656. EXPORT_SYMBOL(wcd938x_micbias_control);
  1657. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1658. {
  1659. int ret = 0;
  1660. uint8_t devnum = 0;
  1661. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1662. if (ret) {
  1663. dev_err(&swr_dev->dev,
  1664. "%s get devnum %d for dev addr %lx failed\n",
  1665. __func__, devnum, swr_dev->addr);
  1666. swr_remove_device(swr_dev);
  1667. return ret;
  1668. }
  1669. swr_dev->dev_num = devnum;
  1670. return 0;
  1671. }
  1672. static int wcd938x_event_notify(struct notifier_block *block,
  1673. unsigned long val,
  1674. void *data)
  1675. {
  1676. u16 event = (val & 0xffff);
  1677. int ret = 0;
  1678. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1679. struct snd_soc_component *component = wcd938x->component;
  1680. struct wcd_mbhc *mbhc;
  1681. switch (event) {
  1682. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1683. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1684. snd_soc_component_update_bits(component,
  1685. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1686. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1687. }
  1688. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1689. snd_soc_component_update_bits(component,
  1690. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1691. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1692. }
  1693. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1694. snd_soc_component_update_bits(component,
  1695. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1696. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1697. }
  1698. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1699. snd_soc_component_update_bits(component,
  1700. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1701. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1702. }
  1703. break;
  1704. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1705. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1706. 0xC0, 0x00);
  1707. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1708. 0x80, 0x00);
  1709. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1710. 0x80, 0x00);
  1711. break;
  1712. case BOLERO_WCD_EVT_SSR_DOWN:
  1713. wcd938x->dev_up = false;
  1714. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1715. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  1716. wcd938x_reset_low(wcd938x->dev);
  1717. break;
  1718. case BOLERO_WCD_EVT_SSR_UP:
  1719. wcd938x_reset(wcd938x->dev);
  1720. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1721. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1722. wcd938x_init_reg(component);
  1723. regcache_mark_dirty(wcd938x->regmap);
  1724. regcache_sync(wcd938x->regmap);
  1725. /* Initialize MBHC module */
  1726. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1727. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1728. if (ret) {
  1729. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1730. __func__);
  1731. } else {
  1732. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1733. }
  1734. wcd938x->dev_up = true;
  1735. break;
  1736. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1737. snd_soc_component_update_bits(component,
  1738. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1739. ((val >> 0x10) << 0x01));
  1740. break;
  1741. default:
  1742. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1743. break;
  1744. }
  1745. return 0;
  1746. }
  1747. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1748. int event)
  1749. {
  1750. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1751. int micb_num;
  1752. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1753. __func__, w->name, event);
  1754. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1755. micb_num = MIC_BIAS_1;
  1756. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1757. micb_num = MIC_BIAS_2;
  1758. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1759. micb_num = MIC_BIAS_3;
  1760. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1761. micb_num = MIC_BIAS_4;
  1762. else
  1763. return -EINVAL;
  1764. switch (event) {
  1765. case SND_SOC_DAPM_PRE_PMU:
  1766. wcd938x_micbias_control(component, micb_num,
  1767. MICB_ENABLE, true);
  1768. break;
  1769. case SND_SOC_DAPM_POST_PMU:
  1770. /* 1 msec delay as per HW requirement */
  1771. usleep_range(1000, 1100);
  1772. break;
  1773. case SND_SOC_DAPM_POST_PMD:
  1774. wcd938x_micbias_control(component, micb_num,
  1775. MICB_DISABLE, true);
  1776. break;
  1777. };
  1778. return 0;
  1779. }
  1780. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1781. struct snd_kcontrol *kcontrol,
  1782. int event)
  1783. {
  1784. return __wcd938x_codec_enable_micbias(w, event);
  1785. }
  1786. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1787. int event)
  1788. {
  1789. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1790. int micb_num;
  1791. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1792. __func__, w->name, event);
  1793. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1794. micb_num = MIC_BIAS_1;
  1795. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1796. micb_num = MIC_BIAS_2;
  1797. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1798. micb_num = MIC_BIAS_3;
  1799. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  1800. micb_num = MIC_BIAS_4;
  1801. else
  1802. return -EINVAL;
  1803. switch (event) {
  1804. case SND_SOC_DAPM_PRE_PMU:
  1805. wcd938x_micbias_control(component, micb_num,
  1806. MICB_PULLUP_ENABLE, true);
  1807. break;
  1808. case SND_SOC_DAPM_POST_PMU:
  1809. /* 1 msec delay as per HW requirement */
  1810. usleep_range(1000, 1100);
  1811. break;
  1812. case SND_SOC_DAPM_POST_PMD:
  1813. wcd938x_micbias_control(component, micb_num,
  1814. MICB_PULLUP_DISABLE, true);
  1815. break;
  1816. };
  1817. return 0;
  1818. }
  1819. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1820. struct snd_kcontrol *kcontrol,
  1821. int event)
  1822. {
  1823. return __wcd938x_codec_enable_micbias_pullup(w, event);
  1824. }
  1825. static inline int wcd938x_tx_path_get(const char *wname,
  1826. unsigned int *path_num)
  1827. {
  1828. int ret = 0;
  1829. char *widget_name = NULL;
  1830. char *w_name = NULL;
  1831. char *path_num_char = NULL;
  1832. char *path_name = NULL;
  1833. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  1834. if (!widget_name)
  1835. return -EINVAL;
  1836. w_name = widget_name;
  1837. path_name = strsep(&widget_name, " ");
  1838. if (!path_name) {
  1839. pr_err("%s: Invalid widget name = %s\n",
  1840. __func__, widget_name);
  1841. ret = -EINVAL;
  1842. goto err;
  1843. }
  1844. path_num_char = strpbrk(path_name, "0123");
  1845. if (!path_num_char) {
  1846. pr_err("%s: tx path index not found\n",
  1847. __func__);
  1848. ret = -EINVAL;
  1849. goto err;
  1850. }
  1851. ret = kstrtouint(path_num_char, 10, path_num);
  1852. if (ret < 0)
  1853. pr_err("%s: Invalid tx path = %s\n",
  1854. __func__, w_name);
  1855. err:
  1856. kfree(w_name);
  1857. return ret;
  1858. }
  1859. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  1860. struct snd_ctl_elem_value *ucontrol)
  1861. {
  1862. struct snd_soc_component *component =
  1863. snd_soc_kcontrol_component(kcontrol);
  1864. struct wcd938x_priv *wcd938x = NULL;
  1865. int ret = 0;
  1866. unsigned int path = 0;
  1867. if (!component)
  1868. return -EINVAL;
  1869. wcd938x = snd_soc_component_get_drvdata(component);
  1870. if (!wcd938x)
  1871. return -EINVAL;
  1872. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  1873. if (ret < 0)
  1874. return ret;
  1875. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  1876. return 0;
  1877. }
  1878. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  1879. struct snd_ctl_elem_value *ucontrol)
  1880. {
  1881. struct snd_soc_component *component =
  1882. snd_soc_kcontrol_component(kcontrol);
  1883. struct wcd938x_priv *wcd938x = NULL;
  1884. u32 mode_val;
  1885. unsigned int path = 0;
  1886. int ret = 0;
  1887. if (!component)
  1888. return -EINVAL;
  1889. wcd938x = snd_soc_component_get_drvdata(component);
  1890. if (!wcd938x)
  1891. return -EINVAL;
  1892. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  1893. if (ret)
  1894. return ret;
  1895. mode_val = ucontrol->value.enumerated.item[0];
  1896. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1897. wcd938x->tx_mode[path] = mode_val;
  1898. return 0;
  1899. }
  1900. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1901. struct snd_ctl_elem_value *ucontrol)
  1902. {
  1903. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1904. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1905. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  1906. return 0;
  1907. }
  1908. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1909. struct snd_ctl_elem_value *ucontrol)
  1910. {
  1911. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1912. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1913. u32 mode_val;
  1914. mode_val = ucontrol->value.enumerated.item[0];
  1915. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1916. if (wcd938x->variant == WCD9380) {
  1917. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  1918. dev_info(component->dev,
  1919. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  1920. __func__);
  1921. mode_val = CLS_H_ULP;
  1922. }
  1923. }
  1924. if (mode_val == CLS_H_NORMAL) {
  1925. dev_info(component->dev,
  1926. "%s:Invalid HPH Mode, default to class_AB\n",
  1927. __func__);
  1928. mode_val = CLS_H_ULP;
  1929. }
  1930. wcd938x->hph_mode = mode_val;
  1931. return 0;
  1932. }
  1933. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  1934. struct snd_ctl_elem_value *ucontrol)
  1935. {
  1936. struct snd_soc_component *component =
  1937. snd_soc_kcontrol_component(kcontrol);
  1938. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1939. bool hphr;
  1940. struct soc_multi_mixer_control *mc;
  1941. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1942. hphr = mc->shift;
  1943. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  1944. wcd938x->comp1_enable;
  1945. return 0;
  1946. }
  1947. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  1948. struct snd_ctl_elem_value *ucontrol)
  1949. {
  1950. struct snd_soc_component *component =
  1951. snd_soc_kcontrol_component(kcontrol);
  1952. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1953. int value = ucontrol->value.integer.value[0];
  1954. bool hphr;
  1955. struct soc_multi_mixer_control *mc;
  1956. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1957. hphr = mc->shift;
  1958. if (hphr)
  1959. wcd938x->comp2_enable = value;
  1960. else
  1961. wcd938x->comp1_enable = value;
  1962. return 0;
  1963. }
  1964. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  1965. struct snd_ctl_elem_value *ucontrol)
  1966. {
  1967. struct snd_soc_component *component =
  1968. snd_soc_kcontrol_component(kcontrol);
  1969. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1970. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  1971. return 0;
  1972. }
  1973. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  1974. struct snd_ctl_elem_value *ucontrol)
  1975. {
  1976. struct snd_soc_component *component =
  1977. snd_soc_kcontrol_component(kcontrol);
  1978. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1979. wcd938x->ldoh = ucontrol->value.integer.value[0];
  1980. return 0;
  1981. }
  1982. static const char * const tx_mode_mux_text_wcd9380[] = {
  1983. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  1984. };
  1985. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  1986. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  1987. tx_mode_mux_text_wcd9380);
  1988. static const char * const tx_mode_mux_text[] = {
  1989. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  1990. "ADC_ULP1", "ADC_ULP2",
  1991. };
  1992. static const struct soc_enum tx_mode_mux_enum =
  1993. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  1994. tx_mode_mux_text);
  1995. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  1996. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  1997. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  1998. "CLS_AB_LOHIFI",
  1999. };
  2000. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  2001. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  2002. rx_hph_mode_mux_text_wcd9380);
  2003. static const char * const rx_hph_mode_mux_text[] = {
  2004. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2005. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2006. };
  2007. static const struct soc_enum rx_hph_mode_mux_enum =
  2008. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2009. rx_hph_mode_mux_text);
  2010. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  2011. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  2012. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2013. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  2014. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2015. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  2016. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2017. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  2018. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2019. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  2020. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2021. };
  2022. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  2023. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2024. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2025. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2026. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2027. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2028. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2029. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2030. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2031. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  2032. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2033. };
  2034. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  2035. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2036. wcd938x_get_compander, wcd938x_set_compander),
  2037. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2038. wcd938x_get_compander, wcd938x_set_compander),
  2039. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  2040. wcd938x_ldoh_get, wcd938x_ldoh_put),
  2041. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  2042. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  2043. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  2044. analog_gain),
  2045. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  2046. analog_gain),
  2047. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  2048. analog_gain),
  2049. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  2050. analog_gain),
  2051. };
  2052. static const struct snd_kcontrol_new adc1_switch[] = {
  2053. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2054. };
  2055. static const struct snd_kcontrol_new adc2_switch[] = {
  2056. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2057. };
  2058. static const struct snd_kcontrol_new adc3_switch[] = {
  2059. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2060. };
  2061. static const struct snd_kcontrol_new adc4_switch[] = {
  2062. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2063. };
  2064. static const struct snd_kcontrol_new dmic1_switch[] = {
  2065. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2066. };
  2067. static const struct snd_kcontrol_new dmic2_switch[] = {
  2068. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2069. };
  2070. static const struct snd_kcontrol_new dmic3_switch[] = {
  2071. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2072. };
  2073. static const struct snd_kcontrol_new dmic4_switch[] = {
  2074. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2075. };
  2076. static const struct snd_kcontrol_new dmic5_switch[] = {
  2077. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2078. };
  2079. static const struct snd_kcontrol_new dmic6_switch[] = {
  2080. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2081. };
  2082. static const struct snd_kcontrol_new dmic7_switch[] = {
  2083. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2084. };
  2085. static const struct snd_kcontrol_new dmic8_switch[] = {
  2086. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2087. };
  2088. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2089. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2090. };
  2091. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2092. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2093. };
  2094. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2095. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2096. };
  2097. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2098. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2099. };
  2100. static const char * const adc2_mux_text[] = {
  2101. "INP2", "INP3"
  2102. };
  2103. static const struct soc_enum adc2_enum =
  2104. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2105. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2106. static const struct snd_kcontrol_new tx_adc2_mux =
  2107. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2108. static const char * const adc3_mux_text[] = {
  2109. "INP4", "INP6"
  2110. };
  2111. static const struct soc_enum adc3_enum =
  2112. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2113. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2114. static const struct snd_kcontrol_new tx_adc3_mux =
  2115. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2116. static const char * const adc4_mux_text[] = {
  2117. "INP5", "INP7"
  2118. };
  2119. static const struct soc_enum adc4_enum =
  2120. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2121. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2122. static const struct snd_kcontrol_new tx_adc4_mux =
  2123. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2124. static const char * const rdac3_mux_text[] = {
  2125. "RX1", "RX3"
  2126. };
  2127. static const char * const hdr12_mux_text[] = {
  2128. "NO_HDR12", "HDR12"
  2129. };
  2130. static const struct soc_enum hdr12_enum =
  2131. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2132. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2133. static const struct snd_kcontrol_new tx_hdr12_mux =
  2134. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2135. static const char * const hdr34_mux_text[] = {
  2136. "NO_HDR34", "HDR34"
  2137. };
  2138. static const struct soc_enum hdr34_enum =
  2139. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2140. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2141. static const struct snd_kcontrol_new tx_hdr34_mux =
  2142. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2143. static const struct soc_enum rdac3_enum =
  2144. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2145. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2146. static const struct snd_kcontrol_new rx_rdac3_mux =
  2147. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2148. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2149. /*input widgets*/
  2150. SND_SOC_DAPM_INPUT("AMIC1"),
  2151. SND_SOC_DAPM_INPUT("AMIC2"),
  2152. SND_SOC_DAPM_INPUT("AMIC3"),
  2153. SND_SOC_DAPM_INPUT("AMIC4"),
  2154. SND_SOC_DAPM_INPUT("AMIC5"),
  2155. SND_SOC_DAPM_INPUT("AMIC6"),
  2156. SND_SOC_DAPM_INPUT("AMIC7"),
  2157. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2158. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2159. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2160. /*tx widgets*/
  2161. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2162. wcd938x_codec_enable_adc,
  2163. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2164. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2165. wcd938x_codec_enable_adc,
  2166. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2167. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2168. wcd938x_codec_enable_adc,
  2169. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2170. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  2171. wcd938x_codec_enable_adc,
  2172. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2173. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2174. wcd938x_codec_enable_dmic,
  2175. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2176. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2177. wcd938x_codec_enable_dmic,
  2178. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2179. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2180. wcd938x_codec_enable_dmic,
  2181. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2182. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2183. wcd938x_codec_enable_dmic,
  2184. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2185. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2186. wcd938x_codec_enable_dmic,
  2187. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2188. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2189. wcd938x_codec_enable_dmic,
  2190. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2191. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  2192. wcd938x_codec_enable_dmic,
  2193. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2194. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  2195. wcd938x_codec_enable_dmic,
  2196. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2197. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2198. NULL, 0, wcd938x_enable_req,
  2199. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2200. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  2201. NULL, 0, wcd938x_enable_req,
  2202. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2203. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  2204. NULL, 0, wcd938x_enable_req,
  2205. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2206. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  2207. NULL, 0, wcd938x_enable_req,
  2208. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2209. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2210. &tx_adc2_mux),
  2211. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2212. &tx_adc3_mux),
  2213. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  2214. &tx_adc4_mux),
  2215. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  2216. &tx_hdr12_mux),
  2217. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  2218. &tx_hdr34_mux),
  2219. /*tx mixers*/
  2220. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2221. adc1_switch, ARRAY_SIZE(adc1_switch),
  2222. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2223. SND_SOC_DAPM_POST_PMD),
  2224. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  2225. adc2_switch, ARRAY_SIZE(adc2_switch),
  2226. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2227. SND_SOC_DAPM_POST_PMD),
  2228. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  2229. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  2230. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2231. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
  2232. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  2233. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2234. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2235. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2236. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2237. SND_SOC_DAPM_POST_PMD),
  2238. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  2239. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2240. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2241. SND_SOC_DAPM_POST_PMD),
  2242. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  2243. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2244. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2245. SND_SOC_DAPM_POST_PMD),
  2246. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  2247. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2248. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2249. SND_SOC_DAPM_POST_PMD),
  2250. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  2251. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2252. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2253. SND_SOC_DAPM_POST_PMD),
  2254. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  2255. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2256. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2257. SND_SOC_DAPM_POST_PMD),
  2258. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0,
  2259. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  2260. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2261. SND_SOC_DAPM_POST_PMD),
  2262. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0,
  2263. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  2264. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2265. SND_SOC_DAPM_POST_PMD),
  2266. /* micbias widgets*/
  2267. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2268. wcd938x_codec_enable_micbias,
  2269. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2270. SND_SOC_DAPM_POST_PMD),
  2271. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2272. wcd938x_codec_enable_micbias,
  2273. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2274. SND_SOC_DAPM_POST_PMD),
  2275. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2276. wcd938x_codec_enable_micbias,
  2277. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2278. SND_SOC_DAPM_POST_PMD),
  2279. SND_SOC_DAPM_MICBIAS_E("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2280. wcd938x_codec_enable_micbias,
  2281. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2282. SND_SOC_DAPM_POST_PMD),
  2283. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2284. wcd938x_enable_clsh,
  2285. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2286. /*rx widgets*/
  2287. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  2288. wcd938x_codec_enable_ear_pa,
  2289. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2290. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2291. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  2292. wcd938x_codec_enable_aux_pa,
  2293. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2294. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2295. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  2296. wcd938x_codec_enable_hphl_pa,
  2297. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2298. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2299. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  2300. wcd938x_codec_enable_hphr_pa,
  2301. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2302. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2303. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2304. wcd938x_codec_hphl_dac_event,
  2305. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2306. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2307. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2308. wcd938x_codec_hphr_dac_event,
  2309. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2310. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2311. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2312. wcd938x_codec_ear_dac_event,
  2313. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2314. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2315. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2316. wcd938x_codec_aux_dac_event,
  2317. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2318. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2319. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2320. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2321. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2322. SND_SOC_DAPM_POST_PMD),
  2323. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2324. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2325. SND_SOC_DAPM_POST_PMD),
  2326. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2327. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2328. SND_SOC_DAPM_POST_PMD),
  2329. /* rx mixer widgets*/
  2330. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2331. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2332. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2333. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2334. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2335. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2336. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2337. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2338. /*output widgets tx*/
  2339. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  2340. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  2341. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  2342. SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
  2343. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  2344. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  2345. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  2346. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  2347. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  2348. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  2349. SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
  2350. SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
  2351. /*output widgets rx*/
  2352. SND_SOC_DAPM_OUTPUT("EAR"),
  2353. SND_SOC_DAPM_OUTPUT("AUX"),
  2354. SND_SOC_DAPM_OUTPUT("HPHL"),
  2355. SND_SOC_DAPM_OUTPUT("HPHR"),
  2356. /* micbias pull up widgets*/
  2357. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2358. wcd938x_codec_enable_micbias_pullup,
  2359. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2360. SND_SOC_DAPM_POST_PMD),
  2361. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2362. wcd938x_codec_enable_micbias_pullup,
  2363. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2364. SND_SOC_DAPM_POST_PMD),
  2365. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2366. wcd938x_codec_enable_micbias_pullup,
  2367. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2368. SND_SOC_DAPM_POST_PMD),
  2369. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2370. wcd938x_codec_enable_micbias_pullup,
  2371. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2372. SND_SOC_DAPM_POST_PMD),
  2373. };
  2374. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  2375. {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
  2376. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2377. {"ADC1 REQ", NULL, "ADC1"},
  2378. {"ADC1", NULL, "AMIC1"},
  2379. {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
  2380. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2381. {"ADC2 REQ", NULL, "ADC2"},
  2382. {"ADC2", NULL, "HDR12 MUX"},
  2383. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  2384. {"HDR12 MUX", "HDR12", "AMIC1"},
  2385. {"ADC2 MUX", "INP3", "AMIC3"},
  2386. {"ADC2 MUX", "INP2", "AMIC2"},
  2387. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  2388. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2389. {"ADC3 REQ", NULL, "ADC3"},
  2390. {"ADC3", NULL, "HDR34 MUX"},
  2391. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  2392. {"HDR34 MUX", "HDR34", "AMIC5"},
  2393. {"ADC3 MUX", "INP4", "AMIC4"},
  2394. {"ADC3 MUX", "INP6", "AMIC6"},
  2395. {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
  2396. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  2397. {"ADC4 REQ", NULL, "ADC4"},
  2398. {"ADC4", NULL, "ADC4 MUX"},
  2399. {"ADC4 MUX", "INP5", "AMIC5"},
  2400. {"ADC4 MUX", "INP7", "AMIC7"},
  2401. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  2402. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2403. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  2404. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2405. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  2406. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2407. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  2408. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2409. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  2410. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2411. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  2412. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2413. {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
  2414. {"DMIC7_MIXER", "Switch", "DMIC7"},
  2415. {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
  2416. {"DMIC8_MIXER", "Switch", "DMIC8"},
  2417. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2418. {"RX1", NULL, "IN1_HPHL"},
  2419. {"RDAC1", NULL, "RX1"},
  2420. {"HPHL_RDAC", "Switch", "RDAC1"},
  2421. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2422. {"HPHL", NULL, "HPHL PGA"},
  2423. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2424. {"RX2", NULL, "IN2_HPHR"},
  2425. {"RDAC2", NULL, "RX2"},
  2426. {"HPHR_RDAC", "Switch", "RDAC2"},
  2427. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2428. {"HPHR", NULL, "HPHR PGA"},
  2429. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2430. {"RX3", NULL, "IN3_AUX"},
  2431. {"RDAC4", NULL, "RX3"},
  2432. {"AUX_RDAC", "Switch", "RDAC4"},
  2433. {"AUX PGA", NULL, "AUX_RDAC"},
  2434. {"AUX", NULL, "AUX PGA"},
  2435. {"RDAC3_MUX", "RX3", "RX3"},
  2436. {"RDAC3_MUX", "RX1", "RX1"},
  2437. {"RDAC3", NULL, "RDAC3_MUX"},
  2438. {"EAR_RDAC", "Switch", "RDAC3"},
  2439. {"EAR PGA", NULL, "EAR_RDAC"},
  2440. {"EAR", NULL, "EAR PGA"},
  2441. };
  2442. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  2443. void *file_private_data,
  2444. struct file *file,
  2445. char __user *buf, size_t count,
  2446. loff_t pos)
  2447. {
  2448. struct wcd938x_priv *priv;
  2449. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  2450. int len = 0;
  2451. priv = (struct wcd938x_priv *) entry->private_data;
  2452. if (!priv) {
  2453. pr_err("%s: wcd938x priv is null\n", __func__);
  2454. return -EINVAL;
  2455. }
  2456. switch (priv->version) {
  2457. case WCD938X_VERSION_1_0:
  2458. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  2459. break;
  2460. default:
  2461. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2462. }
  2463. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2464. }
  2465. static struct snd_info_entry_ops wcd938x_info_ops = {
  2466. .read = wcd938x_version_read,
  2467. };
  2468. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  2469. void *file_private_data,
  2470. struct file *file,
  2471. char __user *buf, size_t count,
  2472. loff_t pos)
  2473. {
  2474. struct wcd938x_priv *priv;
  2475. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  2476. int len = 0;
  2477. priv = (struct wcd938x_priv *) entry->private_data;
  2478. if (!priv) {
  2479. pr_err("%s: wcd938x priv is null\n", __func__);
  2480. return -EINVAL;
  2481. }
  2482. switch (priv->variant) {
  2483. case WCD9380:
  2484. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  2485. break;
  2486. case WCD9385:
  2487. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  2488. break;
  2489. default:
  2490. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2491. }
  2492. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2493. }
  2494. static struct snd_info_entry_ops wcd938x_variant_ops = {
  2495. .read = wcd938x_variant_read,
  2496. };
  2497. /*
  2498. * wcd938x_get_codec_variant
  2499. * @component: component instance
  2500. *
  2501. * Return: codec variant or -EINVAL in error.
  2502. */
  2503. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  2504. {
  2505. struct wcd938x_priv *priv = NULL;
  2506. if (!component)
  2507. return -EINVAL;
  2508. priv = snd_soc_component_get_drvdata(component);
  2509. if (!priv) {
  2510. dev_err(component->dev,
  2511. "%s:wcd938x not probed\n", __func__);
  2512. return 0;
  2513. }
  2514. return priv->variant;
  2515. }
  2516. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  2517. /*
  2518. * wcd938x_info_create_codec_entry - creates wcd938x module
  2519. * @codec_root: The parent directory
  2520. * @component: component instance
  2521. *
  2522. * Creates wcd938x module, variant and version entry under the given
  2523. * parent directory.
  2524. *
  2525. * Return: 0 on success or negative error code on failure.
  2526. */
  2527. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2528. struct snd_soc_component *component)
  2529. {
  2530. struct snd_info_entry *version_entry;
  2531. struct snd_info_entry *variant_entry;
  2532. struct wcd938x_priv *priv;
  2533. struct snd_soc_card *card;
  2534. if (!codec_root || !component)
  2535. return -EINVAL;
  2536. priv = snd_soc_component_get_drvdata(component);
  2537. if (priv->entry) {
  2538. dev_dbg(priv->dev,
  2539. "%s:wcd938x module already created\n", __func__);
  2540. return 0;
  2541. }
  2542. card = component->card;
  2543. priv->entry = snd_info_create_subdir(codec_root->module,
  2544. "wcd938x", codec_root);
  2545. if (!priv->entry) {
  2546. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  2547. __func__);
  2548. return -ENOMEM;
  2549. }
  2550. version_entry = snd_info_create_card_entry(card->snd_card,
  2551. "version",
  2552. priv->entry);
  2553. if (!version_entry) {
  2554. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  2555. __func__);
  2556. return -ENOMEM;
  2557. }
  2558. version_entry->private_data = priv;
  2559. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  2560. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2561. version_entry->c.ops = &wcd938x_info_ops;
  2562. if (snd_info_register(version_entry) < 0) {
  2563. snd_info_free_entry(version_entry);
  2564. return -ENOMEM;
  2565. }
  2566. priv->version_entry = version_entry;
  2567. variant_entry = snd_info_create_card_entry(card->snd_card,
  2568. "variant",
  2569. priv->entry);
  2570. if (!variant_entry) {
  2571. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  2572. __func__);
  2573. return -ENOMEM;
  2574. }
  2575. variant_entry->private_data = priv;
  2576. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  2577. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2578. variant_entry->c.ops = &wcd938x_variant_ops;
  2579. if (snd_info_register(variant_entry) < 0) {
  2580. snd_info_free_entry(variant_entry);
  2581. return -ENOMEM;
  2582. }
  2583. priv->variant_entry = variant_entry;
  2584. return 0;
  2585. }
  2586. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  2587. static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x,
  2588. struct wcd938x_pdata *pdata)
  2589. {
  2590. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  2591. int rc = 0;
  2592. if (!pdata) {
  2593. dev_err(wcd938x->dev, "%s: NULL pdata\n", __func__);
  2594. return -ENODEV;
  2595. }
  2596. /* set micbias voltage */
  2597. vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2598. vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2599. vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2600. vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  2601. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  2602. vout_ctl_4 < 0) {
  2603. rc = -EINVAL;
  2604. goto done;
  2605. }
  2606. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 0x3F,
  2607. vout_ctl_1);
  2608. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 0x3F,
  2609. vout_ctl_2);
  2610. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 0x3F,
  2611. vout_ctl_3);
  2612. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 0x3F,
  2613. vout_ctl_4);
  2614. done:
  2615. return rc;
  2616. }
  2617. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  2618. {
  2619. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2620. struct snd_soc_dapm_context *dapm =
  2621. snd_soc_component_get_dapm(component);
  2622. int variant;
  2623. int ret = -EINVAL;
  2624. dev_info(component->dev, "%s()\n", __func__);
  2625. wcd938x = snd_soc_component_get_drvdata(component);
  2626. if (!wcd938x)
  2627. return -EINVAL;
  2628. wcd938x->component = component;
  2629. snd_soc_component_init_regmap(component, wcd938x->regmap);
  2630. variant = (snd_soc_component_read32(component,
  2631. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2632. wcd938x->variant = variant;
  2633. wcd938x->fw_data = devm_kzalloc(component->dev,
  2634. sizeof(*(wcd938x->fw_data)),
  2635. GFP_KERNEL);
  2636. if (!wcd938x->fw_data) {
  2637. dev_err(component->dev, "Failed to allocate fw_data\n");
  2638. ret = -ENOMEM;
  2639. goto err;
  2640. }
  2641. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  2642. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  2643. WCD9XXX_CODEC_HWDEP_NODE, component);
  2644. if (ret < 0) {
  2645. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2646. goto err_hwdep;
  2647. }
  2648. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  2649. if (ret) {
  2650. pr_err("%s: mbhc initialization failed\n", __func__);
  2651. goto err_hwdep;
  2652. }
  2653. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2654. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2655. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2656. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2657. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  2658. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  2659. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  2660. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2661. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2662. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2663. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2664. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2665. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2666. snd_soc_dapm_ignore_suspend(dapm, "DMIC7_OUTPUT");
  2667. snd_soc_dapm_ignore_suspend(dapm, "DMIC8_OUTPUT");
  2668. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2669. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2670. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2671. snd_soc_dapm_ignore_suspend(dapm, "ADC4_OUTPUT");
  2672. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2673. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2674. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2675. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2676. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2677. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2678. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2679. snd_soc_dapm_sync(dapm);
  2680. wcd_cls_h_init(&wcd938x->clsh_info);
  2681. wcd938x_init_reg(component);
  2682. if (wcd938x->variant == WCD9380) {
  2683. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  2684. ARRAY_SIZE(wcd9380_snd_controls));
  2685. if (ret < 0) {
  2686. dev_err(component->dev,
  2687. "%s: Failed to add snd ctrls for variant: %d\n",
  2688. __func__, wcd938x->variant);
  2689. goto err_hwdep;
  2690. }
  2691. }
  2692. if (wcd938x->variant == WCD9385) {
  2693. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  2694. ARRAY_SIZE(wcd9385_snd_controls));
  2695. if (ret < 0) {
  2696. dev_err(component->dev,
  2697. "%s: Failed to add snd ctrls for variant: %d\n",
  2698. __func__, wcd938x->variant);
  2699. goto err_hwdep;
  2700. }
  2701. }
  2702. wcd938x->version = WCD938X_VERSION_1_0;
  2703. /* Register event notifier */
  2704. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  2705. if (wcd938x->register_notifier) {
  2706. ret = wcd938x->register_notifier(wcd938x->handle,
  2707. &wcd938x->nblock,
  2708. true);
  2709. if (ret) {
  2710. dev_err(component->dev,
  2711. "%s: Failed to register notifier %d\n",
  2712. __func__, ret);
  2713. return ret;
  2714. }
  2715. }
  2716. wcd938x->dev_up = true;
  2717. return ret;
  2718. err_hwdep:
  2719. wcd938x->fw_data = NULL;
  2720. err:
  2721. return ret;
  2722. }
  2723. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  2724. {
  2725. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2726. if (!wcd938x) {
  2727. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  2728. __func__);
  2729. return;
  2730. }
  2731. if (wcd938x->register_notifier)
  2732. wcd938x->register_notifier(wcd938x->handle,
  2733. &wcd938x->nblock,
  2734. false);
  2735. }
  2736. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  2737. .name = WCD938X_DRV_NAME,
  2738. .probe = wcd938x_soc_codec_probe,
  2739. .remove = wcd938x_soc_codec_remove,
  2740. .controls = wcd938x_snd_controls,
  2741. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  2742. .dapm_widgets = wcd938x_dapm_widgets,
  2743. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  2744. .dapm_routes = wcd938x_audio_map,
  2745. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  2746. };
  2747. static int wcd938x_reset(struct device *dev)
  2748. {
  2749. struct wcd938x_priv *wcd938x = NULL;
  2750. int rc = 0;
  2751. int value = 0;
  2752. if (!dev)
  2753. return -ENODEV;
  2754. wcd938x = dev_get_drvdata(dev);
  2755. if (!wcd938x)
  2756. return -EINVAL;
  2757. if (!wcd938x->rst_np) {
  2758. dev_err(dev, "%s: reset gpio device node not specified\n",
  2759. __func__);
  2760. return -EINVAL;
  2761. }
  2762. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  2763. if (value > 0)
  2764. return 0;
  2765. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2766. if (rc) {
  2767. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2768. __func__);
  2769. return rc;
  2770. }
  2771. /* 20us sleep required after pulling the reset gpio to LOW */
  2772. usleep_range(20, 30);
  2773. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  2774. if (rc) {
  2775. dev_err(dev, "%s: wcd active state request fail!\n",
  2776. __func__);
  2777. return rc;
  2778. }
  2779. /* 20us sleep required after pulling the reset gpio to HIGH */
  2780. usleep_range(20, 30);
  2781. return rc;
  2782. }
  2783. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  2784. u32 *val)
  2785. {
  2786. int rc = 0;
  2787. rc = of_property_read_u32(dev->of_node, name, val);
  2788. if (rc)
  2789. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2790. __func__, name, dev->of_node->full_name);
  2791. return rc;
  2792. }
  2793. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  2794. struct wcd938x_micbias_setting *mb)
  2795. {
  2796. u32 prop_val = 0;
  2797. int rc = 0;
  2798. /* MB1 */
  2799. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2800. NULL)) {
  2801. rc = wcd938x_read_of_property_u32(dev,
  2802. "qcom,cdc-micbias1-mv",
  2803. &prop_val);
  2804. if (!rc)
  2805. mb->micb1_mv = prop_val;
  2806. } else {
  2807. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2808. __func__);
  2809. }
  2810. /* MB2 */
  2811. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2812. NULL)) {
  2813. rc = wcd938x_read_of_property_u32(dev,
  2814. "qcom,cdc-micbias2-mv",
  2815. &prop_val);
  2816. if (!rc)
  2817. mb->micb2_mv = prop_val;
  2818. } else {
  2819. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2820. __func__);
  2821. }
  2822. /* MB3 */
  2823. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2824. NULL)) {
  2825. rc = wcd938x_read_of_property_u32(dev,
  2826. "qcom,cdc-micbias3-mv",
  2827. &prop_val);
  2828. if (!rc)
  2829. mb->micb3_mv = prop_val;
  2830. } else {
  2831. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2832. __func__);
  2833. }
  2834. /* MB4 */
  2835. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  2836. NULL)) {
  2837. rc = wcd938x_read_of_property_u32(dev,
  2838. "qcom,cdc-micbias4-mv",
  2839. &prop_val);
  2840. if (!rc)
  2841. mb->micb4_mv = prop_val;
  2842. } else {
  2843. dev_info(dev, "%s: Micbias4 DT property not found\n",
  2844. __func__);
  2845. }
  2846. }
  2847. static int wcd938x_reset_low(struct device *dev)
  2848. {
  2849. struct wcd938x_priv *wcd938x = NULL;
  2850. int rc = 0;
  2851. if (!dev)
  2852. return -ENODEV;
  2853. wcd938x = dev_get_drvdata(dev);
  2854. if (!wcd938x)
  2855. return -EINVAL;
  2856. if (!wcd938x->rst_np) {
  2857. dev_err(dev, "%s: reset gpio device node not specified\n",
  2858. __func__);
  2859. return -EINVAL;
  2860. }
  2861. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2862. if (rc) {
  2863. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2864. __func__);
  2865. return rc;
  2866. }
  2867. /* 20us sleep required after pulling the reset gpio to LOW */
  2868. usleep_range(20, 30);
  2869. return rc;
  2870. }
  2871. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  2872. {
  2873. struct wcd938x_pdata *pdata = NULL;
  2874. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  2875. GFP_KERNEL);
  2876. if (!pdata)
  2877. return NULL;
  2878. pdata->rst_np = of_parse_phandle(dev->of_node,
  2879. "qcom,wcd-rst-gpio-node", 0);
  2880. if (!pdata->rst_np) {
  2881. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2882. __func__, "qcom,wcd-rst-gpio-node",
  2883. dev->of_node->full_name);
  2884. return NULL;
  2885. }
  2886. /* Parse power supplies */
  2887. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2888. &pdata->num_supplies);
  2889. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2890. dev_err(dev, "%s: no power supplies defined for codec\n",
  2891. __func__);
  2892. return NULL;
  2893. }
  2894. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2895. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2896. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  2897. return pdata;
  2898. }
  2899. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  2900. {
  2901. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2902. __func__, irq);
  2903. return IRQ_HANDLED;
  2904. }
  2905. static int wcd938x_bind(struct device *dev)
  2906. {
  2907. int ret = 0, i = 0;
  2908. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  2909. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2910. /*
  2911. * Add 5msec delay to provide sufficient time for
  2912. * soundwire auto enumeration of slave devices as
  2913. * as per HW requirement.
  2914. */
  2915. usleep_range(5000, 5010);
  2916. ret = component_bind_all(dev, wcd938x);
  2917. if (ret) {
  2918. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2919. __func__, ret);
  2920. return ret;
  2921. }
  2922. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2923. if (!wcd938x->rx_swr_dev) {
  2924. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2925. __func__);
  2926. ret = -ENODEV;
  2927. goto err;
  2928. }
  2929. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2930. if (!wcd938x->tx_swr_dev) {
  2931. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2932. __func__);
  2933. ret = -ENODEV;
  2934. goto err;
  2935. }
  2936. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  2937. &wcd938x_regmap_config);
  2938. if (!wcd938x->regmap) {
  2939. dev_err(dev, "%s: Regmap init failed\n",
  2940. __func__);
  2941. goto err;
  2942. }
  2943. /* Set all interupts as edge triggered */
  2944. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  2945. regmap_write(wcd938x->regmap,
  2946. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2947. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  2948. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  2949. wcd938x->irq_info.codec_name = "WCD938X";
  2950. wcd938x->irq_info.regmap = wcd938x->regmap;
  2951. wcd938x->irq_info.dev = dev;
  2952. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  2953. if (ret) {
  2954. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  2955. __func__, ret);
  2956. goto err;
  2957. }
  2958. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  2959. ret = wcd938x_set_micbias_data(wcd938x, pdata);
  2960. if (ret < 0) {
  2961. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  2962. goto err_irq;
  2963. }
  2964. /* Request for watchdog interrupt */
  2965. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  2966. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  2967. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  2968. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  2969. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  2970. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  2971. /* Disable watchdog interrupt for HPH and AUX */
  2972. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  2973. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  2974. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  2975. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  2976. NULL, 0);
  2977. if (ret) {
  2978. dev_err(dev, "%s: Codec registration failed\n",
  2979. __func__);
  2980. goto err_irq;
  2981. }
  2982. return ret;
  2983. err_irq:
  2984. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2985. err:
  2986. component_unbind_all(dev, wcd938x);
  2987. return ret;
  2988. }
  2989. static void wcd938x_unbind(struct device *dev)
  2990. {
  2991. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2992. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  2993. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  2994. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  2995. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2996. snd_soc_unregister_component(dev);
  2997. component_unbind_all(dev, wcd938x);
  2998. }
  2999. static const struct of_device_id wcd938x_dt_match[] = {
  3000. { .compatible = "qcom,wcd938x-codec" },
  3001. {}
  3002. };
  3003. static const struct component_master_ops wcd938x_comp_ops = {
  3004. .bind = wcd938x_bind,
  3005. .unbind = wcd938x_unbind,
  3006. };
  3007. static int wcd938x_compare_of(struct device *dev, void *data)
  3008. {
  3009. return dev->of_node == data;
  3010. }
  3011. static void wcd938x_release_of(struct device *dev, void *data)
  3012. {
  3013. of_node_put(data);
  3014. }
  3015. static int wcd938x_add_slave_components(struct device *dev,
  3016. struct component_match **matchptr)
  3017. {
  3018. struct device_node *np, *rx_node, *tx_node;
  3019. np = dev->of_node;
  3020. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3021. if (!rx_node) {
  3022. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3023. return -ENODEV;
  3024. }
  3025. of_node_get(rx_node);
  3026. component_match_add_release(dev, matchptr,
  3027. wcd938x_release_of,
  3028. wcd938x_compare_of,
  3029. rx_node);
  3030. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3031. if (!tx_node) {
  3032. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3033. return -ENODEV;
  3034. }
  3035. of_node_get(tx_node);
  3036. component_match_add_release(dev, matchptr,
  3037. wcd938x_release_of,
  3038. wcd938x_compare_of,
  3039. tx_node);
  3040. return 0;
  3041. }
  3042. static int wcd938x_wakeup(void *handle, bool enable)
  3043. {
  3044. struct wcd938x_priv *priv;
  3045. if (!handle) {
  3046. pr_err("%s: NULL handle\n", __func__);
  3047. return -EINVAL;
  3048. }
  3049. priv = (struct wcd938x_priv *)handle;
  3050. if (!priv->tx_swr_dev) {
  3051. pr_err("%s: tx swr dev is NULL\n", __func__);
  3052. return -EINVAL;
  3053. }
  3054. if (enable)
  3055. return swr_device_wakeup_vote(priv->tx_swr_dev);
  3056. else
  3057. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  3058. }
  3059. static int wcd938x_probe(struct platform_device *pdev)
  3060. {
  3061. struct component_match *match = NULL;
  3062. struct wcd938x_priv *wcd938x = NULL;
  3063. struct wcd938x_pdata *pdata = NULL;
  3064. struct wcd_ctrl_platform_data *plat_data = NULL;
  3065. struct device *dev = &pdev->dev;
  3066. int ret;
  3067. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  3068. GFP_KERNEL);
  3069. if (!wcd938x)
  3070. return -ENOMEM;
  3071. dev_set_drvdata(dev, wcd938x);
  3072. wcd938x->dev = dev;
  3073. pdata = wcd938x_populate_dt_data(dev);
  3074. if (!pdata) {
  3075. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3076. return -EINVAL;
  3077. }
  3078. dev->platform_data = pdata;
  3079. wcd938x->rst_np = pdata->rst_np;
  3080. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  3081. pdata->regulator, pdata->num_supplies);
  3082. if (!wcd938x->supplies) {
  3083. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3084. __func__);
  3085. return ret;
  3086. }
  3087. plat_data = dev_get_platdata(dev->parent);
  3088. if (!plat_data) {
  3089. dev_err(dev, "%s: platform data from parent is NULL\n",
  3090. __func__);
  3091. return -EINVAL;
  3092. }
  3093. wcd938x->handle = (void *)plat_data->handle;
  3094. if (!wcd938x->handle) {
  3095. dev_err(dev, "%s: handle is NULL\n", __func__);
  3096. return -EINVAL;
  3097. }
  3098. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  3099. if (!wcd938x->update_wcd_event) {
  3100. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3101. __func__);
  3102. return -EINVAL;
  3103. }
  3104. wcd938x->register_notifier = plat_data->register_notifier;
  3105. if (!wcd938x->register_notifier) {
  3106. dev_err(dev, "%s: register_notifier api is null!\n",
  3107. __func__);
  3108. return -EINVAL;
  3109. }
  3110. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  3111. pdata->regulator,
  3112. pdata->num_supplies);
  3113. if (ret) {
  3114. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3115. __func__);
  3116. return ret;
  3117. }
  3118. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3119. CODEC_RX);
  3120. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3121. CODEC_TX);
  3122. if (ret) {
  3123. dev_err(dev, "Failed to read port mapping\n");
  3124. goto err;
  3125. }
  3126. mutex_init(&wcd938x->micb_lock);
  3127. ret = wcd938x_add_slave_components(dev, &match);
  3128. if (ret)
  3129. goto err_lock_init;
  3130. wcd938x_reset(dev);
  3131. wcd938x->wakeup = wcd938x_wakeup;
  3132. return component_master_add_with_match(dev,
  3133. &wcd938x_comp_ops, match);
  3134. err_lock_init:
  3135. mutex_destroy(&wcd938x->micb_lock);
  3136. err:
  3137. return ret;
  3138. }
  3139. static int wcd938x_remove(struct platform_device *pdev)
  3140. {
  3141. struct wcd938x_priv *wcd938x = NULL;
  3142. wcd938x = platform_get_drvdata(pdev);
  3143. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  3144. mutex_destroy(&wcd938x->micb_lock);
  3145. dev_set_drvdata(&pdev->dev, NULL);
  3146. return 0;
  3147. }
  3148. #ifdef CONFIG_PM_SLEEP
  3149. static int wcd938x_suspend(struct device *dev)
  3150. {
  3151. return 0;
  3152. }
  3153. static int wcd938x_resume(struct device *dev)
  3154. {
  3155. return 0;
  3156. }
  3157. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  3158. SET_SYSTEM_SLEEP_PM_OPS(
  3159. wcd938x_suspend,
  3160. wcd938x_resume
  3161. )
  3162. };
  3163. #endif
  3164. static struct platform_driver wcd938x_codec_driver = {
  3165. .probe = wcd938x_probe,
  3166. .remove = wcd938x_remove,
  3167. .driver = {
  3168. .name = "wcd938x_codec",
  3169. .owner = THIS_MODULE,
  3170. .of_match_table = of_match_ptr(wcd938x_dt_match),
  3171. #ifdef CONFIG_PM_SLEEP
  3172. .pm = &wcd938x_dev_pm_ops,
  3173. #endif
  3174. .suppress_bind_attrs = true,
  3175. },
  3176. };
  3177. module_platform_driver(wcd938x_codec_driver);
  3178. MODULE_DESCRIPTION("WCD938X Codec driver");
  3179. MODULE_LICENSE("GPL v2");