wcd938x.c 101 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "internal.h"
  23. #include "wcd938x-registers.h"
  24. #include "wcd938x.h"
  25. #define WCD938X_DRV_NAME "wcd938x_codec"
  26. #define NUM_SWRS_DT_PARAMS 5
  27. #define WCD938X_VARIANT_ENTRY_SIZE 32
  28. #define WCD938X_VERSION_1_0 1
  29. #define WCD938X_VERSION_ENTRY_SIZE 32
  30. #define EAR_RX_PATH_AUX 1
  31. #define ADC_MODE_VAL_HIFI 0x01
  32. #define ADC_MODE_VAL_LO_HIF 0x02
  33. #define ADC_MODE_VAL_NORMAL 0x03
  34. #define ADC_MODE_VAL_LP 0x05
  35. #define ADC_MODE_VAL_ULP1 0x09
  36. #define ADC_MODE_VAL_ULP2 0x0B
  37. enum {
  38. CODEC_TX = 0,
  39. CODEC_RX,
  40. };
  41. enum {
  42. WCD_ADC1 = 0,
  43. WCD_ADC2,
  44. WCD_ADC3,
  45. WCD_ADC4,
  46. ALLOW_BUCK_DISABLE,
  47. HPH_COMP_DELAY,
  48. HPH_PA_DELAY,
  49. AMIC2_BCS_ENABLE,
  50. };
  51. enum {
  52. ADC_MODE_INVALID = 0,
  53. ADC_MODE_HIFI,
  54. ADC_MODE_LO_HIF,
  55. ADC_MODE_NORMAL,
  56. ADC_MODE_LP,
  57. ADC_MODE_ULP1,
  58. ADC_MODE_ULP2,
  59. };
  60. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  61. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  62. static int wcd938x_handle_post_irq(void *data);
  63. static int wcd938x_reset(struct device *dev);
  64. static int wcd938x_reset_low(struct device *dev);
  65. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  66. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  67. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  68. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  69. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  70. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  71. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  72. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  73. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  74. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  75. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  76. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  77. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  78. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  79. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  80. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  81. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  82. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  83. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  84. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  85. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  86. };
  87. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  88. .name = "wcd938x",
  89. .irqs = wcd938x_irqs,
  90. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  91. .num_regs = 3,
  92. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  93. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  94. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  95. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  96. .use_ack = 1,
  97. .runtime_pm = false,
  98. .handle_post_irq = wcd938x_handle_post_irq,
  99. .irq_drv_data = NULL,
  100. };
  101. static int wcd938x_handle_post_irq(void *data)
  102. {
  103. struct wcd938x_priv *wcd938x = data;
  104. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  105. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  106. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  107. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  108. wcd938x->tx_swr_dev->slave_irq_pending =
  109. ((sts1 || sts2 || sts3) ? true : false);
  110. return IRQ_HANDLED;
  111. }
  112. static int wcd938x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  113. {
  114. int ret = 0;
  115. int bank = 0;
  116. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  117. if (ret)
  118. return -EINVAL;
  119. return ((bank & 0x40) ? 1: 0);
  120. }
  121. static int wcd938x_swr_slv_set_host_clk_div2(struct swr_device *dev,
  122. u8 devnum, int bank)
  123. {
  124. u8 val = (bank ? 1 : 0);
  125. return (swr_write(dev, devnum,
  126. (SWR_SCP_HOST_CLK_DIV2_CTL_BANK + (0x10 * bank)), &val));
  127. }
  128. static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
  129. int mode, int bank)
  130. {
  131. u8 mask = (bank ? 0xF0 : 0x0F);
  132. u8 val = 0;
  133. if ((mode == ADC_MODE_ULP1) || (mode == ADC_MODE_ULP2))
  134. val = (bank ? 0x60 : 0x06);
  135. else
  136. val = 0x00;
  137. snd_soc_component_update_bits(component,
  138. WCD938X_DIGITAL_SWR_TX_CLK_RATE,
  139. mask, val);
  140. return 0;
  141. }
  142. static int wcd938x_init_reg(struct snd_soc_component *component)
  143. {
  144. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  145. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  146. /* 1 msec delay as per HW requirement */
  147. usleep_range(1000, 1010);
  148. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  149. /* 1 msec delay as per HW requirement */
  150. usleep_range(1000, 1010);
  151. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  152. 0x10, 0x00);
  153. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  154. 0xF0, 0x80);
  155. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  156. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  157. /* 10 msec delay as per HW requirement */
  158. usleep_range(10000, 10010);
  159. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  160. snd_soc_component_update_bits(component,
  161. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  162. 0xF0, 0x00);
  163. snd_soc_component_update_bits(component,
  164. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  165. 0x1F, 0x15);
  166. snd_soc_component_update_bits(component,
  167. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  168. 0x1F, 0x15);
  169. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  170. 0xC0, 0x80);
  171. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  172. 0x02, 0x02);
  173. snd_soc_component_update_bits(component,
  174. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  175. 0xFF, 0x14);
  176. snd_soc_component_update_bits(component,
  177. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  178. 0x1F, 0x08);
  179. snd_soc_component_update_bits(component,
  180. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  181. snd_soc_component_update_bits(component,
  182. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  183. snd_soc_component_update_bits(component,
  184. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  185. snd_soc_component_update_bits(component,
  186. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  187. snd_soc_component_update_bits(component,
  188. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  189. snd_soc_component_update_bits(component,
  190. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  191. snd_soc_component_update_bits(component,
  192. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  193. snd_soc_component_update_bits(component,
  194. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  195. snd_soc_component_update_bits(component,
  196. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  197. return 0;
  198. }
  199. static int wcd938x_set_port_params(struct snd_soc_component *component,
  200. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  201. u8 *ch_mask, u32 *ch_rate,
  202. u8 *port_type, u8 path)
  203. {
  204. int i, j;
  205. u8 num_ports = 0;
  206. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  207. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  208. switch (path) {
  209. case CODEC_RX:
  210. map = &wcd938x->rx_port_mapping;
  211. num_ports = wcd938x->num_rx_ports;
  212. break;
  213. case CODEC_TX:
  214. map = &wcd938x->tx_port_mapping;
  215. num_ports = wcd938x->num_tx_ports;
  216. break;
  217. default:
  218. dev_err(component->dev, "%s Invalid path selected %u\n",
  219. __func__, path);
  220. return -EINVAL;
  221. }
  222. for (i = 0; i <= num_ports; i++) {
  223. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  224. if ((*map)[i][j].slave_port_type == slv_prt_type)
  225. goto found;
  226. }
  227. }
  228. found:
  229. if (i > num_ports || j == MAX_CH_PER_PORT) {
  230. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  231. __func__, slv_prt_type);
  232. return -EINVAL;
  233. }
  234. *port_id = i;
  235. *num_ch = (*map)[i][j].num_ch;
  236. *ch_mask = (*map)[i][j].ch_mask;
  237. *ch_rate = (*map)[i][j].ch_rate;
  238. *port_type = (*map)[i][j].master_port_type;
  239. return 0;
  240. }
  241. static int wcd938x_parse_port_mapping(struct device *dev,
  242. char *prop, u8 path)
  243. {
  244. u32 *dt_array, map_size, map_length;
  245. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  246. u32 slave_port_type, master_port_type;
  247. u32 i, ch_iter = 0;
  248. int ret = 0;
  249. u8 *num_ports = NULL;
  250. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  251. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  252. switch (path) {
  253. case CODEC_RX:
  254. map = &wcd938x->rx_port_mapping;
  255. num_ports = &wcd938x->num_rx_ports;
  256. break;
  257. case CODEC_TX:
  258. map = &wcd938x->tx_port_mapping;
  259. num_ports = &wcd938x->num_tx_ports;
  260. break;
  261. default:
  262. dev_err(dev, "%s Invalid path selected %u\n",
  263. __func__, path);
  264. return -EINVAL;
  265. }
  266. if (!of_find_property(dev->of_node, prop,
  267. &map_size)) {
  268. dev_err(dev, "missing port mapping prop %s\n", prop);
  269. ret = -EINVAL;
  270. goto err_port_map;
  271. }
  272. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  273. dt_array = kzalloc(map_size, GFP_KERNEL);
  274. if (!dt_array) {
  275. ret = -ENOMEM;
  276. goto err_alloc;
  277. }
  278. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  279. NUM_SWRS_DT_PARAMS * map_length);
  280. if (ret) {
  281. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  282. __func__, prop);
  283. goto err_pdata_fail;
  284. }
  285. for (i = 0; i < map_length; i++) {
  286. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  287. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  288. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  289. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  290. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  291. if (port_num != old_port_num)
  292. ch_iter = 0;
  293. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  294. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  295. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  296. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  297. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  298. old_port_num = port_num;
  299. }
  300. *num_ports = port_num;
  301. kfree(dt_array);
  302. return 0;
  303. err_pdata_fail:
  304. kfree(dt_array);
  305. err_alloc:
  306. err_port_map:
  307. return ret;
  308. }
  309. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  310. u8 slv_port_type, u8 enable)
  311. {
  312. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  313. u8 port_id, num_ch, ch_mask, port_type;
  314. u32 ch_rate;
  315. u8 num_port = 1;
  316. int ret = 0;
  317. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  318. &num_ch, &ch_mask, &ch_rate,
  319. &port_type, CODEC_TX);
  320. if (ret)
  321. return ret;
  322. if (enable)
  323. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  324. num_port, &ch_mask, &ch_rate,
  325. &num_ch, &port_type);
  326. else
  327. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  328. num_port, &ch_mask, &port_type);
  329. return ret;
  330. }
  331. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  332. u8 slv_port_type, u8 enable)
  333. {
  334. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  335. u8 port_id, num_ch, ch_mask, port_type;
  336. u32 ch_rate;
  337. u8 num_port = 1;
  338. int ret = 0;
  339. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  340. &num_ch, &ch_mask, &ch_rate,
  341. &port_type, CODEC_RX);
  342. if (ret)
  343. return ret;
  344. if (enable)
  345. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  346. num_port, &ch_mask, &ch_rate,
  347. &num_ch, &port_type);
  348. else
  349. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  350. num_port, &ch_mask, &port_type);
  351. return ret;
  352. }
  353. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  354. {
  355. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  356. if (wcd938x->rx_clk_cnt == 0) {
  357. snd_soc_component_update_bits(component,
  358. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  359. snd_soc_component_update_bits(component,
  360. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  361. snd_soc_component_update_bits(component,
  362. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  363. snd_soc_component_update_bits(component,
  364. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  365. snd_soc_component_update_bits(component,
  366. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  367. snd_soc_component_update_bits(component,
  368. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  369. snd_soc_component_update_bits(component,
  370. WCD938X_AUX_AUXPA, 0x10, 0x10);
  371. }
  372. wcd938x->rx_clk_cnt++;
  373. return 0;
  374. }
  375. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  376. {
  377. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  378. wcd938x->rx_clk_cnt--;
  379. if (wcd938x->rx_clk_cnt == 0) {
  380. snd_soc_component_update_bits(component,
  381. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  382. snd_soc_component_update_bits(component,
  383. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  384. snd_soc_component_update_bits(component,
  385. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  386. snd_soc_component_update_bits(component,
  387. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  388. snd_soc_component_update_bits(component,
  389. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  390. }
  391. return 0;
  392. }
  393. /*
  394. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  395. * @component: handle to snd_soc_component *
  396. *
  397. * return wcd938x_mbhc handle or error code in case of failure
  398. */
  399. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  400. {
  401. struct wcd938x_priv *wcd938x;
  402. if (!component) {
  403. pr_err("%s: Invalid params, NULL component\n", __func__);
  404. return NULL;
  405. }
  406. wcd938x = snd_soc_component_get_drvdata(component);
  407. if (!wcd938x) {
  408. pr_err("%s: wcd938x is NULL\n", __func__);
  409. return NULL;
  410. }
  411. return wcd938x->mbhc;
  412. }
  413. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  414. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  415. struct snd_kcontrol *kcontrol,
  416. int event)
  417. {
  418. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  419. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  420. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  421. w->name, event);
  422. switch (event) {
  423. case SND_SOC_DAPM_PRE_PMU:
  424. wcd938x_rx_clk_enable(component);
  425. snd_soc_component_update_bits(component,
  426. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  427. snd_soc_component_update_bits(component,
  428. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  429. snd_soc_component_update_bits(component,
  430. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  431. break;
  432. case SND_SOC_DAPM_POST_PMU:
  433. snd_soc_component_update_bits(component,
  434. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  435. if (wcd938x->comp1_enable) {
  436. snd_soc_component_update_bits(component,
  437. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  438. /* 5msec compander delay as per HW requirement */
  439. if (!wcd938x->comp2_enable ||
  440. (snd_soc_component_read32(component,
  441. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  442. usleep_range(5000, 5010);
  443. snd_soc_component_update_bits(component,
  444. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  445. } else {
  446. snd_soc_component_update_bits(component,
  447. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  448. 0x02, 0x00);
  449. snd_soc_component_update_bits(component,
  450. WCD938X_HPH_L_EN, 0x20, 0x20);
  451. }
  452. break;
  453. case SND_SOC_DAPM_POST_PMD:
  454. snd_soc_component_update_bits(component,
  455. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  456. 0x0F, 0x01);
  457. break;
  458. }
  459. return 0;
  460. }
  461. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  462. struct snd_kcontrol *kcontrol,
  463. int event)
  464. {
  465. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  466. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  467. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  468. w->name, event);
  469. switch (event) {
  470. case SND_SOC_DAPM_PRE_PMU:
  471. wcd938x_rx_clk_enable(component);
  472. snd_soc_component_update_bits(component,
  473. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  474. snd_soc_component_update_bits(component,
  475. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  476. snd_soc_component_update_bits(component,
  477. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  478. break;
  479. case SND_SOC_DAPM_POST_PMU:
  480. snd_soc_component_update_bits(component,
  481. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  482. if (wcd938x->comp2_enable) {
  483. snd_soc_component_update_bits(component,
  484. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  485. /* 5msec compander delay as per HW requirement */
  486. if (!wcd938x->comp1_enable ||
  487. (snd_soc_component_read32(component,
  488. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  489. usleep_range(5000, 5010);
  490. snd_soc_component_update_bits(component,
  491. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  492. } else {
  493. snd_soc_component_update_bits(component,
  494. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  495. 0x01, 0x00);
  496. snd_soc_component_update_bits(component,
  497. WCD938X_HPH_R_EN, 0x20, 0x20);
  498. }
  499. break;
  500. case SND_SOC_DAPM_POST_PMD:
  501. snd_soc_component_update_bits(component,
  502. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  503. 0x0F, 0x01);
  504. break;
  505. }
  506. return 0;
  507. }
  508. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  509. struct snd_kcontrol *kcontrol,
  510. int event)
  511. {
  512. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  513. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  514. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  515. w->name, event);
  516. switch (event) {
  517. case SND_SOC_DAPM_PRE_PMU:
  518. wcd938x_rx_clk_enable(component);
  519. wcd938x->ear_rx_path =
  520. snd_soc_component_read32(
  521. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  522. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  523. snd_soc_component_update_bits(component,
  524. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x00);
  525. snd_soc_component_update_bits(component,
  526. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  527. snd_soc_component_update_bits(component,
  528. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  529. snd_soc_component_update_bits(component,
  530. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  531. } else {
  532. snd_soc_component_update_bits(component,
  533. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  534. snd_soc_component_update_bits(component,
  535. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  536. snd_soc_component_update_bits(component,
  537. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  538. }
  539. /* 5 msec delay as per HW requirement */
  540. usleep_range(5000, 5010);
  541. if (wcd938x->flyback_cur_det_disable == 0)
  542. snd_soc_component_update_bits(component,
  543. WCD938X_FLYBACK_EN,
  544. 0x04, 0x00);
  545. wcd938x->flyback_cur_det_disable++;
  546. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  547. WCD_CLSH_EVENT_PRE_DAC,
  548. WCD_CLSH_STATE_EAR,
  549. wcd938x->hph_mode);
  550. break;
  551. case SND_SOC_DAPM_POST_PMD:
  552. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  553. snd_soc_component_update_bits(component,
  554. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x00);
  555. }
  556. snd_soc_component_update_bits(component,
  557. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  558. snd_soc_component_update_bits(component,
  559. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x80);
  560. break;
  561. };
  562. return 0;
  563. }
  564. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  565. struct snd_kcontrol *kcontrol,
  566. int event)
  567. {
  568. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  569. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  570. int ret = 0;
  571. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  572. w->name, event);
  573. switch (event) {
  574. case SND_SOC_DAPM_PRE_PMU:
  575. wcd938x_rx_clk_enable(component);
  576. snd_soc_component_update_bits(component,
  577. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  578. snd_soc_component_update_bits(component,
  579. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  580. snd_soc_component_update_bits(component,
  581. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  582. if (wcd938x->flyback_cur_det_disable == 0)
  583. snd_soc_component_update_bits(component,
  584. WCD938X_FLYBACK_EN,
  585. 0x04, 0x00);
  586. wcd938x->flyback_cur_det_disable++;
  587. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  588. WCD_CLSH_EVENT_PRE_DAC,
  589. WCD_CLSH_STATE_AUX,
  590. wcd938x->hph_mode);
  591. break;
  592. case SND_SOC_DAPM_POST_PMD:
  593. snd_soc_component_update_bits(component,
  594. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  595. break;
  596. };
  597. return ret;
  598. }
  599. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  600. struct snd_kcontrol *kcontrol,
  601. int event)
  602. {
  603. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  604. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  605. int ret = 0;
  606. int hph_mode = wcd938x->hph_mode;
  607. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  608. w->name, event);
  609. switch (event) {
  610. case SND_SOC_DAPM_PRE_PMU:
  611. if (wcd938x->ldoh)
  612. snd_soc_component_update_bits(component,
  613. WCD938X_LDOH_MODE,
  614. 0x80, 0x80);
  615. if (wcd938x->update_wcd_event)
  616. wcd938x->update_wcd_event(wcd938x->handle,
  617. WCD_BOLERO_EVT_RX_MUTE,
  618. (WCD_RX2 << 0x10 | 0x1));
  619. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  620. wcd938x->rx_swr_dev->dev_num,
  621. true);
  622. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  623. WCD_CLSH_EVENT_PRE_DAC,
  624. WCD_CLSH_STATE_HPHR,
  625. hph_mode);
  626. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  627. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  628. 0x10, 0x10);
  629. wcd_clsh_set_hph_mode(component, hph_mode);
  630. /* 100 usec delay as per HW requirement */
  631. usleep_range(100, 110);
  632. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  633. snd_soc_component_update_bits(component,
  634. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  635. break;
  636. case SND_SOC_DAPM_POST_PMU:
  637. /*
  638. * 7ms sleep is required if compander is enabled as per
  639. * HW requirement. If compander is disabled, then
  640. * 20ms delay is required.
  641. */
  642. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  643. if (!wcd938x->comp2_enable)
  644. usleep_range(20000, 20100);
  645. else
  646. usleep_range(7000, 7100);
  647. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  648. }
  649. snd_soc_component_update_bits(component,
  650. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  651. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  652. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  653. snd_soc_component_update_bits(component,
  654. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  655. if (wcd938x->update_wcd_event)
  656. wcd938x->update_wcd_event(wcd938x->handle,
  657. WCD_BOLERO_EVT_RX_MUTE,
  658. (WCD_RX2 << 0x10));
  659. wcd_enable_irq(&wcd938x->irq_info,
  660. WCD938X_IRQ_HPHR_PDM_WD_INT);
  661. break;
  662. case SND_SOC_DAPM_PRE_PMD:
  663. if (wcd938x->update_wcd_event)
  664. wcd938x->update_wcd_event(wcd938x->handle,
  665. WCD_BOLERO_EVT_RX_MUTE,
  666. (WCD_RX2 << 0x10 | 0x1));
  667. wcd_disable_irq(&wcd938x->irq_info,
  668. WCD938X_IRQ_HPHR_PDM_WD_INT);
  669. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  670. wcd938x->update_wcd_event(wcd938x->handle,
  671. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  672. (WCD_RX2 << 0x10));
  673. /*
  674. * 7ms sleep is required if compander is enabled as per
  675. * HW requirement. If compander is disabled, then
  676. * 20ms delay is required.
  677. */
  678. if (!wcd938x->comp2_enable)
  679. usleep_range(20000, 20100);
  680. else
  681. usleep_range(7000, 7100);
  682. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  683. 0x40, 0x00);
  684. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  685. WCD_EVENT_PRE_HPHR_PA_OFF,
  686. &wcd938x->mbhc->wcd_mbhc);
  687. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  688. break;
  689. case SND_SOC_DAPM_POST_PMD:
  690. /*
  691. * 7ms sleep is required if compander is enabled as per
  692. * HW requirement. If compander is disabled, then
  693. * 20ms delay is required.
  694. */
  695. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  696. if (!wcd938x->comp2_enable)
  697. usleep_range(20000, 20100);
  698. else
  699. usleep_range(7000, 7100);
  700. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  701. }
  702. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  703. WCD_EVENT_POST_HPHR_PA_OFF,
  704. &wcd938x->mbhc->wcd_mbhc);
  705. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  706. 0x10, 0x00);
  707. snd_soc_component_update_bits(component,
  708. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  709. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  710. WCD_CLSH_EVENT_POST_PA,
  711. WCD_CLSH_STATE_HPHR,
  712. hph_mode);
  713. if (wcd938x->ldoh)
  714. snd_soc_component_update_bits(component,
  715. WCD938X_LDOH_MODE,
  716. 0x80, 0x00);
  717. break;
  718. };
  719. return ret;
  720. }
  721. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  722. struct snd_kcontrol *kcontrol,
  723. int event)
  724. {
  725. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  726. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  727. int ret = 0;
  728. int hph_mode = wcd938x->hph_mode;
  729. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  730. w->name, event);
  731. switch (event) {
  732. case SND_SOC_DAPM_PRE_PMU:
  733. if (wcd938x->ldoh)
  734. snd_soc_component_update_bits(component,
  735. WCD938X_LDOH_MODE,
  736. 0x80, 0x80);
  737. if (wcd938x->update_wcd_event)
  738. wcd938x->update_wcd_event(wcd938x->handle,
  739. WCD_BOLERO_EVT_RX_MUTE,
  740. (WCD_RX1 << 0x10 | 0x01));
  741. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  742. wcd938x->rx_swr_dev->dev_num,
  743. true);
  744. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  745. WCD_CLSH_EVENT_PRE_DAC,
  746. WCD_CLSH_STATE_HPHL,
  747. hph_mode);
  748. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  749. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  750. 0x20, 0x20);
  751. wcd_clsh_set_hph_mode(component, hph_mode);
  752. /* 100 usec delay as per HW requirement */
  753. usleep_range(100, 110);
  754. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  755. snd_soc_component_update_bits(component,
  756. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  757. break;
  758. case SND_SOC_DAPM_POST_PMU:
  759. /*
  760. * 7ms sleep is required if compander is enabled as per
  761. * HW requirement. If compander is disabled, then
  762. * 20ms delay is required.
  763. */
  764. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  765. if (!wcd938x->comp1_enable)
  766. usleep_range(20000, 20100);
  767. else
  768. usleep_range(7000, 7100);
  769. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  770. }
  771. snd_soc_component_update_bits(component,
  772. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  773. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  774. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  775. snd_soc_component_update_bits(component,
  776. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  777. if (wcd938x->update_wcd_event)
  778. wcd938x->update_wcd_event(wcd938x->handle,
  779. WCD_BOLERO_EVT_RX_MUTE,
  780. (WCD_RX1 << 0x10));
  781. wcd_enable_irq(&wcd938x->irq_info,
  782. WCD938X_IRQ_HPHL_PDM_WD_INT);
  783. break;
  784. case SND_SOC_DAPM_PRE_PMD:
  785. if (wcd938x->update_wcd_event)
  786. wcd938x->update_wcd_event(wcd938x->handle,
  787. WCD_BOLERO_EVT_RX_MUTE,
  788. (WCD_RX1 << 0x10 | 0x1));
  789. wcd_disable_irq(&wcd938x->irq_info,
  790. WCD938X_IRQ_HPHL_PDM_WD_INT);
  791. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  792. wcd938x->update_wcd_event(wcd938x->handle,
  793. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  794. (WCD_RX1 << 0x10));
  795. /*
  796. * 7ms sleep is required if compander is enabled as per
  797. * HW requirement. If compander is disabled, then
  798. * 20ms delay is required.
  799. */
  800. if (!wcd938x->comp1_enable)
  801. usleep_range(20000, 20100);
  802. else
  803. usleep_range(7000, 7100);
  804. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  805. 0x80, 0x00);
  806. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  807. WCD_EVENT_PRE_HPHL_PA_OFF,
  808. &wcd938x->mbhc->wcd_mbhc);
  809. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  810. break;
  811. case SND_SOC_DAPM_POST_PMD:
  812. /*
  813. * 7ms sleep is required if compander is enabled as per
  814. * HW requirement. If compander is disabled, then
  815. * 20ms delay is required.
  816. */
  817. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  818. if (!wcd938x->comp1_enable)
  819. usleep_range(21000, 21100);
  820. else
  821. usleep_range(7000, 7100);
  822. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  823. }
  824. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  825. WCD_EVENT_POST_HPHL_PA_OFF,
  826. &wcd938x->mbhc->wcd_mbhc);
  827. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  828. 0x20, 0x00);
  829. snd_soc_component_update_bits(component,
  830. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  831. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  832. WCD_CLSH_EVENT_POST_PA,
  833. WCD_CLSH_STATE_HPHL,
  834. hph_mode);
  835. if (wcd938x->ldoh)
  836. snd_soc_component_update_bits(component,
  837. WCD938X_LDOH_MODE,
  838. 0x80, 0x00);
  839. break;
  840. };
  841. return ret;
  842. }
  843. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  844. struct snd_kcontrol *kcontrol,
  845. int event)
  846. {
  847. struct snd_soc_component *component =
  848. snd_soc_dapm_to_component(w->dapm);
  849. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  850. int hph_mode = wcd938x->hph_mode;
  851. int ret = 0;
  852. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  853. w->name, event);
  854. switch (event) {
  855. case SND_SOC_DAPM_PRE_PMU:
  856. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  857. wcd938x->rx_swr_dev->dev_num,
  858. true);
  859. snd_soc_component_update_bits(component,
  860. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  861. break;
  862. case SND_SOC_DAPM_POST_PMU:
  863. /* 1 msec delay as per HW requirement */
  864. usleep_range(1000, 1010);
  865. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  866. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  867. snd_soc_component_update_bits(component,
  868. WCD938X_ANA_RX_SUPPLIES,
  869. 0x02, 0x02);
  870. if (wcd938x->update_wcd_event)
  871. wcd938x->update_wcd_event(wcd938x->handle,
  872. WCD_BOLERO_EVT_RX_MUTE,
  873. (WCD_RX3 << 0x10));
  874. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  875. break;
  876. case SND_SOC_DAPM_PRE_PMD:
  877. wcd_disable_irq(&wcd938x->irq_info,
  878. WCD938X_IRQ_AUX_PDM_WD_INT);
  879. if (wcd938x->update_wcd_event)
  880. wcd938x->update_wcd_event(wcd938x->handle,
  881. WCD_BOLERO_EVT_RX_MUTE,
  882. (WCD_RX3 << 0x10 | 0x1));
  883. break;
  884. case SND_SOC_DAPM_POST_PMD:
  885. /* 1 msec delay as per HW requirement */
  886. usleep_range(1000, 1010);
  887. snd_soc_component_update_bits(component,
  888. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  889. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  890. WCD_CLSH_EVENT_POST_PA,
  891. WCD_CLSH_STATE_AUX,
  892. hph_mode);
  893. wcd938x->flyback_cur_det_disable--;
  894. if (wcd938x->flyback_cur_det_disable == 0)
  895. snd_soc_component_update_bits(component,
  896. WCD938X_FLYBACK_EN,
  897. 0x04, 0x04);
  898. break;
  899. };
  900. return ret;
  901. }
  902. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  903. struct snd_kcontrol *kcontrol,
  904. int event)
  905. {
  906. struct snd_soc_component *component =
  907. snd_soc_dapm_to_component(w->dapm);
  908. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  909. int hph_mode = wcd938x->hph_mode;
  910. int ret = 0;
  911. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  912. w->name, event);
  913. switch (event) {
  914. case SND_SOC_DAPM_PRE_PMU:
  915. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  916. wcd938x->rx_swr_dev->dev_num,
  917. true);
  918. /*
  919. * Enable watchdog interrupt for HPHL or AUX
  920. * depending on mux value
  921. */
  922. wcd938x->ear_rx_path =
  923. snd_soc_component_read32(
  924. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  925. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  926. snd_soc_component_update_bits(component,
  927. WCD938X_DIGITAL_PDM_WD_CTL2,
  928. 0x05, 0x05);
  929. else
  930. snd_soc_component_update_bits(component,
  931. WCD938X_DIGITAL_PDM_WD_CTL0,
  932. 0x17, 0x13);
  933. break;
  934. case SND_SOC_DAPM_POST_PMU:
  935. /* 6 msec delay as per HW requirement */
  936. usleep_range(6000, 6010);
  937. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  938. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  939. snd_soc_component_update_bits(component,
  940. WCD938X_ANA_RX_SUPPLIES,
  941. 0x02, 0x02);
  942. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  943. if (wcd938x->update_wcd_event)
  944. wcd938x->update_wcd_event(wcd938x->handle,
  945. WCD_BOLERO_EVT_RX_MUTE,
  946. (WCD_RX3 << 0x10));
  947. wcd_enable_irq(&wcd938x->irq_info,
  948. WCD938X_IRQ_AUX_PDM_WD_INT);
  949. } else {
  950. if (wcd938x->update_wcd_event)
  951. wcd938x->update_wcd_event(wcd938x->handle,
  952. WCD_BOLERO_EVT_RX_MUTE,
  953. (WCD_RX1 << 0x10));
  954. wcd_enable_irq(&wcd938x->irq_info,
  955. WCD938X_IRQ_HPHL_PDM_WD_INT);
  956. }
  957. break;
  958. case SND_SOC_DAPM_PRE_PMD:
  959. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  960. wcd_disable_irq(&wcd938x->irq_info,
  961. WCD938X_IRQ_AUX_PDM_WD_INT);
  962. else
  963. wcd_disable_irq(&wcd938x->irq_info,
  964. WCD938X_IRQ_HPHL_PDM_WD_INT);
  965. if (wcd938x->update_wcd_event)
  966. wcd938x->update_wcd_event(wcd938x->handle,
  967. WCD_BOLERO_EVT_RX_MUTE,
  968. (WCD_RX1 << 0x10 | 0x1));
  969. break;
  970. case SND_SOC_DAPM_POST_PMD:
  971. /* 7 msec delay as per HW requirement */
  972. usleep_range(7000, 7010);
  973. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  974. snd_soc_component_update_bits(component,
  975. WCD938X_DIGITAL_PDM_WD_CTL2,
  976. 0x05, 0x00);
  977. else
  978. snd_soc_component_update_bits(component,
  979. WCD938X_DIGITAL_PDM_WD_CTL0,
  980. 0x17, 0x00);
  981. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  982. WCD_CLSH_EVENT_POST_PA,
  983. WCD_CLSH_STATE_EAR,
  984. hph_mode);
  985. wcd938x->flyback_cur_det_disable--;
  986. if (wcd938x->flyback_cur_det_disable == 0)
  987. snd_soc_component_update_bits(component,
  988. WCD938X_FLYBACK_EN,
  989. 0x04, 0x04);
  990. break;
  991. };
  992. return ret;
  993. }
  994. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  995. struct snd_kcontrol *kcontrol,
  996. int event)
  997. {
  998. struct snd_soc_component *component =
  999. snd_soc_dapm_to_component(w->dapm);
  1000. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1001. int mode = wcd938x->hph_mode;
  1002. int ret = 0;
  1003. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1004. w->name, event);
  1005. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1006. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1007. wcd938x_rx_connect_port(component, CLSH,
  1008. SND_SOC_DAPM_EVENT_ON(event));
  1009. }
  1010. if (SND_SOC_DAPM_EVENT_OFF(event))
  1011. ret = swr_slvdev_datapath_control(
  1012. wcd938x->rx_swr_dev,
  1013. wcd938x->rx_swr_dev->dev_num,
  1014. false);
  1015. return ret;
  1016. }
  1017. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  1018. struct snd_kcontrol *kcontrol,
  1019. int event)
  1020. {
  1021. struct snd_soc_component *component =
  1022. snd_soc_dapm_to_component(w->dapm);
  1023. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1024. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1025. w->name, event);
  1026. switch (event) {
  1027. case SND_SOC_DAPM_PRE_PMU:
  1028. wcd938x_rx_connect_port(component, HPH_L, true);
  1029. if (wcd938x->comp1_enable)
  1030. wcd938x_rx_connect_port(component, COMP_L, true);
  1031. break;
  1032. case SND_SOC_DAPM_POST_PMD:
  1033. wcd938x_rx_connect_port(component, HPH_L, false);
  1034. if (wcd938x->comp1_enable)
  1035. wcd938x_rx_connect_port(component, COMP_L, false);
  1036. wcd938x_rx_clk_disable(component);
  1037. snd_soc_component_update_bits(component,
  1038. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1039. 0x01, 0x00);
  1040. break;
  1041. };
  1042. return 0;
  1043. }
  1044. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  1045. struct snd_kcontrol *kcontrol, int event)
  1046. {
  1047. struct snd_soc_component *component =
  1048. snd_soc_dapm_to_component(w->dapm);
  1049. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1050. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1051. w->name, event);
  1052. switch (event) {
  1053. case SND_SOC_DAPM_PRE_PMU:
  1054. wcd938x_rx_connect_port(component, HPH_R, true);
  1055. if (wcd938x->comp2_enable)
  1056. wcd938x_rx_connect_port(component, COMP_R, true);
  1057. break;
  1058. case SND_SOC_DAPM_POST_PMD:
  1059. wcd938x_rx_connect_port(component, HPH_R, false);
  1060. if (wcd938x->comp2_enable)
  1061. wcd938x_rx_connect_port(component, COMP_R, false);
  1062. wcd938x_rx_clk_disable(component);
  1063. snd_soc_component_update_bits(component,
  1064. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1065. 0x02, 0x00);
  1066. break;
  1067. };
  1068. return 0;
  1069. }
  1070. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1071. struct snd_kcontrol *kcontrol,
  1072. int event)
  1073. {
  1074. struct snd_soc_component *component =
  1075. snd_soc_dapm_to_component(w->dapm);
  1076. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1077. w->name, event);
  1078. switch (event) {
  1079. case SND_SOC_DAPM_PRE_PMU:
  1080. wcd938x_rx_connect_port(component, LO, true);
  1081. break;
  1082. case SND_SOC_DAPM_POST_PMD:
  1083. wcd938x_rx_connect_port(component, LO, false);
  1084. /* 6 msec delay as per HW requirement */
  1085. usleep_range(6000, 6010);
  1086. wcd938x_rx_clk_disable(component);
  1087. snd_soc_component_update_bits(component,
  1088. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1089. break;
  1090. }
  1091. return 0;
  1092. }
  1093. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1094. struct snd_kcontrol *kcontrol,
  1095. int event)
  1096. {
  1097. struct snd_soc_component *component =
  1098. snd_soc_dapm_to_component(w->dapm);
  1099. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1100. u16 dmic_clk_reg, dmic_clk_en_reg;
  1101. s32 *dmic_clk_cnt;
  1102. u8 dmic_ctl_shift = 0;
  1103. u8 dmic_clk_shift = 0;
  1104. u8 dmic_clk_mask = 0;
  1105. u16 dmic2_left_en = 0;
  1106. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1107. w->name, event);
  1108. switch (w->shift) {
  1109. case 0:
  1110. case 1:
  1111. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1112. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1113. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1114. dmic_clk_mask = 0x0F;
  1115. dmic_clk_shift = 0x00;
  1116. dmic_ctl_shift = 0x00;
  1117. break;
  1118. case 2:
  1119. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1120. case 3:
  1121. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1122. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1123. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1124. dmic_clk_mask = 0xF0;
  1125. dmic_clk_shift = 0x04;
  1126. dmic_ctl_shift = 0x01;
  1127. break;
  1128. case 4:
  1129. case 5:
  1130. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1131. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1132. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1133. dmic_clk_mask = 0x0F;
  1134. dmic_clk_shift = 0x00;
  1135. dmic_ctl_shift = 0x02;
  1136. break;
  1137. case 6:
  1138. case 7:
  1139. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1140. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1141. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1142. dmic_clk_mask = 0xF0;
  1143. dmic_clk_shift = 0x04;
  1144. dmic_ctl_shift = 0x03;
  1145. break;
  1146. default:
  1147. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1148. __func__);
  1149. return -EINVAL;
  1150. };
  1151. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1152. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1153. switch (event) {
  1154. case SND_SOC_DAPM_PRE_PMU:
  1155. snd_soc_component_update_bits(component,
  1156. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1157. (0x01 << dmic_ctl_shift), 0x00);
  1158. /* 250us sleep as per HW requirement */
  1159. usleep_range(250, 260);
  1160. if (dmic2_left_en)
  1161. snd_soc_component_update_bits(component,
  1162. dmic2_left_en, 0x80, 0x80);
  1163. /* Setting DMIC clock rate to 2.4MHz */
  1164. snd_soc_component_update_bits(component,
  1165. dmic_clk_reg, dmic_clk_mask,
  1166. (0x03 << dmic_clk_shift));
  1167. snd_soc_component_update_bits(component,
  1168. dmic_clk_en_reg, 0x08, 0x08);
  1169. /* enable clock scaling */
  1170. snd_soc_component_update_bits(component,
  1171. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1172. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1173. break;
  1174. case SND_SOC_DAPM_POST_PMD:
  1175. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1176. snd_soc_component_update_bits(component,
  1177. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1178. (0x01 << dmic_ctl_shift),
  1179. (0x01 << dmic_ctl_shift));
  1180. if (dmic2_left_en)
  1181. snd_soc_component_update_bits(component,
  1182. dmic2_left_en, 0x80, 0x00);
  1183. snd_soc_component_update_bits(component,
  1184. dmic_clk_en_reg, 0x08, 0x00);
  1185. break;
  1186. };
  1187. return 0;
  1188. }
  1189. /*
  1190. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1191. * @micb_mv: micbias in mv
  1192. *
  1193. * return register value converted
  1194. */
  1195. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1196. {
  1197. /* min micbias voltage is 1V and maximum is 2.85V */
  1198. if (micb_mv < 1000 || micb_mv > 2850) {
  1199. pr_err("%s: unsupported micbias voltage\n", __func__);
  1200. return -EINVAL;
  1201. }
  1202. return (micb_mv - 1000) / 50;
  1203. }
  1204. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1205. /*
  1206. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1207. * @component: handle to snd_soc_component *
  1208. * @req_volt: micbias voltage to be set
  1209. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1210. *
  1211. * return 0 if adjustment is success or error code in case of failure
  1212. */
  1213. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1214. int req_volt, int micb_num)
  1215. {
  1216. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1217. int cur_vout_ctl, req_vout_ctl;
  1218. int micb_reg, micb_val, micb_en;
  1219. int ret = 0;
  1220. switch (micb_num) {
  1221. case MIC_BIAS_1:
  1222. micb_reg = WCD938X_ANA_MICB1;
  1223. break;
  1224. case MIC_BIAS_2:
  1225. micb_reg = WCD938X_ANA_MICB2;
  1226. break;
  1227. case MIC_BIAS_3:
  1228. micb_reg = WCD938X_ANA_MICB3;
  1229. break;
  1230. case MIC_BIAS_4:
  1231. micb_reg = WCD938X_ANA_MICB4;
  1232. break;
  1233. default:
  1234. return -EINVAL;
  1235. }
  1236. mutex_lock(&wcd938x->micb_lock);
  1237. /*
  1238. * If requested micbias voltage is same as current micbias
  1239. * voltage, then just return. Otherwise, adjust voltage as
  1240. * per requested value. If micbias is already enabled, then
  1241. * to avoid slow micbias ramp-up or down enable pull-up
  1242. * momentarily, change the micbias value and then re-enable
  1243. * micbias.
  1244. */
  1245. micb_val = snd_soc_component_read32(component, micb_reg);
  1246. micb_en = (micb_val & 0xC0) >> 6;
  1247. cur_vout_ctl = micb_val & 0x3F;
  1248. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1249. if (req_vout_ctl < 0) {
  1250. ret = -EINVAL;
  1251. goto exit;
  1252. }
  1253. if (cur_vout_ctl == req_vout_ctl) {
  1254. ret = 0;
  1255. goto exit;
  1256. }
  1257. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1258. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1259. req_volt, micb_en);
  1260. if (micb_en == 0x1)
  1261. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1262. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1263. if (micb_en == 0x1) {
  1264. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1265. /*
  1266. * Add 2ms delay as per HW requirement after enabling
  1267. * micbias
  1268. */
  1269. usleep_range(2000, 2100);
  1270. }
  1271. exit:
  1272. mutex_unlock(&wcd938x->micb_lock);
  1273. return ret;
  1274. }
  1275. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1276. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1277. struct snd_kcontrol *kcontrol,
  1278. int event)
  1279. {
  1280. struct snd_soc_component *component =
  1281. snd_soc_dapm_to_component(w->dapm);
  1282. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1283. int ret = 0;
  1284. int bank = 0;
  1285. int mode = 0;
  1286. bank = wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1287. wcd938x->tx_swr_dev->dev_num);
  1288. wcd938x_swr_slv_set_host_clk_div2(wcd938x->tx_swr_dev,
  1289. wcd938x->tx_swr_dev->dev_num, bank);
  1290. switch (event) {
  1291. case SND_SOC_DAPM_PRE_PMU:
  1292. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1293. wcd938x->tx_swr_dev->dev_num,
  1294. true);
  1295. if (test_bit(WCD_ADC1, &wcd938x->status_mask))
  1296. mode |= wcd938x->tx_mode[WCD_ADC1];
  1297. if (test_bit(WCD_ADC2, &wcd938x->status_mask))
  1298. mode |= wcd938x->tx_mode[WCD_ADC2];
  1299. if (test_bit(WCD_ADC3, &wcd938x->status_mask))
  1300. mode |= wcd938x->tx_mode[WCD_ADC3];
  1301. if (test_bit(WCD_ADC4, &wcd938x->status_mask))
  1302. mode |= wcd938x->tx_mode[WCD_ADC4];
  1303. wcd938x_set_swr_clk_rate(component, mode, bank);
  1304. break;
  1305. case SND_SOC_DAPM_POST_PMD:
  1306. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1307. wcd938x->tx_swr_dev->dev_num,
  1308. false);
  1309. wcd938x_set_swr_clk_rate(component, ADC_MODE_INVALID, bank);
  1310. break;
  1311. };
  1312. return ret;
  1313. }
  1314. static int wcd938x_get_adc_mode(int val)
  1315. {
  1316. int ret = 0;
  1317. switch (val) {
  1318. case ADC_MODE_INVALID:
  1319. ret = ADC_MODE_VAL_NORMAL;
  1320. break;
  1321. case ADC_MODE_HIFI:
  1322. ret = ADC_MODE_VAL_HIFI;
  1323. break;
  1324. case ADC_MODE_LO_HIF:
  1325. ret = ADC_MODE_VAL_LO_HIF;
  1326. break;
  1327. case ADC_MODE_NORMAL:
  1328. ret = ADC_MODE_VAL_NORMAL;
  1329. break;
  1330. case ADC_MODE_LP:
  1331. ret = ADC_MODE_VAL_LP;
  1332. break;
  1333. case ADC_MODE_ULP1:
  1334. ret = ADC_MODE_VAL_ULP1;
  1335. break;
  1336. case ADC_MODE_ULP2:
  1337. ret = ADC_MODE_VAL_ULP2;
  1338. break;
  1339. default:
  1340. ret = -EINVAL;
  1341. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1342. break;
  1343. }
  1344. return ret;
  1345. }
  1346. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1347. struct snd_kcontrol *kcontrol,
  1348. int event){
  1349. struct snd_soc_component *component =
  1350. snd_soc_dapm_to_component(w->dapm);
  1351. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1352. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1353. w->name, event);
  1354. switch (event) {
  1355. case SND_SOC_DAPM_PRE_PMU:
  1356. snd_soc_component_update_bits(component,
  1357. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1358. snd_soc_component_update_bits(component,
  1359. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1360. set_bit(w->shift, &wcd938x->status_mask);
  1361. /* Enable BCS for Headset mic */
  1362. if (w->shift == 1 && !(snd_soc_component_read32(component,
  1363. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1364. wcd938x_tx_connect_port(component, MBHC, true);
  1365. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1366. }
  1367. wcd938x_tx_connect_port(component, ADC1 + (w->shift), true);
  1368. break;
  1369. case SND_SOC_DAPM_POST_PMD:
  1370. wcd938x_tx_connect_port(component, ADC1 + (w->shift), false);
  1371. if (w->shift == 1 &&
  1372. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1373. wcd938x_tx_connect_port(component, MBHC, false);
  1374. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1375. }
  1376. snd_soc_component_update_bits(component,
  1377. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1378. clear_bit(w->shift, &wcd938x->status_mask);
  1379. break;
  1380. };
  1381. return 0;
  1382. }
  1383. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1384. int channel, int mode)
  1385. {
  1386. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1387. int ret = 0;
  1388. switch (channel) {
  1389. case 0:
  1390. reg = WCD938X_ANA_TX_CH2;
  1391. mask = 0x40;
  1392. break;
  1393. case 1:
  1394. reg = WCD938X_ANA_TX_CH2;
  1395. mask = 0x20;
  1396. break;
  1397. case 2:
  1398. reg = WCD938X_ANA_TX_CH4;
  1399. mask = 0x40;
  1400. break;
  1401. case 3:
  1402. reg = WCD938X_ANA_TX_CH4;
  1403. mask = 0x20;
  1404. break;
  1405. default:
  1406. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1407. ret = -EINVAL;
  1408. break;
  1409. }
  1410. if (!mode)
  1411. val = 0x00;
  1412. else
  1413. val = mask;
  1414. if (!ret)
  1415. snd_soc_component_update_bits(component, reg, mask, val);
  1416. return ret;
  1417. }
  1418. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1419. struct snd_kcontrol *kcontrol, int event)
  1420. {
  1421. struct snd_soc_component *component =
  1422. snd_soc_dapm_to_component(w->dapm);
  1423. int mode;
  1424. int ret = 0;
  1425. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1426. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1427. w->name, event);
  1428. switch (event) {
  1429. case SND_SOC_DAPM_PRE_PMU:
  1430. snd_soc_component_update_bits(component,
  1431. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1432. snd_soc_component_update_bits(component,
  1433. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1434. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1435. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1436. if (mode < 0) {
  1437. dev_info(component->dev,
  1438. "%s: invalid mode, setting to normal mode\n",
  1439. __func__);
  1440. mode = ADC_MODE_VAL_NORMAL;
  1441. }
  1442. switch (w->shift) {
  1443. case 0:
  1444. snd_soc_component_update_bits(component,
  1445. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1446. mode);
  1447. snd_soc_component_update_bits(component,
  1448. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1449. break;
  1450. case 1:
  1451. snd_soc_component_update_bits(component,
  1452. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1453. mode << 4);
  1454. snd_soc_component_update_bits(component,
  1455. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1456. break;
  1457. case 2:
  1458. snd_soc_component_update_bits(component,
  1459. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1460. mode);
  1461. snd_soc_component_update_bits(component,
  1462. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1463. break;
  1464. case 3:
  1465. snd_soc_component_update_bits(component,
  1466. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1467. mode << 4);
  1468. snd_soc_component_update_bits(component,
  1469. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1470. break;
  1471. default:
  1472. break;
  1473. }
  1474. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1475. break;
  1476. case SND_SOC_DAPM_POST_PMD:
  1477. switch (w->shift) {
  1478. case 0:
  1479. snd_soc_component_update_bits(component,
  1480. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1481. break;
  1482. case 1:
  1483. snd_soc_component_update_bits(component,
  1484. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1485. break;
  1486. case 2:
  1487. snd_soc_component_update_bits(component,
  1488. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1489. break;
  1490. case 3:
  1491. snd_soc_component_update_bits(component,
  1492. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1493. break;
  1494. default:
  1495. break;
  1496. }
  1497. snd_soc_component_update_bits(component,
  1498. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1499. break;
  1500. };
  1501. return ret;
  1502. }
  1503. int wcd938x_micbias_control(struct snd_soc_component *component,
  1504. int micb_num, int req, bool is_dapm)
  1505. {
  1506. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1507. int micb_index = micb_num - 1;
  1508. u16 micb_reg;
  1509. int pre_off_event = 0, post_off_event = 0;
  1510. int post_on_event = 0, post_dapm_off = 0;
  1511. int post_dapm_on = 0;
  1512. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1513. dev_err(component->dev,
  1514. "%s: Invalid micbias index, micb_ind:%d\n",
  1515. __func__, micb_index);
  1516. return -EINVAL;
  1517. }
  1518. if (NULL == wcd938x) {
  1519. dev_err(component->dev,
  1520. "%s: wcd938x private data is NULL\n", __func__);
  1521. return -EINVAL;
  1522. }
  1523. switch (micb_num) {
  1524. case MIC_BIAS_1:
  1525. micb_reg = WCD938X_ANA_MICB1;
  1526. break;
  1527. case MIC_BIAS_2:
  1528. micb_reg = WCD938X_ANA_MICB2;
  1529. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1530. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1531. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1532. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1533. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1534. break;
  1535. case MIC_BIAS_3:
  1536. micb_reg = WCD938X_ANA_MICB3;
  1537. break;
  1538. case MIC_BIAS_4:
  1539. micb_reg = WCD938X_ANA_MICB4;
  1540. break;
  1541. default:
  1542. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1543. __func__, micb_num);
  1544. return -EINVAL;
  1545. };
  1546. mutex_lock(&wcd938x->micb_lock);
  1547. switch (req) {
  1548. case MICB_PULLUP_ENABLE:
  1549. wcd938x->pullup_ref[micb_index]++;
  1550. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1551. (wcd938x->micb_ref[micb_index] == 0))
  1552. snd_soc_component_update_bits(component, micb_reg,
  1553. 0xC0, 0x80);
  1554. break;
  1555. case MICB_PULLUP_DISABLE:
  1556. if (wcd938x->pullup_ref[micb_index] > 0)
  1557. wcd938x->pullup_ref[micb_index]--;
  1558. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1559. (wcd938x->micb_ref[micb_index] == 0))
  1560. snd_soc_component_update_bits(component, micb_reg,
  1561. 0xC0, 0x00);
  1562. break;
  1563. case MICB_ENABLE:
  1564. wcd938x->micb_ref[micb_index]++;
  1565. if (wcd938x->micb_ref[micb_index] == 1) {
  1566. snd_soc_component_update_bits(component,
  1567. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1568. snd_soc_component_update_bits(component,
  1569. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1570. snd_soc_component_update_bits(component,
  1571. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1572. snd_soc_component_update_bits(component,
  1573. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1574. snd_soc_component_update_bits(component,
  1575. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1576. snd_soc_component_update_bits(component,
  1577. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1578. snd_soc_component_update_bits(component,
  1579. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1580. snd_soc_component_update_bits(component,
  1581. micb_reg, 0xC0, 0x40);
  1582. if (post_on_event)
  1583. blocking_notifier_call_chain(
  1584. &wcd938x->mbhc->notifier,
  1585. post_on_event,
  1586. &wcd938x->mbhc->wcd_mbhc);
  1587. }
  1588. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1589. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1590. post_dapm_on,
  1591. &wcd938x->mbhc->wcd_mbhc);
  1592. break;
  1593. case MICB_DISABLE:
  1594. if (wcd938x->micb_ref[micb_index] > 0)
  1595. wcd938x->micb_ref[micb_index]--;
  1596. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1597. (wcd938x->pullup_ref[micb_index] > 0))
  1598. snd_soc_component_update_bits(component, micb_reg,
  1599. 0xC0, 0x80);
  1600. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1601. (wcd938x->pullup_ref[micb_index] == 0)) {
  1602. if (pre_off_event && wcd938x->mbhc)
  1603. blocking_notifier_call_chain(
  1604. &wcd938x->mbhc->notifier,
  1605. pre_off_event,
  1606. &wcd938x->mbhc->wcd_mbhc);
  1607. snd_soc_component_update_bits(component, micb_reg,
  1608. 0xC0, 0x00);
  1609. if (post_off_event && wcd938x->mbhc)
  1610. blocking_notifier_call_chain(
  1611. &wcd938x->mbhc->notifier,
  1612. post_off_event,
  1613. &wcd938x->mbhc->wcd_mbhc);
  1614. }
  1615. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1616. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1617. post_dapm_off,
  1618. &wcd938x->mbhc->wcd_mbhc);
  1619. break;
  1620. };
  1621. dev_dbg(component->dev,
  1622. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1623. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1624. wcd938x->pullup_ref[micb_index]);
  1625. mutex_unlock(&wcd938x->micb_lock);
  1626. return 0;
  1627. }
  1628. EXPORT_SYMBOL(wcd938x_micbias_control);
  1629. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1630. {
  1631. int ret = 0;
  1632. uint8_t devnum = 0;
  1633. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1634. if (ret) {
  1635. dev_err(&swr_dev->dev,
  1636. "%s get devnum %d for dev addr %lx failed\n",
  1637. __func__, devnum, swr_dev->addr);
  1638. swr_remove_device(swr_dev);
  1639. return ret;
  1640. }
  1641. swr_dev->dev_num = devnum;
  1642. return 0;
  1643. }
  1644. static int wcd938x_event_notify(struct notifier_block *block,
  1645. unsigned long val,
  1646. void *data)
  1647. {
  1648. u16 event = (val & 0xffff);
  1649. int ret = 0;
  1650. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1651. struct snd_soc_component *component = wcd938x->component;
  1652. struct wcd_mbhc *mbhc;
  1653. switch (event) {
  1654. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1655. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1656. snd_soc_component_update_bits(component,
  1657. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1658. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1659. }
  1660. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1661. snd_soc_component_update_bits(component,
  1662. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1663. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1664. }
  1665. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1666. snd_soc_component_update_bits(component,
  1667. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1668. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1669. }
  1670. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1671. snd_soc_component_update_bits(component,
  1672. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1673. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1674. }
  1675. break;
  1676. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1677. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1678. 0xC0, 0x00);
  1679. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1680. 0x80, 0x00);
  1681. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1682. 0x80, 0x00);
  1683. break;
  1684. case BOLERO_WCD_EVT_SSR_DOWN:
  1685. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1686. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  1687. wcd938x_reset_low(wcd938x->dev);
  1688. break;
  1689. case BOLERO_WCD_EVT_SSR_UP:
  1690. wcd938x_reset(wcd938x->dev);
  1691. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1692. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1693. wcd938x_init_reg(component);
  1694. regcache_mark_dirty(wcd938x->regmap);
  1695. regcache_sync(wcd938x->regmap);
  1696. /* Initialize MBHC module */
  1697. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1698. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1699. if (ret) {
  1700. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1701. __func__);
  1702. } else {
  1703. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1704. }
  1705. break;
  1706. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1707. snd_soc_component_update_bits(component,
  1708. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1709. ((val >> 0x10) << 0x01));
  1710. break;
  1711. default:
  1712. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1713. break;
  1714. }
  1715. return 0;
  1716. }
  1717. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1718. int event)
  1719. {
  1720. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1721. int micb_num;
  1722. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1723. __func__, w->name, event);
  1724. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1725. micb_num = MIC_BIAS_1;
  1726. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1727. micb_num = MIC_BIAS_2;
  1728. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1729. micb_num = MIC_BIAS_3;
  1730. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1731. micb_num = MIC_BIAS_4;
  1732. else
  1733. return -EINVAL;
  1734. switch (event) {
  1735. case SND_SOC_DAPM_PRE_PMU:
  1736. wcd938x_micbias_control(component, micb_num,
  1737. MICB_ENABLE, true);
  1738. break;
  1739. case SND_SOC_DAPM_POST_PMU:
  1740. /* 1 msec delay as per HW requirement */
  1741. usleep_range(1000, 1100);
  1742. break;
  1743. case SND_SOC_DAPM_POST_PMD:
  1744. wcd938x_micbias_control(component, micb_num,
  1745. MICB_DISABLE, true);
  1746. break;
  1747. };
  1748. return 0;
  1749. }
  1750. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1751. struct snd_kcontrol *kcontrol,
  1752. int event)
  1753. {
  1754. return __wcd938x_codec_enable_micbias(w, event);
  1755. }
  1756. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1757. int event)
  1758. {
  1759. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1760. int micb_num;
  1761. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1762. __func__, w->name, event);
  1763. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1764. micb_num = MIC_BIAS_1;
  1765. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1766. micb_num = MIC_BIAS_2;
  1767. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1768. micb_num = MIC_BIAS_3;
  1769. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  1770. micb_num = MIC_BIAS_4;
  1771. else
  1772. return -EINVAL;
  1773. switch (event) {
  1774. case SND_SOC_DAPM_PRE_PMU:
  1775. wcd938x_micbias_control(component, micb_num,
  1776. MICB_PULLUP_ENABLE, true);
  1777. break;
  1778. case SND_SOC_DAPM_POST_PMU:
  1779. /* 1 msec delay as per HW requirement */
  1780. usleep_range(1000, 1100);
  1781. break;
  1782. case SND_SOC_DAPM_POST_PMD:
  1783. wcd938x_micbias_control(component, micb_num,
  1784. MICB_PULLUP_DISABLE, true);
  1785. break;
  1786. };
  1787. return 0;
  1788. }
  1789. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1790. struct snd_kcontrol *kcontrol,
  1791. int event)
  1792. {
  1793. return __wcd938x_codec_enable_micbias_pullup(w, event);
  1794. }
  1795. static inline int wcd938x_tx_path_get(const char *wname,
  1796. unsigned int *path_num)
  1797. {
  1798. int ret = 0;
  1799. char *widget_name = NULL;
  1800. char *w_name = NULL;
  1801. char *path_num_char = NULL;
  1802. char *path_name = NULL;
  1803. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  1804. if (!widget_name)
  1805. return -EINVAL;
  1806. w_name = widget_name;
  1807. path_name = strsep(&widget_name, " ");
  1808. if (!path_name) {
  1809. pr_err("%s: Invalid widget name = %s\n",
  1810. __func__, widget_name);
  1811. ret = -EINVAL;
  1812. goto err;
  1813. }
  1814. path_num_char = strpbrk(path_name, "0123");
  1815. if (!path_num_char) {
  1816. pr_err("%s: tx path index not found\n",
  1817. __func__);
  1818. ret = -EINVAL;
  1819. goto err;
  1820. }
  1821. ret = kstrtouint(path_num_char, 10, path_num);
  1822. if (ret < 0)
  1823. pr_err("%s: Invalid tx path = %s\n",
  1824. __func__, w_name);
  1825. err:
  1826. kfree(w_name);
  1827. return ret;
  1828. }
  1829. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  1830. struct snd_ctl_elem_value *ucontrol)
  1831. {
  1832. struct snd_soc_component *component =
  1833. snd_soc_kcontrol_component(kcontrol);
  1834. struct wcd938x_priv *wcd938x = NULL;
  1835. int ret = 0;
  1836. unsigned int path = 0;
  1837. if (!component)
  1838. return -EINVAL;
  1839. wcd938x = snd_soc_component_get_drvdata(component);
  1840. if (!wcd938x)
  1841. return -EINVAL;
  1842. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  1843. if (ret < 0)
  1844. return ret;
  1845. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  1846. return 0;
  1847. }
  1848. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  1849. struct snd_ctl_elem_value *ucontrol)
  1850. {
  1851. struct snd_soc_component *component =
  1852. snd_soc_kcontrol_component(kcontrol);
  1853. struct wcd938x_priv *wcd938x = NULL;
  1854. u32 mode_val;
  1855. unsigned int path = 0;
  1856. int ret = 0;
  1857. if (!component)
  1858. return -EINVAL;
  1859. wcd938x = snd_soc_component_get_drvdata(component);
  1860. if (!wcd938x)
  1861. return -EINVAL;
  1862. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  1863. if (ret)
  1864. return ret;
  1865. mode_val = ucontrol->value.enumerated.item[0];
  1866. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1867. wcd938x->tx_mode[path] = mode_val;
  1868. return 0;
  1869. }
  1870. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1871. struct snd_ctl_elem_value *ucontrol)
  1872. {
  1873. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1874. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1875. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  1876. return 0;
  1877. }
  1878. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1879. struct snd_ctl_elem_value *ucontrol)
  1880. {
  1881. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1882. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1883. u32 mode_val;
  1884. mode_val = ucontrol->value.enumerated.item[0];
  1885. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1886. if (wcd938x->variant == WCD9380) {
  1887. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  1888. dev_info(component->dev,
  1889. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  1890. __func__);
  1891. mode_val = CLS_H_ULP;
  1892. }
  1893. }
  1894. if (mode_val == CLS_H_NORMAL) {
  1895. dev_info(component->dev,
  1896. "%s:Invalid HPH Mode, default to class_AB\n",
  1897. __func__);
  1898. mode_val = CLS_H_ULP;
  1899. }
  1900. wcd938x->hph_mode = mode_val;
  1901. return 0;
  1902. }
  1903. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  1904. struct snd_ctl_elem_value *ucontrol)
  1905. {
  1906. struct snd_soc_component *component =
  1907. snd_soc_kcontrol_component(kcontrol);
  1908. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1909. bool hphr;
  1910. struct soc_multi_mixer_control *mc;
  1911. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1912. hphr = mc->shift;
  1913. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  1914. wcd938x->comp1_enable;
  1915. return 0;
  1916. }
  1917. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  1918. struct snd_ctl_elem_value *ucontrol)
  1919. {
  1920. struct snd_soc_component *component =
  1921. snd_soc_kcontrol_component(kcontrol);
  1922. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1923. int value = ucontrol->value.integer.value[0];
  1924. bool hphr;
  1925. struct soc_multi_mixer_control *mc;
  1926. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1927. hphr = mc->shift;
  1928. if (hphr)
  1929. wcd938x->comp2_enable = value;
  1930. else
  1931. wcd938x->comp1_enable = value;
  1932. return 0;
  1933. }
  1934. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  1935. struct snd_ctl_elem_value *ucontrol)
  1936. {
  1937. struct snd_soc_component *component =
  1938. snd_soc_kcontrol_component(kcontrol);
  1939. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1940. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  1941. return 0;
  1942. }
  1943. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  1944. struct snd_ctl_elem_value *ucontrol)
  1945. {
  1946. struct snd_soc_component *component =
  1947. snd_soc_kcontrol_component(kcontrol);
  1948. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1949. wcd938x->ldoh = ucontrol->value.integer.value[0];
  1950. return 0;
  1951. }
  1952. static const char * const tx_mode_mux_text_wcd9380[] = {
  1953. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  1954. };
  1955. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  1956. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  1957. tx_mode_mux_text_wcd9380);
  1958. static const char * const tx_mode_mux_text[] = {
  1959. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  1960. "ADC_ULP1", "ADC_ULP2",
  1961. };
  1962. static const struct soc_enum tx_mode_mux_enum =
  1963. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  1964. tx_mode_mux_text);
  1965. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  1966. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  1967. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  1968. "CLS_AB_LOHIFI",
  1969. };
  1970. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  1971. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  1972. rx_hph_mode_mux_text_wcd9380);
  1973. static const char * const rx_hph_mode_mux_text[] = {
  1974. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1975. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  1976. };
  1977. static const struct soc_enum rx_hph_mode_mux_enum =
  1978. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1979. rx_hph_mode_mux_text);
  1980. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  1981. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  1982. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  1983. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  1984. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1985. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  1986. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1987. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  1988. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1989. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  1990. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1991. };
  1992. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  1993. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1994. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  1995. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  1996. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1997. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  1998. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1999. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2000. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2001. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  2002. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2003. };
  2004. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  2005. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2006. wcd938x_get_compander, wcd938x_set_compander),
  2007. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2008. wcd938x_get_compander, wcd938x_set_compander),
  2009. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  2010. wcd938x_ldoh_get, wcd938x_ldoh_put),
  2011. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  2012. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  2013. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  2014. analog_gain),
  2015. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  2016. analog_gain),
  2017. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  2018. analog_gain),
  2019. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  2020. analog_gain),
  2021. };
  2022. static const struct snd_kcontrol_new adc1_switch[] = {
  2023. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2024. };
  2025. static const struct snd_kcontrol_new adc2_switch[] = {
  2026. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2027. };
  2028. static const struct snd_kcontrol_new adc3_switch[] = {
  2029. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2030. };
  2031. static const struct snd_kcontrol_new adc4_switch[] = {
  2032. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2033. };
  2034. static const struct snd_kcontrol_new dmic1_switch[] = {
  2035. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2036. };
  2037. static const struct snd_kcontrol_new dmic2_switch[] = {
  2038. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2039. };
  2040. static const struct snd_kcontrol_new dmic3_switch[] = {
  2041. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2042. };
  2043. static const struct snd_kcontrol_new dmic4_switch[] = {
  2044. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2045. };
  2046. static const struct snd_kcontrol_new dmic5_switch[] = {
  2047. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2048. };
  2049. static const struct snd_kcontrol_new dmic6_switch[] = {
  2050. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2051. };
  2052. static const struct snd_kcontrol_new dmic7_switch[] = {
  2053. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2054. };
  2055. static const struct snd_kcontrol_new dmic8_switch[] = {
  2056. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2057. };
  2058. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2059. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2060. };
  2061. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2062. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2063. };
  2064. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2065. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2066. };
  2067. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2068. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2069. };
  2070. static const char * const adc2_mux_text[] = {
  2071. "INP2", "INP3"
  2072. };
  2073. static const struct soc_enum adc2_enum =
  2074. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2075. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2076. static const struct snd_kcontrol_new tx_adc2_mux =
  2077. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2078. static const char * const adc3_mux_text[] = {
  2079. "INP4", "INP6"
  2080. };
  2081. static const struct soc_enum adc3_enum =
  2082. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2083. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2084. static const struct snd_kcontrol_new tx_adc3_mux =
  2085. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2086. static const char * const adc4_mux_text[] = {
  2087. "INP5", "INP7"
  2088. };
  2089. static const struct soc_enum adc4_enum =
  2090. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2091. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2092. static const struct snd_kcontrol_new tx_adc4_mux =
  2093. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2094. static const char * const rdac3_mux_text[] = {
  2095. "RX1", "RX3"
  2096. };
  2097. static const char * const hdr12_mux_text[] = {
  2098. "NO_HDR12", "HDR12"
  2099. };
  2100. static const struct soc_enum hdr12_enum =
  2101. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2102. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2103. static const struct snd_kcontrol_new tx_hdr12_mux =
  2104. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2105. static const char * const hdr34_mux_text[] = {
  2106. "NO_HDR34", "HDR34"
  2107. };
  2108. static const struct soc_enum hdr34_enum =
  2109. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2110. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2111. static const struct snd_kcontrol_new tx_hdr34_mux =
  2112. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2113. static const struct soc_enum rdac3_enum =
  2114. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2115. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2116. static const struct snd_kcontrol_new rx_rdac3_mux =
  2117. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2118. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2119. /*input widgets*/
  2120. SND_SOC_DAPM_INPUT("AMIC1"),
  2121. SND_SOC_DAPM_INPUT("AMIC2"),
  2122. SND_SOC_DAPM_INPUT("AMIC3"),
  2123. SND_SOC_DAPM_INPUT("AMIC4"),
  2124. SND_SOC_DAPM_INPUT("AMIC5"),
  2125. SND_SOC_DAPM_INPUT("AMIC6"),
  2126. SND_SOC_DAPM_INPUT("AMIC7"),
  2127. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2128. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2129. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2130. /*tx widgets*/
  2131. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2132. wcd938x_codec_enable_adc,
  2133. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2134. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2135. wcd938x_codec_enable_adc,
  2136. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2137. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2138. wcd938x_codec_enable_adc,
  2139. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2140. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  2141. wcd938x_codec_enable_adc,
  2142. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2143. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2144. wcd938x_codec_enable_dmic,
  2145. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2146. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2147. wcd938x_codec_enable_dmic,
  2148. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2149. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2150. wcd938x_codec_enable_dmic,
  2151. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2152. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2153. wcd938x_codec_enable_dmic,
  2154. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2155. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2156. wcd938x_codec_enable_dmic,
  2157. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2158. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2159. wcd938x_codec_enable_dmic,
  2160. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2161. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  2162. wcd938x_codec_enable_dmic,
  2163. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2164. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  2165. wcd938x_codec_enable_dmic,
  2166. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2167. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2168. NULL, 0, wcd938x_enable_req,
  2169. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2170. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  2171. NULL, 0, wcd938x_enable_req,
  2172. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2173. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  2174. NULL, 0, wcd938x_enable_req,
  2175. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2176. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  2177. NULL, 0, wcd938x_enable_req,
  2178. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2179. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2180. &tx_adc2_mux),
  2181. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2182. &tx_adc3_mux),
  2183. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  2184. &tx_adc4_mux),
  2185. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  2186. &tx_hdr12_mux),
  2187. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  2188. &tx_hdr34_mux),
  2189. /*tx mixers*/
  2190. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2191. adc1_switch, ARRAY_SIZE(adc1_switch),
  2192. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2193. SND_SOC_DAPM_POST_PMD),
  2194. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  2195. adc2_switch, ARRAY_SIZE(adc2_switch),
  2196. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2197. SND_SOC_DAPM_POST_PMD),
  2198. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  2199. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  2200. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2201. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
  2202. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  2203. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2204. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2205. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2206. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2207. SND_SOC_DAPM_POST_PMD),
  2208. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  2209. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2210. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2211. SND_SOC_DAPM_POST_PMD),
  2212. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  2213. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2214. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2215. SND_SOC_DAPM_POST_PMD),
  2216. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  2217. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2218. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2219. SND_SOC_DAPM_POST_PMD),
  2220. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  2221. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2222. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2223. SND_SOC_DAPM_POST_PMD),
  2224. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  2225. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2226. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2227. SND_SOC_DAPM_POST_PMD),
  2228. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0,
  2229. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  2230. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2231. SND_SOC_DAPM_POST_PMD),
  2232. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0,
  2233. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  2234. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2235. SND_SOC_DAPM_POST_PMD),
  2236. /* micbias widgets*/
  2237. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2238. wcd938x_codec_enable_micbias,
  2239. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2240. SND_SOC_DAPM_POST_PMD),
  2241. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2242. wcd938x_codec_enable_micbias,
  2243. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2244. SND_SOC_DAPM_POST_PMD),
  2245. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2246. wcd938x_codec_enable_micbias,
  2247. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2248. SND_SOC_DAPM_POST_PMD),
  2249. SND_SOC_DAPM_MICBIAS_E("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2250. wcd938x_codec_enable_micbias,
  2251. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2252. SND_SOC_DAPM_POST_PMD),
  2253. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2254. wcd938x_enable_clsh,
  2255. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2256. /*rx widgets*/
  2257. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  2258. wcd938x_codec_enable_ear_pa,
  2259. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2260. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2261. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  2262. wcd938x_codec_enable_aux_pa,
  2263. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2264. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2265. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  2266. wcd938x_codec_enable_hphl_pa,
  2267. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2268. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2269. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  2270. wcd938x_codec_enable_hphr_pa,
  2271. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2272. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2273. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2274. wcd938x_codec_hphl_dac_event,
  2275. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2276. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2277. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2278. wcd938x_codec_hphr_dac_event,
  2279. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2280. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2281. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2282. wcd938x_codec_ear_dac_event,
  2283. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2284. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2285. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2286. wcd938x_codec_aux_dac_event,
  2287. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2288. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2289. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2290. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2291. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2292. SND_SOC_DAPM_POST_PMD),
  2293. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2294. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2295. SND_SOC_DAPM_POST_PMD),
  2296. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2297. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2298. SND_SOC_DAPM_POST_PMD),
  2299. /* rx mixer widgets*/
  2300. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2301. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2302. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2303. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2304. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2305. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2306. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2307. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2308. /*output widgets tx*/
  2309. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  2310. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  2311. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  2312. SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
  2313. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  2314. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  2315. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  2316. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  2317. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  2318. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  2319. SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
  2320. SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
  2321. /*output widgets rx*/
  2322. SND_SOC_DAPM_OUTPUT("EAR"),
  2323. SND_SOC_DAPM_OUTPUT("AUX"),
  2324. SND_SOC_DAPM_OUTPUT("HPHL"),
  2325. SND_SOC_DAPM_OUTPUT("HPHR"),
  2326. /* micbias pull up widgets*/
  2327. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2328. wcd938x_codec_enable_micbias_pullup,
  2329. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2330. SND_SOC_DAPM_POST_PMD),
  2331. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2332. wcd938x_codec_enable_micbias_pullup,
  2333. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2334. SND_SOC_DAPM_POST_PMD),
  2335. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2336. wcd938x_codec_enable_micbias_pullup,
  2337. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2338. SND_SOC_DAPM_POST_PMD),
  2339. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2340. wcd938x_codec_enable_micbias_pullup,
  2341. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2342. SND_SOC_DAPM_POST_PMD),
  2343. };
  2344. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  2345. {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
  2346. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2347. {"ADC1 REQ", NULL, "ADC1"},
  2348. {"ADC1", NULL, "AMIC1"},
  2349. {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
  2350. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2351. {"ADC2 REQ", NULL, "ADC2"},
  2352. {"ADC2", NULL, "HDR12 MUX"},
  2353. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  2354. {"HDR12 MUX", "HDR12", "AMIC1"},
  2355. {"ADC2 MUX", "INP3", "AMIC3"},
  2356. {"ADC2 MUX", "INP2", "AMIC2"},
  2357. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  2358. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2359. {"ADC3 REQ", NULL, "ADC3"},
  2360. {"ADC3", NULL, "HDR34 MUX"},
  2361. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  2362. {"HDR34 MUX", "HDR34", "AMIC5"},
  2363. {"ADC3 MUX", "INP4", "AMIC4"},
  2364. {"ADC3 MUX", "INP6", "AMIC6"},
  2365. {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
  2366. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  2367. {"ADC4 REQ", NULL, "ADC4"},
  2368. {"ADC4", NULL, "ADC4 MUX"},
  2369. {"ADC4 MUX", "INP5", "AMIC5"},
  2370. {"ADC4 MUX", "INP7", "AMIC7"},
  2371. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  2372. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2373. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  2374. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2375. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  2376. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2377. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  2378. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2379. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  2380. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2381. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  2382. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2383. {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
  2384. {"DMIC7_MIXER", "Switch", "DMIC7"},
  2385. {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
  2386. {"DMIC8_MIXER", "Switch", "DMIC8"},
  2387. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2388. {"RX1", NULL, "IN1_HPHL"},
  2389. {"RDAC1", NULL, "RX1"},
  2390. {"HPHL_RDAC", "Switch", "RDAC1"},
  2391. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2392. {"HPHL", NULL, "HPHL PGA"},
  2393. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2394. {"RX2", NULL, "IN2_HPHR"},
  2395. {"RDAC2", NULL, "RX2"},
  2396. {"HPHR_RDAC", "Switch", "RDAC2"},
  2397. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2398. {"HPHR", NULL, "HPHR PGA"},
  2399. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2400. {"RX3", NULL, "IN3_AUX"},
  2401. {"RDAC4", NULL, "RX3"},
  2402. {"AUX_RDAC", "Switch", "RDAC4"},
  2403. {"AUX PGA", NULL, "AUX_RDAC"},
  2404. {"AUX", NULL, "AUX PGA"},
  2405. {"RDAC3_MUX", "RX3", "RX3"},
  2406. {"RDAC3_MUX", "RX1", "RX1"},
  2407. {"RDAC3", NULL, "RDAC3_MUX"},
  2408. {"EAR_RDAC", "Switch", "RDAC3"},
  2409. {"EAR PGA", NULL, "EAR_RDAC"},
  2410. {"EAR", NULL, "EAR PGA"},
  2411. };
  2412. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  2413. void *file_private_data,
  2414. struct file *file,
  2415. char __user *buf, size_t count,
  2416. loff_t pos)
  2417. {
  2418. struct wcd938x_priv *priv;
  2419. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  2420. int len = 0;
  2421. priv = (struct wcd938x_priv *) entry->private_data;
  2422. if (!priv) {
  2423. pr_err("%s: wcd938x priv is null\n", __func__);
  2424. return -EINVAL;
  2425. }
  2426. switch (priv->version) {
  2427. case WCD938X_VERSION_1_0:
  2428. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  2429. break;
  2430. default:
  2431. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2432. }
  2433. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2434. }
  2435. static struct snd_info_entry_ops wcd938x_info_ops = {
  2436. .read = wcd938x_version_read,
  2437. };
  2438. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  2439. void *file_private_data,
  2440. struct file *file,
  2441. char __user *buf, size_t count,
  2442. loff_t pos)
  2443. {
  2444. struct wcd938x_priv *priv;
  2445. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  2446. int len = 0;
  2447. priv = (struct wcd938x_priv *) entry->private_data;
  2448. if (!priv) {
  2449. pr_err("%s: wcd938x priv is null\n", __func__);
  2450. return -EINVAL;
  2451. }
  2452. switch (priv->variant) {
  2453. case WCD9380:
  2454. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  2455. break;
  2456. case WCD9385:
  2457. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  2458. break;
  2459. default:
  2460. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2461. }
  2462. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2463. }
  2464. static struct snd_info_entry_ops wcd938x_variant_ops = {
  2465. .read = wcd938x_variant_read,
  2466. };
  2467. /*
  2468. * wcd938x_get_codec_variant
  2469. * @component: component instance
  2470. *
  2471. * Return: codec variant or -EINVAL in error.
  2472. */
  2473. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  2474. {
  2475. struct wcd938x_priv *priv = NULL;
  2476. if (!component)
  2477. return -EINVAL;
  2478. priv = snd_soc_component_get_drvdata(component);
  2479. if (!priv) {
  2480. dev_err(component->dev,
  2481. "%s:wcd938x not probed\n", __func__);
  2482. return 0;
  2483. }
  2484. return priv->variant;
  2485. }
  2486. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  2487. /*
  2488. * wcd938x_info_create_codec_entry - creates wcd938x module
  2489. * @codec_root: The parent directory
  2490. * @component: component instance
  2491. *
  2492. * Creates wcd938x module, variant and version entry under the given
  2493. * parent directory.
  2494. *
  2495. * Return: 0 on success or negative error code on failure.
  2496. */
  2497. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2498. struct snd_soc_component *component)
  2499. {
  2500. struct snd_info_entry *version_entry;
  2501. struct snd_info_entry *variant_entry;
  2502. struct wcd938x_priv *priv;
  2503. struct snd_soc_card *card;
  2504. if (!codec_root || !component)
  2505. return -EINVAL;
  2506. priv = snd_soc_component_get_drvdata(component);
  2507. if (priv->entry) {
  2508. dev_dbg(priv->dev,
  2509. "%s:wcd938x module already created\n", __func__);
  2510. return 0;
  2511. }
  2512. card = component->card;
  2513. priv->entry = snd_info_create_subdir(codec_root->module,
  2514. "wcd938x", codec_root);
  2515. if (!priv->entry) {
  2516. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  2517. __func__);
  2518. return -ENOMEM;
  2519. }
  2520. version_entry = snd_info_create_card_entry(card->snd_card,
  2521. "version",
  2522. priv->entry);
  2523. if (!version_entry) {
  2524. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  2525. __func__);
  2526. return -ENOMEM;
  2527. }
  2528. version_entry->private_data = priv;
  2529. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  2530. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2531. version_entry->c.ops = &wcd938x_info_ops;
  2532. if (snd_info_register(version_entry) < 0) {
  2533. snd_info_free_entry(version_entry);
  2534. return -ENOMEM;
  2535. }
  2536. priv->version_entry = version_entry;
  2537. variant_entry = snd_info_create_card_entry(card->snd_card,
  2538. "variant",
  2539. priv->entry);
  2540. if (!variant_entry) {
  2541. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  2542. __func__);
  2543. return -ENOMEM;
  2544. }
  2545. variant_entry->private_data = priv;
  2546. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  2547. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2548. variant_entry->c.ops = &wcd938x_variant_ops;
  2549. if (snd_info_register(variant_entry) < 0) {
  2550. snd_info_free_entry(variant_entry);
  2551. return -ENOMEM;
  2552. }
  2553. priv->variant_entry = variant_entry;
  2554. return 0;
  2555. }
  2556. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  2557. static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x,
  2558. struct wcd938x_pdata *pdata)
  2559. {
  2560. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  2561. int rc = 0;
  2562. if (!pdata) {
  2563. dev_err(wcd938x->dev, "%s: NULL pdata\n", __func__);
  2564. return -ENODEV;
  2565. }
  2566. /* set micbias voltage */
  2567. vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2568. vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2569. vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2570. vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  2571. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  2572. vout_ctl_4 < 0) {
  2573. rc = -EINVAL;
  2574. goto done;
  2575. }
  2576. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 0x3F,
  2577. vout_ctl_1);
  2578. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 0x3F,
  2579. vout_ctl_2);
  2580. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 0x3F,
  2581. vout_ctl_3);
  2582. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 0x3F,
  2583. vout_ctl_4);
  2584. done:
  2585. return rc;
  2586. }
  2587. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  2588. {
  2589. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2590. struct snd_soc_dapm_context *dapm =
  2591. snd_soc_component_get_dapm(component);
  2592. int variant;
  2593. int ret = -EINVAL;
  2594. dev_info(component->dev, "%s()\n", __func__);
  2595. wcd938x = snd_soc_component_get_drvdata(component);
  2596. if (!wcd938x)
  2597. return -EINVAL;
  2598. wcd938x->component = component;
  2599. snd_soc_component_init_regmap(component, wcd938x->regmap);
  2600. variant = (snd_soc_component_read32(component,
  2601. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2602. wcd938x->variant = variant;
  2603. wcd938x->fw_data = devm_kzalloc(component->dev,
  2604. sizeof(*(wcd938x->fw_data)),
  2605. GFP_KERNEL);
  2606. if (!wcd938x->fw_data) {
  2607. dev_err(component->dev, "Failed to allocate fw_data\n");
  2608. ret = -ENOMEM;
  2609. goto err;
  2610. }
  2611. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  2612. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  2613. WCD9XXX_CODEC_HWDEP_NODE, component);
  2614. if (ret < 0) {
  2615. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2616. goto err_hwdep;
  2617. }
  2618. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  2619. if (ret) {
  2620. pr_err("%s: mbhc initialization failed\n", __func__);
  2621. goto err_hwdep;
  2622. }
  2623. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2624. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2625. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2626. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2627. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  2628. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  2629. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  2630. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2631. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2632. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2633. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2634. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2635. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2636. snd_soc_dapm_ignore_suspend(dapm, "DMIC7_OUTPUT");
  2637. snd_soc_dapm_ignore_suspend(dapm, "DMIC8_OUTPUT");
  2638. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2639. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2640. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2641. snd_soc_dapm_ignore_suspend(dapm, "ADC4_OUTPUT");
  2642. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2643. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2644. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2645. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2646. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2647. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2648. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2649. snd_soc_dapm_sync(dapm);
  2650. wcd_cls_h_init(&wcd938x->clsh_info);
  2651. wcd938x_init_reg(component);
  2652. if (wcd938x->variant == WCD9380) {
  2653. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  2654. ARRAY_SIZE(wcd9380_snd_controls));
  2655. if (ret < 0) {
  2656. dev_err(component->dev,
  2657. "%s: Failed to add snd ctrls for variant: %d\n",
  2658. __func__, wcd938x->variant);
  2659. goto err_hwdep;
  2660. }
  2661. }
  2662. if (wcd938x->variant == WCD9385) {
  2663. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  2664. ARRAY_SIZE(wcd9385_snd_controls));
  2665. if (ret < 0) {
  2666. dev_err(component->dev,
  2667. "%s: Failed to add snd ctrls for variant: %d\n",
  2668. __func__, wcd938x->variant);
  2669. goto err_hwdep;
  2670. }
  2671. }
  2672. wcd938x->version = WCD938X_VERSION_1_0;
  2673. /* Register event notifier */
  2674. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  2675. if (wcd938x->register_notifier) {
  2676. ret = wcd938x->register_notifier(wcd938x->handle,
  2677. &wcd938x->nblock,
  2678. true);
  2679. if (ret) {
  2680. dev_err(component->dev,
  2681. "%s: Failed to register notifier %d\n",
  2682. __func__, ret);
  2683. return ret;
  2684. }
  2685. }
  2686. return ret;
  2687. err_hwdep:
  2688. wcd938x->fw_data = NULL;
  2689. err:
  2690. return ret;
  2691. }
  2692. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  2693. {
  2694. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2695. if (!wcd938x) {
  2696. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  2697. __func__);
  2698. return;
  2699. }
  2700. if (wcd938x->register_notifier)
  2701. wcd938x->register_notifier(wcd938x->handle,
  2702. &wcd938x->nblock,
  2703. false);
  2704. }
  2705. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  2706. .name = WCD938X_DRV_NAME,
  2707. .probe = wcd938x_soc_codec_probe,
  2708. .remove = wcd938x_soc_codec_remove,
  2709. .controls = wcd938x_snd_controls,
  2710. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  2711. .dapm_widgets = wcd938x_dapm_widgets,
  2712. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  2713. .dapm_routes = wcd938x_audio_map,
  2714. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  2715. };
  2716. static int wcd938x_reset(struct device *dev)
  2717. {
  2718. struct wcd938x_priv *wcd938x = NULL;
  2719. int rc = 0;
  2720. int value = 0;
  2721. if (!dev)
  2722. return -ENODEV;
  2723. wcd938x = dev_get_drvdata(dev);
  2724. if (!wcd938x)
  2725. return -EINVAL;
  2726. if (!wcd938x->rst_np) {
  2727. dev_err(dev, "%s: reset gpio device node not specified\n",
  2728. __func__);
  2729. return -EINVAL;
  2730. }
  2731. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  2732. if (value > 0)
  2733. return 0;
  2734. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2735. if (rc) {
  2736. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2737. __func__);
  2738. return rc;
  2739. }
  2740. /* 20us sleep required after pulling the reset gpio to LOW */
  2741. usleep_range(20, 30);
  2742. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  2743. if (rc) {
  2744. dev_err(dev, "%s: wcd active state request fail!\n",
  2745. __func__);
  2746. return rc;
  2747. }
  2748. /* 20us sleep required after pulling the reset gpio to HIGH */
  2749. usleep_range(20, 30);
  2750. return rc;
  2751. }
  2752. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  2753. u32 *val)
  2754. {
  2755. int rc = 0;
  2756. rc = of_property_read_u32(dev->of_node, name, val);
  2757. if (rc)
  2758. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2759. __func__, name, dev->of_node->full_name);
  2760. return rc;
  2761. }
  2762. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  2763. struct wcd938x_micbias_setting *mb)
  2764. {
  2765. u32 prop_val = 0;
  2766. int rc = 0;
  2767. /* MB1 */
  2768. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2769. NULL)) {
  2770. rc = wcd938x_read_of_property_u32(dev,
  2771. "qcom,cdc-micbias1-mv",
  2772. &prop_val);
  2773. if (!rc)
  2774. mb->micb1_mv = prop_val;
  2775. } else {
  2776. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2777. __func__);
  2778. }
  2779. /* MB2 */
  2780. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2781. NULL)) {
  2782. rc = wcd938x_read_of_property_u32(dev,
  2783. "qcom,cdc-micbias2-mv",
  2784. &prop_val);
  2785. if (!rc)
  2786. mb->micb2_mv = prop_val;
  2787. } else {
  2788. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2789. __func__);
  2790. }
  2791. /* MB3 */
  2792. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2793. NULL)) {
  2794. rc = wcd938x_read_of_property_u32(dev,
  2795. "qcom,cdc-micbias3-mv",
  2796. &prop_val);
  2797. if (!rc)
  2798. mb->micb3_mv = prop_val;
  2799. } else {
  2800. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2801. __func__);
  2802. }
  2803. /* MB4 */
  2804. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  2805. NULL)) {
  2806. rc = wcd938x_read_of_property_u32(dev,
  2807. "qcom,cdc-micbias4-mv",
  2808. &prop_val);
  2809. if (!rc)
  2810. mb->micb4_mv = prop_val;
  2811. } else {
  2812. dev_info(dev, "%s: Micbias4 DT property not found\n",
  2813. __func__);
  2814. }
  2815. }
  2816. static int wcd938x_reset_low(struct device *dev)
  2817. {
  2818. struct wcd938x_priv *wcd938x = NULL;
  2819. int rc = 0;
  2820. if (!dev)
  2821. return -ENODEV;
  2822. wcd938x = dev_get_drvdata(dev);
  2823. if (!wcd938x)
  2824. return -EINVAL;
  2825. if (!wcd938x->rst_np) {
  2826. dev_err(dev, "%s: reset gpio device node not specified\n",
  2827. __func__);
  2828. return -EINVAL;
  2829. }
  2830. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2831. if (rc) {
  2832. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2833. __func__);
  2834. return rc;
  2835. }
  2836. /* 20us sleep required after pulling the reset gpio to LOW */
  2837. usleep_range(20, 30);
  2838. return rc;
  2839. }
  2840. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  2841. {
  2842. struct wcd938x_pdata *pdata = NULL;
  2843. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  2844. GFP_KERNEL);
  2845. if (!pdata)
  2846. return NULL;
  2847. pdata->rst_np = of_parse_phandle(dev->of_node,
  2848. "qcom,wcd-rst-gpio-node", 0);
  2849. if (!pdata->rst_np) {
  2850. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2851. __func__, "qcom,wcd-rst-gpio-node",
  2852. dev->of_node->full_name);
  2853. return NULL;
  2854. }
  2855. /* Parse power supplies */
  2856. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2857. &pdata->num_supplies);
  2858. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2859. dev_err(dev, "%s: no power supplies defined for codec\n",
  2860. __func__);
  2861. return NULL;
  2862. }
  2863. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2864. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2865. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  2866. return pdata;
  2867. }
  2868. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  2869. {
  2870. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2871. __func__, irq);
  2872. return IRQ_HANDLED;
  2873. }
  2874. static int wcd938x_bind(struct device *dev)
  2875. {
  2876. int ret = 0, i = 0;
  2877. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  2878. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2879. /*
  2880. * Add 5msec delay to provide sufficient time for
  2881. * soundwire auto enumeration of slave devices as
  2882. * as per HW requirement.
  2883. */
  2884. usleep_range(5000, 5010);
  2885. ret = component_bind_all(dev, wcd938x);
  2886. if (ret) {
  2887. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2888. __func__, ret);
  2889. return ret;
  2890. }
  2891. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2892. if (!wcd938x->rx_swr_dev) {
  2893. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2894. __func__);
  2895. ret = -ENODEV;
  2896. goto err;
  2897. }
  2898. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2899. if (!wcd938x->tx_swr_dev) {
  2900. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2901. __func__);
  2902. ret = -ENODEV;
  2903. goto err;
  2904. }
  2905. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  2906. &wcd938x_regmap_config);
  2907. if (!wcd938x->regmap) {
  2908. dev_err(dev, "%s: Regmap init failed\n",
  2909. __func__);
  2910. goto err;
  2911. }
  2912. /* Set all interupts as edge triggered */
  2913. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  2914. regmap_write(wcd938x->regmap,
  2915. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2916. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  2917. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  2918. wcd938x->irq_info.codec_name = "WCD938X";
  2919. wcd938x->irq_info.regmap = wcd938x->regmap;
  2920. wcd938x->irq_info.dev = dev;
  2921. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  2922. if (ret) {
  2923. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  2924. __func__, ret);
  2925. goto err;
  2926. }
  2927. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  2928. ret = wcd938x_set_micbias_data(wcd938x, pdata);
  2929. if (ret < 0) {
  2930. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  2931. goto err_irq;
  2932. }
  2933. /* Request for watchdog interrupt */
  2934. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  2935. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  2936. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  2937. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  2938. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  2939. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  2940. /* Disable watchdog interrupt for HPH and AUX */
  2941. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  2942. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  2943. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  2944. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  2945. NULL, 0);
  2946. if (ret) {
  2947. dev_err(dev, "%s: Codec registration failed\n",
  2948. __func__);
  2949. goto err_irq;
  2950. }
  2951. return ret;
  2952. err_irq:
  2953. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2954. err:
  2955. component_unbind_all(dev, wcd938x);
  2956. return ret;
  2957. }
  2958. static void wcd938x_unbind(struct device *dev)
  2959. {
  2960. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2961. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  2962. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  2963. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  2964. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2965. snd_soc_unregister_component(dev);
  2966. component_unbind_all(dev, wcd938x);
  2967. }
  2968. static const struct of_device_id wcd938x_dt_match[] = {
  2969. { .compatible = "qcom,wcd938x-codec" },
  2970. {}
  2971. };
  2972. static const struct component_master_ops wcd938x_comp_ops = {
  2973. .bind = wcd938x_bind,
  2974. .unbind = wcd938x_unbind,
  2975. };
  2976. static int wcd938x_compare_of(struct device *dev, void *data)
  2977. {
  2978. return dev->of_node == data;
  2979. }
  2980. static void wcd938x_release_of(struct device *dev, void *data)
  2981. {
  2982. of_node_put(data);
  2983. }
  2984. static int wcd938x_add_slave_components(struct device *dev,
  2985. struct component_match **matchptr)
  2986. {
  2987. struct device_node *np, *rx_node, *tx_node;
  2988. np = dev->of_node;
  2989. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2990. if (!rx_node) {
  2991. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2992. return -ENODEV;
  2993. }
  2994. of_node_get(rx_node);
  2995. component_match_add_release(dev, matchptr,
  2996. wcd938x_release_of,
  2997. wcd938x_compare_of,
  2998. rx_node);
  2999. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3000. if (!tx_node) {
  3001. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3002. return -ENODEV;
  3003. }
  3004. of_node_get(tx_node);
  3005. component_match_add_release(dev, matchptr,
  3006. wcd938x_release_of,
  3007. wcd938x_compare_of,
  3008. tx_node);
  3009. return 0;
  3010. }
  3011. static int wcd938x_wakeup(void *handle, bool enable)
  3012. {
  3013. struct wcd938x_priv *priv;
  3014. if (!handle) {
  3015. pr_err("%s: NULL handle\n", __func__);
  3016. return -EINVAL;
  3017. }
  3018. priv = (struct wcd938x_priv *)handle;
  3019. if (!priv->tx_swr_dev) {
  3020. pr_err("%s: tx swr dev is NULL\n", __func__);
  3021. return -EINVAL;
  3022. }
  3023. if (enable)
  3024. return swr_device_wakeup_vote(priv->tx_swr_dev);
  3025. else
  3026. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  3027. }
  3028. static int wcd938x_probe(struct platform_device *pdev)
  3029. {
  3030. struct component_match *match = NULL;
  3031. struct wcd938x_priv *wcd938x = NULL;
  3032. struct wcd938x_pdata *pdata = NULL;
  3033. struct wcd_ctrl_platform_data *plat_data = NULL;
  3034. struct device *dev = &pdev->dev;
  3035. int ret;
  3036. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  3037. GFP_KERNEL);
  3038. if (!wcd938x)
  3039. return -ENOMEM;
  3040. dev_set_drvdata(dev, wcd938x);
  3041. wcd938x->dev = dev;
  3042. pdata = wcd938x_populate_dt_data(dev);
  3043. if (!pdata) {
  3044. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3045. return -EINVAL;
  3046. }
  3047. dev->platform_data = pdata;
  3048. wcd938x->rst_np = pdata->rst_np;
  3049. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  3050. pdata->regulator, pdata->num_supplies);
  3051. if (!wcd938x->supplies) {
  3052. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3053. __func__);
  3054. return ret;
  3055. }
  3056. plat_data = dev_get_platdata(dev->parent);
  3057. if (!plat_data) {
  3058. dev_err(dev, "%s: platform data from parent is NULL\n",
  3059. __func__);
  3060. return -EINVAL;
  3061. }
  3062. wcd938x->handle = (void *)plat_data->handle;
  3063. if (!wcd938x->handle) {
  3064. dev_err(dev, "%s: handle is NULL\n", __func__);
  3065. return -EINVAL;
  3066. }
  3067. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  3068. if (!wcd938x->update_wcd_event) {
  3069. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3070. __func__);
  3071. return -EINVAL;
  3072. }
  3073. wcd938x->register_notifier = plat_data->register_notifier;
  3074. if (!wcd938x->register_notifier) {
  3075. dev_err(dev, "%s: register_notifier api is null!\n",
  3076. __func__);
  3077. return -EINVAL;
  3078. }
  3079. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  3080. pdata->regulator,
  3081. pdata->num_supplies);
  3082. if (ret) {
  3083. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3084. __func__);
  3085. return ret;
  3086. }
  3087. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3088. CODEC_RX);
  3089. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3090. CODEC_TX);
  3091. if (ret) {
  3092. dev_err(dev, "Failed to read port mapping\n");
  3093. goto err;
  3094. }
  3095. mutex_init(&wcd938x->micb_lock);
  3096. ret = wcd938x_add_slave_components(dev, &match);
  3097. if (ret)
  3098. goto err_lock_init;
  3099. wcd938x_reset(dev);
  3100. wcd938x->wakeup = wcd938x_wakeup;
  3101. return component_master_add_with_match(dev,
  3102. &wcd938x_comp_ops, match);
  3103. err_lock_init:
  3104. mutex_destroy(&wcd938x->micb_lock);
  3105. err:
  3106. return ret;
  3107. }
  3108. static int wcd938x_remove(struct platform_device *pdev)
  3109. {
  3110. struct wcd938x_priv *wcd938x = NULL;
  3111. wcd938x = platform_get_drvdata(pdev);
  3112. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  3113. mutex_destroy(&wcd938x->micb_lock);
  3114. dev_set_drvdata(&pdev->dev, NULL);
  3115. return 0;
  3116. }
  3117. #ifdef CONFIG_PM_SLEEP
  3118. static int wcd938x_suspend(struct device *dev)
  3119. {
  3120. return 0;
  3121. }
  3122. static int wcd938x_resume(struct device *dev)
  3123. {
  3124. return 0;
  3125. }
  3126. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  3127. SET_SYSTEM_SLEEP_PM_OPS(
  3128. wcd938x_suspend,
  3129. wcd938x_resume
  3130. )
  3131. };
  3132. #endif
  3133. static struct platform_driver wcd938x_codec_driver = {
  3134. .probe = wcd938x_probe,
  3135. .remove = wcd938x_remove,
  3136. .driver = {
  3137. .name = "wcd938x_codec",
  3138. .owner = THIS_MODULE,
  3139. .of_match_table = of_match_ptr(wcd938x_dt_match),
  3140. #ifdef CONFIG_PM_SLEEP
  3141. .pm = &wcd938x_dev_pm_ops,
  3142. #endif
  3143. .suppress_bind_attrs = true,
  3144. },
  3145. };
  3146. module_platform_driver(wcd938x_codec_driver);
  3147. MODULE_DESCRIPTION("WCD938X Codec driver");
  3148. MODULE_LICENSE("GPL v2");