dp_aux.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #include <linux/delay.h>
  7. #if IS_ENABLED(CONFIG_QCOM_FSA4480_I2C)
  8. #include <linux/soc/qcom/fsa4480-i2c.h>
  9. #elif IS_ENABLED(CONFIG_QCOM_WCD939X_I2C)
  10. #include <linux/soc/qcom/wcd939x-i2c.h>
  11. #endif
  12. #include "dp_aux.h"
  13. #include "dp_hpd.h"
  14. #include "dp_debug.h"
  15. #define DP_AUX_ENUM_STR(x) #x
  16. #define DP_AUX_IPC_NUM_PAGES 10
  17. #define DP_AUX_DEBUG(dp_aux, fmt, ...) \
  18. do { \
  19. if (dp_aux) \
  20. ipc_log_string(dp_aux->ipc_log_context, "[d][%-4d]"fmt,\
  21. current->pid, ##__VA_ARGS__); \
  22. DP_DEBUG_V(fmt, ##__VA_ARGS__); \
  23. } while (0)
  24. #define DP_AUX_WARN(dp_aux, fmt, ...) \
  25. do { \
  26. if (dp_aux) \
  27. ipc_log_string(dp_aux->ipc_log_context, "[w][%-4d]"fmt,\
  28. current->pid, ##__VA_ARGS__); \
  29. DP_WARN_V(fmt, ##__VA_ARGS__); \
  30. } while (0)
  31. #define DP_AUX_ERR(dp_aux, fmt, ...) \
  32. do { \
  33. if (dp_aux) \
  34. ipc_log_string(dp_aux->ipc_log_context, "[e][%-4d]"fmt,\
  35. current->pid, ##__VA_ARGS__); \
  36. DP_ERR_V(fmt, ##__VA_ARGS__); \
  37. } while (0)
  38. #define DP_AUX_ERR_RATELIMITED(dp_aux, fmt, ...) \
  39. do { \
  40. if (dp_aux) \
  41. ipc_log_string(dp_aux->ipc_log_context, "[e][%-4d]"fmt,\
  42. current->pid, ##__VA_ARGS__); \
  43. DP_ERR_RATELIMITED_V(fmt, ##__VA_ARGS__); \
  44. } while (0)
  45. enum {
  46. DP_AUX_DATA_INDEX_WRITE = BIT(31),
  47. };
  48. struct dp_aux_private {
  49. struct device *dev;
  50. struct dp_aux dp_aux;
  51. struct dp_catalog_aux *catalog;
  52. struct dp_aux_cfg *cfg;
  53. struct device_node *aux_switch_node;
  54. struct mutex mutex;
  55. struct completion comp;
  56. struct drm_dp_aux drm_aux;
  57. struct dp_aux_bridge *aux_bridge;
  58. struct dp_aux_bridge *sim_bridge;
  59. bool bridge_in_transfer;
  60. bool sim_in_transfer;
  61. bool cmd_busy;
  62. bool native;
  63. bool read;
  64. bool no_send_addr;
  65. bool no_send_stop;
  66. bool enabled;
  67. u32 offset;
  68. u32 segment;
  69. u32 aux_error_num;
  70. u32 retry_cnt;
  71. atomic_t aborted;
  72. };
  73. #if IS_ENABLED(CONFIG_DYNAMIC_DEBUG)
  74. static void dp_aux_hex_dump(struct drm_dp_aux *drm_aux,
  75. struct drm_dp_aux_msg *msg)
  76. {
  77. char prefix[64];
  78. int i, linelen, remaining = msg->size;
  79. const int rowsize = 16;
  80. u8 linebuf[64];
  81. struct dp_aux_private *aux = container_of(drm_aux,
  82. struct dp_aux_private, drm_aux);
  83. struct dp_aux *dp_aux = &aux->dp_aux;
  84. snprintf(prefix, sizeof(prefix), "%s %s %4xh(%2zu): ",
  85. (msg->request & DP_AUX_I2C_MOT) ? "I2C" : "NAT",
  86. (msg->request & DP_AUX_I2C_READ) ? "RD" : "WR",
  87. msg->address, msg->size);
  88. for (i = 0; i < msg->size; i += rowsize) {
  89. linelen = min(remaining, rowsize);
  90. remaining -= rowsize;
  91. hex_dump_to_buffer(msg->buffer + i, linelen, rowsize, 1,
  92. linebuf, sizeof(linebuf), false);
  93. if (msg->size == 1 && msg->address == 0)
  94. DP_DEBUG_V("%s%s\n", prefix, linebuf);
  95. else
  96. DP_AUX_DEBUG(dp_aux, "%s%s\n", prefix, linebuf);
  97. }
  98. }
  99. #else
  100. static void dp_aux_hex_dump(struct drm_dp_aux *drm_aux,
  101. struct drm_dp_aux_msg *msg)
  102. {
  103. }
  104. #endif /* CONFIG_DYNAMIC_DEBUG */
  105. static char *dp_aux_get_error(u32 aux_error)
  106. {
  107. switch (aux_error) {
  108. case DP_AUX_ERR_NONE:
  109. return DP_AUX_ENUM_STR(DP_AUX_ERR_NONE);
  110. case DP_AUX_ERR_ADDR:
  111. return DP_AUX_ENUM_STR(DP_AUX_ERR_ADDR);
  112. case DP_AUX_ERR_TOUT:
  113. return DP_AUX_ENUM_STR(DP_AUX_ERR_TOUT);
  114. case DP_AUX_ERR_NACK:
  115. return DP_AUX_ENUM_STR(DP_AUX_ERR_NACK);
  116. case DP_AUX_ERR_DEFER:
  117. return DP_AUX_ENUM_STR(DP_AUX_ERR_DEFER);
  118. case DP_AUX_ERR_NACK_DEFER:
  119. return DP_AUX_ENUM_STR(DP_AUX_ERR_NACK_DEFER);
  120. default:
  121. return "unknown";
  122. }
  123. }
  124. static u32 dp_aux_write(struct dp_aux_private *aux,
  125. struct drm_dp_aux_msg *msg)
  126. {
  127. u32 data[4], reg, len;
  128. u8 *msgdata = msg->buffer;
  129. int const aux_cmd_fifo_len = 128;
  130. int i = 0;
  131. struct dp_aux *dp_aux = &aux->dp_aux;
  132. if (aux->read)
  133. len = 4;
  134. else
  135. len = msg->size + 4;
  136. /*
  137. * cmd fifo only has depth of 144 bytes
  138. * limit buf length to 128 bytes here
  139. */
  140. if (len > aux_cmd_fifo_len) {
  141. DP_AUX_ERR(dp_aux, "buf len error\n");
  142. return 0;
  143. }
  144. /* Pack cmd and write to HW */
  145. data[0] = (msg->address >> 16) & 0xf; /* addr[19:16] */
  146. if (aux->read)
  147. data[0] |= BIT(4); /* R/W */
  148. data[1] = (msg->address >> 8) & 0xff; /* addr[15:8] */
  149. data[2] = msg->address & 0xff; /* addr[7:0] */
  150. data[3] = (msg->size - 1) & 0xff; /* len[7:0] */
  151. for (i = 0; i < len; i++) {
  152. reg = (i < 4) ? data[i] : msgdata[i - 4];
  153. reg = ((reg) << 8) & 0x0000ff00; /* index = 0, write */
  154. if (i == 0)
  155. reg |= DP_AUX_DATA_INDEX_WRITE;
  156. aux->catalog->data = reg;
  157. aux->catalog->write_data(aux->catalog);
  158. }
  159. aux->catalog->clear_trans(aux->catalog, false);
  160. aux->catalog->clear_hw_interrupts(aux->catalog);
  161. reg = 0; /* Transaction number == 1 */
  162. if (!aux->native) { /* i2c */
  163. reg |= BIT(8);
  164. if (aux->no_send_addr)
  165. reg |= BIT(10);
  166. if (aux->no_send_stop)
  167. reg |= BIT(11);
  168. }
  169. reg |= BIT(9);
  170. aux->catalog->data = reg;
  171. aux->catalog->write_trans(aux->catalog);
  172. return len;
  173. }
  174. static int dp_aux_cmd_fifo_tx(struct dp_aux_private *aux,
  175. struct drm_dp_aux_msg *msg)
  176. {
  177. u32 ret = 0, len = 0, timeout;
  178. int const aux_timeout_ms = HZ/4;
  179. struct dp_aux *dp_aux = &aux->dp_aux;
  180. reinit_completion(&aux->comp);
  181. len = dp_aux_write(aux, msg);
  182. if (len == 0) {
  183. DP_AUX_ERR(dp_aux, "DP AUX write failed\n");
  184. return -EINVAL;
  185. }
  186. timeout = wait_for_completion_timeout(&aux->comp, aux_timeout_ms);
  187. if (!timeout) {
  188. DP_AUX_ERR(dp_aux, "aux %s timeout\n", (aux->read ? "read" : "write"));
  189. return -ETIMEDOUT;
  190. }
  191. if (aux->aux_error_num == DP_AUX_ERR_NONE) {
  192. ret = len;
  193. } else {
  194. DP_AUX_ERR_RATELIMITED(dp_aux, "aux err: %s\n",
  195. dp_aux_get_error(aux->aux_error_num));
  196. ret = -EINVAL;
  197. }
  198. return ret;
  199. }
  200. static void dp_aux_cmd_fifo_rx(struct dp_aux_private *aux,
  201. struct drm_dp_aux_msg *msg)
  202. {
  203. u32 data;
  204. u8 *dp;
  205. u32 i, actual_i;
  206. u32 len = msg->size;
  207. struct dp_aux *dp_aux = &aux->dp_aux;
  208. aux->catalog->clear_trans(aux->catalog, true);
  209. data = 0;
  210. data |= DP_AUX_DATA_INDEX_WRITE; /* INDEX_WRITE */
  211. data |= BIT(0); /* read */
  212. aux->catalog->data = data;
  213. aux->catalog->write_data(aux->catalog);
  214. dp = msg->buffer;
  215. /* discard first byte */
  216. data = aux->catalog->read_data(aux->catalog);
  217. for (i = 0; i < len; i++) {
  218. data = aux->catalog->read_data(aux->catalog);
  219. *dp++ = (u8)((data >> 8) & 0xff);
  220. actual_i = (data >> 16) & 0xFF;
  221. if (i != actual_i)
  222. DP_AUX_WARN(dp_aux, "Index mismatch: expected %d, found %d\n",
  223. i, actual_i);
  224. }
  225. }
  226. static void dp_aux_native_handler(struct dp_aux_private *aux)
  227. {
  228. u32 isr = aux->catalog->isr;
  229. if (isr & DP_INTR_AUX_I2C_DONE)
  230. aux->aux_error_num = DP_AUX_ERR_NONE;
  231. else if (isr & DP_INTR_WRONG_ADDR)
  232. aux->aux_error_num = DP_AUX_ERR_ADDR;
  233. else if (isr & DP_INTR_TIMEOUT)
  234. aux->aux_error_num = DP_AUX_ERR_TOUT;
  235. if (isr & DP_INTR_NACK_DEFER)
  236. aux->aux_error_num = DP_AUX_ERR_NACK;
  237. if (isr & DP_INTR_AUX_ERROR) {
  238. aux->aux_error_num = DP_AUX_ERR_PHY;
  239. aux->catalog->clear_hw_interrupts(aux->catalog);
  240. }
  241. complete(&aux->comp);
  242. }
  243. static void dp_aux_i2c_handler(struct dp_aux_private *aux)
  244. {
  245. u32 isr = aux->catalog->isr;
  246. if (isr & DP_INTR_AUX_I2C_DONE) {
  247. if (isr & (DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER))
  248. aux->aux_error_num = DP_AUX_ERR_NACK;
  249. else
  250. aux->aux_error_num = DP_AUX_ERR_NONE;
  251. } else {
  252. if (isr & DP_INTR_WRONG_ADDR)
  253. aux->aux_error_num = DP_AUX_ERR_ADDR;
  254. else if (isr & DP_INTR_TIMEOUT)
  255. aux->aux_error_num = DP_AUX_ERR_TOUT;
  256. if (isr & DP_INTR_NACK_DEFER)
  257. aux->aux_error_num = DP_AUX_ERR_NACK_DEFER;
  258. if (isr & DP_INTR_I2C_NACK)
  259. aux->aux_error_num = DP_AUX_ERR_NACK;
  260. if (isr & DP_INTR_I2C_DEFER)
  261. aux->aux_error_num = DP_AUX_ERR_DEFER;
  262. if (isr & DP_INTR_AUX_ERROR) {
  263. aux->aux_error_num = DP_AUX_ERR_PHY;
  264. aux->catalog->clear_hw_interrupts(aux->catalog);
  265. }
  266. }
  267. complete(&aux->comp);
  268. }
  269. static void dp_aux_isr(struct dp_aux *dp_aux)
  270. {
  271. struct dp_aux_private *aux;
  272. if (!dp_aux) {
  273. DP_AUX_ERR(dp_aux, "invalid input\n");
  274. return;
  275. }
  276. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  277. aux->catalog->get_irq(aux->catalog, aux->cmd_busy);
  278. if (!aux->cmd_busy)
  279. return;
  280. if (aux->native)
  281. dp_aux_native_handler(aux);
  282. else
  283. dp_aux_i2c_handler(aux);
  284. }
  285. static void dp_aux_reconfig(struct dp_aux *dp_aux)
  286. {
  287. struct dp_aux_private *aux;
  288. if (!dp_aux) {
  289. DP_AUX_ERR(dp_aux, "invalid input\n");
  290. return;
  291. }
  292. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  293. aux->catalog->update_aux_cfg(aux->catalog,
  294. aux->cfg, PHY_AUX_CFG1);
  295. aux->catalog->reset(aux->catalog);
  296. }
  297. static void dp_aux_abort_transaction(struct dp_aux *dp_aux, bool abort)
  298. {
  299. struct dp_aux_private *aux;
  300. if (!dp_aux) {
  301. DP_AUX_ERR(dp_aux, "invalid input\n");
  302. return;
  303. }
  304. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  305. atomic_set(&aux->aborted, abort);
  306. }
  307. static void dp_aux_update_offset_and_segment(struct dp_aux_private *aux,
  308. struct drm_dp_aux_msg *input_msg)
  309. {
  310. u32 const edid_address = 0x50;
  311. u32 const segment_address = 0x30;
  312. bool i2c_read = input_msg->request &
  313. (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);
  314. u8 *data = NULL;
  315. if (aux->native || i2c_read || ((input_msg->address != edid_address) &&
  316. (input_msg->address != segment_address)))
  317. return;
  318. data = input_msg->buffer;
  319. if (input_msg->address == segment_address)
  320. aux->segment = *data;
  321. else
  322. aux->offset = *data;
  323. }
  324. /**
  325. * dp_aux_transfer_helper() - helper function for EDID read transactions
  326. *
  327. * @aux: DP AUX private structure
  328. * @input_msg: input message from DRM upstream APIs
  329. * @send_seg: send the seg to sink
  330. *
  331. * return: void
  332. *
  333. * This helper function is used to fix EDID reads for non-compliant
  334. * sinks that do not handle the i2c middle-of-transaction flag correctly.
  335. */
  336. static void dp_aux_transfer_helper(struct dp_aux_private *aux,
  337. struct drm_dp_aux_msg *input_msg, bool send_seg)
  338. {
  339. struct drm_dp_aux_msg helper_msg;
  340. u32 const message_size = 0x10;
  341. u32 const segment_address = 0x30;
  342. u32 const edid_block_length = 0x80;
  343. bool i2c_mot = input_msg->request & DP_AUX_I2C_MOT;
  344. bool i2c_read = input_msg->request &
  345. (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);
  346. if (!i2c_mot || !i2c_read || (input_msg->size == 0))
  347. return;
  348. /*
  349. * Sending the segment value and EDID offset will be performed
  350. * from the DRM upstream EDID driver for each block. Avoid
  351. * duplicate AUX transactions related to this while reading the
  352. * first 16 bytes of each block.
  353. */
  354. if (!(aux->offset % edid_block_length) || !send_seg)
  355. goto end;
  356. aux->read = false;
  357. aux->cmd_busy = true;
  358. aux->no_send_addr = true;
  359. aux->no_send_stop = true;
  360. /*
  361. * Send the segment address for i2c reads for segment > 0 and for which
  362. * the middle-of-transaction flag is set. This is required to support
  363. * EDID reads of more than 2 blocks as the segment address is reset to 0
  364. * since we are overriding the middle-of-transaction flag for read
  365. * transactions.
  366. */
  367. if (aux->segment) {
  368. memset(&helper_msg, 0, sizeof(helper_msg));
  369. helper_msg.address = segment_address;
  370. helper_msg.buffer = &aux->segment;
  371. helper_msg.size = 1;
  372. dp_aux_cmd_fifo_tx(aux, &helper_msg);
  373. }
  374. /*
  375. * Send the offset address for every i2c read in which the
  376. * middle-of-transaction flag is set. This will ensure that the sink
  377. * will update its read pointer and return the correct portion of the
  378. * EDID buffer in the subsequent i2c read trasntion triggered in the
  379. * native AUX transfer function.
  380. */
  381. memset(&helper_msg, 0, sizeof(helper_msg));
  382. helper_msg.address = input_msg->address;
  383. helper_msg.buffer = &aux->offset;
  384. helper_msg.size = 1;
  385. dp_aux_cmd_fifo_tx(aux, &helper_msg);
  386. end:
  387. aux->offset += message_size;
  388. if (aux->offset == 0x80 || aux->offset == 0x100)
  389. aux->segment = 0x0; /* reset segment at end of block */
  390. }
  391. static int dp_aux_transfer_ready(struct dp_aux_private *aux,
  392. struct drm_dp_aux_msg *msg, bool send_seg)
  393. {
  394. int ret = 0;
  395. int const aux_cmd_native_max = 16;
  396. int const aux_cmd_i2c_max = 128;
  397. struct dp_aux *dp_aux = &aux->dp_aux;
  398. if (atomic_read(&aux->aborted)) {
  399. ret = -ETIMEDOUT;
  400. goto error;
  401. }
  402. aux->native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ);
  403. /* Ignore address only message */
  404. if ((msg->size == 0) || (msg->buffer == NULL)) {
  405. msg->reply = aux->native ?
  406. DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
  407. goto error;
  408. }
  409. /* msg sanity check */
  410. if ((aux->native && (msg->size > aux_cmd_native_max)) ||
  411. (msg->size > aux_cmd_i2c_max)) {
  412. DP_AUX_ERR(dp_aux, "%s: invalid msg: size(%zu), request(%x)\n",
  413. __func__, msg->size, msg->request);
  414. ret = -EINVAL;
  415. goto error;
  416. }
  417. dp_aux_update_offset_and_segment(aux, msg);
  418. dp_aux_transfer_helper(aux, msg, send_seg);
  419. aux->read = msg->request & (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);
  420. if (aux->read) {
  421. aux->no_send_addr = true;
  422. aux->no_send_stop = false;
  423. } else {
  424. aux->no_send_addr = true;
  425. aux->no_send_stop = true;
  426. }
  427. aux->cmd_busy = true;
  428. error:
  429. return ret;
  430. }
  431. static inline bool dp_aux_is_sideband_msg(u32 address, size_t size)
  432. {
  433. return (address >= 0x1000 && address + size < 0x1800) ||
  434. (address >= 0x2000 && address + size < 0x2200);
  435. }
  436. /*
  437. * This function does the real job to process an AUX transaction.
  438. * It will call aux_reset() function to reset the AUX channel,
  439. * if the waiting is timeout.
  440. */
  441. static ssize_t dp_aux_transfer(struct drm_dp_aux *drm_aux,
  442. struct drm_dp_aux_msg *msg)
  443. {
  444. ssize_t ret;
  445. int const retry_count = 5;
  446. struct dp_aux_private *aux = container_of(drm_aux,
  447. struct dp_aux_private, drm_aux);
  448. mutex_lock(&aux->mutex);
  449. ret = dp_aux_transfer_ready(aux, msg, true);
  450. if (ret)
  451. goto unlock_exit;
  452. if (!aux->cmd_busy) {
  453. ret = msg->size;
  454. goto unlock_exit;
  455. }
  456. ret = dp_aux_cmd_fifo_tx(aux, msg);
  457. if ((ret < 0) && !atomic_read(&aux->aborted)) {
  458. aux->retry_cnt++;
  459. if (!(aux->retry_cnt % retry_count))
  460. aux->catalog->update_aux_cfg(aux->catalog,
  461. aux->cfg, PHY_AUX_CFG1);
  462. aux->catalog->reset(aux->catalog);
  463. goto unlock_exit;
  464. } else if (ret < 0) {
  465. goto unlock_exit;
  466. }
  467. if (aux->aux_error_num == DP_AUX_ERR_NONE) {
  468. if (aux->read)
  469. dp_aux_cmd_fifo_rx(aux, msg);
  470. dp_aux_hex_dump(drm_aux, msg);
  471. msg->reply = aux->native ?
  472. DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
  473. } else {
  474. /* Reply defer to retry */
  475. msg->reply = aux->native ?
  476. DP_AUX_NATIVE_REPLY_DEFER : DP_AUX_I2C_REPLY_DEFER;
  477. }
  478. /* Return requested size for success or retry */
  479. ret = msg->size;
  480. aux->retry_cnt = 0;
  481. unlock_exit:
  482. aux->cmd_busy = false;
  483. mutex_unlock(&aux->mutex);
  484. return ret;
  485. }
  486. static ssize_t dp_aux_bridge_transfer(struct drm_dp_aux *drm_aux,
  487. struct drm_dp_aux_msg *msg)
  488. {
  489. struct dp_aux_private *aux = container_of(drm_aux,
  490. struct dp_aux_private, drm_aux);
  491. ssize_t size;
  492. if (aux->bridge_in_transfer) {
  493. size = dp_aux_transfer(drm_aux, msg);
  494. } else {
  495. aux->bridge_in_transfer = true;
  496. size = aux->aux_bridge->transfer(aux->aux_bridge,
  497. drm_aux, msg);
  498. aux->bridge_in_transfer = false;
  499. dp_aux_hex_dump(drm_aux, msg);
  500. }
  501. return size;
  502. }
  503. static ssize_t dp_aux_transfer_debug(struct drm_dp_aux *drm_aux,
  504. struct drm_dp_aux_msg *msg)
  505. {
  506. struct dp_aux_private *aux = container_of(drm_aux,
  507. struct dp_aux_private, drm_aux);
  508. ssize_t size;
  509. int aborted;
  510. mutex_lock(&aux->mutex);
  511. aborted = atomic_read(&aux->aborted);
  512. mutex_unlock(&aux->mutex);
  513. if (aborted) {
  514. size = -ETIMEDOUT;
  515. goto end;
  516. }
  517. if (aux->sim_in_transfer) {
  518. if (aux->aux_bridge && aux->aux_bridge->transfer)
  519. size = dp_aux_bridge_transfer(drm_aux, msg);
  520. else
  521. size = dp_aux_transfer(drm_aux, msg);
  522. } else {
  523. aux->sim_in_transfer = true;
  524. size = aux->sim_bridge->transfer(aux->sim_bridge,
  525. drm_aux, msg);
  526. aux->sim_in_transfer = false;
  527. dp_aux_hex_dump(drm_aux, msg);
  528. }
  529. end:
  530. return size;
  531. }
  532. static void dp_aux_reset_phy_config_indices(struct dp_aux_cfg *aux_cfg)
  533. {
  534. int i = 0;
  535. for (i = 0; i < PHY_AUX_CFG_MAX; i++)
  536. aux_cfg[i].current_index = 0;
  537. }
  538. static void dp_aux_init(struct dp_aux *dp_aux, struct dp_aux_cfg *aux_cfg)
  539. {
  540. struct dp_aux_private *aux;
  541. if (!dp_aux || !aux_cfg) {
  542. DP_AUX_ERR(dp_aux, "invalid input\n");
  543. return;
  544. }
  545. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  546. if (aux->enabled)
  547. return;
  548. dp_aux_reset_phy_config_indices(aux_cfg);
  549. aux->catalog->setup(aux->catalog, aux_cfg);
  550. aux->catalog->reset(aux->catalog);
  551. aux->catalog->enable(aux->catalog, true);
  552. atomic_set(&aux->aborted, 0);
  553. aux->retry_cnt = 0;
  554. aux->enabled = true;
  555. }
  556. static void dp_aux_deinit(struct dp_aux *dp_aux)
  557. {
  558. struct dp_aux_private *aux;
  559. if (!dp_aux) {
  560. DP_AUX_ERR(dp_aux, "invalid input\n");
  561. return;
  562. }
  563. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  564. if (!aux->enabled)
  565. return;
  566. atomic_set(&aux->aborted, 1);
  567. aux->catalog->enable(aux->catalog, false);
  568. aux->enabled = false;
  569. }
  570. static int dp_aux_register(struct dp_aux *dp_aux, struct drm_device *drm_dev)
  571. {
  572. struct dp_aux_private *aux;
  573. int ret = 0;
  574. if (!dp_aux) {
  575. DP_AUX_ERR(dp_aux, "invalid input\n");
  576. ret = -EINVAL;
  577. goto exit;
  578. }
  579. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  580. aux->drm_aux.name = "sde_dp_aux";
  581. aux->drm_aux.dev = aux->dev;
  582. aux->drm_aux.transfer = dp_aux_transfer;
  583. #if (KERNEL_VERSION(5, 15, 0) <= LINUX_VERSION_CODE)
  584. aux->drm_aux.drm_dev = drm_dev;
  585. #endif
  586. atomic_set(&aux->aborted, 1);
  587. ret = drm_dp_aux_register(&aux->drm_aux);
  588. if (ret) {
  589. DP_AUX_ERR(dp_aux, "%s: failed to register drm aux: %d\n", __func__, ret);
  590. goto exit;
  591. }
  592. dp_aux->drm_aux = &aux->drm_aux;
  593. /* if bridge is defined, override transfer function */
  594. if (aux->aux_bridge && aux->aux_bridge->transfer)
  595. aux->drm_aux.transfer = dp_aux_bridge_transfer;
  596. exit:
  597. return ret;
  598. }
  599. static void dp_aux_deregister(struct dp_aux *dp_aux)
  600. {
  601. struct dp_aux_private *aux;
  602. if (!dp_aux) {
  603. DP_AUX_ERR(dp_aux, "invalid input\n");
  604. return;
  605. }
  606. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  607. drm_dp_aux_unregister(&aux->drm_aux);
  608. }
  609. static void dp_aux_set_sim_mode(struct dp_aux *dp_aux,
  610. struct dp_aux_bridge *sim_bridge)
  611. {
  612. struct dp_aux_private *aux;
  613. if (!dp_aux) {
  614. DP_AUX_ERR(dp_aux, "invalid input\n");
  615. return;
  616. }
  617. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  618. mutex_lock(&aux->mutex);
  619. aux->sim_bridge = sim_bridge;
  620. if (sim_bridge) {
  621. atomic_set(&aux->aborted, 0);
  622. aux->drm_aux.transfer = dp_aux_transfer_debug;
  623. } else if (aux->aux_bridge && aux->aux_bridge->transfer) {
  624. aux->drm_aux.transfer = dp_aux_bridge_transfer;
  625. } else {
  626. aux->drm_aux.transfer = dp_aux_transfer;
  627. }
  628. mutex_unlock(&aux->mutex);
  629. }
  630. #if IS_ENABLED(CONFIG_QCOM_FSA4480_I2C)
  631. static int dp_aux_configure_fsa_switch(struct dp_aux *dp_aux,
  632. bool enable, int orientation)
  633. {
  634. struct dp_aux_private *aux;
  635. int rc = 0;
  636. enum fsa_function event = FSA_USBC_DISPLAYPORT_DISCONNECTED;
  637. if (!dp_aux) {
  638. DP_AUX_ERR(dp_aux, "invalid input\n");
  639. rc = -EINVAL;
  640. goto end;
  641. }
  642. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  643. if (!aux->aux_switch_node) {
  644. DP_AUX_DEBUG(dp_aux, "undefined fsa4480 handle\n");
  645. rc = -EINVAL;
  646. goto end;
  647. }
  648. if (enable) {
  649. switch (orientation) {
  650. case ORIENTATION_CC1:
  651. event = FSA_USBC_ORIENTATION_CC1;
  652. break;
  653. case ORIENTATION_CC2:
  654. event = FSA_USBC_ORIENTATION_CC2;
  655. break;
  656. default:
  657. DP_AUX_ERR(dp_aux, "invalid orientation\n");
  658. rc = -EINVAL;
  659. goto end;
  660. }
  661. }
  662. DP_AUX_DEBUG(dp_aux, "enable=%d, orientation=%d, event=%d\n",
  663. enable, orientation, event);
  664. rc = fsa4480_switch_event(aux->aux_switch_node, event);
  665. if (rc)
  666. DP_AUX_ERR(dp_aux, "failed to configure fsa4480 i2c device (%d)\n", rc);
  667. end:
  668. return rc;
  669. }
  670. #endif
  671. #if IS_ENABLED(CONFIG_QCOM_WCD939X_I2C)
  672. static int dp_aux_configure_wcd_switch(struct dp_aux *dp_aux,
  673. bool enable, int orientation)
  674. {
  675. struct dp_aux_private *aux;
  676. int rc = 0;
  677. enum wcd_usbss_cable_status status = WCD_USBSS_CABLE_DISCONNECT;
  678. enum wcd_usbss_cable_types event = WCD_USBSS_DP_AUX_CC1;
  679. if (!dp_aux) {
  680. DP_AUX_ERR(dp_aux, "invalid input\n");
  681. rc = -EINVAL;
  682. goto end;
  683. }
  684. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  685. if (!aux->aux_switch_node) {
  686. DP_AUX_DEBUG(dp_aux, "undefined wcd939x switch handle\n");
  687. rc = -EINVAL;
  688. goto end;
  689. }
  690. if (enable) {
  691. status = WCD_USBSS_CABLE_CONNECT;
  692. switch (orientation) {
  693. case ORIENTATION_CC1:
  694. event = WCD_USBSS_DP_AUX_CC1;
  695. break;
  696. case ORIENTATION_CC2:
  697. event = WCD_USBSS_DP_AUX_CC2;
  698. break;
  699. default:
  700. DP_AUX_ERR(dp_aux, "invalid orientation\n");
  701. rc = -EINVAL;
  702. goto end;
  703. }
  704. }
  705. DP_AUX_DEBUG(dp_aux, "enable=%d, orientation=%d, event=%d\n",
  706. enable, orientation, event);
  707. rc = wcd_usbss_switch_update(event, status);
  708. if (rc)
  709. DP_AUX_ERR(dp_aux, "failed to configure wcd939x i2c device (%d)\n", rc);
  710. end:
  711. return rc;
  712. }
  713. #endif
  714. struct dp_aux *dp_aux_get(struct device *dev, struct dp_catalog_aux *catalog,
  715. struct dp_parser *parser, struct device_node *aux_switch,
  716. struct dp_aux_bridge *aux_bridge, void *ipc_log_context)
  717. {
  718. int rc = 0;
  719. struct dp_aux_private *aux;
  720. struct dp_aux *dp_aux = NULL;
  721. if (!catalog || !parser) {
  722. DP_AUX_ERR(dp_aux, "invalid input\n");
  723. rc = -ENODEV;
  724. goto error;
  725. }
  726. aux = devm_kzalloc(dev, sizeof(*aux), GFP_KERNEL);
  727. if (!aux) {
  728. rc = -ENOMEM;
  729. goto error;
  730. }
  731. init_completion(&aux->comp);
  732. aux->cmd_busy = false;
  733. mutex_init(&aux->mutex);
  734. aux->dev = dev;
  735. aux->catalog = catalog;
  736. aux->cfg = parser->aux_cfg;
  737. aux->aux_switch_node = aux_switch;
  738. aux->aux_bridge = aux_bridge;
  739. dp_aux = &aux->dp_aux;
  740. aux->retry_cnt = 0;
  741. dp_aux->isr = dp_aux_isr;
  742. dp_aux->init = dp_aux_init;
  743. dp_aux->deinit = dp_aux_deinit;
  744. dp_aux->drm_aux_register = dp_aux_register;
  745. dp_aux->drm_aux_deregister = dp_aux_deregister;
  746. dp_aux->reconfig = dp_aux_reconfig;
  747. dp_aux->abort = dp_aux_abort_transaction;
  748. dp_aux->set_sim_mode = dp_aux_set_sim_mode;
  749. dp_aux->ipc_log_context = ipc_log_context;
  750. #if IS_ENABLED(CONFIG_QCOM_FSA4480_I2C)
  751. dp_aux->switch_configure = dp_aux_configure_fsa_switch;
  752. dp_aux->switch_register_notifier = fsa4480_reg_notifier;
  753. dp_aux->switch_unregister_notifier = fsa4480_unreg_notifier;
  754. #elif IS_ENABLED(CONFIG_QCOM_WCD939X_I2C)
  755. dp_aux->switch_configure = dp_aux_configure_wcd_switch;
  756. dp_aux->switch_register_notifier = wcd_usbss_reg_notifier;
  757. dp_aux->switch_unregister_notifier = wcd_usbss_unreg_notifier;
  758. #endif
  759. return dp_aux;
  760. error:
  761. return ERR_PTR(rc);
  762. }
  763. void dp_aux_put(struct dp_aux *dp_aux)
  764. {
  765. struct dp_aux_private *aux;
  766. if (!dp_aux)
  767. return;
  768. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  769. mutex_destroy(&aux->mutex);
  770. devm_kfree(aux->dev, aux);
  771. }