dp_main.c 117 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107
  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <qdf_net_types.h>
  21. #include <qdf_lro.h>
  22. #include <hal_api.h>
  23. #include <hif.h>
  24. #include <htt.h>
  25. #include <wdi_event.h>
  26. #include <queue.h>
  27. #include "dp_htt.h"
  28. #include "dp_types.h"
  29. #include "dp_internal.h"
  30. #include "dp_tx.h"
  31. #include "dp_rx.h"
  32. #include <cdp_txrx_handle.h>
  33. #include <wlan_cfg.h>
  34. #include "cdp_txrx_cmn_struct.h"
  35. #include <qdf_util.h>
  36. #include "dp_peer.h"
  37. #include "dp_rx_mon.h"
  38. #include "htt_stats.h"
  39. #define DP_INTR_POLL_TIMER_MS 10
  40. #define DP_MCS_LENGTH (6*MAX_MCS)
  41. #define DP_NSS_LENGTH (6*SS_COUNT)
  42. #define DP_RXDMA_ERR_LENGTH (6*MAX_RXDMA_ERRORS)
  43. #define DP_REO_ERR_LENGTH (6*REO_ERROR_TYPE_MAX)
  44. #define DP_CURR_FW_STATS_AVAIL 19
  45. #define DP_HTT_DBG_EXT_STATS_MAX 256
  46. /**
  47. * default_dscp_tid_map - Default DSCP-TID mapping
  48. *
  49. * DSCP TID AC
  50. * 000000 0 WME_AC_BE
  51. * 001000 1 WME_AC_BK
  52. * 010000 1 WME_AC_BK
  53. * 011000 0 WME_AC_BE
  54. * 100000 5 WME_AC_VI
  55. * 101000 5 WME_AC_VI
  56. * 110000 6 WME_AC_VO
  57. * 111000 6 WME_AC_VO
  58. */
  59. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  60. 0, 0, 0, 0, 0, 0, 0, 0,
  61. 1, 1, 1, 1, 1, 1, 1, 1,
  62. 1, 1, 1, 1, 1, 1, 1, 1,
  63. 0, 0, 0, 0, 0, 0, 0, 0,
  64. 5, 5, 5, 5, 5, 5, 5, 5,
  65. 5, 5, 5, 5, 5, 5, 5, 5,
  66. 6, 6, 6, 6, 6, 6, 6, 6,
  67. 6, 6, 6, 6, 6, 6, 6, 6,
  68. };
  69. /**
  70. * @brief Select the type of statistics
  71. */
  72. enum dp_stats_type {
  73. STATS_FW = 0,
  74. STATS_HOST = 1,
  75. STATS_TYPE_MAX = 2,
  76. };
  77. /**
  78. * @brief General Firmware statistics options
  79. *
  80. */
  81. enum dp_fw_stats {
  82. TXRX_FW_STATS_INVALID = -1,
  83. };
  84. /**
  85. * @brief Firmware and Host statistics
  86. * currently supported
  87. */
  88. const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
  89. {HTT_DBG_EXT_STATS_RESET, TXRX_HOST_STATS_INVALID},
  90. {HTT_DBG_EXT_STATS_PDEV_TX, TXRX_HOST_STATS_INVALID},
  91. {HTT_DBG_EXT_STATS_PDEV_RX, TXRX_HOST_STATS_INVALID},
  92. {HTT_DBG_EXT_STATS_PDEV_TX_HWQ, TXRX_HOST_STATS_INVALID},
  93. {HTT_DBG_EXT_STATS_PDEV_TX_SCHED, TXRX_HOST_STATS_INVALID},
  94. {HTT_DBG_EXT_STATS_PDEV_ERROR, TXRX_HOST_STATS_INVALID},
  95. {HTT_DBG_EXT_STATS_PDEV_TQM, TXRX_HOST_STATS_INVALID},
  96. {HTT_DBG_EXT_STATS_TQM_CMDQ, TXRX_HOST_STATS_INVALID},
  97. {HTT_DBG_EXT_STATS_TX_DE_INFO, TXRX_HOST_STATS_INVALID},
  98. {HTT_DBG_EXT_STATS_PDEV_TX_RATE, TXRX_HOST_STATS_INVALID},
  99. {HTT_DBG_EXT_STATS_PDEV_RX_RATE, TXRX_HOST_STATS_INVALID},
  100. {TXRX_FW_STATS_INVALID, TXRX_HOST_STATS_INVALID},
  101. {HTT_DBG_EXT_STATS_TX_SELFGEN_INFO, TXRX_HOST_STATS_INVALID},
  102. {HTT_DBG_EXT_STATS_TX_MU_HWQ, TXRX_HOST_STATS_INVALID},
  103. {HTT_DBG_EXT_STATS_RING_IF_INFO, TXRX_HOST_STATS_INVALID},
  104. {HTT_DBG_EXT_STATS_SRNG_INFO, TXRX_HOST_STATS_INVALID},
  105. {HTT_DBG_EXT_STATS_SFM_INFO, TXRX_HOST_STATS_INVALID},
  106. {HTT_DBG_EXT_STATS_PDEV_TX_MU, TXRX_HOST_STATS_INVALID},
  107. {HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST, TXRX_HOST_STATS_INVALID},
  108. /* Last ENUM for HTT FW STATS */
  109. {DP_HTT_DBG_EXT_STATS_MAX, TXRX_HOST_STATS_INVALID},
  110. {TXRX_FW_STATS_INVALID, TXRX_CLEAR_STATS},
  111. {TXRX_FW_STATS_INVALID, TXRX_RX_RATE_STATS},
  112. {TXRX_FW_STATS_INVALID, TXRX_TX_RATE_STATS},
  113. {TXRX_FW_STATS_INVALID, TXRX_TX_HOST_STATS},
  114. {TXRX_FW_STATS_INVALID, TXRX_RX_HOST_STATS},
  115. };
  116. /*
  117. * dp_setup_srng - Internal function to setup SRNG rings used by data path
  118. */
  119. static int dp_srng_setup(struct dp_soc *soc, struct dp_srng *srng,
  120. int ring_type, int ring_num, int mac_id, uint32_t num_entries)
  121. {
  122. void *hal_soc = soc->hal_soc;
  123. uint32_t entry_size = hal_srng_get_entrysize(hal_soc, ring_type);
  124. /* TODO: See if we should get align size from hal */
  125. uint32_t ring_base_align = 8;
  126. struct hal_srng_params ring_params;
  127. uint32_t max_entries = hal_srng_max_entries(hal_soc, ring_type);
  128. num_entries = (num_entries > max_entries) ? max_entries : num_entries;
  129. srng->hal_srng = NULL;
  130. srng->alloc_size = (num_entries * entry_size) + ring_base_align - 1;
  131. srng->base_vaddr_unaligned = qdf_mem_alloc_consistent(
  132. soc->osdev, soc->osdev->dev, srng->alloc_size,
  133. &(srng->base_paddr_unaligned));
  134. if (!srng->base_vaddr_unaligned) {
  135. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  136. FL("alloc failed - ring_type: %d, ring_num %d"),
  137. ring_type, ring_num);
  138. return QDF_STATUS_E_NOMEM;
  139. }
  140. ring_params.ring_base_vaddr = srng->base_vaddr_unaligned +
  141. ((unsigned long)srng->base_vaddr_unaligned % ring_base_align);
  142. ring_params.ring_base_paddr = srng->base_paddr_unaligned +
  143. ((unsigned long)(ring_params.ring_base_vaddr) -
  144. (unsigned long)srng->base_vaddr_unaligned);
  145. ring_params.num_entries = num_entries;
  146. /* TODO: Check MSI support and get MSI settings from HIF layer */
  147. ring_params.msi_data = 0;
  148. ring_params.msi_addr = 0;
  149. /*
  150. * Setup interrupt timer and batch counter thresholds for
  151. * interrupt mitigation based on ring type
  152. */
  153. if (ring_type == REO_DST) {
  154. ring_params.intr_timer_thres_us =
  155. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  156. ring_params.intr_batch_cntr_thres_entries =
  157. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  158. } else if (ring_type == WBM2SW_RELEASE && (ring_num < 3)) {
  159. ring_params.intr_timer_thres_us =
  160. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  161. ring_params.intr_batch_cntr_thres_entries =
  162. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  163. } else {
  164. ring_params.intr_timer_thres_us =
  165. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  166. ring_params.intr_batch_cntr_thres_entries =
  167. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  168. }
  169. /* TODO: Currently hal layer takes care of endianness related settings.
  170. * See if these settings need to passed from DP layer
  171. */
  172. ring_params.flags = 0;
  173. /* Enable low threshold interrupts for rx buffer rings (regular and
  174. * monitor buffer rings.
  175. * TODO: See if this is required for any other ring
  176. */
  177. if ((ring_type == RXDMA_BUF) || (ring_type == RXDMA_MONITOR_BUF)) {
  178. /* TODO: Setting low threshold to 1/8th of ring size
  179. * see if this needs to be configurable
  180. */
  181. ring_params.low_threshold = num_entries >> 3;
  182. ring_params.flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  183. }
  184. srng->hal_srng = hal_srng_setup(hal_soc, ring_type, ring_num,
  185. mac_id, &ring_params);
  186. return 0;
  187. }
  188. /**
  189. * dp_srng_cleanup - Internal function to cleanup SRNG rings used by data path
  190. * Any buffers allocated and attached to ring entries are expected to be freed
  191. * before calling this function.
  192. */
  193. static void dp_srng_cleanup(struct dp_soc *soc, struct dp_srng *srng,
  194. int ring_type, int ring_num)
  195. {
  196. if (!srng->hal_srng) {
  197. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  198. FL("Ring type: %d, num:%d not setup"),
  199. ring_type, ring_num);
  200. return;
  201. }
  202. hal_srng_cleanup(soc->hal_soc, srng->hal_srng);
  203. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  204. srng->alloc_size,
  205. srng->base_vaddr_unaligned,
  206. srng->base_paddr_unaligned, 0);
  207. }
  208. /* TODO: Need this interface from HIF */
  209. void *hif_get_hal_handle(void *hif_handle);
  210. /*
  211. * dp_service_srngs() - Top level interrupt handler for DP Ring interrupts
  212. * @dp_ctx: DP SOC handle
  213. * @budget: Number of frames/descriptors that can be processed in one shot
  214. *
  215. * Return: remaining budget/quota for the soc device
  216. */
  217. static uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget)
  218. {
  219. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  220. struct dp_soc *soc = int_ctx->soc;
  221. int ring = 0;
  222. uint32_t work_done = 0;
  223. uint32_t budget = dp_budget;
  224. uint8_t tx_mask = int_ctx->tx_ring_mask;
  225. uint8_t rx_mask = int_ctx->rx_ring_mask;
  226. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  227. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  228. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  229. /* Process Tx completion interrupts first to return back buffers */
  230. if (tx_mask) {
  231. for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
  232. if (tx_mask & (1 << ring)) {
  233. work_done =
  234. dp_tx_comp_handler(soc, ring, budget);
  235. budget -= work_done;
  236. if (work_done)
  237. QDF_TRACE(QDF_MODULE_ID_DP,
  238. QDF_TRACE_LEVEL_INFO,
  239. "tx mask 0x%x ring %d,"
  240. "budget %d",
  241. tx_mask, ring, budget);
  242. if (budget <= 0)
  243. goto budget_done;
  244. }
  245. }
  246. }
  247. /* Process REO Exception ring interrupt */
  248. if (rx_err_mask) {
  249. work_done = dp_rx_err_process(soc,
  250. soc->reo_exception_ring.hal_srng, budget);
  251. budget -= work_done;
  252. if (work_done)
  253. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  254. "REO Exception Ring: work_done %d budget %d",
  255. work_done, budget);
  256. if (budget <= 0) {
  257. goto budget_done;
  258. }
  259. }
  260. /* Process Rx WBM release ring interrupt */
  261. if (rx_wbm_rel_mask) {
  262. work_done = dp_rx_wbm_err_process(soc,
  263. soc->rx_rel_ring.hal_srng, budget);
  264. budget -= work_done;
  265. if (work_done)
  266. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  267. "WBM Release Ring: work_done %d budget %d",
  268. work_done, budget);
  269. if (budget <= 0) {
  270. goto budget_done;
  271. }
  272. }
  273. /* Process Rx interrupts */
  274. if (rx_mask) {
  275. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  276. if (rx_mask & (1 << ring)) {
  277. work_done =
  278. dp_rx_process(int_ctx,
  279. soc->reo_dest_ring[ring].hal_srng,
  280. budget);
  281. budget -= work_done;
  282. if (work_done)
  283. QDF_TRACE(QDF_MODULE_ID_DP,
  284. QDF_TRACE_LEVEL_INFO,
  285. "rx mask 0x%x ring %d,"
  286. "budget %d",
  287. tx_mask, ring, budget);
  288. if (budget <= 0)
  289. goto budget_done;
  290. }
  291. }
  292. }
  293. if (reo_status_mask)
  294. dp_reo_status_ring_handler(soc);
  295. /* Process Rx monitor interrupts */
  296. for (ring = 0 ; ring < MAX_PDEV_CNT; ring++) {
  297. if (int_ctx->rx_mon_ring_mask & (1 << ring)) {
  298. work_done =
  299. dp_mon_process(soc, ring, budget);
  300. budget -= work_done;
  301. }
  302. }
  303. qdf_lro_flush(int_ctx->lro_ctx);
  304. budget_done:
  305. return dp_budget - budget;
  306. }
  307. /* dp_interrupt_timer()- timer poll for interrupts
  308. *
  309. * @arg: SoC Handle
  310. *
  311. * Return:
  312. *
  313. */
  314. #ifdef DP_INTR_POLL_BASED
  315. static void dp_interrupt_timer(void *arg)
  316. {
  317. struct dp_soc *soc = (struct dp_soc *) arg;
  318. int i;
  319. if (qdf_atomic_read(&soc->cmn_init_done)) {
  320. for (i = 0;
  321. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  322. dp_service_srngs(&soc->intr_ctx[i], 0xffff);
  323. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  324. }
  325. }
  326. /*
  327. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  328. * @txrx_soc: DP SOC handle
  329. *
  330. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  331. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  332. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  333. *
  334. * Return: 0 for success. nonzero for failure.
  335. */
  336. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  337. {
  338. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  339. int i;
  340. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  341. soc->intr_ctx[i].tx_ring_mask = 0xF;
  342. soc->intr_ctx[i].rx_ring_mask = 0xF;
  343. soc->intr_ctx[i].rx_mon_ring_mask = 0x1;
  344. soc->intr_ctx[i].rx_err_ring_mask = 0x1;
  345. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0x1;
  346. soc->intr_ctx[i].reo_status_ring_mask = 0x1;
  347. soc->intr_ctx[i].soc = soc;
  348. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  349. }
  350. qdf_timer_init(soc->osdev, &soc->int_timer,
  351. dp_interrupt_timer, (void *)soc,
  352. QDF_TIMER_TYPE_WAKE_APPS);
  353. return QDF_STATUS_SUCCESS;
  354. }
  355. /*
  356. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  357. * @txrx_soc: DP SOC handle
  358. *
  359. * Return: void
  360. */
  361. static void dp_soc_interrupt_detach(void *txrx_soc)
  362. {
  363. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  364. qdf_timer_stop(&soc->int_timer);
  365. qdf_timer_free(&soc->int_timer);
  366. }
  367. #else
  368. /*
  369. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  370. * @txrx_soc: DP SOC handle
  371. *
  372. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  373. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  374. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  375. *
  376. * Return: 0 for success. nonzero for failure.
  377. */
  378. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  379. {
  380. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  381. int i = 0;
  382. int num_irq = 0;
  383. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  384. int j = 0;
  385. int ret = 0;
  386. /* Map of IRQ ids registered with one interrupt context */
  387. int irq_id_map[HIF_MAX_GRP_IRQ];
  388. int tx_mask =
  389. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  390. int rx_mask =
  391. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  392. int rx_mon_mask =
  393. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  394. /*
  395. * Mapping the exception/status rings to IRQ Group 0 (CPU 0).
  396. * Later add wlan_cfg interface for these masks
  397. */
  398. int rx_err_ring_mask = 0x1;
  399. int rx_wbm_rel_ring_mask = 0x1;
  400. int reo_status_ring_mask = 0x1;
  401. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  402. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  403. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  404. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  405. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  406. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  407. soc->intr_ctx[i].soc = soc;
  408. num_irq = 0;
  409. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  410. if (tx_mask & (1 << j)) {
  411. irq_id_map[num_irq++] =
  412. (wbm2host_tx_completions_ring1 - j);
  413. }
  414. if (rx_mask & (1 << j)) {
  415. irq_id_map[num_irq++] =
  416. (reo2host_destination_ring1 - j);
  417. }
  418. if (rx_mon_mask & (1 << j)) {
  419. irq_id_map[num_irq++] =
  420. (rxdma2host_monitor_destination_mac1
  421. - j);
  422. }
  423. if (rx_wbm_rel_ring_mask & (1 << j))
  424. irq_id_map[num_irq++] = wbm2host_rx_release;
  425. if (rx_err_ring_mask & (1 << j))
  426. irq_id_map[num_irq++] = reo2host_exception;
  427. if (reo_status_ring_mask & (1 << j))
  428. irq_id_map[num_irq++] = reo2host_status;
  429. }
  430. ret = hif_register_ext_group_int_handler(soc->hif_handle,
  431. num_irq, irq_id_map,
  432. dp_service_srngs,
  433. &soc->intr_ctx[i]);
  434. if (ret) {
  435. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  436. FL("failed, ret = %d"), ret);
  437. return QDF_STATUS_E_FAILURE;
  438. }
  439. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  440. }
  441. hif_configure_ext_group_interrupts(soc->hif_handle);
  442. return QDF_STATUS_SUCCESS;
  443. }
  444. /*
  445. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  446. * @txrx_soc: DP SOC handle
  447. *
  448. * Return: void
  449. */
  450. static void dp_soc_interrupt_detach(void *txrx_soc)
  451. {
  452. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  453. int i;
  454. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  455. soc->intr_ctx[i].tx_ring_mask = 0;
  456. soc->intr_ctx[i].rx_ring_mask = 0;
  457. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  458. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  459. }
  460. }
  461. #endif
  462. #define AVG_MAX_MPDUS_PER_TID 128
  463. #define AVG_TIDS_PER_CLIENT 2
  464. #define AVG_FLOWS_PER_TID 2
  465. #define AVG_MSDUS_PER_FLOW 128
  466. #define AVG_MSDUS_PER_MPDU 4
  467. /*
  468. * Allocate and setup link descriptor pool that will be used by HW for
  469. * various link and queue descriptors and managed by WBM
  470. */
  471. static int dp_hw_link_desc_pool_setup(struct dp_soc *soc)
  472. {
  473. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  474. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  475. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  476. uint32_t num_mpdus_per_link_desc =
  477. hal_num_mpdus_per_link_desc(soc->hal_soc);
  478. uint32_t num_msdus_per_link_desc =
  479. hal_num_msdus_per_link_desc(soc->hal_soc);
  480. uint32_t num_mpdu_links_per_queue_desc =
  481. hal_num_mpdu_links_per_queue_desc(soc->hal_soc);
  482. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  483. uint32_t total_link_descs, total_mem_size;
  484. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  485. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  486. uint32_t num_link_desc_banks;
  487. uint32_t last_bank_size = 0;
  488. uint32_t entry_size, num_entries;
  489. int i;
  490. /* Only Tx queue descriptors are allocated from common link descriptor
  491. * pool Rx queue descriptors are not included in this because (REO queue
  492. * extension descriptors) they are expected to be allocated contiguously
  493. * with REO queue descriptors
  494. */
  495. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  496. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  497. num_mpdu_queue_descs = num_mpdu_link_descs /
  498. num_mpdu_links_per_queue_desc;
  499. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  500. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  501. num_msdus_per_link_desc;
  502. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  503. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  504. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  505. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  506. /* Round up to power of 2 */
  507. total_link_descs = 1;
  508. while (total_link_descs < num_entries)
  509. total_link_descs <<= 1;
  510. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  511. FL("total_link_descs: %u, link_desc_size: %d"),
  512. total_link_descs, link_desc_size);
  513. total_mem_size = total_link_descs * link_desc_size;
  514. total_mem_size += link_desc_align;
  515. if (total_mem_size <= max_alloc_size) {
  516. num_link_desc_banks = 0;
  517. last_bank_size = total_mem_size;
  518. } else {
  519. num_link_desc_banks = (total_mem_size) /
  520. (max_alloc_size - link_desc_align);
  521. last_bank_size = total_mem_size %
  522. (max_alloc_size - link_desc_align);
  523. }
  524. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  525. FL("total_mem_size: %d, num_link_desc_banks: %u"),
  526. total_mem_size, num_link_desc_banks);
  527. for (i = 0; i < num_link_desc_banks; i++) {
  528. soc->link_desc_banks[i].base_vaddr_unaligned =
  529. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  530. max_alloc_size,
  531. &(soc->link_desc_banks[i].base_paddr_unaligned));
  532. soc->link_desc_banks[i].size = max_alloc_size;
  533. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)(
  534. soc->link_desc_banks[i].base_vaddr_unaligned) +
  535. ((unsigned long)(
  536. soc->link_desc_banks[i].base_vaddr_unaligned) %
  537. link_desc_align));
  538. soc->link_desc_banks[i].base_paddr = (unsigned long)(
  539. soc->link_desc_banks[i].base_paddr_unaligned) +
  540. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  541. (unsigned long)(
  542. soc->link_desc_banks[i].base_vaddr_unaligned));
  543. if (!soc->link_desc_banks[i].base_vaddr_unaligned) {
  544. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  545. FL("Link descriptor memory alloc failed"));
  546. goto fail;
  547. }
  548. }
  549. if (last_bank_size) {
  550. /* Allocate last bank in case total memory required is not exact
  551. * multiple of max_alloc_size
  552. */
  553. soc->link_desc_banks[i].base_vaddr_unaligned =
  554. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  555. last_bank_size,
  556. &(soc->link_desc_banks[i].base_paddr_unaligned));
  557. soc->link_desc_banks[i].size = last_bank_size;
  558. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)
  559. (soc->link_desc_banks[i].base_vaddr_unaligned) +
  560. ((unsigned long)(
  561. soc->link_desc_banks[i].base_vaddr_unaligned) %
  562. link_desc_align));
  563. soc->link_desc_banks[i].base_paddr =
  564. (unsigned long)(
  565. soc->link_desc_banks[i].base_paddr_unaligned) +
  566. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  567. (unsigned long)(
  568. soc->link_desc_banks[i].base_vaddr_unaligned));
  569. }
  570. /* Allocate and setup link descriptor idle list for HW internal use */
  571. entry_size = hal_srng_get_entrysize(soc->hal_soc, WBM_IDLE_LINK);
  572. total_mem_size = entry_size * total_link_descs;
  573. if (total_mem_size <= max_alloc_size) {
  574. void *desc;
  575. if (dp_srng_setup(soc, &soc->wbm_idle_link_ring,
  576. WBM_IDLE_LINK, 0, 0, total_link_descs)) {
  577. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  578. FL("Link desc idle ring setup failed"));
  579. goto fail;
  580. }
  581. hal_srng_access_start_unlocked(soc->hal_soc,
  582. soc->wbm_idle_link_ring.hal_srng);
  583. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  584. soc->link_desc_banks[i].base_paddr; i++) {
  585. uint32_t num_entries = (soc->link_desc_banks[i].size -
  586. ((unsigned long)(
  587. soc->link_desc_banks[i].base_vaddr) -
  588. (unsigned long)(
  589. soc->link_desc_banks[i].base_vaddr_unaligned)))
  590. / link_desc_size;
  591. unsigned long paddr = (unsigned long)(
  592. soc->link_desc_banks[i].base_paddr);
  593. while (num_entries && (desc = hal_srng_src_get_next(
  594. soc->hal_soc,
  595. soc->wbm_idle_link_ring.hal_srng))) {
  596. hal_set_link_desc_addr(desc, i, paddr);
  597. num_entries--;
  598. paddr += link_desc_size;
  599. }
  600. }
  601. hal_srng_access_end_unlocked(soc->hal_soc,
  602. soc->wbm_idle_link_ring.hal_srng);
  603. } else {
  604. uint32_t num_scatter_bufs;
  605. uint32_t num_entries_per_buf;
  606. uint32_t rem_entries;
  607. uint8_t *scatter_buf_ptr;
  608. uint16_t scatter_buf_num;
  609. soc->wbm_idle_scatter_buf_size =
  610. hal_idle_list_scatter_buf_size(soc->hal_soc);
  611. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  612. soc->hal_soc, soc->wbm_idle_scatter_buf_size);
  613. num_scatter_bufs = (total_mem_size /
  614. soc->wbm_idle_scatter_buf_size) + (total_mem_size %
  615. soc->wbm_idle_scatter_buf_size) ? 1 : 0;
  616. for (i = 0; i < num_scatter_bufs; i++) {
  617. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  618. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  619. soc->wbm_idle_scatter_buf_size,
  620. &(soc->wbm_idle_scatter_buf_base_paddr[i]));
  621. if (soc->wbm_idle_scatter_buf_base_vaddr[i] == NULL) {
  622. QDF_TRACE(QDF_MODULE_ID_DP,
  623. QDF_TRACE_LEVEL_ERROR,
  624. FL("Scatter list memory alloc failed"));
  625. goto fail;
  626. }
  627. }
  628. /* Populate idle list scatter buffers with link descriptor
  629. * pointers
  630. */
  631. scatter_buf_num = 0;
  632. scatter_buf_ptr = (uint8_t *)(
  633. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  634. rem_entries = num_entries_per_buf;
  635. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  636. soc->link_desc_banks[i].base_paddr; i++) {
  637. uint32_t num_link_descs =
  638. (soc->link_desc_banks[i].size -
  639. ((unsigned long)(
  640. soc->link_desc_banks[i].base_vaddr) -
  641. (unsigned long)(
  642. soc->link_desc_banks[i].base_vaddr_unaligned)))
  643. / link_desc_size;
  644. unsigned long paddr = (unsigned long)(
  645. soc->link_desc_banks[i].base_paddr);
  646. void *desc = NULL;
  647. while (num_link_descs && (desc =
  648. hal_srng_src_get_next(soc->hal_soc,
  649. soc->wbm_idle_link_ring.hal_srng))) {
  650. hal_set_link_desc_addr((void *)scatter_buf_ptr,
  651. i, paddr);
  652. num_link_descs--;
  653. paddr += link_desc_size;
  654. if (rem_entries) {
  655. rem_entries--;
  656. scatter_buf_ptr += link_desc_size;
  657. } else {
  658. rem_entries = num_entries_per_buf;
  659. scatter_buf_num++;
  660. scatter_buf_ptr = (uint8_t *)(
  661. soc->wbm_idle_scatter_buf_base_vaddr[
  662. scatter_buf_num]);
  663. }
  664. }
  665. }
  666. /* Setup link descriptor idle list in HW */
  667. hal_setup_link_idle_list(soc->hal_soc,
  668. soc->wbm_idle_scatter_buf_base_paddr,
  669. soc->wbm_idle_scatter_buf_base_vaddr,
  670. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  671. (uint32_t)(scatter_buf_ptr -
  672. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  673. scatter_buf_num])));
  674. }
  675. return 0;
  676. fail:
  677. if (soc->wbm_idle_link_ring.hal_srng) {
  678. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  679. WBM_IDLE_LINK, 0);
  680. }
  681. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  682. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  683. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  684. soc->wbm_idle_scatter_buf_size,
  685. soc->wbm_idle_scatter_buf_base_vaddr[i],
  686. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  687. }
  688. }
  689. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  690. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  691. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  692. soc->link_desc_banks[i].size,
  693. soc->link_desc_banks[i].base_vaddr_unaligned,
  694. soc->link_desc_banks[i].base_paddr_unaligned,
  695. 0);
  696. }
  697. }
  698. return QDF_STATUS_E_FAILURE;
  699. }
  700. #ifdef notused
  701. /*
  702. * Free link descriptor pool that was setup HW
  703. */
  704. static void dp_hw_link_desc_pool_cleanup(struct dp_soc *soc)
  705. {
  706. int i;
  707. if (soc->wbm_idle_link_ring.hal_srng) {
  708. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  709. WBM_IDLE_LINK, 0);
  710. }
  711. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  712. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  713. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  714. soc->wbm_idle_scatter_buf_size,
  715. soc->wbm_idle_scatter_buf_base_vaddr[i],
  716. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  717. }
  718. }
  719. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  720. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  721. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  722. soc->link_desc_banks[i].size,
  723. soc->link_desc_banks[i].base_vaddr_unaligned,
  724. soc->link_desc_banks[i].base_paddr_unaligned,
  725. 0);
  726. }
  727. }
  728. }
  729. #endif /* notused */
  730. /* TODO: Following should be configurable */
  731. #define WBM_RELEASE_RING_SIZE 64
  732. #define TCL_DATA_RING_SIZE 512
  733. #define TX_COMP_RING_SIZE 1024
  734. #define TCL_CMD_RING_SIZE 32
  735. #define TCL_STATUS_RING_SIZE 32
  736. #define REO_DST_RING_SIZE 2048
  737. #define REO_REINJECT_RING_SIZE 32
  738. #define RX_RELEASE_RING_SIZE 1024
  739. #define REO_EXCEPTION_RING_SIZE 128
  740. #define REO_CMD_RING_SIZE 32
  741. #define REO_STATUS_RING_SIZE 32
  742. #define RXDMA_BUF_RING_SIZE 1024
  743. #define RXDMA_REFILL_RING_SIZE 2048
  744. #define RXDMA_MONITOR_BUF_RING_SIZE 1024
  745. #define RXDMA_MONITOR_DST_RING_SIZE 1024
  746. #define RXDMA_MONITOR_STATUS_RING_SIZE 1024
  747. #define RXDMA_MONITOR_DESC_RING_SIZE 1024
  748. /*
  749. * dp_soc_cmn_setup() - Common SoC level initializion
  750. * @soc: Datapath SOC handle
  751. *
  752. * This is an internal function used to setup common SOC data structures,
  753. * to be called from PDEV attach after receiving HW mode capabilities from FW
  754. */
  755. static int dp_soc_cmn_setup(struct dp_soc *soc)
  756. {
  757. int i;
  758. struct hal_reo_params reo_params;
  759. if (qdf_atomic_read(&soc->cmn_init_done))
  760. return 0;
  761. if (dp_peer_find_attach(soc))
  762. goto fail0;
  763. if (dp_hw_link_desc_pool_setup(soc))
  764. goto fail1;
  765. /* Setup SRNG rings */
  766. /* Common rings */
  767. if (dp_srng_setup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0,
  768. WBM_RELEASE_RING_SIZE)) {
  769. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  770. FL("dp_srng_setup failed for wbm_desc_rel_ring"));
  771. goto fail1;
  772. }
  773. soc->num_tcl_data_rings = 0;
  774. /* Tx data rings */
  775. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  776. soc->num_tcl_data_rings =
  777. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  778. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  779. if (dp_srng_setup(soc, &soc->tcl_data_ring[i],
  780. TCL_DATA, i, 0, TCL_DATA_RING_SIZE)) {
  781. QDF_TRACE(QDF_MODULE_ID_DP,
  782. QDF_TRACE_LEVEL_ERROR,
  783. FL("dp_srng_setup failed for tcl_data_ring[%d]"), i);
  784. goto fail1;
  785. }
  786. if (dp_srng_setup(soc, &soc->tx_comp_ring[i],
  787. WBM2SW_RELEASE, i, 0, TX_COMP_RING_SIZE)) {
  788. QDF_TRACE(QDF_MODULE_ID_DP,
  789. QDF_TRACE_LEVEL_ERROR,
  790. FL("dp_srng_setup failed for tx_comp_ring[%d]"), i);
  791. goto fail1;
  792. }
  793. }
  794. } else {
  795. /* This will be incremented during per pdev ring setup */
  796. soc->num_tcl_data_rings = 0;
  797. }
  798. if (dp_tx_soc_attach(soc)) {
  799. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  800. FL("dp_tx_soc_attach failed"));
  801. goto fail1;
  802. }
  803. /* TCL command and status rings */
  804. if (dp_srng_setup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0, 0,
  805. TCL_CMD_RING_SIZE)) {
  806. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  807. FL("dp_srng_setup failed for tcl_cmd_ring"));
  808. goto fail1;
  809. }
  810. if (dp_srng_setup(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0,
  811. TCL_STATUS_RING_SIZE)) {
  812. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  813. FL("dp_srng_setup failed for tcl_status_ring"));
  814. goto fail1;
  815. }
  816. /* TBD: call dp_tx_init to setup Tx SW descriptors and MSDU extension
  817. * descriptors
  818. */
  819. /* Rx data rings */
  820. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  821. soc->num_reo_dest_rings =
  822. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  823. QDF_TRACE(QDF_MODULE_ID_DP,
  824. QDF_TRACE_LEVEL_ERROR,
  825. FL("num_reo_dest_rings %d\n"), soc->num_reo_dest_rings);
  826. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  827. if (dp_srng_setup(soc, &soc->reo_dest_ring[i], REO_DST,
  828. i, 0, REO_DST_RING_SIZE)) {
  829. QDF_TRACE(QDF_MODULE_ID_DP,
  830. QDF_TRACE_LEVEL_ERROR,
  831. FL("dp_srng_setup failed for reo_dest_ring[%d]"), i);
  832. goto fail1;
  833. }
  834. }
  835. } else {
  836. /* This will be incremented during per pdev ring setup */
  837. soc->num_reo_dest_rings = 0;
  838. }
  839. /* TBD: call dp_rx_init to setup Rx SW descriptors */
  840. /* REO reinjection ring */
  841. if (dp_srng_setup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0,
  842. REO_REINJECT_RING_SIZE)) {
  843. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  844. FL("dp_srng_setup failed for reo_reinject_ring"));
  845. goto fail1;
  846. }
  847. /* Rx release ring */
  848. if (dp_srng_setup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 3, 0,
  849. RX_RELEASE_RING_SIZE)) {
  850. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  851. FL("dp_srng_setup failed for rx_rel_ring"));
  852. goto fail1;
  853. }
  854. /* Rx exception ring */
  855. if (dp_srng_setup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0,
  856. MAX_REO_DEST_RINGS, REO_EXCEPTION_RING_SIZE)) {
  857. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  858. FL("dp_srng_setup failed for reo_exception_ring"));
  859. goto fail1;
  860. }
  861. /* REO command and status rings */
  862. if (dp_srng_setup(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0,
  863. REO_CMD_RING_SIZE)) {
  864. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  865. FL("dp_srng_setup failed for reo_cmd_ring"));
  866. goto fail1;
  867. }
  868. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  869. TAILQ_INIT(&soc->rx.reo_cmd_list);
  870. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  871. if (dp_srng_setup(soc, &soc->reo_status_ring, REO_STATUS, 0, 0,
  872. REO_STATUS_RING_SIZE)) {
  873. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  874. FL("dp_srng_setup failed for reo_status_ring"));
  875. goto fail1;
  876. }
  877. /* Setup HW REO */
  878. qdf_mem_zero(&reo_params, sizeof(reo_params));
  879. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx))
  880. reo_params.rx_hash_enabled = true;
  881. hal_reo_setup(soc->hal_soc, &reo_params);
  882. qdf_atomic_set(&soc->cmn_init_done, 1);
  883. qdf_nbuf_queue_init(&soc->htt_stats_msg);
  884. return 0;
  885. fail1:
  886. /*
  887. * Cleanup will be done as part of soc_detach, which will
  888. * be called on pdev attach failure
  889. */
  890. fail0:
  891. return QDF_STATUS_E_FAILURE;
  892. }
  893. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force);
  894. static void dp_lro_hash_setup(struct dp_soc *soc)
  895. {
  896. struct cdp_lro_hash_config lro_hash;
  897. if (!wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  898. !wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  899. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  900. FL("LRO disabled RX hash disabled"));
  901. return;
  902. }
  903. qdf_mem_zero(&lro_hash, sizeof(lro_hash));
  904. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx)) {
  905. lro_hash.lro_enable = 1;
  906. lro_hash.tcp_flag = QDF_TCPHDR_ACK;
  907. lro_hash.tcp_flag_mask = QDF_TCPHDR_FIN | QDF_TCPHDR_SYN |
  908. QDF_TCPHDR_RST | QDF_TCPHDR_ACK | QDF_TCPHDR_URG |
  909. QDF_TCPHDR_ECE | QDF_TCPHDR_CWR;
  910. }
  911. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, FL("enabled"));
  912. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv4,
  913. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  914. LRO_IPV4_SEED_ARR_SZ));
  915. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv6,
  916. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  917. LRO_IPV6_SEED_ARR_SZ));
  918. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  919. "lro_hash: lro_enable: 0x%x"
  920. "lro_hash: tcp_flag 0x%x tcp_flag_mask 0x%x",
  921. lro_hash.lro_enable, lro_hash.tcp_flag,
  922. lro_hash.tcp_flag_mask);
  923. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  924. FL("lro_hash: toeplitz_hash_ipv4:"));
  925. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  926. QDF_TRACE_LEVEL_ERROR,
  927. (void *)lro_hash.toeplitz_hash_ipv4,
  928. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  929. LRO_IPV4_SEED_ARR_SZ));
  930. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  931. FL("lro_hash: toeplitz_hash_ipv6:"));
  932. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  933. QDF_TRACE_LEVEL_ERROR,
  934. (void *)lro_hash.toeplitz_hash_ipv6,
  935. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  936. LRO_IPV6_SEED_ARR_SZ));
  937. qdf_assert(soc->cdp_soc.ol_ops->lro_hash_config);
  938. if (soc->cdp_soc.ol_ops->lro_hash_config)
  939. (void)soc->cdp_soc.ol_ops->lro_hash_config
  940. (soc->osif_soc, &lro_hash);
  941. }
  942. /*
  943. * dp_rxdma_ring_setup() - configure the RX DMA rings
  944. * @soc: data path SoC handle
  945. * @pdev: Physical device handle
  946. *
  947. * Return: 0 - success, > 0 - failure
  948. */
  949. #ifdef QCA_HOST2FW_RXBUF_RING
  950. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  951. struct dp_pdev *pdev)
  952. {
  953. int max_mac_rings =
  954. wlan_cfg_get_num_mac_rings
  955. (pdev->wlan_cfg_ctx);
  956. int i;
  957. for (i = 0; i < max_mac_rings; i++) {
  958. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  959. "%s: pdev_id %d mac_id %d\n",
  960. __func__, pdev->pdev_id, i);
  961. if (dp_srng_setup(soc, &pdev->rx_mac_buf_ring[i],
  962. RXDMA_BUF, 1, i, RXDMA_BUF_RING_SIZE)) {
  963. QDF_TRACE(QDF_MODULE_ID_DP,
  964. QDF_TRACE_LEVEL_ERROR,
  965. FL("failed rx mac ring setup"));
  966. return QDF_STATUS_E_FAILURE;
  967. }
  968. }
  969. return QDF_STATUS_SUCCESS;
  970. }
  971. #else
  972. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  973. struct dp_pdev *pdev)
  974. {
  975. return QDF_STATUS_SUCCESS;
  976. }
  977. #endif
  978. /**
  979. * dp_dscp_tid_map_setup(): Initialize the dscp-tid maps
  980. * @pdev - DP_PDEV handle
  981. *
  982. * Return: void
  983. */
  984. static inline void
  985. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  986. {
  987. uint8_t map_id;
  988. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  989. qdf_mem_copy(pdev->dscp_tid_map[map_id], default_dscp_tid_map,
  990. sizeof(default_dscp_tid_map));
  991. }
  992. for (map_id = 0; map_id < HAL_MAX_HW_DSCP_TID_MAPS; map_id++) {
  993. hal_tx_set_dscp_tid_map(pdev->soc->hal_soc,
  994. pdev->dscp_tid_map[map_id],
  995. map_id);
  996. }
  997. }
  998. /*
  999. * dp_pdev_attach_wifi3() - attach txrx pdev
  1000. * @osif_pdev: Opaque PDEV handle from OSIF/HDD
  1001. * @txrx_soc: Datapath SOC handle
  1002. * @htc_handle: HTC handle for host-target interface
  1003. * @qdf_osdev: QDF OS device
  1004. * @pdev_id: PDEV ID
  1005. *
  1006. * Return: DP PDEV handle on success, NULL on failure
  1007. */
  1008. static struct cdp_pdev *dp_pdev_attach_wifi3(struct cdp_soc_t *txrx_soc,
  1009. struct cdp_cfg *ctrl_pdev,
  1010. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev, uint8_t pdev_id)
  1011. {
  1012. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1013. struct dp_pdev *pdev = qdf_mem_malloc(sizeof(*pdev));
  1014. if (!pdev) {
  1015. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1016. FL("DP PDEV memory allocation failed"));
  1017. goto fail0;
  1018. }
  1019. pdev->wlan_cfg_ctx = wlan_cfg_pdev_attach();
  1020. if (!pdev->wlan_cfg_ctx) {
  1021. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1022. FL("pdev cfg_attach failed"));
  1023. qdf_mem_free(pdev);
  1024. goto fail0;
  1025. }
  1026. /*
  1027. * set nss pdev config based on soc config
  1028. */
  1029. wlan_cfg_set_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx,
  1030. (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx) & (1 << pdev->pdev_id)));
  1031. pdev->soc = soc;
  1032. pdev->osif_pdev = ctrl_pdev;
  1033. pdev->pdev_id = pdev_id;
  1034. soc->pdev_list[pdev_id] = pdev;
  1035. soc->pdev_count++;
  1036. TAILQ_INIT(&pdev->vdev_list);
  1037. pdev->vdev_count = 0;
  1038. qdf_spinlock_create(&pdev->tx_mutex);
  1039. qdf_spinlock_create(&pdev->neighbour_peer_mutex);
  1040. TAILQ_INIT(&pdev->neighbour_peers_list);
  1041. if (dp_soc_cmn_setup(soc)) {
  1042. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1043. FL("dp_soc_cmn_setup failed"));
  1044. goto fail1;
  1045. }
  1046. /* Setup per PDEV TCL rings if configured */
  1047. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1048. if (dp_srng_setup(soc, &soc->tcl_data_ring[pdev_id], TCL_DATA,
  1049. pdev_id, pdev_id, TCL_DATA_RING_SIZE)) {
  1050. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1051. FL("dp_srng_setup failed for tcl_data_ring"));
  1052. goto fail1;
  1053. }
  1054. if (dp_srng_setup(soc, &soc->tx_comp_ring[pdev_id],
  1055. WBM2SW_RELEASE, pdev_id, pdev_id, TCL_DATA_RING_SIZE)) {
  1056. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1057. FL("dp_srng_setup failed for tx_comp_ring"));
  1058. goto fail1;
  1059. }
  1060. soc->num_tcl_data_rings++;
  1061. }
  1062. /* Tx specific init */
  1063. if (dp_tx_pdev_attach(pdev)) {
  1064. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1065. FL("dp_tx_pdev_attach failed"));
  1066. goto fail1;
  1067. }
  1068. /* Setup per PDEV REO rings if configured */
  1069. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1070. if (dp_srng_setup(soc, &soc->reo_dest_ring[pdev_id], REO_DST,
  1071. pdev_id, pdev_id, REO_DST_RING_SIZE)) {
  1072. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1073. FL("dp_srng_setup failed for reo_dest_ringn"));
  1074. goto fail1;
  1075. }
  1076. soc->num_reo_dest_rings++;
  1077. }
  1078. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0, pdev_id,
  1079. RXDMA_REFILL_RING_SIZE)) {
  1080. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1081. FL("dp_srng_setup failed rx refill ring"));
  1082. goto fail1;
  1083. }
  1084. if (dp_rxdma_ring_setup(soc, pdev)) {
  1085. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1086. FL("RXDMA ring config failed"));
  1087. goto fail1;
  1088. }
  1089. if (dp_srng_setup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0,
  1090. pdev_id, RXDMA_MONITOR_BUF_RING_SIZE)) {
  1091. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1092. FL("dp_srng_setup failed for rxdma_mon_buf_ring"));
  1093. goto fail1;
  1094. }
  1095. if (dp_srng_setup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0,
  1096. pdev_id, RXDMA_MONITOR_DST_RING_SIZE)) {
  1097. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1098. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  1099. goto fail1;
  1100. }
  1101. if (dp_srng_setup(soc, &pdev->rxdma_mon_status_ring,
  1102. RXDMA_MONITOR_STATUS, 0, pdev_id,
  1103. RXDMA_MONITOR_STATUS_RING_SIZE)) {
  1104. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1105. FL("dp_srng_setup failed for rxdma_mon_status_ring"));
  1106. goto fail1;
  1107. }
  1108. if (dp_srng_setup(soc, &pdev->rxdma_mon_desc_ring,
  1109. RXDMA_MONITOR_DESC, 0, pdev_id, RXDMA_MONITOR_DESC_RING_SIZE)) {
  1110. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1111. "dp_srng_setup failed for rxdma_mon_desc_ring\n");
  1112. goto fail1;
  1113. }
  1114. /* Rx specific init */
  1115. if (dp_rx_pdev_attach(pdev)) {
  1116. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1117. FL("dp_rx_pdev_attach failed "));
  1118. goto fail0;
  1119. }
  1120. DP_STATS_INIT(pdev);
  1121. #ifndef CONFIG_WIN
  1122. /* MCL */
  1123. dp_local_peer_id_pool_init(pdev);
  1124. #endif
  1125. dp_dscp_tid_map_setup(pdev);
  1126. /* Rx monitor mode specific init */
  1127. if (dp_rx_pdev_mon_attach(pdev)) {
  1128. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1129. "dp_rx_pdev_attach failed\n");
  1130. goto fail0;
  1131. }
  1132. /* set the reo destination to 1 during initialization */
  1133. pdev->reo_dest = 1;
  1134. return (struct cdp_pdev *)pdev;
  1135. fail1:
  1136. dp_pdev_detach_wifi3((struct cdp_pdev *)pdev, 0);
  1137. fail0:
  1138. return NULL;
  1139. }
  1140. /*
  1141. * dp_rxdma_ring_cleanup() - configure the RX DMA rings
  1142. * @soc: data path SoC handle
  1143. * @pdev: Physical device handle
  1144. *
  1145. * Return: void
  1146. */
  1147. #ifdef QCA_HOST2FW_RXBUF_RING
  1148. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  1149. struct dp_pdev *pdev)
  1150. {
  1151. int max_mac_rings =
  1152. wlan_cfg_get_num_mac_rings(pdev->wlan_cfg_ctx);
  1153. int i;
  1154. max_mac_rings = max_mac_rings < MAX_RX_MAC_RINGS ?
  1155. max_mac_rings : MAX_RX_MAC_RINGS;
  1156. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  1157. dp_srng_cleanup(soc, &pdev->rx_mac_buf_ring[i],
  1158. RXDMA_BUF, 1);
  1159. }
  1160. #else
  1161. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  1162. struct dp_pdev *pdev)
  1163. {
  1164. }
  1165. #endif
  1166. /*
  1167. * dp_neighbour_peers_detach() - Detach neighbour peers(nac clients)
  1168. * @pdev: device object
  1169. *
  1170. * Return: void
  1171. */
  1172. static void dp_neighbour_peers_detach(struct dp_pdev *pdev)
  1173. {
  1174. struct dp_neighbour_peer *peer = NULL;
  1175. struct dp_neighbour_peer *temp_peer = NULL;
  1176. TAILQ_FOREACH_SAFE(peer, &pdev->neighbour_peers_list,
  1177. neighbour_peer_list_elem, temp_peer) {
  1178. /* delete this peer from the list */
  1179. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  1180. peer, neighbour_peer_list_elem);
  1181. qdf_mem_free(peer);
  1182. }
  1183. qdf_spinlock_destroy(&pdev->neighbour_peer_mutex);
  1184. }
  1185. /*
  1186. * dp_pdev_detach_wifi3() - detach txrx pdev
  1187. * @txrx_pdev: Datapath PDEV handle
  1188. * @force: Force detach
  1189. *
  1190. */
  1191. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force)
  1192. {
  1193. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  1194. struct dp_soc *soc = pdev->soc;
  1195. dp_tx_pdev_detach(pdev);
  1196. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1197. dp_srng_cleanup(soc, &soc->tcl_data_ring[pdev->pdev_id],
  1198. TCL_DATA, pdev->pdev_id);
  1199. dp_srng_cleanup(soc, &soc->tx_comp_ring[pdev->pdev_id],
  1200. WBM2SW_RELEASE, pdev->pdev_id);
  1201. }
  1202. dp_rx_pdev_detach(pdev);
  1203. dp_rx_pdev_mon_detach(pdev);
  1204. dp_neighbour_peers_detach(pdev);
  1205. qdf_spinlock_destroy(&pdev->tx_mutex);
  1206. /* Setup per PDEV REO rings if configured */
  1207. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1208. dp_srng_cleanup(soc, &soc->reo_dest_ring[pdev->pdev_id],
  1209. REO_DST, pdev->pdev_id);
  1210. }
  1211. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0);
  1212. dp_rxdma_ring_cleanup(soc, pdev);
  1213. dp_srng_cleanup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0);
  1214. dp_srng_cleanup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0);
  1215. dp_srng_cleanup(soc, &pdev->rxdma_mon_status_ring,
  1216. RXDMA_MONITOR_STATUS, 0);
  1217. dp_srng_cleanup(soc, &pdev->rxdma_mon_desc_ring,
  1218. RXDMA_MONITOR_DESC, 0);
  1219. soc->pdev_list[pdev->pdev_id] = NULL;
  1220. soc->pdev_count--;
  1221. wlan_cfg_pdev_detach(pdev->wlan_cfg_ctx);
  1222. qdf_mem_free(pdev);
  1223. }
  1224. /*
  1225. * dp_reo_desc_freelist_destroy() - Flush REO descriptors from deferred freelist
  1226. * @soc: DP SOC handle
  1227. */
  1228. static inline void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  1229. {
  1230. struct reo_desc_list_node *desc;
  1231. struct dp_rx_tid *rx_tid;
  1232. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  1233. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  1234. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  1235. rx_tid = &desc->rx_tid;
  1236. qdf_mem_unmap_nbytes_single(soc->osdev,
  1237. rx_tid->hw_qdesc_paddr,
  1238. QDF_DMA_BIDIRECTIONAL,
  1239. rx_tid->hw_qdesc_alloc_size);
  1240. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  1241. qdf_mem_free(desc);
  1242. }
  1243. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  1244. qdf_list_destroy(&soc->reo_desc_freelist);
  1245. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  1246. }
  1247. /*
  1248. * dp_soc_detach_wifi3() - Detach txrx SOC
  1249. * @txrx_soc: DP SOC handle
  1250. *
  1251. */
  1252. static void dp_soc_detach_wifi3(void *txrx_soc)
  1253. {
  1254. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1255. int i;
  1256. qdf_atomic_set(&soc->cmn_init_done, 0);
  1257. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1258. if (soc->pdev_list[i])
  1259. dp_pdev_detach_wifi3(
  1260. (struct cdp_pdev *)soc->pdev_list[i], 1);
  1261. }
  1262. dp_peer_find_detach(soc);
  1263. /* TBD: Call Tx and Rx cleanup functions to free buffers and
  1264. * SW descriptors
  1265. */
  1266. /* Free the ring memories */
  1267. /* Common rings */
  1268. dp_srng_cleanup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  1269. dp_tx_soc_detach(soc);
  1270. /* Tx data rings */
  1271. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1272. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  1273. dp_srng_cleanup(soc, &soc->tcl_data_ring[i],
  1274. TCL_DATA, i);
  1275. dp_srng_cleanup(soc, &soc->tx_comp_ring[i],
  1276. WBM2SW_RELEASE, i);
  1277. }
  1278. }
  1279. /* TCL command and status rings */
  1280. dp_srng_cleanup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0);
  1281. dp_srng_cleanup(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  1282. /* Rx data rings */
  1283. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1284. soc->num_reo_dest_rings =
  1285. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1286. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  1287. /* TODO: Get number of rings and ring sizes
  1288. * from wlan_cfg
  1289. */
  1290. dp_srng_cleanup(soc, &soc->reo_dest_ring[i],
  1291. REO_DST, i);
  1292. }
  1293. }
  1294. /* REO reinjection ring */
  1295. dp_srng_cleanup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  1296. /* Rx release ring */
  1297. dp_srng_cleanup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  1298. /* Rx exception ring */
  1299. /* TODO: Better to store ring_type and ring_num in
  1300. * dp_srng during setup
  1301. */
  1302. dp_srng_cleanup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  1303. /* REO command and status rings */
  1304. dp_srng_cleanup(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  1305. dp_srng_cleanup(soc, &soc->reo_status_ring, REO_STATUS, 0);
  1306. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  1307. qdf_spinlock_destroy(&soc->peer_ref_mutex);
  1308. htt_soc_detach(soc->htt_handle);
  1309. dp_reo_desc_freelist_destroy(soc);
  1310. wlan_cfg_soc_detach(soc->wlan_cfg_ctx);
  1311. qdf_mem_free(soc);
  1312. }
  1313. /*
  1314. * dp_rxdma_ring_config() - configure the RX DMA rings
  1315. *
  1316. * This function is used to configure the MAC rings.
  1317. * On MCL host provides buffers in Host2FW ring
  1318. * FW refills (copies) buffers to the ring and updates
  1319. * ring_idx in register
  1320. *
  1321. * @soc: data path SoC handle
  1322. * @pdev: Physical device handle
  1323. *
  1324. * Return: void
  1325. */
  1326. #ifdef QCA_HOST2FW_RXBUF_RING
  1327. static void dp_rxdma_ring_config(struct dp_soc *soc)
  1328. {
  1329. int i;
  1330. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1331. struct dp_pdev *pdev = soc->pdev_list[i];
  1332. if (pdev) {
  1333. int mac_id = 0;
  1334. int j;
  1335. bool dbs_enable = 0;
  1336. int max_mac_rings =
  1337. wlan_cfg_get_num_mac_rings
  1338. (pdev->wlan_cfg_ctx);
  1339. htt_srng_setup(soc->htt_handle, 0,
  1340. pdev->rx_refill_buf_ring.hal_srng,
  1341. RXDMA_BUF);
  1342. if (soc->cdp_soc.ol_ops->
  1343. is_hw_dbs_2x2_capable) {
  1344. dbs_enable = soc->cdp_soc.ol_ops->
  1345. is_hw_dbs_2x2_capable(soc->psoc);
  1346. }
  1347. if (dbs_enable) {
  1348. QDF_TRACE(QDF_MODULE_ID_TXRX,
  1349. QDF_TRACE_LEVEL_ERROR,
  1350. FL("DBS enabled max_mac_rings %d\n"),
  1351. max_mac_rings);
  1352. } else {
  1353. max_mac_rings = 1;
  1354. QDF_TRACE(QDF_MODULE_ID_TXRX,
  1355. QDF_TRACE_LEVEL_ERROR,
  1356. FL("DBS disabled, max_mac_rings %d\n"),
  1357. max_mac_rings);
  1358. }
  1359. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1360. FL("pdev_id %d max_mac_rings %d\n"),
  1361. pdev->pdev_id, max_mac_rings);
  1362. for (j = 0; j < max_mac_rings; j++) {
  1363. QDF_TRACE(QDF_MODULE_ID_TXRX,
  1364. QDF_TRACE_LEVEL_ERROR,
  1365. FL("mac_id %d\n"), mac_id);
  1366. htt_srng_setup(soc->htt_handle, mac_id,
  1367. pdev->rx_mac_buf_ring[j]
  1368. .hal_srng,
  1369. RXDMA_BUF);
  1370. mac_id++;
  1371. }
  1372. }
  1373. }
  1374. }
  1375. #else
  1376. static void dp_rxdma_ring_config(struct dp_soc *soc)
  1377. {
  1378. int i;
  1379. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1380. struct dp_pdev *pdev = soc->pdev_list[i];
  1381. if (pdev) {
  1382. htt_srng_setup(soc->htt_handle, i,
  1383. pdev->rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  1384. htt_srng_setup(soc->htt_handle, i,
  1385. pdev->rxdma_mon_buf_ring.hal_srng,
  1386. RXDMA_MONITOR_BUF);
  1387. htt_srng_setup(soc->htt_handle, i,
  1388. pdev->rxdma_mon_dst_ring.hal_srng,
  1389. RXDMA_MONITOR_DST);
  1390. htt_srng_setup(soc->htt_handle, i,
  1391. pdev->rxdma_mon_status_ring.hal_srng,
  1392. RXDMA_MONITOR_STATUS);
  1393. htt_srng_setup(soc->htt_handle, i,
  1394. pdev->rxdma_mon_desc_ring.hal_srng,
  1395. RXDMA_MONITOR_DESC);
  1396. }
  1397. }
  1398. }
  1399. #endif
  1400. /*
  1401. * dp_soc_attach_target_wifi3() - SOC initialization in the target
  1402. * @txrx_soc: Datapath SOC handle
  1403. */
  1404. static int dp_soc_attach_target_wifi3(struct cdp_soc_t *cdp_soc)
  1405. {
  1406. struct dp_soc *soc = (struct dp_soc *)cdp_soc;
  1407. htt_soc_attach_target(soc->htt_handle);
  1408. dp_rxdma_ring_config(soc);
  1409. DP_STATS_INIT(soc);
  1410. return 0;
  1411. }
  1412. /*
  1413. * dp_soc_get_nss_cfg_wifi3() - SOC get nss config
  1414. * @txrx_soc: Datapath SOC handle
  1415. */
  1416. static int dp_soc_get_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc)
  1417. {
  1418. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  1419. return wlan_cfg_get_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx);
  1420. }
  1421. /*
  1422. * dp_soc_set_nss_cfg_wifi3() - SOC set nss config
  1423. * @txrx_soc: Datapath SOC handle
  1424. * @nss_cfg: nss config
  1425. */
  1426. static void dp_soc_set_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc, int config)
  1427. {
  1428. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  1429. wlan_cfg_set_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx, config);
  1430. if (config) {
  1431. /*
  1432. * disable dp interrupt if nss enabled
  1433. */
  1434. wlan_cfg_set_num_contexts(dsoc->wlan_cfg_ctx, 0);
  1435. }
  1436. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1437. FL("nss-wifi<0> nss config is enabled"));
  1438. }
  1439. /*
  1440. * dp_vdev_attach_wifi3() - attach txrx vdev
  1441. * @txrx_pdev: Datapath PDEV handle
  1442. * @vdev_mac_addr: MAC address of the virtual interface
  1443. * @vdev_id: VDEV Id
  1444. * @wlan_op_mode: VDEV operating mode
  1445. *
  1446. * Return: DP VDEV handle on success, NULL on failure
  1447. */
  1448. static struct cdp_vdev *dp_vdev_attach_wifi3(struct cdp_pdev *txrx_pdev,
  1449. uint8_t *vdev_mac_addr, uint8_t vdev_id, enum wlan_op_mode op_mode)
  1450. {
  1451. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  1452. struct dp_soc *soc = pdev->soc;
  1453. struct dp_vdev *vdev = qdf_mem_malloc(sizeof(*vdev));
  1454. if (!vdev) {
  1455. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1456. FL("DP VDEV memory allocation failed"));
  1457. goto fail0;
  1458. }
  1459. vdev->pdev = pdev;
  1460. vdev->vdev_id = vdev_id;
  1461. vdev->opmode = op_mode;
  1462. vdev->osdev = soc->osdev;
  1463. vdev->osif_rx = NULL;
  1464. vdev->osif_rsim_rx_decap = NULL;
  1465. vdev->osif_rx_mon = NULL;
  1466. vdev->osif_tx_free_ext = NULL;
  1467. vdev->osif_vdev = NULL;
  1468. vdev->delete.pending = 0;
  1469. vdev->safemode = 0;
  1470. vdev->drop_unenc = 1;
  1471. #ifdef notyet
  1472. vdev->filters_num = 0;
  1473. #endif
  1474. qdf_mem_copy(
  1475. &vdev->mac_addr.raw[0], vdev_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  1476. vdev->tx_encap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  1477. vdev->rx_decap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  1478. vdev->dscp_tid_map_id = 0;
  1479. vdev->mcast_enhancement_en = 0;
  1480. /* TODO: Initialize default HTT meta data that will be used in
  1481. * TCL descriptors for packets transmitted from this VDEV
  1482. */
  1483. TAILQ_INIT(&vdev->peer_list);
  1484. /* add this vdev into the pdev's list */
  1485. TAILQ_INSERT_TAIL(&pdev->vdev_list, vdev, vdev_list_elem);
  1486. pdev->vdev_count++;
  1487. dp_tx_vdev_attach(vdev);
  1488. #ifdef DP_INTR_POLL_BASED
  1489. if (wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx) != 0) {
  1490. if (pdev->vdev_count == 1)
  1491. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  1492. }
  1493. #endif
  1494. dp_lro_hash_setup(soc);
  1495. /* LRO */
  1496. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  1497. wlan_op_mode_sta == vdev->opmode)
  1498. vdev->lro_enable = true;
  1499. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1500. "LRO: vdev_id %d lro_enable %d", vdev_id, vdev->lro_enable);
  1501. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1502. "Created vdev %p (%pM)", vdev, vdev->mac_addr.raw);
  1503. DP_STATS_INIT(vdev);
  1504. return (struct cdp_vdev *)vdev;
  1505. fail0:
  1506. return NULL;
  1507. }
  1508. /**
  1509. * dp_vdev_register_wifi3() - Register VDEV operations from osif layer
  1510. * @vdev: Datapath VDEV handle
  1511. * @osif_vdev: OSIF vdev handle
  1512. * @txrx_ops: Tx and Rx operations
  1513. *
  1514. * Return: DP VDEV handle on success, NULL on failure
  1515. */
  1516. static void dp_vdev_register_wifi3(struct cdp_vdev *vdev_handle,
  1517. void *osif_vdev,
  1518. struct ol_txrx_ops *txrx_ops)
  1519. {
  1520. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  1521. vdev->osif_vdev = osif_vdev;
  1522. vdev->osif_rx = txrx_ops->rx.rx;
  1523. vdev->osif_rsim_rx_decap = txrx_ops->rx.rsim_rx_decap;
  1524. vdev->osif_rx_mon = txrx_ops->rx.mon;
  1525. vdev->osif_tx_free_ext = txrx_ops->tx.tx_free_ext;
  1526. #ifdef notyet
  1527. #if ATH_SUPPORT_WAPI
  1528. vdev->osif_check_wai = txrx_ops->rx.wai_check;
  1529. #endif
  1530. #endif
  1531. #ifdef UMAC_SUPPORT_PROXY_ARP
  1532. vdev->osif_proxy_arp = txrx_ops->proxy_arp;
  1533. #endif
  1534. vdev->me_convert = txrx_ops->me_convert;
  1535. /* TODO: Enable the following once Tx code is integrated */
  1536. txrx_ops->tx.tx = dp_tx_send;
  1537. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1538. "DP Vdev Register success");
  1539. }
  1540. /*
  1541. * dp_vdev_detach_wifi3() - Detach txrx vdev
  1542. * @txrx_vdev: Datapath VDEV handle
  1543. * @callback: Callback OL_IF on completion of detach
  1544. * @cb_context: Callback context
  1545. *
  1546. */
  1547. static void dp_vdev_detach_wifi3(struct cdp_vdev *vdev_handle,
  1548. ol_txrx_vdev_delete_cb callback, void *cb_context)
  1549. {
  1550. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  1551. struct dp_pdev *pdev = vdev->pdev;
  1552. struct dp_soc *soc = pdev->soc;
  1553. /* preconditions */
  1554. qdf_assert(vdev);
  1555. /* remove the vdev from its parent pdev's list */
  1556. TAILQ_REMOVE(&pdev->vdev_list, vdev, vdev_list_elem);
  1557. /*
  1558. * Use peer_ref_mutex while accessing peer_list, in case
  1559. * a peer is in the process of being removed from the list.
  1560. */
  1561. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  1562. /* check that the vdev has no peers allocated */
  1563. if (!TAILQ_EMPTY(&vdev->peer_list)) {
  1564. /* debug print - will be removed later */
  1565. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  1566. FL("not deleting vdev object %p (%pM)"
  1567. "until deletion finishes for all its peers"),
  1568. vdev, vdev->mac_addr.raw);
  1569. /* indicate that the vdev needs to be deleted */
  1570. vdev->delete.pending = 1;
  1571. vdev->delete.callback = callback;
  1572. vdev->delete.context = cb_context;
  1573. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  1574. return;
  1575. }
  1576. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  1577. dp_tx_vdev_detach(vdev);
  1578. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1579. FL("deleting vdev object %p (%pM)"), vdev, vdev->mac_addr.raw);
  1580. qdf_mem_free(vdev);
  1581. if (callback)
  1582. callback(cb_context);
  1583. }
  1584. /*
  1585. * dp_peer_create_wifi3() - attach txrx peer
  1586. * @txrx_vdev: Datapath VDEV handle
  1587. * @peer_mac_addr: Peer MAC address
  1588. *
  1589. * Return: DP peeer handle on success, NULL on failure
  1590. */
  1591. static void *dp_peer_create_wifi3(struct cdp_vdev *vdev_handle,
  1592. uint8_t *peer_mac_addr)
  1593. {
  1594. struct dp_peer *peer;
  1595. int i;
  1596. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  1597. struct dp_pdev *pdev;
  1598. struct dp_soc *soc;
  1599. /* preconditions */
  1600. qdf_assert(vdev);
  1601. qdf_assert(peer_mac_addr);
  1602. pdev = vdev->pdev;
  1603. soc = pdev->soc;
  1604. #ifdef notyet
  1605. peer = (struct dp_peer *)qdf_mempool_alloc(soc->osdev,
  1606. soc->mempool_ol_ath_peer);
  1607. #else
  1608. peer = (struct dp_peer *)qdf_mem_malloc(sizeof(*peer));
  1609. #endif
  1610. if (!peer)
  1611. return NULL; /* failure */
  1612. qdf_mem_zero(peer, sizeof(struct dp_peer));
  1613. TAILQ_INIT(&peer->ast_entry_list);
  1614. qdf_mem_copy(&peer->self_ast_entry.mac_addr, peer_mac_addr,
  1615. DP_MAC_ADDR_LEN);
  1616. peer->self_ast_entry.peer = peer;
  1617. TAILQ_INSERT_TAIL(&peer->ast_entry_list, &peer->self_ast_entry,
  1618. ast_entry_elem);
  1619. qdf_spinlock_create(&peer->peer_info_lock);
  1620. /* store provided params */
  1621. peer->vdev = vdev;
  1622. qdf_mem_copy(
  1623. &peer->mac_addr.raw[0], peer_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  1624. /* TODO: See of rx_opt_proc is really required */
  1625. peer->rx_opt_proc = soc->rx_opt_proc;
  1626. /* initialize the peer_id */
  1627. for (i = 0; i < MAX_NUM_PEER_ID_PER_PEER; i++)
  1628. peer->peer_ids[i] = HTT_INVALID_PEER;
  1629. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  1630. qdf_atomic_init(&peer->ref_cnt);
  1631. /* keep one reference for attach */
  1632. qdf_atomic_inc(&peer->ref_cnt);
  1633. /* add this peer into the vdev's list */
  1634. TAILQ_INSERT_TAIL(&vdev->peer_list, peer, peer_list_elem);
  1635. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  1636. /* TODO: See if hash based search is required */
  1637. dp_peer_find_hash_add(soc, peer);
  1638. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1639. "vdev %p created peer %p (%pM) ref_cnt: %d",
  1640. vdev, peer, peer->mac_addr.raw,
  1641. qdf_atomic_read(&peer->ref_cnt));
  1642. /*
  1643. * For every peer MAp message search and set if bss_peer
  1644. */
  1645. if (memcmp(peer->mac_addr.raw, vdev->mac_addr.raw, 6) == 0) {
  1646. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1647. "vdev bss_peer!!!!");
  1648. peer->bss_peer = 1;
  1649. vdev->vap_bss_peer = peer;
  1650. }
  1651. #ifndef CONFIG_WIN
  1652. dp_local_peer_id_alloc(pdev, peer);
  1653. #endif
  1654. DP_STATS_INIT(peer);
  1655. return (void *)peer;
  1656. }
  1657. /*
  1658. * dp_peer_setup_wifi3() - initialize the peer
  1659. * @vdev_hdl: virtual device object
  1660. * @peer: Peer object
  1661. *
  1662. * Return: void
  1663. */
  1664. static void dp_peer_setup_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  1665. {
  1666. struct dp_peer *peer = (struct dp_peer *)peer_hdl;
  1667. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  1668. struct dp_pdev *pdev;
  1669. struct dp_soc *soc;
  1670. bool hash_based = 0;
  1671. enum cdp_host_reo_dest_ring reo_dest;
  1672. /* preconditions */
  1673. qdf_assert(vdev);
  1674. qdf_assert(peer);
  1675. pdev = vdev->pdev;
  1676. soc = pdev->soc;
  1677. dp_peer_rx_init(pdev, peer);
  1678. peer->last_assoc_rcvd = 0;
  1679. peer->last_disassoc_rcvd = 0;
  1680. peer->last_deauth_rcvd = 0;
  1681. hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  1682. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1683. FL("hash based steering %d\n"), hash_based);
  1684. if (!hash_based)
  1685. reo_dest = pdev->reo_dest;
  1686. else
  1687. reo_dest = 1;
  1688. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  1689. /* TODO: Check the destination ring number to be passed to FW */
  1690. soc->cdp_soc.ol_ops->peer_set_default_routing(
  1691. pdev->osif_pdev, peer->mac_addr.raw,
  1692. peer->vdev->vdev_id, hash_based, reo_dest);
  1693. }
  1694. return;
  1695. }
  1696. /*
  1697. * dp_set_vdev_tx_encap_type() - set the encap type of the vdev
  1698. * @vdev_handle: virtual device object
  1699. * @htt_pkt_type: type of pkt
  1700. *
  1701. * Return: void
  1702. */
  1703. static void dp_set_vdev_tx_encap_type(struct cdp_vdev *vdev_handle,
  1704. enum htt_cmn_pkt_type val)
  1705. {
  1706. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  1707. vdev->tx_encap_type = val;
  1708. }
  1709. /*
  1710. * dp_set_vdev_rx_decap_type() - set the decap type of the vdev
  1711. * @vdev_handle: virtual device object
  1712. * @htt_pkt_type: type of pkt
  1713. *
  1714. * Return: void
  1715. */
  1716. static void dp_set_vdev_rx_decap_type(struct cdp_vdev *vdev_handle,
  1717. enum htt_cmn_pkt_type val)
  1718. {
  1719. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  1720. vdev->rx_decap_type = val;
  1721. }
  1722. /*
  1723. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  1724. * @pdev_handle: physical device object
  1725. * @val: reo destination ring index (1 - 4)
  1726. *
  1727. * Return: void
  1728. */
  1729. static void dp_set_pdev_reo_dest(struct cdp_pdev *pdev_handle,
  1730. enum cdp_host_reo_dest_ring val)
  1731. {
  1732. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  1733. if (pdev)
  1734. pdev->reo_dest = val;
  1735. }
  1736. /*
  1737. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  1738. * @pdev_handle: physical device object
  1739. *
  1740. * Return: reo destination ring index
  1741. */
  1742. static enum cdp_host_reo_dest_ring
  1743. dp_get_pdev_reo_dest(struct cdp_pdev *pdev_handle)
  1744. {
  1745. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  1746. if (pdev)
  1747. return pdev->reo_dest;
  1748. else
  1749. return cdp_host_reo_dest_ring_unknown;
  1750. }
  1751. #ifdef QCA_SUPPORT_SON
  1752. static void dp_son_peer_authorize(struct dp_peer *peer)
  1753. {
  1754. struct dp_soc *soc;
  1755. soc = peer->vdev->pdev->soc;
  1756. peer->peer_bs_inact_flag = 0;
  1757. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  1758. return;
  1759. }
  1760. #else
  1761. static void dp_son_peer_authorize(struct dp_peer *peer)
  1762. {
  1763. return;
  1764. }
  1765. #endif
  1766. /*
  1767. * dp_set_filter_neighbour_peers() - set filter neighbour peers for smart mesh
  1768. * @pdev_handle: device object
  1769. * @val: value to be set
  1770. *
  1771. * Return: void
  1772. */
  1773. static int dp_set_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  1774. uint32_t val)
  1775. {
  1776. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  1777. /* Enable/Disable smart mesh filtering. This flag will be checked
  1778. * during rx processing to check if packets are from NAC clients.
  1779. */
  1780. pdev->filter_neighbour_peers = val;
  1781. return 0;
  1782. }
  1783. /*
  1784. * dp_update_filter_neighbour_peers() - set neighbour peers(nac clients)
  1785. * address for smart mesh filtering
  1786. * @pdev_handle: device object
  1787. * @cmd: Add/Del command
  1788. * @macaddr: nac client mac address
  1789. *
  1790. * Return: void
  1791. */
  1792. static int dp_update_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  1793. uint32_t cmd, uint8_t *macaddr)
  1794. {
  1795. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  1796. struct dp_neighbour_peer *peer = NULL;
  1797. if (!macaddr)
  1798. goto fail0;
  1799. /* Store address of NAC (neighbour peer) which will be checked
  1800. * against TA of received packets.
  1801. */
  1802. if (cmd == DP_NAC_PARAM_ADD) {
  1803. peer = (struct dp_neighbour_peer *) qdf_mem_malloc(
  1804. sizeof(*peer));
  1805. if (!peer) {
  1806. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1807. FL("DP neighbour peer node memory allocation failed"));
  1808. goto fail0;
  1809. }
  1810. qdf_mem_copy(&peer->neighbour_peers_macaddr.raw[0],
  1811. macaddr, DP_MAC_ADDR_LEN);
  1812. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  1813. /* add this neighbour peer into the list */
  1814. TAILQ_INSERT_TAIL(&pdev->neighbour_peers_list, peer,
  1815. neighbour_peer_list_elem);
  1816. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  1817. return 1;
  1818. } else if (cmd == DP_NAC_PARAM_DEL) {
  1819. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  1820. TAILQ_FOREACH(peer, &pdev->neighbour_peers_list,
  1821. neighbour_peer_list_elem) {
  1822. if (!qdf_mem_cmp(&peer->neighbour_peers_macaddr.raw[0],
  1823. macaddr, DP_MAC_ADDR_LEN)) {
  1824. /* delete this peer from the list */
  1825. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  1826. peer, neighbour_peer_list_elem);
  1827. qdf_mem_free(peer);
  1828. break;
  1829. }
  1830. }
  1831. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  1832. return 1;
  1833. }
  1834. fail0:
  1835. return 0;
  1836. }
  1837. /*
  1838. * dp_peer_authorize() - authorize txrx peer
  1839. * @peer_handle: Datapath peer handle
  1840. * @authorize
  1841. *
  1842. */
  1843. static void dp_peer_authorize(void *peer_handle, uint32_t authorize)
  1844. {
  1845. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  1846. struct dp_soc *soc;
  1847. if (peer != NULL) {
  1848. soc = peer->vdev->pdev->soc;
  1849. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  1850. dp_son_peer_authorize(peer);
  1851. peer->authorize = authorize ? 1 : 0;
  1852. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  1853. }
  1854. }
  1855. /*
  1856. * dp_peer_unref_delete() - unref and delete peer
  1857. * @peer_handle: Datapath peer handle
  1858. *
  1859. */
  1860. void dp_peer_unref_delete(void *peer_handle)
  1861. {
  1862. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  1863. struct dp_vdev *vdev = peer->vdev;
  1864. struct dp_pdev *pdev = vdev->pdev;
  1865. struct dp_soc *soc = pdev->soc;
  1866. struct dp_peer *tmppeer;
  1867. int found = 0;
  1868. uint16_t peer_id;
  1869. uint16_t hw_peer_id;
  1870. struct dp_ast_entry *ast_entry;
  1871. /*
  1872. * Hold the lock all the way from checking if the peer ref count
  1873. * is zero until the peer references are removed from the hash
  1874. * table and vdev list (if the peer ref count is zero).
  1875. * This protects against a new HL tx operation starting to use the
  1876. * peer object just after this function concludes it's done being used.
  1877. * Furthermore, the lock needs to be held while checking whether the
  1878. * vdev's list of peers is empty, to make sure that list is not modified
  1879. * concurrently with the empty check.
  1880. */
  1881. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  1882. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1883. "%s: peer %p ref_cnt(before decrement): %d\n", __func__,
  1884. peer, qdf_atomic_read(&peer->ref_cnt));
  1885. if (qdf_atomic_dec_and_test(&peer->ref_cnt)) {
  1886. peer_id = peer->peer_ids[0];
  1887. /*
  1888. * Make sure that the reference to the peer in
  1889. * peer object map is removed
  1890. */
  1891. if (peer_id != HTT_INVALID_PEER)
  1892. soc->peer_id_to_obj_map[peer_id] = NULL;
  1893. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1894. "Deleting peer %p (%pM)", peer, peer->mac_addr.raw);
  1895. /* remove the reference to the peer from the hash table */
  1896. dp_peer_find_hash_remove(soc, peer);
  1897. TAILQ_FOREACH(tmppeer, &peer->vdev->peer_list, peer_list_elem) {
  1898. if (tmppeer == peer) {
  1899. found = 1;
  1900. break;
  1901. }
  1902. }
  1903. if (found) {
  1904. TAILQ_REMOVE(&peer->vdev->peer_list, peer,
  1905. peer_list_elem);
  1906. } else {
  1907. /*Ignoring the remove operation as peer not found*/
  1908. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  1909. "peer %p not found in vdev (%p)->peer_list:%p",
  1910. peer, vdev, &peer->vdev->peer_list);
  1911. }
  1912. /* cleanup the peer data */
  1913. dp_peer_cleanup(vdev, peer);
  1914. /* check whether the parent vdev has no peers left */
  1915. if (TAILQ_EMPTY(&vdev->peer_list)) {
  1916. /*
  1917. * Now that there are no references to the peer, we can
  1918. * release the peer reference lock.
  1919. */
  1920. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  1921. /*
  1922. * Check if the parent vdev was waiting for its peers
  1923. * to be deleted, in order for it to be deleted too.
  1924. */
  1925. if (vdev->delete.pending) {
  1926. ol_txrx_vdev_delete_cb vdev_delete_cb =
  1927. vdev->delete.callback;
  1928. void *vdev_delete_context =
  1929. vdev->delete.context;
  1930. QDF_TRACE(QDF_MODULE_ID_DP,
  1931. QDF_TRACE_LEVEL_INFO_HIGH,
  1932. FL("deleting vdev object %p (%pM)"
  1933. " - its last peer is done"),
  1934. vdev, vdev->mac_addr.raw);
  1935. /* all peers are gone, go ahead and delete it */
  1936. qdf_mem_free(vdev);
  1937. if (vdev_delete_cb)
  1938. vdev_delete_cb(vdev_delete_context);
  1939. }
  1940. } else {
  1941. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  1942. }
  1943. #ifdef notyet
  1944. qdf_mempool_free(soc->osdev, soc->mempool_ol_ath_peer, peer);
  1945. #else
  1946. TAILQ_FOREACH(ast_entry, &peer->ast_entry_list,
  1947. ast_entry_elem) {
  1948. hw_peer_id = ast_entry->ast_idx;
  1949. if (peer->self_ast_entry.ast_idx != hw_peer_id)
  1950. qdf_mem_free(ast_entry);
  1951. else
  1952. peer->self_ast_entry.ast_idx =
  1953. HTT_INVALID_PEER;
  1954. soc->ast_table[hw_peer_id] = NULL;
  1955. }
  1956. qdf_mem_free(peer);
  1957. #endif
  1958. if (soc->cdp_soc.ol_ops->peer_unref_delete) {
  1959. soc->cdp_soc.ol_ops->peer_unref_delete(pdev->osif_pdev,
  1960. vdev->vdev_id, peer->mac_addr.raw);
  1961. }
  1962. } else {
  1963. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  1964. }
  1965. }
  1966. /*
  1967. * dp_peer_detach_wifi3() – Detach txrx peer
  1968. * @peer_handle: Datapath peer handle
  1969. *
  1970. */
  1971. static void dp_peer_delete_wifi3(void *peer_handle)
  1972. {
  1973. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  1974. /* redirect the peer's rx delivery function to point to a
  1975. * discard func
  1976. */
  1977. peer->rx_opt_proc = dp_rx_discard;
  1978. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1979. FL("peer %p (%pM)"), peer, peer->mac_addr.raw);
  1980. #ifndef CONFIG_WIN
  1981. dp_local_peer_id_free(peer->vdev->pdev, peer);
  1982. #endif
  1983. qdf_spinlock_destroy(&peer->peer_info_lock);
  1984. /*
  1985. * Remove the reference added during peer_attach.
  1986. * The peer will still be left allocated until the
  1987. * PEER_UNMAP message arrives to remove the other
  1988. * reference, added by the PEER_MAP message.
  1989. */
  1990. dp_peer_unref_delete(peer_handle);
  1991. }
  1992. /*
  1993. * dp_get_vdev_mac_addr_wifi3() – Detach txrx peer
  1994. * @peer_handle: Datapath peer handle
  1995. *
  1996. */
  1997. static uint8 *dp_get_vdev_mac_addr_wifi3(struct cdp_vdev *pvdev)
  1998. {
  1999. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2000. return vdev->mac_addr.raw;
  2001. }
  2002. /*
  2003. * dp_vdev_set_wds() - Enable per packet stats
  2004. * @vdev_handle: DP VDEV handle
  2005. * @val: value
  2006. *
  2007. * Return: none
  2008. */
  2009. static int dp_vdev_set_wds(void *vdev_handle, uint32_t val)
  2010. {
  2011. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2012. vdev->wds_enabled = val;
  2013. return 0;
  2014. }
  2015. /*
  2016. * dp_get_vdev_from_vdev_id_wifi3() – Detach txrx peer
  2017. * @peer_handle: Datapath peer handle
  2018. *
  2019. */
  2020. static struct cdp_vdev *dp_get_vdev_from_vdev_id_wifi3(struct cdp_pdev *dev,
  2021. uint8_t vdev_id)
  2022. {
  2023. struct dp_pdev *pdev = (struct dp_pdev *)dev;
  2024. struct dp_vdev *vdev = NULL;
  2025. if (qdf_unlikely(!pdev))
  2026. return NULL;
  2027. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  2028. if (vdev->vdev_id == vdev_id)
  2029. break;
  2030. }
  2031. return (struct cdp_vdev *)vdev;
  2032. }
  2033. static int dp_get_opmode(struct cdp_vdev *vdev_handle)
  2034. {
  2035. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2036. return vdev->opmode;
  2037. }
  2038. static struct cdp_cfg *dp_get_ctrl_pdev_from_vdev_wifi3(struct cdp_vdev *pvdev)
  2039. {
  2040. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2041. struct dp_pdev *pdev = vdev->pdev;
  2042. return (struct cdp_cfg *)pdev->wlan_cfg_ctx;
  2043. }
  2044. /**
  2045. * dp_vdev_set_monitor_mode() - Set DP VDEV to monitor mode
  2046. * @vdev_handle: Datapath VDEV handle
  2047. * @smart_monitor: Flag to denote if its smart monitor mode
  2048. *
  2049. * Return: 0 on success, not 0 on failure
  2050. */
  2051. static int dp_vdev_set_monitor_mode(struct cdp_vdev *vdev_handle,
  2052. uint8_t smart_monitor)
  2053. {
  2054. /* Many monitor VAPs can exists in a system but only one can be up at
  2055. * anytime
  2056. */
  2057. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2058. struct dp_pdev *pdev;
  2059. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  2060. struct dp_soc *soc;
  2061. uint8_t pdev_id;
  2062. qdf_assert(vdev);
  2063. pdev = vdev->pdev;
  2064. pdev_id = pdev->pdev_id;
  2065. soc = pdev->soc;
  2066. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  2067. "pdev=%p, pdev_id=%d, soc=%p vdev=%p\n",
  2068. pdev, pdev_id, soc, vdev);
  2069. /*Check if current pdev's monitor_vdev exists */
  2070. if (pdev->monitor_vdev) {
  2071. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2072. "vdev=%p\n", vdev);
  2073. qdf_assert(vdev);
  2074. }
  2075. pdev->monitor_vdev = vdev;
  2076. /* If smart monitor mode, do not configure monitor ring */
  2077. if (smart_monitor)
  2078. return QDF_STATUS_SUCCESS;
  2079. htt_tlv_filter.mpdu_start = 1;
  2080. htt_tlv_filter.msdu_start = 1;
  2081. htt_tlv_filter.packet = 1;
  2082. htt_tlv_filter.msdu_end = 1;
  2083. htt_tlv_filter.mpdu_end = 1;
  2084. htt_tlv_filter.packet_header = 1;
  2085. htt_tlv_filter.attention = 1;
  2086. htt_tlv_filter.ppdu_start = 0;
  2087. htt_tlv_filter.ppdu_end = 0;
  2088. htt_tlv_filter.ppdu_end_user_stats = 0;
  2089. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  2090. htt_tlv_filter.ppdu_end_status_done = 0;
  2091. htt_tlv_filter.enable_fp = 1;
  2092. htt_tlv_filter.enable_md = 0;
  2093. htt_tlv_filter.enable_mo = 1;
  2094. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  2095. pdev->rxdma_mon_buf_ring.hal_srng,
  2096. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  2097. htt_tlv_filter.mpdu_start = 1;
  2098. htt_tlv_filter.msdu_start = 1;
  2099. htt_tlv_filter.packet = 0;
  2100. htt_tlv_filter.msdu_end = 1;
  2101. htt_tlv_filter.mpdu_end = 1;
  2102. htt_tlv_filter.packet_header = 1;
  2103. htt_tlv_filter.attention = 1;
  2104. htt_tlv_filter.ppdu_start = 1;
  2105. htt_tlv_filter.ppdu_end = 1;
  2106. htt_tlv_filter.ppdu_end_user_stats = 1;
  2107. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  2108. htt_tlv_filter.ppdu_end_status_done = 1;
  2109. htt_tlv_filter.enable_fp = 1;
  2110. htt_tlv_filter.enable_md = 0;
  2111. htt_tlv_filter.enable_mo = 1;
  2112. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  2113. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  2114. RX_BUFFER_SIZE, &htt_tlv_filter);
  2115. return QDF_STATUS_SUCCESS;
  2116. }
  2117. #ifdef MESH_MODE_SUPPORT
  2118. void dp_peer_set_mesh_mode(struct cdp_vdev *vdev_hdl, uint32_t val)
  2119. {
  2120. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2121. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2122. FL("val %d"), val);
  2123. vdev->mesh_vdev = val;
  2124. }
  2125. /*
  2126. * dp_peer_set_mesh_rx_filter() - to set the mesh rx filter
  2127. * @vdev_hdl: virtual device object
  2128. * @val: value to be set
  2129. *
  2130. * Return: void
  2131. */
  2132. void dp_peer_set_mesh_rx_filter(struct cdp_vdev *vdev_hdl, uint32_t val)
  2133. {
  2134. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2135. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2136. FL("val %d"), val);
  2137. vdev->mesh_rx_filter = val;
  2138. }
  2139. #endif
  2140. /**
  2141. * dp_aggregate_vdev_stats(): Consolidate stats at VDEV level
  2142. * @vdev: DP VDEV handle
  2143. *
  2144. * return: void
  2145. */
  2146. void dp_aggregate_vdev_stats(struct dp_vdev *vdev)
  2147. {
  2148. struct dp_peer *peer = NULL;
  2149. int i;
  2150. qdf_mem_set(&(vdev->stats.tx), sizeof(vdev->stats.tx), 0x0);
  2151. qdf_mem_set(&(vdev->stats.rx), sizeof(vdev->stats.rx), 0x0);
  2152. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2153. if (!peer)
  2154. return;
  2155. for (i = 0; i <= MAX_MCS; i++) {
  2156. DP_STATS_AGGR(vdev, peer, tx.pkt_type[0].mcs_count[i]);
  2157. DP_STATS_AGGR(vdev, peer, tx.pkt_type[1].mcs_count[i]);
  2158. DP_STATS_AGGR(vdev, peer, tx.pkt_type[2].mcs_count[i]);
  2159. DP_STATS_AGGR(vdev, peer, tx.pkt_type[3].mcs_count[i]);
  2160. DP_STATS_AGGR(vdev, peer, tx.pkt_type[4].mcs_count[i]);
  2161. DP_STATS_AGGR(vdev, peer, rx.pkt_type[0].mcs_count[i]);
  2162. DP_STATS_AGGR(vdev, peer, rx.pkt_type[1].mcs_count[i]);
  2163. DP_STATS_AGGR(vdev, peer, rx.pkt_type[2].mcs_count[i]);
  2164. DP_STATS_AGGR(vdev, peer, rx.pkt_type[3].mcs_count[i]);
  2165. DP_STATS_AGGR(vdev, peer, rx.pkt_type[4].mcs_count[i]);
  2166. }
  2167. for (i = 0; i < SUPPORTED_BW; i++) {
  2168. DP_STATS_AGGR(vdev, peer, tx.bw[i]);
  2169. DP_STATS_AGGR(vdev, peer, rx.bw[i]);
  2170. }
  2171. for (i = 0; i < SS_COUNT; i++)
  2172. DP_STATS_AGGR(vdev, peer, rx.nss[i]);
  2173. for (i = 0; i < WME_AC_MAX; i++) {
  2174. DP_STATS_AGGR(vdev, peer, tx.wme_ac_type[i]);
  2175. DP_STATS_AGGR(vdev, peer, rx.wme_ac_type[i]);
  2176. DP_STATS_AGGR(vdev, peer, tx.excess_retries_ac[i]);
  2177. }
  2178. for (i = 0; i < MAX_MCS + 1; i++) {
  2179. DP_STATS_AGGR(vdev, peer, tx.sgi_count[i]);
  2180. DP_STATS_AGGR(vdev, peer, rx.sgi_count[i]);
  2181. }
  2182. DP_STATS_AGGR_PKT(vdev, peer, tx.comp_pkt);
  2183. DP_STATS_AGGR_PKT(vdev, peer, tx.ucast);
  2184. DP_STATS_AGGR_PKT(vdev, peer, tx.mcast);
  2185. DP_STATS_AGGR_PKT(vdev, peer, tx.tx_success);
  2186. DP_STATS_AGGR(vdev, peer, tx.tx_failed);
  2187. DP_STATS_AGGR(vdev, peer, tx.ofdma);
  2188. DP_STATS_AGGR(vdev, peer, tx.stbc);
  2189. DP_STATS_AGGR(vdev, peer, tx.ldpc);
  2190. DP_STATS_AGGR(vdev, peer, tx.retries);
  2191. DP_STATS_AGGR(vdev, peer, tx.non_amsdu_cnt);
  2192. DP_STATS_AGGR(vdev, peer, tx.amsdu_cnt);
  2193. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_discard);
  2194. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_discard_retired);
  2195. DP_STATS_AGGR(vdev, peer, tx.dropped.mpdu_age_out);
  2196. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_discard_reason1);
  2197. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_discard_reason2);
  2198. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_discard_reason3);
  2199. DP_STATS_AGGR(vdev, peer, rx.err.mic_err);
  2200. DP_STATS_AGGR(vdev, peer, rx.err.decrypt_err);
  2201. DP_STATS_AGGR(vdev, peer, rx.non_ampdu_cnt);
  2202. DP_STATS_AGGR(vdev, peer, rx.ampdu_cnt);
  2203. DP_STATS_AGGR(vdev, peer, rx.non_amsdu_cnt);
  2204. DP_STATS_AGGR(vdev, peer, rx.amsdu_cnt);
  2205. DP_STATS_AGGR_PKT(vdev, peer, rx.to_stack);
  2206. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  2207. DP_STATS_AGGR_PKT(vdev, peer, rx.rcvd_reo[i]);
  2208. peer->stats.rx.unicast.num = peer->stats.rx.to_stack.num -
  2209. peer->stats.rx.multicast.num;
  2210. peer->stats.rx.unicast.bytes = peer->stats.rx.to_stack.bytes -
  2211. peer->stats.rx.multicast.bytes;
  2212. DP_STATS_AGGR_PKT(vdev, peer, rx.unicast);
  2213. DP_STATS_AGGR_PKT(vdev, peer, rx.multicast);
  2214. DP_STATS_AGGR_PKT(vdev, peer, rx.wds);
  2215. DP_STATS_AGGR_PKT(vdev, peer, rx.raw);
  2216. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.pkts);
  2217. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.fail);
  2218. vdev->stats.tx.last_ack_rssi =
  2219. peer->stats.tx.last_ack_rssi;
  2220. }
  2221. }
  2222. /**
  2223. * dp_aggregate_pdev_stats(): Consolidate stats at PDEV level
  2224. * @pdev: DP PDEV handle
  2225. *
  2226. * return: void
  2227. */
  2228. static inline void dp_aggregate_pdev_stats(struct dp_pdev *pdev)
  2229. {
  2230. struct dp_vdev *vdev = NULL;
  2231. uint8_t i;
  2232. qdf_mem_set(&(pdev->stats.tx), sizeof(pdev->stats.tx), 0x0);
  2233. qdf_mem_set(&(pdev->stats.rx), sizeof(pdev->stats.rx), 0x0);
  2234. qdf_mem_set(&(pdev->stats.tx_i), sizeof(pdev->stats.tx_i), 0x0);
  2235. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  2236. if (!vdev)
  2237. return;
  2238. dp_aggregate_vdev_stats(vdev);
  2239. for (i = 0; i <= MAX_MCS; i++) {
  2240. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[0].mcs_count[i]);
  2241. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[1].mcs_count[i]);
  2242. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[2].mcs_count[i]);
  2243. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[3].mcs_count[i]);
  2244. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[4].mcs_count[i]);
  2245. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[0].mcs_count[i]);
  2246. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[1].mcs_count[i]);
  2247. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[2].mcs_count[i]);
  2248. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[3].mcs_count[i]);
  2249. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[4].mcs_count[i]);
  2250. }
  2251. for (i = 0; i < SUPPORTED_BW; i++) {
  2252. DP_STATS_AGGR(pdev, vdev, tx.bw[i]);
  2253. DP_STATS_AGGR(pdev, vdev, rx.bw[i]);
  2254. }
  2255. for (i = 0; i < SS_COUNT; i++)
  2256. DP_STATS_AGGR(pdev, vdev, rx.nss[i]);
  2257. for (i = 0; i < WME_AC_MAX; i++) {
  2258. DP_STATS_AGGR(pdev, vdev, tx.wme_ac_type[i]);
  2259. DP_STATS_AGGR(pdev, vdev, rx.wme_ac_type[i]);
  2260. DP_STATS_AGGR(pdev, vdev,
  2261. tx.excess_retries_ac[i]);
  2262. }
  2263. for (i = 0; i < MAX_MCS + 1; i++) {
  2264. DP_STATS_AGGR(pdev, vdev, tx.sgi_count[i]);
  2265. DP_STATS_AGGR(pdev, vdev, rx.sgi_count[i]);
  2266. }
  2267. DP_STATS_AGGR_PKT(pdev, vdev, tx.comp_pkt);
  2268. DP_STATS_AGGR_PKT(pdev, vdev, tx.ucast);
  2269. DP_STATS_AGGR_PKT(pdev, vdev, tx.mcast);
  2270. DP_STATS_AGGR_PKT(pdev, vdev, tx.tx_success);
  2271. DP_STATS_AGGR(pdev, vdev, tx.tx_failed);
  2272. DP_STATS_AGGR(pdev, vdev, tx.ofdma);
  2273. DP_STATS_AGGR(pdev, vdev, tx.stbc);
  2274. DP_STATS_AGGR(pdev, vdev, tx.ldpc);
  2275. DP_STATS_AGGR(pdev, vdev, tx.retries);
  2276. DP_STATS_AGGR(pdev, vdev, tx.non_amsdu_cnt);
  2277. DP_STATS_AGGR(pdev, vdev, tx.amsdu_cnt);
  2278. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_discard);
  2279. DP_STATS_AGGR(pdev, vdev,
  2280. tx.dropped.fw_discard_retired);
  2281. DP_STATS_AGGR(pdev, vdev, tx.dropped.mpdu_age_out);
  2282. DP_STATS_AGGR(pdev, vdev,
  2283. tx.dropped.fw_discard_reason1);
  2284. DP_STATS_AGGR(pdev, vdev,
  2285. tx.dropped.fw_discard_reason2);
  2286. DP_STATS_AGGR(pdev, vdev,
  2287. tx.dropped.fw_discard_reason3);
  2288. DP_STATS_AGGR(pdev, vdev, rx.err.mic_err);
  2289. DP_STATS_AGGR(pdev, vdev, rx.err.decrypt_err);
  2290. DP_STATS_AGGR(pdev, vdev, rx.non_ampdu_cnt);
  2291. DP_STATS_AGGR(pdev, vdev, rx.ampdu_cnt);
  2292. DP_STATS_AGGR(pdev, vdev, rx.non_amsdu_cnt);
  2293. DP_STATS_AGGR(pdev, vdev, rx.amsdu_cnt);
  2294. DP_STATS_AGGR_PKT(pdev, vdev, rx.to_stack);
  2295. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[0]);
  2296. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[1]);
  2297. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[2]);
  2298. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[3]);
  2299. DP_STATS_AGGR_PKT(pdev, vdev, rx.unicast);
  2300. DP_STATS_AGGR_PKT(pdev, vdev, rx.multicast);
  2301. DP_STATS_AGGR_PKT(pdev, vdev, rx.wds);
  2302. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.pkts);
  2303. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.fail);
  2304. DP_STATS_AGGR_PKT(pdev, vdev, rx.raw);
  2305. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.rcvd);
  2306. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.processed);
  2307. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.reinject_pkts);
  2308. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.inspect_pkts);
  2309. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.raw.raw_pkt);
  2310. DP_STATS_AGGR(pdev, vdev, tx_i.raw.dma_map_error);
  2311. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.tso.tso_pkt);
  2312. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_host);
  2313. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_target);
  2314. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_host);
  2315. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_target);
  2316. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.sg.sg_pkt);
  2317. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.mcast_en.mcast_pkt);
  2318. DP_STATS_AGGR(pdev, vdev,
  2319. tx_i.mcast_en.dropped_map_error);
  2320. DP_STATS_AGGR(pdev, vdev,
  2321. tx_i.mcast_en.dropped_self_mac);
  2322. DP_STATS_AGGR(pdev, vdev,
  2323. tx_i.mcast_en.dropped_send_fail);
  2324. DP_STATS_AGGR(pdev, vdev, tx_i.mcast_en.ucast);
  2325. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.dma_error);
  2326. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.ring_full);
  2327. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.enqueue_fail);
  2328. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.desc_na);
  2329. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.res_full);
  2330. pdev->stats.tx_i.dropped.dropped_pkt.num =
  2331. pdev->stats.tx_i.dropped.dma_error +
  2332. pdev->stats.tx_i.dropped.ring_full +
  2333. pdev->stats.tx_i.dropped.enqueue_fail +
  2334. pdev->stats.tx_i.dropped.desc_na +
  2335. pdev->stats.tx_i.dropped.res_full;
  2336. pdev->stats.tx.last_ack_rssi =
  2337. vdev->stats.tx.last_ack_rssi;
  2338. pdev->stats.tx_i.tso.num_seg =
  2339. vdev->stats.tx_i.tso.num_seg;
  2340. }
  2341. }
  2342. /**
  2343. * dp_print_pdev_tx_stats(): Print Pdev level TX stats
  2344. * @pdev: DP_PDEV Handle
  2345. *
  2346. * Return:void
  2347. */
  2348. static inline void
  2349. dp_print_pdev_tx_stats(struct dp_pdev *pdev)
  2350. {
  2351. DP_TRACE_STATS(FATAL, "WLAN Tx Stats:\n");
  2352. DP_TRACE_STATS(FATAL, "Received From Stack:\n");
  2353. DP_TRACE_STATS(FATAL, "Packets = %d",
  2354. pdev->stats.tx_i.rcvd.num);
  2355. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  2356. pdev->stats.tx_i.rcvd.bytes);
  2357. DP_TRACE_STATS(FATAL, "Processed:\n");
  2358. DP_TRACE_STATS(FATAL, "Packets = %d",
  2359. pdev->stats.tx_i.processed.num);
  2360. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  2361. pdev->stats.tx_i.processed.bytes);
  2362. DP_TRACE_STATS(FATAL, "Completions:\n");
  2363. DP_TRACE_STATS(FATAL, "Packets = %d",
  2364. pdev->stats.tx.comp_pkt.num);
  2365. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  2366. pdev->stats.tx.comp_pkt.bytes);
  2367. DP_TRACE_STATS(FATAL, "Dropped:\n");
  2368. DP_TRACE_STATS(FATAL, "Packets = %d",
  2369. pdev->stats.tx_i.dropped.dropped_pkt.num);
  2370. DP_TRACE_STATS(FATAL, "Dma_map_error = %d",
  2371. pdev->stats.tx_i.dropped.dma_error);
  2372. DP_TRACE_STATS(FATAL, "Ring Full = %d",
  2373. pdev->stats.tx_i.dropped.ring_full);
  2374. DP_TRACE_STATS(FATAL, "Descriptor Not available = %d",
  2375. pdev->stats.tx_i.dropped.desc_na);
  2376. DP_TRACE_STATS(FATAL, "HW enqueue failed= %d",
  2377. pdev->stats.tx_i.dropped.enqueue_fail);
  2378. DP_TRACE_STATS(FATAL, "Resources Full = %d",
  2379. pdev->stats.tx_i.dropped.res_full);
  2380. DP_TRACE_STATS(FATAL, "Fw Discard = %d",
  2381. pdev->stats.tx.dropped.fw_discard);
  2382. DP_TRACE_STATS(FATAL, "Fw Discard Retired = %d",
  2383. pdev->stats.tx.dropped.fw_discard_retired);
  2384. DP_TRACE_STATS(FATAL, "Firmware Discard Untransmitted = %d",
  2385. pdev->stats.tx.dropped.fw_discard_untransmitted);
  2386. DP_TRACE_STATS(FATAL, "Mpdu Age Out = %d",
  2387. pdev->stats.tx.dropped.mpdu_age_out);
  2388. DP_TRACE_STATS(FATAL, "Firmware Discard Reason1 = %d",
  2389. pdev->stats.tx.dropped.fw_discard_reason1);
  2390. DP_TRACE_STATS(FATAL, "Firmware Discard Reason2 = %d",
  2391. pdev->stats.tx.dropped.fw_discard_reason2);
  2392. DP_TRACE_STATS(FATAL, "Firmware Discard Reason3 = %d\n",
  2393. pdev->stats.tx.dropped.fw_discard_reason3);
  2394. DP_TRACE_STATS(FATAL, "Scatter Gather:\n");
  2395. DP_TRACE_STATS(FATAL, "Packets = %d",
  2396. pdev->stats.tx_i.sg.sg_pkt.num);
  2397. DP_TRACE_STATS(FATAL, "Bytes = %d",
  2398. pdev->stats.tx_i.sg.sg_pkt.bytes);
  2399. DP_TRACE_STATS(FATAL, "Dropped By Host = %d",
  2400. pdev->stats.tx_i.sg.dropped_host);
  2401. DP_TRACE_STATS(FATAL, "Dropped By Target = %d\n",
  2402. pdev->stats.tx_i.sg.dropped_target);
  2403. DP_TRACE_STATS(FATAL, "Tso:\n");
  2404. DP_TRACE_STATS(FATAL, "Number of Segments = %d",
  2405. pdev->stats.tx_i.tso.num_seg);
  2406. DP_TRACE_STATS(FATAL, "Packets = %d",
  2407. pdev->stats.tx_i.tso.tso_pkt.num);
  2408. DP_TRACE_STATS(FATAL, "Bytes = %d",
  2409. pdev->stats.tx_i.tso.tso_pkt.bytes);
  2410. DP_TRACE_STATS(FATAL, "Dropped By Host = %d\n",
  2411. pdev->stats.tx_i.tso.dropped_host);
  2412. DP_TRACE_STATS(FATAL, "Mcast Enhancement:\n");
  2413. DP_TRACE_STATS(FATAL, "Packets = %d",
  2414. pdev->stats.tx_i.mcast_en.mcast_pkt.num);
  2415. DP_TRACE_STATS(FATAL, "Bytes = %d",
  2416. pdev->stats.tx_i.mcast_en.mcast_pkt.bytes);
  2417. DP_TRACE_STATS(FATAL, "Dropped: Map Errors = %d",
  2418. pdev->stats.tx_i.mcast_en.dropped_map_error);
  2419. DP_TRACE_STATS(FATAL, "Dropped: Self Mac = %d",
  2420. pdev->stats.tx_i.mcast_en.dropped_self_mac);
  2421. DP_TRACE_STATS(FATAL, "Dropped: Send Fail = %d",
  2422. pdev->stats.tx_i.mcast_en.dropped_send_fail);
  2423. DP_TRACE_STATS(FATAL, "Unicast sent = %d\n",
  2424. pdev->stats.tx_i.mcast_en.ucast);
  2425. DP_TRACE_STATS(FATAL, "Raw:\n");
  2426. DP_TRACE_STATS(FATAL, "Packets = %d",
  2427. pdev->stats.tx_i.raw.raw_pkt.num);
  2428. DP_TRACE_STATS(FATAL, "Bytes = %d",
  2429. pdev->stats.tx_i.raw.raw_pkt.bytes);
  2430. DP_TRACE_STATS(FATAL, "DMA map error = %d\n",
  2431. pdev->stats.tx_i.raw.dma_map_error);
  2432. DP_TRACE_STATS(FATAL, "Reinjected:\n");
  2433. DP_TRACE_STATS(FATAL, "Packets = %d",
  2434. pdev->stats.tx_i.reinject_pkts.num);
  2435. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  2436. pdev->stats.tx_i.reinject_pkts.bytes);
  2437. DP_TRACE_STATS(FATAL, "Inspected:\n");
  2438. DP_TRACE_STATS(FATAL, "Packets = %d",
  2439. pdev->stats.tx_i.inspect_pkts.num);
  2440. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  2441. pdev->stats.tx_i.inspect_pkts.bytes);
  2442. }
  2443. /**
  2444. * dp_print_pdev_rx_stats(): Print Pdev level RX stats
  2445. * @pdev: DP_PDEV Handle
  2446. *
  2447. * Return: void
  2448. */
  2449. static inline void
  2450. dp_print_pdev_rx_stats(struct dp_pdev *pdev)
  2451. {
  2452. DP_TRACE_STATS(FATAL, "WLAN Rx Stats:\n");
  2453. DP_TRACE_STATS(FATAL, "Received From HW (Per Rx Ring):\n");
  2454. DP_TRACE_STATS(FATAL, "Packets = %d %d %d %d",
  2455. pdev->stats.rx.rcvd_reo[0].num,
  2456. pdev->stats.rx.rcvd_reo[1].num,
  2457. pdev->stats.rx.rcvd_reo[2].num,
  2458. pdev->stats.rx.rcvd_reo[3].num);
  2459. DP_TRACE_STATS(FATAL, "Bytes = %d %d %d %d\n",
  2460. pdev->stats.rx.rcvd_reo[0].bytes,
  2461. pdev->stats.rx.rcvd_reo[1].bytes,
  2462. pdev->stats.rx.rcvd_reo[2].bytes,
  2463. pdev->stats.rx.rcvd_reo[3].bytes);
  2464. DP_TRACE_STATS(FATAL, "Replenished:\n");
  2465. DP_TRACE_STATS(FATAL, "Packets = %d",
  2466. pdev->stats.replenish.pkts.num);
  2467. DP_TRACE_STATS(FATAL, "Bytes = %d",
  2468. pdev->stats.replenish.pkts.bytes);
  2469. DP_TRACE_STATS(FATAL, "Buffers Added To Freelist = %d\n",
  2470. pdev->stats.buf_freelist);
  2471. DP_TRACE_STATS(FATAL, "Dropped:\n");
  2472. DP_TRACE_STATS(FATAL, "Total Packets With Msdu Not Done = %d\n",
  2473. pdev->stats.dropped.msdu_not_done);
  2474. DP_TRACE_STATS(FATAL, "Sent To Stack:\n");
  2475. DP_TRACE_STATS(FATAL, "Packets = %d",
  2476. pdev->stats.rx.to_stack.num);
  2477. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  2478. pdev->stats.rx.to_stack.bytes);
  2479. DP_TRACE_STATS(FATAL, "Multicast/Broadcast:\n");
  2480. DP_TRACE_STATS(FATAL, "Packets = %d",
  2481. pdev->stats.rx.multicast.num);
  2482. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  2483. pdev->stats.rx.multicast.bytes);
  2484. DP_TRACE_STATS(FATAL, "Errors:\n");
  2485. DP_TRACE_STATS(FATAL, "Rxdma Ring Un-inititalized = %d",
  2486. pdev->stats.replenish.rxdma_err);
  2487. DP_TRACE_STATS(FATAL, "Desc Alloc Failed: = %d",
  2488. pdev->stats.err.desc_alloc_fail);
  2489. }
  2490. /**
  2491. * dp_print_soc_tx_stats(): Print SOC level stats
  2492. * @soc DP_SOC Handle
  2493. *
  2494. * Return: void
  2495. */
  2496. static inline void
  2497. dp_print_soc_tx_stats(struct dp_soc *soc)
  2498. {
  2499. DP_TRACE_STATS(FATAL, "SOC Tx Stats:\n");
  2500. DP_TRACE_STATS(FATAL, "Tx Descriptors In Use = %d",
  2501. soc->stats.tx.desc_in_use);
  2502. DP_TRACE_STATS(FATAL, "Invalid peer:\n");
  2503. DP_TRACE_STATS(FATAL, "Packets = %d",
  2504. soc->stats.tx.tx_invalid_peer.num);
  2505. DP_TRACE_STATS(FATAL, "Bytes = %d",
  2506. soc->stats.tx.tx_invalid_peer.bytes);
  2507. DP_TRACE_STATS(FATAL, "Packets dropped due to TCL ring full = %d %d %d",
  2508. soc->stats.tx.tcl_ring_full[0],
  2509. soc->stats.tx.tcl_ring_full[1],
  2510. soc->stats.tx.tcl_ring_full[2]);
  2511. }
  2512. /**
  2513. * dp_print_soc_rx_stats: Print SOC level Rx stats
  2514. * @soc: DP_SOC Handle
  2515. *
  2516. * Return:void
  2517. */
  2518. static inline void
  2519. dp_print_soc_rx_stats(struct dp_soc *soc)
  2520. {
  2521. uint32_t i;
  2522. char reo_error[DP_REO_ERR_LENGTH];
  2523. char rxdma_error[DP_RXDMA_ERR_LENGTH];
  2524. uint8_t index = 0;
  2525. DP_TRACE_STATS(FATAL, "SOC Rx Stats:\n");
  2526. DP_TRACE_STATS(FATAL, "Errors:\n");
  2527. DP_TRACE_STATS(FATAL, "Rx Decrypt Errors = %d",
  2528. (soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_DECRYPT] +
  2529. soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_TKIP_MIC]));
  2530. DP_TRACE_STATS(FATAL, "Invalid RBM = %d",
  2531. soc->stats.rx.err.invalid_rbm);
  2532. DP_TRACE_STATS(FATAL, "Invalid Vdev = %d",
  2533. soc->stats.rx.err.invalid_vdev);
  2534. DP_TRACE_STATS(FATAL, "Invalid Pdev = %d",
  2535. soc->stats.rx.err.invalid_pdev);
  2536. DP_TRACE_STATS(FATAL, "Invalid Peer = %d",
  2537. soc->stats.rx.err.rx_invalid_peer.num);
  2538. DP_TRACE_STATS(FATAL, "HAL Ring Access Fail = %d",
  2539. soc->stats.rx.err.hal_ring_access_fail);
  2540. for (i = 0; i < MAX_RXDMA_ERRORS; i++) {
  2541. index += qdf_snprint(&rxdma_error[index],
  2542. DP_RXDMA_ERR_LENGTH - index,
  2543. " %d", soc->stats.rx.err.rxdma_error[i]);
  2544. }
  2545. DP_TRACE_STATS(FATAL, "RXDMA Error (0-31):%s",
  2546. rxdma_error);
  2547. index = 0;
  2548. for (i = 0; i < REO_ERROR_TYPE_MAX; i++) {
  2549. index += qdf_snprint(&reo_error[index],
  2550. DP_REO_ERR_LENGTH - index,
  2551. " %d", soc->stats.rx.err.reo_error[i]);
  2552. }
  2553. DP_TRACE_STATS(FATAL, "REO Error(0-14):%s",
  2554. reo_error);
  2555. }
  2556. /**
  2557. * dp_txrx_host_stats_clr(): Reinitialize the txrx stats
  2558. * @vdev: DP_VDEV handle
  2559. *
  2560. * Return:void
  2561. */
  2562. static inline void
  2563. dp_txrx_host_stats_clr(struct dp_vdev *vdev)
  2564. {
  2565. struct dp_peer *peer = NULL;
  2566. DP_STATS_CLR(vdev->pdev);
  2567. DP_STATS_CLR(vdev->pdev->soc);
  2568. DP_STATS_CLR(vdev);
  2569. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2570. if (!peer)
  2571. return;
  2572. DP_STATS_CLR(peer);
  2573. }
  2574. }
  2575. /**
  2576. * dp_print_rx_rates(): Print Rx rate stats
  2577. * @vdev: DP_VDEV handle
  2578. *
  2579. * Return:void
  2580. */
  2581. static inline void
  2582. dp_print_rx_rates(struct dp_vdev *vdev)
  2583. {
  2584. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  2585. uint8_t i, pkt_type;
  2586. uint8_t index = 0;
  2587. char rx_mcs[DOT11_MAX][DP_MCS_LENGTH];
  2588. char nss[DP_NSS_LENGTH];
  2589. DP_TRACE_STATS(FATAL, "Rx Rate Info:\n");
  2590. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  2591. index = 0;
  2592. for (i = 0; i < MAX_MCS; i++) {
  2593. index += qdf_snprint(&rx_mcs[pkt_type][index],
  2594. DP_MCS_LENGTH - index,
  2595. " %d ",
  2596. pdev->stats.rx.pkt_type[pkt_type].
  2597. mcs_count[i]);
  2598. }
  2599. }
  2600. DP_TRACE_STATS(FATAL, "11A MCS(0-7) = %s",
  2601. rx_mcs[0]);
  2602. DP_TRACE_STATS(FATAL, "11A MCS Invalid = %d",
  2603. pdev->stats.rx.pkt_type[DOT11_A].mcs_count[MAX_MCS]);
  2604. DP_TRACE_STATS(FATAL, "11B MCS(0-6) = %s",
  2605. rx_mcs[1]);
  2606. DP_TRACE_STATS(FATAL, "11B MCS Invalid = %d",
  2607. pdev->stats.rx.pkt_type[DOT11_B].mcs_count[MAX_MCS]);
  2608. DP_TRACE_STATS(FATAL, "11N MCS(0-7) = %s",
  2609. rx_mcs[2]);
  2610. DP_TRACE_STATS(FATAL, "11N MCS Invalid = %d",
  2611. pdev->stats.rx.pkt_type[DOT11_N].mcs_count[MAX_MCS]);
  2612. DP_TRACE_STATS(FATAL, "Type 11AC MCS(0-9) = %s",
  2613. rx_mcs[3]);
  2614. DP_TRACE_STATS(FATAL, "11AC MCS Invalid = %d",
  2615. pdev->stats.rx.pkt_type[DOT11_AC].mcs_count[MAX_MCS]);
  2616. DP_TRACE_STATS(FATAL, "11AX MCS(0-11) = %s",
  2617. rx_mcs[4]);
  2618. DP_TRACE_STATS(FATAL, "11AX MCS Invalid = %d",
  2619. pdev->stats.rx.pkt_type[DOT11_AX].mcs_count[MAX_MCS]);
  2620. index = 0;
  2621. for (i = 0; i < SS_COUNT; i++) {
  2622. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  2623. " %d", pdev->stats.rx.nss[i]);
  2624. }
  2625. DP_TRACE_STATS(FATAL, "NSS(0-7) = %s",
  2626. nss);
  2627. DP_TRACE_STATS(FATAL, "SGI ="
  2628. " 0.8us %d,"
  2629. " 0.4us %d,"
  2630. " 1.6us %d,"
  2631. " 3.2us %d,",
  2632. pdev->stats.rx.sgi_count[0],
  2633. pdev->stats.rx.sgi_count[1],
  2634. pdev->stats.rx.sgi_count[2],
  2635. pdev->stats.rx.sgi_count[3]);
  2636. DP_TRACE_STATS(FATAL, "BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  2637. pdev->stats.rx.bw[0], pdev->stats.rx.bw[1],
  2638. pdev->stats.rx.bw[2], pdev->stats.rx.bw[3]);
  2639. DP_TRACE_STATS(FATAL, "Reception Type ="
  2640. " SU: %d,"
  2641. " MU_MIMO:%d,"
  2642. " MU_OFDMA:%d,"
  2643. " MU_OFDMA_MIMO:%d\n",
  2644. pdev->stats.rx.reception_type[0],
  2645. pdev->stats.rx.reception_type[1],
  2646. pdev->stats.rx.reception_type[2],
  2647. pdev->stats.rx.reception_type[3]);
  2648. DP_TRACE_STATS(FATAL, "Aggregation:\n");
  2649. DP_TRACE_STATS(FATAL, "Number of Msdu's Part of Ampdus = %d",
  2650. pdev->stats.rx.ampdu_cnt);
  2651. DP_TRACE_STATS(FATAL, "Number of Msdu's With No Mpdu Level Aggregation : %d",
  2652. pdev->stats.rx.non_ampdu_cnt);
  2653. DP_TRACE_STATS(FATAL, "Number of Msdu's Part of Amsdu: %d",
  2654. pdev->stats.rx.amsdu_cnt);
  2655. DP_TRACE_STATS(FATAL, "Number of Msdu's With No Msdu Level Aggregation: %d",
  2656. pdev->stats.rx.non_amsdu_cnt);
  2657. }
  2658. /**
  2659. * dp_print_tx_rates(): Print tx rates
  2660. * @vdev: DP_VDEV handle
  2661. *
  2662. * Return:void
  2663. */
  2664. static inline void
  2665. dp_print_tx_rates(struct dp_vdev *vdev)
  2666. {
  2667. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  2668. uint8_t i, pkt_type;
  2669. char mcs[DOT11_MAX][DP_MCS_LENGTH];
  2670. uint32_t index;
  2671. DP_TRACE_STATS(FATAL, "Tx Rate Info:\n");
  2672. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  2673. index = 0;
  2674. for (i = 0; i < MAX_MCS; i++) {
  2675. index += qdf_snprint(&mcs[pkt_type][index],
  2676. DP_MCS_LENGTH - index,
  2677. " %d ",
  2678. pdev->stats.tx.pkt_type[pkt_type].
  2679. mcs_count[i]);
  2680. }
  2681. }
  2682. DP_TRACE_STATS(FATAL, "11A MCS(0-7) = %s",
  2683. mcs[0]);
  2684. DP_TRACE_STATS(FATAL, "11A MCS Invalid = %d",
  2685. pdev->stats.tx.pkt_type[DOT11_A].mcs_count[MAX_MCS]);
  2686. DP_TRACE_STATS(FATAL, "11B MCS(0-6) = %s",
  2687. mcs[1]);
  2688. DP_TRACE_STATS(FATAL, "11B MCS Invalid = %d",
  2689. pdev->stats.tx.pkt_type[DOT11_B].mcs_count[MAX_MCS]);
  2690. DP_TRACE_STATS(FATAL, "11N MCS(0-7) = %s",
  2691. mcs[2]);
  2692. DP_TRACE_STATS(FATAL, "11N MCS Invalid = %d",
  2693. pdev->stats.tx.pkt_type[DOT11_N].mcs_count[MAX_MCS]);
  2694. DP_TRACE_STATS(FATAL, "Type 11AC MCS(0-9) = %s",
  2695. mcs[3]);
  2696. DP_TRACE_STATS(FATAL, "11AC MCS Invalid = %d",
  2697. pdev->stats.tx.pkt_type[DOT11_AC].mcs_count[MAX_MCS]);
  2698. DP_TRACE_STATS(FATAL, "11AX MCS(0-11) = %s",
  2699. mcs[4]);
  2700. DP_TRACE_STATS(FATAL, "11AX MCS Invalid = %d",
  2701. pdev->stats.tx.pkt_type[DOT11_AX].mcs_count[MAX_MCS]);
  2702. DP_TRACE_STATS(FATAL, "SGI ="
  2703. " 0.8us %d"
  2704. " 0.4us %d"
  2705. " 1.6us %d"
  2706. " 3.2us %d",
  2707. pdev->stats.tx.sgi_count[0],
  2708. pdev->stats.tx.sgi_count[1],
  2709. pdev->stats.tx.sgi_count[2],
  2710. pdev->stats.tx.sgi_count[3]);
  2711. DP_TRACE_STATS(FATAL, "BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  2712. pdev->stats.tx.bw[0], pdev->stats.tx.bw[1],
  2713. pdev->stats.tx.bw[2], pdev->stats.tx.bw[3]);
  2714. DP_TRACE_STATS(FATAL, "OFDMA = %d", pdev->stats.tx.ofdma);
  2715. DP_TRACE_STATS(FATAL, "STBC = %d", pdev->stats.tx.stbc);
  2716. DP_TRACE_STATS(FATAL, "LDPC = %d", pdev->stats.tx.ldpc);
  2717. DP_TRACE_STATS(FATAL, "Retries = %d", pdev->stats.tx.retries);
  2718. DP_TRACE_STATS(FATAL, "Last ack rssi = %d\n", pdev->stats.tx.last_ack_rssi);
  2719. DP_TRACE_STATS(FATAL, "Aggregation:\n");
  2720. DP_TRACE_STATS(FATAL, "Number of Msdu's Part of Amsdu = %d",
  2721. pdev->stats.tx.amsdu_cnt);
  2722. DP_TRACE_STATS(FATAL, "Number of Msdu's With No Msdu Level Aggregation = %d",
  2723. pdev->stats.tx.non_amsdu_cnt);
  2724. }
  2725. /**
  2726. * dp_print_peer_stats():print peer stats
  2727. * @peer: DP_PEER handle
  2728. *
  2729. * return void
  2730. */
  2731. static inline void dp_print_peer_stats(struct dp_peer *peer)
  2732. {
  2733. uint8_t i, pkt_type;
  2734. char tx_mcs[DOT11_MAX][DP_MCS_LENGTH];
  2735. char rx_mcs[DOT11_MAX][DP_MCS_LENGTH];
  2736. uint32_t index;
  2737. char nss[DP_NSS_LENGTH];
  2738. DP_TRACE_STATS(FATAL, "Node Tx Stats:\n");
  2739. DP_TRACE_STATS(FATAL, "Total Packet Completions = %d",
  2740. peer->stats.tx.comp_pkt.num);
  2741. DP_TRACE_STATS(FATAL, "Total Bytes Completions = %d",
  2742. peer->stats.tx.comp_pkt.bytes);
  2743. DP_TRACE_STATS(FATAL, "Success Packets = %d",
  2744. peer->stats.tx.tx_success.num);
  2745. DP_TRACE_STATS(FATAL, "Success Bytes = %d",
  2746. peer->stats.tx.tx_success.bytes);
  2747. DP_TRACE_STATS(FATAL, "Packets Failed = %d",
  2748. peer->stats.tx.tx_failed);
  2749. DP_TRACE_STATS(FATAL, "Packets In OFDMA = %d",
  2750. peer->stats.tx.ofdma);
  2751. DP_TRACE_STATS(FATAL, "Packets In STBC = %d",
  2752. peer->stats.tx.stbc);
  2753. DP_TRACE_STATS(FATAL, "Packets In LDPC = %d",
  2754. peer->stats.tx.ldpc);
  2755. DP_TRACE_STATS(FATAL, "Packet Retries = %d",
  2756. peer->stats.tx.retries);
  2757. DP_TRACE_STATS(FATAL, "Msdu's Not Part of Ampdu = %d",
  2758. peer->stats.tx.non_amsdu_cnt);
  2759. DP_TRACE_STATS(FATAL, "Mpdu's Part of Ampdu = %d",
  2760. peer->stats.tx.amsdu_cnt);
  2761. DP_TRACE_STATS(FATAL, "Last Packet RSSI = %d",
  2762. peer->stats.tx.last_ack_rssi);
  2763. DP_TRACE_STATS(FATAL, "Dropped At FW: FW Discard = %d",
  2764. peer->stats.tx.dropped.fw_discard);
  2765. DP_TRACE_STATS(FATAL, "Dropped At FW: FW Discard Retired = %d",
  2766. peer->stats.tx.dropped.fw_discard_retired);
  2767. DP_TRACE_STATS(FATAL, "Dropped At FW: FW Discard Untransmitted = %d",
  2768. peer->stats.tx.dropped.fw_discard_untransmitted);
  2769. DP_TRACE_STATS(FATAL, "Dropped : Mpdu Age Out = %d",
  2770. peer->stats.tx.dropped.mpdu_age_out);
  2771. DP_TRACE_STATS(FATAL, "Dropped : FW Discard Reason1 = %d",
  2772. peer->stats.tx.dropped.fw_discard_reason1);
  2773. DP_TRACE_STATS(FATAL, "Dropped : FW Discard Reason2 = %d",
  2774. peer->stats.tx.dropped.fw_discard_reason2);
  2775. DP_TRACE_STATS(FATAL, "Dropped : FW Discard Reason3 = %d",
  2776. peer->stats.tx.dropped.fw_discard_reason3);
  2777. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  2778. index = 0;
  2779. for (i = 0; i < MAX_MCS; i++) {
  2780. index += qdf_snprint(&tx_mcs[pkt_type][index],
  2781. DP_MCS_LENGTH - index,
  2782. " %d ",
  2783. peer->stats.tx.pkt_type[pkt_type].
  2784. mcs_count[i]);
  2785. }
  2786. }
  2787. DP_TRACE_STATS(FATAL, "11A MCS(0-7) = %s",
  2788. tx_mcs[0]);
  2789. DP_TRACE_STATS(FATAL, "11A MCS Invalid = %d",
  2790. peer->stats.tx.pkt_type[DOT11_A].mcs_count[MAX_MCS]);
  2791. DP_TRACE_STATS(FATAL, "11B MCS(0-6) = %s",
  2792. tx_mcs[1]);
  2793. DP_TRACE_STATS(FATAL, "11B MCS Invalid = %d",
  2794. peer->stats.tx.pkt_type[DOT11_B].mcs_count[MAX_MCS]);
  2795. DP_TRACE_STATS(FATAL, "11N MCS(0-7) = %s",
  2796. tx_mcs[2]);
  2797. DP_TRACE_STATS(FATAL, "11N MCS Invalid = %d",
  2798. peer->stats.tx.pkt_type[DOT11_N].mcs_count[MAX_MCS]);
  2799. DP_TRACE_STATS(FATAL, "11AC MCS(0-9) = %s",
  2800. tx_mcs[3]);
  2801. DP_TRACE_STATS(FATAL, "11AC MCS Invalid = %d",
  2802. peer->stats.tx.pkt_type[DOT11_AC].mcs_count[MAX_MCS]);
  2803. DP_TRACE_STATS(FATAL, "11AX MCS(0-11) = %s",
  2804. tx_mcs[4]);
  2805. DP_TRACE_STATS(FATAL, "11AX MCS Invalid = %d",
  2806. peer->stats.tx.pkt_type[DOT11_AX].mcs_count[MAX_MCS]);
  2807. DP_TRACE_STATS(FATAL, "SGI = "
  2808. " 0.8us %d"
  2809. " 0.4us %d"
  2810. " 1.6us %d"
  2811. " 3.2us %d",
  2812. peer->stats.tx.sgi_count[0],
  2813. peer->stats.tx.sgi_count[1],
  2814. peer->stats.tx.sgi_count[2],
  2815. peer->stats.tx.sgi_count[3]);
  2816. DP_TRACE_STATS(FATAL, "BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d\n",
  2817. peer->stats.tx.bw[0], peer->stats.tx.bw[1],
  2818. peer->stats.tx.bw[2], peer->stats.tx.bw[3]);
  2819. DP_TRACE_STATS(FATAL, "Aggregation:\n");
  2820. DP_TRACE_STATS(FATAL, "Number of Msdu's Part of Amsdu = %d",
  2821. peer->stats.tx.amsdu_cnt);
  2822. DP_TRACE_STATS(FATAL, "Number of Msdu's With No Msdu Level Aggregation = %d\n",
  2823. peer->stats.tx.non_amsdu_cnt);
  2824. DP_TRACE_STATS(FATAL, "Node Rx Stats:\n");
  2825. DP_TRACE_STATS(FATAL, "Packets Sent To Stack = %d",
  2826. peer->stats.rx.to_stack.num);
  2827. DP_TRACE_STATS(FATAL, "Bytes Sent To Stack = %d",
  2828. peer->stats.rx.to_stack.bytes);
  2829. for (i = 0; i < CDP_MAX_RX_RINGS; i++) {
  2830. DP_TRACE_STATS(FATAL, "Packets Received = %d",
  2831. peer->stats.rx.rcvd_reo[i].num);
  2832. DP_TRACE_STATS(FATAL, "Bytes Received = %d",
  2833. peer->stats.rx.rcvd_reo[i].bytes);
  2834. }
  2835. DP_TRACE_STATS(FATAL, "Multicast Packets Received = %d",
  2836. peer->stats.rx.multicast.num);
  2837. DP_TRACE_STATS(FATAL, "Multicast Bytes Received = %d",
  2838. peer->stats.rx.multicast.bytes);
  2839. DP_TRACE_STATS(FATAL, "WDS Packets Received = %d",
  2840. peer->stats.rx.wds.num);
  2841. DP_TRACE_STATS(FATAL, "WDS Bytes Received = %d",
  2842. peer->stats.rx.wds.bytes);
  2843. DP_TRACE_STATS(FATAL, "Intra BSS Packets Received = %d",
  2844. peer->stats.rx.intra_bss.pkts.num);
  2845. DP_TRACE_STATS(FATAL, "Intra BSS Bytes Received = %d",
  2846. peer->stats.rx.intra_bss.pkts.bytes);
  2847. DP_TRACE_STATS(FATAL, "Raw Packets Received = %d",
  2848. peer->stats.rx.raw.num);
  2849. DP_TRACE_STATS(FATAL, "Raw Bytes Received = %d",
  2850. peer->stats.rx.raw.bytes);
  2851. DP_TRACE_STATS(FATAL, "Errors: MIC Errors = %d",
  2852. peer->stats.rx.err.mic_err);
  2853. DP_TRACE_STATS(FATAL, "Erros: Decryption Errors = %d",
  2854. peer->stats.rx.err.decrypt_err);
  2855. DP_TRACE_STATS(FATAL, "Msdu's Received As Part of Ampdu = %d",
  2856. peer->stats.rx.non_ampdu_cnt);
  2857. DP_TRACE_STATS(FATAL, "Msdu's Recived As Ampdu = %d",
  2858. peer->stats.rx.ampdu_cnt);
  2859. DP_TRACE_STATS(FATAL, "Msdu's Received Not Part of Amsdu's = %d",
  2860. peer->stats.rx.non_amsdu_cnt);
  2861. DP_TRACE_STATS(FATAL, "MSDUs Received As Part of Amsdu = %d",
  2862. peer->stats.rx.amsdu_cnt);
  2863. DP_TRACE_STATS(FATAL, "SGI ="
  2864. " 0.8us %d"
  2865. " 0.4us %d"
  2866. " 1.6us %d"
  2867. " 3.2us %d",
  2868. peer->stats.rx.sgi_count[0],
  2869. peer->stats.rx.sgi_count[1],
  2870. peer->stats.rx.sgi_count[2],
  2871. peer->stats.rx.sgi_count[3]);
  2872. DP_TRACE_STATS(FATAL, "BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d",
  2873. peer->stats.rx.bw[0], peer->stats.rx.bw[1],
  2874. peer->stats.rx.bw[2], peer->stats.rx.bw[3]);
  2875. DP_TRACE_STATS(FATAL, "Reception Type ="
  2876. " SU %d,"
  2877. " MU_MIMO %d,"
  2878. " MU_OFDMA %d,"
  2879. " MU_OFDMA_MIMO %d",
  2880. peer->stats.rx.reception_type[0],
  2881. peer->stats.rx.reception_type[1],
  2882. peer->stats.rx.reception_type[2],
  2883. peer->stats.rx.reception_type[3]);
  2884. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  2885. index = 0;
  2886. for (i = 0; i < MAX_MCS; i++) {
  2887. index += qdf_snprint(&rx_mcs[pkt_type][index],
  2888. DP_MCS_LENGTH - index,
  2889. " %d ",
  2890. peer->stats.rx.pkt_type[pkt_type].
  2891. mcs_count[i]);
  2892. }
  2893. }
  2894. DP_TRACE_STATS(FATAL, "11A MCS(0-7) = %s",
  2895. rx_mcs[0]);
  2896. DP_TRACE_STATS(FATAL, "11A MCS Invalid = %d",
  2897. peer->stats.rx.pkt_type[DOT11_A].mcs_count[MAX_MCS]);
  2898. DP_TRACE_STATS(FATAL, "11B MCS(0-6) = %s",
  2899. rx_mcs[1]);
  2900. DP_TRACE_STATS(FATAL, "11B MCS Invalid = %d",
  2901. peer->stats.rx.pkt_type[DOT11_B].mcs_count[MAX_MCS]);
  2902. DP_TRACE_STATS(FATAL, "11N MCS(0-7) = %s",
  2903. rx_mcs[2]);
  2904. DP_TRACE_STATS(FATAL, "11N MCS Invalid = %d",
  2905. peer->stats.rx.pkt_type[DOT11_N].mcs_count[MAX_MCS]);
  2906. DP_TRACE_STATS(FATAL, "11AC MCS(0-9) = %s",
  2907. rx_mcs[3]);
  2908. DP_TRACE_STATS(FATAL, "11AC MCS Invalid = %d",
  2909. peer->stats.rx.pkt_type[DOT11_AC].mcs_count[MAX_MCS]);
  2910. DP_TRACE_STATS(FATAL, "11AX MCS(0-11) = %s",
  2911. rx_mcs[4]);
  2912. DP_TRACE_STATS(FATAL, "11AX MCS Invalid = %d",
  2913. peer->stats.rx.pkt_type[DOT11_AX].mcs_count[MAX_MCS]);
  2914. index = 0;
  2915. for (i = 0; i < SS_COUNT; i++) {
  2916. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  2917. " %d", peer->stats.rx.nss[i]);
  2918. }
  2919. DP_TRACE_STATS(FATAL, "NSS(0-7) = %s\n",
  2920. nss);
  2921. DP_TRACE_STATS(FATAL, "Aggregation:\n");
  2922. DP_TRACE_STATS(FATAL, "Number of Msdu's Part of Ampdu = %d",
  2923. peer->stats.rx.ampdu_cnt);
  2924. DP_TRACE_STATS(FATAL, "Number of Msdu's With No Mpdu Level Aggregation = %d",
  2925. peer->stats.rx.non_ampdu_cnt);
  2926. DP_TRACE_STATS(FATAL, "Number of Msdu's Part of Amsdu = %d",
  2927. peer->stats.rx.amsdu_cnt);
  2928. DP_TRACE_STATS(FATAL, "Number of Msdu's With No Msdu Level Aggregation = %d",
  2929. peer->stats.rx.non_amsdu_cnt);
  2930. }
  2931. /**
  2932. * dp_print_host_stats()- Function to print the stats aggregated at host
  2933. * @vdev_handle: DP_VDEV handle
  2934. * @type: host stats type
  2935. *
  2936. * Available Stat types
  2937. * TXRX_CLEAR_STATS : Clear the stats
  2938. * TXRX_RX_RATE_STATS: Print Rx Rate Info
  2939. * TXRX_TX_RATE_STATS: Print Tx Rate Info
  2940. * TXRX_TX_HOST_STATS: Print Tx Stats
  2941. * TXRX_RX_HOST_STATS: Print Rx Stats
  2942. *
  2943. * Return: 0 on success, print error message in case of failure
  2944. */
  2945. static int
  2946. dp_print_host_stats(struct cdp_vdev *vdev_handle, enum cdp_host_txrx_stats type)
  2947. {
  2948. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2949. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  2950. dp_aggregate_pdev_stats(pdev);
  2951. switch (type) {
  2952. case TXRX_CLEAR_STATS:
  2953. dp_txrx_host_stats_clr(vdev);
  2954. break;
  2955. case TXRX_RX_RATE_STATS:
  2956. dp_print_rx_rates(vdev);
  2957. break;
  2958. case TXRX_TX_RATE_STATS:
  2959. dp_print_tx_rates(vdev);
  2960. break;
  2961. case TXRX_TX_HOST_STATS:
  2962. dp_print_pdev_tx_stats(pdev);
  2963. dp_print_soc_tx_stats(pdev->soc);
  2964. break;
  2965. case TXRX_RX_HOST_STATS:
  2966. dp_print_pdev_rx_stats(pdev);
  2967. dp_print_soc_rx_stats(pdev->soc);
  2968. break;
  2969. default:
  2970. DP_TRACE(FATAL, "Wrong Input For TxRx Host Stats");
  2971. break;
  2972. }
  2973. return 0;
  2974. }
  2975. /*
  2976. * dp_get_host_peer_stats()- function to print peer stats
  2977. * @pdev_handle: DP_PDEV handle
  2978. * @mac_addr: mac address of the peer
  2979. *
  2980. * Return: void
  2981. */
  2982. static void
  2983. dp_get_host_peer_stats(struct cdp_pdev *pdev_handle, char *mac_addr)
  2984. {
  2985. struct dp_peer *peer;
  2986. uint8_t local_id;
  2987. peer = (struct dp_peer *)dp_find_peer_by_addr(pdev_handle, mac_addr,
  2988. &local_id);
  2989. if (!peer) {
  2990. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2991. "%s: Invalid peer\n", __func__);
  2992. return;
  2993. }
  2994. dp_print_peer_stats(peer);
  2995. dp_peer_rxtid_stats(peer);
  2996. return;
  2997. }
  2998. /*
  2999. * dp_enable_enhanced_stats()- API to enable enhanced statistcs
  3000. * @pdev_handle: DP_PDEV handle
  3001. *
  3002. * Return: void
  3003. */
  3004. static void
  3005. dp_enable_enhanced_stats(struct cdp_pdev *pdev_handle)
  3006. {
  3007. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3008. pdev->enhanced_stats_en = 1;
  3009. }
  3010. /*
  3011. * dp_disable_enhanced_stats()- API to disable enhanced statistcs
  3012. * @pdev_handle: DP_PDEV handle
  3013. *
  3014. * Return: void
  3015. */
  3016. static void
  3017. dp_disable_enhanced_stats(struct cdp_pdev *pdev_handle)
  3018. {
  3019. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3020. pdev->enhanced_stats_en = 0;
  3021. }
  3022. /*
  3023. * dp_get_fw_peer_stats()- function to print peer stats
  3024. * @pdev_handle: DP_PDEV handle
  3025. * @mac_addr: mac address of the peer
  3026. * @cap: Type of htt stats requested
  3027. *
  3028. * Currently Supporting only MAC ID based requests Only
  3029. * 1: HTT_PEER_STATS_REQ_MODE_NO_QUERY
  3030. * 2: HTT_PEER_STATS_REQ_MODE_QUERY_TQM
  3031. * 3: HTT_PEER_STATS_REQ_MODE_FLUSH_TQM
  3032. *
  3033. * Return: void
  3034. */
  3035. static void
  3036. dp_get_fw_peer_stats(struct cdp_pdev *pdev_handle, uint8_t *mac_addr,
  3037. uint32_t cap)
  3038. {
  3039. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3040. uint32_t config_param0 = 0;
  3041. uint32_t config_param1 = 0;
  3042. uint32_t config_param2 = 0;
  3043. uint32_t config_param3 = 0;
  3044. HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(config_param0, 1);
  3045. config_param0 |= (1 << (cap + 1));
  3046. config_param1 = 0x8f;
  3047. config_param2 |= (mac_addr[0] & 0x000000ff);
  3048. config_param2 |= ((mac_addr[1] << 8) & 0x0000ff00);
  3049. config_param2 |= ((mac_addr[2] << 16) & 0x00ff0000);
  3050. config_param2 |= ((mac_addr[3] << 24) & 0xff000000);
  3051. config_param3 |= (mac_addr[4] & 0x000000ff);
  3052. config_param3 |= ((mac_addr[5] << 8) & 0x0000ff00);
  3053. dp_h2t_ext_stats_msg_send(pdev, HTT_DBG_EXT_STATS_PEER_INFO,
  3054. config_param0, config_param1, config_param2,
  3055. config_param3);
  3056. }
  3057. /*
  3058. * dp_set_vdev_param: function to set parameters in vdev
  3059. * @param: parameter type to be set
  3060. * @val: value of parameter to be set
  3061. *
  3062. * return: void
  3063. */
  3064. static void dp_set_vdev_param(struct cdp_vdev *vdev_handle,
  3065. enum cdp_vdev_param_type param, uint32_t val)
  3066. {
  3067. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3068. switch (param) {
  3069. case CDP_ENABLE_WDS:
  3070. vdev->wds_enabled = val;
  3071. break;
  3072. case CDP_ENABLE_NAWDS:
  3073. vdev->nawds_enabled = val;
  3074. break;
  3075. case CDP_ENABLE_MCAST_EN:
  3076. vdev->mcast_enhancement_en = val;
  3077. break;
  3078. case CDP_ENABLE_PROXYSTA:
  3079. vdev->proxysta_vdev = val;
  3080. break;
  3081. case CDP_UPDATE_TDLS_FLAGS:
  3082. vdev->tdls_link_connected = val;
  3083. break;
  3084. default:
  3085. break;
  3086. }
  3087. dp_tx_vdev_update_search_flags(vdev);
  3088. }
  3089. /**
  3090. * dp_peer_set_nawds: set nawds bit in peer
  3091. * @peer_handle: pointer to peer
  3092. * @value: enable/disable nawds
  3093. *
  3094. * return: void
  3095. */
  3096. static void dp_peer_set_nawds(void *peer_handle, uint8_t value)
  3097. {
  3098. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  3099. peer->nawds_enabled = value;
  3100. }
  3101. /*
  3102. * dp_set_vdev_dscp_tid_map_wifi3(): Update Map ID selected for particular vdev
  3103. * @vdev_handle: DP_VDEV handle
  3104. * @map_id:ID of map that needs to be updated
  3105. *
  3106. * Return: void
  3107. */
  3108. static void dp_set_vdev_dscp_tid_map_wifi3(struct cdp_vdev *vdev_handle,
  3109. uint8_t map_id)
  3110. {
  3111. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3112. vdev->dscp_tid_map_id = map_id;
  3113. return;
  3114. }
  3115. /**
  3116. * dp_set_pdev_dscp_tid_map_wifi3(): update dscp tid map in pdev
  3117. * @pdev: DP_PDEV handle
  3118. * @map_id: ID of map that needs to be updated
  3119. * @tos: index value in map
  3120. * @tid: tid value passed by the user
  3121. *
  3122. * Return: void
  3123. */
  3124. static void dp_set_pdev_dscp_tid_map_wifi3(struct cdp_pdev *pdev_handle,
  3125. uint8_t map_id, uint8_t tos, uint8_t tid)
  3126. {
  3127. uint8_t dscp;
  3128. struct dp_pdev *pdev = (struct dp_pdev *) pdev_handle;
  3129. dscp = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  3130. pdev->dscp_tid_map[map_id][dscp] = tid;
  3131. hal_tx_update_dscp_tid(pdev->soc->hal_soc, tid,
  3132. map_id, dscp);
  3133. return;
  3134. }
  3135. /**
  3136. * dp_fw_stats_process(): Process TxRX FW stats request
  3137. * @vdev_handle: DP VDEV handle
  3138. * @val: value passed by user
  3139. *
  3140. * return: int
  3141. */
  3142. static int dp_fw_stats_process(struct cdp_vdev *vdev_handle, uint32_t val)
  3143. {
  3144. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3145. struct dp_pdev *pdev = NULL;
  3146. if (!vdev) {
  3147. DP_TRACE(NONE, "VDEV not found");
  3148. return 1;
  3149. }
  3150. pdev = vdev->pdev;
  3151. return dp_h2t_ext_stats_msg_send(pdev, val, 0, 0, 0, 0);
  3152. }
  3153. /*
  3154. * dp_txrx_stats() - function to map to firmware and host stats
  3155. * @vdev: virtual handle
  3156. * @stats: type of statistics requested
  3157. *
  3158. * Return: integer
  3159. */
  3160. static int dp_txrx_stats(struct cdp_vdev *vdev, enum cdp_stats stats)
  3161. {
  3162. int host_stats;
  3163. int fw_stats;
  3164. if (stats >= CDP_TXRX_MAX_STATS)
  3165. return 0;
  3166. /*
  3167. * DP_CURR_FW_STATS_AVAIL: no of FW stats currently available
  3168. * has to be updated if new FW HTT stats added
  3169. */
  3170. if (stats > CDP_TXRX_STATS_HTT_MAX)
  3171. stats = stats + DP_CURR_FW_STATS_AVAIL - DP_HTT_DBG_EXT_STATS_MAX;
  3172. fw_stats = dp_stats_mapping_table[stats][STATS_FW];
  3173. host_stats = dp_stats_mapping_table[stats][STATS_HOST];
  3174. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3175. "stats: %u fw_stats_type: %d host_stats_type: %d",
  3176. stats, fw_stats, host_stats);
  3177. if (fw_stats != TXRX_FW_STATS_INVALID)
  3178. return dp_fw_stats_process(vdev, fw_stats);
  3179. if ((host_stats != TXRX_HOST_STATS_INVALID) &&
  3180. (host_stats <= TXRX_HOST_STATS_MAX))
  3181. return dp_print_host_stats(vdev, host_stats);
  3182. else
  3183. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3184. "Wrong Input for TxRx Stats");
  3185. return 0;
  3186. }
  3187. /*
  3188. * dp_print_per_ring_stats(): Packet count per ring
  3189. * @soc - soc handle
  3190. */
  3191. static void dp_print_per_ring_stats(struct dp_soc *soc)
  3192. {
  3193. uint8_t core, ring;
  3194. uint64_t total_packets;
  3195. DP_TRACE(FATAL, "Reo packets per ring:");
  3196. for (ring = 0; ring < MAX_REO_DEST_RINGS; ring++) {
  3197. total_packets = 0;
  3198. DP_TRACE(FATAL, "Packets on ring %u:", ring);
  3199. for (core = 0; core < NR_CPUS; core++) {
  3200. DP_TRACE(FATAL, "Packets arriving on core %u: %llu",
  3201. core, soc->stats.rx.ring_packets[core][ring]);
  3202. total_packets += soc->stats.rx.ring_packets[core][ring];
  3203. }
  3204. DP_TRACE(FATAL, "Total packets on ring %u: %llu",
  3205. ring, total_packets);
  3206. }
  3207. }
  3208. /*
  3209. * dp_txrx_path_stats() - Function to display dump stats
  3210. * @soc - soc handle
  3211. *
  3212. * return: none
  3213. */
  3214. static void dp_txrx_path_stats(struct dp_soc *soc)
  3215. {
  3216. uint8_t error_code;
  3217. uint8_t loop_pdev;
  3218. struct dp_pdev *pdev;
  3219. uint8_t i;
  3220. for (loop_pdev = 0; loop_pdev < soc->pdev_count; loop_pdev++) {
  3221. pdev = soc->pdev_list[loop_pdev];
  3222. dp_aggregate_pdev_stats(pdev);
  3223. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3224. "Tx path Statistics:");
  3225. DP_TRACE(FATAL, "from stack: %u msdus (%u bytes)",
  3226. pdev->stats.tx_i.rcvd.num,
  3227. pdev->stats.tx_i.rcvd.bytes);
  3228. DP_TRACE(FATAL, "processed from host: %u msdus (%u bytes)",
  3229. pdev->stats.tx_i.processed.num,
  3230. pdev->stats.tx_i.processed.bytes);
  3231. DP_TRACE(FATAL, "successfully transmitted: %u msdus (%u bytes)",
  3232. pdev->stats.tx.tx_success.num,
  3233. pdev->stats.tx.tx_success.bytes);
  3234. DP_TRACE(FATAL, "Dropped in host:");
  3235. DP_TRACE(FATAL, "Total packets dropped: %u,",
  3236. pdev->stats.tx_i.dropped.dropped_pkt.num);
  3237. DP_TRACE(FATAL, "Descriptor not available: %u",
  3238. pdev->stats.tx_i.dropped.desc_na);
  3239. DP_TRACE(FATAL, "Ring full: %u",
  3240. pdev->stats.tx_i.dropped.ring_full);
  3241. DP_TRACE(FATAL, "Enqueue fail: %u",
  3242. pdev->stats.tx_i.dropped.enqueue_fail);
  3243. DP_TRACE(FATAL, "DMA Error: %u",
  3244. pdev->stats.tx_i.dropped.dma_error);
  3245. DP_TRACE(FATAL, "Dropped in hardware:");
  3246. DP_TRACE(FATAL, "total packets dropped: %u",
  3247. pdev->stats.tx.tx_failed);
  3248. DP_TRACE(FATAL, "mpdu age out: %u",
  3249. pdev->stats.tx.dropped.mpdu_age_out);
  3250. DP_TRACE(FATAL, "firmware discard reason1: %u",
  3251. pdev->stats.tx.dropped.fw_discard_reason1);
  3252. DP_TRACE(FATAL, "firmware discard reason2: %u",
  3253. pdev->stats.tx.dropped.fw_discard_reason2);
  3254. DP_TRACE(FATAL, "firmware discard reason3: %u",
  3255. pdev->stats.tx.dropped.fw_discard_reason3);
  3256. DP_TRACE(FATAL, "peer_invalid: %u",
  3257. pdev->soc->stats.tx.tx_invalid_peer.num);
  3258. DP_TRACE(FATAL, "Tx packets sent per interrupt:");
  3259. DP_TRACE(FATAL, "Single Packet: %u",
  3260. pdev->stats.tx_comp_histogram.pkts_1);
  3261. DP_TRACE(FATAL, "2-20 Packets: %u",
  3262. pdev->stats.tx_comp_histogram.pkts_2_20);
  3263. DP_TRACE(FATAL, "21-40 Packets: %u",
  3264. pdev->stats.tx_comp_histogram.pkts_21_40);
  3265. DP_TRACE(FATAL, "41-60 Packets: %u",
  3266. pdev->stats.tx_comp_histogram.pkts_41_60);
  3267. DP_TRACE(FATAL, "61-80 Packets: %u",
  3268. pdev->stats.tx_comp_histogram.pkts_61_80);
  3269. DP_TRACE(FATAL, "81-100 Packets: %u",
  3270. pdev->stats.tx_comp_histogram.pkts_81_100);
  3271. DP_TRACE(FATAL, "101-200 Packets: %u",
  3272. pdev->stats.tx_comp_histogram.pkts_101_200);
  3273. DP_TRACE(FATAL, " 201+ Packets: %u",
  3274. pdev->stats.tx_comp_histogram.pkts_201_plus);
  3275. DP_TRACE(FATAL, "Rx path statistics");
  3276. DP_TRACE(FATAL, "delivered %u msdus ( %u bytes),",
  3277. pdev->stats.rx.to_stack.num,
  3278. pdev->stats.rx.to_stack.bytes);
  3279. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  3280. DP_TRACE(FATAL, "received on reo[%d] %u msdus ( %u bytes),",
  3281. i, pdev->stats.rx.rcvd_reo[i].num,
  3282. pdev->stats.rx.rcvd_reo[i].bytes);
  3283. DP_TRACE(FATAL, "intra-bss packets %u msdus ( %u bytes),",
  3284. pdev->stats.rx.intra_bss.pkts.num,
  3285. pdev->stats.rx.intra_bss.pkts.bytes);
  3286. DP_TRACE(FATAL, "raw packets %u msdus ( %u bytes),",
  3287. pdev->stats.rx.raw.num,
  3288. pdev->stats.rx.raw.bytes);
  3289. DP_TRACE(FATAL, "dropped: error %u msdus",
  3290. pdev->stats.rx.err.mic_err);
  3291. DP_TRACE(FATAL, "peer invalid %u",
  3292. pdev->soc->stats.rx.err.rx_invalid_peer.num);
  3293. DP_TRACE(FATAL, "Reo Statistics");
  3294. DP_TRACE(FATAL, "rbm error: %u msdus",
  3295. pdev->soc->stats.rx.err.invalid_rbm);
  3296. DP_TRACE(FATAL, "hal ring access fail: %u msdus",
  3297. pdev->soc->stats.rx.err.hal_ring_access_fail);
  3298. DP_TRACE(FATAL, "Reo errors");
  3299. for (error_code = 0; error_code < REO_ERROR_TYPE_MAX;
  3300. error_code++) {
  3301. DP_TRACE(FATAL, "Reo error number (%u): %u msdus",
  3302. error_code,
  3303. pdev->soc->stats.rx.err.reo_error[error_code]);
  3304. }
  3305. for (error_code = 0; error_code < MAX_RXDMA_ERRORS;
  3306. error_code++) {
  3307. DP_TRACE(FATAL, "Rxdma error number (%u): %u msdus",
  3308. error_code,
  3309. pdev->soc->stats.rx.err
  3310. .rxdma_error[error_code]);
  3311. }
  3312. DP_TRACE(FATAL, "Rx packets reaped per interrupt:");
  3313. DP_TRACE(FATAL, "Single Packet: %u",
  3314. pdev->stats.rx_ind_histogram.pkts_1);
  3315. DP_TRACE(FATAL, "2-20 Packets: %u",
  3316. pdev->stats.rx_ind_histogram.pkts_2_20);
  3317. DP_TRACE(FATAL, "21-40 Packets: %u",
  3318. pdev->stats.rx_ind_histogram.pkts_21_40);
  3319. DP_TRACE(FATAL, "41-60 Packets: %u",
  3320. pdev->stats.rx_ind_histogram.pkts_41_60);
  3321. DP_TRACE(FATAL, "61-80 Packets: %u",
  3322. pdev->stats.rx_ind_histogram.pkts_61_80);
  3323. DP_TRACE(FATAL, "81-100 Packets: %u",
  3324. pdev->stats.rx_ind_histogram.pkts_81_100);
  3325. DP_TRACE(FATAL, "101-200 Packets: %u",
  3326. pdev->stats.rx_ind_histogram.pkts_101_200);
  3327. DP_TRACE(FATAL, " 201+ Packets: %u",
  3328. pdev->stats.rx_ind_histogram.pkts_201_plus);
  3329. }
  3330. }
  3331. /*
  3332. * dp_txrx_dump_stats() - Dump statistics
  3333. * @value - Statistics option
  3334. */
  3335. static QDF_STATUS dp_txrx_dump_stats(void *psoc, uint16_t value)
  3336. {
  3337. struct dp_soc *soc =
  3338. (struct dp_soc *)psoc;
  3339. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3340. if (!soc) {
  3341. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3342. "%s: soc is NULL", __func__);
  3343. return QDF_STATUS_E_INVAL;
  3344. }
  3345. switch (value) {
  3346. case CDP_TXRX_PATH_STATS:
  3347. dp_txrx_path_stats(soc);
  3348. break;
  3349. case CDP_RX_RING_STATS:
  3350. dp_print_per_ring_stats(soc);
  3351. break;
  3352. case CDP_TXRX_TSO_STATS:
  3353. /* TODO: NOT IMPLEMENTED */
  3354. break;
  3355. case CDP_DUMP_TX_FLOW_POOL_INFO:
  3356. /* TODO: NOT IMPLEMENTED */
  3357. break;
  3358. case CDP_TXRX_DESC_STATS:
  3359. /* TODO: NOT IMPLEMENTED */
  3360. break;
  3361. default:
  3362. status = QDF_STATUS_E_INVAL;
  3363. break;
  3364. }
  3365. return status;
  3366. }
  3367. static struct cdp_wds_ops dp_ops_wds = {
  3368. .vdev_set_wds = dp_vdev_set_wds,
  3369. };
  3370. static struct cdp_cmn_ops dp_ops_cmn = {
  3371. .txrx_soc_attach_target = dp_soc_attach_target_wifi3,
  3372. .txrx_vdev_attach = dp_vdev_attach_wifi3,
  3373. .txrx_vdev_detach = dp_vdev_detach_wifi3,
  3374. .txrx_pdev_attach = dp_pdev_attach_wifi3,
  3375. .txrx_pdev_detach = dp_pdev_detach_wifi3,
  3376. .txrx_peer_create = dp_peer_create_wifi3,
  3377. .txrx_peer_setup = dp_peer_setup_wifi3,
  3378. .txrx_peer_teardown = NULL,
  3379. .txrx_peer_delete = dp_peer_delete_wifi3,
  3380. .txrx_vdev_register = dp_vdev_register_wifi3,
  3381. .txrx_soc_detach = dp_soc_detach_wifi3,
  3382. .txrx_get_vdev_mac_addr = dp_get_vdev_mac_addr_wifi3,
  3383. .txrx_get_vdev_from_vdev_id = dp_get_vdev_from_vdev_id_wifi3,
  3384. .txrx_get_ctrl_pdev_from_vdev = dp_get_ctrl_pdev_from_vdev_wifi3,
  3385. .addba_requestprocess = dp_addba_requestprocess_wifi3,
  3386. .addba_responsesetup = dp_addba_responsesetup_wifi3,
  3387. .delba_process = dp_delba_process_wifi3,
  3388. .get_peer_mac_addr_frm_id = dp_get_peer_mac_addr_frm_id,
  3389. .flush_cache_rx_queue = NULL,
  3390. /* TODO: get API's for dscp-tid need to be added*/
  3391. .set_vdev_dscp_tid_map = dp_set_vdev_dscp_tid_map_wifi3,
  3392. .set_pdev_dscp_tid_map = dp_set_pdev_dscp_tid_map_wifi3,
  3393. .txrx_stats = dp_txrx_stats,
  3394. .txrx_set_monitor_mode = dp_vdev_set_monitor_mode,
  3395. .display_stats = dp_txrx_dump_stats,
  3396. .txrx_soc_set_nss_cfg = dp_soc_set_nss_cfg_wifi3,
  3397. .txrx_soc_get_nss_cfg = dp_soc_get_nss_cfg_wifi3,
  3398. .txrx_intr_attach = dp_soc_interrupt_attach,
  3399. .txrx_intr_detach = dp_soc_interrupt_detach,
  3400. .set_pn_check = dp_set_pn_check_wifi3,
  3401. /* TODO: Add other functions */
  3402. };
  3403. static struct cdp_ctrl_ops dp_ops_ctrl = {
  3404. .txrx_peer_authorize = dp_peer_authorize,
  3405. .txrx_set_vdev_rx_decap_type = dp_set_vdev_rx_decap_type,
  3406. .txrx_set_tx_encap_type = dp_set_vdev_tx_encap_type,
  3407. #ifdef MESH_MODE_SUPPORT
  3408. .txrx_set_mesh_mode = dp_peer_set_mesh_mode,
  3409. .txrx_set_mesh_rx_filter = dp_peer_set_mesh_rx_filter,
  3410. #endif
  3411. .txrx_set_vdev_param = dp_set_vdev_param,
  3412. .txrx_peer_set_nawds = dp_peer_set_nawds,
  3413. .txrx_set_pdev_reo_dest = dp_set_pdev_reo_dest,
  3414. .txrx_get_pdev_reo_dest = dp_get_pdev_reo_dest,
  3415. .txrx_set_filter_neighbour_peers = dp_set_filter_neighbour_peers,
  3416. .txrx_update_filter_neighbour_peers =
  3417. dp_update_filter_neighbour_peers,
  3418. /* TODO: Add other functions */
  3419. };
  3420. static struct cdp_me_ops dp_ops_me = {
  3421. #ifdef ATH_SUPPORT_IQUE
  3422. .tx_me_alloc_descriptor = dp_tx_me_alloc_descriptor,
  3423. .tx_me_free_descriptor = dp_tx_me_free_descriptor,
  3424. .tx_me_convert_ucast = dp_tx_me_send_convert_ucast,
  3425. #endif
  3426. };
  3427. static struct cdp_mon_ops dp_ops_mon = {
  3428. .txrx_monitor_set_filter_ucast_data = NULL,
  3429. .txrx_monitor_set_filter_mcast_data = NULL,
  3430. .txrx_monitor_set_filter_non_data = NULL,
  3431. .txrx_monitor_get_filter_ucast_data = NULL,
  3432. .txrx_monitor_get_filter_mcast_data = NULL,
  3433. .txrx_monitor_get_filter_non_data = NULL,
  3434. .txrx_reset_monitor_mode = NULL,
  3435. };
  3436. static struct cdp_host_stats_ops dp_ops_host_stats = {
  3437. .txrx_per_peer_stats = dp_get_host_peer_stats,
  3438. .get_fw_peer_stats = dp_get_fw_peer_stats,
  3439. .txrx_enable_enhanced_stats = dp_enable_enhanced_stats,
  3440. .txrx_disable_enhanced_stats = dp_disable_enhanced_stats,
  3441. /* TODO */
  3442. };
  3443. static struct cdp_raw_ops dp_ops_raw = {
  3444. /* TODO */
  3445. };
  3446. #ifdef CONFIG_WIN
  3447. static struct cdp_pflow_ops dp_ops_pflow = {
  3448. /* TODO */
  3449. };
  3450. #endif /* CONFIG_WIN */
  3451. #ifdef DP_INTR_POLL_BASED
  3452. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  3453. {
  3454. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  3455. struct dp_soc *soc = pdev->soc;
  3456. qdf_timer_stop(&soc->int_timer);
  3457. return QDF_STATUS_SUCCESS;
  3458. }
  3459. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  3460. {
  3461. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  3462. struct dp_soc *soc = pdev->soc;
  3463. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  3464. return QDF_STATUS_SUCCESS;
  3465. }
  3466. #else
  3467. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  3468. {
  3469. return QDF_STATUS_SUCCESS;
  3470. }
  3471. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  3472. {
  3473. return QDF_STATUS_SUCCESS;
  3474. }
  3475. #endif /* DP_INTR_POLL_BASED */
  3476. #ifndef CONFIG_WIN
  3477. static struct cdp_misc_ops dp_ops_misc = {
  3478. .get_opmode = dp_get_opmode,
  3479. #ifdef FEATURE_RUNTIME_PM
  3480. .runtime_suspend = dp_bus_suspend,
  3481. .runtime_resume = dp_bus_resume,
  3482. #endif
  3483. };
  3484. static struct cdp_flowctl_ops dp_ops_flowctl = {
  3485. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  3486. };
  3487. static struct cdp_lflowctl_ops dp_ops_l_flowctl = {
  3488. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  3489. };
  3490. static struct cdp_ipa_ops dp_ops_ipa = {
  3491. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  3492. };
  3493. static struct cdp_bus_ops dp_ops_bus = {
  3494. .bus_suspend = dp_bus_suspend,
  3495. .bus_resume = dp_bus_resume
  3496. };
  3497. static struct cdp_ocb_ops dp_ops_ocb = {
  3498. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  3499. };
  3500. static struct cdp_throttle_ops dp_ops_throttle = {
  3501. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  3502. };
  3503. static struct cdp_mob_stats_ops dp_ops_mob_stats = {
  3504. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  3505. };
  3506. static struct cdp_cfg_ops dp_ops_cfg = {
  3507. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  3508. };
  3509. static struct cdp_peer_ops dp_ops_peer = {
  3510. .register_peer = dp_register_peer,
  3511. .clear_peer = dp_clear_peer,
  3512. .find_peer_by_addr = dp_find_peer_by_addr,
  3513. .find_peer_by_addr_and_vdev = dp_find_peer_by_addr_and_vdev,
  3514. .local_peer_id = dp_local_peer_id,
  3515. .peer_find_by_local_id = dp_peer_find_by_local_id,
  3516. .peer_state_update = dp_peer_state_update,
  3517. .get_vdevid = dp_get_vdevid,
  3518. .peer_get_peer_mac_addr = dp_peer_get_peer_mac_addr,
  3519. .get_vdev_for_peer = dp_get_vdev_for_peer,
  3520. .get_peer_state = dp_get_peer_state,
  3521. .last_assoc_received = dp_get_last_assoc_received,
  3522. .last_disassoc_received = dp_get_last_disassoc_received,
  3523. .last_deauth_received = dp_get_last_deauth_received,
  3524. };
  3525. #endif
  3526. static struct cdp_ops dp_txrx_ops = {
  3527. .cmn_drv_ops = &dp_ops_cmn,
  3528. .ctrl_ops = &dp_ops_ctrl,
  3529. .me_ops = &dp_ops_me,
  3530. .mon_ops = &dp_ops_mon,
  3531. .host_stats_ops = &dp_ops_host_stats,
  3532. .wds_ops = &dp_ops_wds,
  3533. .raw_ops = &dp_ops_raw,
  3534. #ifdef CONFIG_WIN
  3535. .pflow_ops = &dp_ops_pflow,
  3536. #endif /* CONFIG_WIN */
  3537. #ifndef CONFIG_WIN
  3538. .misc_ops = &dp_ops_misc,
  3539. .cfg_ops = &dp_ops_cfg,
  3540. .flowctl_ops = &dp_ops_flowctl,
  3541. .l_flowctl_ops = &dp_ops_l_flowctl,
  3542. .ipa_ops = &dp_ops_ipa,
  3543. .bus_ops = &dp_ops_bus,
  3544. .ocb_ops = &dp_ops_ocb,
  3545. .peer_ops = &dp_ops_peer,
  3546. .throttle_ops = &dp_ops_throttle,
  3547. .mob_stats_ops = &dp_ops_mob_stats,
  3548. #endif
  3549. };
  3550. /*
  3551. * dp_soc_attach_wifi3() - Attach txrx SOC
  3552. * @osif_soc: Opaque SOC handle from OSIF/HDD
  3553. * @htc_handle: Opaque HTC handle
  3554. * @hif_handle: Opaque HIF handle
  3555. * @qdf_osdev: QDF device
  3556. *
  3557. * Return: DP SOC handle on success, NULL on failure
  3558. */
  3559. /*
  3560. * Local prototype added to temporarily address warning caused by
  3561. * -Wmissing-prototypes. A more correct solution, namely to expose
  3562. * a prototype in an appropriate header file, will come later.
  3563. */
  3564. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  3565. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  3566. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc);
  3567. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  3568. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  3569. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc)
  3570. {
  3571. struct dp_soc *soc = qdf_mem_malloc(sizeof(*soc));
  3572. if (!soc) {
  3573. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3574. FL("DP SOC memory allocation failed"));
  3575. goto fail0;
  3576. }
  3577. soc->cdp_soc.ops = &dp_txrx_ops;
  3578. soc->cdp_soc.ol_ops = ol_ops;
  3579. soc->osif_soc = osif_soc;
  3580. soc->osdev = qdf_osdev;
  3581. soc->hif_handle = hif_handle;
  3582. soc->psoc = psoc;
  3583. soc->hal_soc = hif_get_hal_handle(hif_handle);
  3584. soc->htt_handle = htt_soc_attach(soc, osif_soc, htc_handle,
  3585. soc->hal_soc, qdf_osdev);
  3586. if (!soc->htt_handle) {
  3587. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3588. FL("HTT attach failed"));
  3589. goto fail1;
  3590. }
  3591. soc->wlan_cfg_ctx = wlan_cfg_soc_attach();
  3592. if (!soc->wlan_cfg_ctx) {
  3593. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3594. FL("wlan_cfg_soc_attach failed"));
  3595. goto fail2;
  3596. }
  3597. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  3598. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc,
  3599. CDP_CFG_MAX_PEER_ID);
  3600. if (ret != -EINVAL) {
  3601. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  3602. }
  3603. }
  3604. qdf_spinlock_create(&soc->peer_ref_mutex);
  3605. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  3606. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  3607. return (void *)soc;
  3608. fail2:
  3609. htt_soc_detach(soc->htt_handle);
  3610. fail1:
  3611. qdf_mem_free(soc);
  3612. fail0:
  3613. return NULL;
  3614. }