internal.h 4.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  3. */
  4. #ifndef _WCD937X_INTERNAL_H
  5. #define _WCD937X_INTERNAL_H
  6. #include <asoc/wcd-clsh.h>
  7. #include <asoc/wcd-mbhc-v2.h>
  8. #include <asoc/wcd-irq.h>
  9. #include "wcd937x-mbhc.h"
  10. #include "wcd937x.h"
  11. #define WCD937X_MAX_MICBIAS 3
  12. /* Convert from vout ctl to micbias voltage in mV */
  13. #define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50)
  14. #define MAX_PORT 8
  15. #define MAX_CH_PER_PORT 8
  16. #define WCD937X_MAX_SLAVE_PORT_TYPES 10
  17. extern struct regmap_config wcd937x_regmap_config;
  18. struct codec_port_info {
  19. u32 slave_port_type;
  20. u32 master_port_type;
  21. u32 ch_mask;
  22. u32 num_ch;
  23. u32 ch_rate;
  24. };
  25. struct wcd937x_priv {
  26. struct device *dev;
  27. int variant;
  28. struct snd_soc_component *component;
  29. struct device_node *rst_np;
  30. struct regmap *regmap;
  31. struct swr_device *rx_swr_dev;
  32. struct swr_device *tx_swr_dev;
  33. s32 micb_ref[WCD937X_MAX_MICBIAS];
  34. s32 pullup_ref[WCD937X_MAX_MICBIAS];
  35. struct fw_info *fw_data;
  36. struct device_node *wcd_rst_np;
  37. struct mutex micb_lock;
  38. s32 dmic_0_1_clk_cnt;
  39. s32 dmic_2_3_clk_cnt;
  40. s32 dmic_4_5_clk_cnt;
  41. /* class h specific info */
  42. struct wcd_clsh_cdc_info clsh_info;
  43. /* mbhc module */
  44. struct wcd937x_mbhc *mbhc;
  45. u32 hph_mode;
  46. bool comp1_enable;
  47. bool comp2_enable;
  48. struct irq_domain *virq;
  49. struct wcd_irq_info irq_info;
  50. u32 rx_clk_cnt;
  51. int num_irq_regs;
  52. /* to track the status */
  53. unsigned long status_mask;
  54. u8 num_tx_ports;
  55. u8 num_rx_ports;
  56. struct codec_port_info
  57. tx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
  58. struct codec_port_info
  59. rx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
  60. struct regulator_bulk_data *supplies;
  61. struct notifier_block nblock;
  62. /* wcd callback to bolero */
  63. void *handle;
  64. int (*update_wcd_event)(void *handle, u16 event, u32 data);
  65. int (*register_notifier)(void *handle,
  66. struct notifier_block *nblock,
  67. bool enable);
  68. int (*wakeup)(void *handle, bool enable);
  69. u32 version;
  70. /* Entry for version info */
  71. struct snd_info_entry *entry;
  72. struct snd_info_entry *version_entry;
  73. /*Entry for Variant info*/
  74. struct snd_info_entry *variant_entry;
  75. int ear_rx_path;
  76. int ana_clk_count;
  77. struct mutex ana_tx_clk_lock;
  78. u8 tx_master_ch_map[WCD937X_MAX_SLAVE_CH_TYPES];
  79. };
  80. struct wcd937x_micbias_setting {
  81. u8 ldoh_v;
  82. u32 cfilt1_mv;
  83. u32 micb1_mv;
  84. u32 micb2_mv;
  85. u32 micb3_mv;
  86. u8 bias1_cfilt_sel;
  87. };
  88. struct wcd937x_pdata {
  89. struct device_node *rst_np;
  90. struct device_node *rx_slave;
  91. struct device_node *tx_slave;
  92. struct wcd937x_micbias_setting micbias;
  93. struct cdc_regulator *regulator;
  94. int num_supplies;
  95. };
  96. struct wcd_ctrl_platform_data {
  97. void *handle;
  98. int (*update_wcd_event)(void *handle, u16 event, u32 data);
  99. int (*register_notifier)(void *handle,
  100. struct notifier_block *nblock,
  101. bool enable);
  102. };
  103. enum {
  104. WCD_RX1,
  105. WCD_RX2,
  106. WCD_RX3
  107. };
  108. enum {
  109. BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR = 1,
  110. BOLERO_WCD_EVT_PA_OFF_PRE_SSR,
  111. BOLERO_WCD_EVT_SSR_DOWN,
  112. BOLERO_WCD_EVT_SSR_UP,
  113. };
  114. enum {
  115. WCD_BOLERO_EVT_RX_MUTE = 1, /* for RX mute/unmute */
  116. WCD_BOLERO_EVT_IMPED_TRUE, /* for imped true */
  117. WCD_BOLERO_EVT_IMPED_FALSE, /* for imped false */
  118. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  119. WCD_BOLERO_EVT_BCS_CLK_OFF,
  120. };
  121. enum {
  122. /* INTR_CTRL_INT_MASK_0 */
  123. WCD937X_IRQ_MBHC_BUTTON_PRESS_DET = 0,
  124. WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET,
  125. WCD937X_IRQ_MBHC_ELECT_INS_REM_DET,
  126. WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
  127. WCD937X_IRQ_MBHC_SW_DET,
  128. WCD937X_IRQ_HPHR_OCP_INT,
  129. WCD937X_IRQ_HPHR_CNP_INT,
  130. WCD937X_IRQ_HPHL_OCP_INT,
  131. /* INTR_CTRL_INT_MASK_1 */
  132. WCD937X_IRQ_HPHL_CNP_INT,
  133. WCD937X_IRQ_EAR_CNP_INT,
  134. WCD937X_IRQ_EAR_SCD_INT,
  135. WCD937X_IRQ_AUX_CNP_INT,
  136. WCD937X_IRQ_AUX_SCD_INT,
  137. WCD937X_IRQ_HPHL_PDM_WD_INT,
  138. WCD937X_IRQ_HPHR_PDM_WD_INT,
  139. WCD937X_IRQ_AUX_PDM_WD_INT,
  140. /* INTR_CTRL_INT_MASK_2 */
  141. WCD937X_IRQ_LDORT_SCD_INT,
  142. WCD937X_IRQ_MBHC_MOISTURE_INT,
  143. WCD937X_IRQ_HPHL_SURGE_DET_INT,
  144. WCD937X_IRQ_HPHR_SURGE_DET_INT,
  145. WCD937X_NUM_IRQS,
  146. };
  147. extern void wcd937x_disable_bcs_before_slow_insert(
  148. struct snd_soc_component *component,
  149. bool bcs_disable);
  150. extern struct wcd937x_mbhc *wcd937x_soc_get_mbhc(
  151. struct snd_soc_component *component);
  152. extern int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  153. int volt, int micb_num);
  154. extern int wcd937x_get_micb_vout_ctl_val(u32 micb_mv);
  155. extern int wcd937x_micbias_control(struct snd_soc_component *component,
  156. int micb_num, int req, bool is_dapm);
  157. #endif