debug.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */
  3. /* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */
  4. #include <linux/err.h>
  5. #include <linux/seq_file.h>
  6. #include <linux/debugfs.h>
  7. #include "main.h"
  8. #include "bus.h"
  9. #include "debug.h"
  10. #include "pci.h"
  11. #define MMIO_REG_ACCESS_MEM_TYPE 0xFF
  12. #define MMIO_REG_RAW_ACCESS_MEM_TYPE 0xFE
  13. #if IS_ENABLED(CONFIG_IPC_LOGGING)
  14. void *cnss_ipc_log_context;
  15. void *cnss_ipc_log_long_context;
  16. #endif
  17. static int cnss_pin_connect_show(struct seq_file *s, void *data)
  18. {
  19. struct cnss_plat_data *cnss_priv = s->private;
  20. seq_puts(s, "Pin connect results\n");
  21. seq_printf(s, "FW power pin result: %04x\n",
  22. cnss_priv->pin_result.fw_pwr_pin_result);
  23. seq_printf(s, "FW PHY IO pin result: %04x\n",
  24. cnss_priv->pin_result.fw_phy_io_pin_result);
  25. seq_printf(s, "FW RF pin result: %04x\n",
  26. cnss_priv->pin_result.fw_rf_pin_result);
  27. seq_printf(s, "Host pin result: %04x\n",
  28. cnss_priv->pin_result.host_pin_result);
  29. seq_puts(s, "\n");
  30. return 0;
  31. }
  32. static int cnss_pin_connect_open(struct inode *inode, struct file *file)
  33. {
  34. return single_open(file, cnss_pin_connect_show, inode->i_private);
  35. }
  36. static const struct file_operations cnss_pin_connect_fops = {
  37. .read = seq_read,
  38. .release = single_release,
  39. .open = cnss_pin_connect_open,
  40. .owner = THIS_MODULE,
  41. .llseek = seq_lseek,
  42. };
  43. static int cnss_stats_show_state(struct seq_file *s,
  44. struct cnss_plat_data *plat_priv)
  45. {
  46. enum cnss_driver_state i;
  47. int skip = 0;
  48. unsigned long state;
  49. seq_printf(s, "\nState: 0x%lx(", plat_priv->driver_state);
  50. for (i = 0, state = plat_priv->driver_state; state != 0;
  51. state >>= 1, i++) {
  52. if (!(state & 0x1))
  53. continue;
  54. if (skip++)
  55. seq_puts(s, " | ");
  56. switch (i) {
  57. case CNSS_QMI_WLFW_CONNECTED:
  58. seq_puts(s, "QMI_WLFW_CONNECTED");
  59. continue;
  60. case CNSS_FW_MEM_READY:
  61. seq_puts(s, "FW_MEM_READY");
  62. continue;
  63. case CNSS_FW_READY:
  64. seq_puts(s, "FW_READY");
  65. continue;
  66. case CNSS_IN_COLD_BOOT_CAL:
  67. seq_puts(s, "IN_COLD_BOOT_CAL");
  68. continue;
  69. case CNSS_DRIVER_LOADING:
  70. seq_puts(s, "DRIVER_LOADING");
  71. continue;
  72. case CNSS_DRIVER_UNLOADING:
  73. seq_puts(s, "DRIVER_UNLOADING");
  74. continue;
  75. case CNSS_DRIVER_IDLE_RESTART:
  76. seq_puts(s, "IDLE_RESTART");
  77. continue;
  78. case CNSS_DRIVER_IDLE_SHUTDOWN:
  79. seq_puts(s, "IDLE_SHUTDOWN");
  80. continue;
  81. case CNSS_DRIVER_PROBED:
  82. seq_puts(s, "DRIVER_PROBED");
  83. continue;
  84. case CNSS_DRIVER_RECOVERY:
  85. seq_puts(s, "DRIVER_RECOVERY");
  86. continue;
  87. case CNSS_FW_BOOT_RECOVERY:
  88. seq_puts(s, "FW_BOOT_RECOVERY");
  89. continue;
  90. case CNSS_DEV_ERR_NOTIFY:
  91. seq_puts(s, "DEV_ERR");
  92. continue;
  93. case CNSS_DRIVER_DEBUG:
  94. seq_puts(s, "DRIVER_DEBUG");
  95. continue;
  96. case CNSS_COEX_CONNECTED:
  97. seq_puts(s, "COEX_CONNECTED");
  98. continue;
  99. case CNSS_IMS_CONNECTED:
  100. seq_puts(s, "IMS_CONNECTED");
  101. continue;
  102. case CNSS_IN_SUSPEND_RESUME:
  103. seq_puts(s, "IN_SUSPEND_RESUME");
  104. continue;
  105. case CNSS_IN_REBOOT:
  106. seq_puts(s, "IN_REBOOT");
  107. continue;
  108. case CNSS_COLD_BOOT_CAL_DONE:
  109. seq_puts(s, "COLD_BOOT_CAL_DONE");
  110. continue;
  111. case CNSS_IN_PANIC:
  112. seq_puts(s, "IN_PANIC");
  113. continue;
  114. case CNSS_QMI_DEL_SERVER:
  115. seq_puts(s, "DEL_SERVER_IN_PROGRESS");
  116. continue;
  117. case CNSS_QMI_DMS_CONNECTED:
  118. seq_puts(s, "DMS_CONNECTED");
  119. continue;
  120. case CNSS_DAEMON_CONNECTED:
  121. seq_puts(s, "DAEMON_CONNECTED");
  122. continue;
  123. case CNSS_PCI_PROBE_DONE:
  124. seq_puts(s, "PCI PROBE DONE");
  125. continue;
  126. case CNSS_DRIVER_REGISTER:
  127. seq_puts(s, "DRIVER REGISTERED");
  128. continue;
  129. case CNSS_WLAN_HW_DISABLED:
  130. seq_puts(s, "WLAN HW DISABLED");
  131. continue;
  132. case CNSS_FS_READY:
  133. seq_puts(s, "FS READY");
  134. continue;
  135. }
  136. seq_printf(s, "UNKNOWN-%d", i);
  137. }
  138. seq_puts(s, ")\n");
  139. return 0;
  140. }
  141. static int cnss_stats_show_gpio_state(struct seq_file *s,
  142. struct cnss_plat_data *plat_priv)
  143. {
  144. seq_printf(s, "\nHost SOL: %d", cnss_get_host_sol_value(plat_priv));
  145. seq_printf(s, "\nDev SOL: %d", cnss_get_dev_sol_value(plat_priv));
  146. return 0;
  147. }
  148. static int cnss_stats_show(struct seq_file *s, void *data)
  149. {
  150. struct cnss_plat_data *plat_priv = s->private;
  151. cnss_stats_show_state(s, plat_priv);
  152. cnss_stats_show_gpio_state(s, plat_priv);
  153. return 0;
  154. }
  155. static int cnss_stats_open(struct inode *inode, struct file *file)
  156. {
  157. return single_open(file, cnss_stats_show, inode->i_private);
  158. }
  159. static const struct file_operations cnss_stats_fops = {
  160. .read = seq_read,
  161. .release = single_release,
  162. .open = cnss_stats_open,
  163. .owner = THIS_MODULE,
  164. .llseek = seq_lseek,
  165. };
  166. static ssize_t cnss_dev_boot_debug_write(struct file *fp,
  167. const char __user *user_buf,
  168. size_t count, loff_t *off)
  169. {
  170. struct cnss_plat_data *plat_priv =
  171. ((struct seq_file *)fp->private_data)->private;
  172. struct cnss_pci_data *pci_priv;
  173. char buf[64];
  174. char *cmd;
  175. unsigned int len = 0;
  176. char *sptr, *token;
  177. const char *delim = " ";
  178. int ret = 0;
  179. if (!plat_priv)
  180. return -ENODEV;
  181. len = min(count, sizeof(buf) - 1);
  182. if (copy_from_user(buf, user_buf, len))
  183. return -EFAULT;
  184. buf[len] = '\0';
  185. sptr = buf;
  186. token = strsep(&sptr, delim);
  187. if (!token)
  188. return -EINVAL;
  189. cmd = token;
  190. cnss_pr_dbg("Received dev_boot debug command: %s\n", cmd);
  191. if (sysfs_streq(cmd, "on")) {
  192. ret = cnss_power_on_device(plat_priv);
  193. } else if (sysfs_streq(cmd, "off")) {
  194. cnss_power_off_device(plat_priv);
  195. } else if (sysfs_streq(cmd, "enumerate")) {
  196. ret = cnss_pci_init(plat_priv);
  197. } else if (sysfs_streq(cmd, "powerup")) {
  198. set_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
  199. ret = cnss_driver_event_post(plat_priv,
  200. CNSS_DRIVER_EVENT_POWER_UP,
  201. CNSS_EVENT_SYNC, NULL);
  202. } else if (sysfs_streq(cmd, "shutdown")) {
  203. ret = cnss_driver_event_post(plat_priv,
  204. CNSS_DRIVER_EVENT_POWER_DOWN,
  205. 0, NULL);
  206. clear_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
  207. } else if (sysfs_streq(cmd, "assert_host_sol")) {
  208. ret = cnss_set_host_sol_value(plat_priv, 1);
  209. } else if (sysfs_streq(cmd, "deassert_host_sol")) {
  210. ret = cnss_set_host_sol_value(plat_priv, 0);
  211. } else if (sysfs_streq(cmd, "pdc_update")) {
  212. if (!sptr)
  213. return -EINVAL;
  214. ret = cnss_aop_send_msg(plat_priv, sptr);
  215. } else if (sysfs_streq(cmd, "dev_check")) {
  216. cnss_wlan_hw_disable_check(plat_priv);
  217. } else if (sysfs_streq(cmd, "dev_enable")) {
  218. cnss_wlan_hw_enable();
  219. } else {
  220. pci_priv = plat_priv->bus_priv;
  221. if (!pci_priv)
  222. return -ENODEV;
  223. if (sysfs_streq(cmd, "download")) {
  224. set_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
  225. ret = cnss_pci_start_mhi(pci_priv);
  226. } else if (sysfs_streq(cmd, "linkup")) {
  227. ret = cnss_resume_pci_link(pci_priv);
  228. } else if (sysfs_streq(cmd, "linkdown")) {
  229. ret = cnss_suspend_pci_link(pci_priv);
  230. } else if (sysfs_streq(cmd, "assert")) {
  231. cnss_pr_info("FW Assert triggered for debug\n");
  232. ret = cnss_force_fw_assert(&pci_priv->pci_dev->dev);
  233. } else if (sysfs_streq(cmd, "set_cbc_done")) {
  234. cnss_pr_dbg("Force set cold boot cal done status\n");
  235. set_bit(CNSS_COLD_BOOT_CAL_DONE,
  236. &plat_priv->driver_state);
  237. } else {
  238. cnss_pr_err("Device boot debugfs command is invalid\n");
  239. ret = -EINVAL;
  240. }
  241. }
  242. if (ret < 0)
  243. return ret;
  244. return count;
  245. }
  246. static int cnss_dev_boot_debug_show(struct seq_file *s, void *data)
  247. {
  248. seq_puts(s, "\nUsage: echo <action> > <debugfs_path>/cnss/dev_boot\n");
  249. seq_puts(s, "<action> can be one of below:\n");
  250. seq_puts(s, "on: turn on device power, assert WLAN_EN\n");
  251. seq_puts(s, "off: de-assert WLAN_EN, turn off device power\n");
  252. seq_puts(s, "enumerate: de-assert PERST, enumerate PCIe\n");
  253. seq_puts(s, "download: download FW and do QMI handshake with FW\n");
  254. seq_puts(s, "linkup: bring up PCIe link\n");
  255. seq_puts(s, "linkdown: bring down PCIe link\n");
  256. seq_puts(s, "powerup: full power on sequence to boot device, download FW and do QMI handshake with FW\n");
  257. seq_puts(s, "shutdown: full power off sequence to shutdown device\n");
  258. seq_puts(s, "assert: trigger firmware assert\n");
  259. seq_puts(s, "set_cbc_done: Set cold boot calibration done status\n");
  260. seq_puts(s, "\npdc_update usage:");
  261. seq_puts(s, "1. echo pdc_update {class: wlan_pdc ss: <pdc_ss>, res: <vreg>.<mode>, <seq>: <val>} > <debugfs_path>/cnss/dev_boot\n");
  262. seq_puts(s, "2. echo pdc_update {class: wlan_pdc ss: <pdc_ss>, res: pdc, enable: <val>} > <debugfs_path>/cnss/dev_boot\n");
  263. return 0;
  264. }
  265. static int cnss_dev_boot_debug_open(struct inode *inode, struct file *file)
  266. {
  267. return single_open(file, cnss_dev_boot_debug_show, inode->i_private);
  268. }
  269. static const struct file_operations cnss_dev_boot_debug_fops = {
  270. .read = seq_read,
  271. .write = cnss_dev_boot_debug_write,
  272. .release = single_release,
  273. .open = cnss_dev_boot_debug_open,
  274. .owner = THIS_MODULE,
  275. .llseek = seq_lseek,
  276. };
  277. static int cnss_reg_read_debug_show(struct seq_file *s, void *data)
  278. {
  279. struct cnss_plat_data *plat_priv = s->private;
  280. mutex_lock(&plat_priv->dev_lock);
  281. if (!plat_priv->diag_reg_read_buf) {
  282. seq_puts(s, "\nUsage: echo <mem_type> <offset> <data_len> > <debugfs_path>/cnss/reg_read\n");
  283. seq_puts(s, "Use mem_type = 0xff for register read by IO access, data_len will be ignored\n");
  284. seq_puts(s, "Use mem_type = 0xfe for register read by raw IO access which skips sanity checks, data_len will be ignored\n");
  285. seq_puts(s, "Use other mem_type for register read by QMI\n");
  286. mutex_unlock(&plat_priv->dev_lock);
  287. return 0;
  288. }
  289. seq_printf(s, "\nRegister read, address: 0x%x memory type: 0x%x length: 0x%x\n\n",
  290. plat_priv->diag_reg_read_addr,
  291. plat_priv->diag_reg_read_mem_type,
  292. plat_priv->diag_reg_read_len);
  293. seq_hex_dump(s, "", DUMP_PREFIX_OFFSET, 32, 4,
  294. plat_priv->diag_reg_read_buf,
  295. plat_priv->diag_reg_read_len, false);
  296. plat_priv->diag_reg_read_len = 0;
  297. kfree(plat_priv->diag_reg_read_buf);
  298. plat_priv->diag_reg_read_buf = NULL;
  299. mutex_unlock(&plat_priv->dev_lock);
  300. return 0;
  301. }
  302. static ssize_t cnss_reg_read_debug_write(struct file *fp,
  303. const char __user *user_buf,
  304. size_t count, loff_t *off)
  305. {
  306. struct cnss_plat_data *plat_priv =
  307. ((struct seq_file *)fp->private_data)->private;
  308. char buf[64];
  309. char *sptr, *token;
  310. unsigned int len = 0;
  311. u32 reg_offset, mem_type;
  312. u32 data_len = 0, reg_val = 0;
  313. u8 *reg_buf = NULL;
  314. const char *delim = " ";
  315. int ret = 0;
  316. len = min(count, sizeof(buf) - 1);
  317. if (copy_from_user(buf, user_buf, len))
  318. return -EFAULT;
  319. buf[len] = '\0';
  320. sptr = buf;
  321. token = strsep(&sptr, delim);
  322. if (!token)
  323. return -EINVAL;
  324. if (!sptr)
  325. return -EINVAL;
  326. if (kstrtou32(token, 0, &mem_type))
  327. return -EINVAL;
  328. token = strsep(&sptr, delim);
  329. if (!token)
  330. return -EINVAL;
  331. if (!sptr)
  332. return -EINVAL;
  333. if (kstrtou32(token, 0, &reg_offset))
  334. return -EINVAL;
  335. token = strsep(&sptr, delim);
  336. if (!token)
  337. return -EINVAL;
  338. if (kstrtou32(token, 0, &data_len))
  339. return -EINVAL;
  340. if (mem_type == MMIO_REG_ACCESS_MEM_TYPE ||
  341. mem_type == MMIO_REG_RAW_ACCESS_MEM_TYPE) {
  342. ret = cnss_bus_debug_reg_read(plat_priv, reg_offset, &reg_val,
  343. mem_type ==
  344. MMIO_REG_RAW_ACCESS_MEM_TYPE);
  345. if (ret)
  346. return ret;
  347. cnss_pr_dbg("Read 0x%x from register offset 0x%x\n", reg_val,
  348. reg_offset);
  349. return count;
  350. }
  351. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  352. cnss_pr_err("Firmware is not ready yet\n");
  353. return -EINVAL;
  354. }
  355. mutex_lock(&plat_priv->dev_lock);
  356. kfree(plat_priv->diag_reg_read_buf);
  357. plat_priv->diag_reg_read_buf = NULL;
  358. reg_buf = kzalloc(data_len, GFP_KERNEL);
  359. if (!reg_buf) {
  360. mutex_unlock(&plat_priv->dev_lock);
  361. return -ENOMEM;
  362. }
  363. ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, reg_offset,
  364. mem_type, data_len,
  365. reg_buf);
  366. if (ret) {
  367. kfree(reg_buf);
  368. mutex_unlock(&plat_priv->dev_lock);
  369. return ret;
  370. }
  371. plat_priv->diag_reg_read_addr = reg_offset;
  372. plat_priv->diag_reg_read_mem_type = mem_type;
  373. plat_priv->diag_reg_read_len = data_len;
  374. plat_priv->diag_reg_read_buf = reg_buf;
  375. mutex_unlock(&plat_priv->dev_lock);
  376. return count;
  377. }
  378. static int cnss_reg_read_debug_open(struct inode *inode, struct file *file)
  379. {
  380. return single_open(file, cnss_reg_read_debug_show, inode->i_private);
  381. }
  382. static const struct file_operations cnss_reg_read_debug_fops = {
  383. .read = seq_read,
  384. .write = cnss_reg_read_debug_write,
  385. .open = cnss_reg_read_debug_open,
  386. .owner = THIS_MODULE,
  387. .llseek = seq_lseek,
  388. };
  389. static int cnss_reg_write_debug_show(struct seq_file *s, void *data)
  390. {
  391. seq_puts(s, "\nUsage: echo <mem_type> <offset> <reg_val> > <debugfs_path>/cnss/reg_write\n");
  392. seq_puts(s, "Use mem_type = 0xff for register write by IO access\n");
  393. seq_puts(s, "Use mem_type = 0xfe for register write by raw IO access which skips sanity checks\n");
  394. seq_puts(s, "Use other mem_type for register write by QMI\n");
  395. return 0;
  396. }
  397. static ssize_t cnss_reg_write_debug_write(struct file *fp,
  398. const char __user *user_buf,
  399. size_t count, loff_t *off)
  400. {
  401. struct cnss_plat_data *plat_priv =
  402. ((struct seq_file *)fp->private_data)->private;
  403. char buf[64];
  404. char *sptr, *token;
  405. unsigned int len = 0;
  406. u32 reg_offset, mem_type, reg_val;
  407. const char *delim = " ";
  408. int ret = 0;
  409. len = min(count, sizeof(buf) - 1);
  410. if (copy_from_user(buf, user_buf, len))
  411. return -EFAULT;
  412. buf[len] = '\0';
  413. sptr = buf;
  414. token = strsep(&sptr, delim);
  415. if (!token)
  416. return -EINVAL;
  417. if (!sptr)
  418. return -EINVAL;
  419. if (kstrtou32(token, 0, &mem_type))
  420. return -EINVAL;
  421. token = strsep(&sptr, delim);
  422. if (!token)
  423. return -EINVAL;
  424. if (!sptr)
  425. return -EINVAL;
  426. if (kstrtou32(token, 0, &reg_offset))
  427. return -EINVAL;
  428. token = strsep(&sptr, delim);
  429. if (!token)
  430. return -EINVAL;
  431. if (kstrtou32(token, 0, &reg_val))
  432. return -EINVAL;
  433. if (mem_type == MMIO_REG_ACCESS_MEM_TYPE ||
  434. mem_type == MMIO_REG_RAW_ACCESS_MEM_TYPE) {
  435. ret = cnss_bus_debug_reg_write(plat_priv, reg_offset, reg_val,
  436. mem_type ==
  437. MMIO_REG_RAW_ACCESS_MEM_TYPE);
  438. if (ret)
  439. return ret;
  440. cnss_pr_dbg("Wrote 0x%x to register offset 0x%x\n", reg_val,
  441. reg_offset);
  442. return count;
  443. }
  444. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  445. cnss_pr_err("Firmware is not ready yet\n");
  446. return -EINVAL;
  447. }
  448. ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, reg_offset, mem_type,
  449. sizeof(u32),
  450. (u8 *)&reg_val);
  451. if (ret)
  452. return ret;
  453. return count;
  454. }
  455. static int cnss_reg_write_debug_open(struct inode *inode, struct file *file)
  456. {
  457. return single_open(file, cnss_reg_write_debug_show, inode->i_private);
  458. }
  459. static const struct file_operations cnss_reg_write_debug_fops = {
  460. .read = seq_read,
  461. .write = cnss_reg_write_debug_write,
  462. .open = cnss_reg_write_debug_open,
  463. .owner = THIS_MODULE,
  464. .llseek = seq_lseek,
  465. };
  466. static ssize_t cnss_runtime_pm_debug_write(struct file *fp,
  467. const char __user *user_buf,
  468. size_t count, loff_t *off)
  469. {
  470. struct cnss_plat_data *plat_priv =
  471. ((struct seq_file *)fp->private_data)->private;
  472. struct cnss_pci_data *pci_priv;
  473. char buf[64];
  474. char *cmd;
  475. unsigned int len = 0;
  476. int ret = 0;
  477. if (!plat_priv)
  478. return -ENODEV;
  479. pci_priv = plat_priv->bus_priv;
  480. if (!pci_priv)
  481. return -ENODEV;
  482. len = min(count, sizeof(buf) - 1);
  483. if (copy_from_user(buf, user_buf, len))
  484. return -EFAULT;
  485. buf[len] = '\0';
  486. cmd = buf;
  487. if (sysfs_streq(cmd, "usage_count")) {
  488. cnss_pci_pm_runtime_show_usage_count(pci_priv);
  489. } else if (sysfs_streq(cmd, "request_resume")) {
  490. ret = cnss_pci_pm_request_resume(pci_priv);
  491. } else if (sysfs_streq(cmd, "resume")) {
  492. ret = cnss_pci_pm_runtime_resume(pci_priv);
  493. } else if (sysfs_streq(cmd, "get")) {
  494. ret = cnss_pci_pm_runtime_get(pci_priv, RTPM_ID_CNSS);
  495. } else if (sysfs_streq(cmd, "get_noresume")) {
  496. cnss_pci_pm_runtime_get_noresume(pci_priv, RTPM_ID_CNSS);
  497. } else if (sysfs_streq(cmd, "put_autosuspend")) {
  498. ret = cnss_pci_pm_runtime_put_autosuspend(pci_priv,
  499. RTPM_ID_CNSS);
  500. } else if (sysfs_streq(cmd, "put_noidle")) {
  501. cnss_pci_pm_runtime_put_noidle(pci_priv, RTPM_ID_CNSS);
  502. } else if (sysfs_streq(cmd, "mark_last_busy")) {
  503. cnss_pci_pm_runtime_mark_last_busy(pci_priv);
  504. } else if (sysfs_streq(cmd, "resume_bus")) {
  505. cnss_pci_resume_bus(pci_priv);
  506. } else if (sysfs_streq(cmd, "suspend_bus")) {
  507. cnss_pci_suspend_bus(pci_priv);
  508. } else {
  509. cnss_pr_err("Runtime PM debugfs command is invalid\n");
  510. ret = -EINVAL;
  511. }
  512. if (ret < 0)
  513. return ret;
  514. return count;
  515. }
  516. static int cnss_runtime_pm_debug_show(struct seq_file *s, void *data)
  517. {
  518. struct cnss_plat_data *plat_priv = s->private;
  519. struct cnss_pci_data *pci_priv;
  520. int i;
  521. if (!plat_priv)
  522. return -ENODEV;
  523. pci_priv = plat_priv->bus_priv;
  524. if (!pci_priv)
  525. return -ENODEV;
  526. seq_puts(s, "\nUsage: echo <action> > <debugfs_path>/cnss/runtime_pm\n");
  527. seq_puts(s, "<action> can be one of below:\n");
  528. seq_puts(s, "usage_count: get runtime PM usage count\n");
  529. seq_puts(s, "reques_resume: do async runtime PM resume\n");
  530. seq_puts(s, "resume: do sync runtime PM resume\n");
  531. seq_puts(s, "get: do runtime PM get\n");
  532. seq_puts(s, "get_noresume: do runtime PM get noresume\n");
  533. seq_puts(s, "put_noidle: do runtime PM put noidle\n");
  534. seq_puts(s, "put_autosuspend: do runtime PM put autosuspend\n");
  535. seq_puts(s, "mark_last_busy: do runtime PM mark last busy\n");
  536. seq_puts(s, "resume_bus: do bus resume only\n");
  537. seq_puts(s, "suspend_bus: do bus suspend only\n");
  538. seq_puts(s, "\nStats:\n");
  539. seq_printf(s, "%s: %u\n", "get count",
  540. atomic_read(&pci_priv->pm_stats.runtime_get));
  541. seq_printf(s, "%s: %u\n", "put count",
  542. atomic_read(&pci_priv->pm_stats.runtime_put));
  543. seq_printf(s, "%-10s%-10s%-10s%-15s%-15s\n",
  544. "id:", "get", "put", "get time(us)", "put time(us)");
  545. for (i = 0; i < RTPM_ID_MAX; i++) {
  546. seq_printf(s, "%d%-9s", i, ":");
  547. seq_printf(s, "%-10d",
  548. atomic_read(&pci_priv->pm_stats.runtime_get_id[i]));
  549. seq_printf(s, "%-10d",
  550. atomic_read(&pci_priv->pm_stats.runtime_put_id[i]));
  551. seq_printf(s, "%-15llu",
  552. pci_priv->pm_stats.runtime_get_timestamp_id[i]);
  553. seq_printf(s, "%-15llu\n",
  554. pci_priv->pm_stats.runtime_put_timestamp_id[i]);
  555. }
  556. return 0;
  557. }
  558. static int cnss_runtime_pm_debug_open(struct inode *inode, struct file *file)
  559. {
  560. return single_open(file, cnss_runtime_pm_debug_show, inode->i_private);
  561. }
  562. static const struct file_operations cnss_runtime_pm_debug_fops = {
  563. .read = seq_read,
  564. .write = cnss_runtime_pm_debug_write,
  565. .open = cnss_runtime_pm_debug_open,
  566. .owner = THIS_MODULE,
  567. .llseek = seq_lseek,
  568. };
  569. static int process_drv(struct cnss_plat_data *plat_priv, bool enabled)
  570. {
  571. if (test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state)) {
  572. cnss_pr_err("DRV cmd must be used before QMI ready\n");
  573. return -EINVAL;
  574. }
  575. enabled ? cnss_set_feature_list(plat_priv, CNSS_DRV_SUPPORT_V01) :
  576. cnss_clear_feature_list(plat_priv, CNSS_DRV_SUPPORT_V01);
  577. cnss_pr_info("%s DRV suspend\n", enabled ? "enable" : "disable");
  578. return 0;
  579. }
  580. static int process_quirks(struct cnss_plat_data *plat_priv, u32 val)
  581. {
  582. enum cnss_debug_quirks i;
  583. int ret = 0;
  584. unsigned long state;
  585. unsigned long quirks = 0;
  586. for (i = 0, state = val; i < QUIRK_MAX_VALUE; state >>= 1, i++) {
  587. switch (i) {
  588. case DISABLE_DRV:
  589. ret = process_drv(plat_priv, !(state & 0x1));
  590. if (!ret)
  591. quirks |= (state & 0x1) << i;
  592. continue;
  593. default:
  594. quirks |= (state & 0x1) << i;
  595. continue;
  596. }
  597. }
  598. plat_priv->ctrl_params.quirks = quirks;
  599. return 0;
  600. }
  601. static ssize_t cnss_control_params_debug_write(struct file *fp,
  602. const char __user *user_buf,
  603. size_t count, loff_t *off)
  604. {
  605. struct cnss_plat_data *plat_priv =
  606. ((struct seq_file *)fp->private_data)->private;
  607. char buf[64];
  608. char *sptr, *token;
  609. char *cmd;
  610. u32 val;
  611. unsigned int len = 0;
  612. const char *delim = " ";
  613. if (!plat_priv)
  614. return -ENODEV;
  615. len = min(count, sizeof(buf) - 1);
  616. if (copy_from_user(buf, user_buf, len))
  617. return -EFAULT;
  618. buf[len] = '\0';
  619. sptr = buf;
  620. token = strsep(&sptr, delim);
  621. if (!token)
  622. return -EINVAL;
  623. if (!sptr)
  624. return -EINVAL;
  625. cmd = token;
  626. token = strsep(&sptr, delim);
  627. if (!token)
  628. return -EINVAL;
  629. if (kstrtou32(token, 0, &val))
  630. return -EINVAL;
  631. if (strcmp(cmd, "quirks") == 0)
  632. process_quirks(plat_priv, val);
  633. else if (strcmp(cmd, "mhi_timeout") == 0)
  634. plat_priv->ctrl_params.mhi_timeout = val;
  635. else if (strcmp(cmd, "mhi_m2_timeout") == 0)
  636. plat_priv->ctrl_params.mhi_m2_timeout = val;
  637. else if (strcmp(cmd, "qmi_timeout") == 0)
  638. plat_priv->ctrl_params.qmi_timeout = val;
  639. else if (strcmp(cmd, "bdf_type") == 0)
  640. plat_priv->ctrl_params.bdf_type = val;
  641. else if (strcmp(cmd, "time_sync_period") == 0)
  642. plat_priv->ctrl_params.time_sync_period = val;
  643. else
  644. return -EINVAL;
  645. return count;
  646. }
  647. static int cnss_show_quirks_state(struct seq_file *s,
  648. struct cnss_plat_data *plat_priv)
  649. {
  650. enum cnss_debug_quirks i;
  651. int skip = 0;
  652. unsigned long state;
  653. seq_printf(s, "quirks: 0x%lx (", plat_priv->ctrl_params.quirks);
  654. for (i = 0, state = plat_priv->ctrl_params.quirks;
  655. state != 0; state >>= 1, i++) {
  656. if (!(state & 0x1))
  657. continue;
  658. if (skip++)
  659. seq_puts(s, " | ");
  660. switch (i) {
  661. case LINK_DOWN_SELF_RECOVERY:
  662. seq_puts(s, "LINK_DOWN_SELF_RECOVERY");
  663. continue;
  664. case SKIP_DEVICE_BOOT:
  665. seq_puts(s, "SKIP_DEVICE_BOOT");
  666. continue;
  667. case USE_CORE_ONLY_FW:
  668. seq_puts(s, "USE_CORE_ONLY_FW");
  669. continue;
  670. case SKIP_RECOVERY:
  671. seq_puts(s, "SKIP_RECOVERY");
  672. continue;
  673. case QMI_BYPASS:
  674. seq_puts(s, "QMI_BYPASS");
  675. continue;
  676. case ENABLE_WALTEST:
  677. seq_puts(s, "WALTEST");
  678. continue;
  679. case ENABLE_PCI_LINK_DOWN_PANIC:
  680. seq_puts(s, "PCI_LINK_DOWN_PANIC");
  681. continue;
  682. case FBC_BYPASS:
  683. seq_puts(s, "FBC_BYPASS");
  684. continue;
  685. case ENABLE_DAEMON_SUPPORT:
  686. seq_puts(s, "DAEMON_SUPPORT");
  687. continue;
  688. case DISABLE_DRV:
  689. seq_puts(s, "DISABLE_DRV");
  690. continue;
  691. case DISABLE_IO_COHERENCY:
  692. seq_puts(s, "DISABLE_IO_COHERENCY");
  693. continue;
  694. case IGNORE_PCI_LINK_FAILURE:
  695. seq_puts(s, "IGNORE_PCI_LINK_FAILURE");
  696. continue;
  697. case DISABLE_TIME_SYNC:
  698. seq_puts(s, "DISABLE_TIME_SYNC");
  699. continue;
  700. default:
  701. continue;
  702. }
  703. }
  704. seq_puts(s, ")\n");
  705. return 0;
  706. }
  707. static int cnss_control_params_debug_show(struct seq_file *s, void *data)
  708. {
  709. struct cnss_plat_data *cnss_priv = s->private;
  710. seq_puts(s, "\nUsage: echo <params_name> <value> > <debugfs_path>/cnss/control_params\n");
  711. seq_puts(s, "<params_name> can be one of below:\n");
  712. seq_puts(s, "quirks: Debug quirks for driver\n");
  713. seq_puts(s, "mhi_timeout: Timeout for MHI operation in milliseconds\n");
  714. seq_puts(s, "qmi_timeout: Timeout for QMI message in milliseconds\n");
  715. seq_puts(s, "bdf_type: Type of board data file to be downloaded\n");
  716. seq_puts(s, "time_sync_period: Time period to do time sync with device in milliseconds\n");
  717. seq_puts(s, "\nCurrent value:\n");
  718. cnss_show_quirks_state(s, cnss_priv);
  719. seq_printf(s, "mhi_timeout: %u\n", cnss_priv->ctrl_params.mhi_timeout);
  720. seq_printf(s, "mhi_m2_timeout: %u\n",
  721. cnss_priv->ctrl_params.mhi_m2_timeout);
  722. seq_printf(s, "qmi_timeout: %u\n", cnss_priv->ctrl_params.qmi_timeout);
  723. seq_printf(s, "bdf_type: %u\n", cnss_priv->ctrl_params.bdf_type);
  724. seq_printf(s, "time_sync_period: %u\n",
  725. cnss_priv->ctrl_params.time_sync_period);
  726. return 0;
  727. }
  728. static int cnss_control_params_debug_open(struct inode *inode,
  729. struct file *file)
  730. {
  731. return single_open(file, cnss_control_params_debug_show,
  732. inode->i_private);
  733. }
  734. static const struct file_operations cnss_control_params_debug_fops = {
  735. .read = seq_read,
  736. .write = cnss_control_params_debug_write,
  737. .open = cnss_control_params_debug_open,
  738. .owner = THIS_MODULE,
  739. .llseek = seq_lseek,
  740. };
  741. static ssize_t cnss_dynamic_feature_write(struct file *fp,
  742. const char __user *user_buf,
  743. size_t count, loff_t *off)
  744. {
  745. struct cnss_plat_data *plat_priv =
  746. ((struct seq_file *)fp->private_data)->private;
  747. int ret = 0;
  748. u64 val;
  749. ret = kstrtou64_from_user(user_buf, count, 0, &val);
  750. if (ret)
  751. return ret;
  752. plat_priv->dynamic_feature = val;
  753. ret = cnss_wlfw_dynamic_feature_mask_send_sync(plat_priv);
  754. if (ret < 0)
  755. return ret;
  756. return count;
  757. }
  758. static int cnss_dynamic_feature_show(struct seq_file *s, void *data)
  759. {
  760. struct cnss_plat_data *cnss_priv = s->private;
  761. seq_printf(s, "dynamic_feature: 0x%llx\n", cnss_priv->dynamic_feature);
  762. return 0;
  763. }
  764. static int cnss_dynamic_feature_open(struct inode *inode,
  765. struct file *file)
  766. {
  767. return single_open(file, cnss_dynamic_feature_show,
  768. inode->i_private);
  769. }
  770. static const struct file_operations cnss_dynamic_feature_fops = {
  771. .read = seq_read,
  772. .write = cnss_dynamic_feature_write,
  773. .open = cnss_dynamic_feature_open,
  774. .owner = THIS_MODULE,
  775. .llseek = seq_lseek,
  776. };
  777. #ifdef CONFIG_DEBUG_FS
  778. #ifdef CONFIG_CNSS2_DEBUG
  779. static int cnss_create_debug_only_node(struct cnss_plat_data *plat_priv)
  780. {
  781. struct dentry *root_dentry = plat_priv->root_dentry;
  782. debugfs_create_file("dev_boot", 0600, root_dentry, plat_priv,
  783. &cnss_dev_boot_debug_fops);
  784. debugfs_create_file("reg_read", 0600, root_dentry, plat_priv,
  785. &cnss_reg_read_debug_fops);
  786. debugfs_create_file("reg_write", 0600, root_dentry, plat_priv,
  787. &cnss_reg_write_debug_fops);
  788. debugfs_create_file("runtime_pm", 0600, root_dentry, plat_priv,
  789. &cnss_runtime_pm_debug_fops);
  790. debugfs_create_file("control_params", 0600, root_dentry, plat_priv,
  791. &cnss_control_params_debug_fops);
  792. debugfs_create_file("dynamic_feature", 0600, root_dentry, plat_priv,
  793. &cnss_dynamic_feature_fops);
  794. return 0;
  795. }
  796. #else
  797. static int cnss_create_debug_only_node(struct cnss_plat_data *plat_priv)
  798. {
  799. return 0;
  800. }
  801. #endif
  802. int cnss_debugfs_create(struct cnss_plat_data *plat_priv)
  803. {
  804. int ret = 0;
  805. struct dentry *root_dentry;
  806. root_dentry = debugfs_create_dir("cnss", 0);
  807. if (IS_ERR(root_dentry)) {
  808. ret = PTR_ERR(root_dentry);
  809. cnss_pr_err("Unable to create debugfs %d\n", ret);
  810. goto out;
  811. }
  812. plat_priv->root_dentry = root_dentry;
  813. debugfs_create_file("pin_connect_result", 0644, root_dentry, plat_priv,
  814. &cnss_pin_connect_fops);
  815. debugfs_create_file("stats", 0644, root_dentry, plat_priv,
  816. &cnss_stats_fops);
  817. cnss_create_debug_only_node(plat_priv);
  818. out:
  819. return ret;
  820. }
  821. void cnss_debugfs_destroy(struct cnss_plat_data *plat_priv)
  822. {
  823. debugfs_remove_recursive(plat_priv->root_dentry);
  824. }
  825. #else
  826. int cnss_debugfs_create(struct cnss_plat_data *plat_priv)
  827. {
  828. plat_priv->root_dentry = NULL;
  829. return 0;
  830. }
  831. void cnss_debugfs_destroy(struct cnss_plat_data *plat_priv)
  832. {
  833. }
  834. #endif
  835. #if IS_ENABLED(CONFIG_IPC_LOGGING)
  836. void cnss_debug_ipc_log_print(void *log_ctx, char *process, const char *fn,
  837. const char *log_level, char *fmt, ...)
  838. {
  839. struct va_format vaf;
  840. va_list va_args;
  841. va_start(va_args, fmt);
  842. vaf.fmt = fmt;
  843. vaf.va = &va_args;
  844. if (log_level)
  845. printk("%scnss: %pV", log_level, &vaf);
  846. ipc_log_string(log_ctx, "[%s] %s: %pV", process, fn, &vaf);
  847. va_end(va_args);
  848. }
  849. static int cnss_ipc_logging_init(void)
  850. {
  851. cnss_ipc_log_context = ipc_log_context_create(CNSS_IPC_LOG_PAGES,
  852. "cnss", 0);
  853. if (!cnss_ipc_log_context) {
  854. cnss_pr_err("Unable to create IPC log context\n");
  855. return -EINVAL;
  856. }
  857. cnss_ipc_log_long_context = ipc_log_context_create(CNSS_IPC_LOG_PAGES,
  858. "cnss-long", 0);
  859. if (!cnss_ipc_log_long_context) {
  860. cnss_pr_err("Unable to create IPC long log context\n");
  861. ipc_log_context_destroy(cnss_ipc_log_context);
  862. return -EINVAL;
  863. }
  864. return 0;
  865. }
  866. static void cnss_ipc_logging_deinit(void)
  867. {
  868. if (cnss_ipc_log_long_context) {
  869. ipc_log_context_destroy(cnss_ipc_log_long_context);
  870. cnss_ipc_log_long_context = NULL;
  871. }
  872. if (cnss_ipc_log_context) {
  873. ipc_log_context_destroy(cnss_ipc_log_context);
  874. cnss_ipc_log_context = NULL;
  875. }
  876. }
  877. #else
  878. static int cnss_ipc_logging_init(void) { return 0; }
  879. static void cnss_ipc_logging_deinit(void) {}
  880. void cnss_debug_ipc_log_print(void *log_ctx, char *process, const char *fn,
  881. const char *log_level, char *fmt, ...)
  882. {
  883. struct va_format vaf;
  884. va_list va_args;
  885. va_start(va_args, fmt);
  886. vaf.fmt = fmt;
  887. vaf.va = &va_args;
  888. if (log_level)
  889. printk("%scnss: %pV", log_level, &vaf);
  890. va_end(va_args);
  891. }
  892. #endif
  893. int cnss_debug_init(void)
  894. {
  895. return cnss_ipc_logging_init();
  896. }
  897. void cnss_debug_deinit(void)
  898. {
  899. cnss_ipc_logging_deinit();
  900. }