hal_be_generic_api.h 51 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_BE_GENERIC_API_H_
  20. #define _HAL_BE_GENERIC_API_H_
  21. #include <hal_be_hw_headers.h>
  22. #include "hal_be_tx.h"
  23. #include "hal_be_reo.h"
  24. #include <hal_api_mon.h>
  25. #include <hal_generic_api.h>
  26. /**
  27. * hal_tx_comp_get_status() - TQM Release reason
  28. * @hal_desc: completion ring Tx status
  29. *
  30. * This function will parse the WBM completion descriptor and populate in
  31. * HAL structure
  32. *
  33. * Return: none
  34. */
  35. static inline void
  36. hal_tx_comp_get_status_generic_be(void *desc, void *ts1,
  37. struct hal_soc *hal)
  38. {
  39. uint8_t rate_stats_valid = 0;
  40. uint32_t rate_stats = 0;
  41. struct hal_tx_completion_status *ts =
  42. (struct hal_tx_completion_status *)ts1;
  43. ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  44. TQM_STATUS_NUMBER);
  45. ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  46. ACK_FRAME_RSSI);
  47. ts->first_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  48. FIRST_MSDU);
  49. ts->last_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  50. LAST_MSDU);
  51. #if 0
  52. // TODO - This has to be calculated form first and last msdu
  53. ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc,
  54. WBM2SW_COMPLETION_RING_TX,
  55. MSDU_PART_OF_AMSDU);
  56. #endif
  57. ts->peer_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  58. SW_PEER_ID);
  59. ts->tid = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, TID);
  60. ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  61. TRANSMIT_COUNT);
  62. rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS);
  63. rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO,
  64. TX_RATE_STATS_INFO_VALID, rate_stats);
  65. ts->valid = rate_stats_valid;
  66. if (rate_stats_valid) {
  67. ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_BW,
  68. rate_stats);
  69. ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO,
  70. TRANSMIT_PKT_TYPE, rate_stats);
  71. ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO,
  72. TRANSMIT_STBC, rate_stats);
  73. ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_LDPC,
  74. rate_stats);
  75. ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_SGI,
  76. rate_stats);
  77. ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_MCS,
  78. rate_stats);
  79. ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO, OFDMA_TRANSMISSION,
  80. rate_stats);
  81. ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO, TONES_IN_RU,
  82. rate_stats);
  83. }
  84. ts->release_src = hal_tx_comp_get_buffer_source_generic_be(desc);
  85. ts->status = hal_tx_comp_get_release_reason(
  86. desc,
  87. hal_soc_to_hal_soc_handle(hal));
  88. ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6,
  89. TX_RATE_STATS_INFO_TX_RATE_STATS);
  90. }
  91. #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX)
  92. /**
  93. * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL
  94. * tlv_tag: Taf of the TLVs
  95. * rx_tlv: the pointer to the TLVs
  96. * @ppdu_info: pointer to ppdu_info
  97. *
  98. * Return: true if the tlv is handled, false if not
  99. */
  100. static inline bool
  101. hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv,
  102. struct hal_rx_ppdu_info *ppdu_info)
  103. {
  104. uint32_t value;
  105. switch (tlv_tag) {
  106. case WIFIPHYRX_HE_SIG_A_MU_UL_E:
  107. {
  108. uint8_t *he_sig_a_mu_ul_info =
  109. (uint8_t *)rx_tlv +
  110. HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL,
  111. HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS);
  112. ppdu_info->rx_status.he_flags = 1;
  113. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO,
  114. FORMAT_INDICATION);
  115. if (value == 0) {
  116. ppdu_info->rx_status.he_data1 =
  117. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  118. } else {
  119. ppdu_info->rx_status.he_data1 =
  120. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  121. }
  122. /* data1 */
  123. ppdu_info->rx_status.he_data1 |=
  124. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  125. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  126. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
  127. /* data2 */
  128. ppdu_info->rx_status.he_data2 |=
  129. QDF_MON_STATUS_TXOP_KNOWN;
  130. /*data3*/
  131. value = HAL_RX_GET(he_sig_a_mu_ul_info,
  132. HE_SIG_A_MU_UL_INFO, BSS_COLOR_ID);
  133. ppdu_info->rx_status.he_data3 = value;
  134. /* 1 for UL and 0 for DL */
  135. value = 1;
  136. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  137. ppdu_info->rx_status.he_data3 |= value;
  138. /*data4*/
  139. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO,
  140. SPATIAL_REUSE);
  141. ppdu_info->rx_status.he_data4 = value;
  142. /*data5*/
  143. value = HAL_RX_GET(he_sig_a_mu_ul_info,
  144. HE_SIG_A_MU_UL_INFO, TRANSMIT_BW);
  145. ppdu_info->rx_status.he_data5 = value;
  146. ppdu_info->rx_status.bw = value;
  147. /*data6*/
  148. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO,
  149. TXOP_DURATION);
  150. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  151. ppdu_info->rx_status.he_data6 |= value;
  152. return true;
  153. }
  154. default:
  155. return false;
  156. }
  157. }
  158. #else
  159. static inline bool
  160. hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv,
  161. struct hal_rx_ppdu_info *ppdu_info)
  162. {
  163. return false;
  164. }
  165. #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */
  166. #if defined(RX_PPDU_END_USER_STATS_OFDMA_INFO_VALID_OFFSET) && \
  167. defined(RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET)
  168. static inline void
  169. hal_rx_handle_mu_ul_info(void *rx_tlv,
  170. struct mon_rx_user_status *mon_rx_user_status)
  171. {
  172. mon_rx_user_status->mu_ul_user_v0_word0 =
  173. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  174. SW_RESPONSE_REFERENCE_PTR);
  175. mon_rx_user_status->mu_ul_user_v0_word1 =
  176. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  177. SW_RESPONSE_REFERENCE_PTR_EXT);
  178. }
  179. static inline void
  180. hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
  181. struct mon_rx_user_status *mon_rx_user_status)
  182. {
  183. uint32_t mpdu_ok_byte_count;
  184. uint32_t mpdu_err_byte_count;
  185. mpdu_ok_byte_count = HAL_RX_GET(rx_tlv,
  186. RX_PPDU_END_USER_STATS,
  187. MPDU_OK_BYTE_COUNT);
  188. mpdu_err_byte_count = HAL_RX_GET(rx_tlv,
  189. RX_PPDU_END_USER_STATS,
  190. MPDU_ERR_BYTE_COUNT);
  191. mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count;
  192. mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count;
  193. }
  194. #else
  195. static inline void
  196. hal_rx_handle_mu_ul_info(void *rx_tlv,
  197. struct mon_rx_user_status *mon_rx_user_status)
  198. {
  199. }
  200. static inline void
  201. hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
  202. struct mon_rx_user_status *mon_rx_user_status)
  203. {
  204. struct hal_rx_ppdu_info *ppdu_info =
  205. (struct hal_rx_ppdu_info *)ppduinfo;
  206. /* HKV1: doesn't support mpdu byte count */
  207. mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len;
  208. mon_rx_user_status->mpdu_err_byte_count = 0;
  209. }
  210. #endif
  211. static inline void
  212. hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, uint32_t user_id,
  213. struct mon_rx_user_status *mon_rx_user_status)
  214. {
  215. struct mon_rx_info *mon_rx_info;
  216. struct mon_rx_user_info *mon_rx_user_info;
  217. struct hal_rx_ppdu_info *ppdu_info =
  218. (struct hal_rx_ppdu_info *)ppduinfo;
  219. mon_rx_info = &ppdu_info->rx_info;
  220. mon_rx_user_info = &ppdu_info->rx_user_info[user_id];
  221. mon_rx_user_info->qos_control_info_valid =
  222. mon_rx_info->qos_control_info_valid;
  223. mon_rx_user_info->qos_control = mon_rx_info->qos_control;
  224. mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index;
  225. mon_rx_user_status->tid = ppdu_info->rx_status.tid;
  226. mon_rx_user_status->tcp_msdu_count =
  227. ppdu_info->rx_status.tcp_msdu_count;
  228. mon_rx_user_status->udp_msdu_count =
  229. ppdu_info->rx_status.udp_msdu_count;
  230. mon_rx_user_status->other_msdu_count =
  231. ppdu_info->rx_status.other_msdu_count;
  232. mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control;
  233. mon_rx_user_status->frame_control_info_valid =
  234. ppdu_info->rx_status.frame_control_info_valid;
  235. mon_rx_user_status->data_sequence_control_info_valid =
  236. ppdu_info->rx_status.data_sequence_control_info_valid;
  237. mon_rx_user_status->first_data_seq_ctrl =
  238. ppdu_info->rx_status.first_data_seq_ctrl;
  239. mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type;
  240. mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags;
  241. mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags;
  242. mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags;
  243. mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags;
  244. mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags;
  245. mon_rx_user_status->mpdu_cnt_fcs_ok =
  246. ppdu_info->com_info.mpdu_cnt_fcs_ok;
  247. mon_rx_user_status->mpdu_cnt_fcs_err =
  248. ppdu_info->com_info.mpdu_cnt_fcs_err;
  249. qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap,
  250. &ppdu_info->com_info.mpdu_fcs_ok_bitmap,
  251. HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
  252. sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0]));
  253. hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status);
  254. }
  255. #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, \
  256. ppdu_info, rssi_info_tlv) \
  257. { \
  258. ppdu_info->rx_status.rssi_chain[chain][0] = \
  259. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  260. RSSI_PRI20_CHAIN##chain); \
  261. ppdu_info->rx_status.rssi_chain[chain][1] = \
  262. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  263. RSSI_EXT20_CHAIN##chain); \
  264. ppdu_info->rx_status.rssi_chain[chain][2] = \
  265. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  266. RSSI_EXT40_LOW20_CHAIN##chain); \
  267. ppdu_info->rx_status.rssi_chain[chain][3] = \
  268. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  269. RSSI_EXT40_HIGH20_CHAIN##chain); \
  270. ppdu_info->rx_status.rssi_chain[chain][4] = \
  271. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  272. RSSI_EXT80_LOW20_CHAIN##chain); \
  273. ppdu_info->rx_status.rssi_chain[chain][5] = \
  274. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  275. RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \
  276. ppdu_info->rx_status.rssi_chain[chain][6] = \
  277. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  278. RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \
  279. ppdu_info->rx_status.rssi_chain[chain][7] = \
  280. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  281. RSSI_EXT80_HIGH20_CHAIN##chain); \
  282. } \
  283. #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \
  284. {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, ppdu_info, rssi_info_tlv) \
  285. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, ppdu_info, rssi_info_tlv) \
  286. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, ppdu_info, rssi_info_tlv) \
  287. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, ppdu_info, rssi_info_tlv) \
  288. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, ppdu_info, rssi_info_tlv) \
  289. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, ppdu_info, rssi_info_tlv) \
  290. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, ppdu_info, rssi_info_tlv) \
  291. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, ppdu_info, rssi_info_tlv)} \
  292. static inline uint32_t
  293. hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info,
  294. uint8_t *rssi_info_tlv)
  295. {
  296. // TODO - Find all these registers for kiwi
  297. #if 0
  298. HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv)
  299. #endif
  300. return 0;
  301. }
  302. #ifdef WLAN_TX_PKT_CAPTURE_ENH
  303. static inline void
  304. hal_get_qos_control(void *rx_tlv,
  305. struct hal_rx_ppdu_info *ppdu_info)
  306. {
  307. ppdu_info->rx_info.qos_control_info_valid =
  308. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  309. QOS_CONTROL_INFO_VALID);
  310. if (ppdu_info->rx_info.qos_control_info_valid)
  311. ppdu_info->rx_info.qos_control =
  312. HAL_RX_GET(rx_tlv,
  313. RX_PPDU_END_USER_STATS,
  314. QOS_CONTROL_FIELD);
  315. }
  316. static inline void
  317. hal_get_mac_addr1(uint8_t *rx_mpdu_start,
  318. struct hal_rx_ppdu_info *ppdu_info)
  319. {
  320. if ((ppdu_info->sw_frame_group_id
  321. == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) ||
  322. (ppdu_info->sw_frame_group_id ==
  323. HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) {
  324. ppdu_info->rx_info.mac_addr1_valid =
  325. HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start);
  326. *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] =
  327. HAL_RX_GET(rx_mpdu_start,
  328. RX_MPDU_INFO,
  329. MAC_ADDR_AD1_31_0);
  330. if (ppdu_info->sw_frame_group_id ==
  331. HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) {
  332. *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] =
  333. HAL_RX_GET(rx_mpdu_start,
  334. RX_MPDU_INFO,
  335. MAC_ADDR_AD1_47_32);
  336. }
  337. }
  338. }
  339. #else
  340. static inline void
  341. hal_get_qos_control(void *rx_tlv,
  342. struct hal_rx_ppdu_info *ppdu_info)
  343. {
  344. }
  345. static inline void
  346. hal_get_mac_addr1(uint8_t *rx_mpdu_start,
  347. struct hal_rx_ppdu_info *ppdu_info)
  348. {
  349. }
  350. #endif
  351. /**
  352. * hal_rx_status_get_tlv_info() - process receive info TLV
  353. * @rx_tlv_hdr: pointer to TLV header
  354. * @ppdu_info: pointer to ppdu_info
  355. *
  356. * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv
  357. */
  358. static inline uint32_t
  359. hal_rx_status_get_tlv_info_generic_be(void *rx_tlv_hdr, void *ppduinfo,
  360. hal_soc_handle_t hal_soc_hdl,
  361. qdf_nbuf_t nbuf)
  362. {
  363. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  364. uint32_t tlv_tag, user_id, tlv_len, value;
  365. uint8_t group_id = 0;
  366. uint8_t he_dcm = 0;
  367. uint8_t he_stbc = 0;
  368. uint16_t he_gi = 0;
  369. uint16_t he_ltf = 0;
  370. void *rx_tlv;
  371. bool unhandled = false;
  372. struct mon_rx_user_status *mon_rx_user_status;
  373. struct hal_rx_ppdu_info *ppdu_info =
  374. (struct hal_rx_ppdu_info *)ppduinfo;
  375. tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr);
  376. user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr);
  377. tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr);
  378. rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
  379. qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  380. rx_tlv, tlv_len);
  381. switch (tlv_tag) {
  382. case WIFIRX_PPDU_START_E:
  383. {
  384. if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id ==
  385. HAL_RX_GET(rx_tlv, RX_PPDU_START, PHY_PPDU_ID)))
  386. hal_err("Matching ppdu_id(%u) detected",
  387. ppdu_info->com_info.last_ppdu_id);
  388. /* Reset ppdu_info before processing the ppdu */
  389. qdf_mem_zero(ppdu_info,
  390. sizeof(struct hal_rx_ppdu_info));
  391. ppdu_info->com_info.last_ppdu_id =
  392. ppdu_info->com_info.ppdu_id =
  393. HAL_RX_GET(rx_tlv, RX_PPDU_START,
  394. PHY_PPDU_ID);
  395. /* channel number is set in PHY meta data */
  396. ppdu_info->rx_status.chan_num =
  397. (HAL_RX_GET(rx_tlv, RX_PPDU_START,
  398. SW_PHY_META_DATA) & 0x0000FFFF);
  399. ppdu_info->rx_status.chan_freq =
  400. (HAL_RX_GET(rx_tlv, RX_PPDU_START,
  401. SW_PHY_META_DATA) & 0xFFFF0000) >> 16;
  402. if (ppdu_info->rx_status.chan_num &&
  403. ppdu_info->rx_status.chan_freq) {
  404. ppdu_info->rx_status.chan_freq =
  405. hal_rx_radiotap_num_to_freq(
  406. ppdu_info->rx_status.chan_num,
  407. ppdu_info->rx_status.chan_freq);
  408. }
  409. ppdu_info->com_info.ppdu_timestamp =
  410. HAL_RX_GET(rx_tlv, RX_PPDU_START,
  411. PPDU_START_TIMESTAMP_31_0);
  412. ppdu_info->rx_status.ppdu_timestamp =
  413. ppdu_info->com_info.ppdu_timestamp;
  414. ppdu_info->rx_state = HAL_RX_MON_PPDU_START;
  415. break;
  416. }
  417. case WIFIRX_PPDU_START_USER_INFO_E:
  418. break;
  419. case WIFIRX_PPDU_END_E:
  420. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  421. "[%s][%d] ppdu_end_e len=%d",
  422. __func__, __LINE__, tlv_len);
  423. /* This is followed by sub-TLVs of PPDU_END */
  424. ppdu_info->rx_state = HAL_RX_MON_PPDU_END;
  425. break;
  426. case WIFIPHYRX_LOCATION_E:
  427. hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info);
  428. break;
  429. case WIFIRXPCU_PPDU_END_INFO_E:
  430. ppdu_info->rx_status.rx_antenna =
  431. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, RX_ANTENNA);
  432. ppdu_info->rx_status.tsft =
  433. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO,
  434. WB_TIMESTAMP_UPPER_32);
  435. ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) |
  436. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO,
  437. WB_TIMESTAMP_LOWER_32);
  438. ppdu_info->rx_status.duration =
  439. HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8,
  440. RX_PPDU_DURATION);
  441. hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info);
  442. break;
  443. /*
  444. * WIFIRX_PPDU_END_USER_STATS_E comes for each user received.
  445. * for MU, based on num users we see this tlv that many times.
  446. */
  447. case WIFIRX_PPDU_END_USER_STATS_E:
  448. {
  449. unsigned long tid = 0;
  450. uint16_t seq = 0;
  451. ppdu_info->rx_status.ast_index =
  452. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  453. AST_INDEX);
  454. tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  455. RECEIVED_QOS_DATA_TID_BITMAP);
  456. ppdu_info->rx_status.tid = qdf_find_first_bit(&tid,
  457. sizeof(tid) * 8);
  458. if (ppdu_info->rx_status.tid == (sizeof(tid) * 8))
  459. ppdu_info->rx_status.tid = HAL_TID_INVALID;
  460. ppdu_info->rx_status.tcp_msdu_count =
  461. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  462. TCP_MSDU_COUNT) +
  463. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  464. TCP_ACK_MSDU_COUNT);
  465. ppdu_info->rx_status.udp_msdu_count =
  466. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  467. UDP_MSDU_COUNT);
  468. ppdu_info->rx_status.other_msdu_count =
  469. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  470. OTHER_MSDU_COUNT);
  471. if (ppdu_info->sw_frame_group_id
  472. != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) {
  473. ppdu_info->rx_status.frame_control_info_valid =
  474. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  475. FRAME_CONTROL_INFO_VALID);
  476. if (ppdu_info->rx_status.frame_control_info_valid)
  477. ppdu_info->rx_status.frame_control =
  478. HAL_RX_GET(rx_tlv,
  479. RX_PPDU_END_USER_STATS,
  480. FRAME_CONTROL_FIELD);
  481. hal_get_qos_control(rx_tlv, ppdu_info);
  482. }
  483. ppdu_info->rx_status.data_sequence_control_info_valid =
  484. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  485. DATA_SEQUENCE_CONTROL_INFO_VALID);
  486. seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  487. FIRST_DATA_SEQ_CTRL);
  488. if (ppdu_info->rx_status.data_sequence_control_info_valid)
  489. ppdu_info->rx_status.first_data_seq_ctrl = seq;
  490. ppdu_info->rx_status.preamble_type =
  491. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  492. HT_CONTROL_FIELD_PKT_TYPE);
  493. switch (ppdu_info->rx_status.preamble_type) {
  494. case HAL_RX_PKT_TYPE_11N:
  495. ppdu_info->rx_status.ht_flags = 1;
  496. ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT;
  497. break;
  498. case HAL_RX_PKT_TYPE_11AC:
  499. ppdu_info->rx_status.vht_flags = 1;
  500. break;
  501. case HAL_RX_PKT_TYPE_11AX:
  502. ppdu_info->rx_status.he_flags = 1;
  503. break;
  504. default:
  505. break;
  506. }
  507. ppdu_info->com_info.mpdu_cnt_fcs_ok =
  508. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  509. MPDU_CNT_FCS_OK);
  510. ppdu_info->com_info.mpdu_cnt_fcs_err =
  511. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  512. MPDU_CNT_FCS_ERR);
  513. if ((ppdu_info->com_info.mpdu_cnt_fcs_ok |
  514. ppdu_info->com_info.mpdu_cnt_fcs_err) > 1)
  515. ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG;
  516. else
  517. ppdu_info->rx_status.rs_flags &=
  518. (~IEEE80211_AMPDU_FLAG);
  519. ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] =
  520. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  521. FCS_OK_BITMAP_31_0);
  522. ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] =
  523. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  524. FCS_OK_BITMAP_63_32);
  525. if (user_id < HAL_MAX_UL_MU_USERS) {
  526. mon_rx_user_status =
  527. &ppdu_info->rx_user_status[user_id];
  528. hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status);
  529. ppdu_info->com_info.num_users++;
  530. hal_rx_populate_mu_user_info(rx_tlv, ppdu_info,
  531. user_id,
  532. mon_rx_user_status);
  533. }
  534. break;
  535. }
  536. case WIFIRX_PPDU_END_USER_STATS_EXT_E:
  537. ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] =
  538. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  539. FCS_OK_BITMAP_95_64);
  540. ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] =
  541. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  542. FCS_OK_BITMAP_127_96);
  543. ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] =
  544. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  545. FCS_OK_BITMAP_159_128);
  546. ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] =
  547. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  548. FCS_OK_BITMAP_191_160);
  549. ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] =
  550. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  551. FCS_OK_BITMAP_223_192);
  552. ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] =
  553. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  554. FCS_OK_BITMAP_255_224);
  555. break;
  556. case WIFIRX_PPDU_END_STATUS_DONE_E:
  557. return HAL_TLV_STATUS_PPDU_DONE;
  558. case WIFIDUMMY_E:
  559. return HAL_TLV_STATUS_BUF_DONE;
  560. case WIFIPHYRX_HT_SIG_E:
  561. {
  562. uint8_t *ht_sig_info = (uint8_t *)rx_tlv +
  563. HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0,
  564. HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS);
  565. value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO,
  566. FEC_CODING);
  567. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  568. 1 : 0;
  569. ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info,
  570. HT_SIG_INFO, MCS);
  571. ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs;
  572. ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info,
  573. HT_SIG_INFO, CBW);
  574. ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info,
  575. HT_SIG_INFO, SHORT_GI);
  576. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  577. ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >>
  578. HT_SIG_SU_NSS_SHIFT) + 1;
  579. ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1);
  580. break;
  581. }
  582. case WIFIPHYRX_L_SIG_B_E:
  583. {
  584. uint8_t *l_sig_b_info = (uint8_t *)rx_tlv +
  585. HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0,
  586. L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS);
  587. value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO, RATE);
  588. ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info);
  589. switch (value) {
  590. case 1:
  591. ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS;
  592. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3;
  593. break;
  594. case 2:
  595. ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS;
  596. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2;
  597. break;
  598. case 3:
  599. ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS;
  600. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1;
  601. break;
  602. case 4:
  603. ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS;
  604. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0;
  605. break;
  606. case 5:
  607. ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS;
  608. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6;
  609. break;
  610. case 6:
  611. ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS;
  612. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5;
  613. break;
  614. case 7:
  615. ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS;
  616. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4;
  617. break;
  618. default:
  619. break;
  620. }
  621. ppdu_info->rx_status.cck_flag = 1;
  622. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  623. break;
  624. }
  625. case WIFIPHYRX_L_SIG_A_E:
  626. {
  627. uint8_t *l_sig_a_info = (uint8_t *)rx_tlv +
  628. HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0,
  629. L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS);
  630. value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO, RATE);
  631. ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info);
  632. switch (value) {
  633. case 8:
  634. ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS;
  635. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0;
  636. break;
  637. case 9:
  638. ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS;
  639. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1;
  640. break;
  641. case 10:
  642. ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS;
  643. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2;
  644. break;
  645. case 11:
  646. ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS;
  647. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3;
  648. break;
  649. case 12:
  650. ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS;
  651. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4;
  652. break;
  653. case 13:
  654. ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS;
  655. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5;
  656. break;
  657. case 14:
  658. ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS;
  659. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6;
  660. break;
  661. case 15:
  662. ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS;
  663. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7;
  664. break;
  665. default:
  666. break;
  667. }
  668. ppdu_info->rx_status.ofdm_flag = 1;
  669. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  670. break;
  671. }
  672. case WIFIPHYRX_VHT_SIG_A_E:
  673. {
  674. uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv +
  675. HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0,
  676. VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS);
  677. value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO,
  678. SU_MU_CODING);
  679. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  680. 1 : 0;
  681. group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO, GROUP_ID);
  682. ppdu_info->rx_status.vht_flag_values5 = group_id;
  683. ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info,
  684. VHT_SIG_A_INFO, MCS);
  685. ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info,
  686. VHT_SIG_A_INFO, GI_SETTING);
  687. switch (hal->target_type) {
  688. case TARGET_TYPE_QCA8074:
  689. case TARGET_TYPE_QCA8074V2:
  690. case TARGET_TYPE_QCA6018:
  691. case TARGET_TYPE_QCA5018:
  692. case TARGET_TYPE_QCN9000:
  693. case TARGET_TYPE_QCN6122:
  694. #ifdef QCA_WIFI_QCA6390
  695. case TARGET_TYPE_QCA6390:
  696. #endif
  697. ppdu_info->rx_status.is_stbc =
  698. HAL_RX_GET(vht_sig_a_info,
  699. VHT_SIG_A_INFO, STBC);
  700. value = HAL_RX_GET(vht_sig_a_info,
  701. VHT_SIG_A_INFO, N_STS);
  702. value = value & VHT_SIG_SU_NSS_MASK;
  703. if (ppdu_info->rx_status.is_stbc && (value > 0))
  704. value = ((value + 1) >> 1) - 1;
  705. ppdu_info->rx_status.nss =
  706. ((value & VHT_SIG_SU_NSS_MASK) + 1);
  707. break;
  708. case TARGET_TYPE_QCA6290:
  709. #if !defined(QCA_WIFI_QCA6290_11AX)
  710. ppdu_info->rx_status.is_stbc =
  711. HAL_RX_GET(vht_sig_a_info,
  712. VHT_SIG_A_INFO, STBC);
  713. value = HAL_RX_GET(vht_sig_a_info,
  714. VHT_SIG_A_INFO, N_STS);
  715. value = value & VHT_SIG_SU_NSS_MASK;
  716. if (ppdu_info->rx_status.is_stbc && (value > 0))
  717. value = ((value + 1) >> 1) - 1;
  718. ppdu_info->rx_status.nss =
  719. ((value & VHT_SIG_SU_NSS_MASK) + 1);
  720. #else
  721. ppdu_info->rx_status.nss = 0;
  722. #endif
  723. break;
  724. case TARGET_TYPE_QCA6490:
  725. case TARGET_TYPE_QCA6750:
  726. case TARGET_TYPE_KIWI:
  727. ppdu_info->rx_status.nss = 0;
  728. break;
  729. default:
  730. break;
  731. }
  732. ppdu_info->rx_status.vht_flag_values3[0] =
  733. (((ppdu_info->rx_status.mcs) << 4)
  734. | ppdu_info->rx_status.nss);
  735. ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info,
  736. VHT_SIG_A_INFO, BANDWIDTH);
  737. ppdu_info->rx_status.vht_flag_values2 =
  738. ppdu_info->rx_status.bw;
  739. ppdu_info->rx_status.vht_flag_values4 =
  740. HAL_RX_GET(vht_sig_a_info,
  741. VHT_SIG_A_INFO, SU_MU_CODING);
  742. ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info,
  743. VHT_SIG_A_INFO, BEAMFORMED);
  744. if (group_id == 0 || group_id == 63)
  745. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  746. else
  747. ppdu_info->rx_status.reception_type =
  748. HAL_RX_TYPE_MU_MIMO;
  749. break;
  750. }
  751. case WIFIPHYRX_HE_SIG_A_SU_E:
  752. {
  753. uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv +
  754. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0,
  755. HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS);
  756. ppdu_info->rx_status.he_flags = 1;
  757. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  758. FORMAT_INDICATION);
  759. if (value == 0) {
  760. ppdu_info->rx_status.he_data1 =
  761. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  762. } else {
  763. ppdu_info->rx_status.he_data1 =
  764. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  765. }
  766. /* data1 */
  767. ppdu_info->rx_status.he_data1 |=
  768. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  769. QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN |
  770. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  771. QDF_MON_STATUS_HE_MCS_KNOWN |
  772. QDF_MON_STATUS_HE_DCM_KNOWN |
  773. QDF_MON_STATUS_HE_CODING_KNOWN |
  774. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  775. QDF_MON_STATUS_HE_STBC_KNOWN |
  776. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  777. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  778. /* data2 */
  779. ppdu_info->rx_status.he_data2 =
  780. QDF_MON_STATUS_HE_GI_KNOWN;
  781. ppdu_info->rx_status.he_data2 |=
  782. QDF_MON_STATUS_TXBF_KNOWN |
  783. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  784. QDF_MON_STATUS_TXOP_KNOWN |
  785. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  786. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  787. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  788. /* data3 */
  789. value = HAL_RX_GET(he_sig_a_su_info,
  790. HE_SIG_A_SU_INFO, BSS_COLOR_ID);
  791. ppdu_info->rx_status.he_data3 = value;
  792. value = HAL_RX_GET(he_sig_a_su_info,
  793. HE_SIG_A_SU_INFO, BEAM_CHANGE);
  794. value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT;
  795. ppdu_info->rx_status.he_data3 |= value;
  796. value = HAL_RX_GET(he_sig_a_su_info,
  797. HE_SIG_A_SU_INFO, DL_UL_FLAG);
  798. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  799. ppdu_info->rx_status.he_data3 |= value;
  800. value = HAL_RX_GET(he_sig_a_su_info,
  801. HE_SIG_A_SU_INFO, TRANSMIT_MCS);
  802. ppdu_info->rx_status.mcs = value;
  803. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  804. ppdu_info->rx_status.he_data3 |= value;
  805. value = HAL_RX_GET(he_sig_a_su_info,
  806. HE_SIG_A_SU_INFO, DCM);
  807. he_dcm = value;
  808. value = value << QDF_MON_STATUS_DCM_SHIFT;
  809. ppdu_info->rx_status.he_data3 |= value;
  810. value = HAL_RX_GET(he_sig_a_su_info,
  811. HE_SIG_A_SU_INFO, CODING);
  812. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  813. 1 : 0;
  814. value = value << QDF_MON_STATUS_CODING_SHIFT;
  815. ppdu_info->rx_status.he_data3 |= value;
  816. value = HAL_RX_GET(he_sig_a_su_info,
  817. HE_SIG_A_SU_INFO,
  818. LDPC_EXTRA_SYMBOL);
  819. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  820. ppdu_info->rx_status.he_data3 |= value;
  821. value = HAL_RX_GET(he_sig_a_su_info,
  822. HE_SIG_A_SU_INFO, STBC);
  823. he_stbc = value;
  824. value = value << QDF_MON_STATUS_STBC_SHIFT;
  825. ppdu_info->rx_status.he_data3 |= value;
  826. /* data4 */
  827. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  828. SPATIAL_REUSE);
  829. ppdu_info->rx_status.he_data4 = value;
  830. /* data5 */
  831. value = HAL_RX_GET(he_sig_a_su_info,
  832. HE_SIG_A_SU_INFO, TRANSMIT_BW);
  833. ppdu_info->rx_status.he_data5 = value;
  834. ppdu_info->rx_status.bw = value;
  835. value = HAL_RX_GET(he_sig_a_su_info,
  836. HE_SIG_A_SU_INFO, CP_LTF_SIZE);
  837. switch (value) {
  838. case 0:
  839. he_gi = HE_GI_0_8;
  840. he_ltf = HE_LTF_1_X;
  841. break;
  842. case 1:
  843. he_gi = HE_GI_0_8;
  844. he_ltf = HE_LTF_2_X;
  845. break;
  846. case 2:
  847. he_gi = HE_GI_1_6;
  848. he_ltf = HE_LTF_2_X;
  849. break;
  850. case 3:
  851. if (he_dcm && he_stbc) {
  852. he_gi = HE_GI_0_8;
  853. he_ltf = HE_LTF_4_X;
  854. } else {
  855. he_gi = HE_GI_3_2;
  856. he_ltf = HE_LTF_4_X;
  857. }
  858. break;
  859. }
  860. ppdu_info->rx_status.sgi = he_gi;
  861. ppdu_info->rx_status.ltf_size = he_ltf;
  862. hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf);
  863. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  864. ppdu_info->rx_status.he_data5 |= value;
  865. value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
  866. ppdu_info->rx_status.he_data5 |= value;
  867. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS);
  868. value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  869. ppdu_info->rx_status.he_data5 |= value;
  870. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  871. PACKET_EXTENSION_A_FACTOR);
  872. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  873. ppdu_info->rx_status.he_data5 |= value;
  874. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, TXBF);
  875. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  876. ppdu_info->rx_status.he_data5 |= value;
  877. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  878. PACKET_EXTENSION_PE_DISAMBIGUITY);
  879. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  880. ppdu_info->rx_status.he_data5 |= value;
  881. /* data6 */
  882. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS);
  883. value++;
  884. ppdu_info->rx_status.nss = value;
  885. ppdu_info->rx_status.he_data6 = value;
  886. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  887. DOPPLER_INDICATION);
  888. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  889. ppdu_info->rx_status.he_data6 |= value;
  890. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  891. TXOP_DURATION);
  892. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  893. ppdu_info->rx_status.he_data6 |= value;
  894. ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info,
  895. HE_SIG_A_SU_INFO, TXBF);
  896. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  897. break;
  898. }
  899. case WIFIPHYRX_HE_SIG_A_MU_DL_E:
  900. {
  901. uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv +
  902. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0,
  903. HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS);
  904. ppdu_info->rx_status.he_mu_flags = 1;
  905. /* HE Flags */
  906. /*data1*/
  907. ppdu_info->rx_status.he_data1 =
  908. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  909. ppdu_info->rx_status.he_data1 |=
  910. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  911. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  912. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  913. QDF_MON_STATUS_HE_STBC_KNOWN |
  914. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  915. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  916. /* data2 */
  917. ppdu_info->rx_status.he_data2 =
  918. QDF_MON_STATUS_HE_GI_KNOWN;
  919. ppdu_info->rx_status.he_data2 |=
  920. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  921. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  922. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  923. QDF_MON_STATUS_TXOP_KNOWN |
  924. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  925. /*data3*/
  926. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  927. HE_SIG_A_MU_DL_INFO, BSS_COLOR_ID);
  928. ppdu_info->rx_status.he_data3 = value;
  929. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  930. HE_SIG_A_MU_DL_INFO, DL_UL_FLAG);
  931. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  932. ppdu_info->rx_status.he_data3 |= value;
  933. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  934. HE_SIG_A_MU_DL_INFO,
  935. LDPC_EXTRA_SYMBOL);
  936. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  937. ppdu_info->rx_status.he_data3 |= value;
  938. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  939. HE_SIG_A_MU_DL_INFO, STBC);
  940. he_stbc = value;
  941. value = value << QDF_MON_STATUS_STBC_SHIFT;
  942. ppdu_info->rx_status.he_data3 |= value;
  943. /*data4*/
  944. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  945. SPATIAL_REUSE);
  946. ppdu_info->rx_status.he_data4 = value;
  947. /*data5*/
  948. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  949. HE_SIG_A_MU_DL_INFO, TRANSMIT_BW);
  950. ppdu_info->rx_status.he_data5 = value;
  951. ppdu_info->rx_status.bw = value;
  952. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  953. HE_SIG_A_MU_DL_INFO, CP_LTF_SIZE);
  954. switch (value) {
  955. case 0:
  956. he_gi = HE_GI_0_8;
  957. he_ltf = HE_LTF_4_X;
  958. break;
  959. case 1:
  960. he_gi = HE_GI_0_8;
  961. he_ltf = HE_LTF_2_X;
  962. break;
  963. case 2:
  964. he_gi = HE_GI_1_6;
  965. he_ltf = HE_LTF_2_X;
  966. break;
  967. case 3:
  968. he_gi = HE_GI_3_2;
  969. he_ltf = HE_LTF_4_X;
  970. break;
  971. }
  972. ppdu_info->rx_status.sgi = he_gi;
  973. ppdu_info->rx_status.ltf_size = he_ltf;
  974. hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf);
  975. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  976. ppdu_info->rx_status.he_data5 |= value;
  977. value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
  978. ppdu_info->rx_status.he_data5 |= value;
  979. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  980. HE_SIG_A_MU_DL_INFO, NUM_LTF_SYMBOLS);
  981. value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  982. ppdu_info->rx_status.he_data5 |= value;
  983. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  984. PACKET_EXTENSION_A_FACTOR);
  985. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  986. ppdu_info->rx_status.he_data5 |= value;
  987. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  988. PACKET_EXTENSION_PE_DISAMBIGUITY);
  989. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  990. ppdu_info->rx_status.he_data5 |= value;
  991. /*data6*/
  992. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  993. DOPPLER_INDICATION);
  994. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  995. ppdu_info->rx_status.he_data6 |= value;
  996. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  997. TXOP_DURATION);
  998. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  999. ppdu_info->rx_status.he_data6 |= value;
  1000. /* HE-MU Flags */
  1001. /* HE-MU-flags1 */
  1002. ppdu_info->rx_status.he_flags1 =
  1003. QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  1004. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  1005. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
  1006. QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
  1007. QDF_MON_STATUS_RU_0_KNOWN;
  1008. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1009. HE_SIG_A_MU_DL_INFO, MCS_OF_SIG_B);
  1010. ppdu_info->rx_status.he_flags1 |= value;
  1011. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1012. HE_SIG_A_MU_DL_INFO, DCM_OF_SIG_B);
  1013. value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT;
  1014. ppdu_info->rx_status.he_flags1 |= value;
  1015. /* HE-MU-flags2 */
  1016. ppdu_info->rx_status.he_flags2 =
  1017. QDF_MON_STATUS_BW_KNOWN;
  1018. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1019. HE_SIG_A_MU_DL_INFO, TRANSMIT_BW);
  1020. ppdu_info->rx_status.he_flags2 |= value;
  1021. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1022. HE_SIG_A_MU_DL_INFO, COMP_MODE_SIG_B);
  1023. value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  1024. ppdu_info->rx_status.he_flags2 |= value;
  1025. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1026. HE_SIG_A_MU_DL_INFO, NUM_SIG_B_SYMBOLS);
  1027. value = value - 1;
  1028. value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
  1029. ppdu_info->rx_status.he_flags2 |= value;
  1030. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
  1031. break;
  1032. }
  1033. case WIFIPHYRX_HE_SIG_B1_MU_E:
  1034. {
  1035. uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv +
  1036. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0,
  1037. HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS);
  1038. ppdu_info->rx_status.he_sig_b_common_known |=
  1039. QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0;
  1040. /* TODO: Check on the availability of other fields in
  1041. * sig_b_common
  1042. */
  1043. value = HAL_RX_GET(he_sig_b1_mu_info,
  1044. HE_SIG_B1_MU_INFO, RU_ALLOCATION);
  1045. ppdu_info->rx_status.he_RU[0] = value;
  1046. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
  1047. break;
  1048. }
  1049. case WIFIPHYRX_HE_SIG_B2_MU_E:
  1050. {
  1051. uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv +
  1052. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0,
  1053. HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS);
  1054. /*
  1055. * Not all "HE" fields can be updated from
  1056. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  1057. * to populate rest of the "HE" fields for MU scenarios.
  1058. */
  1059. /* HE-data1 */
  1060. ppdu_info->rx_status.he_data1 |=
  1061. QDF_MON_STATUS_HE_MCS_KNOWN |
  1062. QDF_MON_STATUS_HE_CODING_KNOWN;
  1063. /* HE-data2 */
  1064. /* HE-data3 */
  1065. value = HAL_RX_GET(he_sig_b2_mu_info,
  1066. HE_SIG_B2_MU_INFO, STA_MCS);
  1067. ppdu_info->rx_status.mcs = value;
  1068. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1069. ppdu_info->rx_status.he_data3 |= value;
  1070. value = HAL_RX_GET(he_sig_b2_mu_info,
  1071. HE_SIG_B2_MU_INFO, STA_CODING);
  1072. value = value << QDF_MON_STATUS_CODING_SHIFT;
  1073. ppdu_info->rx_status.he_data3 |= value;
  1074. /* HE-data4 */
  1075. value = HAL_RX_GET(he_sig_b2_mu_info,
  1076. HE_SIG_B2_MU_INFO, STA_ID);
  1077. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  1078. ppdu_info->rx_status.he_data4 |= value;
  1079. /* HE-data5 */
  1080. /* HE-data6 */
  1081. value = HAL_RX_GET(he_sig_b2_mu_info,
  1082. HE_SIG_B2_MU_INFO, NSTS);
  1083. /* value n indicates n+1 spatial streams */
  1084. value++;
  1085. ppdu_info->rx_status.nss = value;
  1086. ppdu_info->rx_status.he_data6 |= value;
  1087. break;
  1088. }
  1089. case WIFIPHYRX_HE_SIG_B2_OFDMA_E:
  1090. {
  1091. uint8_t *he_sig_b2_ofdma_info =
  1092. (uint8_t *)rx_tlv +
  1093. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0,
  1094. HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS);
  1095. /*
  1096. * Not all "HE" fields can be updated from
  1097. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  1098. * to populate rest of "HE" fields for MU OFDMA scenarios.
  1099. */
  1100. /* HE-data1 */
  1101. ppdu_info->rx_status.he_data1 |=
  1102. QDF_MON_STATUS_HE_MCS_KNOWN |
  1103. QDF_MON_STATUS_HE_DCM_KNOWN |
  1104. QDF_MON_STATUS_HE_CODING_KNOWN;
  1105. /* HE-data2 */
  1106. ppdu_info->rx_status.he_data2 |=
  1107. QDF_MON_STATUS_TXBF_KNOWN;
  1108. /* HE-data3 */
  1109. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1110. HE_SIG_B2_OFDMA_INFO, STA_MCS);
  1111. ppdu_info->rx_status.mcs = value;
  1112. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1113. ppdu_info->rx_status.he_data3 |= value;
  1114. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1115. HE_SIG_B2_OFDMA_INFO, STA_DCM);
  1116. he_dcm = value;
  1117. value = value << QDF_MON_STATUS_DCM_SHIFT;
  1118. ppdu_info->rx_status.he_data3 |= value;
  1119. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1120. HE_SIG_B2_OFDMA_INFO, STA_CODING);
  1121. value = value << QDF_MON_STATUS_CODING_SHIFT;
  1122. ppdu_info->rx_status.he_data3 |= value;
  1123. /* HE-data4 */
  1124. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1125. HE_SIG_B2_OFDMA_INFO, STA_ID);
  1126. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  1127. ppdu_info->rx_status.he_data4 |= value;
  1128. /* HE-data5 */
  1129. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1130. HE_SIG_B2_OFDMA_INFO, TXBF);
  1131. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  1132. ppdu_info->rx_status.he_data5 |= value;
  1133. /* HE-data6 */
  1134. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1135. HE_SIG_B2_OFDMA_INFO, NSTS);
  1136. /* value n indicates n+1 spatial streams */
  1137. value++;
  1138. ppdu_info->rx_status.nss = value;
  1139. ppdu_info->rx_status.he_data6 |= value;
  1140. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA;
  1141. break;
  1142. }
  1143. case WIFIPHYRX_RSSI_LEGACY_E:
  1144. {
  1145. uint8_t reception_type;
  1146. int8_t rssi_value;
  1147. uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv +
  1148. HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19,
  1149. RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS);
  1150. ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv,
  1151. PHYRX_RSSI_LEGACY, RSSI_COMB);
  1152. ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv);
  1153. ppdu_info->rx_status.he_re = 0;
  1154. reception_type = HAL_RX_GET(rx_tlv,
  1155. PHYRX_RSSI_LEGACY,
  1156. RECEPTION_TYPE);
  1157. switch (reception_type) {
  1158. case QDF_RECEPTION_TYPE_ULOFMDA:
  1159. ppdu_info->rx_status.reception_type =
  1160. HAL_RX_TYPE_MU_OFDMA;
  1161. ppdu_info->rx_status.ulofdma_flag = 1;
  1162. ppdu_info->rx_status.he_data1 =
  1163. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  1164. break;
  1165. case QDF_RECEPTION_TYPE_ULMIMO:
  1166. ppdu_info->rx_status.reception_type =
  1167. HAL_RX_TYPE_MU_MIMO;
  1168. ppdu_info->rx_status.he_data1 =
  1169. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  1170. break;
  1171. default:
  1172. ppdu_info->rx_status.reception_type =
  1173. HAL_RX_TYPE_SU;
  1174. break;
  1175. }
  1176. hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv);
  1177. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1178. RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN0);
  1179. ppdu_info->rx_status.rssi[0] = rssi_value;
  1180. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1181. "RSSI_PRI20_CHAIN0: %d\n", rssi_value);
  1182. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1183. RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN1);
  1184. ppdu_info->rx_status.rssi[1] = rssi_value;
  1185. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1186. "RSSI_PRI20_CHAIN1: %d\n", rssi_value);
  1187. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1188. RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN2);
  1189. ppdu_info->rx_status.rssi[2] = rssi_value;
  1190. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1191. "RSSI_PRI20_CHAIN2: %d\n", rssi_value);
  1192. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1193. RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN3);
  1194. ppdu_info->rx_status.rssi[3] = rssi_value;
  1195. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1196. "RSSI_PRI20_CHAIN3: %d\n", rssi_value);
  1197. #ifdef DP_BE_NOTYET_WAR
  1198. // TODO - this is not preset for kiwi
  1199. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1200. RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN4);
  1201. ppdu_info->rx_status.rssi[4] = rssi_value;
  1202. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1203. "RSSI_PRI20_CHAIN4: %d\n", rssi_value);
  1204. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1205. RECEIVE_RSSI_INFO,
  1206. RSSI_PRI20_CHAIN5);
  1207. ppdu_info->rx_status.rssi[5] = rssi_value;
  1208. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1209. "RSSI_PRI20_CHAIN5: %d\n", rssi_value);
  1210. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1211. RECEIVE_RSSI_INFO,
  1212. RSSI_PRI20_CHAIN6);
  1213. ppdu_info->rx_status.rssi[6] = rssi_value;
  1214. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1215. "RSSI_PRI20_CHAIN6: %d\n", rssi_value);
  1216. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1217. RECEIVE_RSSI_INFO,
  1218. RSSI_PRI20_CHAIN7);
  1219. ppdu_info->rx_status.rssi[7] = rssi_value;
  1220. #endif
  1221. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1222. "RSSI_PRI20_CHAIN7: %d\n", rssi_value);
  1223. break;
  1224. }
  1225. case WIFIPHYRX_OTHER_RECEIVE_INFO_E:
  1226. hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr,
  1227. ppdu_info);
  1228. break;
  1229. case WIFIRX_HEADER_E:
  1230. {
  1231. struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info;
  1232. if (ppdu_info->fcs_ok_cnt >=
  1233. HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) {
  1234. hal_err("Number of MPDUs(%d) per status buff exceeded",
  1235. ppdu_info->fcs_ok_cnt);
  1236. break;
  1237. }
  1238. /* Update first_msdu_payload for every mpdu and increment
  1239. * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV
  1240. */
  1241. ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload =
  1242. rx_tlv;
  1243. ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len;
  1244. ppdu_info->msdu_info.first_msdu_payload = rx_tlv;
  1245. ppdu_info->msdu_info.payload_len = tlv_len;
  1246. ppdu_info->user_id = user_id;
  1247. ppdu_info->hdr_len = tlv_len;
  1248. ppdu_info->data = rx_tlv;
  1249. ppdu_info->data += 4;
  1250. /* for every RX_HEADER TLV increment mpdu_cnt */
  1251. com_info->mpdu_cnt++;
  1252. return HAL_TLV_STATUS_HEADER;
  1253. }
  1254. case WIFIRX_MPDU_START_E:
  1255. {
  1256. uint8_t *rx_mpdu_start = (uint8_t *)rx_tlv;
  1257. uint32_t ppdu_id = HAL_RX_GET_PPDU_ID(rx_tlv);
  1258. uint8_t filter_category = 0;
  1259. ppdu_info->nac_info.fc_valid =
  1260. HAL_RX_MON_GET_FC_VALID(rx_tlv);
  1261. ppdu_info->nac_info.to_ds_flag =
  1262. HAL_RX_MON_GET_TO_DS_FLAG(rx_tlv);
  1263. ppdu_info->nac_info.frame_control =
  1264. HAL_RX_GET(rx_mpdu_start,
  1265. RX_MPDU_INFO,
  1266. MPDU_FRAME_CONTROL_FIELD);
  1267. ppdu_info->sw_frame_group_id =
  1268. HAL_RX_GET_SW_FRAME_GROUP_ID(rx_tlv);
  1269. ppdu_info->rx_user_status[user_id].sw_peer_id =
  1270. HAL_RX_GET(rx_mpdu_start,
  1271. RX_MPDU_INFO,
  1272. SW_PEER_ID);
  1273. if (ppdu_info->sw_frame_group_id ==
  1274. HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) {
  1275. ppdu_info->rx_status.frame_control_info_valid =
  1276. ppdu_info->nac_info.fc_valid;
  1277. ppdu_info->rx_status.frame_control =
  1278. ppdu_info->nac_info.frame_control;
  1279. }
  1280. hal_get_mac_addr1(rx_mpdu_start,
  1281. ppdu_info);
  1282. ppdu_info->nac_info.mac_addr2_valid =
  1283. HAL_RX_MON_GET_MAC_ADDR2_VALID(rx_mpdu_start);
  1284. *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] =
  1285. HAL_RX_GET(rx_mpdu_start,
  1286. RX_MPDU_INFO,
  1287. MAC_ADDR_AD2_15_0);
  1288. *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] =
  1289. HAL_RX_GET(rx_mpdu_start,
  1290. RX_MPDU_INFO,
  1291. MAC_ADDR_AD2_47_16);
  1292. if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) {
  1293. ppdu_info->rx_status.prev_ppdu_id = ppdu_id;
  1294. ppdu_info->rx_status.ppdu_len =
  1295. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO,
  1296. MPDU_LENGTH);
  1297. } else {
  1298. ppdu_info->rx_status.ppdu_len +=
  1299. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO,
  1300. MPDU_LENGTH);
  1301. }
  1302. filter_category =
  1303. HAL_RX_GET_FILTER_CATEGORY(rx_tlv);
  1304. if (filter_category == 0)
  1305. ppdu_info->rx_status.rxpcu_filter_pass = 1;
  1306. else if (filter_category == 1)
  1307. ppdu_info->rx_status.monitor_direct_used = 1;
  1308. ppdu_info->nac_info.mcast_bcast =
  1309. HAL_RX_GET(rx_mpdu_start,
  1310. RX_MPDU_INFO,
  1311. MCAST_BCAST);
  1312. break;
  1313. }
  1314. case WIFIRX_MPDU_END_E:
  1315. ppdu_info->user_id = user_id;
  1316. ppdu_info->fcs_err =
  1317. HAL_RX_GET(rx_tlv, RX_MPDU_END,
  1318. FCS_ERR);
  1319. return HAL_TLV_STATUS_MPDU_END;
  1320. case WIFIRX_MSDU_END_E:
  1321. if (user_id < HAL_MAX_UL_MU_USERS) {
  1322. ppdu_info->rx_msdu_info[user_id].cce_metadata =
  1323. HAL_RX_TLV_CCE_METADATA_GET(rx_tlv);
  1324. ppdu_info->rx_msdu_info[user_id].fse_metadata =
  1325. HAL_RX_TLV_FSE_METADATA_GET(rx_tlv);
  1326. ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout =
  1327. HAL_RX_TLV_FLOW_IDX_TIMEOUT_GET(rx_tlv);
  1328. ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid =
  1329. HAL_RX_TLV_FLOW_IDX_INVALID_GET(rx_tlv);
  1330. ppdu_info->rx_msdu_info[user_id].flow_idx =
  1331. HAL_RX_TLV_FLOW_IDX_GET(rx_tlv);
  1332. }
  1333. return HAL_TLV_STATUS_MSDU_END;
  1334. case 0:
  1335. return HAL_TLV_STATUS_PPDU_DONE;
  1336. default:
  1337. if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info))
  1338. unhandled = false;
  1339. else
  1340. unhandled = true;
  1341. break;
  1342. }
  1343. if (!unhandled)
  1344. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1345. "%s TLV type: %d, TLV len:%d %s",
  1346. __func__, tlv_tag, tlv_len,
  1347. unhandled == true ? "unhandled" : "");
  1348. qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1349. rx_tlv, tlv_len);
  1350. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1351. }
  1352. /**
  1353. * hal_tx_set_pcp_tid_map_generic_be() - Configure default PCP to TID map table
  1354. * @soc: HAL SoC context
  1355. * @map: PCP-TID mapping table
  1356. *
  1357. * PCP are mapped to 8 TID values using TID values programmed
  1358. * in one set of mapping registers PCP_TID_MAP_<0 to 6>
  1359. * The mapping register has TID mapping for 8 PCP values
  1360. *
  1361. * Return: none
  1362. */
  1363. static void hal_tx_set_pcp_tid_map_generic_be(struct hal_soc *soc, uint8_t *map)
  1364. {
  1365. uint32_t addr, value;
  1366. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  1367. MAC_TCL_REG_REG_BASE);
  1368. value = (map[0] |
  1369. (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) |
  1370. (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) |
  1371. (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) |
  1372. (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) |
  1373. (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) |
  1374. (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) |
  1375. (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT));
  1376. HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  1377. }
  1378. /**
  1379. * hal_tx_update_pcp_tid_generic_be() - Update the pcp tid map table with
  1380. * value received from user-space
  1381. * @soc: HAL SoC context
  1382. * @pcp: pcp value
  1383. * @tid : tid value
  1384. *
  1385. * Return: void
  1386. */
  1387. static void
  1388. hal_tx_update_pcp_tid_generic_be(struct hal_soc *soc,
  1389. uint8_t pcp, uint8_t tid)
  1390. {
  1391. uint32_t addr, value, regval;
  1392. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  1393. MAC_TCL_REG_REG_BASE);
  1394. value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp);
  1395. /* Read back previous PCP TID config and update
  1396. * with new config.
  1397. */
  1398. regval = HAL_REG_READ(soc, addr);
  1399. regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp));
  1400. regval |= value;
  1401. HAL_REG_WRITE(soc, addr,
  1402. (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  1403. }
  1404. /**
  1405. * hal_tx_update_tidmap_prty_generic_be() - Update the tid map priority
  1406. * @soc: HAL SoC context
  1407. * @val: priority value
  1408. *
  1409. * Return: void
  1410. */
  1411. static
  1412. void hal_tx_update_tidmap_prty_generic_be(struct hal_soc *soc, uint8_t value)
  1413. {
  1414. uint32_t addr;
  1415. addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR(
  1416. MAC_TCL_REG_REG_BASE);
  1417. HAL_REG_WRITE(soc, addr,
  1418. (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK));
  1419. }
  1420. /**
  1421. * hal_rx_get_tlv_size_generic_be() - Get rx packet tlv size
  1422. * @rx_pkt_tlv_size: TLV size for regular RX packets
  1423. * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets
  1424. *
  1425. * Return: size of rx pkt tlv before the actual data
  1426. */
  1427. static void hal_rx_get_tlv_size_generic_be(uint16_t *rx_pkt_tlv_size,
  1428. uint16_t *rx_mon_pkt_tlv_size)
  1429. {
  1430. *rx_pkt_tlv_size = RX_PKT_TLVS_LEN;
  1431. /* For now mon pkt tlv is same as rx pkt tlv */
  1432. *rx_mon_pkt_tlv_size = RX_PKT_TLVS_LEN;
  1433. }
  1434. /**
  1435. * hal_rx_flow_get_tuple_info_be() - Setup a flow search entry in HW FST
  1436. * @fst: Pointer to the Rx Flow Search Table
  1437. * @hal_hash: HAL 5 tuple hash
  1438. * @tuple_info: 5-tuple info of the flow returned to the caller
  1439. *
  1440. * Return: Success/Failure
  1441. */
  1442. static void *
  1443. hal_rx_flow_get_tuple_info_be(uint8_t *rx_fst, uint32_t hal_hash,
  1444. uint8_t *flow_tuple_info)
  1445. {
  1446. struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
  1447. void *hal_fse = NULL;
  1448. struct hal_flow_tuple_info *tuple_info
  1449. = (struct hal_flow_tuple_info *)flow_tuple_info;
  1450. hal_fse = (uint8_t *)fst->base_vaddr +
  1451. (hal_hash * HAL_RX_FST_ENTRY_SIZE);
  1452. if (!hal_fse || !tuple_info)
  1453. return NULL;
  1454. if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY, VALID))
  1455. return NULL;
  1456. tuple_info->src_ip_127_96 =
  1457. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1458. RX_FLOW_SEARCH_ENTRY,
  1459. SRC_IP_127_96));
  1460. tuple_info->src_ip_95_64 =
  1461. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1462. RX_FLOW_SEARCH_ENTRY,
  1463. SRC_IP_95_64));
  1464. tuple_info->src_ip_63_32 =
  1465. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1466. RX_FLOW_SEARCH_ENTRY,
  1467. SRC_IP_63_32));
  1468. tuple_info->src_ip_31_0 =
  1469. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1470. RX_FLOW_SEARCH_ENTRY,
  1471. SRC_IP_31_0));
  1472. tuple_info->dest_ip_127_96 =
  1473. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1474. RX_FLOW_SEARCH_ENTRY,
  1475. DEST_IP_127_96));
  1476. tuple_info->dest_ip_95_64 =
  1477. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1478. RX_FLOW_SEARCH_ENTRY,
  1479. DEST_IP_95_64));
  1480. tuple_info->dest_ip_63_32 =
  1481. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1482. RX_FLOW_SEARCH_ENTRY,
  1483. DEST_IP_63_32));
  1484. tuple_info->dest_ip_31_0 =
  1485. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1486. RX_FLOW_SEARCH_ENTRY,
  1487. DEST_IP_31_0));
  1488. tuple_info->dest_port = HAL_GET_FLD(hal_fse,
  1489. RX_FLOW_SEARCH_ENTRY,
  1490. DEST_PORT);
  1491. tuple_info->src_port = HAL_GET_FLD(hal_fse,
  1492. RX_FLOW_SEARCH_ENTRY,
  1493. SRC_PORT);
  1494. tuple_info->l4_protocol = HAL_GET_FLD(hal_fse,
  1495. RX_FLOW_SEARCH_ENTRY,
  1496. L4_PROTOCOL);
  1497. return hal_fse;
  1498. }
  1499. /**
  1500. * hal_rx_flow_delete_entry_be() - Setup a flow search entry in HW FST
  1501. * @fst: Pointer to the Rx Flow Search Table
  1502. * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST
  1503. *
  1504. * Return: Success/Failure
  1505. */
  1506. static QDF_STATUS
  1507. hal_rx_flow_delete_entry_be(uint8_t *rx_fst, void *hal_rx_fse)
  1508. {
  1509. uint8_t *fse = (uint8_t *)hal_rx_fse;
  1510. if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID))
  1511. return QDF_STATUS_E_NOENT;
  1512. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
  1513. return QDF_STATUS_SUCCESS;
  1514. }
  1515. /**
  1516. * hal_rx_fst_get_fse_size_be() - Retrieve the size of each entry in Rx FST
  1517. *
  1518. * Return: size of each entry/flow in Rx FST
  1519. */
  1520. static inline uint32_t
  1521. hal_rx_fst_get_fse_size_be(void)
  1522. {
  1523. return HAL_RX_FST_ENTRY_SIZE;
  1524. }
  1525. #endif /* _HAL_BE_GENERIC_API_H_ */