c3fae0027c
Added qcn6432 target header files based on E3R47 under qcn6432 to make fw-api project compatible to host. Change-Id: I3bdf6298281323f4f0fe75aed04db93cd698ee1f CRs-Fixed: 3463782
2448 rivejä
93 KiB
C
2448 rivejä
93 KiB
C
/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _RX_REO_QUEUE_EXT_H_
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#define _RX_REO_QUEUE_EXT_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#include "rx_mpdu_link_ptr.h"
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#include "uniform_descriptor_header.h"
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#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32
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struct rx_reo_queue_ext {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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struct uniform_descriptor_header descriptor_header;
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uint32_t reserved_1a : 32; // [31:0]
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struct rx_mpdu_link_ptr mpdu_link_pointer_0;
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struct rx_mpdu_link_ptr mpdu_link_pointer_1;
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struct rx_mpdu_link_ptr mpdu_link_pointer_2;
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struct rx_mpdu_link_ptr mpdu_link_pointer_3;
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struct rx_mpdu_link_ptr mpdu_link_pointer_4;
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struct rx_mpdu_link_ptr mpdu_link_pointer_5;
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struct rx_mpdu_link_ptr mpdu_link_pointer_6;
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struct rx_mpdu_link_ptr mpdu_link_pointer_7;
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struct rx_mpdu_link_ptr mpdu_link_pointer_8;
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struct rx_mpdu_link_ptr mpdu_link_pointer_9;
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struct rx_mpdu_link_ptr mpdu_link_pointer_10;
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struct rx_mpdu_link_ptr mpdu_link_pointer_11;
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struct rx_mpdu_link_ptr mpdu_link_pointer_12;
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struct rx_mpdu_link_ptr mpdu_link_pointer_13;
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struct rx_mpdu_link_ptr mpdu_link_pointer_14;
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#else
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struct uniform_descriptor_header descriptor_header;
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uint32_t reserved_1a : 32; // [31:0]
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struct rx_mpdu_link_ptr mpdu_link_pointer_0;
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struct rx_mpdu_link_ptr mpdu_link_pointer_1;
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struct rx_mpdu_link_ptr mpdu_link_pointer_2;
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struct rx_mpdu_link_ptr mpdu_link_pointer_3;
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struct rx_mpdu_link_ptr mpdu_link_pointer_4;
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struct rx_mpdu_link_ptr mpdu_link_pointer_5;
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struct rx_mpdu_link_ptr mpdu_link_pointer_6;
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struct rx_mpdu_link_ptr mpdu_link_pointer_7;
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struct rx_mpdu_link_ptr mpdu_link_pointer_8;
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struct rx_mpdu_link_ptr mpdu_link_pointer_9;
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struct rx_mpdu_link_ptr mpdu_link_pointer_10;
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struct rx_mpdu_link_ptr mpdu_link_pointer_11;
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struct rx_mpdu_link_ptr mpdu_link_pointer_12;
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struct rx_mpdu_link_ptr mpdu_link_pointer_13;
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struct rx_mpdu_link_ptr mpdu_link_pointer_14;
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#endif
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};
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/* Description DESCRIPTOR_HEADER
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Details about which module owns this struct.
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Note that sub field "Buffer_type" shall be set to "Receive_REO_queue_ext_descriptor"
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*/
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/* Description OWNER
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Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
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Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
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The owner of this data structure:
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<enum 0 WBM_owned> Buffer Manager currently owns this data
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structure.
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<enum 1 SW_OR_FW_owned> Software of FW currently owns this
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data structure.
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<enum 2 TQM_owned> Transmit Queue Manager currently owns
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this data structure.
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<enum 3 RXDMA_owned> Receive DMA currently owns this data
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structure.
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<enum 4 REO_owned> Reorder currently owns this data structure.
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<enum 5 SWITCH_owned> SWITCH currently owns this data structure.
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<legal 0-5>
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*/
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#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
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#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_LSB 0
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#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MSB 3
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#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
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/* Description BUFFER_TYPE
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Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
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Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
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Field describing what contents format is of this descriptor
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<enum 0 Transmit_MSDU_Link_descriptor>
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<enum 1 Transmit_MPDU_Link_descriptor>
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<enum 2 Transmit_MPDU_Queue_head_descriptor>
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<enum 3 Transmit_MPDU_Queue_ext_descriptor>
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<enum 4 Transmit_flow_descriptor>
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<enum 5 Transmit_buffer> NOT TO BE USED:
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<enum 6 Receive_MSDU_Link_descriptor>
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<enum 7 Receive_MPDU_Link_descriptor>
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<enum 8 Receive_REO_queue_descriptor>
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<enum 9 Receive_REO_queue_1k_descriptor>
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<enum 10 Receive_REO_queue_ext_descriptor>
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<enum 11 Receive_buffer>
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<enum 12 Idle_link_list_entry>
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<legal 0-12>
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*/
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#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
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#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
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#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7
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#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
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/* Description TX_MPDU_QUEUE_NUMBER
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Consumer: TQM/Debug
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Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere)
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Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor
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Indicates the MPDU queue ID to which this MPDU descriptor
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belongs
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Used for tracking and debugging
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<legal all>
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*/
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#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000
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#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8
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#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27
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#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00
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/* Description RESERVED_0A
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<legal 0>
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*/
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#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
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#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28
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#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
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#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000
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/* Description RESERVED_1A
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<legal 0>
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*/
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#define RX_REO_QUEUE_EXT_RESERVED_1A_OFFSET 0x00000004
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#define RX_REO_QUEUE_EXT_RESERVED_1A_LSB 0
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#define RX_REO_QUEUE_EXT_RESERVED_1A_MSB 31
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#define RX_REO_QUEUE_EXT_RESERVED_1A_MASK 0xffffffff
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/* Description MPDU_LINK_POINTER_0
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Consumer: REO
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Producer: REO
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Pointer to the next MPDU_link descriptor in the MPDU queue
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*/
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/* Description MPDU_LINK_DESC_ADDR_INFO
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Details of the physical address of an MPDU link descriptor
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*/
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/* Description BUFFER_ADDR_31_0
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Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
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descriptor OR Link Descriptor
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In case of 'NULL' pointer, this field is set to 0
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<legal all>
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*/
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
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/* Description BUFFER_ADDR_39_32
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Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
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descriptor OR Link Descriptor
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In case of 'NULL' pointer, this field is set to 0
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<legal all>
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*/
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
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/* Description RETURN_BUFFER_MANAGER
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Consumer: WBM
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Producer: SW/FW
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In case of 'NULL' pointer, this field is set to 0
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Indicates to which buffer manager the buffer OR MSDU_EXTENSION
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descriptor OR link descriptor that is being pointed to
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shall be returned after the frame has been processed. It
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is used by WBM for routing purposes.
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<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
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to the WMB buffer idle list
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<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
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to the WBM idle link descriptor idle list, where the chip
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0 WBM is chosen in case of a multi-chip config
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<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
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to the chip 1 WBM idle link descriptor idle list
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<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
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to the chip 2 WBM idle link descriptor idle list
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<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
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returned to chip 3 WBM idle link descriptor idle list
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<enum 4 FW_BM> This buffer shall be returned to the FW
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<enum 5 SW0_BM> This buffer shall be returned to the SW,
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ring 0
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<enum 6 SW1_BM> This buffer shall be returned to the SW,
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ring 1
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<enum 7 SW2_BM> This buffer shall be returned to the SW,
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ring 2
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<enum 8 SW3_BM> This buffer shall be returned to the SW,
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ring 3
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<enum 9 SW4_BM> This buffer shall be returned to the SW,
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ring 4
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<enum 10 SW5_BM> This buffer shall be returned to the SW,
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ring 5
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<enum 11 SW6_BM> This buffer shall be returned to the SW,
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ring 6
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<legal 0-12>
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*/
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
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/* Description SW_BUFFER_COOKIE
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Cookie field exclusively used by SW.
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In case of 'NULL' pointer, this field is set to 0
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HW ignores the contents, accept that it passes the programmed
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value on to other descriptors together with the physical
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address
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Field can be used by SW to for example associate the buffers
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physical address with the virtual address
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The bit definitions as used by SW are within SW HLD specification
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NOTE1:
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The three most significant bits can have a special meaning
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in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
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and field transmit_bw_restriction is set
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In case of NON punctured transmission:
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Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
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Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
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Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
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Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
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Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
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Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
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Sw_buffer_cookie[19:18] = 2'b11: reserved
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In case of punctured transmission:
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Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
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Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
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Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
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Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
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Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
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Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
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Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
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Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
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Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
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Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
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Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
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Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
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Sw_buffer_cookie[19:18] = 2'b11: reserved
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Note: a punctured transmission is indicated by the presence
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of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
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<legal all>
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*/
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
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/* Description MPDU_LINK_POINTER_1
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Consumer: REO
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Producer: REO
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Pointer to the next MPDU_link descriptor in the MPDU queue
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*/
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/* Description MPDU_LINK_DESC_ADDR_INFO
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Details of the physical address of an MPDU link descriptor
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*/
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/* Description BUFFER_ADDR_31_0
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Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
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descriptor OR Link Descriptor
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In case of 'NULL' pointer, this field is set to 0
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<legal all>
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*/
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
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/* Description BUFFER_ADDR_39_32
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Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
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descriptor OR Link Descriptor
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In case of 'NULL' pointer, this field is set to 0
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<legal all>
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*/
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
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/* Description RETURN_BUFFER_MANAGER
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Consumer: WBM
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Producer: SW/FW
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In case of 'NULL' pointer, this field is set to 0
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Indicates to which buffer manager the buffer OR MSDU_EXTENSION
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descriptor OR link descriptor that is being pointed to
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shall be returned after the frame has been processed. It
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is used by WBM for routing purposes.
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<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
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to the WMB buffer idle list
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<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
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to the WBM idle link descriptor idle list, where the chip
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0 WBM is chosen in case of a multi-chip config
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<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
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to the chip 1 WBM idle link descriptor idle list
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<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
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to the chip 2 WBM idle link descriptor idle list
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<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
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returned to chip 3 WBM idle link descriptor idle list
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<enum 4 FW_BM> This buffer shall be returned to the FW
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<enum 5 SW0_BM> This buffer shall be returned to the SW,
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ring 0
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<enum 6 SW1_BM> This buffer shall be returned to the SW,
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ring 1
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<enum 7 SW2_BM> This buffer shall be returned to the SW,
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ring 2
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<enum 8 SW3_BM> This buffer shall be returned to the SW,
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ring 3
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<enum 9 SW4_BM> This buffer shall be returned to the SW,
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ring 4
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<enum 10 SW5_BM> This buffer shall be returned to the SW,
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ring 5
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<enum 11 SW6_BM> This buffer shall be returned to the SW,
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ring 6
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<legal 0-12>
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*/
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
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#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
|
|
|
|
|
/* Description SW_BUFFER_COOKIE
|
|
|
|
Cookie field exclusively used by SW.
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
HW ignores the contents, accept that it passes the programmed
|
|
value on to other descriptors together with the physical
|
|
address
|
|
|
|
Field can be used by SW to for example associate the buffers
|
|
physical address with the virtual address
|
|
The bit definitions as used by SW are within SW HLD specification
|
|
|
|
|
|
NOTE1:
|
|
The three most significant bits can have a special meaning
|
|
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
|
|
and field transmit_bw_restriction is set
|
|
|
|
In case of NON punctured transmission:
|
|
Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
In case of punctured transmission:
|
|
Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
|
|
Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
|
|
Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
|
|
Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
|
|
Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
|
|
Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
|
|
Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
|
|
Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
|
|
Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
|
|
Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
|
|
Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
|
|
Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
Note: a punctured transmission is indicated by the presence
|
|
of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
|
|
|
|
|
|
/* Description MPDU_LINK_POINTER_2
|
|
|
|
Consumer: REO
|
|
Producer: REO
|
|
|
|
Pointer to the next MPDU_link descriptor in the MPDU queue
|
|
|
|
*/
|
|
|
|
|
|
/* Description MPDU_LINK_DESC_ADDR_INFO
|
|
|
|
Details of the physical address of an MPDU link descriptor
|
|
|
|
*/
|
|
|
|
|
|
/* Description BUFFER_ADDR_31_0
|
|
|
|
Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
|
|
|
|
|
|
/* Description BUFFER_ADDR_39_32
|
|
|
|
Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
|
|
|
|
|
|
/* Description RETURN_BUFFER_MANAGER
|
|
|
|
Consumer: WBM
|
|
Producer: SW/FW
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
Indicates to which buffer manager the buffer OR MSDU_EXTENSION
|
|
descriptor OR link descriptor that is being pointed to
|
|
shall be returned after the frame has been processed. It
|
|
is used by WBM for routing purposes.
|
|
|
|
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
|
|
to the WMB buffer idle list
|
|
<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the WBM idle link descriptor idle list, where the chip
|
|
0 WBM is chosen in case of a multi-chip config
|
|
<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 1 WBM idle link descriptor idle list
|
|
<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 2 WBM idle link descriptor idle list
|
|
<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
|
|
returned to chip 3 WBM idle link descriptor idle list
|
|
<enum 4 FW_BM> This buffer shall be returned to the FW
|
|
<enum 5 SW0_BM> This buffer shall be returned to the SW,
|
|
ring 0
|
|
<enum 6 SW1_BM> This buffer shall be returned to the SW,
|
|
ring 1
|
|
<enum 7 SW2_BM> This buffer shall be returned to the SW,
|
|
ring 2
|
|
<enum 8 SW3_BM> This buffer shall be returned to the SW,
|
|
ring 3
|
|
<enum 9 SW4_BM> This buffer shall be returned to the SW,
|
|
ring 4
|
|
<enum 10 SW5_BM> This buffer shall be returned to the SW,
|
|
ring 5
|
|
<enum 11 SW6_BM> This buffer shall be returned to the SW,
|
|
ring 6
|
|
|
|
<legal 0-12>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
|
|
|
|
|
/* Description SW_BUFFER_COOKIE
|
|
|
|
Cookie field exclusively used by SW.
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
HW ignores the contents, accept that it passes the programmed
|
|
value on to other descriptors together with the physical
|
|
address
|
|
|
|
Field can be used by SW to for example associate the buffers
|
|
physical address with the virtual address
|
|
The bit definitions as used by SW are within SW HLD specification
|
|
|
|
|
|
NOTE1:
|
|
The three most significant bits can have a special meaning
|
|
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
|
|
and field transmit_bw_restriction is set
|
|
|
|
In case of NON punctured transmission:
|
|
Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
In case of punctured transmission:
|
|
Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
|
|
Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
|
|
Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
|
|
Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
|
|
Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
|
|
Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
|
|
Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
|
|
Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
|
|
Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
|
|
Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
|
|
Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
|
|
Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
Note: a punctured transmission is indicated by the presence
|
|
of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
|
|
|
|
|
|
/* Description MPDU_LINK_POINTER_3
|
|
|
|
Consumer: REO
|
|
Producer: REO
|
|
|
|
Pointer to the next MPDU_link descriptor in the MPDU queue
|
|
|
|
*/
|
|
|
|
|
|
/* Description MPDU_LINK_DESC_ADDR_INFO
|
|
|
|
Details of the physical address of an MPDU link descriptor
|
|
|
|
*/
|
|
|
|
|
|
/* Description BUFFER_ADDR_31_0
|
|
|
|
Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
|
|
|
|
|
|
/* Description BUFFER_ADDR_39_32
|
|
|
|
Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
|
|
|
|
|
|
/* Description RETURN_BUFFER_MANAGER
|
|
|
|
Consumer: WBM
|
|
Producer: SW/FW
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
Indicates to which buffer manager the buffer OR MSDU_EXTENSION
|
|
descriptor OR link descriptor that is being pointed to
|
|
shall be returned after the frame has been processed. It
|
|
is used by WBM for routing purposes.
|
|
|
|
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
|
|
to the WMB buffer idle list
|
|
<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the WBM idle link descriptor idle list, where the chip
|
|
0 WBM is chosen in case of a multi-chip config
|
|
<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 1 WBM idle link descriptor idle list
|
|
<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 2 WBM idle link descriptor idle list
|
|
<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
|
|
returned to chip 3 WBM idle link descriptor idle list
|
|
<enum 4 FW_BM> This buffer shall be returned to the FW
|
|
<enum 5 SW0_BM> This buffer shall be returned to the SW,
|
|
ring 0
|
|
<enum 6 SW1_BM> This buffer shall be returned to the SW,
|
|
ring 1
|
|
<enum 7 SW2_BM> This buffer shall be returned to the SW,
|
|
ring 2
|
|
<enum 8 SW3_BM> This buffer shall be returned to the SW,
|
|
ring 3
|
|
<enum 9 SW4_BM> This buffer shall be returned to the SW,
|
|
ring 4
|
|
<enum 10 SW5_BM> This buffer shall be returned to the SW,
|
|
ring 5
|
|
<enum 11 SW6_BM> This buffer shall be returned to the SW,
|
|
ring 6
|
|
|
|
<legal 0-12>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
|
|
|
|
|
/* Description SW_BUFFER_COOKIE
|
|
|
|
Cookie field exclusively used by SW.
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
HW ignores the contents, accept that it passes the programmed
|
|
value on to other descriptors together with the physical
|
|
address
|
|
|
|
Field can be used by SW to for example associate the buffers
|
|
physical address with the virtual address
|
|
The bit definitions as used by SW are within SW HLD specification
|
|
|
|
|
|
NOTE1:
|
|
The three most significant bits can have a special meaning
|
|
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
|
|
and field transmit_bw_restriction is set
|
|
|
|
In case of NON punctured transmission:
|
|
Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
In case of punctured transmission:
|
|
Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
|
|
Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
|
|
Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
|
|
Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
|
|
Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
|
|
Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
|
|
Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
|
|
Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
|
|
Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
|
|
Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
|
|
Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
|
|
Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
Note: a punctured transmission is indicated by the presence
|
|
of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
|
|
|
|
|
|
/* Description MPDU_LINK_POINTER_4
|
|
|
|
Consumer: REO
|
|
Producer: REO
|
|
|
|
Pointer to the next MPDU_link descriptor in the MPDU queue
|
|
|
|
*/
|
|
|
|
|
|
/* Description MPDU_LINK_DESC_ADDR_INFO
|
|
|
|
Details of the physical address of an MPDU link descriptor
|
|
|
|
*/
|
|
|
|
|
|
/* Description BUFFER_ADDR_31_0
|
|
|
|
Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
|
|
|
|
|
|
/* Description BUFFER_ADDR_39_32
|
|
|
|
Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
|
|
|
|
|
|
/* Description RETURN_BUFFER_MANAGER
|
|
|
|
Consumer: WBM
|
|
Producer: SW/FW
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
Indicates to which buffer manager the buffer OR MSDU_EXTENSION
|
|
descriptor OR link descriptor that is being pointed to
|
|
shall be returned after the frame has been processed. It
|
|
is used by WBM for routing purposes.
|
|
|
|
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
|
|
to the WMB buffer idle list
|
|
<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the WBM idle link descriptor idle list, where the chip
|
|
0 WBM is chosen in case of a multi-chip config
|
|
<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 1 WBM idle link descriptor idle list
|
|
<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 2 WBM idle link descriptor idle list
|
|
<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
|
|
returned to chip 3 WBM idle link descriptor idle list
|
|
<enum 4 FW_BM> This buffer shall be returned to the FW
|
|
<enum 5 SW0_BM> This buffer shall be returned to the SW,
|
|
ring 0
|
|
<enum 6 SW1_BM> This buffer shall be returned to the SW,
|
|
ring 1
|
|
<enum 7 SW2_BM> This buffer shall be returned to the SW,
|
|
ring 2
|
|
<enum 8 SW3_BM> This buffer shall be returned to the SW,
|
|
ring 3
|
|
<enum 9 SW4_BM> This buffer shall be returned to the SW,
|
|
ring 4
|
|
<enum 10 SW5_BM> This buffer shall be returned to the SW,
|
|
ring 5
|
|
<enum 11 SW6_BM> This buffer shall be returned to the SW,
|
|
ring 6
|
|
|
|
<legal 0-12>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
|
|
|
|
|
/* Description SW_BUFFER_COOKIE
|
|
|
|
Cookie field exclusively used by SW.
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
HW ignores the contents, accept that it passes the programmed
|
|
value on to other descriptors together with the physical
|
|
address
|
|
|
|
Field can be used by SW to for example associate the buffers
|
|
physical address with the virtual address
|
|
The bit definitions as used by SW are within SW HLD specification
|
|
|
|
|
|
NOTE1:
|
|
The three most significant bits can have a special meaning
|
|
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
|
|
and field transmit_bw_restriction is set
|
|
|
|
In case of NON punctured transmission:
|
|
Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
In case of punctured transmission:
|
|
Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
|
|
Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
|
|
Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
|
|
Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
|
|
Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
|
|
Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
|
|
Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
|
|
Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
|
|
Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
|
|
Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
|
|
Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
|
|
Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
Note: a punctured transmission is indicated by the presence
|
|
of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
|
|
|
|
|
|
/* Description MPDU_LINK_POINTER_5
|
|
|
|
Consumer: REO
|
|
Producer: REO
|
|
|
|
Pointer to the next MPDU_link descriptor in the MPDU queue
|
|
|
|
*/
|
|
|
|
|
|
/* Description MPDU_LINK_DESC_ADDR_INFO
|
|
|
|
Details of the physical address of an MPDU link descriptor
|
|
|
|
*/
|
|
|
|
|
|
/* Description BUFFER_ADDR_31_0
|
|
|
|
Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
|
|
|
|
|
|
/* Description BUFFER_ADDR_39_32
|
|
|
|
Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
|
|
|
|
|
|
/* Description RETURN_BUFFER_MANAGER
|
|
|
|
Consumer: WBM
|
|
Producer: SW/FW
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
Indicates to which buffer manager the buffer OR MSDU_EXTENSION
|
|
descriptor OR link descriptor that is being pointed to
|
|
shall be returned after the frame has been processed. It
|
|
is used by WBM for routing purposes.
|
|
|
|
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
|
|
to the WMB buffer idle list
|
|
<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the WBM idle link descriptor idle list, where the chip
|
|
0 WBM is chosen in case of a multi-chip config
|
|
<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 1 WBM idle link descriptor idle list
|
|
<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 2 WBM idle link descriptor idle list
|
|
<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
|
|
returned to chip 3 WBM idle link descriptor idle list
|
|
<enum 4 FW_BM> This buffer shall be returned to the FW
|
|
<enum 5 SW0_BM> This buffer shall be returned to the SW,
|
|
ring 0
|
|
<enum 6 SW1_BM> This buffer shall be returned to the SW,
|
|
ring 1
|
|
<enum 7 SW2_BM> This buffer shall be returned to the SW,
|
|
ring 2
|
|
<enum 8 SW3_BM> This buffer shall be returned to the SW,
|
|
ring 3
|
|
<enum 9 SW4_BM> This buffer shall be returned to the SW,
|
|
ring 4
|
|
<enum 10 SW5_BM> This buffer shall be returned to the SW,
|
|
ring 5
|
|
<enum 11 SW6_BM> This buffer shall be returned to the SW,
|
|
ring 6
|
|
|
|
<legal 0-12>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
|
|
|
|
|
/* Description SW_BUFFER_COOKIE
|
|
|
|
Cookie field exclusively used by SW.
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
HW ignores the contents, accept that it passes the programmed
|
|
value on to other descriptors together with the physical
|
|
address
|
|
|
|
Field can be used by SW to for example associate the buffers
|
|
physical address with the virtual address
|
|
The bit definitions as used by SW are within SW HLD specification
|
|
|
|
|
|
NOTE1:
|
|
The three most significant bits can have a special meaning
|
|
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
|
|
and field transmit_bw_restriction is set
|
|
|
|
In case of NON punctured transmission:
|
|
Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
In case of punctured transmission:
|
|
Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
|
|
Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
|
|
Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
|
|
Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
|
|
Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
|
|
Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
|
|
Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
|
|
Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
|
|
Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
|
|
Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
|
|
Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
|
|
Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
Note: a punctured transmission is indicated by the presence
|
|
of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
|
|
|
|
|
|
/* Description MPDU_LINK_POINTER_6
|
|
|
|
Consumer: REO
|
|
Producer: REO
|
|
|
|
Pointer to the next MPDU_link descriptor in the MPDU queue
|
|
|
|
*/
|
|
|
|
|
|
/* Description MPDU_LINK_DESC_ADDR_INFO
|
|
|
|
Details of the physical address of an MPDU link descriptor
|
|
|
|
*/
|
|
|
|
|
|
/* Description BUFFER_ADDR_31_0
|
|
|
|
Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
|
|
|
|
|
|
/* Description BUFFER_ADDR_39_32
|
|
|
|
Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
|
|
|
|
|
|
/* Description RETURN_BUFFER_MANAGER
|
|
|
|
Consumer: WBM
|
|
Producer: SW/FW
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
Indicates to which buffer manager the buffer OR MSDU_EXTENSION
|
|
descriptor OR link descriptor that is being pointed to
|
|
shall be returned after the frame has been processed. It
|
|
is used by WBM for routing purposes.
|
|
|
|
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
|
|
to the WMB buffer idle list
|
|
<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the WBM idle link descriptor idle list, where the chip
|
|
0 WBM is chosen in case of a multi-chip config
|
|
<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 1 WBM idle link descriptor idle list
|
|
<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 2 WBM idle link descriptor idle list
|
|
<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
|
|
returned to chip 3 WBM idle link descriptor idle list
|
|
<enum 4 FW_BM> This buffer shall be returned to the FW
|
|
<enum 5 SW0_BM> This buffer shall be returned to the SW,
|
|
ring 0
|
|
<enum 6 SW1_BM> This buffer shall be returned to the SW,
|
|
ring 1
|
|
<enum 7 SW2_BM> This buffer shall be returned to the SW,
|
|
ring 2
|
|
<enum 8 SW3_BM> This buffer shall be returned to the SW,
|
|
ring 3
|
|
<enum 9 SW4_BM> This buffer shall be returned to the SW,
|
|
ring 4
|
|
<enum 10 SW5_BM> This buffer shall be returned to the SW,
|
|
ring 5
|
|
<enum 11 SW6_BM> This buffer shall be returned to the SW,
|
|
ring 6
|
|
|
|
<legal 0-12>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
|
|
|
|
|
/* Description SW_BUFFER_COOKIE
|
|
|
|
Cookie field exclusively used by SW.
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
HW ignores the contents, accept that it passes the programmed
|
|
value on to other descriptors together with the physical
|
|
address
|
|
|
|
Field can be used by SW to for example associate the buffers
|
|
physical address with the virtual address
|
|
The bit definitions as used by SW are within SW HLD specification
|
|
|
|
|
|
NOTE1:
|
|
The three most significant bits can have a special meaning
|
|
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
|
|
and field transmit_bw_restriction is set
|
|
|
|
In case of NON punctured transmission:
|
|
Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
In case of punctured transmission:
|
|
Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
|
|
Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
|
|
Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
|
|
Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
|
|
Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
|
|
Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
|
|
Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
|
|
Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
|
|
Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
|
|
Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
|
|
Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
|
|
Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
Note: a punctured transmission is indicated by the presence
|
|
of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
|
|
|
|
|
|
/* Description MPDU_LINK_POINTER_7
|
|
|
|
Consumer: REO
|
|
Producer: REO
|
|
|
|
Pointer to the next MPDU_link descriptor in the MPDU queue
|
|
|
|
*/
|
|
|
|
|
|
/* Description MPDU_LINK_DESC_ADDR_INFO
|
|
|
|
Details of the physical address of an MPDU link descriptor
|
|
|
|
*/
|
|
|
|
|
|
/* Description BUFFER_ADDR_31_0
|
|
|
|
Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
|
|
|
|
|
|
/* Description BUFFER_ADDR_39_32
|
|
|
|
Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
|
|
|
|
|
|
/* Description RETURN_BUFFER_MANAGER
|
|
|
|
Consumer: WBM
|
|
Producer: SW/FW
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
Indicates to which buffer manager the buffer OR MSDU_EXTENSION
|
|
descriptor OR link descriptor that is being pointed to
|
|
shall be returned after the frame has been processed. It
|
|
is used by WBM for routing purposes.
|
|
|
|
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
|
|
to the WMB buffer idle list
|
|
<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the WBM idle link descriptor idle list, where the chip
|
|
0 WBM is chosen in case of a multi-chip config
|
|
<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 1 WBM idle link descriptor idle list
|
|
<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 2 WBM idle link descriptor idle list
|
|
<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
|
|
returned to chip 3 WBM idle link descriptor idle list
|
|
<enum 4 FW_BM> This buffer shall be returned to the FW
|
|
<enum 5 SW0_BM> This buffer shall be returned to the SW,
|
|
ring 0
|
|
<enum 6 SW1_BM> This buffer shall be returned to the SW,
|
|
ring 1
|
|
<enum 7 SW2_BM> This buffer shall be returned to the SW,
|
|
ring 2
|
|
<enum 8 SW3_BM> This buffer shall be returned to the SW,
|
|
ring 3
|
|
<enum 9 SW4_BM> This buffer shall be returned to the SW,
|
|
ring 4
|
|
<enum 10 SW5_BM> This buffer shall be returned to the SW,
|
|
ring 5
|
|
<enum 11 SW6_BM> This buffer shall be returned to the SW,
|
|
ring 6
|
|
|
|
<legal 0-12>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
|
|
|
|
|
/* Description SW_BUFFER_COOKIE
|
|
|
|
Cookie field exclusively used by SW.
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
HW ignores the contents, accept that it passes the programmed
|
|
value on to other descriptors together with the physical
|
|
address
|
|
|
|
Field can be used by SW to for example associate the buffers
|
|
physical address with the virtual address
|
|
The bit definitions as used by SW are within SW HLD specification
|
|
|
|
|
|
NOTE1:
|
|
The three most significant bits can have a special meaning
|
|
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
|
|
and field transmit_bw_restriction is set
|
|
|
|
In case of NON punctured transmission:
|
|
Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
In case of punctured transmission:
|
|
Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
|
|
Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
|
|
Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
|
|
Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
|
|
Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
|
|
Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
|
|
Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
|
|
Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
|
|
Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
|
|
Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
|
|
Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
|
|
Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
Note: a punctured transmission is indicated by the presence
|
|
of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
|
|
|
|
|
|
/* Description MPDU_LINK_POINTER_8
|
|
|
|
Consumer: REO
|
|
Producer: REO
|
|
|
|
Pointer to the next MPDU_link descriptor in the MPDU queue
|
|
|
|
*/
|
|
|
|
|
|
/* Description MPDU_LINK_DESC_ADDR_INFO
|
|
|
|
Details of the physical address of an MPDU link descriptor
|
|
|
|
*/
|
|
|
|
|
|
/* Description BUFFER_ADDR_31_0
|
|
|
|
Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
|
|
|
|
|
|
/* Description BUFFER_ADDR_39_32
|
|
|
|
Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
|
|
|
|
|
|
/* Description RETURN_BUFFER_MANAGER
|
|
|
|
Consumer: WBM
|
|
Producer: SW/FW
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
Indicates to which buffer manager the buffer OR MSDU_EXTENSION
|
|
descriptor OR link descriptor that is being pointed to
|
|
shall be returned after the frame has been processed. It
|
|
is used by WBM for routing purposes.
|
|
|
|
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
|
|
to the WMB buffer idle list
|
|
<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the WBM idle link descriptor idle list, where the chip
|
|
0 WBM is chosen in case of a multi-chip config
|
|
<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 1 WBM idle link descriptor idle list
|
|
<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 2 WBM idle link descriptor idle list
|
|
<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
|
|
returned to chip 3 WBM idle link descriptor idle list
|
|
<enum 4 FW_BM> This buffer shall be returned to the FW
|
|
<enum 5 SW0_BM> This buffer shall be returned to the SW,
|
|
ring 0
|
|
<enum 6 SW1_BM> This buffer shall be returned to the SW,
|
|
ring 1
|
|
<enum 7 SW2_BM> This buffer shall be returned to the SW,
|
|
ring 2
|
|
<enum 8 SW3_BM> This buffer shall be returned to the SW,
|
|
ring 3
|
|
<enum 9 SW4_BM> This buffer shall be returned to the SW,
|
|
ring 4
|
|
<enum 10 SW5_BM> This buffer shall be returned to the SW,
|
|
ring 5
|
|
<enum 11 SW6_BM> This buffer shall be returned to the SW,
|
|
ring 6
|
|
|
|
<legal 0-12>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
|
|
|
|
|
/* Description SW_BUFFER_COOKIE
|
|
|
|
Cookie field exclusively used by SW.
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
HW ignores the contents, accept that it passes the programmed
|
|
value on to other descriptors together with the physical
|
|
address
|
|
|
|
Field can be used by SW to for example associate the buffers
|
|
physical address with the virtual address
|
|
The bit definitions as used by SW are within SW HLD specification
|
|
|
|
|
|
NOTE1:
|
|
The three most significant bits can have a special meaning
|
|
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
|
|
and field transmit_bw_restriction is set
|
|
|
|
In case of NON punctured transmission:
|
|
Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
In case of punctured transmission:
|
|
Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
|
|
Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
|
|
Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
|
|
Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
|
|
Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
|
|
Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
|
|
Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
|
|
Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
|
|
Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
|
|
Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
|
|
Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
|
|
Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
Note: a punctured transmission is indicated by the presence
|
|
of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
|
|
|
|
|
|
/* Description MPDU_LINK_POINTER_9
|
|
|
|
Consumer: REO
|
|
Producer: REO
|
|
|
|
Pointer to the next MPDU_link descriptor in the MPDU queue
|
|
|
|
*/
|
|
|
|
|
|
/* Description MPDU_LINK_DESC_ADDR_INFO
|
|
|
|
Details of the physical address of an MPDU link descriptor
|
|
|
|
*/
|
|
|
|
|
|
/* Description BUFFER_ADDR_31_0
|
|
|
|
Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
|
|
|
|
|
|
/* Description BUFFER_ADDR_39_32
|
|
|
|
Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
|
|
|
|
|
|
/* Description RETURN_BUFFER_MANAGER
|
|
|
|
Consumer: WBM
|
|
Producer: SW/FW
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
Indicates to which buffer manager the buffer OR MSDU_EXTENSION
|
|
descriptor OR link descriptor that is being pointed to
|
|
shall be returned after the frame has been processed. It
|
|
is used by WBM for routing purposes.
|
|
|
|
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
|
|
to the WMB buffer idle list
|
|
<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the WBM idle link descriptor idle list, where the chip
|
|
0 WBM is chosen in case of a multi-chip config
|
|
<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 1 WBM idle link descriptor idle list
|
|
<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 2 WBM idle link descriptor idle list
|
|
<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
|
|
returned to chip 3 WBM idle link descriptor idle list
|
|
<enum 4 FW_BM> This buffer shall be returned to the FW
|
|
<enum 5 SW0_BM> This buffer shall be returned to the SW,
|
|
ring 0
|
|
<enum 6 SW1_BM> This buffer shall be returned to the SW,
|
|
ring 1
|
|
<enum 7 SW2_BM> This buffer shall be returned to the SW,
|
|
ring 2
|
|
<enum 8 SW3_BM> This buffer shall be returned to the SW,
|
|
ring 3
|
|
<enum 9 SW4_BM> This buffer shall be returned to the SW,
|
|
ring 4
|
|
<enum 10 SW5_BM> This buffer shall be returned to the SW,
|
|
ring 5
|
|
<enum 11 SW6_BM> This buffer shall be returned to the SW,
|
|
ring 6
|
|
|
|
<legal 0-12>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
|
|
|
|
|
/* Description SW_BUFFER_COOKIE
|
|
|
|
Cookie field exclusively used by SW.
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
HW ignores the contents, accept that it passes the programmed
|
|
value on to other descriptors together with the physical
|
|
address
|
|
|
|
Field can be used by SW to for example associate the buffers
|
|
physical address with the virtual address
|
|
The bit definitions as used by SW are within SW HLD specification
|
|
|
|
|
|
NOTE1:
|
|
The three most significant bits can have a special meaning
|
|
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
|
|
and field transmit_bw_restriction is set
|
|
|
|
In case of NON punctured transmission:
|
|
Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
In case of punctured transmission:
|
|
Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
|
|
Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
|
|
Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
|
|
Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
|
|
Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
|
|
Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
|
|
Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
|
|
Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
|
|
Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
|
|
Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
|
|
Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
|
|
Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
Note: a punctured transmission is indicated by the presence
|
|
of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
|
|
|
|
|
|
/* Description MPDU_LINK_POINTER_10
|
|
|
|
Consumer: REO
|
|
Producer: REO
|
|
|
|
Pointer to the next MPDU_link descriptor in the MPDU queue
|
|
|
|
*/
|
|
|
|
|
|
/* Description MPDU_LINK_DESC_ADDR_INFO
|
|
|
|
Details of the physical address of an MPDU link descriptor
|
|
|
|
*/
|
|
|
|
|
|
/* Description BUFFER_ADDR_31_0
|
|
|
|
Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
|
|
|
|
|
|
/* Description BUFFER_ADDR_39_32
|
|
|
|
Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
|
|
|
|
|
|
/* Description RETURN_BUFFER_MANAGER
|
|
|
|
Consumer: WBM
|
|
Producer: SW/FW
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
Indicates to which buffer manager the buffer OR MSDU_EXTENSION
|
|
descriptor OR link descriptor that is being pointed to
|
|
shall be returned after the frame has been processed. It
|
|
is used by WBM for routing purposes.
|
|
|
|
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
|
|
to the WMB buffer idle list
|
|
<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the WBM idle link descriptor idle list, where the chip
|
|
0 WBM is chosen in case of a multi-chip config
|
|
<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 1 WBM idle link descriptor idle list
|
|
<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 2 WBM idle link descriptor idle list
|
|
<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
|
|
returned to chip 3 WBM idle link descriptor idle list
|
|
<enum 4 FW_BM> This buffer shall be returned to the FW
|
|
<enum 5 SW0_BM> This buffer shall be returned to the SW,
|
|
ring 0
|
|
<enum 6 SW1_BM> This buffer shall be returned to the SW,
|
|
ring 1
|
|
<enum 7 SW2_BM> This buffer shall be returned to the SW,
|
|
ring 2
|
|
<enum 8 SW3_BM> This buffer shall be returned to the SW,
|
|
ring 3
|
|
<enum 9 SW4_BM> This buffer shall be returned to the SW,
|
|
ring 4
|
|
<enum 10 SW5_BM> This buffer shall be returned to the SW,
|
|
ring 5
|
|
<enum 11 SW6_BM> This buffer shall be returned to the SW,
|
|
ring 6
|
|
|
|
<legal 0-12>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
|
|
|
|
|
/* Description SW_BUFFER_COOKIE
|
|
|
|
Cookie field exclusively used by SW.
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
HW ignores the contents, accept that it passes the programmed
|
|
value on to other descriptors together with the physical
|
|
address
|
|
|
|
Field can be used by SW to for example associate the buffers
|
|
physical address with the virtual address
|
|
The bit definitions as used by SW are within SW HLD specification
|
|
|
|
|
|
NOTE1:
|
|
The three most significant bits can have a special meaning
|
|
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
|
|
and field transmit_bw_restriction is set
|
|
|
|
In case of NON punctured transmission:
|
|
Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
In case of punctured transmission:
|
|
Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
|
|
Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
|
|
Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
|
|
Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
|
|
Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
|
|
Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
|
|
Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
|
|
Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
|
|
Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
|
|
Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
|
|
Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
|
|
Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
Note: a punctured transmission is indicated by the presence
|
|
of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
|
|
|
|
|
|
/* Description MPDU_LINK_POINTER_11
|
|
|
|
Consumer: REO
|
|
Producer: REO
|
|
|
|
Pointer to the next MPDU_link descriptor in the MPDU queue
|
|
|
|
*/
|
|
|
|
|
|
/* Description MPDU_LINK_DESC_ADDR_INFO
|
|
|
|
Details of the physical address of an MPDU link descriptor
|
|
|
|
*/
|
|
|
|
|
|
/* Description BUFFER_ADDR_31_0
|
|
|
|
Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
|
|
|
|
|
|
/* Description BUFFER_ADDR_39_32
|
|
|
|
Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
|
|
|
|
|
|
/* Description RETURN_BUFFER_MANAGER
|
|
|
|
Consumer: WBM
|
|
Producer: SW/FW
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
Indicates to which buffer manager the buffer OR MSDU_EXTENSION
|
|
descriptor OR link descriptor that is being pointed to
|
|
shall be returned after the frame has been processed. It
|
|
is used by WBM for routing purposes.
|
|
|
|
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
|
|
to the WMB buffer idle list
|
|
<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the WBM idle link descriptor idle list, where the chip
|
|
0 WBM is chosen in case of a multi-chip config
|
|
<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 1 WBM idle link descriptor idle list
|
|
<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 2 WBM idle link descriptor idle list
|
|
<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
|
|
returned to chip 3 WBM idle link descriptor idle list
|
|
<enum 4 FW_BM> This buffer shall be returned to the FW
|
|
<enum 5 SW0_BM> This buffer shall be returned to the SW,
|
|
ring 0
|
|
<enum 6 SW1_BM> This buffer shall be returned to the SW,
|
|
ring 1
|
|
<enum 7 SW2_BM> This buffer shall be returned to the SW,
|
|
ring 2
|
|
<enum 8 SW3_BM> This buffer shall be returned to the SW,
|
|
ring 3
|
|
<enum 9 SW4_BM> This buffer shall be returned to the SW,
|
|
ring 4
|
|
<enum 10 SW5_BM> This buffer shall be returned to the SW,
|
|
ring 5
|
|
<enum 11 SW6_BM> This buffer shall be returned to the SW,
|
|
ring 6
|
|
|
|
<legal 0-12>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
|
|
|
|
|
/* Description SW_BUFFER_COOKIE
|
|
|
|
Cookie field exclusively used by SW.
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
HW ignores the contents, accept that it passes the programmed
|
|
value on to other descriptors together with the physical
|
|
address
|
|
|
|
Field can be used by SW to for example associate the buffers
|
|
physical address with the virtual address
|
|
The bit definitions as used by SW are within SW HLD specification
|
|
|
|
|
|
NOTE1:
|
|
The three most significant bits can have a special meaning
|
|
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
|
|
and field transmit_bw_restriction is set
|
|
|
|
In case of NON punctured transmission:
|
|
Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
In case of punctured transmission:
|
|
Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
|
|
Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
|
|
Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
|
|
Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
|
|
Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
|
|
Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
|
|
Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
|
|
Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
|
|
Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
|
|
Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
|
|
Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
|
|
Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
Note: a punctured transmission is indicated by the presence
|
|
of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
|
|
|
|
|
|
/* Description MPDU_LINK_POINTER_12
|
|
|
|
Consumer: REO
|
|
Producer: REO
|
|
|
|
Pointer to the next MPDU_link descriptor in the MPDU queue
|
|
|
|
*/
|
|
|
|
|
|
/* Description MPDU_LINK_DESC_ADDR_INFO
|
|
|
|
Details of the physical address of an MPDU link descriptor
|
|
|
|
*/
|
|
|
|
|
|
/* Description BUFFER_ADDR_31_0
|
|
|
|
Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
|
|
|
|
|
|
/* Description BUFFER_ADDR_39_32
|
|
|
|
Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
|
|
|
|
|
|
/* Description RETURN_BUFFER_MANAGER
|
|
|
|
Consumer: WBM
|
|
Producer: SW/FW
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
Indicates to which buffer manager the buffer OR MSDU_EXTENSION
|
|
descriptor OR link descriptor that is being pointed to
|
|
shall be returned after the frame has been processed. It
|
|
is used by WBM for routing purposes.
|
|
|
|
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
|
|
to the WMB buffer idle list
|
|
<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the WBM idle link descriptor idle list, where the chip
|
|
0 WBM is chosen in case of a multi-chip config
|
|
<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 1 WBM idle link descriptor idle list
|
|
<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 2 WBM idle link descriptor idle list
|
|
<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
|
|
returned to chip 3 WBM idle link descriptor idle list
|
|
<enum 4 FW_BM> This buffer shall be returned to the FW
|
|
<enum 5 SW0_BM> This buffer shall be returned to the SW,
|
|
ring 0
|
|
<enum 6 SW1_BM> This buffer shall be returned to the SW,
|
|
ring 1
|
|
<enum 7 SW2_BM> This buffer shall be returned to the SW,
|
|
ring 2
|
|
<enum 8 SW3_BM> This buffer shall be returned to the SW,
|
|
ring 3
|
|
<enum 9 SW4_BM> This buffer shall be returned to the SW,
|
|
ring 4
|
|
<enum 10 SW5_BM> This buffer shall be returned to the SW,
|
|
ring 5
|
|
<enum 11 SW6_BM> This buffer shall be returned to the SW,
|
|
ring 6
|
|
|
|
<legal 0-12>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
|
|
|
|
|
/* Description SW_BUFFER_COOKIE
|
|
|
|
Cookie field exclusively used by SW.
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
HW ignores the contents, accept that it passes the programmed
|
|
value on to other descriptors together with the physical
|
|
address
|
|
|
|
Field can be used by SW to for example associate the buffers
|
|
physical address with the virtual address
|
|
The bit definitions as used by SW are within SW HLD specification
|
|
|
|
|
|
NOTE1:
|
|
The three most significant bits can have a special meaning
|
|
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
|
|
and field transmit_bw_restriction is set
|
|
|
|
In case of NON punctured transmission:
|
|
Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
In case of punctured transmission:
|
|
Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
|
|
Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
|
|
Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
|
|
Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
|
|
Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
|
|
Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
|
|
Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
|
|
Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
|
|
Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
|
|
Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
|
|
Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
|
|
Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
Note: a punctured transmission is indicated by the presence
|
|
of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
|
|
|
|
|
|
/* Description MPDU_LINK_POINTER_13
|
|
|
|
Consumer: REO
|
|
Producer: REO
|
|
|
|
Pointer to the next MPDU_link descriptor in the MPDU queue
|
|
|
|
*/
|
|
|
|
|
|
/* Description MPDU_LINK_DESC_ADDR_INFO
|
|
|
|
Details of the physical address of an MPDU link descriptor
|
|
|
|
*/
|
|
|
|
|
|
/* Description BUFFER_ADDR_31_0
|
|
|
|
Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
|
|
|
|
|
|
/* Description BUFFER_ADDR_39_32
|
|
|
|
Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
|
|
|
|
|
|
/* Description RETURN_BUFFER_MANAGER
|
|
|
|
Consumer: WBM
|
|
Producer: SW/FW
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
Indicates to which buffer manager the buffer OR MSDU_EXTENSION
|
|
descriptor OR link descriptor that is being pointed to
|
|
shall be returned after the frame has been processed. It
|
|
is used by WBM for routing purposes.
|
|
|
|
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
|
|
to the WMB buffer idle list
|
|
<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the WBM idle link descriptor idle list, where the chip
|
|
0 WBM is chosen in case of a multi-chip config
|
|
<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 1 WBM idle link descriptor idle list
|
|
<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 2 WBM idle link descriptor idle list
|
|
<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
|
|
returned to chip 3 WBM idle link descriptor idle list
|
|
<enum 4 FW_BM> This buffer shall be returned to the FW
|
|
<enum 5 SW0_BM> This buffer shall be returned to the SW,
|
|
ring 0
|
|
<enum 6 SW1_BM> This buffer shall be returned to the SW,
|
|
ring 1
|
|
<enum 7 SW2_BM> This buffer shall be returned to the SW,
|
|
ring 2
|
|
<enum 8 SW3_BM> This buffer shall be returned to the SW,
|
|
ring 3
|
|
<enum 9 SW4_BM> This buffer shall be returned to the SW,
|
|
ring 4
|
|
<enum 10 SW5_BM> This buffer shall be returned to the SW,
|
|
ring 5
|
|
<enum 11 SW6_BM> This buffer shall be returned to the SW,
|
|
ring 6
|
|
|
|
<legal 0-12>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
|
|
|
|
|
/* Description SW_BUFFER_COOKIE
|
|
|
|
Cookie field exclusively used by SW.
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
HW ignores the contents, accept that it passes the programmed
|
|
value on to other descriptors together with the physical
|
|
address
|
|
|
|
Field can be used by SW to for example associate the buffers
|
|
physical address with the virtual address
|
|
The bit definitions as used by SW are within SW HLD specification
|
|
|
|
|
|
NOTE1:
|
|
The three most significant bits can have a special meaning
|
|
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
|
|
and field transmit_bw_restriction is set
|
|
|
|
In case of NON punctured transmission:
|
|
Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
In case of punctured transmission:
|
|
Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
|
|
Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
|
|
Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
|
|
Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
|
|
Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
|
|
Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
|
|
Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
|
|
Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
|
|
Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
|
|
Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
|
|
Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
|
|
Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
Note: a punctured transmission is indicated by the presence
|
|
of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
|
|
|
|
|
|
/* Description MPDU_LINK_POINTER_14
|
|
|
|
Consumer: REO
|
|
Producer: REO
|
|
|
|
Pointer to the next MPDU_link descriptor in the MPDU queue
|
|
|
|
*/
|
|
|
|
|
|
/* Description MPDU_LINK_DESC_ADDR_INFO
|
|
|
|
Details of the physical address of an MPDU link descriptor
|
|
|
|
*/
|
|
|
|
|
|
/* Description BUFFER_ADDR_31_0
|
|
|
|
Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
|
|
|
|
|
|
/* Description BUFFER_ADDR_39_32
|
|
|
|
Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
|
|
descriptor OR Link Descriptor
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
|
|
|
|
|
|
/* Description RETURN_BUFFER_MANAGER
|
|
|
|
Consumer: WBM
|
|
Producer: SW/FW
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
Indicates to which buffer manager the buffer OR MSDU_EXTENSION
|
|
descriptor OR link descriptor that is being pointed to
|
|
shall be returned after the frame has been processed. It
|
|
is used by WBM for routing purposes.
|
|
|
|
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
|
|
to the WMB buffer idle list
|
|
<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the WBM idle link descriptor idle list, where the chip
|
|
0 WBM is chosen in case of a multi-chip config
|
|
<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 1 WBM idle link descriptor idle list
|
|
<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
|
|
to the chip 2 WBM idle link descriptor idle list
|
|
<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
|
|
returned to chip 3 WBM idle link descriptor idle list
|
|
<enum 4 FW_BM> This buffer shall be returned to the FW
|
|
<enum 5 SW0_BM> This buffer shall be returned to the SW,
|
|
ring 0
|
|
<enum 6 SW1_BM> This buffer shall be returned to the SW,
|
|
ring 1
|
|
<enum 7 SW2_BM> This buffer shall be returned to the SW,
|
|
ring 2
|
|
<enum 8 SW3_BM> This buffer shall be returned to the SW,
|
|
ring 3
|
|
<enum 9 SW4_BM> This buffer shall be returned to the SW,
|
|
ring 4
|
|
<enum 10 SW5_BM> This buffer shall be returned to the SW,
|
|
ring 5
|
|
<enum 11 SW6_BM> This buffer shall be returned to the SW,
|
|
ring 6
|
|
|
|
<legal 0-12>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
|
|
|
|
|
/* Description SW_BUFFER_COOKIE
|
|
|
|
Cookie field exclusively used by SW.
|
|
|
|
In case of 'NULL' pointer, this field is set to 0
|
|
|
|
HW ignores the contents, accept that it passes the programmed
|
|
value on to other descriptors together with the physical
|
|
address
|
|
|
|
Field can be used by SW to for example associate the buffers
|
|
physical address with the virtual address
|
|
The bit definitions as used by SW are within SW HLD specification
|
|
|
|
|
|
NOTE1:
|
|
The three most significant bits can have a special meaning
|
|
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
|
|
and field transmit_bw_restriction is set
|
|
|
|
In case of NON punctured transmission:
|
|
Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
|
|
Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
In case of punctured transmission:
|
|
Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
|
|
Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
|
|
Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
|
|
Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
|
|
Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
|
|
Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
|
|
Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
|
|
Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
|
|
Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
|
|
Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
|
|
Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
|
|
Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
|
|
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
|
|
|
Note: a punctured transmission is indicated by the presence
|
|
of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
|
|
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
|
|
|
|
|
|
|
|
#endif // RX_REO_QUEUE_EXT
|