sde_encoder.c 140 KB

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  1. /*
  2. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/kthread.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/input.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/sde_rsc.h>
  24. #include "msm_drv.h"
  25. #include "sde_kms.h"
  26. #include <drm/drm_crtc.h>
  27. #include <drm/drm_probe_helper.h>
  28. #include "sde_hwio.h"
  29. #include "sde_hw_catalog.h"
  30. #include "sde_hw_intf.h"
  31. #include "sde_hw_ctl.h"
  32. #include "sde_formats.h"
  33. #include "sde_encoder.h"
  34. #include "sde_encoder_phys.h"
  35. #include "sde_hw_dsc.h"
  36. #include "sde_crtc.h"
  37. #include "sde_trace.h"
  38. #include "sde_core_irq.h"
  39. #include "sde_hw_top.h"
  40. #include "sde_hw_qdss.h"
  41. #include "sde_encoder_dce.h"
  42. #define SDE_DEBUG_ENC(e, fmt, ...) SDE_DEBUG("enc%d " fmt,\
  43. (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  44. #define SDE_ERROR_ENC(e, fmt, ...) SDE_ERROR("enc%d " fmt,\
  45. (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  46. #define SDE_DEBUG_PHYS(p, fmt, ...) SDE_DEBUG("enc%d intf%d pp%d " fmt,\
  47. (p) ? (p)->parent->base.id : -1, \
  48. (p) ? (p)->intf_idx - INTF_0 : -1, \
  49. (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  50. ##__VA_ARGS__)
  51. #define SDE_ERROR_PHYS(p, fmt, ...) SDE_ERROR("enc%d intf%d pp%d " fmt,\
  52. (p) ? (p)->parent->base.id : -1, \
  53. (p) ? (p)->intf_idx - INTF_0 : -1, \
  54. (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  55. ##__VA_ARGS__)
  56. #define MISR_BUFF_SIZE 256
  57. #define IDLE_SHORT_TIMEOUT 1
  58. #define EVT_TIME_OUT_SPLIT 2
  59. /* Maximum number of VSYNC wait attempts for RSC state transition */
  60. #define MAX_RSC_WAIT 5
  61. #define TOPOLOGY_DUALPIPE_MERGE_MODE(x) \
  62. (((x) == SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE) || \
  63. ((x) == SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE) || \
  64. ((x) == SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC))
  65. /**
  66. * enum sde_enc_rc_events - events for resource control state machine
  67. * @SDE_ENC_RC_EVENT_KICKOFF:
  68. * This event happens at NORMAL priority.
  69. * Event that signals the start of the transfer. When this event is
  70. * received, enable MDP/DSI core clocks and request RSC with CMD state.
  71. * Regardless of the previous state, the resource should be in ON state
  72. * at the end of this event.
  73. * @SDE_ENC_RC_EVENT_FRAME_DONE:
  74. * This event happens at INTERRUPT level.
  75. * Event signals the end of the data transfer after the PP FRAME_DONE
  76. * event. At the end of this event, a delayed work is scheduled to go to
  77. * IDLE_PC state after IDLE_POWERCOLLAPSE_DURATION time.
  78. * @SDE_ENC_RC_EVENT_PRE_STOP:
  79. * This event happens at NORMAL priority.
  80. * This event, when received during the ON state, set RSC to IDLE, and
  81. * and leave the RC STATE in the PRE_OFF state.
  82. * It should be followed by the STOP event as part of encoder disable.
  83. * If received during IDLE or OFF states, it will do nothing.
  84. * @SDE_ENC_RC_EVENT_STOP:
  85. * This event happens at NORMAL priority.
  86. * When this event is received, disable all the MDP/DSI core clocks, and
  87. * disable IRQs. It should be called from the PRE_OFF or IDLE states.
  88. * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
  89. * PRE_OFF is expected when PRE_STOP was executed during the ON state.
  90. * Resource state should be in OFF at the end of the event.
  91. * @SDE_ENC_RC_EVENT_PRE_MODESET:
  92. * This event happens at NORMAL priority from a work item.
  93. * Event signals that there is a seamless mode switch is in prgoress. A
  94. * client needs to turn of only irq - leave clocks ON to reduce the mode
  95. * switch latency.
  96. * @SDE_ENC_RC_EVENT_POST_MODESET:
  97. * This event happens at NORMAL priority from a work item.
  98. * Event signals that seamless mode switch is complete and resources are
  99. * acquired. Clients wants to turn on the irq again and update the rsc
  100. * with new vtotal.
  101. * @SDE_ENC_RC_EVENT_ENTER_IDLE:
  102. * This event happens at NORMAL priority from a work item.
  103. * Event signals that there were no frame updates for
  104. * IDLE_POWERCOLLAPSE_DURATION time. This would disable MDP/DSI core clocks
  105. * and request RSC with IDLE state and change the resource state to IDLE.
  106. * @SDE_ENC_RC_EVENT_EARLY_WAKEUP:
  107. * This event is triggered from the input event thread when touch event is
  108. * received from the input device. On receiving this event,
  109. * - If the device is in SDE_ENC_RC_STATE_IDLE state, it turns ON the
  110. clocks and enable RSC.
  111. * - If the device is in SDE_ENC_RC_STATE_ON state, it resets the delayed
  112. * off work since a new commit is imminent.
  113. */
  114. enum sde_enc_rc_events {
  115. SDE_ENC_RC_EVENT_KICKOFF = 1,
  116. SDE_ENC_RC_EVENT_FRAME_DONE,
  117. SDE_ENC_RC_EVENT_PRE_STOP,
  118. SDE_ENC_RC_EVENT_STOP,
  119. SDE_ENC_RC_EVENT_PRE_MODESET,
  120. SDE_ENC_RC_EVENT_POST_MODESET,
  121. SDE_ENC_RC_EVENT_ENTER_IDLE,
  122. SDE_ENC_RC_EVENT_EARLY_WAKEUP,
  123. };
  124. void sde_encoder_uidle_enable(struct drm_encoder *drm_enc, bool enable)
  125. {
  126. struct sde_encoder_virt *sde_enc;
  127. int i;
  128. sde_enc = to_sde_encoder_virt(drm_enc);
  129. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  130. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  131. if (phys && phys->hw_ctl && phys->hw_ctl->ops.uidle_enable) {
  132. SDE_EVT32(DRMID(drm_enc), enable);
  133. phys->hw_ctl->ops.uidle_enable(phys->hw_ctl, enable);
  134. }
  135. }
  136. }
  137. static bool _sde_encoder_is_autorefresh_enabled(
  138. struct sde_encoder_virt *sde_enc)
  139. {
  140. struct drm_connector *drm_conn;
  141. if (!sde_enc->cur_master ||
  142. !(sde_enc->disp_info.capabilities & MSM_DISPLAY_CAP_CMD_MODE))
  143. return false;
  144. drm_conn = sde_enc->cur_master->connector;
  145. if (!drm_conn || !drm_conn->state)
  146. return false;
  147. return sde_connector_get_property(drm_conn->state,
  148. CONNECTOR_PROP_AUTOREFRESH) ? true : false;
  149. }
  150. static void sde_configure_qdss(struct sde_encoder_virt *sde_enc,
  151. struct sde_hw_qdss *hw_qdss,
  152. struct sde_encoder_phys *phys, bool enable)
  153. {
  154. if (sde_enc->qdss_status == enable)
  155. return;
  156. sde_enc->qdss_status = enable;
  157. phys->hw_mdptop->ops.set_mdp_hw_events(phys->hw_mdptop,
  158. sde_enc->qdss_status);
  159. hw_qdss->ops.enable_qdss_events(hw_qdss, sde_enc->qdss_status);
  160. }
  161. static int _sde_encoder_wait_timeout(int32_t drm_id, int32_t hw_id,
  162. s64 timeout_ms, struct sde_encoder_wait_info *info)
  163. {
  164. int rc = 0;
  165. s64 wait_time_jiffies = msecs_to_jiffies(timeout_ms);
  166. ktime_t cur_ktime;
  167. ktime_t exp_ktime = ktime_add_ms(ktime_get(), timeout_ms);
  168. do {
  169. rc = wait_event_timeout(*(info->wq),
  170. atomic_read(info->atomic_cnt) == info->count_check,
  171. wait_time_jiffies);
  172. cur_ktime = ktime_get();
  173. SDE_EVT32(drm_id, hw_id, rc, ktime_to_ms(cur_ktime),
  174. timeout_ms, atomic_read(info->atomic_cnt),
  175. info->count_check);
  176. /* If we timed out, counter is valid and time is less, wait again */
  177. } while ((atomic_read(info->atomic_cnt) != info->count_check) &&
  178. (rc == 0) &&
  179. (ktime_compare_safe(exp_ktime, cur_ktime) > 0));
  180. return rc;
  181. }
  182. bool sde_encoder_is_primary_display(struct drm_encoder *drm_enc)
  183. {
  184. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  185. return sde_enc &&
  186. (sde_enc->disp_info.display_type ==
  187. SDE_CONNECTOR_PRIMARY);
  188. }
  189. bool sde_encoder_is_dsi_display(struct drm_encoder *drm_enc)
  190. {
  191. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  192. return sde_enc &&
  193. (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI);
  194. }
  195. int sde_encoder_in_cont_splash(struct drm_encoder *drm_enc)
  196. {
  197. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  198. return sde_enc && sde_enc->cur_master &&
  199. sde_enc->cur_master->cont_splash_enabled;
  200. }
  201. void sde_encoder_helper_report_irq_timeout(struct sde_encoder_phys *phys_enc,
  202. enum sde_intr_idx intr_idx)
  203. {
  204. SDE_EVT32(DRMID(phys_enc->parent),
  205. phys_enc->intf_idx - INTF_0,
  206. phys_enc->hw_pp->idx - PINGPONG_0,
  207. intr_idx);
  208. SDE_ERROR_PHYS(phys_enc, "irq %d timeout\n", intr_idx);
  209. if (phys_enc->parent_ops.handle_frame_done)
  210. phys_enc->parent_ops.handle_frame_done(
  211. phys_enc->parent, phys_enc,
  212. SDE_ENCODER_FRAME_EVENT_ERROR);
  213. }
  214. int sde_encoder_helper_wait_for_irq(struct sde_encoder_phys *phys_enc,
  215. enum sde_intr_idx intr_idx,
  216. struct sde_encoder_wait_info *wait_info)
  217. {
  218. struct sde_encoder_irq *irq;
  219. u32 irq_status;
  220. int ret, i;
  221. if (!phys_enc || !wait_info || intr_idx >= INTR_IDX_MAX) {
  222. SDE_ERROR("invalid params\n");
  223. return -EINVAL;
  224. }
  225. irq = &phys_enc->irq[intr_idx];
  226. /* note: do master / slave checking outside */
  227. /* return EWOULDBLOCK since we know the wait isn't necessary */
  228. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  229. SDE_ERROR_PHYS(phys_enc, "encoder is disabled\n");
  230. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  231. irq->irq_idx, intr_idx, SDE_EVTLOG_ERROR);
  232. return -EWOULDBLOCK;
  233. }
  234. if (irq->irq_idx < 0) {
  235. SDE_DEBUG_PHYS(phys_enc, "irq %s hw %d disabled, skip wait\n",
  236. irq->name, irq->hw_idx);
  237. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  238. irq->irq_idx);
  239. return 0;
  240. }
  241. SDE_DEBUG_PHYS(phys_enc, "pending_cnt %d\n",
  242. atomic_read(wait_info->atomic_cnt));
  243. SDE_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  244. irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
  245. atomic_read(wait_info->atomic_cnt), SDE_EVTLOG_FUNC_ENTRY);
  246. /*
  247. * Some module X may disable interrupt for longer duration
  248. * and it may trigger all interrupts including timer interrupt
  249. * when module X again enable the interrupt.
  250. * That may cause interrupt wait timeout API in this API.
  251. * It is handled by split the wait timer in two halves.
  252. */
  253. for (i = 0; i < EVT_TIME_OUT_SPLIT; i++) {
  254. ret = _sde_encoder_wait_timeout(DRMID(phys_enc->parent),
  255. irq->hw_idx,
  256. (wait_info->timeout_ms/EVT_TIME_OUT_SPLIT),
  257. wait_info);
  258. if (ret)
  259. break;
  260. }
  261. if (ret <= 0) {
  262. irq_status = sde_core_irq_read(phys_enc->sde_kms,
  263. irq->irq_idx, true);
  264. if (irq_status) {
  265. unsigned long flags;
  266. SDE_EVT32(DRMID(phys_enc->parent), intr_idx,
  267. irq->hw_idx, irq->irq_idx,
  268. phys_enc->hw_pp->idx - PINGPONG_0,
  269. atomic_read(wait_info->atomic_cnt));
  270. SDE_DEBUG_PHYS(phys_enc,
  271. "done but irq %d not triggered\n",
  272. irq->irq_idx);
  273. local_irq_save(flags);
  274. irq->cb.func(phys_enc, irq->irq_idx);
  275. local_irq_restore(flags);
  276. ret = 0;
  277. } else {
  278. ret = -ETIMEDOUT;
  279. SDE_EVT32(DRMID(phys_enc->parent), intr_idx,
  280. irq->hw_idx, irq->irq_idx,
  281. phys_enc->hw_pp->idx - PINGPONG_0,
  282. atomic_read(wait_info->atomic_cnt), irq_status,
  283. SDE_EVTLOG_ERROR);
  284. }
  285. } else {
  286. ret = 0;
  287. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  288. irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
  289. atomic_read(wait_info->atomic_cnt));
  290. }
  291. SDE_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  292. irq->irq_idx, ret, phys_enc->hw_pp->idx - PINGPONG_0,
  293. atomic_read(wait_info->atomic_cnt), SDE_EVTLOG_FUNC_EXIT);
  294. return ret;
  295. }
  296. int sde_encoder_helper_register_irq(struct sde_encoder_phys *phys_enc,
  297. enum sde_intr_idx intr_idx)
  298. {
  299. struct sde_encoder_irq *irq;
  300. int ret = 0;
  301. if (!phys_enc || intr_idx >= INTR_IDX_MAX) {
  302. SDE_ERROR("invalid params\n");
  303. return -EINVAL;
  304. }
  305. irq = &phys_enc->irq[intr_idx];
  306. if (irq->irq_idx >= 0) {
  307. SDE_DEBUG_PHYS(phys_enc,
  308. "skipping already registered irq %s type %d\n",
  309. irq->name, irq->intr_type);
  310. return 0;
  311. }
  312. irq->irq_idx = sde_core_irq_idx_lookup(phys_enc->sde_kms,
  313. irq->intr_type, irq->hw_idx);
  314. if (irq->irq_idx < 0) {
  315. SDE_ERROR_PHYS(phys_enc,
  316. "failed to lookup IRQ index for %s type:%d\n",
  317. irq->name, irq->intr_type);
  318. return -EINVAL;
  319. }
  320. ret = sde_core_irq_register_callback(phys_enc->sde_kms, irq->irq_idx,
  321. &irq->cb);
  322. if (ret) {
  323. SDE_ERROR_PHYS(phys_enc,
  324. "failed to register IRQ callback for %s\n",
  325. irq->name);
  326. irq->irq_idx = -EINVAL;
  327. return ret;
  328. }
  329. ret = sde_core_irq_enable(phys_enc->sde_kms, &irq->irq_idx, 1);
  330. if (ret) {
  331. SDE_ERROR_PHYS(phys_enc,
  332. "enable IRQ for intr:%s failed, irq_idx %d\n",
  333. irq->name, irq->irq_idx);
  334. sde_core_irq_unregister_callback(phys_enc->sde_kms,
  335. irq->irq_idx, &irq->cb);
  336. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  337. irq->irq_idx, SDE_EVTLOG_ERROR);
  338. irq->irq_idx = -EINVAL;
  339. return ret;
  340. }
  341. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
  342. SDE_DEBUG_PHYS(phys_enc, "registered irq %s idx: %d\n",
  343. irq->name, irq->irq_idx);
  344. return ret;
  345. }
  346. int sde_encoder_helper_unregister_irq(struct sde_encoder_phys *phys_enc,
  347. enum sde_intr_idx intr_idx)
  348. {
  349. struct sde_encoder_irq *irq;
  350. int ret;
  351. if (!phys_enc) {
  352. SDE_ERROR("invalid encoder\n");
  353. return -EINVAL;
  354. }
  355. irq = &phys_enc->irq[intr_idx];
  356. /* silently skip irqs that weren't registered */
  357. if (irq->irq_idx < 0) {
  358. SDE_ERROR(
  359. "extra unregister irq, enc%d intr_idx:0x%x hw_idx:0x%x irq_idx:0x%x\n",
  360. DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  361. irq->irq_idx);
  362. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  363. irq->irq_idx, SDE_EVTLOG_ERROR);
  364. return 0;
  365. }
  366. ret = sde_core_irq_disable(phys_enc->sde_kms, &irq->irq_idx, 1);
  367. if (ret)
  368. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  369. irq->irq_idx, ret, SDE_EVTLOG_ERROR);
  370. ret = sde_core_irq_unregister_callback(phys_enc->sde_kms, irq->irq_idx,
  371. &irq->cb);
  372. if (ret)
  373. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  374. irq->irq_idx, ret, SDE_EVTLOG_ERROR);
  375. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
  376. SDE_DEBUG_PHYS(phys_enc, "unregistered %d\n", irq->irq_idx);
  377. irq->irq_idx = -EINVAL;
  378. return 0;
  379. }
  380. void sde_encoder_get_hw_resources(struct drm_encoder *drm_enc,
  381. struct sde_encoder_hw_resources *hw_res,
  382. struct drm_connector_state *conn_state)
  383. {
  384. struct sde_encoder_virt *sde_enc = NULL;
  385. struct msm_mode_info mode_info;
  386. int i = 0;
  387. if (!hw_res || !drm_enc || !conn_state) {
  388. SDE_ERROR("invalid argument(s), drm_enc %d, res %d, state %d\n",
  389. !drm_enc, !hw_res, !conn_state);
  390. return;
  391. }
  392. sde_enc = to_sde_encoder_virt(drm_enc);
  393. SDE_DEBUG_ENC(sde_enc, "\n");
  394. /* Query resources used by phys encs, expected to be without overlap */
  395. memset(hw_res, 0, sizeof(*hw_res));
  396. hw_res->display_num_of_h_tiles = sde_enc->display_num_of_h_tiles;
  397. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  398. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  399. if (phys && phys->ops.get_hw_resources)
  400. phys->ops.get_hw_resources(phys, hw_res, conn_state);
  401. }
  402. /*
  403. * NOTE: Do not use sde_encoder_get_mode_info here as this function is
  404. * called from atomic_check phase. Use the below API to get mode
  405. * information of the temporary conn_state passed
  406. */
  407. sde_connector_state_get_mode_info(conn_state, &mode_info);
  408. hw_res->topology = mode_info.topology;
  409. hw_res->display_type = sde_enc->disp_info.display_type;
  410. }
  411. void sde_encoder_destroy(struct drm_encoder *drm_enc)
  412. {
  413. struct sde_encoder_virt *sde_enc = NULL;
  414. int i = 0;
  415. if (!drm_enc) {
  416. SDE_ERROR("invalid encoder\n");
  417. return;
  418. }
  419. sde_enc = to_sde_encoder_virt(drm_enc);
  420. SDE_DEBUG_ENC(sde_enc, "\n");
  421. mutex_lock(&sde_enc->enc_lock);
  422. sde_rsc_client_destroy(sde_enc->rsc_client);
  423. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  424. struct sde_encoder_phys *phys;
  425. phys = sde_enc->phys_vid_encs[i];
  426. if (phys && phys->ops.destroy) {
  427. phys->ops.destroy(phys);
  428. --sde_enc->num_phys_encs;
  429. sde_enc->phys_encs[i] = NULL;
  430. }
  431. phys = sde_enc->phys_cmd_encs[i];
  432. if (phys && phys->ops.destroy) {
  433. phys->ops.destroy(phys);
  434. --sde_enc->num_phys_encs;
  435. sde_enc->phys_encs[i] = NULL;
  436. }
  437. }
  438. if (sde_enc->num_phys_encs)
  439. SDE_ERROR_ENC(sde_enc, "expected 0 num_phys_encs not %d\n",
  440. sde_enc->num_phys_encs);
  441. sde_enc->num_phys_encs = 0;
  442. mutex_unlock(&sde_enc->enc_lock);
  443. drm_encoder_cleanup(drm_enc);
  444. mutex_destroy(&sde_enc->enc_lock);
  445. kfree(sde_enc->input_handler);
  446. sde_enc->input_handler = NULL;
  447. kfree(sde_enc);
  448. }
  449. void sde_encoder_helper_update_intf_cfg(
  450. struct sde_encoder_phys *phys_enc)
  451. {
  452. struct sde_encoder_virt *sde_enc;
  453. struct sde_hw_intf_cfg_v1 *intf_cfg;
  454. enum sde_3d_blend_mode mode_3d;
  455. if (!phys_enc || !phys_enc->hw_pp) {
  456. SDE_ERROR("invalid args, encoder %d\n", !phys_enc);
  457. return;
  458. }
  459. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  460. intf_cfg = &sde_enc->cur_master->intf_cfg_v1;
  461. SDE_DEBUG_ENC(sde_enc,
  462. "intf_cfg updated for %d at idx %d\n",
  463. phys_enc->intf_idx,
  464. intf_cfg->intf_count);
  465. /* setup interface configuration */
  466. if (intf_cfg->intf_count >= MAX_INTF_PER_CTL_V1) {
  467. pr_err("invalid inf_count %d\n", intf_cfg->intf_count);
  468. return;
  469. }
  470. intf_cfg->intf[intf_cfg->intf_count++] = phys_enc->intf_idx;
  471. if (phys_enc == sde_enc->cur_master) {
  472. if (sde_enc->cur_master->intf_mode == INTF_MODE_CMD)
  473. intf_cfg->intf_mode_sel = SDE_CTL_MODE_SEL_CMD;
  474. else
  475. intf_cfg->intf_mode_sel = SDE_CTL_MODE_SEL_VID;
  476. }
  477. /* configure this interface as master for split display */
  478. if (phys_enc->split_role == ENC_ROLE_MASTER)
  479. intf_cfg->intf_master = phys_enc->hw_intf->idx;
  480. /* setup which pp blk will connect to this intf */
  481. if (phys_enc->hw_intf->ops.bind_pingpong_blk)
  482. phys_enc->hw_intf->ops.bind_pingpong_blk(
  483. phys_enc->hw_intf,
  484. true,
  485. phys_enc->hw_pp->idx);
  486. /*setup merge_3d configuration */
  487. mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
  488. if (mode_3d && phys_enc->hw_pp->merge_3d &&
  489. intf_cfg->merge_3d_count < MAX_MERGE_3D_PER_CTL_V1)
  490. intf_cfg->merge_3d[intf_cfg->merge_3d_count++] =
  491. phys_enc->hw_pp->merge_3d->idx;
  492. if (phys_enc->hw_pp->ops.setup_3d_mode)
  493. phys_enc->hw_pp->ops.setup_3d_mode(phys_enc->hw_pp,
  494. mode_3d);
  495. }
  496. void sde_encoder_helper_split_config(
  497. struct sde_encoder_phys *phys_enc,
  498. enum sde_intf interface)
  499. {
  500. struct sde_encoder_virt *sde_enc;
  501. struct split_pipe_cfg *cfg;
  502. struct sde_hw_mdp *hw_mdptop;
  503. enum sde_rm_topology_name topology;
  504. struct msm_display_info *disp_info;
  505. if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
  506. SDE_ERROR("invalid arg(s), encoder %d\n", !phys_enc);
  507. return;
  508. }
  509. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  510. hw_mdptop = phys_enc->hw_mdptop;
  511. disp_info = &sde_enc->disp_info;
  512. cfg = &phys_enc->hw_intf->cfg;
  513. memset(cfg, 0, sizeof(*cfg));
  514. if (disp_info->intf_type != DRM_MODE_CONNECTOR_DSI)
  515. return;
  516. if (disp_info->capabilities & MSM_DISPLAY_SPLIT_LINK)
  517. cfg->split_link_en = true;
  518. /**
  519. * disable split modes since encoder will be operating in as the only
  520. * encoder, either for the entire use case in the case of, for example,
  521. * single DSI, or for this frame in the case of left/right only partial
  522. * update.
  523. */
  524. if (phys_enc->split_role == ENC_ROLE_SOLO) {
  525. if (hw_mdptop->ops.setup_split_pipe)
  526. hw_mdptop->ops.setup_split_pipe(hw_mdptop, cfg);
  527. if (hw_mdptop->ops.setup_pp_split)
  528. hw_mdptop->ops.setup_pp_split(hw_mdptop, cfg);
  529. return;
  530. }
  531. cfg->en = true;
  532. cfg->mode = phys_enc->intf_mode;
  533. cfg->intf = interface;
  534. if (cfg->en && phys_enc->ops.needs_single_flush &&
  535. phys_enc->ops.needs_single_flush(phys_enc))
  536. cfg->split_flush_en = true;
  537. topology = sde_connector_get_topology_name(phys_enc->connector);
  538. if (topology == SDE_RM_TOPOLOGY_PPSPLIT)
  539. cfg->pp_split_slave = cfg->intf;
  540. else
  541. cfg->pp_split_slave = INTF_MAX;
  542. if (phys_enc->split_role == ENC_ROLE_MASTER) {
  543. SDE_DEBUG_ENC(sde_enc, "enable %d\n", cfg->en);
  544. if (hw_mdptop->ops.setup_split_pipe)
  545. hw_mdptop->ops.setup_split_pipe(hw_mdptop, cfg);
  546. } else if (sde_enc->hw_pp[0]) {
  547. /*
  548. * slave encoder
  549. * - determine split index from master index,
  550. * assume master is first pp
  551. */
  552. cfg->pp_split_index = sde_enc->hw_pp[0]->idx - PINGPONG_0;
  553. SDE_DEBUG_ENC(sde_enc, "master using pp%d\n",
  554. cfg->pp_split_index);
  555. if (hw_mdptop->ops.setup_pp_split)
  556. hw_mdptop->ops.setup_pp_split(hw_mdptop, cfg);
  557. }
  558. }
  559. bool sde_encoder_in_clone_mode(struct drm_encoder *drm_enc)
  560. {
  561. struct sde_encoder_virt *sde_enc;
  562. int i = 0;
  563. if (!drm_enc)
  564. return false;
  565. sde_enc = to_sde_encoder_virt(drm_enc);
  566. if (!sde_enc)
  567. return false;
  568. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  569. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  570. if (phys && phys->in_clone_mode)
  571. return true;
  572. }
  573. return false;
  574. }
  575. static int _sde_encoder_atomic_check_phys_enc(struct sde_encoder_virt *sde_enc,
  576. struct drm_crtc_state *crtc_state,
  577. struct drm_connector_state *conn_state)
  578. {
  579. const struct drm_display_mode *mode;
  580. struct drm_display_mode *adj_mode;
  581. int i = 0;
  582. int ret = 0;
  583. mode = &crtc_state->mode;
  584. adj_mode = &crtc_state->adjusted_mode;
  585. /* perform atomic check on the first physical encoder (master) */
  586. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  587. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  588. if (phys && phys->ops.atomic_check)
  589. ret = phys->ops.atomic_check(phys, crtc_state,
  590. conn_state);
  591. else if (phys && phys->ops.mode_fixup)
  592. if (!phys->ops.mode_fixup(phys, mode, adj_mode))
  593. ret = -EINVAL;
  594. if (ret) {
  595. SDE_ERROR_ENC(sde_enc,
  596. "mode unsupported, phys idx %d\n", i);
  597. break;
  598. }
  599. }
  600. return ret;
  601. }
  602. static int _sde_encoder_atomic_check_pu_roi(struct sde_encoder_virt *sde_enc,
  603. struct drm_crtc_state *crtc_state,
  604. struct drm_connector_state *conn_state,
  605. struct sde_connector_state *sde_conn_state,
  606. struct sde_crtc_state *sde_crtc_state)
  607. {
  608. int ret = 0;
  609. if (crtc_state->mode_changed || crtc_state->active_changed) {
  610. struct sde_rect mode_roi, roi;
  611. mode_roi.x = 0;
  612. mode_roi.y = 0;
  613. mode_roi.w = crtc_state->adjusted_mode.hdisplay;
  614. mode_roi.h = crtc_state->adjusted_mode.vdisplay;
  615. if (sde_conn_state->rois.num_rects) {
  616. sde_kms_rect_merge_rectangles(
  617. &sde_conn_state->rois, &roi);
  618. if (!sde_kms_rect_is_equal(&mode_roi, &roi)) {
  619. SDE_ERROR_ENC(sde_enc,
  620. "roi (%d,%d,%d,%d) on connector invalid during modeset\n",
  621. roi.x, roi.y, roi.w, roi.h);
  622. ret = -EINVAL;
  623. }
  624. }
  625. if (sde_crtc_state->user_roi_list.num_rects) {
  626. sde_kms_rect_merge_rectangles(
  627. &sde_crtc_state->user_roi_list, &roi);
  628. if (!sde_kms_rect_is_equal(&mode_roi, &roi)) {
  629. SDE_ERROR_ENC(sde_enc,
  630. "roi (%d,%d,%d,%d) on crtc invalid during modeset\n",
  631. roi.x, roi.y, roi.w, roi.h);
  632. ret = -EINVAL;
  633. }
  634. }
  635. }
  636. return ret;
  637. }
  638. static int _sde_encoder_atomic_check_reserve(struct drm_encoder *drm_enc,
  639. struct drm_crtc_state *crtc_state,
  640. struct drm_connector_state *conn_state,
  641. struct sde_encoder_virt *sde_enc, struct sde_kms *sde_kms,
  642. struct sde_connector *sde_conn,
  643. struct sde_connector_state *sde_conn_state)
  644. {
  645. int ret = 0;
  646. struct drm_display_mode *adj_mode = &crtc_state->adjusted_mode;
  647. if (sde_conn && drm_atomic_crtc_needs_modeset(crtc_state)) {
  648. struct msm_display_topology *topology = NULL;
  649. ret = sde_connector_get_mode_info(&sde_conn->base,
  650. adj_mode, &sde_conn_state->mode_info);
  651. if (ret) {
  652. SDE_ERROR_ENC(sde_enc,
  653. "failed to get mode info, rc = %d\n", ret);
  654. return ret;
  655. }
  656. if (sde_conn_state->mode_info.comp_info.comp_type &&
  657. sde_conn_state->mode_info.comp_info.comp_ratio >=
  658. MSM_DISPLAY_COMPRESSION_RATIO_MAX) {
  659. SDE_ERROR_ENC(sde_enc,
  660. "invalid compression ratio: %d\n",
  661. sde_conn_state->mode_info.comp_info.comp_ratio);
  662. ret = -EINVAL;
  663. return ret;
  664. }
  665. /* Reserve dynamic resources, indicating atomic_check phase */
  666. ret = sde_rm_reserve(&sde_kms->rm, drm_enc, crtc_state,
  667. conn_state, true);
  668. if (ret) {
  669. SDE_ERROR_ENC(sde_enc,
  670. "RM failed to reserve resources, rc = %d\n",
  671. ret);
  672. return ret;
  673. }
  674. /**
  675. * Update connector state with the topology selected for the
  676. * resource set validated. Reset the topology if we are
  677. * de-activating crtc.
  678. */
  679. if (crtc_state->active)
  680. topology = &sde_conn_state->mode_info.topology;
  681. ret = sde_rm_update_topology(conn_state, topology);
  682. if (ret) {
  683. SDE_ERROR_ENC(sde_enc,
  684. "RM failed to update topology, rc: %d\n", ret);
  685. return ret;
  686. }
  687. ret = sde_connector_set_blob_data(conn_state->connector,
  688. conn_state,
  689. CONNECTOR_PROP_SDE_INFO);
  690. if (ret) {
  691. SDE_ERROR_ENC(sde_enc,
  692. "connector failed to update info, rc: %d\n",
  693. ret);
  694. return ret;
  695. }
  696. }
  697. return ret;
  698. }
  699. static int sde_encoder_virt_atomic_check(
  700. struct drm_encoder *drm_enc, struct drm_crtc_state *crtc_state,
  701. struct drm_connector_state *conn_state)
  702. {
  703. struct sde_encoder_virt *sde_enc;
  704. struct msm_drm_private *priv;
  705. struct sde_kms *sde_kms;
  706. const struct drm_display_mode *mode;
  707. struct drm_display_mode *adj_mode;
  708. struct sde_connector *sde_conn = NULL;
  709. struct sde_connector_state *sde_conn_state = NULL;
  710. struct sde_crtc_state *sde_crtc_state = NULL;
  711. enum sde_rm_topology_name old_top;
  712. int ret = 0;
  713. if (!drm_enc || !crtc_state || !conn_state) {
  714. SDE_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
  715. !drm_enc, !crtc_state, !conn_state);
  716. return -EINVAL;
  717. }
  718. sde_enc = to_sde_encoder_virt(drm_enc);
  719. SDE_DEBUG_ENC(sde_enc, "\n");
  720. priv = drm_enc->dev->dev_private;
  721. sde_kms = to_sde_kms(priv->kms);
  722. mode = &crtc_state->mode;
  723. adj_mode = &crtc_state->adjusted_mode;
  724. sde_conn = to_sde_connector(conn_state->connector);
  725. sde_conn_state = to_sde_connector_state(conn_state);
  726. sde_crtc_state = to_sde_crtc_state(crtc_state);
  727. SDE_EVT32(DRMID(drm_enc), drm_atomic_crtc_needs_modeset(crtc_state));
  728. ret = _sde_encoder_atomic_check_phys_enc(sde_enc, crtc_state,
  729. conn_state);
  730. if (ret)
  731. return ret;
  732. ret = _sde_encoder_atomic_check_pu_roi(sde_enc, crtc_state,
  733. conn_state, sde_conn_state, sde_crtc_state);
  734. if (ret)
  735. return ret;
  736. /**
  737. * record topology in previous atomic state to be able to handle
  738. * topology transitions correctly.
  739. */
  740. old_top = sde_connector_get_property(conn_state,
  741. CONNECTOR_PROP_TOPOLOGY_NAME);
  742. ret = sde_connector_set_old_topology_name(conn_state, old_top);
  743. if (ret)
  744. return ret;
  745. ret = _sde_encoder_atomic_check_reserve(drm_enc, crtc_state,
  746. conn_state, sde_enc, sde_kms, sde_conn, sde_conn_state);
  747. if (ret)
  748. return ret;
  749. ret = sde_connector_roi_v1_check_roi(conn_state);
  750. if (ret) {
  751. SDE_ERROR_ENC(sde_enc, "connector roi check failed, rc: %d",
  752. ret);
  753. return ret;
  754. }
  755. drm_mode_set_crtcinfo(adj_mode, 0);
  756. SDE_EVT32(DRMID(drm_enc), adj_mode->flags, adj_mode->private_flags);
  757. return ret;
  758. }
  759. static void _sde_encoder_get_connector_roi(
  760. struct sde_encoder_virt *sde_enc,
  761. struct sde_rect *merged_conn_roi)
  762. {
  763. struct drm_connector *drm_conn;
  764. struct sde_connector_state *c_state;
  765. if (!sde_enc || !merged_conn_roi)
  766. return;
  767. drm_conn = sde_enc->phys_encs[0]->connector;
  768. if (!drm_conn || !drm_conn->state)
  769. return;
  770. c_state = to_sde_connector_state(drm_conn->state);
  771. sde_kms_rect_merge_rectangles(&c_state->rois, merged_conn_roi);
  772. }
  773. static int _sde_encoder_update_roi(struct drm_encoder *drm_enc)
  774. {
  775. struct sde_encoder_virt *sde_enc;
  776. struct drm_connector *drm_conn;
  777. struct drm_display_mode *adj_mode;
  778. struct sde_rect roi;
  779. if (!drm_enc) {
  780. SDE_ERROR("invalid encoder parameter\n");
  781. return -EINVAL;
  782. }
  783. sde_enc = to_sde_encoder_virt(drm_enc);
  784. if (!sde_enc->crtc || !sde_enc->crtc->state) {
  785. SDE_ERROR("invalid crtc parameter\n");
  786. return -EINVAL;
  787. }
  788. if (!sde_enc->cur_master) {
  789. SDE_ERROR("invalid cur_master parameter\n");
  790. return -EINVAL;
  791. }
  792. adj_mode = &sde_enc->cur_master->cached_mode;
  793. drm_conn = sde_enc->cur_master->connector;
  794. _sde_encoder_get_connector_roi(sde_enc, &roi);
  795. if (sde_kms_rect_is_null(&roi)) {
  796. roi.w = adj_mode->hdisplay;
  797. roi.h = adj_mode->vdisplay;
  798. }
  799. memcpy(&sde_enc->prv_conn_roi, &sde_enc->cur_conn_roi,
  800. sizeof(sde_enc->prv_conn_roi));
  801. memcpy(&sde_enc->cur_conn_roi, &roi, sizeof(sde_enc->cur_conn_roi));
  802. return 0;
  803. }
  804. void sde_encoder_helper_vsync_config(struct sde_encoder_phys *phys_enc,
  805. u32 vsync_source, bool is_dummy)
  806. {
  807. struct sde_vsync_source_cfg vsync_cfg = { 0 };
  808. struct msm_drm_private *priv;
  809. struct sde_kms *sde_kms;
  810. struct sde_hw_mdp *hw_mdptop;
  811. struct drm_encoder *drm_enc;
  812. struct sde_encoder_virt *sde_enc;
  813. int i;
  814. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  815. if (!sde_enc) {
  816. SDE_ERROR("invalid param sde_enc:%d\n", sde_enc != NULL);
  817. return;
  818. } else if (sde_enc->num_phys_encs > ARRAY_SIZE(sde_enc->hw_pp)) {
  819. SDE_ERROR("invalid num phys enc %d/%d\n",
  820. sde_enc->num_phys_encs,
  821. (int) ARRAY_SIZE(sde_enc->hw_pp));
  822. return;
  823. }
  824. drm_enc = &sde_enc->base;
  825. /* this pointers are checked in virt_enable_helper */
  826. priv = drm_enc->dev->dev_private;
  827. sde_kms = to_sde_kms(priv->kms);
  828. if (!sde_kms) {
  829. SDE_ERROR("invalid sde_kms\n");
  830. return;
  831. }
  832. hw_mdptop = sde_kms->hw_mdp;
  833. if (!hw_mdptop) {
  834. SDE_ERROR("invalid mdptop\n");
  835. return;
  836. }
  837. if (hw_mdptop->ops.setup_vsync_source) {
  838. for (i = 0; i < sde_enc->num_phys_encs; i++)
  839. vsync_cfg.ppnumber[i] = sde_enc->hw_pp[i]->idx;
  840. vsync_cfg.pp_count = sde_enc->num_phys_encs;
  841. vsync_cfg.frame_rate = sde_enc->mode_info.frame_rate;
  842. vsync_cfg.vsync_source = vsync_source;
  843. vsync_cfg.is_dummy = is_dummy;
  844. hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
  845. }
  846. }
  847. static void _sde_encoder_update_vsync_source(struct sde_encoder_virt *sde_enc,
  848. struct msm_display_info *disp_info, bool is_dummy)
  849. {
  850. struct sde_encoder_phys *phys;
  851. int i;
  852. u32 vsync_source;
  853. if (!sde_enc || !disp_info) {
  854. SDE_ERROR("invalid param sde_enc:%d or disp_info:%d\n",
  855. sde_enc != NULL, disp_info != NULL);
  856. return;
  857. } else if (sde_enc->num_phys_encs > ARRAY_SIZE(sde_enc->hw_pp)) {
  858. SDE_ERROR("invalid num phys enc %d/%d\n",
  859. sde_enc->num_phys_encs,
  860. (int) ARRAY_SIZE(sde_enc->hw_pp));
  861. return;
  862. }
  863. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_CMD_MODE)) {
  864. if (is_dummy)
  865. vsync_source = SDE_VSYNC_SOURCE_WD_TIMER_0 -
  866. sde_enc->te_source;
  867. else if (disp_info->is_te_using_watchdog_timer)
  868. vsync_source = SDE_VSYNC_SOURCE_WD_TIMER_4;
  869. else
  870. vsync_source = sde_enc->te_source;
  871. SDE_EVT32(DRMID(&sde_enc->base), vsync_source, is_dummy,
  872. disp_info->is_te_using_watchdog_timer);
  873. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  874. phys = sde_enc->phys_encs[i];
  875. if (phys && phys->ops.setup_vsync_source)
  876. phys->ops.setup_vsync_source(phys,
  877. vsync_source, is_dummy);
  878. }
  879. }
  880. }
  881. int sde_encoder_helper_switch_vsync(struct drm_encoder *drm_enc,
  882. bool watchdog_te)
  883. {
  884. struct sde_encoder_virt *sde_enc;
  885. struct msm_display_info disp_info;
  886. if (!drm_enc) {
  887. pr_err("invalid drm encoder\n");
  888. return -EINVAL;
  889. }
  890. sde_enc = to_sde_encoder_virt(drm_enc);
  891. sde_encoder_control_te(drm_enc, false);
  892. memcpy(&disp_info, &sde_enc->disp_info, sizeof(disp_info));
  893. disp_info.is_te_using_watchdog_timer = watchdog_te;
  894. _sde_encoder_update_vsync_source(sde_enc, &disp_info, false);
  895. sde_encoder_control_te(drm_enc, true);
  896. return 0;
  897. }
  898. static int _sde_encoder_rsc_client_update_vsync_wait(
  899. struct drm_encoder *drm_enc, struct sde_encoder_virt *sde_enc,
  900. int wait_vblank_crtc_id)
  901. {
  902. int wait_refcount = 0, ret = 0;
  903. int pipe = -1;
  904. int wait_count = 0;
  905. struct drm_crtc *primary_crtc;
  906. struct drm_crtc *crtc;
  907. crtc = sde_enc->crtc;
  908. if (wait_vblank_crtc_id)
  909. wait_refcount =
  910. sde_rsc_client_get_vsync_refcount(sde_enc->rsc_client);
  911. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id, wait_refcount,
  912. SDE_EVTLOG_FUNC_ENTRY);
  913. if (crtc->base.id != wait_vblank_crtc_id) {
  914. primary_crtc = drm_crtc_find(drm_enc->dev,
  915. NULL, wait_vblank_crtc_id);
  916. if (!primary_crtc) {
  917. SDE_ERROR_ENC(sde_enc,
  918. "failed to find primary crtc id %d\n",
  919. wait_vblank_crtc_id);
  920. return -EINVAL;
  921. }
  922. pipe = drm_crtc_index(primary_crtc);
  923. }
  924. /**
  925. * note: VBLANK is expected to be enabled at this point in
  926. * resource control state machine if on primary CRTC
  927. */
  928. for (wait_count = 0; wait_count < MAX_RSC_WAIT; wait_count++) {
  929. if (sde_rsc_client_is_state_update_complete(
  930. sde_enc->rsc_client))
  931. break;
  932. if (crtc->base.id == wait_vblank_crtc_id)
  933. ret = sde_encoder_wait_for_event(drm_enc,
  934. MSM_ENC_VBLANK);
  935. else
  936. drm_wait_one_vblank(drm_enc->dev, pipe);
  937. if (ret) {
  938. SDE_ERROR_ENC(sde_enc,
  939. "wait for vblank failed ret:%d\n", ret);
  940. /**
  941. * rsc hardware may hang without vsync. avoid rsc hang
  942. * by generating the vsync from watchdog timer.
  943. */
  944. if (crtc->base.id == wait_vblank_crtc_id)
  945. sde_encoder_helper_switch_vsync(drm_enc, true);
  946. }
  947. }
  948. if (wait_count >= MAX_RSC_WAIT)
  949. SDE_EVT32(DRMID(drm_enc), wait_vblank_crtc_id, wait_count,
  950. SDE_EVTLOG_ERROR);
  951. if (wait_refcount)
  952. sde_rsc_client_reset_vsync_refcount(sde_enc->rsc_client);
  953. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id, wait_refcount,
  954. SDE_EVTLOG_FUNC_EXIT);
  955. return ret;
  956. }
  957. static int _sde_encoder_update_rsc_client(
  958. struct drm_encoder *drm_enc, bool enable)
  959. {
  960. struct sde_encoder_virt *sde_enc;
  961. struct drm_crtc *crtc;
  962. enum sde_rsc_state rsc_state = SDE_RSC_IDLE_STATE;
  963. struct sde_rsc_cmd_config *rsc_config;
  964. int ret;
  965. struct msm_display_info *disp_info;
  966. struct msm_mode_info *mode_info;
  967. int wait_vblank_crtc_id = SDE_RSC_INVALID_CRTC_ID;
  968. u32 qsync_mode = 0, v_front_porch;
  969. struct drm_display_mode *mode;
  970. bool is_vid_mode;
  971. if (!drm_enc || !drm_enc->dev) {
  972. SDE_ERROR("invalid encoder arguments\n");
  973. return -EINVAL;
  974. }
  975. sde_enc = to_sde_encoder_virt(drm_enc);
  976. mode_info = &sde_enc->mode_info;
  977. crtc = sde_enc->crtc;
  978. if (!sde_enc->crtc) {
  979. SDE_ERROR("invalid crtc parameter\n");
  980. return -EINVAL;
  981. }
  982. disp_info = &sde_enc->disp_info;
  983. rsc_config = &sde_enc->rsc_config;
  984. if (!sde_enc->rsc_client) {
  985. SDE_DEBUG_ENC(sde_enc, "rsc client not created\n");
  986. return 0;
  987. }
  988. /**
  989. * only primary command mode panel without Qsync can request CMD state.
  990. * all other panels/displays can request for VID state including
  991. * secondary command mode panel.
  992. * Clone mode encoder can request CLK STATE only.
  993. */
  994. if (sde_enc->cur_master)
  995. qsync_mode = sde_connector_get_qsync_mode(
  996. sde_enc->cur_master->connector);
  997. if (sde_encoder_in_clone_mode(drm_enc) ||
  998. (disp_info->display_type != SDE_CONNECTOR_PRIMARY) ||
  999. (disp_info->display_type && qsync_mode))
  1000. rsc_state = enable ? SDE_RSC_CLK_STATE : SDE_RSC_IDLE_STATE;
  1001. else if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1002. rsc_state = enable ? SDE_RSC_CMD_STATE : SDE_RSC_IDLE_STATE;
  1003. else if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE))
  1004. rsc_state = enable ? SDE_RSC_VID_STATE : SDE_RSC_IDLE_STATE;
  1005. SDE_EVT32(rsc_state, qsync_mode);
  1006. is_vid_mode = sde_encoder_check_curr_mode(&sde_enc->base,
  1007. MSM_DISPLAY_VIDEO_MODE);
  1008. mode = &sde_enc->crtc->state->mode;
  1009. v_front_porch = mode->vsync_start - mode->vdisplay;
  1010. /* compare specific items and reconfigure the rsc */
  1011. if ((rsc_config->fps != mode_info->frame_rate) ||
  1012. (rsc_config->vtotal != mode_info->vtotal) ||
  1013. (rsc_config->prefill_lines != mode_info->prefill_lines) ||
  1014. (rsc_config->jitter_numer != mode_info->jitter_numer) ||
  1015. (rsc_config->jitter_denom != mode_info->jitter_denom)) {
  1016. rsc_config->fps = mode_info->frame_rate;
  1017. rsc_config->vtotal = mode_info->vtotal;
  1018. /*
  1019. * for video mode, prefill lines should not go beyond vertical
  1020. * front porch for RSCC configuration. This will ensure bw
  1021. * downvotes are not sent within the active region. Additional
  1022. * -1 is to give one line time for rscc mode min_threshold.
  1023. */
  1024. if (is_vid_mode && (mode_info->prefill_lines >= v_front_porch))
  1025. rsc_config->prefill_lines = v_front_porch - 1;
  1026. else
  1027. rsc_config->prefill_lines = mode_info->prefill_lines;
  1028. rsc_config->jitter_numer = mode_info->jitter_numer;
  1029. rsc_config->jitter_denom = mode_info->jitter_denom;
  1030. sde_enc->rsc_state_init = false;
  1031. }
  1032. if (rsc_state != SDE_RSC_IDLE_STATE && !sde_enc->rsc_state_init
  1033. && (disp_info->display_type == SDE_CONNECTOR_PRIMARY)) {
  1034. /* update it only once */
  1035. sde_enc->rsc_state_init = true;
  1036. ret = sde_rsc_client_state_update(sde_enc->rsc_client,
  1037. rsc_state, rsc_config, crtc->base.id,
  1038. &wait_vblank_crtc_id);
  1039. } else {
  1040. ret = sde_rsc_client_state_update(sde_enc->rsc_client,
  1041. rsc_state, NULL, crtc->base.id,
  1042. &wait_vblank_crtc_id);
  1043. }
  1044. /**
  1045. * if RSC performed a state change that requires a VBLANK wait, it will
  1046. * set wait_vblank_crtc_id to the CRTC whose VBLANK we must wait on.
  1047. *
  1048. * if we are the primary display, we will need to enable and wait
  1049. * locally since we hold the commit thread
  1050. *
  1051. * if we are an external display, we must send a signal to the primary
  1052. * to enable its VBLANK and wait one, since the RSC hardware is driven
  1053. * by the primary panel's VBLANK signals
  1054. */
  1055. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id);
  1056. if (ret) {
  1057. SDE_ERROR_ENC(sde_enc,
  1058. "sde rsc client update failed ret:%d\n", ret);
  1059. return ret;
  1060. } else if (wait_vblank_crtc_id == SDE_RSC_INVALID_CRTC_ID) {
  1061. return ret;
  1062. }
  1063. ret = _sde_encoder_rsc_client_update_vsync_wait(drm_enc,
  1064. sde_enc, wait_vblank_crtc_id);
  1065. return ret;
  1066. }
  1067. static void _sde_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
  1068. {
  1069. struct sde_encoder_virt *sde_enc;
  1070. int i;
  1071. if (!drm_enc) {
  1072. SDE_ERROR("invalid encoder\n");
  1073. return;
  1074. }
  1075. sde_enc = to_sde_encoder_virt(drm_enc);
  1076. SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
  1077. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1078. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1079. if (phys && phys->ops.irq_control)
  1080. phys->ops.irq_control(phys, enable);
  1081. }
  1082. }
  1083. /* keep track of the userspace vblank during modeset */
  1084. static void _sde_encoder_modeset_helper_locked(struct drm_encoder *drm_enc,
  1085. u32 sw_event)
  1086. {
  1087. struct sde_encoder_virt *sde_enc;
  1088. bool enable;
  1089. int i;
  1090. if (!drm_enc) {
  1091. SDE_ERROR("invalid encoder\n");
  1092. return;
  1093. }
  1094. sde_enc = to_sde_encoder_virt(drm_enc);
  1095. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, vblank_enabled:%d\n",
  1096. sw_event, sde_enc->vblank_enabled);
  1097. /* nothing to do if vblank not enabled by userspace */
  1098. if (!sde_enc->vblank_enabled)
  1099. return;
  1100. /* disable vblank on pre_modeset */
  1101. if (sw_event == SDE_ENC_RC_EVENT_PRE_MODESET)
  1102. enable = false;
  1103. /* enable vblank on post_modeset */
  1104. else if (sw_event == SDE_ENC_RC_EVENT_POST_MODESET)
  1105. enable = true;
  1106. else
  1107. return;
  1108. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1109. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1110. if (phys && phys->ops.control_vblank_irq)
  1111. phys->ops.control_vblank_irq(phys, enable);
  1112. }
  1113. }
  1114. struct sde_rsc_client *sde_encoder_get_rsc_client(struct drm_encoder *drm_enc)
  1115. {
  1116. struct sde_encoder_virt *sde_enc;
  1117. if (!drm_enc)
  1118. return NULL;
  1119. sde_enc = to_sde_encoder_virt(drm_enc);
  1120. return sde_enc->rsc_client;
  1121. }
  1122. static int _sde_encoder_resource_control_helper(struct drm_encoder *drm_enc,
  1123. bool enable)
  1124. {
  1125. struct msm_drm_private *priv;
  1126. struct sde_kms *sde_kms;
  1127. struct sde_encoder_virt *sde_enc;
  1128. int rc;
  1129. bool is_cmd_mode = false;
  1130. sde_enc = to_sde_encoder_virt(drm_enc);
  1131. priv = drm_enc->dev->dev_private;
  1132. sde_kms = to_sde_kms(priv->kms);
  1133. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1134. is_cmd_mode = true;
  1135. SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
  1136. SDE_EVT32(DRMID(drm_enc), enable);
  1137. if (!sde_enc->cur_master) {
  1138. SDE_ERROR("encoder master not set\n");
  1139. return -EINVAL;
  1140. }
  1141. if (enable) {
  1142. /* enable SDE core clks */
  1143. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  1144. if (rc < 0) {
  1145. SDE_ERROR("failed to enable power resource %d\n", rc);
  1146. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  1147. return rc;
  1148. }
  1149. sde_enc->elevated_ahb_vote = true;
  1150. /* enable DSI clks */
  1151. rc = sde_connector_clk_ctrl(sde_enc->cur_master->connector,
  1152. true);
  1153. if (rc) {
  1154. SDE_ERROR("failed to enable clk control %d\n", rc);
  1155. pm_runtime_put_sync(drm_enc->dev->dev);
  1156. return rc;
  1157. }
  1158. /* enable all the irq */
  1159. _sde_encoder_irq_control(drm_enc, true);
  1160. } else {
  1161. /* disable all the irq */
  1162. _sde_encoder_irq_control(drm_enc, false);
  1163. /* disable DSI clks */
  1164. sde_connector_clk_ctrl(sde_enc->cur_master->connector, false);
  1165. /* disable SDE core clks */
  1166. pm_runtime_put_sync(drm_enc->dev->dev);
  1167. }
  1168. return 0;
  1169. }
  1170. static void sde_encoder_misr_configure(struct drm_encoder *drm_enc,
  1171. bool enable, u32 frame_count)
  1172. {
  1173. struct sde_encoder_virt *sde_enc;
  1174. int i;
  1175. if (!drm_enc) {
  1176. SDE_ERROR("invalid encoder\n");
  1177. return;
  1178. }
  1179. sde_enc = to_sde_encoder_virt(drm_enc);
  1180. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1181. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1182. if (!phys || !phys->ops.setup_misr)
  1183. continue;
  1184. phys->ops.setup_misr(phys, enable, frame_count);
  1185. }
  1186. }
  1187. static void sde_encoder_input_event_handler(struct input_handle *handle,
  1188. unsigned int type, unsigned int code, int value)
  1189. {
  1190. struct drm_encoder *drm_enc = NULL;
  1191. struct sde_encoder_virt *sde_enc = NULL;
  1192. struct msm_drm_thread *disp_thread = NULL;
  1193. struct msm_drm_private *priv = NULL;
  1194. if (!handle || !handle->handler || !handle->handler->private) {
  1195. SDE_ERROR("invalid encoder for the input event\n");
  1196. return;
  1197. }
  1198. drm_enc = (struct drm_encoder *)handle->handler->private;
  1199. if (!drm_enc->dev || !drm_enc->dev->dev_private) {
  1200. SDE_ERROR("invalid parameters\n");
  1201. return;
  1202. }
  1203. priv = drm_enc->dev->dev_private;
  1204. sde_enc = to_sde_encoder_virt(drm_enc);
  1205. if (!sde_enc->crtc || (sde_enc->crtc->index
  1206. >= ARRAY_SIZE(priv->disp_thread))) {
  1207. SDE_DEBUG_ENC(sde_enc,
  1208. "invalid cached CRTC: %d or crtc index: %d\n",
  1209. sde_enc->crtc == NULL,
  1210. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  1211. return;
  1212. }
  1213. SDE_EVT32_VERBOSE(DRMID(drm_enc));
  1214. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1215. kthread_queue_work(&disp_thread->worker,
  1216. &sde_enc->input_event_work);
  1217. }
  1218. void sde_encoder_control_idle_pc(struct drm_encoder *drm_enc, bool enable)
  1219. {
  1220. struct sde_encoder_virt *sde_enc;
  1221. if (!drm_enc) {
  1222. SDE_ERROR("invalid encoder\n");
  1223. return;
  1224. }
  1225. sde_enc = to_sde_encoder_virt(drm_enc);
  1226. /* return early if there is no state change */
  1227. if (sde_enc->idle_pc_enabled == enable)
  1228. return;
  1229. sde_enc->idle_pc_enabled = enable;
  1230. SDE_DEBUG("idle-pc state:%d\n", sde_enc->idle_pc_enabled);
  1231. SDE_EVT32(sde_enc->idle_pc_enabled);
  1232. }
  1233. static void _sde_encoder_rc_cancel_delayed(struct sde_encoder_virt *sde_enc,
  1234. u32 sw_event)
  1235. {
  1236. if (kthread_cancel_delayed_work_sync(
  1237. &sde_enc->delayed_off_work))
  1238. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work cancelled\n",
  1239. sw_event);
  1240. }
  1241. static int _sde_encoder_rc_kickoff(struct drm_encoder *drm_enc,
  1242. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1243. {
  1244. int ret = 0;
  1245. /* cancel delayed off work, if any */
  1246. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1247. mutex_lock(&sde_enc->rc_lock);
  1248. /* return if the resource control is already in ON state */
  1249. if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
  1250. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in ON state\n",
  1251. sw_event);
  1252. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1253. SDE_EVTLOG_FUNC_CASE1);
  1254. goto end;
  1255. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_OFF &&
  1256. sde_enc->rc_state != SDE_ENC_RC_STATE_IDLE) {
  1257. SDE_ERROR_ENC(sde_enc, "sw_event:%d, rc in state %d\n",
  1258. sw_event, sde_enc->rc_state);
  1259. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1260. SDE_EVTLOG_ERROR);
  1261. goto end;
  1262. }
  1263. if (is_vid_mode && sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1264. _sde_encoder_irq_control(drm_enc, true);
  1265. } else {
  1266. /* enable all the clks and resources */
  1267. ret = _sde_encoder_resource_control_helper(drm_enc,
  1268. true);
  1269. if (ret) {
  1270. SDE_ERROR_ENC(sde_enc,
  1271. "sw_event:%d, rc in state %d\n",
  1272. sw_event, sde_enc->rc_state);
  1273. SDE_EVT32(DRMID(drm_enc), sw_event,
  1274. sde_enc->rc_state,
  1275. SDE_EVTLOG_ERROR);
  1276. goto end;
  1277. }
  1278. _sde_encoder_update_rsc_client(drm_enc, true);
  1279. }
  1280. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1281. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE1);
  1282. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1283. end:
  1284. mutex_unlock(&sde_enc->rc_lock);
  1285. return ret;
  1286. }
  1287. static int _sde_encoder_rc_frame_done(struct drm_encoder *drm_enc,
  1288. u32 sw_event, struct sde_encoder_virt *sde_enc,
  1289. struct msm_drm_private *priv)
  1290. {
  1291. unsigned int lp, idle_pc_duration;
  1292. struct msm_drm_thread *disp_thread;
  1293. bool autorefresh_enabled = false;
  1294. if (!sde_enc->crtc) {
  1295. SDE_ERROR("invalid crtc, sw_event:%u\n", sw_event);
  1296. return -EINVAL;
  1297. }
  1298. if (sde_enc->crtc->index >= ARRAY_SIZE(priv->disp_thread)) {
  1299. SDE_ERROR("invalid crtc index :%u\n",
  1300. sde_enc->crtc->index);
  1301. return -EINVAL;
  1302. }
  1303. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1304. /*
  1305. * mutex lock is not used as this event happens at interrupt
  1306. * context. And locking is not required as, the other events
  1307. * like KICKOFF and STOP does a wait-for-idle before executing
  1308. * the resource_control
  1309. */
  1310. if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  1311. SDE_ERROR_ENC(sde_enc, "sw_event:%d,rc:%d-unexpected\n",
  1312. sw_event, sde_enc->rc_state);
  1313. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1314. SDE_EVTLOG_ERROR);
  1315. return -EINVAL;
  1316. }
  1317. /*
  1318. * schedule off work item only when there are no
  1319. * frames pending
  1320. */
  1321. if (sde_crtc_frame_pending(sde_enc->crtc) > 1) {
  1322. SDE_DEBUG_ENC(sde_enc, "skip schedule work");
  1323. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1324. SDE_EVTLOG_FUNC_CASE2);
  1325. return 0;
  1326. }
  1327. /* schedule delayed off work if autorefresh is disabled */
  1328. if (sde_enc->cur_master &&
  1329. sde_enc->cur_master->ops.is_autorefresh_enabled)
  1330. autorefresh_enabled =
  1331. sde_enc->cur_master->ops.is_autorefresh_enabled(
  1332. sde_enc->cur_master);
  1333. /* set idle timeout based on master connector's lp value */
  1334. if (sde_enc->cur_master)
  1335. lp = sde_connector_get_lp(
  1336. sde_enc->cur_master->connector);
  1337. else
  1338. lp = SDE_MODE_DPMS_ON;
  1339. if (lp == SDE_MODE_DPMS_LP2)
  1340. idle_pc_duration = IDLE_SHORT_TIMEOUT;
  1341. else
  1342. idle_pc_duration = IDLE_POWERCOLLAPSE_DURATION;
  1343. if (!autorefresh_enabled)
  1344. kthread_mod_delayed_work(
  1345. &disp_thread->worker,
  1346. &sde_enc->delayed_off_work,
  1347. msecs_to_jiffies(idle_pc_duration));
  1348. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1349. autorefresh_enabled,
  1350. idle_pc_duration, SDE_EVTLOG_FUNC_CASE2);
  1351. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work scheduled\n",
  1352. sw_event);
  1353. return 0;
  1354. }
  1355. static int _sde_encoder_rc_pre_stop(struct drm_encoder *drm_enc,
  1356. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1357. {
  1358. /* cancel delayed off work, if any */
  1359. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1360. mutex_lock(&sde_enc->rc_lock);
  1361. if (is_vid_mode &&
  1362. sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1363. _sde_encoder_irq_control(drm_enc, true);
  1364. }
  1365. /* skip if is already OFF or IDLE, resources are off already */
  1366. else if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF ||
  1367. sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1368. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in %d state\n",
  1369. sw_event, sde_enc->rc_state);
  1370. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1371. SDE_EVTLOG_FUNC_CASE3);
  1372. goto end;
  1373. }
  1374. /**
  1375. * IRQs are still enabled currently, which allows wait for
  1376. * VBLANK which RSC may require to correctly transition to OFF
  1377. */
  1378. _sde_encoder_update_rsc_client(drm_enc, false);
  1379. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1380. SDE_ENC_RC_STATE_PRE_OFF,
  1381. SDE_EVTLOG_FUNC_CASE3);
  1382. sde_enc->rc_state = SDE_ENC_RC_STATE_PRE_OFF;
  1383. end:
  1384. mutex_unlock(&sde_enc->rc_lock);
  1385. return 0;
  1386. }
  1387. static int _sde_encoder_rc_stop(struct drm_encoder *drm_enc,
  1388. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1389. {
  1390. int ret = 0;
  1391. /* cancel vsync event work and timer */
  1392. kthread_cancel_work_sync(&sde_enc->vsync_event_work);
  1393. if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI)
  1394. del_timer_sync(&sde_enc->vsync_event_timer);
  1395. mutex_lock(&sde_enc->rc_lock);
  1396. /* return if the resource control is already in OFF state */
  1397. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1398. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1399. sw_event);
  1400. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1401. SDE_EVTLOG_FUNC_CASE4);
  1402. goto end;
  1403. } else if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON ||
  1404. sde_enc->rc_state == SDE_ENC_RC_STATE_MODESET) {
  1405. SDE_ERROR_ENC(sde_enc, "sw_event:%d, rc in state %d\n",
  1406. sw_event, sde_enc->rc_state);
  1407. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1408. SDE_EVTLOG_ERROR);
  1409. ret = -EINVAL;
  1410. goto end;
  1411. }
  1412. /**
  1413. * expect to arrive here only if in either idle state or pre-off
  1414. * and in IDLE state the resources are already disabled
  1415. */
  1416. if (sde_enc->rc_state == SDE_ENC_RC_STATE_PRE_OFF)
  1417. _sde_encoder_resource_control_helper(drm_enc, false);
  1418. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1419. SDE_ENC_RC_STATE_OFF, SDE_EVTLOG_FUNC_CASE4);
  1420. sde_enc->rc_state = SDE_ENC_RC_STATE_OFF;
  1421. end:
  1422. mutex_unlock(&sde_enc->rc_lock);
  1423. return ret;
  1424. }
  1425. static int _sde_encoder_rc_pre_modeset(struct drm_encoder *drm_enc,
  1426. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1427. {
  1428. int ret = 0;
  1429. /* cancel delayed off work, if any */
  1430. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1431. mutex_lock(&sde_enc->rc_lock);
  1432. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1433. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1434. sw_event);
  1435. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1436. SDE_EVTLOG_FUNC_CASE5);
  1437. goto end;
  1438. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  1439. /* enable all the clks and resources */
  1440. ret = _sde_encoder_resource_control_helper(drm_enc,
  1441. true);
  1442. if (ret) {
  1443. SDE_ERROR_ENC(sde_enc,
  1444. "sw_event:%d, rc in state %d\n",
  1445. sw_event, sde_enc->rc_state);
  1446. SDE_EVT32(DRMID(drm_enc), sw_event,
  1447. sde_enc->rc_state,
  1448. SDE_EVTLOG_ERROR);
  1449. goto end;
  1450. }
  1451. _sde_encoder_update_rsc_client(drm_enc, true);
  1452. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1453. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE5);
  1454. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1455. }
  1456. ret = sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
  1457. if (ret && ret != -EWOULDBLOCK) {
  1458. SDE_ERROR_ENC(sde_enc,
  1459. "wait for commit done returned %d\n",
  1460. ret);
  1461. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1462. ret, SDE_EVTLOG_ERROR);
  1463. ret = -EINVAL;
  1464. goto end;
  1465. }
  1466. _sde_encoder_irq_control(drm_enc, false);
  1467. _sde_encoder_modeset_helper_locked(drm_enc, sw_event);
  1468. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1469. SDE_ENC_RC_STATE_MODESET, SDE_EVTLOG_FUNC_CASE5);
  1470. sde_enc->rc_state = SDE_ENC_RC_STATE_MODESET;
  1471. end:
  1472. mutex_unlock(&sde_enc->rc_lock);
  1473. return ret;
  1474. }
  1475. static int _sde_encoder_rc_post_modeset(struct drm_encoder *drm_enc,
  1476. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1477. {
  1478. int ret = 0;
  1479. mutex_lock(&sde_enc->rc_lock);
  1480. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1481. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1482. sw_event);
  1483. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1484. SDE_EVTLOG_FUNC_CASE5);
  1485. goto end;
  1486. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_MODESET) {
  1487. SDE_ERROR_ENC(sde_enc,
  1488. "sw_event:%d, rc:%d !MODESET state\n",
  1489. sw_event, sde_enc->rc_state);
  1490. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1491. SDE_EVTLOG_ERROR);
  1492. ret = -EINVAL;
  1493. goto end;
  1494. }
  1495. _sde_encoder_modeset_helper_locked(drm_enc, sw_event);
  1496. _sde_encoder_irq_control(drm_enc, true);
  1497. _sde_encoder_update_rsc_client(drm_enc, true);
  1498. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1499. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE6);
  1500. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1501. end:
  1502. mutex_unlock(&sde_enc->rc_lock);
  1503. return ret;
  1504. }
  1505. static int _sde_encoder_rc_idle(struct drm_encoder *drm_enc,
  1506. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1507. {
  1508. mutex_lock(&sde_enc->rc_lock);
  1509. if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  1510. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc:%d !ON state\n",
  1511. sw_event, sde_enc->rc_state);
  1512. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1513. SDE_EVTLOG_ERROR);
  1514. goto end;
  1515. } else if (sde_crtc_frame_pending(sde_enc->crtc)) {
  1516. SDE_DEBUG_ENC(sde_enc, "skip idle entry");
  1517. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1518. sde_crtc_frame_pending(sde_enc->crtc),
  1519. SDE_EVTLOG_ERROR);
  1520. goto end;
  1521. }
  1522. if (is_vid_mode) {
  1523. _sde_encoder_irq_control(drm_enc, false);
  1524. } else {
  1525. /* disable all the clks and resources */
  1526. _sde_encoder_update_rsc_client(drm_enc, false);
  1527. _sde_encoder_resource_control_helper(drm_enc, false);
  1528. }
  1529. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1530. SDE_ENC_RC_STATE_IDLE, SDE_EVTLOG_FUNC_CASE7);
  1531. sde_enc->rc_state = SDE_ENC_RC_STATE_IDLE;
  1532. end:
  1533. mutex_unlock(&sde_enc->rc_lock);
  1534. return 0;
  1535. }
  1536. static int _sde_encoder_rc_early_wakeup(struct drm_encoder *drm_enc,
  1537. u32 sw_event, struct sde_encoder_virt *sde_enc,
  1538. struct msm_drm_private *priv, bool is_vid_mode)
  1539. {
  1540. bool autorefresh_enabled = false;
  1541. struct msm_drm_thread *disp_thread;
  1542. int ret = 0;
  1543. if (!sde_enc->crtc ||
  1544. sde_enc->crtc->index >= ARRAY_SIZE(priv->disp_thread)) {
  1545. SDE_DEBUG_ENC(sde_enc,
  1546. "invalid crtc:%d or crtc index:%d , sw_event:%u\n",
  1547. sde_enc->crtc == NULL,
  1548. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL,
  1549. sw_event);
  1550. return -EINVAL;
  1551. }
  1552. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1553. mutex_lock(&sde_enc->rc_lock);
  1554. if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
  1555. if (sde_enc->cur_master &&
  1556. sde_enc->cur_master->ops.is_autorefresh_enabled)
  1557. autorefresh_enabled =
  1558. sde_enc->cur_master->ops.is_autorefresh_enabled(
  1559. sde_enc->cur_master);
  1560. if (autorefresh_enabled) {
  1561. SDE_DEBUG_ENC(sde_enc,
  1562. "not handling early wakeup since auto refresh is enabled\n");
  1563. goto end;
  1564. }
  1565. if (!sde_crtc_frame_pending(sde_enc->crtc))
  1566. kthread_mod_delayed_work(&disp_thread->worker,
  1567. &sde_enc->delayed_off_work,
  1568. msecs_to_jiffies(
  1569. IDLE_POWERCOLLAPSE_DURATION));
  1570. } else if (sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1571. /* enable all the clks and resources */
  1572. ret = _sde_encoder_resource_control_helper(drm_enc,
  1573. true);
  1574. if (ret) {
  1575. SDE_ERROR_ENC(sde_enc,
  1576. "sw_event:%d, rc in state %d\n",
  1577. sw_event, sde_enc->rc_state);
  1578. SDE_EVT32(DRMID(drm_enc), sw_event,
  1579. sde_enc->rc_state,
  1580. SDE_EVTLOG_ERROR);
  1581. goto end;
  1582. }
  1583. _sde_encoder_update_rsc_client(drm_enc, true);
  1584. /*
  1585. * In some cases, commit comes with slight delay
  1586. * (> 80 ms)after early wake up, prevent clock switch
  1587. * off to avoid jank in next update. So, increase the
  1588. * command mode idle timeout sufficiently to prevent
  1589. * such case.
  1590. */
  1591. kthread_mod_delayed_work(&disp_thread->worker,
  1592. &sde_enc->delayed_off_work,
  1593. msecs_to_jiffies(
  1594. IDLE_POWERCOLLAPSE_IN_EARLY_WAKEUP));
  1595. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1596. }
  1597. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1598. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE8);
  1599. end:
  1600. mutex_unlock(&sde_enc->rc_lock);
  1601. return ret;
  1602. }
  1603. static int sde_encoder_resource_control(struct drm_encoder *drm_enc,
  1604. u32 sw_event)
  1605. {
  1606. struct sde_encoder_virt *sde_enc;
  1607. struct msm_drm_private *priv;
  1608. int ret = 0;
  1609. bool is_vid_mode = false;
  1610. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  1611. SDE_ERROR("invalid encoder parameters, sw_event:%u\n",
  1612. sw_event);
  1613. return -EINVAL;
  1614. }
  1615. sde_enc = to_sde_encoder_virt(drm_enc);
  1616. priv = drm_enc->dev->dev_private;
  1617. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
  1618. is_vid_mode = true;
  1619. /*
  1620. * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
  1621. * events and return early for other events (ie wb display).
  1622. */
  1623. if (!sde_enc->idle_pc_enabled &&
  1624. (sw_event != SDE_ENC_RC_EVENT_KICKOFF &&
  1625. sw_event != SDE_ENC_RC_EVENT_PRE_MODESET &&
  1626. sw_event != SDE_ENC_RC_EVENT_POST_MODESET &&
  1627. sw_event != SDE_ENC_RC_EVENT_STOP &&
  1628. sw_event != SDE_ENC_RC_EVENT_PRE_STOP))
  1629. return 0;
  1630. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, idle_pc:%d\n",
  1631. sw_event, sde_enc->idle_pc_enabled);
  1632. SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event, sde_enc->idle_pc_enabled,
  1633. sde_enc->rc_state, SDE_EVTLOG_FUNC_ENTRY);
  1634. switch (sw_event) {
  1635. case SDE_ENC_RC_EVENT_KICKOFF:
  1636. ret = _sde_encoder_rc_kickoff(drm_enc, sw_event, sde_enc,
  1637. is_vid_mode);
  1638. break;
  1639. case SDE_ENC_RC_EVENT_FRAME_DONE:
  1640. ret = _sde_encoder_rc_frame_done(drm_enc, sw_event, sde_enc,
  1641. priv);
  1642. break;
  1643. case SDE_ENC_RC_EVENT_PRE_STOP:
  1644. ret = _sde_encoder_rc_pre_stop(drm_enc, sw_event, sde_enc,
  1645. is_vid_mode);
  1646. break;
  1647. case SDE_ENC_RC_EVENT_STOP:
  1648. ret = _sde_encoder_rc_stop(drm_enc, sw_event, sde_enc);
  1649. break;
  1650. case SDE_ENC_RC_EVENT_PRE_MODESET:
  1651. ret = _sde_encoder_rc_pre_modeset(drm_enc, sw_event, sde_enc);
  1652. break;
  1653. case SDE_ENC_RC_EVENT_POST_MODESET:
  1654. ret = _sde_encoder_rc_post_modeset(drm_enc, sw_event, sde_enc);
  1655. break;
  1656. case SDE_ENC_RC_EVENT_ENTER_IDLE:
  1657. ret = _sde_encoder_rc_idle(drm_enc, sw_event, sde_enc,
  1658. is_vid_mode);
  1659. break;
  1660. case SDE_ENC_RC_EVENT_EARLY_WAKEUP:
  1661. ret = _sde_encoder_rc_early_wakeup(drm_enc, sw_event, sde_enc,
  1662. priv, is_vid_mode);
  1663. break;
  1664. default:
  1665. SDE_EVT32(DRMID(drm_enc), sw_event, SDE_EVTLOG_ERROR);
  1666. SDE_ERROR("unexpected sw_event: %d\n", sw_event);
  1667. break;
  1668. }
  1669. SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event, sde_enc->idle_pc_enabled,
  1670. sde_enc->rc_state, SDE_EVTLOG_FUNC_EXIT);
  1671. return ret;
  1672. }
  1673. static void sde_encoder_virt_mode_switch(struct drm_encoder *drm_enc,
  1674. enum sde_intf_mode intf_mode, struct drm_display_mode *adj_mode)
  1675. {
  1676. int i = 0;
  1677. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1678. if (intf_mode == INTF_MODE_CMD)
  1679. sde_enc->disp_info.curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  1680. else if (intf_mode == INTF_MODE_VIDEO)
  1681. sde_enc->disp_info.curr_panel_mode = MSM_DISPLAY_CMD_MODE;
  1682. _sde_encoder_update_rsc_client(drm_enc, true);
  1683. if (intf_mode == INTF_MODE_CMD) {
  1684. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1685. sde_enc->phys_encs[i] = sde_enc->phys_vid_encs[i];
  1686. SDE_DEBUG_ENC(sde_enc, "switch to video physical encoder\n");
  1687. SDE_EVT32(DRMID(&sde_enc->base), intf_mode,
  1688. msm_is_mode_seamless_poms(adj_mode),
  1689. SDE_EVTLOG_FUNC_CASE1);
  1690. } else if (intf_mode == INTF_MODE_VIDEO) {
  1691. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1692. sde_enc->phys_encs[i] = sde_enc->phys_cmd_encs[i];
  1693. SDE_EVT32(DRMID(&sde_enc->base), intf_mode,
  1694. msm_is_mode_seamless_poms(adj_mode),
  1695. SDE_EVTLOG_FUNC_CASE2);
  1696. SDE_DEBUG_ENC(sde_enc, "switch to command physical encoder\n");
  1697. }
  1698. }
  1699. static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc,
  1700. struct drm_display_mode *mode,
  1701. struct drm_display_mode *adj_mode)
  1702. {
  1703. struct sde_encoder_virt *sde_enc;
  1704. struct msm_drm_private *priv;
  1705. struct sde_kms *sde_kms;
  1706. struct list_head *connector_list;
  1707. struct drm_connector *conn = NULL, *conn_iter;
  1708. struct sde_rm_hw_iter dsc_iter, pp_iter, qdss_iter;
  1709. struct sde_rm_hw_request request_hw;
  1710. enum sde_intf_mode intf_mode;
  1711. bool is_cmd_mode = false;
  1712. int i = 0, ret;
  1713. if (!drm_enc) {
  1714. SDE_ERROR("invalid encoder\n");
  1715. return;
  1716. }
  1717. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  1718. SDE_ERROR("power resource is not enabled\n");
  1719. return;
  1720. }
  1721. sde_enc = to_sde_encoder_virt(drm_enc);
  1722. SDE_DEBUG_ENC(sde_enc, "\n");
  1723. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1724. is_cmd_mode = true;
  1725. priv = drm_enc->dev->dev_private;
  1726. sde_kms = to_sde_kms(priv->kms);
  1727. connector_list = &sde_kms->dev->mode_config.connector_list;
  1728. SDE_EVT32(DRMID(drm_enc));
  1729. /*
  1730. * cache the crtc in sde_enc on enable for duration of use case
  1731. * for correctly servicing asynchronous irq events and timers
  1732. */
  1733. if (!drm_enc->crtc) {
  1734. SDE_ERROR("invalid crtc\n");
  1735. return;
  1736. }
  1737. sde_enc->crtc = drm_enc->crtc;
  1738. list_for_each_entry(conn_iter, connector_list, head)
  1739. if (conn_iter->encoder == drm_enc)
  1740. conn = conn_iter;
  1741. if (!conn) {
  1742. SDE_ERROR_ENC(sde_enc, "failed to find attached connector\n");
  1743. return;
  1744. } else if (!conn->state) {
  1745. SDE_ERROR_ENC(sde_enc, "invalid connector state\n");
  1746. return;
  1747. }
  1748. intf_mode = sde_encoder_get_intf_mode(drm_enc);
  1749. /* store the mode_info */
  1750. sde_connector_state_get_mode_info(conn->state, &sde_enc->mode_info);
  1751. /* release resources before seamless mode change */
  1752. if (msm_is_mode_seamless_dms(adj_mode) ||
  1753. (msm_is_mode_seamless_dyn_clk(adj_mode) &&
  1754. is_cmd_mode)) {
  1755. /* restore resource state before releasing them */
  1756. ret = sde_encoder_resource_control(drm_enc,
  1757. SDE_ENC_RC_EVENT_PRE_MODESET);
  1758. if (ret) {
  1759. SDE_ERROR_ENC(sde_enc,
  1760. "sde resource control failed: %d\n",
  1761. ret);
  1762. return;
  1763. }
  1764. /*
  1765. * Disable dce before switch the mode and after pre_modeset,
  1766. * to guarantee that previous kickoff finished.
  1767. */
  1768. sde_encoder_dce_disable(sde_enc);
  1769. } else if (msm_is_mode_seamless_poms(adj_mode)) {
  1770. _sde_encoder_modeset_helper_locked(drm_enc,
  1771. SDE_ENC_RC_EVENT_PRE_MODESET);
  1772. sde_encoder_virt_mode_switch(drm_enc, intf_mode, adj_mode);
  1773. }
  1774. /* Reserve dynamic resources now. Indicating non-AtomicTest phase */
  1775. ret = sde_rm_reserve(&sde_kms->rm, drm_enc, drm_enc->crtc->state,
  1776. conn->state, false);
  1777. if (ret) {
  1778. SDE_ERROR_ENC(sde_enc,
  1779. "failed to reserve hw resources, %d\n", ret);
  1780. return;
  1781. }
  1782. sde_rm_init_hw_iter(&pp_iter, drm_enc->base.id, SDE_HW_BLK_PINGPONG);
  1783. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1784. sde_enc->hw_pp[i] = NULL;
  1785. if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
  1786. break;
  1787. sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
  1788. }
  1789. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1790. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1791. if (phys) {
  1792. sde_rm_init_hw_iter(&qdss_iter, drm_enc->base.id,
  1793. SDE_HW_BLK_QDSS);
  1794. for (i = 0; i < QDSS_MAX; i++) {
  1795. if (sde_rm_get_hw(&sde_kms->rm, &qdss_iter)) {
  1796. phys->hw_qdss =
  1797. (struct sde_hw_qdss *)qdss_iter.hw;
  1798. break;
  1799. }
  1800. }
  1801. }
  1802. }
  1803. sde_rm_init_hw_iter(&dsc_iter, drm_enc->base.id, SDE_HW_BLK_DSC);
  1804. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1805. sde_enc->hw_dsc[i] = NULL;
  1806. if (!sde_rm_get_hw(&sde_kms->rm, &dsc_iter))
  1807. break;
  1808. sde_enc->hw_dsc[i] = (struct sde_hw_dsc *) dsc_iter.hw;
  1809. }
  1810. /* Get PP for DSC configuration */
  1811. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1812. sde_enc->hw_dsc_pp[i] = NULL;
  1813. if (!sde_enc->hw_dsc[i])
  1814. continue;
  1815. request_hw.id = sde_enc->hw_dsc[i]->base.id;
  1816. request_hw.type = SDE_HW_BLK_PINGPONG;
  1817. if (!sde_rm_request_hw_blk(&sde_kms->rm, &request_hw))
  1818. break;
  1819. sde_enc->hw_dsc_pp[i] =
  1820. (struct sde_hw_pingpong *) request_hw.hw;
  1821. }
  1822. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1823. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1824. if (phys) {
  1825. if (!sde_enc->hw_pp[i] && sde_enc->topology.num_intf) {
  1826. SDE_ERROR_ENC(sde_enc,
  1827. "invalid pingpong block for the encoder\n");
  1828. return;
  1829. }
  1830. phys->hw_pp = sde_enc->hw_pp[i];
  1831. phys->connector = conn->state->connector;
  1832. if (phys->ops.mode_set)
  1833. phys->ops.mode_set(phys, mode, adj_mode);
  1834. }
  1835. }
  1836. /* update resources after seamless mode change */
  1837. if (msm_is_mode_seamless_dms(adj_mode) ||
  1838. (msm_is_mode_seamless_dyn_clk(adj_mode) &&
  1839. is_cmd_mode))
  1840. sde_encoder_resource_control(&sde_enc->base,
  1841. SDE_ENC_RC_EVENT_POST_MODESET);
  1842. else if (msm_is_mode_seamless_poms(adj_mode))
  1843. _sde_encoder_modeset_helper_locked(drm_enc,
  1844. SDE_ENC_RC_EVENT_POST_MODESET);
  1845. }
  1846. void sde_encoder_control_te(struct drm_encoder *drm_enc, bool enable)
  1847. {
  1848. struct sde_encoder_virt *sde_enc;
  1849. struct sde_encoder_phys *phys;
  1850. int i;
  1851. if (!drm_enc) {
  1852. SDE_ERROR("invalid parameters\n");
  1853. return;
  1854. }
  1855. sde_enc = to_sde_encoder_virt(drm_enc);
  1856. if (!sde_enc) {
  1857. SDE_ERROR("invalid sde encoder\n");
  1858. return;
  1859. }
  1860. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1861. phys = sde_enc->phys_encs[i];
  1862. if (phys && phys->ops.control_te)
  1863. phys->ops.control_te(phys, enable);
  1864. }
  1865. }
  1866. static int _sde_encoder_input_connect(struct input_handler *handler,
  1867. struct input_dev *dev, const struct input_device_id *id)
  1868. {
  1869. struct input_handle *handle;
  1870. int rc = 0;
  1871. handle = kzalloc(sizeof(*handle), GFP_KERNEL);
  1872. if (!handle)
  1873. return -ENOMEM;
  1874. handle->dev = dev;
  1875. handle->handler = handler;
  1876. handle->name = handler->name;
  1877. rc = input_register_handle(handle);
  1878. if (rc) {
  1879. pr_err("failed to register input handle\n");
  1880. goto error;
  1881. }
  1882. rc = input_open_device(handle);
  1883. if (rc) {
  1884. pr_err("failed to open input device\n");
  1885. goto error_unregister;
  1886. }
  1887. return 0;
  1888. error_unregister:
  1889. input_unregister_handle(handle);
  1890. error:
  1891. kfree(handle);
  1892. return rc;
  1893. }
  1894. static void _sde_encoder_input_disconnect(struct input_handle *handle)
  1895. {
  1896. input_close_device(handle);
  1897. input_unregister_handle(handle);
  1898. kfree(handle);
  1899. }
  1900. /**
  1901. * Structure for specifying event parameters on which to receive callbacks.
  1902. * This structure will trigger a callback in case of a touch event (specified by
  1903. * EV_ABS) where there is a change in X and Y coordinates,
  1904. */
  1905. static const struct input_device_id sde_input_ids[] = {
  1906. {
  1907. .flags = INPUT_DEVICE_ID_MATCH_EVBIT,
  1908. .evbit = { BIT_MASK(EV_ABS) },
  1909. .absbit = { [BIT_WORD(ABS_MT_POSITION_X)] =
  1910. BIT_MASK(ABS_MT_POSITION_X) |
  1911. BIT_MASK(ABS_MT_POSITION_Y) },
  1912. },
  1913. { },
  1914. };
  1915. static int _sde_encoder_input_handler_register(
  1916. struct input_handler *input_handler)
  1917. {
  1918. int rc = 0;
  1919. rc = input_register_handler(input_handler);
  1920. if (rc) {
  1921. pr_err("input_register_handler failed, rc= %d\n", rc);
  1922. kfree(input_handler);
  1923. return rc;
  1924. }
  1925. return rc;
  1926. }
  1927. static int _sde_encoder_input_handler(
  1928. struct sde_encoder_virt *sde_enc)
  1929. {
  1930. struct input_handler *input_handler = NULL;
  1931. int rc = 0;
  1932. if (sde_enc->input_handler) {
  1933. SDE_ERROR_ENC(sde_enc,
  1934. "input_handle is active. unexpected\n");
  1935. return -EINVAL;
  1936. }
  1937. input_handler = kzalloc(sizeof(*sde_enc->input_handler), GFP_KERNEL);
  1938. if (!input_handler)
  1939. return -ENOMEM;
  1940. input_handler->event = sde_encoder_input_event_handler;
  1941. input_handler->connect = _sde_encoder_input_connect;
  1942. input_handler->disconnect = _sde_encoder_input_disconnect;
  1943. input_handler->name = "sde";
  1944. input_handler->id_table = sde_input_ids;
  1945. input_handler->private = sde_enc;
  1946. sde_enc->input_handler = input_handler;
  1947. return rc;
  1948. }
  1949. static void _sde_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
  1950. {
  1951. struct sde_encoder_virt *sde_enc = NULL;
  1952. struct msm_drm_private *priv;
  1953. struct sde_kms *sde_kms;
  1954. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  1955. SDE_ERROR("invalid parameters\n");
  1956. return;
  1957. }
  1958. priv = drm_enc->dev->dev_private;
  1959. sde_kms = to_sde_kms(priv->kms);
  1960. if (!sde_kms) {
  1961. SDE_ERROR("invalid sde_kms\n");
  1962. return;
  1963. }
  1964. sde_enc = to_sde_encoder_virt(drm_enc);
  1965. if (!sde_enc || !sde_enc->cur_master) {
  1966. SDE_DEBUG("invalid sde encoder/master\n");
  1967. return;
  1968. }
  1969. if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DisplayPort &&
  1970. sde_enc->cur_master->hw_mdptop &&
  1971. sde_enc->cur_master->hw_mdptop->ops.intf_audio_select)
  1972. sde_enc->cur_master->hw_mdptop->ops.intf_audio_select(
  1973. sde_enc->cur_master->hw_mdptop);
  1974. if (sde_enc->cur_master->hw_mdptop &&
  1975. sde_enc->cur_master->hw_mdptop->ops.reset_ubwc)
  1976. sde_enc->cur_master->hw_mdptop->ops.reset_ubwc(
  1977. sde_enc->cur_master->hw_mdptop,
  1978. sde_kms->catalog);
  1979. if (sde_enc->cur_master->hw_ctl &&
  1980. sde_enc->cur_master->hw_ctl->ops.setup_intf_cfg_v1 &&
  1981. !sde_enc->cur_master->cont_splash_enabled)
  1982. sde_enc->cur_master->hw_ctl->ops.setup_intf_cfg_v1(
  1983. sde_enc->cur_master->hw_ctl,
  1984. &sde_enc->cur_master->intf_cfg_v1);
  1985. _sde_encoder_update_vsync_source(sde_enc, &sde_enc->disp_info, false);
  1986. sde_encoder_control_te(drm_enc, true);
  1987. memset(&sde_enc->prv_conn_roi, 0, sizeof(sde_enc->prv_conn_roi));
  1988. memset(&sde_enc->cur_conn_roi, 0, sizeof(sde_enc->cur_conn_roi));
  1989. }
  1990. void sde_encoder_virt_restore(struct drm_encoder *drm_enc)
  1991. {
  1992. struct sde_encoder_virt *sde_enc = NULL;
  1993. int i;
  1994. if (!drm_enc) {
  1995. SDE_ERROR("invalid encoder\n");
  1996. return;
  1997. }
  1998. sde_enc = to_sde_encoder_virt(drm_enc);
  1999. if (!sde_enc->cur_master) {
  2000. SDE_DEBUG("virt encoder has no master\n");
  2001. return;
  2002. }
  2003. memset(&sde_enc->cur_master->intf_cfg_v1, 0,
  2004. sizeof(sde_enc->cur_master->intf_cfg_v1));
  2005. sde_enc->idle_pc_restore = true;
  2006. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2007. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2008. if (!phys)
  2009. continue;
  2010. if (phys->hw_ctl && phys->hw_ctl->ops.clear_pending_flush)
  2011. phys->hw_ctl->ops.clear_pending_flush(phys->hw_ctl);
  2012. if ((phys != sde_enc->cur_master) && phys->ops.restore)
  2013. phys->ops.restore(phys);
  2014. }
  2015. if (sde_enc->cur_master->ops.restore)
  2016. sde_enc->cur_master->ops.restore(sde_enc->cur_master);
  2017. _sde_encoder_virt_enable_helper(drm_enc);
  2018. }
  2019. static void sde_encoder_off_work(struct kthread_work *work)
  2020. {
  2021. struct sde_encoder_virt *sde_enc = container_of(work,
  2022. struct sde_encoder_virt, delayed_off_work.work);
  2023. struct drm_encoder *drm_enc;
  2024. if (!sde_enc) {
  2025. SDE_ERROR("invalid sde encoder\n");
  2026. return;
  2027. }
  2028. drm_enc = &sde_enc->base;
  2029. SDE_ATRACE_BEGIN("sde_encoder_off_work");
  2030. sde_encoder_idle_request(drm_enc);
  2031. SDE_ATRACE_END("sde_encoder_off_work");
  2032. }
  2033. static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)
  2034. {
  2035. struct sde_encoder_virt *sde_enc = NULL;
  2036. int i, ret = 0;
  2037. struct msm_compression_info *comp_info = NULL;
  2038. struct drm_display_mode *cur_mode = NULL;
  2039. struct msm_display_info *disp_info;
  2040. if (!drm_enc) {
  2041. SDE_ERROR("invalid encoder\n");
  2042. return;
  2043. }
  2044. sde_enc = to_sde_encoder_virt(drm_enc);
  2045. disp_info = &sde_enc->disp_info;
  2046. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2047. SDE_ERROR("power resource is not enabled\n");
  2048. return;
  2049. }
  2050. if (drm_enc->crtc && !sde_enc->crtc)
  2051. sde_enc->crtc = drm_enc->crtc;
  2052. comp_info = &sde_enc->mode_info.comp_info;
  2053. cur_mode = &sde_enc->base.crtc->state->adjusted_mode;
  2054. SDE_DEBUG_ENC(sde_enc, "\n");
  2055. SDE_EVT32(DRMID(drm_enc), cur_mode->hdisplay, cur_mode->vdisplay);
  2056. sde_enc->cur_master = NULL;
  2057. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2058. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2059. if (phys && phys->ops.is_master && phys->ops.is_master(phys)) {
  2060. SDE_DEBUG_ENC(sde_enc, "master is now idx %d\n", i);
  2061. sde_enc->cur_master = phys;
  2062. break;
  2063. }
  2064. }
  2065. if (!sde_enc->cur_master) {
  2066. SDE_ERROR("virt encoder has no master! num_phys %d\n", i);
  2067. return;
  2068. }
  2069. /* register input handler if not already registered */
  2070. if (sde_enc->input_handler && !msm_is_mode_seamless_dms(cur_mode) &&
  2071. sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE) &&
  2072. !msm_is_mode_seamless_dyn_clk(cur_mode)) {
  2073. ret = _sde_encoder_input_handler_register(
  2074. sde_enc->input_handler);
  2075. if (ret)
  2076. SDE_ERROR(
  2077. "input handler registration failed, rc = %d\n", ret);
  2078. }
  2079. if (!(msm_is_mode_seamless_vrr(cur_mode)
  2080. || msm_is_mode_seamless_dms(cur_mode)
  2081. || msm_is_mode_seamless_dyn_clk(cur_mode)))
  2082. kthread_init_delayed_work(&sde_enc->delayed_off_work,
  2083. sde_encoder_off_work);
  2084. ret = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
  2085. if (ret) {
  2086. SDE_ERROR_ENC(sde_enc, "sde resource control failed: %d\n",
  2087. ret);
  2088. return;
  2089. }
  2090. memset(&sde_enc->cur_master->intf_cfg_v1, 0,
  2091. sizeof(sde_enc->cur_master->intf_cfg_v1));
  2092. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2093. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2094. if (!phys)
  2095. continue;
  2096. phys->comp_type = comp_info->comp_type;
  2097. phys->comp_ratio = comp_info->comp_ratio;
  2098. phys->wide_bus_en = sde_enc->mode_info.wide_bus_en;
  2099. phys->frame_trigger_mode = sde_enc->frame_trigger_mode;
  2100. if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC) {
  2101. phys->dsc_extra_pclk_cycle_cnt =
  2102. comp_info->dsc_info.pclk_per_line;
  2103. phys->dsc_extra_disp_width =
  2104. comp_info->dsc_info.extra_width;
  2105. }
  2106. if (phys != sde_enc->cur_master) {
  2107. /**
  2108. * on DMS request, the encoder will be enabled
  2109. * already. Invoke restore to reconfigure the
  2110. * new mode.
  2111. */
  2112. if ((msm_is_mode_seamless_dms(cur_mode) ||
  2113. msm_is_mode_seamless_dyn_clk(cur_mode)) &&
  2114. phys->ops.restore)
  2115. phys->ops.restore(phys);
  2116. else if (phys->ops.enable)
  2117. phys->ops.enable(phys);
  2118. }
  2119. if (sde_enc->misr_enable && phys->ops.setup_misr &&
  2120. (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE)))
  2121. phys->ops.setup_misr(phys, true,
  2122. sde_enc->misr_frame_count);
  2123. }
  2124. if ((msm_is_mode_seamless_dms(cur_mode) ||
  2125. msm_is_mode_seamless_dyn_clk(cur_mode)) &&
  2126. sde_enc->cur_master->ops.restore)
  2127. sde_enc->cur_master->ops.restore(sde_enc->cur_master);
  2128. else if (sde_enc->cur_master->ops.enable)
  2129. sde_enc->cur_master->ops.enable(sde_enc->cur_master);
  2130. _sde_encoder_virt_enable_helper(drm_enc);
  2131. }
  2132. static void sde_encoder_virt_disable(struct drm_encoder *drm_enc)
  2133. {
  2134. struct sde_encoder_virt *sde_enc = NULL;
  2135. struct msm_drm_private *priv;
  2136. struct sde_kms *sde_kms;
  2137. enum sde_intf_mode intf_mode;
  2138. int i = 0;
  2139. if (!drm_enc) {
  2140. SDE_ERROR("invalid encoder\n");
  2141. return;
  2142. } else if (!drm_enc->dev) {
  2143. SDE_ERROR("invalid dev\n");
  2144. return;
  2145. } else if (!drm_enc->dev->dev_private) {
  2146. SDE_ERROR("invalid dev_private\n");
  2147. return;
  2148. }
  2149. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2150. SDE_ERROR("power resource is not enabled\n");
  2151. return;
  2152. }
  2153. sde_enc = to_sde_encoder_virt(drm_enc);
  2154. SDE_DEBUG_ENC(sde_enc, "\n");
  2155. priv = drm_enc->dev->dev_private;
  2156. sde_kms = to_sde_kms(priv->kms);
  2157. intf_mode = sde_encoder_get_intf_mode(drm_enc);
  2158. SDE_EVT32(DRMID(drm_enc));
  2159. /* wait for idle */
  2160. sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
  2161. if (sde_enc->input_handler &&
  2162. sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  2163. input_unregister_handler(sde_enc->input_handler);
  2164. /*
  2165. * For primary command mode and video mode encoders, execute the
  2166. * resource control pre-stop operations before the physical encoders
  2167. * are disabled, to allow the rsc to transition its states properly.
  2168. *
  2169. * For other encoder types, rsc should not be enabled until after
  2170. * they have been fully disabled, so delay the pre-stop operations
  2171. * until after the physical disable calls have returned.
  2172. */
  2173. if (sde_enc->disp_info.display_type == SDE_CONNECTOR_PRIMARY &&
  2174. (intf_mode == INTF_MODE_CMD || intf_mode == INTF_MODE_VIDEO)) {
  2175. sde_encoder_resource_control(drm_enc,
  2176. SDE_ENC_RC_EVENT_PRE_STOP);
  2177. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2178. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2179. if (phys && phys->ops.disable)
  2180. phys->ops.disable(phys);
  2181. }
  2182. } else {
  2183. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2184. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2185. if (phys && phys->ops.disable)
  2186. phys->ops.disable(phys);
  2187. }
  2188. sde_encoder_resource_control(drm_enc,
  2189. SDE_ENC_RC_EVENT_PRE_STOP);
  2190. }
  2191. /*
  2192. * disable dce after the transfer is complete (for command mode)
  2193. * and after physical encoder is disabled, to make sure timing
  2194. * engine is already disabled (for video mode).
  2195. */
  2196. sde_encoder_dce_disable(sde_enc);
  2197. sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_STOP);
  2198. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2199. if (sde_enc->phys_encs[i]) {
  2200. sde_enc->phys_encs[i]->cont_splash_enabled = false;
  2201. sde_enc->phys_encs[i]->connector = NULL;
  2202. }
  2203. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  2204. }
  2205. sde_enc->cur_master = NULL;
  2206. /*
  2207. * clear the cached crtc in sde_enc on use case finish, after all the
  2208. * outstanding events and timers have been completed
  2209. */
  2210. sde_enc->crtc = NULL;
  2211. memset(&sde_enc->mode_info, 0, sizeof(sde_enc->mode_info));
  2212. SDE_DEBUG_ENC(sde_enc, "encoder disabled\n");
  2213. sde_rm_release(&sde_kms->rm, drm_enc, false);
  2214. }
  2215. void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
  2216. struct sde_encoder_phys_wb *wb_enc)
  2217. {
  2218. struct sde_encoder_virt *sde_enc;
  2219. phys_enc->hw_ctl->ops.reset(phys_enc->hw_ctl);
  2220. sde_encoder_helper_reset_mixers(phys_enc, NULL);
  2221. if (wb_enc) {
  2222. if (wb_enc->hw_wb->ops.bind_pingpong_blk) {
  2223. wb_enc->hw_wb->ops.bind_pingpong_blk(wb_enc->hw_wb,
  2224. false, phys_enc->hw_pp->idx);
  2225. if (phys_enc->hw_ctl->ops.update_bitmask_wb)
  2226. phys_enc->hw_ctl->ops.update_bitmask_wb(
  2227. phys_enc->hw_ctl,
  2228. wb_enc->hw_wb->idx, true);
  2229. }
  2230. } else {
  2231. if (phys_enc->hw_intf->ops.bind_pingpong_blk) {
  2232. phys_enc->hw_intf->ops.bind_pingpong_blk(
  2233. phys_enc->hw_intf, false,
  2234. phys_enc->hw_pp->idx);
  2235. if (phys_enc->hw_ctl->ops.update_bitmask_intf)
  2236. phys_enc->hw_ctl->ops.update_bitmask_intf(
  2237. phys_enc->hw_ctl,
  2238. phys_enc->hw_intf->idx, true);
  2239. }
  2240. }
  2241. if (phys_enc->hw_pp && phys_enc->hw_pp->ops.reset_3d_mode) {
  2242. phys_enc->hw_pp->ops.reset_3d_mode(phys_enc->hw_pp);
  2243. if (phys_enc->hw_ctl->ops.update_bitmask_merge3d &&
  2244. phys_enc->hw_pp->merge_3d)
  2245. phys_enc->hw_ctl->ops.update_bitmask_merge3d(
  2246. phys_enc->hw_ctl,
  2247. phys_enc->hw_pp->merge_3d->idx, true);
  2248. }
  2249. if (phys_enc->hw_cdm && phys_enc->hw_cdm->ops.bind_pingpong_blk &&
  2250. phys_enc->hw_pp) {
  2251. phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm,
  2252. false, phys_enc->hw_pp->idx);
  2253. if (phys_enc->hw_ctl->ops.update_bitmask_cdm)
  2254. phys_enc->hw_ctl->ops.update_bitmask_cdm(
  2255. phys_enc->hw_ctl,
  2256. phys_enc->hw_cdm->idx, true);
  2257. }
  2258. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  2259. if (phys_enc == sde_enc->cur_master && phys_enc->hw_pp &&
  2260. phys_enc->hw_ctl->ops.reset_post_disable)
  2261. phys_enc->hw_ctl->ops.reset_post_disable(
  2262. phys_enc->hw_ctl, &phys_enc->intf_cfg_v1,
  2263. phys_enc->hw_pp->merge_3d ?
  2264. phys_enc->hw_pp->merge_3d->idx : 0);
  2265. phys_enc->hw_ctl->ops.trigger_flush(phys_enc->hw_ctl);
  2266. phys_enc->hw_ctl->ops.trigger_start(phys_enc->hw_ctl);
  2267. }
  2268. static enum sde_intf sde_encoder_get_intf(struct sde_mdss_cfg *catalog,
  2269. enum sde_intf_type type, u32 controller_id)
  2270. {
  2271. int i = 0;
  2272. for (i = 0; i < catalog->intf_count; i++) {
  2273. if (catalog->intf[i].type == type
  2274. && catalog->intf[i].controller_id == controller_id) {
  2275. return catalog->intf[i].id;
  2276. }
  2277. }
  2278. return INTF_MAX;
  2279. }
  2280. static enum sde_wb sde_encoder_get_wb(struct sde_mdss_cfg *catalog,
  2281. enum sde_intf_type type, u32 controller_id)
  2282. {
  2283. if (controller_id < catalog->wb_count)
  2284. return catalog->wb[controller_id].id;
  2285. return WB_MAX;
  2286. }
  2287. void sde_encoder_perf_uidle_status(struct sde_kms *sde_kms,
  2288. struct drm_crtc *crtc)
  2289. {
  2290. struct sde_hw_uidle *uidle;
  2291. struct sde_uidle_cntr cntr;
  2292. struct sde_uidle_status status;
  2293. if (!sde_kms || !crtc || !sde_kms->hw_uidle) {
  2294. pr_err("invalid params %d %d\n",
  2295. !sde_kms, !crtc);
  2296. return;
  2297. }
  2298. /* check if perf counters are enabled and setup */
  2299. if (!sde_kms->catalog->uidle_cfg.perf_cntr_en)
  2300. return;
  2301. uidle = sde_kms->hw_uidle;
  2302. if ((sde_kms->catalog->uidle_cfg.debugfs_perf & SDE_PERF_UIDLE_STATUS)
  2303. && uidle->ops.uidle_get_status) {
  2304. uidle->ops.uidle_get_status(uidle, &status);
  2305. trace_sde_perf_uidle_status(
  2306. crtc->base.id,
  2307. status.uidle_danger_status_0,
  2308. status.uidle_danger_status_1,
  2309. status.uidle_safe_status_0,
  2310. status.uidle_safe_status_1,
  2311. status.uidle_idle_status_0,
  2312. status.uidle_idle_status_1,
  2313. status.uidle_fal_status_0,
  2314. status.uidle_fal_status_1,
  2315. status.uidle_status,
  2316. status.uidle_en_fal10);
  2317. }
  2318. if ((sde_kms->catalog->uidle_cfg.debugfs_perf & SDE_PERF_UIDLE_CNT)
  2319. && uidle->ops.uidle_get_cntr) {
  2320. uidle->ops.uidle_get_cntr(uidle, &cntr);
  2321. trace_sde_perf_uidle_cntr(
  2322. crtc->base.id,
  2323. cntr.fal1_gate_cntr,
  2324. cntr.fal10_gate_cntr,
  2325. cntr.fal_wait_gate_cntr,
  2326. cntr.fal1_num_transitions_cntr,
  2327. cntr.fal10_num_transitions_cntr,
  2328. cntr.min_gate_cntr,
  2329. cntr.max_gate_cntr);
  2330. }
  2331. }
  2332. static void sde_encoder_vblank_callback(struct drm_encoder *drm_enc,
  2333. struct sde_encoder_phys *phy_enc)
  2334. {
  2335. struct sde_encoder_virt *sde_enc = NULL;
  2336. unsigned long lock_flags;
  2337. if (!drm_enc || !phy_enc)
  2338. return;
  2339. SDE_ATRACE_BEGIN("encoder_vblank_callback");
  2340. sde_enc = to_sde_encoder_virt(drm_enc);
  2341. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2342. if (sde_enc->crtc_vblank_cb)
  2343. sde_enc->crtc_vblank_cb(sde_enc->crtc_vblank_cb_data);
  2344. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2345. if (phy_enc->sde_kms &&
  2346. phy_enc->sde_kms->catalog->uidle_cfg.debugfs_perf)
  2347. sde_encoder_perf_uidle_status(phy_enc->sde_kms, sde_enc->crtc);
  2348. atomic_inc(&phy_enc->vsync_cnt);
  2349. SDE_ATRACE_END("encoder_vblank_callback");
  2350. }
  2351. static void sde_encoder_underrun_callback(struct drm_encoder *drm_enc,
  2352. struct sde_encoder_phys *phy_enc)
  2353. {
  2354. if (!phy_enc)
  2355. return;
  2356. SDE_ATRACE_BEGIN("encoder_underrun_callback");
  2357. atomic_inc(&phy_enc->underrun_cnt);
  2358. SDE_EVT32(DRMID(drm_enc), atomic_read(&phy_enc->underrun_cnt));
  2359. trace_sde_encoder_underrun(DRMID(drm_enc),
  2360. atomic_read(&phy_enc->underrun_cnt));
  2361. SDE_DBG_CTRL("stop_ftrace");
  2362. SDE_DBG_CTRL("panic_underrun");
  2363. SDE_ATRACE_END("encoder_underrun_callback");
  2364. }
  2365. void sde_encoder_register_vblank_callback(struct drm_encoder *drm_enc,
  2366. void (*vbl_cb)(void *), void *vbl_data)
  2367. {
  2368. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2369. unsigned long lock_flags;
  2370. bool enable;
  2371. int i;
  2372. enable = vbl_cb ? true : false;
  2373. if (!drm_enc) {
  2374. SDE_ERROR("invalid encoder\n");
  2375. return;
  2376. }
  2377. SDE_DEBUG_ENC(sde_enc, "\n");
  2378. SDE_EVT32(DRMID(drm_enc), enable);
  2379. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2380. sde_enc->crtc_vblank_cb = vbl_cb;
  2381. sde_enc->crtc_vblank_cb_data = vbl_data;
  2382. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2383. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2384. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2385. if (phys && phys->ops.control_vblank_irq)
  2386. phys->ops.control_vblank_irq(phys, enable);
  2387. }
  2388. sde_enc->vblank_enabled = enable;
  2389. }
  2390. void sde_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
  2391. void (*frame_event_cb)(void *, u32 event),
  2392. struct drm_crtc *crtc)
  2393. {
  2394. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2395. unsigned long lock_flags;
  2396. bool enable;
  2397. enable = frame_event_cb ? true : false;
  2398. if (!drm_enc) {
  2399. SDE_ERROR("invalid encoder\n");
  2400. return;
  2401. }
  2402. SDE_DEBUG_ENC(sde_enc, "\n");
  2403. SDE_EVT32(DRMID(drm_enc), enable, 0);
  2404. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2405. sde_enc->crtc_frame_event_cb = frame_event_cb;
  2406. sde_enc->crtc_frame_event_cb_data.crtc = crtc;
  2407. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2408. }
  2409. static void sde_encoder_frame_done_callback(
  2410. struct drm_encoder *drm_enc,
  2411. struct sde_encoder_phys *ready_phys, u32 event)
  2412. {
  2413. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2414. unsigned int i;
  2415. bool trigger = true;
  2416. bool is_cmd_mode = false;
  2417. enum sde_rm_topology_name topology = SDE_RM_TOPOLOGY_NONE;
  2418. if (!drm_enc || !sde_enc->cur_master) {
  2419. SDE_ERROR("invalid param: drm_enc %pK, cur_master %pK\n",
  2420. drm_enc, drm_enc ? sde_enc->cur_master : 0);
  2421. return;
  2422. }
  2423. sde_enc->crtc_frame_event_cb_data.connector =
  2424. sde_enc->cur_master->connector;
  2425. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  2426. is_cmd_mode = true;
  2427. if (event & (SDE_ENCODER_FRAME_EVENT_DONE
  2428. | SDE_ENCODER_FRAME_EVENT_ERROR
  2429. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD) && is_cmd_mode) {
  2430. if (ready_phys->connector)
  2431. topology = sde_connector_get_topology_name(
  2432. ready_phys->connector);
  2433. /* One of the physical encoders has become idle */
  2434. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2435. if (sde_enc->phys_encs[i] == ready_phys) {
  2436. SDE_EVT32_VERBOSE(DRMID(drm_enc), i,
  2437. atomic_read(&sde_enc->frame_done_cnt[i]));
  2438. if (!atomic_add_unless(
  2439. &sde_enc->frame_done_cnt[i], 1, 1)) {
  2440. SDE_EVT32(DRMID(drm_enc), event,
  2441. ready_phys->intf_idx,
  2442. SDE_EVTLOG_ERROR);
  2443. SDE_ERROR_ENC(sde_enc,
  2444. "intf idx:%d, event:%d\n",
  2445. ready_phys->intf_idx, event);
  2446. return;
  2447. }
  2448. }
  2449. if (topology != SDE_RM_TOPOLOGY_PPSPLIT &&
  2450. atomic_read(&sde_enc->frame_done_cnt[i]) != 1)
  2451. trigger = false;
  2452. }
  2453. if (trigger) {
  2454. sde_encoder_resource_control(drm_enc,
  2455. SDE_ENC_RC_EVENT_FRAME_DONE);
  2456. if (sde_enc->crtc_frame_event_cb)
  2457. sde_enc->crtc_frame_event_cb(
  2458. &sde_enc->crtc_frame_event_cb_data,
  2459. event);
  2460. for (i = 0; i < sde_enc->num_phys_encs; i++)
  2461. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  2462. }
  2463. } else if (sde_enc->crtc_frame_event_cb) {
  2464. if (!is_cmd_mode)
  2465. sde_encoder_resource_control(drm_enc,
  2466. SDE_ENC_RC_EVENT_FRAME_DONE);
  2467. sde_enc->crtc_frame_event_cb(
  2468. &sde_enc->crtc_frame_event_cb_data, event);
  2469. }
  2470. }
  2471. static void sde_encoder_get_qsync_fps_callback(
  2472. struct drm_encoder *drm_enc,
  2473. u32 *qsync_fps)
  2474. {
  2475. struct msm_display_info *disp_info;
  2476. struct sde_encoder_virt *sde_enc;
  2477. if (!qsync_fps)
  2478. return;
  2479. *qsync_fps = 0;
  2480. if (!drm_enc) {
  2481. SDE_ERROR("invalid drm encoder\n");
  2482. return;
  2483. }
  2484. sde_enc = to_sde_encoder_virt(drm_enc);
  2485. disp_info = &sde_enc->disp_info;
  2486. *qsync_fps = disp_info->qsync_min_fps;
  2487. }
  2488. int sde_encoder_idle_request(struct drm_encoder *drm_enc)
  2489. {
  2490. struct sde_encoder_virt *sde_enc;
  2491. if (!drm_enc) {
  2492. SDE_ERROR("invalid drm encoder\n");
  2493. return -EINVAL;
  2494. }
  2495. sde_enc = to_sde_encoder_virt(drm_enc);
  2496. sde_encoder_resource_control(&sde_enc->base,
  2497. SDE_ENC_RC_EVENT_ENTER_IDLE);
  2498. return 0;
  2499. }
  2500. /**
  2501. * _sde_encoder_trigger_flush - trigger flush for a physical encoder
  2502. * drm_enc: Pointer to drm encoder structure
  2503. * phys: Pointer to physical encoder structure
  2504. * extra_flush: Additional bit mask to include in flush trigger
  2505. */
  2506. static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc,
  2507. struct sde_encoder_phys *phys,
  2508. struct sde_ctl_flush_cfg *extra_flush)
  2509. {
  2510. struct sde_hw_ctl *ctl;
  2511. unsigned long lock_flags;
  2512. struct sde_encoder_virt *sde_enc;
  2513. int pend_ret_fence_cnt;
  2514. struct sde_connector *c_conn;
  2515. if (!drm_enc || !phys) {
  2516. SDE_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n",
  2517. !drm_enc, !phys);
  2518. return;
  2519. }
  2520. sde_enc = to_sde_encoder_virt(drm_enc);
  2521. c_conn = to_sde_connector(phys->connector);
  2522. if (!phys->hw_pp) {
  2523. SDE_ERROR("invalid pingpong hw\n");
  2524. return;
  2525. }
  2526. ctl = phys->hw_ctl;
  2527. if (!ctl || !phys->ops.trigger_flush) {
  2528. SDE_ERROR("missing ctl/trigger cb\n");
  2529. return;
  2530. }
  2531. if (phys->split_role == ENC_ROLE_SKIP) {
  2532. SDE_DEBUG_ENC(to_sde_encoder_virt(phys->parent),
  2533. "skip flush pp%d ctl%d\n",
  2534. phys->hw_pp->idx - PINGPONG_0,
  2535. ctl->idx - CTL_0);
  2536. return;
  2537. }
  2538. /* update pending counts and trigger kickoff ctl flush atomically */
  2539. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2540. if (phys->ops.is_master && phys->ops.is_master(phys))
  2541. atomic_inc(&phys->pending_retire_fence_cnt);
  2542. pend_ret_fence_cnt = atomic_read(&phys->pending_retire_fence_cnt);
  2543. if (phys->hw_intf && phys->hw_intf->cap->type == INTF_DP &&
  2544. ctl->ops.update_bitmask_periph) {
  2545. /* perform peripheral flush on every frame update for dp dsc */
  2546. if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC &&
  2547. phys->comp_ratio && c_conn->ops.update_pps) {
  2548. c_conn->ops.update_pps(phys->connector, NULL,
  2549. c_conn->display);
  2550. ctl->ops.update_bitmask_periph(ctl,
  2551. phys->hw_intf->idx, 1);
  2552. }
  2553. if (sde_enc->dynamic_hdr_updated)
  2554. ctl->ops.update_bitmask_periph(ctl,
  2555. phys->hw_intf->idx, 1);
  2556. }
  2557. if ((extra_flush && extra_flush->pending_flush_mask)
  2558. && ctl->ops.update_pending_flush)
  2559. ctl->ops.update_pending_flush(ctl, extra_flush);
  2560. phys->ops.trigger_flush(phys);
  2561. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2562. if (ctl->ops.get_pending_flush) {
  2563. struct sde_ctl_flush_cfg pending_flush = {0,};
  2564. ctl->ops.get_pending_flush(ctl, &pending_flush);
  2565. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,
  2566. ctl->idx - CTL_0,
  2567. pending_flush.pending_flush_mask,
  2568. pend_ret_fence_cnt);
  2569. } else {
  2570. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,
  2571. ctl->idx - CTL_0,
  2572. pend_ret_fence_cnt);
  2573. }
  2574. }
  2575. /**
  2576. * _sde_encoder_trigger_start - trigger start for a physical encoder
  2577. * phys: Pointer to physical encoder structure
  2578. */
  2579. static inline void _sde_encoder_trigger_start(struct sde_encoder_phys *phys)
  2580. {
  2581. struct sde_hw_ctl *ctl;
  2582. struct sde_encoder_virt *sde_enc;
  2583. if (!phys) {
  2584. SDE_ERROR("invalid argument(s)\n");
  2585. return;
  2586. }
  2587. if (!phys->hw_pp) {
  2588. SDE_ERROR("invalid pingpong hw\n");
  2589. return;
  2590. }
  2591. if (!phys->parent) {
  2592. SDE_ERROR("invalid parent\n");
  2593. return;
  2594. }
  2595. /* avoid ctrl start for encoder in clone mode */
  2596. if (phys->in_clone_mode)
  2597. return;
  2598. ctl = phys->hw_ctl;
  2599. sde_enc = to_sde_encoder_virt(phys->parent);
  2600. if (phys->split_role == ENC_ROLE_SKIP) {
  2601. SDE_DEBUG_ENC(sde_enc,
  2602. "skip start pp%d ctl%d\n",
  2603. phys->hw_pp->idx - PINGPONG_0,
  2604. ctl->idx - CTL_0);
  2605. return;
  2606. }
  2607. if (phys->ops.trigger_start && phys->enable_state != SDE_ENC_DISABLED)
  2608. phys->ops.trigger_start(phys);
  2609. }
  2610. void sde_encoder_helper_trigger_flush(struct sde_encoder_phys *phys_enc)
  2611. {
  2612. struct sde_hw_ctl *ctl;
  2613. if (!phys_enc) {
  2614. SDE_ERROR("invalid encoder\n");
  2615. return;
  2616. }
  2617. ctl = phys_enc->hw_ctl;
  2618. if (ctl && ctl->ops.trigger_flush)
  2619. ctl->ops.trigger_flush(ctl);
  2620. }
  2621. void sde_encoder_helper_trigger_start(struct sde_encoder_phys *phys_enc)
  2622. {
  2623. struct sde_hw_ctl *ctl;
  2624. if (!phys_enc) {
  2625. SDE_ERROR("invalid encoder\n");
  2626. return;
  2627. }
  2628. ctl = phys_enc->hw_ctl;
  2629. if (ctl && ctl->ops.trigger_start) {
  2630. ctl->ops.trigger_start(ctl);
  2631. SDE_EVT32(DRMID(phys_enc->parent), ctl->idx - CTL_0);
  2632. }
  2633. }
  2634. void sde_encoder_helper_hw_reset(struct sde_encoder_phys *phys_enc)
  2635. {
  2636. struct sde_encoder_virt *sde_enc;
  2637. struct sde_connector *sde_con;
  2638. void *sde_con_disp;
  2639. struct sde_hw_ctl *ctl;
  2640. int rc;
  2641. if (!phys_enc) {
  2642. SDE_ERROR("invalid encoder\n");
  2643. return;
  2644. }
  2645. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  2646. ctl = phys_enc->hw_ctl;
  2647. if (!ctl || !ctl->ops.reset)
  2648. return;
  2649. SDE_DEBUG_ENC(sde_enc, "ctl %d reset\n", ctl->idx);
  2650. SDE_EVT32(DRMID(phys_enc->parent), ctl->idx);
  2651. if (phys_enc->ops.is_master && phys_enc->ops.is_master(phys_enc) &&
  2652. phys_enc->connector) {
  2653. sde_con = to_sde_connector(phys_enc->connector);
  2654. sde_con_disp = sde_connector_get_display(phys_enc->connector);
  2655. if (sde_con->ops.soft_reset) {
  2656. rc = sde_con->ops.soft_reset(sde_con_disp);
  2657. if (rc) {
  2658. SDE_ERROR_ENC(sde_enc,
  2659. "connector soft reset failure\n");
  2660. SDE_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus",
  2661. "panic");
  2662. }
  2663. }
  2664. }
  2665. phys_enc->enable_state = SDE_ENC_ENABLED;
  2666. }
  2667. /**
  2668. * _sde_encoder_kickoff_phys - handle physical encoder kickoff
  2669. * Iterate through the physical encoders and perform consolidated flush
  2670. * and/or control start triggering as needed. This is done in the virtual
  2671. * encoder rather than the individual physical ones in order to handle
  2672. * use cases that require visibility into multiple physical encoders at
  2673. * a time.
  2674. * sde_enc: Pointer to virtual encoder structure
  2675. */
  2676. static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc)
  2677. {
  2678. struct sde_hw_ctl *ctl;
  2679. uint32_t i;
  2680. struct sde_ctl_flush_cfg pending_flush = {0,};
  2681. u32 pending_kickoff_cnt;
  2682. struct msm_drm_private *priv = NULL;
  2683. struct sde_kms *sde_kms = NULL;
  2684. struct sde_crtc_misr_info crtc_misr_info = {false, 0};
  2685. bool is_regdma_blocking = false, is_vid_mode = false;
  2686. if (!sde_enc) {
  2687. SDE_ERROR("invalid encoder\n");
  2688. return;
  2689. }
  2690. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
  2691. is_vid_mode = true;
  2692. is_regdma_blocking = (is_vid_mode ||
  2693. _sde_encoder_is_autorefresh_enabled(sde_enc));
  2694. /* don't perform flush/start operations for slave encoders */
  2695. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2696. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2697. enum sde_rm_topology_name topology = SDE_RM_TOPOLOGY_NONE;
  2698. if (!phys || phys->enable_state == SDE_ENC_DISABLED)
  2699. continue;
  2700. ctl = phys->hw_ctl;
  2701. if (!ctl)
  2702. continue;
  2703. if (phys->connector)
  2704. topology = sde_connector_get_topology_name(
  2705. phys->connector);
  2706. if (!phys->ops.needs_single_flush ||
  2707. !phys->ops.needs_single_flush(phys)) {
  2708. if (ctl->ops.reg_dma_flush)
  2709. ctl->ops.reg_dma_flush(ctl, is_regdma_blocking);
  2710. _sde_encoder_trigger_flush(&sde_enc->base, phys, 0x0);
  2711. } else if (ctl->ops.get_pending_flush) {
  2712. ctl->ops.get_pending_flush(ctl, &pending_flush);
  2713. }
  2714. }
  2715. /* for split flush, combine pending flush masks and send to master */
  2716. if (pending_flush.pending_flush_mask && sde_enc->cur_master) {
  2717. ctl = sde_enc->cur_master->hw_ctl;
  2718. if (ctl->ops.reg_dma_flush)
  2719. ctl->ops.reg_dma_flush(ctl, is_regdma_blocking);
  2720. _sde_encoder_trigger_flush(&sde_enc->base, sde_enc->cur_master,
  2721. &pending_flush);
  2722. }
  2723. /* update pending_kickoff_cnt AFTER flush but before trigger start */
  2724. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2725. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2726. if (!phys || phys->enable_state == SDE_ENC_DISABLED)
  2727. continue;
  2728. if (!phys->ops.needs_single_flush ||
  2729. !phys->ops.needs_single_flush(phys)) {
  2730. pending_kickoff_cnt =
  2731. sde_encoder_phys_inc_pending(phys);
  2732. SDE_EVT32(pending_kickoff_cnt, SDE_EVTLOG_FUNC_CASE1);
  2733. } else {
  2734. pending_kickoff_cnt =
  2735. sde_encoder_phys_inc_pending(phys);
  2736. SDE_EVT32(pending_kickoff_cnt,
  2737. pending_flush.pending_flush_mask,
  2738. SDE_EVTLOG_FUNC_CASE2);
  2739. }
  2740. }
  2741. if (sde_enc->misr_enable)
  2742. sde_encoder_misr_configure(&sde_enc->base, true,
  2743. sde_enc->misr_frame_count);
  2744. sde_crtc_get_misr_info(sde_enc->crtc, &crtc_misr_info);
  2745. if (crtc_misr_info.misr_enable)
  2746. sde_crtc_misr_setup(sde_enc->crtc, true,
  2747. crtc_misr_info.misr_frame_count);
  2748. _sde_encoder_trigger_start(sde_enc->cur_master);
  2749. if (sde_enc->elevated_ahb_vote) {
  2750. priv = sde_enc->base.dev->dev_private;
  2751. if (priv != NULL) {
  2752. sde_kms = to_sde_kms(priv->kms);
  2753. if (sde_kms != NULL) {
  2754. sde_power_scale_reg_bus(&priv->phandle,
  2755. VOTE_INDEX_LOW,
  2756. false);
  2757. }
  2758. }
  2759. sde_enc->elevated_ahb_vote = false;
  2760. }
  2761. }
  2762. static void _sde_encoder_ppsplit_swap_intf_for_right_only_update(
  2763. struct drm_encoder *drm_enc,
  2764. unsigned long *affected_displays,
  2765. int num_active_phys)
  2766. {
  2767. struct sde_encoder_virt *sde_enc;
  2768. struct sde_encoder_phys *master;
  2769. enum sde_rm_topology_name topology;
  2770. bool is_right_only;
  2771. if (!drm_enc || !affected_displays)
  2772. return;
  2773. sde_enc = to_sde_encoder_virt(drm_enc);
  2774. master = sde_enc->cur_master;
  2775. if (!master || !master->connector)
  2776. return;
  2777. topology = sde_connector_get_topology_name(master->connector);
  2778. if (topology != SDE_RM_TOPOLOGY_PPSPLIT)
  2779. return;
  2780. /*
  2781. * For pingpong split, the slave pingpong won't generate IRQs. For
  2782. * right-only updates, we can't swap pingpongs, or simply swap the
  2783. * master/slave assignment, we actually have to swap the interfaces
  2784. * so that the master physical encoder will use a pingpong/interface
  2785. * that generates irqs on which to wait.
  2786. */
  2787. is_right_only = !test_bit(0, affected_displays) &&
  2788. test_bit(1, affected_displays);
  2789. if (is_right_only && !sde_enc->intfs_swapped) {
  2790. /* right-only update swap interfaces */
  2791. swap(sde_enc->phys_encs[0]->intf_idx,
  2792. sde_enc->phys_encs[1]->intf_idx);
  2793. sde_enc->intfs_swapped = true;
  2794. } else if (!is_right_only && sde_enc->intfs_swapped) {
  2795. /* left-only or full update, swap back */
  2796. swap(sde_enc->phys_encs[0]->intf_idx,
  2797. sde_enc->phys_encs[1]->intf_idx);
  2798. sde_enc->intfs_swapped = false;
  2799. }
  2800. SDE_DEBUG_ENC(sde_enc,
  2801. "right_only %d swapped %d phys0->intf%d, phys1->intf%d\n",
  2802. is_right_only, sde_enc->intfs_swapped,
  2803. sde_enc->phys_encs[0]->intf_idx - INTF_0,
  2804. sde_enc->phys_encs[1]->intf_idx - INTF_0);
  2805. SDE_EVT32(DRMID(drm_enc), is_right_only, sde_enc->intfs_swapped,
  2806. sde_enc->phys_encs[0]->intf_idx - INTF_0,
  2807. sde_enc->phys_encs[1]->intf_idx - INTF_0,
  2808. *affected_displays);
  2809. /* ppsplit always uses master since ppslave invalid for irqs*/
  2810. if (num_active_phys == 1)
  2811. *affected_displays = BIT(0);
  2812. }
  2813. static void _sde_encoder_update_master(struct drm_encoder *drm_enc,
  2814. struct sde_encoder_kickoff_params *params)
  2815. {
  2816. struct sde_encoder_virt *sde_enc;
  2817. struct sde_encoder_phys *phys;
  2818. int i, num_active_phys;
  2819. bool master_assigned = false;
  2820. if (!drm_enc || !params)
  2821. return;
  2822. sde_enc = to_sde_encoder_virt(drm_enc);
  2823. if (sde_enc->num_phys_encs <= 1)
  2824. return;
  2825. /* count bits set */
  2826. num_active_phys = hweight_long(params->affected_displays);
  2827. SDE_DEBUG_ENC(sde_enc, "affected_displays 0x%lx num_active_phys %d\n",
  2828. params->affected_displays, num_active_phys);
  2829. SDE_EVT32_VERBOSE(DRMID(drm_enc), params->affected_displays,
  2830. num_active_phys);
  2831. /* for left/right only update, ppsplit master switches interface */
  2832. _sde_encoder_ppsplit_swap_intf_for_right_only_update(drm_enc,
  2833. &params->affected_displays, num_active_phys);
  2834. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2835. enum sde_enc_split_role prv_role, new_role;
  2836. bool active = false;
  2837. phys = sde_enc->phys_encs[i];
  2838. if (!phys || !phys->ops.update_split_role || !phys->hw_pp)
  2839. continue;
  2840. active = test_bit(i, &params->affected_displays);
  2841. prv_role = phys->split_role;
  2842. if (active && num_active_phys == 1)
  2843. new_role = ENC_ROLE_SOLO;
  2844. else if (active && !master_assigned)
  2845. new_role = ENC_ROLE_MASTER;
  2846. else if (active)
  2847. new_role = ENC_ROLE_SLAVE;
  2848. else
  2849. new_role = ENC_ROLE_SKIP;
  2850. phys->ops.update_split_role(phys, new_role);
  2851. if (new_role == ENC_ROLE_SOLO || new_role == ENC_ROLE_MASTER) {
  2852. sde_enc->cur_master = phys;
  2853. master_assigned = true;
  2854. }
  2855. SDE_DEBUG_ENC(sde_enc, "pp %d role prv %d new %d active %d\n",
  2856. phys->hw_pp->idx - PINGPONG_0, prv_role,
  2857. phys->split_role, active);
  2858. SDE_EVT32(DRMID(drm_enc), params->affected_displays,
  2859. phys->hw_pp->idx - PINGPONG_0, prv_role,
  2860. phys->split_role, active, num_active_phys);
  2861. }
  2862. }
  2863. bool sde_encoder_check_curr_mode(struct drm_encoder *drm_enc, u32 mode)
  2864. {
  2865. struct sde_encoder_virt *sde_enc;
  2866. struct msm_display_info *disp_info;
  2867. if (!drm_enc) {
  2868. SDE_ERROR("invalid encoder\n");
  2869. return false;
  2870. }
  2871. sde_enc = to_sde_encoder_virt(drm_enc);
  2872. disp_info = &sde_enc->disp_info;
  2873. return (disp_info->curr_panel_mode == mode);
  2874. }
  2875. void sde_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
  2876. {
  2877. struct sde_encoder_virt *sde_enc;
  2878. struct sde_encoder_phys *phys;
  2879. unsigned int i;
  2880. struct sde_hw_ctl *ctl;
  2881. if (!drm_enc) {
  2882. SDE_ERROR("invalid encoder\n");
  2883. return;
  2884. }
  2885. sde_enc = to_sde_encoder_virt(drm_enc);
  2886. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2887. phys = sde_enc->phys_encs[i];
  2888. if (phys && phys->hw_ctl && (phys == sde_enc->cur_master) &&
  2889. sde_encoder_check_curr_mode(drm_enc,
  2890. MSM_DISPLAY_CMD_MODE)) {
  2891. ctl = phys->hw_ctl;
  2892. if (ctl->ops.trigger_pending)
  2893. /* update only for command mode primary ctl */
  2894. ctl->ops.trigger_pending(ctl);
  2895. }
  2896. }
  2897. sde_enc->idle_pc_restore = false;
  2898. }
  2899. static void _sde_encoder_setup_dither(struct sde_encoder_phys *phys)
  2900. {
  2901. void *dither_cfg;
  2902. int ret = 0, i = 0;
  2903. size_t len = 0;
  2904. enum sde_rm_topology_name topology;
  2905. struct drm_encoder *drm_enc;
  2906. struct msm_display_dsc_info *dsc = NULL;
  2907. struct sde_encoder_virt *sde_enc;
  2908. struct sde_hw_pingpong *hw_pp;
  2909. if (!phys || !phys->connector || !phys->hw_pp ||
  2910. !phys->hw_pp->ops.setup_dither || !phys->parent)
  2911. return;
  2912. topology = sde_connector_get_topology_name(phys->connector);
  2913. if ((topology == SDE_RM_TOPOLOGY_PPSPLIT) &&
  2914. (phys->split_role == ENC_ROLE_SLAVE))
  2915. return;
  2916. drm_enc = phys->parent;
  2917. sde_enc = to_sde_encoder_virt(drm_enc);
  2918. dsc = &sde_enc->mode_info.comp_info.dsc_info;
  2919. /* disable dither for 10 bpp or 10bpc dsc config */
  2920. if (dsc->bpp == 10 || dsc->bpc == 10) {
  2921. phys->hw_pp->ops.setup_dither(phys->hw_pp, NULL, 0);
  2922. return;
  2923. }
  2924. ret = sde_connector_get_dither_cfg(phys->connector,
  2925. phys->connector->state, &dither_cfg, &len);
  2926. if (ret)
  2927. return;
  2928. if (TOPOLOGY_DUALPIPE_MERGE_MODE(topology)) {
  2929. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  2930. hw_pp = sde_enc->hw_pp[i];
  2931. if (hw_pp) {
  2932. phys->hw_pp->ops.setup_dither(hw_pp, dither_cfg,
  2933. len);
  2934. }
  2935. }
  2936. } else {
  2937. phys->hw_pp->ops.setup_dither(phys->hw_pp, dither_cfg, len);
  2938. }
  2939. }
  2940. static u32 _sde_encoder_calculate_linetime(struct sde_encoder_virt *sde_enc,
  2941. struct drm_display_mode *mode)
  2942. {
  2943. u64 pclk_rate;
  2944. u32 pclk_period;
  2945. u32 line_time;
  2946. /*
  2947. * For linetime calculation, only operate on master encoder.
  2948. */
  2949. if (!sde_enc->cur_master)
  2950. return 0;
  2951. if (!sde_enc->cur_master->ops.get_line_count) {
  2952. SDE_ERROR("get_line_count function not defined\n");
  2953. return 0;
  2954. }
  2955. pclk_rate = mode->clock; /* pixel clock in kHz */
  2956. if (pclk_rate == 0) {
  2957. SDE_ERROR("pclk is 0, cannot calculate line time\n");
  2958. return 0;
  2959. }
  2960. pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate);
  2961. if (pclk_period == 0) {
  2962. SDE_ERROR("pclk period is 0\n");
  2963. return 0;
  2964. }
  2965. /*
  2966. * Line time calculation based on Pixel clock and HTOTAL.
  2967. * Final unit is in ns.
  2968. */
  2969. line_time = (pclk_period * mode->htotal) / 1000;
  2970. if (line_time == 0) {
  2971. SDE_ERROR("line time calculation is 0\n");
  2972. return 0;
  2973. }
  2974. SDE_DEBUG_ENC(sde_enc,
  2975. "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n",
  2976. pclk_rate, pclk_period, line_time);
  2977. return line_time;
  2978. }
  2979. static int _sde_encoder_wakeup_time(struct drm_encoder *drm_enc,
  2980. ktime_t *wakeup_time)
  2981. {
  2982. struct drm_display_mode *mode;
  2983. struct sde_encoder_virt *sde_enc;
  2984. u32 cur_line;
  2985. u32 line_time;
  2986. u32 vtotal, time_to_vsync;
  2987. ktime_t cur_time;
  2988. sde_enc = to_sde_encoder_virt(drm_enc);
  2989. if (!sde_enc || !sde_enc->cur_master) {
  2990. SDE_ERROR("invalid sde encoder/master\n");
  2991. return -EINVAL;
  2992. }
  2993. mode = &sde_enc->cur_master->cached_mode;
  2994. line_time = _sde_encoder_calculate_linetime(sde_enc, mode);
  2995. if (!line_time)
  2996. return -EINVAL;
  2997. cur_line = sde_enc->cur_master->ops.get_line_count(sde_enc->cur_master);
  2998. vtotal = mode->vtotal;
  2999. if (cur_line >= vtotal)
  3000. time_to_vsync = line_time * vtotal;
  3001. else
  3002. time_to_vsync = line_time * (vtotal - cur_line);
  3003. if (time_to_vsync == 0) {
  3004. SDE_ERROR("time to vsync should not be zero, vtotal=%d\n",
  3005. vtotal);
  3006. return -EINVAL;
  3007. }
  3008. cur_time = ktime_get();
  3009. *wakeup_time = ktime_add_ns(cur_time, time_to_vsync);
  3010. SDE_DEBUG_ENC(sde_enc,
  3011. "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n",
  3012. cur_line, vtotal, time_to_vsync,
  3013. ktime_to_ms(cur_time),
  3014. ktime_to_ms(*wakeup_time));
  3015. return 0;
  3016. }
  3017. static void sde_encoder_vsync_event_handler(struct timer_list *t)
  3018. {
  3019. struct drm_encoder *drm_enc;
  3020. struct sde_encoder_virt *sde_enc =
  3021. from_timer(sde_enc, t, vsync_event_timer);
  3022. struct msm_drm_private *priv;
  3023. struct msm_drm_thread *event_thread;
  3024. if (!sde_enc || !sde_enc->crtc) {
  3025. SDE_ERROR("invalid encoder parameters %d\n", !sde_enc);
  3026. return;
  3027. }
  3028. drm_enc = &sde_enc->base;
  3029. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  3030. SDE_ERROR("invalid encoder parameters\n");
  3031. return;
  3032. }
  3033. priv = drm_enc->dev->dev_private;
  3034. if (sde_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) {
  3035. SDE_ERROR("invalid crtc index:%u\n",
  3036. sde_enc->crtc->index);
  3037. return;
  3038. }
  3039. event_thread = &priv->event_thread[sde_enc->crtc->index];
  3040. if (!event_thread) {
  3041. SDE_ERROR("event_thread not found for crtc:%d\n",
  3042. sde_enc->crtc->index);
  3043. return;
  3044. }
  3045. kthread_queue_work(&event_thread->worker,
  3046. &sde_enc->vsync_event_work);
  3047. }
  3048. static void sde_encoder_esd_trigger_work_handler(struct kthread_work *work)
  3049. {
  3050. struct sde_encoder_virt *sde_enc = container_of(work,
  3051. struct sde_encoder_virt, esd_trigger_work);
  3052. if (!sde_enc) {
  3053. SDE_ERROR("invalid sde encoder\n");
  3054. return;
  3055. }
  3056. sde_encoder_resource_control(&sde_enc->base,
  3057. SDE_ENC_RC_EVENT_KICKOFF);
  3058. }
  3059. static void sde_encoder_input_event_work_handler(struct kthread_work *work)
  3060. {
  3061. struct sde_encoder_virt *sde_enc = container_of(work,
  3062. struct sde_encoder_virt, input_event_work);
  3063. if (!sde_enc) {
  3064. SDE_ERROR("invalid sde encoder\n");
  3065. return;
  3066. }
  3067. sde_encoder_resource_control(&sde_enc->base,
  3068. SDE_ENC_RC_EVENT_EARLY_WAKEUP);
  3069. }
  3070. static void sde_encoder_vsync_event_work_handler(struct kthread_work *work)
  3071. {
  3072. struct sde_encoder_virt *sde_enc = container_of(work,
  3073. struct sde_encoder_virt, vsync_event_work);
  3074. bool autorefresh_enabled = false;
  3075. int rc = 0;
  3076. ktime_t wakeup_time;
  3077. struct drm_encoder *drm_enc;
  3078. if (!sde_enc) {
  3079. SDE_ERROR("invalid sde encoder\n");
  3080. return;
  3081. }
  3082. drm_enc = &sde_enc->base;
  3083. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  3084. if (rc < 0) {
  3085. SDE_ERROR_ENC(sde_enc, "sde enc power enabled failed:%d\n", rc);
  3086. return;
  3087. }
  3088. if (sde_enc->cur_master &&
  3089. sde_enc->cur_master->ops.is_autorefresh_enabled)
  3090. autorefresh_enabled =
  3091. sde_enc->cur_master->ops.is_autorefresh_enabled(
  3092. sde_enc->cur_master);
  3093. /* Update timer if autorefresh is enabled else return */
  3094. if (!autorefresh_enabled)
  3095. goto exit;
  3096. rc = _sde_encoder_wakeup_time(&sde_enc->base, &wakeup_time);
  3097. if (rc)
  3098. goto exit;
  3099. SDE_EVT32_VERBOSE(ktime_to_ms(wakeup_time));
  3100. mod_timer(&sde_enc->vsync_event_timer,
  3101. nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
  3102. exit:
  3103. pm_runtime_put_sync(drm_enc->dev->dev);
  3104. }
  3105. int sde_encoder_poll_line_counts(struct drm_encoder *drm_enc)
  3106. {
  3107. static const uint64_t timeout_us = 50000;
  3108. static const uint64_t sleep_us = 20;
  3109. struct sde_encoder_virt *sde_enc;
  3110. ktime_t cur_ktime, exp_ktime;
  3111. uint32_t line_count, tmp, i;
  3112. if (!drm_enc) {
  3113. SDE_ERROR("invalid encoder\n");
  3114. return -EINVAL;
  3115. }
  3116. sde_enc = to_sde_encoder_virt(drm_enc);
  3117. if (!sde_enc->cur_master ||
  3118. !sde_enc->cur_master->ops.get_line_count) {
  3119. SDE_DEBUG_ENC(sde_enc, "can't get master line count\n");
  3120. SDE_EVT32(DRMID(drm_enc), SDE_EVTLOG_ERROR);
  3121. return -EINVAL;
  3122. }
  3123. exp_ktime = ktime_add_ms(ktime_get(), timeout_us / 1000);
  3124. line_count = sde_enc->cur_master->ops.get_line_count(
  3125. sde_enc->cur_master);
  3126. for (i = 0; i < (timeout_us * 2 / sleep_us); ++i) {
  3127. tmp = line_count;
  3128. line_count = sde_enc->cur_master->ops.get_line_count(
  3129. sde_enc->cur_master);
  3130. if (line_count < tmp) {
  3131. SDE_EVT32(DRMID(drm_enc), line_count);
  3132. return 0;
  3133. }
  3134. cur_ktime = ktime_get();
  3135. if (ktime_compare_safe(exp_ktime, cur_ktime) <= 0)
  3136. break;
  3137. usleep_range(sleep_us / 2, sleep_us);
  3138. }
  3139. SDE_EVT32(DRMID(drm_enc), line_count, SDE_EVTLOG_ERROR);
  3140. return -ETIMEDOUT;
  3141. }
  3142. static int _helper_flush_qsync(struct sde_encoder_phys *phys_enc)
  3143. {
  3144. struct drm_encoder *drm_enc;
  3145. struct sde_rm_hw_iter rm_iter;
  3146. bool lm_valid = false;
  3147. bool intf_valid = false;
  3148. if (!phys_enc || !phys_enc->parent) {
  3149. SDE_ERROR("invalid encoder\n");
  3150. return -EINVAL;
  3151. }
  3152. drm_enc = phys_enc->parent;
  3153. /* Flush the interfaces for AVR update or Qsync with INTF TE */
  3154. if (phys_enc->intf_mode == INTF_MODE_VIDEO ||
  3155. (phys_enc->intf_mode == INTF_MODE_CMD &&
  3156. phys_enc->has_intf_te)) {
  3157. sde_rm_init_hw_iter(&rm_iter, drm_enc->base.id,
  3158. SDE_HW_BLK_INTF);
  3159. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &rm_iter)) {
  3160. struct sde_hw_intf *hw_intf =
  3161. (struct sde_hw_intf *)rm_iter.hw;
  3162. if (!hw_intf)
  3163. continue;
  3164. if (phys_enc->hw_ctl->ops.update_bitmask_intf)
  3165. phys_enc->hw_ctl->ops.update_bitmask_intf(
  3166. phys_enc->hw_ctl,
  3167. hw_intf->idx, 1);
  3168. intf_valid = true;
  3169. }
  3170. if (!intf_valid) {
  3171. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc),
  3172. "intf not found to flush\n");
  3173. return -EFAULT;
  3174. }
  3175. } else {
  3176. sde_rm_init_hw_iter(&rm_iter, drm_enc->base.id, SDE_HW_BLK_LM);
  3177. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &rm_iter)) {
  3178. struct sde_hw_mixer *hw_lm =
  3179. (struct sde_hw_mixer *)rm_iter.hw;
  3180. if (!hw_lm)
  3181. continue;
  3182. /* update LM flush for HW without INTF TE */
  3183. if (phys_enc->hw_ctl->ops.update_bitmask_mixer)
  3184. phys_enc->hw_ctl->ops.update_bitmask_mixer(
  3185. phys_enc->hw_ctl,
  3186. hw_lm->idx, 1);
  3187. lm_valid = true;
  3188. }
  3189. if (!lm_valid) {
  3190. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc),
  3191. "lm not found to flush\n");
  3192. return -EFAULT;
  3193. }
  3194. }
  3195. return 0;
  3196. }
  3197. static void _sde_encoder_helper_hdr_plus_mempool_update(
  3198. struct sde_encoder_virt *sde_enc)
  3199. {
  3200. struct sde_connector_dyn_hdr_metadata *dhdr_meta = NULL;
  3201. struct sde_hw_mdp *mdptop = NULL;
  3202. sde_enc->dynamic_hdr_updated = false;
  3203. if (sde_enc->cur_master) {
  3204. mdptop = sde_enc->cur_master->hw_mdptop;
  3205. dhdr_meta = sde_connector_get_dyn_hdr_meta(
  3206. sde_enc->cur_master->connector);
  3207. }
  3208. if (!mdptop || !dhdr_meta || !dhdr_meta->dynamic_hdr_update)
  3209. return;
  3210. if (mdptop->ops.set_hdr_plus_metadata) {
  3211. sde_enc->dynamic_hdr_updated = true;
  3212. mdptop->ops.set_hdr_plus_metadata(
  3213. mdptop, dhdr_meta->dynamic_hdr_payload,
  3214. dhdr_meta->dynamic_hdr_payload_size,
  3215. sde_enc->cur_master->intf_idx == INTF_0 ?
  3216. 0 : 1);
  3217. }
  3218. }
  3219. void sde_encoder_helper_needs_hw_reset(struct drm_encoder *drm_enc)
  3220. {
  3221. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  3222. struct sde_encoder_phys *phys;
  3223. int i;
  3224. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3225. phys = sde_enc->phys_encs[i];
  3226. if (phys && phys->ops.hw_reset)
  3227. phys->ops.hw_reset(phys);
  3228. }
  3229. }
  3230. int sde_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
  3231. struct sde_encoder_kickoff_params *params)
  3232. {
  3233. struct sde_encoder_virt *sde_enc;
  3234. struct sde_encoder_phys *phys;
  3235. struct sde_kms *sde_kms = NULL;
  3236. struct sde_crtc *sde_crtc;
  3237. struct msm_drm_private *priv = NULL;
  3238. bool needs_hw_reset = false, is_cmd_mode;
  3239. int i, rc, ret = 0;
  3240. struct msm_display_info *disp_info;
  3241. if (!drm_enc || !params || !drm_enc->dev ||
  3242. !drm_enc->dev->dev_private) {
  3243. SDE_ERROR("invalid args\n");
  3244. return -EINVAL;
  3245. }
  3246. sde_enc = to_sde_encoder_virt(drm_enc);
  3247. priv = drm_enc->dev->dev_private;
  3248. sde_kms = to_sde_kms(priv->kms);
  3249. disp_info = &sde_enc->disp_info;
  3250. sde_crtc = to_sde_crtc(sde_enc->crtc);
  3251. SDE_DEBUG_ENC(sde_enc, "\n");
  3252. SDE_EVT32(DRMID(drm_enc));
  3253. is_cmd_mode = sde_encoder_check_curr_mode(drm_enc,
  3254. MSM_DISPLAY_CMD_MODE);
  3255. if (sde_enc->cur_master && sde_enc->cur_master->connector
  3256. && is_cmd_mode)
  3257. sde_enc->frame_trigger_mode = sde_connector_get_property(
  3258. sde_enc->cur_master->connector->state,
  3259. CONNECTOR_PROP_CMD_FRAME_TRIGGER_MODE);
  3260. _sde_encoder_helper_hdr_plus_mempool_update(sde_enc);
  3261. /* prepare for next kickoff, may include waiting on previous kickoff */
  3262. SDE_ATRACE_BEGIN("sde_encoder_prepare_for_kickoff");
  3263. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3264. phys = sde_enc->phys_encs[i];
  3265. params->frame_trigger_mode = sde_enc->frame_trigger_mode;
  3266. params->recovery_events_enabled =
  3267. sde_enc->recovery_events_enabled;
  3268. if (phys) {
  3269. if (phys->ops.prepare_for_kickoff) {
  3270. rc = phys->ops.prepare_for_kickoff(
  3271. phys, params);
  3272. if (rc)
  3273. ret = rc;
  3274. }
  3275. if (phys->enable_state == SDE_ENC_ERR_NEEDS_HW_RESET)
  3276. needs_hw_reset = true;
  3277. _sde_encoder_setup_dither(phys);
  3278. if (sde_enc->cur_master &&
  3279. sde_connector_is_qsync_updated(
  3280. sde_enc->cur_master->connector)) {
  3281. _helper_flush_qsync(phys);
  3282. }
  3283. }
  3284. }
  3285. rc = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
  3286. if (rc) {
  3287. SDE_ERROR_ENC(sde_enc, "resource kickoff failed rc %d\n", rc);
  3288. ret = rc;
  3289. goto end;
  3290. }
  3291. /* if any phys needs reset, reset all phys, in-order */
  3292. if (needs_hw_reset)
  3293. sde_encoder_helper_needs_hw_reset(drm_enc);
  3294. _sde_encoder_update_master(drm_enc, params);
  3295. _sde_encoder_update_roi(drm_enc);
  3296. if (sde_enc->cur_master && sde_enc->cur_master->connector) {
  3297. rc = sde_connector_pre_kickoff(sde_enc->cur_master->connector);
  3298. if (rc) {
  3299. SDE_ERROR_ENC(sde_enc, "kickoff conn%d failed rc %d\n",
  3300. sde_enc->cur_master->connector->base.id,
  3301. rc);
  3302. ret = rc;
  3303. }
  3304. }
  3305. if (sde_enc->cur_master &&
  3306. ((is_cmd_mode && sde_enc->cur_master->cont_splash_enabled) ||
  3307. !sde_enc->cur_master->cont_splash_enabled)) {
  3308. rc = sde_encoder_dce_setup(sde_enc, params);
  3309. if (rc) {
  3310. SDE_ERROR_ENC(sde_enc, "failed to setup DSC: %d\n", rc);
  3311. ret = rc;
  3312. }
  3313. }
  3314. sde_encoder_dce_flush(sde_enc);
  3315. if (sde_enc->cur_master && !sde_enc->cur_master->cont_splash_enabled)
  3316. sde_configure_qdss(sde_enc, sde_enc->cur_master->hw_qdss,
  3317. sde_enc->cur_master, sde_kms->qdss_enabled);
  3318. end:
  3319. SDE_ATRACE_END("sde_encoder_prepare_for_kickoff");
  3320. return ret;
  3321. }
  3322. /**
  3323. * _sde_encoder_reset_ctl_hw - reset h/w configuration for all ctl's associated
  3324. * with the specified encoder, and unstage all pipes from it
  3325. * @encoder: encoder pointer
  3326. * Returns: 0 on success
  3327. */
  3328. static int _sde_encoder_reset_ctl_hw(struct drm_encoder *drm_enc)
  3329. {
  3330. struct sde_encoder_virt *sde_enc;
  3331. struct sde_encoder_phys *phys;
  3332. unsigned int i;
  3333. int rc = 0;
  3334. if (!drm_enc) {
  3335. SDE_ERROR("invalid encoder\n");
  3336. return -EINVAL;
  3337. }
  3338. sde_enc = to_sde_encoder_virt(drm_enc);
  3339. SDE_ATRACE_BEGIN("encoder_release_lm");
  3340. SDE_DEBUG_ENC(sde_enc, "\n");
  3341. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3342. phys = sde_enc->phys_encs[i];
  3343. if (!phys)
  3344. continue;
  3345. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0);
  3346. rc = sde_encoder_helper_reset_mixers(phys, NULL);
  3347. if (rc)
  3348. SDE_EVT32(DRMID(drm_enc), rc, SDE_EVTLOG_ERROR);
  3349. }
  3350. SDE_ATRACE_END("encoder_release_lm");
  3351. return rc;
  3352. }
  3353. void sde_encoder_kickoff(struct drm_encoder *drm_enc, bool is_error)
  3354. {
  3355. struct sde_encoder_virt *sde_enc;
  3356. struct sde_encoder_phys *phys;
  3357. ktime_t wakeup_time;
  3358. unsigned int i;
  3359. if (!drm_enc) {
  3360. SDE_ERROR("invalid encoder\n");
  3361. return;
  3362. }
  3363. SDE_ATRACE_BEGIN("encoder_kickoff");
  3364. sde_enc = to_sde_encoder_virt(drm_enc);
  3365. SDE_DEBUG_ENC(sde_enc, "\n");
  3366. /* create a 'no pipes' commit to release buffers on errors */
  3367. if (is_error)
  3368. _sde_encoder_reset_ctl_hw(drm_enc);
  3369. /* All phys encs are ready to go, trigger the kickoff */
  3370. _sde_encoder_kickoff_phys(sde_enc);
  3371. /* allow phys encs to handle any post-kickoff business */
  3372. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3373. phys = sde_enc->phys_encs[i];
  3374. if (phys && phys->ops.handle_post_kickoff)
  3375. phys->ops.handle_post_kickoff(phys);
  3376. }
  3377. if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI &&
  3378. !_sde_encoder_wakeup_time(drm_enc, &wakeup_time)) {
  3379. SDE_EVT32_VERBOSE(ktime_to_ms(wakeup_time));
  3380. mod_timer(&sde_enc->vsync_event_timer,
  3381. nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
  3382. }
  3383. SDE_ATRACE_END("encoder_kickoff");
  3384. }
  3385. void sde_encoder_helper_get_pp_line_count(struct drm_encoder *drm_enc,
  3386. struct sde_hw_pp_vsync_info *info)
  3387. {
  3388. struct sde_encoder_virt *sde_enc;
  3389. struct sde_encoder_phys *phys;
  3390. int i, ret;
  3391. if (!drm_enc || !info)
  3392. return;
  3393. sde_enc = to_sde_encoder_virt(drm_enc);
  3394. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3395. phys = sde_enc->phys_encs[i];
  3396. if (phys && phys->hw_intf && phys->hw_pp
  3397. && phys->hw_intf->ops.get_vsync_info) {
  3398. ret = phys->hw_intf->ops.get_vsync_info(
  3399. phys->hw_intf, &info[i]);
  3400. if (!ret) {
  3401. info[i].pp_idx = phys->hw_pp->idx - PINGPONG_0;
  3402. info[i].intf_idx = phys->hw_intf->idx - INTF_0;
  3403. }
  3404. }
  3405. }
  3406. }
  3407. int sde_encoder_helper_reset_mixers(struct sde_encoder_phys *phys_enc,
  3408. struct drm_framebuffer *fb)
  3409. {
  3410. struct drm_encoder *drm_enc;
  3411. struct sde_hw_mixer_cfg mixer;
  3412. struct sde_rm_hw_iter lm_iter;
  3413. bool lm_valid = false;
  3414. if (!phys_enc || !phys_enc->parent) {
  3415. SDE_ERROR("invalid encoder\n");
  3416. return -EINVAL;
  3417. }
  3418. drm_enc = phys_enc->parent;
  3419. memset(&mixer, 0, sizeof(mixer));
  3420. /* reset associated CTL/LMs */
  3421. if (phys_enc->hw_ctl->ops.clear_all_blendstages)
  3422. phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl);
  3423. sde_rm_init_hw_iter(&lm_iter, drm_enc->base.id, SDE_HW_BLK_LM);
  3424. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &lm_iter)) {
  3425. struct sde_hw_mixer *hw_lm = (struct sde_hw_mixer *)lm_iter.hw;
  3426. if (!hw_lm)
  3427. continue;
  3428. /* need to flush LM to remove it */
  3429. if (phys_enc->hw_ctl->ops.update_bitmask_mixer)
  3430. phys_enc->hw_ctl->ops.update_bitmask_mixer(
  3431. phys_enc->hw_ctl,
  3432. hw_lm->idx, 1);
  3433. if (fb) {
  3434. /* assume a single LM if targeting a frame buffer */
  3435. if (lm_valid)
  3436. continue;
  3437. mixer.out_height = fb->height;
  3438. mixer.out_width = fb->width;
  3439. if (hw_lm->ops.setup_mixer_out)
  3440. hw_lm->ops.setup_mixer_out(hw_lm, &mixer);
  3441. }
  3442. lm_valid = true;
  3443. /* only enable border color on LM */
  3444. if (phys_enc->hw_ctl->ops.setup_blendstage)
  3445. phys_enc->hw_ctl->ops.setup_blendstage(
  3446. phys_enc->hw_ctl, hw_lm->idx, NULL);
  3447. }
  3448. if (!lm_valid) {
  3449. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc), "lm not found\n");
  3450. return -EFAULT;
  3451. }
  3452. return 0;
  3453. }
  3454. void sde_encoder_prepare_commit(struct drm_encoder *drm_enc)
  3455. {
  3456. struct sde_encoder_virt *sde_enc;
  3457. struct sde_encoder_phys *phys;
  3458. int i, rc = 0;
  3459. struct sde_hw_ctl *ctl;
  3460. if (!drm_enc) {
  3461. SDE_ERROR("invalid encoder\n");
  3462. return;
  3463. }
  3464. sde_enc = to_sde_encoder_virt(drm_enc);
  3465. /* update the qsync parameters for the current frame */
  3466. if (sde_enc->cur_master)
  3467. sde_connector_set_qsync_params(
  3468. sde_enc->cur_master->connector);
  3469. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3470. phys = sde_enc->phys_encs[i];
  3471. if (phys && phys->ops.prepare_commit)
  3472. phys->ops.prepare_commit(phys);
  3473. if (phys && phys->hw_ctl) {
  3474. ctl = phys->hw_ctl;
  3475. /*
  3476. * avoid clearing the pending flush during the first
  3477. * frame update after idle power collpase as the
  3478. * restore path would have updated the pending flush
  3479. */
  3480. if (!sde_enc->idle_pc_restore &&
  3481. ctl->ops.clear_pending_flush)
  3482. ctl->ops.clear_pending_flush(ctl);
  3483. }
  3484. }
  3485. if (sde_enc->cur_master && sde_enc->cur_master->connector) {
  3486. rc = sde_connector_prepare_commit(
  3487. sde_enc->cur_master->connector);
  3488. if (rc)
  3489. SDE_ERROR_ENC(sde_enc,
  3490. "prepare commit failed conn %d rc %d\n",
  3491. sde_enc->cur_master->connector->base.id,
  3492. rc);
  3493. }
  3494. }
  3495. void sde_encoder_helper_setup_misr(struct sde_encoder_phys *phys_enc,
  3496. bool enable, u32 frame_count)
  3497. {
  3498. if (!phys_enc)
  3499. return;
  3500. if (phys_enc->hw_intf && phys_enc->hw_intf->ops.setup_misr)
  3501. phys_enc->hw_intf->ops.setup_misr(phys_enc->hw_intf,
  3502. enable, frame_count);
  3503. }
  3504. int sde_encoder_helper_collect_misr(struct sde_encoder_phys *phys_enc,
  3505. bool nonblock, u32 *misr_value)
  3506. {
  3507. if (!phys_enc)
  3508. return -EINVAL;
  3509. return phys_enc->hw_intf && phys_enc->hw_intf->ops.collect_misr ?
  3510. phys_enc->hw_intf->ops.collect_misr(phys_enc->hw_intf,
  3511. nonblock, misr_value) : -ENOTSUPP;
  3512. }
  3513. #ifdef CONFIG_DEBUG_FS
  3514. static int _sde_encoder_status_show(struct seq_file *s, void *data)
  3515. {
  3516. struct sde_encoder_virt *sde_enc;
  3517. int i;
  3518. if (!s || !s->private)
  3519. return -EINVAL;
  3520. sde_enc = s->private;
  3521. mutex_lock(&sde_enc->enc_lock);
  3522. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3523. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3524. if (!phys)
  3525. continue;
  3526. seq_printf(s, "intf:%d vsync:%8d underrun:%8d ",
  3527. phys->intf_idx - INTF_0,
  3528. atomic_read(&phys->vsync_cnt),
  3529. atomic_read(&phys->underrun_cnt));
  3530. switch (phys->intf_mode) {
  3531. case INTF_MODE_VIDEO:
  3532. seq_puts(s, "mode: video\n");
  3533. break;
  3534. case INTF_MODE_CMD:
  3535. seq_puts(s, "mode: command\n");
  3536. break;
  3537. case INTF_MODE_WB_BLOCK:
  3538. seq_puts(s, "mode: wb block\n");
  3539. break;
  3540. case INTF_MODE_WB_LINE:
  3541. seq_puts(s, "mode: wb line\n");
  3542. break;
  3543. default:
  3544. seq_puts(s, "mode: ???\n");
  3545. break;
  3546. }
  3547. }
  3548. mutex_unlock(&sde_enc->enc_lock);
  3549. return 0;
  3550. }
  3551. static int _sde_encoder_debugfs_status_open(struct inode *inode,
  3552. struct file *file)
  3553. {
  3554. return single_open(file, _sde_encoder_status_show, inode->i_private);
  3555. }
  3556. static ssize_t _sde_encoder_misr_setup(struct file *file,
  3557. const char __user *user_buf, size_t count, loff_t *ppos)
  3558. {
  3559. struct sde_encoder_virt *sde_enc;
  3560. int rc;
  3561. char buf[MISR_BUFF_SIZE + 1];
  3562. size_t buff_copy;
  3563. u32 frame_count, enable;
  3564. struct msm_drm_private *priv = NULL;
  3565. struct sde_kms *sde_kms = NULL;
  3566. struct drm_encoder *drm_enc;
  3567. if (!file || !file->private_data)
  3568. return -EINVAL;
  3569. sde_enc = file->private_data;
  3570. priv = sde_enc->base.dev->dev_private;
  3571. if (!sde_enc || !priv || !priv->kms)
  3572. return -EINVAL;
  3573. sde_kms = to_sde_kms(priv->kms);
  3574. drm_enc = &sde_enc->base;
  3575. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  3576. SDE_DEBUG_ENC(sde_enc, "misr enable/disable not allowed\n");
  3577. return -ENOTSUPP;
  3578. }
  3579. buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
  3580. if (copy_from_user(buf, user_buf, buff_copy))
  3581. return -EINVAL;
  3582. buf[buff_copy] = 0; /* end of string */
  3583. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
  3584. return -EINVAL;
  3585. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  3586. if (rc < 0)
  3587. return rc;
  3588. sde_enc->misr_enable = enable;
  3589. sde_enc->misr_frame_count = frame_count;
  3590. sde_encoder_misr_configure(&sde_enc->base, enable, frame_count);
  3591. pm_runtime_put_sync(drm_enc->dev->dev);
  3592. return count;
  3593. }
  3594. static ssize_t _sde_encoder_misr_read(struct file *file,
  3595. char __user *user_buff, size_t count, loff_t *ppos)
  3596. {
  3597. struct sde_encoder_virt *sde_enc;
  3598. struct msm_drm_private *priv = NULL;
  3599. struct sde_kms *sde_kms = NULL;
  3600. struct drm_encoder *drm_enc;
  3601. int i = 0, len = 0;
  3602. char buf[MISR_BUFF_SIZE + 1] = {'\0'};
  3603. int rc;
  3604. if (*ppos)
  3605. return 0;
  3606. if (!file || !file->private_data)
  3607. return -EINVAL;
  3608. sde_enc = file->private_data;
  3609. priv = sde_enc->base.dev->dev_private;
  3610. if (priv != NULL)
  3611. sde_kms = to_sde_kms(priv->kms);
  3612. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  3613. SDE_DEBUG_ENC(sde_enc, "misr read not allowed\n");
  3614. return -ENOTSUPP;
  3615. }
  3616. drm_enc = &sde_enc->base;
  3617. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  3618. if (rc < 0)
  3619. return rc;
  3620. if (!sde_enc->misr_enable) {
  3621. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3622. "disabled\n");
  3623. goto buff_check;
  3624. }
  3625. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3626. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3627. u32 misr_value = 0;
  3628. if (!phys || !phys->ops.collect_misr) {
  3629. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3630. "invalid\n");
  3631. SDE_ERROR_ENC(sde_enc, "invalid misr ops\n");
  3632. continue;
  3633. }
  3634. rc = phys->ops.collect_misr(phys, false, &misr_value);
  3635. if (rc) {
  3636. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3637. "invalid\n");
  3638. SDE_ERROR_ENC(sde_enc, "failed to collect misr %d\n",
  3639. rc);
  3640. continue;
  3641. } else {
  3642. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3643. "Intf idx:%d\n",
  3644. phys->intf_idx - INTF_0);
  3645. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3646. "0x%x\n", misr_value);
  3647. }
  3648. }
  3649. buff_check:
  3650. if (count <= len) {
  3651. len = 0;
  3652. goto end;
  3653. }
  3654. if (copy_to_user(user_buff, buf, len)) {
  3655. len = -EFAULT;
  3656. goto end;
  3657. }
  3658. *ppos += len; /* increase offset */
  3659. end:
  3660. pm_runtime_put_sync(drm_enc->dev->dev);
  3661. return len;
  3662. }
  3663. static int _sde_encoder_init_debugfs(struct drm_encoder *drm_enc)
  3664. {
  3665. struct sde_encoder_virt *sde_enc;
  3666. struct msm_drm_private *priv;
  3667. struct sde_kms *sde_kms;
  3668. int i;
  3669. static const struct file_operations debugfs_status_fops = {
  3670. .open = _sde_encoder_debugfs_status_open,
  3671. .read = seq_read,
  3672. .llseek = seq_lseek,
  3673. .release = single_release,
  3674. };
  3675. static const struct file_operations debugfs_misr_fops = {
  3676. .open = simple_open,
  3677. .read = _sde_encoder_misr_read,
  3678. .write = _sde_encoder_misr_setup,
  3679. };
  3680. char name[SDE_NAME_SIZE];
  3681. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  3682. SDE_ERROR("invalid encoder or kms\n");
  3683. return -EINVAL;
  3684. }
  3685. sde_enc = to_sde_encoder_virt(drm_enc);
  3686. priv = drm_enc->dev->dev_private;
  3687. sde_kms = to_sde_kms(priv->kms);
  3688. snprintf(name, SDE_NAME_SIZE, "encoder%u", drm_enc->base.id);
  3689. /* create overall sub-directory for the encoder */
  3690. sde_enc->debugfs_root = debugfs_create_dir(name,
  3691. drm_enc->dev->primary->debugfs_root);
  3692. if (!sde_enc->debugfs_root)
  3693. return -ENOMEM;
  3694. /* don't error check these */
  3695. debugfs_create_file("status", 0400,
  3696. sde_enc->debugfs_root, sde_enc, &debugfs_status_fops);
  3697. debugfs_create_file("misr_data", 0600,
  3698. sde_enc->debugfs_root, sde_enc, &debugfs_misr_fops);
  3699. debugfs_create_bool("idle_power_collapse", 0600, sde_enc->debugfs_root,
  3700. &sde_enc->idle_pc_enabled);
  3701. debugfs_create_u32("frame_trigger_mode", 0400, sde_enc->debugfs_root,
  3702. &sde_enc->frame_trigger_mode);
  3703. for (i = 0; i < sde_enc->num_phys_encs; i++)
  3704. if (sde_enc->phys_encs[i] &&
  3705. sde_enc->phys_encs[i]->ops.late_register)
  3706. sde_enc->phys_encs[i]->ops.late_register(
  3707. sde_enc->phys_encs[i],
  3708. sde_enc->debugfs_root);
  3709. return 0;
  3710. }
  3711. static void _sde_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
  3712. {
  3713. struct sde_encoder_virt *sde_enc;
  3714. if (!drm_enc)
  3715. return;
  3716. sde_enc = to_sde_encoder_virt(drm_enc);
  3717. debugfs_remove_recursive(sde_enc->debugfs_root);
  3718. }
  3719. #else
  3720. static int _sde_encoder_init_debugfs(struct drm_encoder *drm_enc)
  3721. {
  3722. return 0;
  3723. }
  3724. static void _sde_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
  3725. {
  3726. }
  3727. #endif
  3728. static int sde_encoder_late_register(struct drm_encoder *encoder)
  3729. {
  3730. return _sde_encoder_init_debugfs(encoder);
  3731. }
  3732. static void sde_encoder_early_unregister(struct drm_encoder *encoder)
  3733. {
  3734. _sde_encoder_destroy_debugfs(encoder);
  3735. }
  3736. static int sde_encoder_virt_add_phys_encs(
  3737. struct msm_display_info *disp_info,
  3738. struct sde_encoder_virt *sde_enc,
  3739. struct sde_enc_phys_init_params *params)
  3740. {
  3741. struct sde_encoder_phys *enc = NULL;
  3742. u32 display_caps = disp_info->capabilities;
  3743. SDE_DEBUG_ENC(sde_enc, "\n");
  3744. /*
  3745. * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
  3746. * in this function, check up-front.
  3747. */
  3748. if (sde_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
  3749. ARRAY_SIZE(sde_enc->phys_encs)) {
  3750. SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
  3751. sde_enc->num_phys_encs);
  3752. return -EINVAL;
  3753. }
  3754. if (display_caps & MSM_DISPLAY_CAP_VID_MODE) {
  3755. enc = sde_encoder_phys_vid_init(params);
  3756. if (IS_ERR_OR_NULL(enc)) {
  3757. SDE_ERROR_ENC(sde_enc, "failed to init vid enc: %ld\n",
  3758. PTR_ERR(enc));
  3759. return !enc ? -EINVAL : PTR_ERR(enc);
  3760. }
  3761. sde_enc->phys_vid_encs[sde_enc->num_phys_encs] = enc;
  3762. }
  3763. if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) {
  3764. enc = sde_encoder_phys_cmd_init(params);
  3765. if (IS_ERR_OR_NULL(enc)) {
  3766. SDE_ERROR_ENC(sde_enc, "failed to init cmd enc: %ld\n",
  3767. PTR_ERR(enc));
  3768. return !enc ? -EINVAL : PTR_ERR(enc);
  3769. }
  3770. sde_enc->phys_cmd_encs[sde_enc->num_phys_encs] = enc;
  3771. }
  3772. if (disp_info->curr_panel_mode == MSM_DISPLAY_VIDEO_MODE)
  3773. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3774. sde_enc->phys_vid_encs[sde_enc->num_phys_encs];
  3775. else
  3776. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3777. sde_enc->phys_cmd_encs[sde_enc->num_phys_encs];
  3778. ++sde_enc->num_phys_encs;
  3779. return 0;
  3780. }
  3781. static int sde_encoder_virt_add_phys_enc_wb(struct sde_encoder_virt *sde_enc,
  3782. struct sde_enc_phys_init_params *params)
  3783. {
  3784. struct sde_encoder_phys *enc = NULL;
  3785. if (!sde_enc) {
  3786. SDE_ERROR("invalid encoder\n");
  3787. return -EINVAL;
  3788. }
  3789. SDE_DEBUG_ENC(sde_enc, "\n");
  3790. if (sde_enc->num_phys_encs + 1 >= ARRAY_SIZE(sde_enc->phys_encs)) {
  3791. SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
  3792. sde_enc->num_phys_encs);
  3793. return -EINVAL;
  3794. }
  3795. enc = sde_encoder_phys_wb_init(params);
  3796. if (IS_ERR_OR_NULL(enc)) {
  3797. SDE_ERROR_ENC(sde_enc, "failed to init wb enc: %ld\n",
  3798. PTR_ERR(enc));
  3799. return !enc ? -EINVAL : PTR_ERR(enc);
  3800. }
  3801. sde_enc->phys_encs[sde_enc->num_phys_encs] = enc;
  3802. ++sde_enc->num_phys_encs;
  3803. return 0;
  3804. }
  3805. static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc,
  3806. struct sde_kms *sde_kms,
  3807. struct msm_display_info *disp_info,
  3808. int *drm_enc_mode)
  3809. {
  3810. int ret = 0;
  3811. int i = 0;
  3812. enum sde_intf_type intf_type;
  3813. struct sde_encoder_virt_ops parent_ops = {
  3814. sde_encoder_vblank_callback,
  3815. sde_encoder_underrun_callback,
  3816. sde_encoder_frame_done_callback,
  3817. sde_encoder_get_qsync_fps_callback,
  3818. };
  3819. struct sde_enc_phys_init_params phys_params;
  3820. if (!sde_enc || !sde_kms) {
  3821. SDE_ERROR("invalid arg(s), enc %d kms %d\n",
  3822. !sde_enc, !sde_kms);
  3823. return -EINVAL;
  3824. }
  3825. memset(&phys_params, 0, sizeof(phys_params));
  3826. phys_params.sde_kms = sde_kms;
  3827. phys_params.parent = &sde_enc->base;
  3828. phys_params.parent_ops = parent_ops;
  3829. phys_params.enc_spinlock = &sde_enc->enc_spinlock;
  3830. phys_params.vblank_ctl_lock = &sde_enc->vblank_ctl_lock;
  3831. SDE_DEBUG("\n");
  3832. if (disp_info->intf_type == DRM_MODE_CONNECTOR_DSI) {
  3833. *drm_enc_mode = DRM_MODE_ENCODER_DSI;
  3834. intf_type = INTF_DSI;
  3835. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_HDMIA) {
  3836. *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
  3837. intf_type = INTF_HDMI;
  3838. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_DisplayPort) {
  3839. if (disp_info->capabilities & MSM_DISPLAY_CAP_MST_MODE)
  3840. *drm_enc_mode = DRM_MODE_ENCODER_DPMST;
  3841. else
  3842. *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
  3843. intf_type = INTF_DP;
  3844. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_VIRTUAL) {
  3845. *drm_enc_mode = DRM_MODE_ENCODER_VIRTUAL;
  3846. intf_type = INTF_WB;
  3847. } else {
  3848. SDE_ERROR_ENC(sde_enc, "unsupported display interface type\n");
  3849. return -EINVAL;
  3850. }
  3851. WARN_ON(disp_info->num_of_h_tiles < 1);
  3852. sde_enc->display_num_of_h_tiles = disp_info->num_of_h_tiles;
  3853. sde_enc->te_source = disp_info->te_source;
  3854. SDE_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
  3855. if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
  3856. (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
  3857. sde_enc->idle_pc_enabled = sde_kms->catalog->has_idle_pc;
  3858. mutex_lock(&sde_enc->enc_lock);
  3859. for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
  3860. /*
  3861. * Left-most tile is at index 0, content is controller id
  3862. * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
  3863. * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
  3864. */
  3865. u32 controller_id = disp_info->h_tile_instance[i];
  3866. if (disp_info->num_of_h_tiles > 1) {
  3867. if (i == 0)
  3868. phys_params.split_role = ENC_ROLE_MASTER;
  3869. else
  3870. phys_params.split_role = ENC_ROLE_SLAVE;
  3871. } else {
  3872. phys_params.split_role = ENC_ROLE_SOLO;
  3873. }
  3874. SDE_DEBUG("h_tile_instance %d = %d, split_role %d\n",
  3875. i, controller_id, phys_params.split_role);
  3876. if (sde_enc->ops.phys_init) {
  3877. struct sde_encoder_phys *enc;
  3878. enc = sde_enc->ops.phys_init(intf_type,
  3879. controller_id,
  3880. &phys_params);
  3881. if (enc) {
  3882. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3883. enc;
  3884. ++sde_enc->num_phys_encs;
  3885. } else
  3886. SDE_ERROR_ENC(sde_enc,
  3887. "failed to add phys encs\n");
  3888. continue;
  3889. }
  3890. if (intf_type == INTF_WB) {
  3891. phys_params.intf_idx = INTF_MAX;
  3892. phys_params.wb_idx = sde_encoder_get_wb(
  3893. sde_kms->catalog,
  3894. intf_type, controller_id);
  3895. if (phys_params.wb_idx == WB_MAX) {
  3896. SDE_ERROR_ENC(sde_enc,
  3897. "could not get wb: type %d, id %d\n",
  3898. intf_type, controller_id);
  3899. ret = -EINVAL;
  3900. }
  3901. } else {
  3902. phys_params.wb_idx = WB_MAX;
  3903. phys_params.intf_idx = sde_encoder_get_intf(
  3904. sde_kms->catalog, intf_type,
  3905. controller_id);
  3906. if (phys_params.intf_idx == INTF_MAX) {
  3907. SDE_ERROR_ENC(sde_enc,
  3908. "could not get wb: type %d, id %d\n",
  3909. intf_type, controller_id);
  3910. ret = -EINVAL;
  3911. }
  3912. }
  3913. if (!ret) {
  3914. if (intf_type == INTF_WB)
  3915. ret = sde_encoder_virt_add_phys_enc_wb(sde_enc,
  3916. &phys_params);
  3917. else
  3918. ret = sde_encoder_virt_add_phys_encs(
  3919. disp_info,
  3920. sde_enc,
  3921. &phys_params);
  3922. if (ret)
  3923. SDE_ERROR_ENC(sde_enc,
  3924. "failed to add phys encs\n");
  3925. }
  3926. }
  3927. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3928. struct sde_encoder_phys *vid_phys = sde_enc->phys_vid_encs[i];
  3929. struct sde_encoder_phys *cmd_phys = sde_enc->phys_cmd_encs[i];
  3930. if (vid_phys) {
  3931. atomic_set(&vid_phys->vsync_cnt, 0);
  3932. atomic_set(&vid_phys->underrun_cnt, 0);
  3933. }
  3934. if (cmd_phys) {
  3935. atomic_set(&cmd_phys->vsync_cnt, 0);
  3936. atomic_set(&cmd_phys->underrun_cnt, 0);
  3937. }
  3938. }
  3939. mutex_unlock(&sde_enc->enc_lock);
  3940. return ret;
  3941. }
  3942. static const struct drm_encoder_helper_funcs sde_encoder_helper_funcs = {
  3943. .mode_set = sde_encoder_virt_mode_set,
  3944. .disable = sde_encoder_virt_disable,
  3945. .enable = sde_encoder_virt_enable,
  3946. .atomic_check = sde_encoder_virt_atomic_check,
  3947. };
  3948. static const struct drm_encoder_funcs sde_encoder_funcs = {
  3949. .destroy = sde_encoder_destroy,
  3950. .late_register = sde_encoder_late_register,
  3951. .early_unregister = sde_encoder_early_unregister,
  3952. };
  3953. struct drm_encoder *sde_encoder_init_with_ops(
  3954. struct drm_device *dev,
  3955. struct msm_display_info *disp_info,
  3956. const struct sde_encoder_ops *ops)
  3957. {
  3958. struct msm_drm_private *priv = dev->dev_private;
  3959. struct sde_kms *sde_kms = to_sde_kms(priv->kms);
  3960. struct drm_encoder *drm_enc = NULL;
  3961. struct sde_encoder_virt *sde_enc = NULL;
  3962. int drm_enc_mode = DRM_MODE_ENCODER_NONE;
  3963. char name[SDE_NAME_SIZE];
  3964. int ret = 0, i, intf_index = INTF_MAX;
  3965. struct sde_encoder_phys *phys = NULL;
  3966. sde_enc = kzalloc(sizeof(*sde_enc), GFP_KERNEL);
  3967. if (!sde_enc) {
  3968. ret = -ENOMEM;
  3969. goto fail;
  3970. }
  3971. if (ops)
  3972. sde_enc->ops = *ops;
  3973. mutex_init(&sde_enc->enc_lock);
  3974. ret = sde_encoder_setup_display(sde_enc, sde_kms, disp_info,
  3975. &drm_enc_mode);
  3976. if (ret)
  3977. goto fail;
  3978. sde_enc->cur_master = NULL;
  3979. spin_lock_init(&sde_enc->enc_spinlock);
  3980. mutex_init(&sde_enc->vblank_ctl_lock);
  3981. for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
  3982. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  3983. drm_enc = &sde_enc->base;
  3984. drm_encoder_init(dev, drm_enc, &sde_encoder_funcs, drm_enc_mode, NULL);
  3985. drm_encoder_helper_add(drm_enc, &sde_encoder_helper_funcs);
  3986. if (disp_info->intf_type == DRM_MODE_CONNECTOR_DSI)
  3987. timer_setup(&sde_enc->vsync_event_timer,
  3988. sde_encoder_vsync_event_handler, 0);
  3989. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3990. phys = sde_enc->phys_encs[i];
  3991. if (!phys)
  3992. continue;
  3993. if (phys->ops.is_master && phys->ops.is_master(phys))
  3994. intf_index = phys->intf_idx - INTF_0;
  3995. }
  3996. snprintf(name, SDE_NAME_SIZE, "rsc_enc%u", drm_enc->base.id);
  3997. sde_enc->rsc_client = sde_rsc_client_create(SDE_RSC_INDEX, name,
  3998. (disp_info->display_type == SDE_CONNECTOR_PRIMARY) ?
  3999. SDE_RSC_PRIMARY_DISP_CLIENT :
  4000. SDE_RSC_EXTERNAL_DISP_CLIENT, intf_index + 1);
  4001. if (IS_ERR_OR_NULL(sde_enc->rsc_client)) {
  4002. SDE_DEBUG("sde rsc client create failed :%ld\n",
  4003. PTR_ERR(sde_enc->rsc_client));
  4004. sde_enc->rsc_client = NULL;
  4005. }
  4006. if (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
  4007. ret = _sde_encoder_input_handler(sde_enc);
  4008. if (ret)
  4009. SDE_ERROR(
  4010. "input handler registration failed, rc = %d\n", ret);
  4011. }
  4012. mutex_init(&sde_enc->rc_lock);
  4013. kthread_init_delayed_work(&sde_enc->delayed_off_work,
  4014. sde_encoder_off_work);
  4015. sde_enc->vblank_enabled = false;
  4016. sde_enc->qdss_status = false;
  4017. kthread_init_work(&sde_enc->vsync_event_work,
  4018. sde_encoder_vsync_event_work_handler);
  4019. kthread_init_work(&sde_enc->input_event_work,
  4020. sde_encoder_input_event_work_handler);
  4021. kthread_init_work(&sde_enc->esd_trigger_work,
  4022. sde_encoder_esd_trigger_work_handler);
  4023. memcpy(&sde_enc->disp_info, disp_info, sizeof(*disp_info));
  4024. SDE_DEBUG_ENC(sde_enc, "created\n");
  4025. return drm_enc;
  4026. fail:
  4027. SDE_ERROR("failed to create encoder\n");
  4028. if (drm_enc)
  4029. sde_encoder_destroy(drm_enc);
  4030. return ERR_PTR(ret);
  4031. }
  4032. struct drm_encoder *sde_encoder_init(
  4033. struct drm_device *dev,
  4034. struct msm_display_info *disp_info)
  4035. {
  4036. return sde_encoder_init_with_ops(dev, disp_info, NULL);
  4037. }
  4038. int sde_encoder_wait_for_event(struct drm_encoder *drm_enc,
  4039. enum msm_event_wait event)
  4040. {
  4041. int (*fn_wait)(struct sde_encoder_phys *phys_enc) = NULL;
  4042. struct sde_encoder_virt *sde_enc = NULL;
  4043. int i, ret = 0;
  4044. char atrace_buf[32];
  4045. if (!drm_enc) {
  4046. SDE_ERROR("invalid encoder\n");
  4047. return -EINVAL;
  4048. }
  4049. sde_enc = to_sde_encoder_virt(drm_enc);
  4050. SDE_DEBUG_ENC(sde_enc, "\n");
  4051. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4052. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4053. switch (event) {
  4054. case MSM_ENC_COMMIT_DONE:
  4055. fn_wait = phys->ops.wait_for_commit_done;
  4056. break;
  4057. case MSM_ENC_TX_COMPLETE:
  4058. fn_wait = phys->ops.wait_for_tx_complete;
  4059. break;
  4060. case MSM_ENC_VBLANK:
  4061. fn_wait = phys->ops.wait_for_vblank;
  4062. break;
  4063. case MSM_ENC_ACTIVE_REGION:
  4064. fn_wait = phys->ops.wait_for_active;
  4065. break;
  4066. default:
  4067. SDE_ERROR_ENC(sde_enc, "unknown wait event %d\n",
  4068. event);
  4069. return -EINVAL;
  4070. }
  4071. if (phys && fn_wait) {
  4072. snprintf(atrace_buf, sizeof(atrace_buf),
  4073. "wait_completion_event_%d", event);
  4074. SDE_ATRACE_BEGIN(atrace_buf);
  4075. ret = fn_wait(phys);
  4076. SDE_ATRACE_END(atrace_buf);
  4077. if (ret)
  4078. return ret;
  4079. }
  4080. }
  4081. return ret;
  4082. }
  4083. void sde_encoder_helper_get_jitter_bounds_ns(struct drm_encoder *drm_enc,
  4084. u64 *l_bound, u64 *u_bound)
  4085. {
  4086. struct sde_encoder_virt *sde_enc;
  4087. u64 jitter_ns, frametime_ns;
  4088. struct msm_mode_info *info;
  4089. if (!drm_enc) {
  4090. SDE_ERROR("invalid encoder\n");
  4091. return;
  4092. }
  4093. sde_enc = to_sde_encoder_virt(drm_enc);
  4094. info = &sde_enc->mode_info;
  4095. frametime_ns = (1 * 1000000000) / info->frame_rate;
  4096. jitter_ns = info->jitter_numer * frametime_ns;
  4097. do_div(jitter_ns, info->jitter_denom * 100);
  4098. *l_bound = frametime_ns - jitter_ns;
  4099. *u_bound = frametime_ns + jitter_ns;
  4100. }
  4101. u32 sde_encoder_get_fps(struct drm_encoder *drm_enc)
  4102. {
  4103. struct sde_encoder_virt *sde_enc;
  4104. if (!drm_enc) {
  4105. SDE_ERROR("invalid encoder\n");
  4106. return 0;
  4107. }
  4108. sde_enc = to_sde_encoder_virt(drm_enc);
  4109. return sde_enc->mode_info.frame_rate;
  4110. }
  4111. enum sde_intf_mode sde_encoder_get_intf_mode(struct drm_encoder *encoder)
  4112. {
  4113. struct sde_encoder_virt *sde_enc = NULL;
  4114. int i;
  4115. if (!encoder) {
  4116. SDE_ERROR("invalid encoder\n");
  4117. return INTF_MODE_NONE;
  4118. }
  4119. sde_enc = to_sde_encoder_virt(encoder);
  4120. if (sde_enc->cur_master)
  4121. return sde_enc->cur_master->intf_mode;
  4122. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4123. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4124. if (phys)
  4125. return phys->intf_mode;
  4126. }
  4127. return INTF_MODE_NONE;
  4128. }
  4129. static void _sde_encoder_cache_hw_res_cont_splash(
  4130. struct drm_encoder *encoder,
  4131. struct sde_kms *sde_kms)
  4132. {
  4133. int i, idx;
  4134. struct sde_encoder_virt *sde_enc;
  4135. struct sde_encoder_phys *phys_enc;
  4136. struct sde_rm_hw_iter dsc_iter, pp_iter, ctl_iter, intf_iter;
  4137. sde_enc = to_sde_encoder_virt(encoder);
  4138. sde_rm_init_hw_iter(&pp_iter, encoder->base.id, SDE_HW_BLK_PINGPONG);
  4139. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  4140. sde_enc->hw_pp[i] = NULL;
  4141. if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
  4142. break;
  4143. sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
  4144. }
  4145. sde_rm_init_hw_iter(&dsc_iter, encoder->base.id, SDE_HW_BLK_DSC);
  4146. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  4147. sde_enc->hw_dsc[i] = NULL;
  4148. if (!sde_rm_get_hw(&sde_kms->rm, &dsc_iter))
  4149. break;
  4150. sde_enc->hw_dsc[i] = (struct sde_hw_dsc *) dsc_iter.hw;
  4151. }
  4152. /*
  4153. * If we have multiple phys encoders with one controller, make
  4154. * sure to populate the controller pointer in both phys encoders.
  4155. */
  4156. for (idx = 0; idx < sde_enc->num_phys_encs; idx++) {
  4157. phys_enc = sde_enc->phys_encs[idx];
  4158. phys_enc->hw_ctl = NULL;
  4159. sde_rm_init_hw_iter(&ctl_iter, encoder->base.id,
  4160. SDE_HW_BLK_CTL);
  4161. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4162. if (sde_rm_get_hw(&sde_kms->rm, &ctl_iter)) {
  4163. phys_enc->hw_ctl =
  4164. (struct sde_hw_ctl *) ctl_iter.hw;
  4165. pr_debug("HW CTL intf_idx:%d hw_ctl:[0x%pK]\n",
  4166. phys_enc->intf_idx, phys_enc->hw_ctl);
  4167. }
  4168. }
  4169. }
  4170. sde_rm_init_hw_iter(&intf_iter, encoder->base.id, SDE_HW_BLK_INTF);
  4171. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4172. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4173. phys->hw_intf = NULL;
  4174. if (!sde_rm_get_hw(&sde_kms->rm, &intf_iter))
  4175. break;
  4176. phys->hw_intf = (struct sde_hw_intf *) intf_iter.hw;
  4177. }
  4178. }
  4179. /**
  4180. * sde_encoder_update_caps_for_cont_splash - update encoder settings during
  4181. * device bootup when cont_splash is enabled
  4182. * @drm_enc: Pointer to drm encoder structure
  4183. * @splash_display: Pointer to sde_splash_display corresponding to this encoder
  4184. * @enable: boolean indicates enable or displae state of splash
  4185. * @Return: true if successful in updating the encoder structure
  4186. */
  4187. int sde_encoder_update_caps_for_cont_splash(struct drm_encoder *encoder,
  4188. struct sde_splash_display *splash_display, bool enable)
  4189. {
  4190. struct sde_encoder_virt *sde_enc;
  4191. struct msm_drm_private *priv;
  4192. struct sde_kms *sde_kms;
  4193. struct drm_connector *conn = NULL;
  4194. struct sde_connector *sde_conn = NULL;
  4195. struct sde_connector_state *sde_conn_state = NULL;
  4196. struct drm_display_mode *drm_mode = NULL;
  4197. struct sde_encoder_phys *phys_enc;
  4198. int ret = 0, i;
  4199. if (!encoder) {
  4200. SDE_ERROR("invalid drm enc\n");
  4201. return -EINVAL;
  4202. }
  4203. if (!encoder->dev || !encoder->dev->dev_private) {
  4204. SDE_ERROR("drm device invalid\n");
  4205. return -EINVAL;
  4206. }
  4207. priv = encoder->dev->dev_private;
  4208. if (!priv->kms) {
  4209. SDE_ERROR("invalid kms\n");
  4210. return -EINVAL;
  4211. }
  4212. sde_kms = to_sde_kms(priv->kms);
  4213. sde_enc = to_sde_encoder_virt(encoder);
  4214. if (!priv->num_connectors) {
  4215. SDE_ERROR_ENC(sde_enc, "No connectors registered\n");
  4216. return -EINVAL;
  4217. }
  4218. SDE_DEBUG_ENC(sde_enc,
  4219. "num of connectors: %d\n", priv->num_connectors);
  4220. SDE_DEBUG_ENC(sde_enc, "enable: %d\n", enable);
  4221. if (!enable) {
  4222. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4223. phys_enc = sde_enc->phys_encs[i];
  4224. if (phys_enc)
  4225. phys_enc->cont_splash_enabled = false;
  4226. }
  4227. return ret;
  4228. }
  4229. if (!splash_display) {
  4230. SDE_ERROR_ENC(sde_enc, "invalid splash data\n");
  4231. return -EINVAL;
  4232. }
  4233. for (i = 0; i < priv->num_connectors; i++) {
  4234. SDE_DEBUG_ENC(sde_enc, "connector id: %d\n",
  4235. priv->connectors[i]->base.id);
  4236. sde_conn = to_sde_connector(priv->connectors[i]);
  4237. if (!sde_conn->encoder) {
  4238. SDE_DEBUG_ENC(sde_enc,
  4239. "encoder not attached to connector\n");
  4240. continue;
  4241. }
  4242. if (sde_conn->encoder->base.id
  4243. == encoder->base.id) {
  4244. conn = (priv->connectors[i]);
  4245. break;
  4246. }
  4247. }
  4248. if (!conn || !conn->state) {
  4249. SDE_ERROR_ENC(sde_enc, "connector not found\n");
  4250. return -EINVAL;
  4251. }
  4252. sde_conn_state = to_sde_connector_state(conn->state);
  4253. if (!sde_conn->ops.get_mode_info) {
  4254. SDE_ERROR_ENC(sde_enc, "conn: get_mode_info ops not found\n");
  4255. return -EINVAL;
  4256. }
  4257. ret = sde_connector_get_mode_info(&sde_conn->base,
  4258. &encoder->crtc->state->adjusted_mode,
  4259. &sde_conn_state->mode_info);
  4260. if (ret) {
  4261. SDE_ERROR_ENC(sde_enc,
  4262. "conn: ->get_mode_info failed. ret=%d\n", ret);
  4263. return ret;
  4264. }
  4265. ret = sde_rm_reserve(&sde_kms->rm, encoder, encoder->crtc->state,
  4266. conn->state, false);
  4267. if (ret) {
  4268. SDE_ERROR_ENC(sde_enc,
  4269. "failed to reserve hw resources, %d\n", ret);
  4270. return ret;
  4271. }
  4272. if (sde_conn->encoder) {
  4273. conn->state->best_encoder = sde_conn->encoder;
  4274. SDE_DEBUG_ENC(sde_enc,
  4275. "configured cstate->best_encoder to ID = %d\n",
  4276. conn->state->best_encoder->base.id);
  4277. } else {
  4278. SDE_ERROR_ENC(sde_enc, "No encoder mapped to connector=%d\n",
  4279. conn->base.id);
  4280. }
  4281. SDE_DEBUG_ENC(sde_enc, "connector topology = %llu\n",
  4282. sde_connector_get_topology_name(conn));
  4283. drm_mode = &encoder->crtc->state->adjusted_mode;
  4284. SDE_DEBUG_ENC(sde_enc, "hdisplay = %d, vdisplay = %d\n",
  4285. drm_mode->hdisplay, drm_mode->vdisplay);
  4286. drm_set_preferred_mode(conn, drm_mode->hdisplay, drm_mode->vdisplay);
  4287. if (encoder->bridge) {
  4288. SDE_DEBUG_ENC(sde_enc, "Bridge mapped to encoder\n");
  4289. /*
  4290. * For cont-splash use case, we update the mode
  4291. * configurations manually. This will skip the
  4292. * usually mode set call when actual frame is
  4293. * pushed from framework. The bridge needs to
  4294. * be updated with the current drm mode by
  4295. * calling the bridge mode set ops.
  4296. */
  4297. if (encoder->bridge->funcs) {
  4298. SDE_DEBUG_ENC(sde_enc, "calling mode_set\n");
  4299. encoder->bridge->funcs->mode_set(encoder->bridge,
  4300. drm_mode, drm_mode);
  4301. }
  4302. } else {
  4303. SDE_ERROR_ENC(sde_enc, "No bridge attached to encoder\n");
  4304. }
  4305. _sde_encoder_cache_hw_res_cont_splash(encoder, sde_kms);
  4306. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4307. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4308. if (!phys) {
  4309. SDE_ERROR_ENC(sde_enc,
  4310. "phys encoders not initialized\n");
  4311. return -EINVAL;
  4312. }
  4313. /* update connector for master and slave phys encoders */
  4314. phys->connector = conn;
  4315. phys->cont_splash_enabled = true;
  4316. phys->hw_pp = sde_enc->hw_pp[i];
  4317. if (phys->ops.cont_splash_mode_set)
  4318. phys->ops.cont_splash_mode_set(phys, drm_mode);
  4319. if (phys->ops.is_master && phys->ops.is_master(phys))
  4320. sde_enc->cur_master = phys;
  4321. }
  4322. return ret;
  4323. }
  4324. int sde_encoder_display_failure_notification(struct drm_encoder *enc,
  4325. bool skip_pre_kickoff)
  4326. {
  4327. struct msm_drm_thread *event_thread = NULL;
  4328. struct msm_drm_private *priv = NULL;
  4329. struct sde_encoder_virt *sde_enc = NULL;
  4330. if (!enc || !enc->dev || !enc->dev->dev_private) {
  4331. SDE_ERROR("invalid parameters\n");
  4332. return -EINVAL;
  4333. }
  4334. priv = enc->dev->dev_private;
  4335. sde_enc = to_sde_encoder_virt(enc);
  4336. if (!sde_enc->crtc || (sde_enc->crtc->index
  4337. >= ARRAY_SIZE(priv->event_thread))) {
  4338. SDE_DEBUG_ENC(sde_enc,
  4339. "invalid cached CRTC: %d or crtc index: %d\n",
  4340. sde_enc->crtc == NULL,
  4341. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  4342. return -EINVAL;
  4343. }
  4344. SDE_EVT32_VERBOSE(DRMID(enc));
  4345. event_thread = &priv->event_thread[sde_enc->crtc->index];
  4346. if (!skip_pre_kickoff) {
  4347. kthread_queue_work(&event_thread->worker,
  4348. &sde_enc->esd_trigger_work);
  4349. kthread_flush_work(&sde_enc->esd_trigger_work);
  4350. }
  4351. /*
  4352. * panel may stop generating te signal (vsync) during esd failure. rsc
  4353. * hardware may hang without vsync. Avoid rsc hang by generating the
  4354. * vsync from watchdog timer instead of panel.
  4355. */
  4356. sde_encoder_helper_switch_vsync(enc, true);
  4357. if (!skip_pre_kickoff)
  4358. sde_encoder_wait_for_event(enc, MSM_ENC_TX_COMPLETE);
  4359. return 0;
  4360. }
  4361. bool sde_encoder_recovery_events_enabled(struct drm_encoder *encoder)
  4362. {
  4363. struct sde_encoder_virt *sde_enc;
  4364. if (!encoder) {
  4365. SDE_ERROR("invalid drm enc\n");
  4366. return false;
  4367. }
  4368. sde_enc = to_sde_encoder_virt(encoder);
  4369. return sde_enc->recovery_events_enabled;
  4370. }
  4371. void sde_encoder_recovery_events_handler(struct drm_encoder *encoder,
  4372. bool enabled)
  4373. {
  4374. struct sde_encoder_virt *sde_enc;
  4375. if (!encoder) {
  4376. SDE_ERROR("invalid drm enc\n");
  4377. return;
  4378. }
  4379. sde_enc = to_sde_encoder_virt(encoder);
  4380. sde_enc->recovery_events_enabled = enabled;
  4381. }