Acquire mngr clk_mutex before updating link clock frequencies.
Failing this may lead to race around condition while setting the
link clock frequency rates.
Make sure byteclk and pclk rates of PLL are configured according
to clock manager and not the controller.
Change-Id: I2cd26e659ce166d5bc55eb6c060672eeee192bea
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
307aea3dc1