cam_mem_mgr.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/types.h>
  7. #include <linux/mutex.h>
  8. #include <linux/slab.h>
  9. #include <linux/dma-buf.h>
  10. #include <linux/version.h>
  11. #include <linux/debugfs.h>
  12. #include "cam_compat.h"
  13. #include "cam_req_mgr_util.h"
  14. #include "cam_mem_mgr.h"
  15. #include "cam_smmu_api.h"
  16. #include "cam_debug_util.h"
  17. #include "cam_trace.h"
  18. #include "cam_common_util.h"
  19. static struct cam_mem_table tbl;
  20. static atomic_t cam_mem_mgr_state = ATOMIC_INIT(CAM_MEM_MGR_UNINITIALIZED);
  21. static void cam_mem_mgr_print_tbl(void)
  22. {
  23. int i;
  24. uint64_t ms, tmp, hrs, min, sec;
  25. struct timespec64 *ts = NULL;
  26. struct timespec64 current_ts;
  27. ktime_get_real_ts64(&(current_ts));
  28. tmp = current_ts.tv_sec;
  29. ms = (current_ts.tv_nsec) / 1000000;
  30. sec = do_div(tmp, 60);
  31. min = do_div(tmp, 60);
  32. hrs = do_div(tmp, 24);
  33. CAM_INFO(CAM_MEM, "***%llu:%llu:%llu:%llu Mem mgr table dump***",
  34. hrs, min, sec, ms);
  35. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  36. if (tbl.bufq[i].active) {
  37. ts = &tbl.bufq[i].timestamp;
  38. tmp = ts->tv_sec;
  39. ms = (ts->tv_nsec) / 1000000;
  40. sec = do_div(tmp, 60);
  41. min = do_div(tmp, 60);
  42. hrs = do_div(tmp, 24);
  43. CAM_INFO(CAM_MEM,
  44. "%llu:%llu:%llu:%llu idx %d fd %d size %llu",
  45. hrs, min, sec, ms, i, tbl.bufq[i].fd,
  46. tbl.bufq[i].len);
  47. }
  48. }
  49. }
  50. static int cam_mem_util_get_dma_dir(uint32_t flags)
  51. {
  52. int rc = -EINVAL;
  53. if (flags & CAM_MEM_FLAG_HW_READ_ONLY)
  54. rc = DMA_TO_DEVICE;
  55. else if (flags & CAM_MEM_FLAG_HW_WRITE_ONLY)
  56. rc = DMA_FROM_DEVICE;
  57. else if (flags & CAM_MEM_FLAG_HW_READ_WRITE)
  58. rc = DMA_BIDIRECTIONAL;
  59. else if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  60. rc = DMA_BIDIRECTIONAL;
  61. return rc;
  62. }
  63. static int cam_mem_util_map_cpu_va(struct dma_buf *dmabuf,
  64. uintptr_t *vaddr,
  65. size_t *len)
  66. {
  67. int rc = 0;
  68. void *addr;
  69. /*
  70. * dma_buf_begin_cpu_access() and dma_buf_end_cpu_access()
  71. * need to be called in pair to avoid stability issue.
  72. */
  73. rc = dma_buf_begin_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  74. if (rc) {
  75. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  76. return rc;
  77. }
  78. addr = dma_buf_vmap(dmabuf);
  79. if (!addr) {
  80. CAM_ERR(CAM_MEM, "kernel map fail");
  81. *vaddr = 0;
  82. *len = 0;
  83. rc = -ENOSPC;
  84. goto fail;
  85. }
  86. *vaddr = (uint64_t)addr;
  87. *len = dmabuf->size;
  88. return 0;
  89. fail:
  90. dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  91. return rc;
  92. }
  93. static int cam_mem_util_unmap_cpu_va(struct dma_buf *dmabuf,
  94. uint64_t vaddr)
  95. {
  96. int rc = 0;
  97. if (!dmabuf || !vaddr) {
  98. CAM_ERR(CAM_MEM, "Invalid input args %pK %llX", dmabuf, vaddr);
  99. return -EINVAL;
  100. }
  101. dma_buf_vunmap(dmabuf, (void *)vaddr);
  102. /*
  103. * dma_buf_begin_cpu_access() and
  104. * dma_buf_end_cpu_access() need to be called in pair
  105. * to avoid stability issue.
  106. */
  107. rc = dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  108. if (rc) {
  109. CAM_ERR(CAM_MEM, "Failed in end cpu access, dmabuf=%pK",
  110. dmabuf);
  111. return rc;
  112. }
  113. return rc;
  114. }
  115. static int cam_mem_mgr_create_debug_fs(void)
  116. {
  117. int rc = 0;
  118. struct dentry *dbgfileptr = NULL;
  119. dbgfileptr = debugfs_create_dir("camera_memmgr", NULL);
  120. if (!dbgfileptr) {
  121. CAM_ERR(CAM_MEM,"DebugFS could not create directory!");
  122. rc = -ENOENT;
  123. goto end;
  124. }
  125. /* Store parent inode for cleanup in caller */
  126. tbl.dentry = dbgfileptr;
  127. dbgfileptr = debugfs_create_bool("alloc_profile_enable", 0644,
  128. tbl.dentry, &tbl.alloc_profile_enable);
  129. if (IS_ERR(dbgfileptr)) {
  130. if (PTR_ERR(dbgfileptr) == -ENODEV)
  131. CAM_WARN(CAM_MEM, "DebugFS not enabled in kernel!");
  132. else
  133. rc = PTR_ERR(dbgfileptr);
  134. }
  135. end:
  136. return rc;
  137. }
  138. int cam_mem_mgr_init(void)
  139. {
  140. int i;
  141. int bitmap_size;
  142. memset(tbl.bufq, 0, sizeof(tbl.bufq));
  143. bitmap_size = BITS_TO_LONGS(CAM_MEM_BUFQ_MAX) * sizeof(long);
  144. tbl.bitmap = kzalloc(bitmap_size, GFP_KERNEL);
  145. if (!tbl.bitmap)
  146. return -ENOMEM;
  147. tbl.bits = bitmap_size * BITS_PER_BYTE;
  148. bitmap_zero(tbl.bitmap, tbl.bits);
  149. /* We need to reserve slot 0 because 0 is invalid */
  150. set_bit(0, tbl.bitmap);
  151. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  152. tbl.bufq[i].fd = -1;
  153. tbl.bufq[i].buf_handle = -1;
  154. }
  155. mutex_init(&tbl.m_lock);
  156. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_INITIALIZED);
  157. cam_mem_mgr_create_debug_fs();
  158. return 0;
  159. }
  160. static int32_t cam_mem_get_slot(void)
  161. {
  162. int32_t idx;
  163. mutex_lock(&tbl.m_lock);
  164. idx = find_first_zero_bit(tbl.bitmap, tbl.bits);
  165. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  166. mutex_unlock(&tbl.m_lock);
  167. return -ENOMEM;
  168. }
  169. set_bit(idx, tbl.bitmap);
  170. tbl.bufq[idx].active = true;
  171. ktime_get_real_ts64(&(tbl.bufq[idx].timestamp));
  172. mutex_init(&tbl.bufq[idx].q_lock);
  173. mutex_unlock(&tbl.m_lock);
  174. return idx;
  175. }
  176. static void cam_mem_put_slot(int32_t idx)
  177. {
  178. mutex_lock(&tbl.m_lock);
  179. mutex_lock(&tbl.bufq[idx].q_lock);
  180. tbl.bufq[idx].active = false;
  181. tbl.bufq[idx].is_internal = false;
  182. memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64));
  183. mutex_unlock(&tbl.bufq[idx].q_lock);
  184. mutex_destroy(&tbl.bufq[idx].q_lock);
  185. clear_bit(idx, tbl.bitmap);
  186. mutex_unlock(&tbl.m_lock);
  187. }
  188. int cam_mem_get_io_buf(int32_t buf_handle, int32_t mmu_handle,
  189. dma_addr_t *iova_ptr, size_t *len_ptr)
  190. {
  191. int rc = 0, idx;
  192. *len_ptr = 0;
  193. if (!atomic_read(&cam_mem_mgr_state)) {
  194. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  195. return -EINVAL;
  196. }
  197. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  198. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  199. return -ENOENT;
  200. if (!tbl.bufq[idx].active) {
  201. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  202. idx);
  203. return -EAGAIN;
  204. }
  205. mutex_lock(&tbl.bufq[idx].q_lock);
  206. if (buf_handle != tbl.bufq[idx].buf_handle) {
  207. rc = -EINVAL;
  208. goto handle_mismatch;
  209. }
  210. if (CAM_MEM_MGR_IS_SECURE_HDL(buf_handle))
  211. rc = cam_smmu_get_stage2_iova(mmu_handle,
  212. tbl.bufq[idx].fd,
  213. iova_ptr,
  214. len_ptr);
  215. else
  216. rc = cam_smmu_get_iova(mmu_handle,
  217. tbl.bufq[idx].fd,
  218. iova_ptr,
  219. len_ptr);
  220. if (rc) {
  221. CAM_ERR(CAM_MEM,
  222. "fail to map buf_hdl:0x%x, mmu_hdl: 0x%x for fd:%d",
  223. buf_handle, mmu_handle, tbl.bufq[idx].fd);
  224. goto handle_mismatch;
  225. }
  226. CAM_DBG(CAM_MEM,
  227. "handle:0x%x fd:%d iova_ptr:%pK len_ptr:%llu",
  228. mmu_handle, tbl.bufq[idx].fd, iova_ptr, *len_ptr);
  229. handle_mismatch:
  230. mutex_unlock(&tbl.bufq[idx].q_lock);
  231. return rc;
  232. }
  233. EXPORT_SYMBOL(cam_mem_get_io_buf);
  234. int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len)
  235. {
  236. int idx;
  237. if (!atomic_read(&cam_mem_mgr_state)) {
  238. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  239. return -EINVAL;
  240. }
  241. if (!atomic_read(&cam_mem_mgr_state)) {
  242. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  243. return -EINVAL;
  244. }
  245. if (!buf_handle || !vaddr_ptr || !len)
  246. return -EINVAL;
  247. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  248. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  249. return -EINVAL;
  250. if (!tbl.bufq[idx].active) {
  251. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  252. idx);
  253. return -EPERM;
  254. }
  255. if (buf_handle != tbl.bufq[idx].buf_handle)
  256. return -EINVAL;
  257. if (!(tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS))
  258. return -EINVAL;
  259. if (tbl.bufq[idx].kmdvaddr) {
  260. *vaddr_ptr = tbl.bufq[idx].kmdvaddr;
  261. *len = tbl.bufq[idx].len;
  262. } else {
  263. CAM_ERR(CAM_MEM, "No KMD access was requested for 0x%x handle",
  264. buf_handle);
  265. return -EINVAL;
  266. }
  267. return 0;
  268. }
  269. EXPORT_SYMBOL(cam_mem_get_cpu_buf);
  270. int cam_mem_mgr_cache_ops(struct cam_mem_cache_ops_cmd *cmd)
  271. {
  272. int rc = 0, idx;
  273. uint32_t cache_dir;
  274. unsigned long dmabuf_flag = 0;
  275. if (!atomic_read(&cam_mem_mgr_state)) {
  276. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  277. return -EINVAL;
  278. }
  279. if (!cmd)
  280. return -EINVAL;
  281. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  282. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  283. return -EINVAL;
  284. mutex_lock(&tbl.bufq[idx].q_lock);
  285. if (!tbl.bufq[idx].active) {
  286. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  287. idx);
  288. rc = -EINVAL;
  289. goto end;
  290. }
  291. if (cmd->buf_handle != tbl.bufq[idx].buf_handle) {
  292. rc = -EINVAL;
  293. goto end;
  294. }
  295. rc = dma_buf_get_flags(tbl.bufq[idx].dma_buf, &dmabuf_flag);
  296. if (rc) {
  297. CAM_ERR(CAM_MEM, "cache get flags failed %d", rc);
  298. goto end;
  299. }
  300. if (dmabuf_flag & ION_FLAG_CACHED) {
  301. switch (cmd->mem_cache_ops) {
  302. case CAM_MEM_CLEAN_CACHE:
  303. cache_dir = DMA_TO_DEVICE;
  304. break;
  305. case CAM_MEM_INV_CACHE:
  306. cache_dir = DMA_FROM_DEVICE;
  307. break;
  308. case CAM_MEM_CLEAN_INV_CACHE:
  309. cache_dir = DMA_BIDIRECTIONAL;
  310. break;
  311. default:
  312. CAM_ERR(CAM_MEM,
  313. "invalid cache ops :%d", cmd->mem_cache_ops);
  314. rc = -EINVAL;
  315. goto end;
  316. }
  317. } else {
  318. CAM_DBG(CAM_MEM, "BUF is not cached");
  319. goto end;
  320. }
  321. rc = dma_buf_begin_cpu_access(tbl.bufq[idx].dma_buf,
  322. (cmd->mem_cache_ops == CAM_MEM_CLEAN_INV_CACHE) ?
  323. DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
  324. if (rc) {
  325. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  326. goto end;
  327. }
  328. rc = dma_buf_end_cpu_access(tbl.bufq[idx].dma_buf,
  329. cache_dir);
  330. if (rc) {
  331. CAM_ERR(CAM_MEM, "dma end access failed rc=%d", rc);
  332. goto end;
  333. }
  334. end:
  335. mutex_unlock(&tbl.bufq[idx].q_lock);
  336. return rc;
  337. }
  338. EXPORT_SYMBOL(cam_mem_mgr_cache_ops);
  339. static int cam_mem_util_get_dma_buf(size_t len,
  340. unsigned int heap_id_mask,
  341. unsigned int flags,
  342. struct dma_buf **buf)
  343. {
  344. int rc = 0;
  345. if (!buf) {
  346. CAM_ERR(CAM_MEM, "Invalid params");
  347. return -EINVAL;
  348. }
  349. *buf = ion_alloc(len, heap_id_mask, flags);
  350. if (IS_ERR_OR_NULL(*buf))
  351. return -ENOMEM;
  352. return rc;
  353. }
  354. static int cam_mem_util_get_dma_buf_fd(size_t len,
  355. size_t align,
  356. unsigned int heap_id_mask,
  357. unsigned int flags,
  358. struct dma_buf **buf,
  359. int *fd)
  360. {
  361. struct dma_buf *dmabuf = NULL;
  362. int rc = 0;
  363. struct timespec64 ts1, ts2;
  364. long microsec = 0;
  365. if (!buf || !fd) {
  366. CAM_ERR(CAM_MEM, "Invalid params, buf=%pK, fd=%pK", buf, fd);
  367. return -EINVAL;
  368. }
  369. if (tbl.alloc_profile_enable)
  370. CAM_GET_TIMESTAMP(ts1);
  371. *buf = ion_alloc(len, heap_id_mask, flags);
  372. if (IS_ERR_OR_NULL(*buf))
  373. return -ENOMEM;
  374. *fd = dma_buf_fd(*buf, O_CLOEXEC);
  375. if (*fd < 0) {
  376. CAM_ERR(CAM_MEM, "get fd fail, *fd=%d", *fd);
  377. rc = -EINVAL;
  378. goto get_fd_fail;
  379. }
  380. /*
  381. * increment the ref count so that ref count becomes 2 here
  382. * when we close fd, refcount becomes 1 and when we do
  383. * dmap_put_buf, ref count becomes 0 and memory will be freed.
  384. */
  385. dmabuf = dma_buf_get(*fd);
  386. if (IS_ERR_OR_NULL(dmabuf)) {
  387. CAM_ERR(CAM_MEM, "dma_buf_get failed, *fd=%d", *fd);
  388. rc = -EINVAL;
  389. }
  390. if (tbl.alloc_profile_enable) {
  391. CAM_GET_TIMESTAMP(ts2);
  392. CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec);
  393. trace_cam_log_event("IONAllocProfile", "size and time in micro",
  394. len, microsec);
  395. }
  396. return rc;
  397. get_fd_fail:
  398. dma_buf_put(*buf);
  399. return rc;
  400. }
  401. static int cam_mem_util_ion_alloc(struct cam_mem_mgr_alloc_cmd *cmd,
  402. struct dma_buf **dmabuf,
  403. int *fd)
  404. {
  405. uint32_t heap_id;
  406. uint32_t ion_flag = 0;
  407. int rc;
  408. if ((cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE) &&
  409. (cmd->flags & CAM_MEM_FLAG_CDSP_OUTPUT)) {
  410. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  411. ion_flag |=
  412. ION_FLAG_SECURE | ION_FLAG_CP_CAMERA | ION_FLAG_CP_CDSP;
  413. } else if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  414. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  415. ion_flag |= ION_FLAG_SECURE | ION_FLAG_CP_CAMERA;
  416. } else {
  417. heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) |
  418. ION_HEAP(ION_CAMERA_HEAP_ID);
  419. }
  420. if (cmd->flags & CAM_MEM_FLAG_CACHE)
  421. ion_flag |= ION_FLAG_CACHED;
  422. else
  423. ion_flag &= ~ION_FLAG_CACHED;
  424. rc = cam_mem_util_get_dma_buf_fd(cmd->len,
  425. cmd->align,
  426. heap_id,
  427. ion_flag,
  428. dmabuf,
  429. fd);
  430. return rc;
  431. }
  432. static int cam_mem_util_check_alloc_flags(struct cam_mem_mgr_alloc_cmd *cmd)
  433. {
  434. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  435. CAM_ERR(CAM_MEM, "Num of mmu hdl exceeded maximum(%d)",
  436. CAM_MEM_MMU_MAX_HANDLE);
  437. return -EINVAL;
  438. }
  439. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  440. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  441. CAM_ERR(CAM_MEM, "Kernel mapping in secure mode not allowed");
  442. return -EINVAL;
  443. }
  444. return 0;
  445. }
  446. static int cam_mem_util_check_map_flags(struct cam_mem_mgr_map_cmd *cmd)
  447. {
  448. if (!cmd->flags) {
  449. CAM_ERR(CAM_MEM, "Invalid flags");
  450. return -EINVAL;
  451. }
  452. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  453. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  454. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  455. return -EINVAL;
  456. }
  457. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  458. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  459. CAM_ERR(CAM_MEM,
  460. "Kernel mapping in secure mode not allowed, flags=0x%x",
  461. cmd->flags);
  462. return -EINVAL;
  463. }
  464. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  465. CAM_ERR(CAM_MEM,
  466. "Shared memory buffers are not allowed to be mapped");
  467. return -EINVAL;
  468. }
  469. return 0;
  470. }
  471. static int cam_mem_util_map_hw_va(uint32_t flags,
  472. int32_t *mmu_hdls,
  473. int32_t num_hdls,
  474. int fd,
  475. dma_addr_t *hw_vaddr,
  476. size_t *len,
  477. enum cam_smmu_region_id region,
  478. bool is_internal)
  479. {
  480. int i;
  481. int rc = -1;
  482. int dir = cam_mem_util_get_dma_dir(flags);
  483. bool dis_delayed_unmap = false;
  484. if (dir < 0) {
  485. CAM_ERR(CAM_MEM, "fail to map DMA direction, dir=%d", dir);
  486. return dir;
  487. }
  488. if (flags & CAM_MEM_FLAG_DISABLE_DELAYED_UNMAP)
  489. dis_delayed_unmap = true;
  490. CAM_DBG(CAM_MEM,
  491. "map_hw_va : fd = %d, flags = 0x%x, dir=%d, num_hdls=%d",
  492. fd, flags, dir, num_hdls);
  493. if (flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  494. for (i = 0; i < num_hdls; i++) {
  495. rc = cam_smmu_map_stage2_iova(mmu_hdls[i],
  496. fd,
  497. dir,
  498. hw_vaddr,
  499. len);
  500. if (rc < 0) {
  501. CAM_ERR(CAM_MEM,
  502. "Failed to securely map to smmu, i=%d, fd=%d, dir=%d, mmu_hdl=%d, rc=%d",
  503. i, fd, dir, mmu_hdls[i], rc);
  504. goto multi_map_fail;
  505. }
  506. }
  507. } else {
  508. for (i = 0; i < num_hdls; i++) {
  509. rc = cam_smmu_map_user_iova(mmu_hdls[i],
  510. fd,
  511. dis_delayed_unmap,
  512. dir,
  513. (dma_addr_t *)hw_vaddr,
  514. len,
  515. region,
  516. is_internal);
  517. if (rc < 0) {
  518. CAM_ERR(CAM_MEM,
  519. "Failed to map to smmu, i=%d, fd=%d, dir=%d, mmu_hdl=%d, region=%d, rc=%d",
  520. i, fd, dir, mmu_hdls[i], region, rc);
  521. goto multi_map_fail;
  522. }
  523. }
  524. }
  525. return rc;
  526. multi_map_fail:
  527. if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  528. for (--i; i >= 0; i--)
  529. cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd);
  530. else
  531. for (--i; i >= 0; i--)
  532. cam_smmu_unmap_user_iova(mmu_hdls[i],
  533. fd,
  534. CAM_SMMU_REGION_IO);
  535. return rc;
  536. }
  537. int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd)
  538. {
  539. int rc;
  540. int32_t idx;
  541. struct dma_buf *dmabuf = NULL;
  542. int fd = -1;
  543. dma_addr_t hw_vaddr = 0;
  544. size_t len;
  545. uintptr_t kvaddr = 0;
  546. size_t klen;
  547. if (!atomic_read(&cam_mem_mgr_state)) {
  548. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  549. return -EINVAL;
  550. }
  551. if (!cmd) {
  552. CAM_ERR(CAM_MEM, " Invalid argument");
  553. return -EINVAL;
  554. }
  555. len = cmd->len;
  556. rc = cam_mem_util_check_alloc_flags(cmd);
  557. if (rc) {
  558. CAM_ERR(CAM_MEM, "Invalid flags: flags = 0x%X, rc=%d",
  559. cmd->flags, rc);
  560. return rc;
  561. }
  562. rc = cam_mem_util_ion_alloc(cmd,
  563. &dmabuf,
  564. &fd);
  565. if (rc) {
  566. CAM_ERR(CAM_MEM,
  567. "Ion Alloc failed, len=%llu, align=%llu, flags=0x%x, num_hdl=%d",
  568. cmd->len, cmd->align, cmd->flags, cmd->num_hdl);
  569. cam_mem_mgr_print_tbl();
  570. return rc;
  571. }
  572. idx = cam_mem_get_slot();
  573. if (idx < 0) {
  574. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  575. rc = -ENOMEM;
  576. goto slot_fail;
  577. }
  578. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  579. (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  580. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  581. enum cam_smmu_region_id region;
  582. if (cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  583. region = CAM_SMMU_REGION_IO;
  584. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  585. region = CAM_SMMU_REGION_SHARED;
  586. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  587. region = CAM_SMMU_REGION_SECHEAP;
  588. rc = cam_mem_util_map_hw_va(cmd->flags,
  589. cmd->mmu_hdls,
  590. cmd->num_hdl,
  591. fd,
  592. &hw_vaddr,
  593. &len,
  594. region,
  595. true);
  596. if (rc) {
  597. CAM_ERR(CAM_MEM,
  598. "Failed in map_hw_va len=%llu, flags=0x%x, fd=%d, region=%d, num_hdl=%d, rc=%d",
  599. len, cmd->flags,
  600. fd, region, cmd->num_hdl, rc);
  601. if (rc == -EALREADY) {
  602. if ((size_t)dmabuf->size != len)
  603. rc = -EBADR;
  604. cam_mem_mgr_print_tbl();
  605. }
  606. goto map_hw_fail;
  607. }
  608. }
  609. mutex_lock(&tbl.bufq[idx].q_lock);
  610. tbl.bufq[idx].fd = fd;
  611. tbl.bufq[idx].dma_buf = NULL;
  612. tbl.bufq[idx].flags = cmd->flags;
  613. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, fd);
  614. tbl.bufq[idx].is_internal = true;
  615. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  616. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  617. if (cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  618. rc = cam_mem_util_map_cpu_va(dmabuf, &kvaddr, &klen);
  619. if (rc) {
  620. CAM_ERR(CAM_MEM, "dmabuf: %pK mapping failed: %d",
  621. dmabuf, rc);
  622. goto map_kernel_fail;
  623. }
  624. }
  625. if (cmd->flags & CAM_MEM_FLAG_KMD_DEBUG_FLAG)
  626. tbl.dbg_buf_idx = idx;
  627. tbl.bufq[idx].kmdvaddr = kvaddr;
  628. tbl.bufq[idx].vaddr = hw_vaddr;
  629. tbl.bufq[idx].dma_buf = dmabuf;
  630. tbl.bufq[idx].len = cmd->len;
  631. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  632. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  633. sizeof(int32_t) * cmd->num_hdl);
  634. tbl.bufq[idx].is_imported = false;
  635. mutex_unlock(&tbl.bufq[idx].q_lock);
  636. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  637. cmd->out.fd = tbl.bufq[idx].fd;
  638. cmd->out.vaddr = 0;
  639. CAM_DBG(CAM_MEM,
  640. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu",
  641. cmd->out.fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  642. tbl.bufq[idx].len);
  643. return rc;
  644. map_kernel_fail:
  645. mutex_unlock(&tbl.bufq[idx].q_lock);
  646. map_hw_fail:
  647. cam_mem_put_slot(idx);
  648. slot_fail:
  649. dma_buf_put(dmabuf);
  650. return rc;
  651. }
  652. static bool cam_mem_util_is_map_internal(int32_t fd)
  653. {
  654. uint32_t i;
  655. bool is_internal = false;
  656. mutex_lock(&tbl.m_lock);
  657. for_each_set_bit(i, tbl.bitmap, tbl.bits) {
  658. if (tbl.bufq[i].fd == fd) {
  659. is_internal = tbl.bufq[i].is_internal;
  660. break;
  661. }
  662. }
  663. mutex_unlock(&tbl.m_lock);
  664. return is_internal;
  665. }
  666. int cam_mem_mgr_map(struct cam_mem_mgr_map_cmd *cmd)
  667. {
  668. int32_t idx;
  669. int rc;
  670. struct dma_buf *dmabuf;
  671. dma_addr_t hw_vaddr = 0;
  672. size_t len = 0;
  673. bool is_internal = false;
  674. if (!atomic_read(&cam_mem_mgr_state)) {
  675. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  676. return -EINVAL;
  677. }
  678. if (!cmd || (cmd->fd < 0)) {
  679. CAM_ERR(CAM_MEM, "Invalid argument");
  680. return -EINVAL;
  681. }
  682. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  683. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  684. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  685. return -EINVAL;
  686. }
  687. rc = cam_mem_util_check_map_flags(cmd);
  688. if (rc) {
  689. CAM_ERR(CAM_MEM, "Invalid flags: flags = %X", cmd->flags);
  690. return rc;
  691. }
  692. dmabuf = dma_buf_get(cmd->fd);
  693. if (IS_ERR_OR_NULL((void *)(dmabuf))) {
  694. CAM_ERR(CAM_MEM, "Failed to import dma_buf fd");
  695. return -EINVAL;
  696. }
  697. is_internal = cam_mem_util_is_map_internal(cmd->fd);
  698. idx = cam_mem_get_slot();
  699. if (idx < 0) {
  700. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d, fd=%d",
  701. idx, cmd->fd);
  702. rc = -ENOMEM;
  703. goto slot_fail;
  704. }
  705. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  706. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  707. rc = cam_mem_util_map_hw_va(cmd->flags,
  708. cmd->mmu_hdls,
  709. cmd->num_hdl,
  710. cmd->fd,
  711. &hw_vaddr,
  712. &len,
  713. CAM_SMMU_REGION_IO,
  714. is_internal);
  715. if (rc) {
  716. CAM_ERR(CAM_MEM,
  717. "Failed in map_hw_va, flags=0x%x, fd=%d, len=%llu, region=%d, num_hdl=%d, rc=%d",
  718. cmd->flags, cmd->fd, len,
  719. CAM_SMMU_REGION_IO, cmd->num_hdl, rc);
  720. if (rc == -EALREADY) {
  721. if ((size_t)dmabuf->size != len) {
  722. rc = -EBADR;
  723. cam_mem_mgr_print_tbl();
  724. }
  725. }
  726. goto map_fail;
  727. }
  728. }
  729. mutex_lock(&tbl.bufq[idx].q_lock);
  730. tbl.bufq[idx].fd = cmd->fd;
  731. tbl.bufq[idx].dma_buf = NULL;
  732. tbl.bufq[idx].flags = cmd->flags;
  733. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, cmd->fd);
  734. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  735. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  736. tbl.bufq[idx].kmdvaddr = 0;
  737. if (cmd->num_hdl > 0)
  738. tbl.bufq[idx].vaddr = hw_vaddr;
  739. else
  740. tbl.bufq[idx].vaddr = 0;
  741. tbl.bufq[idx].dma_buf = dmabuf;
  742. tbl.bufq[idx].len = len;
  743. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  744. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  745. sizeof(int32_t) * cmd->num_hdl);
  746. tbl.bufq[idx].is_imported = true;
  747. tbl.bufq[idx].is_internal = is_internal;
  748. mutex_unlock(&tbl.bufq[idx].q_lock);
  749. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  750. cmd->out.vaddr = 0;
  751. cmd->out.size = (uint32_t)len;
  752. CAM_DBG(CAM_MEM,
  753. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu",
  754. cmd->fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  755. tbl.bufq[idx].len);
  756. return rc;
  757. map_fail:
  758. cam_mem_put_slot(idx);
  759. slot_fail:
  760. dma_buf_put(dmabuf);
  761. return rc;
  762. }
  763. static int cam_mem_util_unmap_hw_va(int32_t idx,
  764. enum cam_smmu_region_id region,
  765. enum cam_smmu_mapping_client client)
  766. {
  767. int i;
  768. uint32_t flags;
  769. int32_t *mmu_hdls;
  770. int num_hdls;
  771. int fd;
  772. int rc = 0;
  773. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  774. CAM_ERR(CAM_MEM, "Incorrect index");
  775. return -EINVAL;
  776. }
  777. flags = tbl.bufq[idx].flags;
  778. mmu_hdls = tbl.bufq[idx].hdls;
  779. num_hdls = tbl.bufq[idx].num_hdl;
  780. fd = tbl.bufq[idx].fd;
  781. CAM_DBG(CAM_MEM,
  782. "unmap_hw_va : idx=%d, fd=%x, flags=0x%x, num_hdls=%d, client=%d",
  783. idx, fd, flags, num_hdls, client);
  784. if (flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  785. for (i = 0; i < num_hdls; i++) {
  786. rc = cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd);
  787. if (rc < 0) {
  788. CAM_ERR(CAM_MEM,
  789. "Failed in secure unmap, i=%d, fd=%d, mmu_hdl=%d, rc=%d",
  790. i, fd, mmu_hdls[i], rc);
  791. goto unmap_end;
  792. }
  793. }
  794. } else {
  795. for (i = 0; i < num_hdls; i++) {
  796. if (client == CAM_SMMU_MAPPING_USER) {
  797. rc = cam_smmu_unmap_user_iova(mmu_hdls[i],
  798. fd, region);
  799. } else if (client == CAM_SMMU_MAPPING_KERNEL) {
  800. rc = cam_smmu_unmap_kernel_iova(mmu_hdls[i],
  801. tbl.bufq[idx].dma_buf, region);
  802. } else {
  803. CAM_ERR(CAM_MEM,
  804. "invalid caller for unmapping : %d",
  805. client);
  806. rc = -EINVAL;
  807. }
  808. if (rc < 0) {
  809. CAM_ERR(CAM_MEM,
  810. "Failed in unmap, i=%d, fd=%d, mmu_hdl=%d, region=%d, rc=%d",
  811. i, fd, mmu_hdls[i], region, rc);
  812. goto unmap_end;
  813. }
  814. }
  815. }
  816. return rc;
  817. unmap_end:
  818. CAM_ERR(CAM_MEM, "unmapping failed");
  819. return rc;
  820. }
  821. static void cam_mem_mgr_unmap_active_buf(int idx)
  822. {
  823. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  824. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  825. region = CAM_SMMU_REGION_SHARED;
  826. else if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  827. region = CAM_SMMU_REGION_IO;
  828. cam_mem_util_unmap_hw_va(idx, region, CAM_SMMU_MAPPING_USER);
  829. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS)
  830. cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf,
  831. tbl.bufq[idx].kmdvaddr);
  832. }
  833. static int cam_mem_mgr_cleanup_table(void)
  834. {
  835. int i;
  836. mutex_lock(&tbl.m_lock);
  837. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  838. if (!tbl.bufq[i].active) {
  839. CAM_DBG(CAM_MEM,
  840. "Buffer inactive at idx=%d, continuing", i);
  841. continue;
  842. } else {
  843. CAM_DBG(CAM_MEM,
  844. "Active buffer at idx=%d, possible leak needs unmapping",
  845. i);
  846. cam_mem_mgr_unmap_active_buf(i);
  847. }
  848. mutex_lock(&tbl.bufq[i].q_lock);
  849. if (tbl.bufq[i].dma_buf) {
  850. dma_buf_put(tbl.bufq[i].dma_buf);
  851. tbl.bufq[i].dma_buf = NULL;
  852. }
  853. tbl.bufq[i].fd = -1;
  854. tbl.bufq[i].flags = 0;
  855. tbl.bufq[i].buf_handle = -1;
  856. tbl.bufq[i].vaddr = 0;
  857. tbl.bufq[i].len = 0;
  858. memset(tbl.bufq[i].hdls, 0,
  859. sizeof(int32_t) * tbl.bufq[i].num_hdl);
  860. tbl.bufq[i].num_hdl = 0;
  861. tbl.bufq[i].dma_buf = NULL;
  862. tbl.bufq[i].active = false;
  863. tbl.bufq[i].is_internal = false;
  864. mutex_unlock(&tbl.bufq[i].q_lock);
  865. mutex_destroy(&tbl.bufq[i].q_lock);
  866. }
  867. bitmap_zero(tbl.bitmap, tbl.bits);
  868. /* We need to reserve slot 0 because 0 is invalid */
  869. set_bit(0, tbl.bitmap);
  870. mutex_unlock(&tbl.m_lock);
  871. return 0;
  872. }
  873. void cam_mem_mgr_deinit(void)
  874. {
  875. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_UNINITIALIZED);
  876. cam_mem_mgr_cleanup_table();
  877. debugfs_remove_recursive(tbl.dentry);
  878. mutex_lock(&tbl.m_lock);
  879. bitmap_zero(tbl.bitmap, tbl.bits);
  880. kfree(tbl.bitmap);
  881. tbl.bitmap = NULL;
  882. tbl.dbg_buf_idx = -1;
  883. mutex_unlock(&tbl.m_lock);
  884. mutex_destroy(&tbl.m_lock);
  885. }
  886. static int cam_mem_util_unmap(int32_t idx,
  887. enum cam_smmu_mapping_client client)
  888. {
  889. int rc = 0;
  890. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  891. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  892. CAM_ERR(CAM_MEM, "Incorrect index");
  893. return -EINVAL;
  894. }
  895. CAM_DBG(CAM_MEM, "Flags = %X idx %d", tbl.bufq[idx].flags, idx);
  896. mutex_lock(&tbl.m_lock);
  897. if ((!tbl.bufq[idx].active) &&
  898. (tbl.bufq[idx].vaddr) == 0) {
  899. CAM_WARN(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  900. idx);
  901. mutex_unlock(&tbl.m_lock);
  902. return 0;
  903. }
  904. /* Deactivate the buffer queue to prevent multiple unmap */
  905. mutex_lock(&tbl.bufq[idx].q_lock);
  906. tbl.bufq[idx].active = false;
  907. tbl.bufq[idx].vaddr = 0;
  908. mutex_unlock(&tbl.bufq[idx].q_lock);
  909. mutex_unlock(&tbl.m_lock);
  910. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS) {
  911. if (tbl.bufq[idx].dma_buf && tbl.bufq[idx].kmdvaddr) {
  912. rc = cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf,
  913. tbl.bufq[idx].kmdvaddr);
  914. if (rc)
  915. CAM_ERR(CAM_MEM,
  916. "Failed, dmabuf=%pK, kmdvaddr=%pK",
  917. tbl.bufq[idx].dma_buf,
  918. (void *) tbl.bufq[idx].kmdvaddr);
  919. }
  920. }
  921. /* SHARED flag gets precedence, all other flags after it */
  922. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  923. region = CAM_SMMU_REGION_SHARED;
  924. } else {
  925. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  926. region = CAM_SMMU_REGION_IO;
  927. }
  928. if ((tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  929. (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  930. (tbl.bufq[idx].flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  931. if (cam_mem_util_unmap_hw_va(idx, region, client))
  932. CAM_ERR(CAM_MEM, "Failed, dmabuf=%pK",
  933. tbl.bufq[idx].dma_buf);
  934. if (client == CAM_SMMU_MAPPING_KERNEL)
  935. tbl.bufq[idx].dma_buf = NULL;
  936. }
  937. mutex_lock(&tbl.m_lock);
  938. mutex_lock(&tbl.bufq[idx].q_lock);
  939. tbl.bufq[idx].flags = 0;
  940. tbl.bufq[idx].buf_handle = -1;
  941. memset(tbl.bufq[idx].hdls, 0,
  942. sizeof(int32_t) * CAM_MEM_MMU_MAX_HANDLE);
  943. CAM_DBG(CAM_MEM,
  944. "Ion buf at idx = %d freeing fd = %d, imported %d, dma_buf %pK",
  945. idx, tbl.bufq[idx].fd,
  946. tbl.bufq[idx].is_imported,
  947. tbl.bufq[idx].dma_buf);
  948. if (tbl.bufq[idx].dma_buf)
  949. dma_buf_put(tbl.bufq[idx].dma_buf);
  950. tbl.bufq[idx].fd = -1;
  951. tbl.bufq[idx].dma_buf = NULL;
  952. tbl.bufq[idx].is_imported = false;
  953. tbl.bufq[idx].is_internal = false;
  954. tbl.bufq[idx].len = 0;
  955. tbl.bufq[idx].num_hdl = 0;
  956. memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64));
  957. mutex_unlock(&tbl.bufq[idx].q_lock);
  958. mutex_destroy(&tbl.bufq[idx].q_lock);
  959. clear_bit(idx, tbl.bitmap);
  960. mutex_unlock(&tbl.m_lock);
  961. return rc;
  962. }
  963. int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd)
  964. {
  965. int idx;
  966. int rc;
  967. if (!atomic_read(&cam_mem_mgr_state)) {
  968. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  969. return -EINVAL;
  970. }
  971. if (!cmd) {
  972. CAM_ERR(CAM_MEM, "Invalid argument");
  973. return -EINVAL;
  974. }
  975. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  976. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  977. CAM_ERR(CAM_MEM, "Incorrect index %d extracted from mem handle",
  978. idx);
  979. return -EINVAL;
  980. }
  981. if (!tbl.bufq[idx].active) {
  982. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  983. return -EINVAL;
  984. }
  985. if (tbl.bufq[idx].buf_handle != cmd->buf_handle) {
  986. CAM_ERR(CAM_MEM,
  987. "Released buf handle %d not matching within table %d, idx=%d",
  988. cmd->buf_handle, tbl.bufq[idx].buf_handle, idx);
  989. return -EINVAL;
  990. }
  991. CAM_DBG(CAM_MEM, "Releasing hdl = %x, idx = %d", cmd->buf_handle, idx);
  992. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_USER);
  993. return rc;
  994. }
  995. int cam_mem_mgr_request_mem(struct cam_mem_mgr_request_desc *inp,
  996. struct cam_mem_mgr_memory_desc *out)
  997. {
  998. struct dma_buf *buf = NULL;
  999. int ion_fd = -1;
  1000. int rc = 0;
  1001. uint32_t heap_id;
  1002. int32_t ion_flag = 0;
  1003. uintptr_t kvaddr;
  1004. dma_addr_t iova = 0;
  1005. size_t request_len = 0;
  1006. uint32_t mem_handle;
  1007. int32_t idx;
  1008. int32_t smmu_hdl = 0;
  1009. int32_t num_hdl = 0;
  1010. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1011. if (!atomic_read(&cam_mem_mgr_state)) {
  1012. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1013. return -EINVAL;
  1014. }
  1015. if (!inp || !out) {
  1016. CAM_ERR(CAM_MEM, "Invalid params");
  1017. return -EINVAL;
  1018. }
  1019. if (!(inp->flags & CAM_MEM_FLAG_HW_READ_WRITE ||
  1020. inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS ||
  1021. inp->flags & CAM_MEM_FLAG_CACHE)) {
  1022. CAM_ERR(CAM_MEM, "Invalid flags for request mem");
  1023. return -EINVAL;
  1024. }
  1025. if (inp->flags & CAM_MEM_FLAG_CACHE)
  1026. ion_flag |= ION_FLAG_CACHED;
  1027. else
  1028. ion_flag &= ~ION_FLAG_CACHED;
  1029. heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) |
  1030. ION_HEAP(ION_CAMERA_HEAP_ID);
  1031. rc = cam_mem_util_get_dma_buf(inp->size,
  1032. heap_id,
  1033. ion_flag,
  1034. &buf);
  1035. if (rc) {
  1036. CAM_ERR(CAM_MEM, "ION alloc failed for shared buffer");
  1037. goto ion_fail;
  1038. } else {
  1039. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1040. }
  1041. /*
  1042. * we are mapping kva always here,
  1043. * update flags so that we do unmap properly
  1044. */
  1045. inp->flags |= CAM_MEM_FLAG_KMD_ACCESS;
  1046. rc = cam_mem_util_map_cpu_va(buf, &kvaddr, &request_len);
  1047. if (rc) {
  1048. CAM_ERR(CAM_MEM, "Failed to get kernel vaddr");
  1049. goto map_fail;
  1050. }
  1051. if (!inp->smmu_hdl) {
  1052. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1053. rc = -EINVAL;
  1054. goto smmu_fail;
  1055. }
  1056. /* SHARED flag gets precedence, all other flags after it */
  1057. if (inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  1058. region = CAM_SMMU_REGION_SHARED;
  1059. } else {
  1060. if (inp->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1061. region = CAM_SMMU_REGION_IO;
  1062. }
  1063. rc = cam_smmu_map_kernel_iova(inp->smmu_hdl,
  1064. buf,
  1065. CAM_SMMU_MAP_RW,
  1066. &iova,
  1067. &request_len,
  1068. region);
  1069. if (rc < 0) {
  1070. CAM_ERR(CAM_MEM, "SMMU mapping failed");
  1071. goto smmu_fail;
  1072. }
  1073. smmu_hdl = inp->smmu_hdl;
  1074. num_hdl = 1;
  1075. idx = cam_mem_get_slot();
  1076. if (idx < 0) {
  1077. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  1078. rc = -ENOMEM;
  1079. goto slot_fail;
  1080. }
  1081. mutex_lock(&tbl.bufq[idx].q_lock);
  1082. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1083. tbl.bufq[idx].dma_buf = buf;
  1084. tbl.bufq[idx].fd = -1;
  1085. tbl.bufq[idx].flags = inp->flags;
  1086. tbl.bufq[idx].buf_handle = mem_handle;
  1087. tbl.bufq[idx].kmdvaddr = kvaddr;
  1088. tbl.bufq[idx].vaddr = iova;
  1089. tbl.bufq[idx].len = inp->size;
  1090. tbl.bufq[idx].num_hdl = num_hdl;
  1091. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1092. sizeof(int32_t));
  1093. tbl.bufq[idx].is_imported = false;
  1094. mutex_unlock(&tbl.bufq[idx].q_lock);
  1095. out->kva = kvaddr;
  1096. out->iova = (uint32_t)iova;
  1097. out->smmu_hdl = smmu_hdl;
  1098. out->mem_handle = mem_handle;
  1099. out->len = inp->size;
  1100. out->region = region;
  1101. return rc;
  1102. slot_fail:
  1103. cam_smmu_unmap_kernel_iova(inp->smmu_hdl,
  1104. buf, region);
  1105. smmu_fail:
  1106. cam_mem_util_unmap_cpu_va(buf, kvaddr);
  1107. map_fail:
  1108. dma_buf_put(buf);
  1109. ion_fail:
  1110. return rc;
  1111. }
  1112. EXPORT_SYMBOL(cam_mem_mgr_request_mem);
  1113. int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp)
  1114. {
  1115. int32_t idx;
  1116. int rc;
  1117. if (!atomic_read(&cam_mem_mgr_state)) {
  1118. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1119. return -EINVAL;
  1120. }
  1121. if (!inp) {
  1122. CAM_ERR(CAM_MEM, "Invalid argument");
  1123. return -EINVAL;
  1124. }
  1125. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1126. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1127. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1128. return -EINVAL;
  1129. }
  1130. if (!tbl.bufq[idx].active) {
  1131. if (tbl.bufq[idx].vaddr == 0) {
  1132. CAM_ERR(CAM_MEM, "buffer is released already");
  1133. return 0;
  1134. }
  1135. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1136. return -EINVAL;
  1137. }
  1138. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1139. CAM_ERR(CAM_MEM,
  1140. "Released buf handle not matching within table");
  1141. return -EINVAL;
  1142. }
  1143. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1144. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1145. return rc;
  1146. }
  1147. EXPORT_SYMBOL(cam_mem_mgr_release_mem);
  1148. int cam_mem_mgr_reserve_memory_region(struct cam_mem_mgr_request_desc *inp,
  1149. enum cam_smmu_region_id region,
  1150. struct cam_mem_mgr_memory_desc *out)
  1151. {
  1152. struct dma_buf *buf = NULL;
  1153. int rc = 0;
  1154. int ion_fd = -1;
  1155. uint32_t heap_id;
  1156. dma_addr_t iova = 0;
  1157. size_t request_len = 0;
  1158. uint32_t mem_handle;
  1159. int32_t idx;
  1160. int32_t smmu_hdl = 0;
  1161. int32_t num_hdl = 0;
  1162. if (!atomic_read(&cam_mem_mgr_state)) {
  1163. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1164. return -EINVAL;
  1165. }
  1166. if (!inp || !out) {
  1167. CAM_ERR(CAM_MEM, "Invalid param(s)");
  1168. return -EINVAL;
  1169. }
  1170. if (!inp->smmu_hdl) {
  1171. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1172. return -EINVAL;
  1173. }
  1174. if (region != CAM_SMMU_REGION_SECHEAP) {
  1175. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1176. return -EINVAL;
  1177. }
  1178. heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) |
  1179. ION_HEAP(ION_CAMERA_HEAP_ID);
  1180. rc = cam_mem_util_get_dma_buf(inp->size,
  1181. heap_id,
  1182. 0,
  1183. &buf);
  1184. if (rc) {
  1185. CAM_ERR(CAM_MEM, "ION alloc failed for sec heap buffer");
  1186. goto ion_fail;
  1187. } else {
  1188. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1189. }
  1190. rc = cam_smmu_reserve_sec_heap(inp->smmu_hdl,
  1191. buf,
  1192. &iova,
  1193. &request_len);
  1194. if (rc) {
  1195. CAM_ERR(CAM_MEM, "Reserving secondary heap failed");
  1196. goto smmu_fail;
  1197. }
  1198. smmu_hdl = inp->smmu_hdl;
  1199. num_hdl = 1;
  1200. idx = cam_mem_get_slot();
  1201. if (idx < 0) {
  1202. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  1203. rc = -ENOMEM;
  1204. goto slot_fail;
  1205. }
  1206. mutex_lock(&tbl.bufq[idx].q_lock);
  1207. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1208. tbl.bufq[idx].fd = -1;
  1209. tbl.bufq[idx].dma_buf = buf;
  1210. tbl.bufq[idx].flags = inp->flags;
  1211. tbl.bufq[idx].buf_handle = mem_handle;
  1212. tbl.bufq[idx].kmdvaddr = 0;
  1213. tbl.bufq[idx].vaddr = iova;
  1214. tbl.bufq[idx].len = request_len;
  1215. tbl.bufq[idx].num_hdl = num_hdl;
  1216. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1217. sizeof(int32_t));
  1218. tbl.bufq[idx].is_imported = false;
  1219. mutex_unlock(&tbl.bufq[idx].q_lock);
  1220. out->kva = 0;
  1221. out->iova = (uint32_t)iova;
  1222. out->smmu_hdl = smmu_hdl;
  1223. out->mem_handle = mem_handle;
  1224. out->len = request_len;
  1225. out->region = region;
  1226. return rc;
  1227. slot_fail:
  1228. cam_smmu_release_sec_heap(smmu_hdl);
  1229. smmu_fail:
  1230. dma_buf_put(buf);
  1231. ion_fail:
  1232. return rc;
  1233. }
  1234. EXPORT_SYMBOL(cam_mem_mgr_reserve_memory_region);
  1235. int cam_mem_mgr_free_memory_region(struct cam_mem_mgr_memory_desc *inp)
  1236. {
  1237. int32_t idx;
  1238. int rc;
  1239. int32_t smmu_hdl;
  1240. if (!atomic_read(&cam_mem_mgr_state)) {
  1241. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1242. return -EINVAL;
  1243. }
  1244. if (!inp) {
  1245. CAM_ERR(CAM_MEM, "Invalid argument");
  1246. return -EINVAL;
  1247. }
  1248. if (inp->region != CAM_SMMU_REGION_SECHEAP) {
  1249. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1250. return -EINVAL;
  1251. }
  1252. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1253. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1254. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1255. return -EINVAL;
  1256. }
  1257. if (!tbl.bufq[idx].active) {
  1258. if (tbl.bufq[idx].vaddr == 0) {
  1259. CAM_ERR(CAM_MEM, "buffer is released already");
  1260. return 0;
  1261. }
  1262. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1263. return -EINVAL;
  1264. }
  1265. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1266. CAM_ERR(CAM_MEM,
  1267. "Released buf handle not matching within table");
  1268. return -EINVAL;
  1269. }
  1270. if (tbl.bufq[idx].num_hdl != 1) {
  1271. CAM_ERR(CAM_MEM,
  1272. "Sec heap region should have only one smmu hdl");
  1273. return -ENODEV;
  1274. }
  1275. memcpy(&smmu_hdl, tbl.bufq[idx].hdls,
  1276. sizeof(int32_t));
  1277. if (inp->smmu_hdl != smmu_hdl) {
  1278. CAM_ERR(CAM_MEM,
  1279. "Passed SMMU handle doesn't match with internal hdl");
  1280. return -ENODEV;
  1281. }
  1282. rc = cam_smmu_release_sec_heap(inp->smmu_hdl);
  1283. if (rc) {
  1284. CAM_ERR(CAM_MEM,
  1285. "Sec heap region release failed");
  1286. return -ENODEV;
  1287. }
  1288. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1289. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1290. if (rc)
  1291. CAM_ERR(CAM_MEM, "unmapping secondary heap failed");
  1292. return rc;
  1293. }
  1294. EXPORT_SYMBOL(cam_mem_mgr_free_memory_region);