dp_power.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/pm_runtime.h>
  7. #include "dp_power.h"
  8. #include "dp_catalog.h"
  9. #include "dp_debug.h"
  10. #include "dp_pll.h"
  11. #define DP_CLIENT_NAME_SIZE 20
  12. struct dp_power_private {
  13. struct dp_parser *parser;
  14. struct dp_pll *pll;
  15. struct platform_device *pdev;
  16. struct clk *pixel_clk_rcg;
  17. struct clk *pixel_parent;
  18. struct clk *pixel1_clk_rcg;
  19. struct dp_power dp_power;
  20. bool core_clks_on;
  21. bool link_clks_on;
  22. bool strm0_clks_on;
  23. bool strm1_clks_on;
  24. };
  25. static int dp_power_regulator_init(struct dp_power_private *power)
  26. {
  27. int rc = 0, i = 0, j = 0;
  28. struct platform_device *pdev;
  29. struct dp_parser *parser;
  30. parser = power->parser;
  31. pdev = power->pdev;
  32. for (i = DP_CORE_PM; !rc && (i < DP_MAX_PM); i++) {
  33. rc = msm_dss_get_vreg(&pdev->dev,
  34. parser->mp[i].vreg_config,
  35. parser->mp[i].num_vreg, 1);
  36. if (rc) {
  37. DP_ERR("failed to init vregs for %s\n",
  38. dp_parser_pm_name(i));
  39. for (j = i - 1; j >= DP_CORE_PM; j--) {
  40. msm_dss_get_vreg(&pdev->dev,
  41. parser->mp[j].vreg_config,
  42. parser->mp[j].num_vreg, 0);
  43. }
  44. goto error;
  45. }
  46. }
  47. error:
  48. return rc;
  49. }
  50. static void dp_power_regulator_deinit(struct dp_power_private *power)
  51. {
  52. int rc = 0, i = 0;
  53. struct platform_device *pdev;
  54. struct dp_parser *parser;
  55. parser = power->parser;
  56. pdev = power->pdev;
  57. for (i = DP_CORE_PM; (i < DP_MAX_PM); i++) {
  58. rc = msm_dss_get_vreg(&pdev->dev,
  59. parser->mp[i].vreg_config,
  60. parser->mp[i].num_vreg, 0);
  61. if (rc)
  62. DP_ERR("failed to deinit vregs for %s\n",
  63. dp_parser_pm_name(i));
  64. }
  65. }
  66. static int dp_power_regulator_ctrl(struct dp_power_private *power, bool enable)
  67. {
  68. int rc = 0, i = 0, j = 0;
  69. struct dp_parser *parser;
  70. parser = power->parser;
  71. for (i = DP_CORE_PM; i < DP_MAX_PM; i++) {
  72. /*
  73. * The DP_PLL_PM regulator is controlled by dp_display based
  74. * on the link configuration.
  75. */
  76. if (i == DP_PLL_PM) {
  77. DP_DEBUG("skipping: '%s' vregs for %s\n",
  78. enable ? "enable" : "disable",
  79. dp_parser_pm_name(i));
  80. continue;
  81. }
  82. rc = msm_dss_enable_vreg(
  83. parser->mp[i].vreg_config,
  84. parser->mp[i].num_vreg, enable);
  85. if (rc) {
  86. DP_ERR("failed to '%s' vregs for %s\n",
  87. enable ? "enable" : "disable",
  88. dp_parser_pm_name(i));
  89. if (enable) {
  90. for (j = i-1; j >= DP_CORE_PM; j--) {
  91. msm_dss_enable_vreg(
  92. parser->mp[j].vreg_config,
  93. parser->mp[j].num_vreg, 0);
  94. }
  95. }
  96. goto error;
  97. }
  98. }
  99. error:
  100. return rc;
  101. }
  102. static int dp_power_pinctrl_set(struct dp_power_private *power, bool active)
  103. {
  104. int rc = -EFAULT;
  105. struct pinctrl_state *pin_state;
  106. struct dp_parser *parser;
  107. parser = power->parser;
  108. if (IS_ERR_OR_NULL(parser->pinctrl.pin))
  109. return 0;
  110. if (parser->no_aux_switch && parser->lphw_hpd) {
  111. pin_state = active ? parser->pinctrl.state_hpd_ctrl
  112. : parser->pinctrl.state_hpd_tlmm;
  113. if (!IS_ERR_OR_NULL(pin_state)) {
  114. rc = pinctrl_select_state(parser->pinctrl.pin,
  115. pin_state);
  116. if (rc) {
  117. DP_ERR("cannot direct hpd line to %s\n",
  118. active ? "ctrl" : "tlmm");
  119. return rc;
  120. }
  121. }
  122. }
  123. if (parser->no_aux_switch)
  124. return 0;
  125. pin_state = active ? parser->pinctrl.state_active
  126. : parser->pinctrl.state_suspend;
  127. if (!IS_ERR_OR_NULL(pin_state)) {
  128. rc = pinctrl_select_state(parser->pinctrl.pin,
  129. pin_state);
  130. if (rc)
  131. DP_ERR("can not set %s pins\n",
  132. active ? "dp_active"
  133. : "dp_sleep");
  134. } else {
  135. DP_ERR("invalid '%s' pinstate\n",
  136. active ? "dp_active"
  137. : "dp_sleep");
  138. }
  139. return rc;
  140. }
  141. static void dp_power_clk_put(struct dp_power_private *power)
  142. {
  143. enum dp_pm_type module;
  144. for (module = DP_CORE_PM; module < DP_MAX_PM; module++) {
  145. struct dss_module_power *pm = &power->parser->mp[module];
  146. if (!pm->num_clk)
  147. continue;
  148. msm_dss_mmrm_deregister(&power->pdev->dev, pm);
  149. msm_dss_put_clk(pm->clk_config, pm->num_clk);
  150. }
  151. }
  152. static int dp_power_clk_init(struct dp_power_private *power, bool enable)
  153. {
  154. int rc = 0;
  155. struct device *dev;
  156. enum dp_pm_type module;
  157. dev = &power->pdev->dev;
  158. if (enable) {
  159. for (module = DP_CORE_PM; module < DP_MAX_PM; module++) {
  160. struct dss_module_power *pm =
  161. &power->parser->mp[module];
  162. if (!pm->num_clk)
  163. continue;
  164. rc = msm_dss_get_clk(dev, pm->clk_config, pm->num_clk);
  165. if (rc) {
  166. DP_ERR("failed to get %s clk. err=%d\n",
  167. dp_parser_pm_name(module), rc);
  168. goto exit;
  169. }
  170. }
  171. power->pixel_clk_rcg = clk_get(dev, "pixel_clk_rcg");
  172. if (IS_ERR(power->pixel_clk_rcg)) {
  173. DP_ERR("Unable to get DP pixel clk RCG: %ld\n",
  174. PTR_ERR(power->pixel_clk_rcg));
  175. rc = PTR_ERR(power->pixel_clk_rcg);
  176. power->pixel_clk_rcg = NULL;
  177. goto err_pixel_clk_rcg;
  178. }
  179. power->pixel_parent = clk_get(dev, "pixel_parent");
  180. if (IS_ERR(power->pixel_parent)) {
  181. DP_ERR("Unable to get DP pixel RCG parent: %d\n",
  182. PTR_ERR(power->pixel_parent));
  183. rc = PTR_ERR(power->pixel_parent);
  184. power->pixel_parent = NULL;
  185. goto err_pixel_parent;
  186. }
  187. if (power->parser->has_mst) {
  188. power->pixel1_clk_rcg = clk_get(dev, "pixel1_clk_rcg");
  189. if (IS_ERR(power->pixel1_clk_rcg)) {
  190. DP_ERR("Unable to get DP pixel1 clk RCG: %d\n",
  191. PTR_ERR(power->pixel1_clk_rcg));
  192. rc = PTR_ERR(power->pixel1_clk_rcg);
  193. power->pixel1_clk_rcg = NULL;
  194. goto err_pixel1_clk_rcg;
  195. }
  196. }
  197. } else {
  198. if (power->pixel1_clk_rcg)
  199. clk_put(power->pixel1_clk_rcg);
  200. if (power->pixel_parent)
  201. clk_put(power->pixel_parent);
  202. if (power->pixel_clk_rcg)
  203. clk_put(power->pixel_clk_rcg);
  204. dp_power_clk_put(power);
  205. }
  206. return rc;
  207. err_pixel1_clk_rcg:
  208. clk_put(power->pixel_parent);
  209. err_pixel_parent:
  210. clk_put(power->pixel_clk_rcg);
  211. err_pixel_clk_rcg:
  212. dp_power_clk_put(power);
  213. exit:
  214. return rc;
  215. }
  216. static int dp_power_clk_set_rate(struct dp_power_private *power,
  217. enum dp_pm_type module, bool enable)
  218. {
  219. int rc = 0;
  220. struct dss_module_power *mp;
  221. if (!power) {
  222. DP_ERR("invalid power data\n");
  223. rc = -EINVAL;
  224. goto exit;
  225. }
  226. mp = &power->parser->mp[module];
  227. if (enable) {
  228. rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
  229. if (rc) {
  230. DP_ERR("failed to set clks rate.\n");
  231. goto exit;
  232. }
  233. rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, 1);
  234. if (rc) {
  235. DP_ERR("failed to enable clks\n");
  236. goto exit;
  237. }
  238. } else {
  239. rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, 0);
  240. if (rc) {
  241. DP_ERR("failed to disable clks\n");
  242. goto exit;
  243. }
  244. }
  245. exit:
  246. return rc;
  247. }
  248. static int dp_power_clk_enable(struct dp_power *dp_power,
  249. enum dp_pm_type pm_type, bool enable)
  250. {
  251. int rc = 0;
  252. struct dss_module_power *mp;
  253. struct dp_power_private *power;
  254. if (!dp_power) {
  255. DP_ERR("invalid power data\n");
  256. rc = -EINVAL;
  257. goto error;
  258. }
  259. power = container_of(dp_power, struct dp_power_private, dp_power);
  260. mp = &power->parser->mp[pm_type];
  261. if (pm_type >= DP_MAX_PM) {
  262. DP_ERR("unsupported power module: %s\n",
  263. dp_parser_pm_name(pm_type));
  264. return -EINVAL;
  265. }
  266. if (enable) {
  267. if (pm_type == DP_CORE_PM && power->core_clks_on) {
  268. DP_DEBUG("core clks already enabled\n");
  269. return 0;
  270. }
  271. if ((pm_type == DP_STREAM0_PM) && (power->strm0_clks_on)) {
  272. DP_DEBUG("strm0 clks already enabled\n");
  273. return 0;
  274. }
  275. if ((pm_type == DP_STREAM1_PM) && (power->strm1_clks_on)) {
  276. DP_DEBUG("strm1 clks already enabled\n");
  277. return 0;
  278. }
  279. if ((pm_type == DP_CTRL_PM) && (!power->core_clks_on)) {
  280. DP_DEBUG("Need to enable core clks before link clks\n");
  281. rc = dp_power_clk_set_rate(power, pm_type, enable);
  282. if (rc) {
  283. DP_ERR("failed to enable clks: %s. err=%d\n",
  284. dp_parser_pm_name(DP_CORE_PM), rc);
  285. goto error;
  286. } else {
  287. power->core_clks_on = true;
  288. }
  289. }
  290. if (pm_type == DP_LINK_PM && power->link_clks_on) {
  291. DP_DEBUG("links clks already enabled\n");
  292. return 0;
  293. }
  294. }
  295. rc = dp_power_clk_set_rate(power, pm_type, enable);
  296. if (rc) {
  297. DP_ERR("failed to '%s' clks for: %s. err=%d\n",
  298. enable ? "enable" : "disable",
  299. dp_parser_pm_name(pm_type), rc);
  300. goto error;
  301. }
  302. if (pm_type == DP_CORE_PM)
  303. power->core_clks_on = enable;
  304. else if (pm_type == DP_STREAM0_PM)
  305. power->strm0_clks_on = enable;
  306. else if (pm_type == DP_STREAM1_PM)
  307. power->strm1_clks_on = enable;
  308. else if (pm_type == DP_LINK_PM)
  309. power->link_clks_on = enable;
  310. /*
  311. * This log is printed only when user connects or disconnects
  312. * a DP cable. As this is a user-action and not a frequent
  313. * usecase, it is not going to flood the kernel logs. Also,
  314. * helpful in debugging the NOC issues.
  315. */
  316. DP_INFO("core:%s link:%s strm0:%s strm1:%s\n",
  317. power->core_clks_on ? "on" : "off",
  318. power->link_clks_on ? "on" : "off",
  319. power->strm0_clks_on ? "on" : "off",
  320. power->strm1_clks_on ? "on" : "off");
  321. error:
  322. return rc;
  323. }
  324. static int dp_power_request_gpios(struct dp_power_private *power)
  325. {
  326. int rc = 0, i;
  327. struct device *dev;
  328. struct dss_module_power *mp;
  329. static const char * const gpio_names[] = {
  330. "aux_enable", "aux_sel", "usbplug_cc",
  331. };
  332. if (!power) {
  333. DP_ERR("invalid power data\n");
  334. return -EINVAL;
  335. }
  336. dev = &power->pdev->dev;
  337. mp = &power->parser->mp[DP_CORE_PM];
  338. for (i = 0; i < ARRAY_SIZE(gpio_names); i++) {
  339. unsigned int gpio = mp->gpio_config[i].gpio;
  340. if (gpio_is_valid(gpio)) {
  341. rc = gpio_request(gpio, gpio_names[i]);
  342. if (rc) {
  343. DP_ERR("request %s gpio failed, rc=%d\n",
  344. gpio_names[i], rc);
  345. goto error;
  346. }
  347. }
  348. }
  349. return 0;
  350. error:
  351. for (i = 0; i < ARRAY_SIZE(gpio_names); i++) {
  352. unsigned int gpio = mp->gpio_config[i].gpio;
  353. if (gpio_is_valid(gpio))
  354. gpio_free(gpio);
  355. }
  356. return rc;
  357. }
  358. static bool dp_power_find_gpio(const char *gpio1, const char *gpio2)
  359. {
  360. return !!strnstr(gpio1, gpio2, strlen(gpio1));
  361. }
  362. static void dp_power_set_gpio(struct dp_power_private *power, bool flip)
  363. {
  364. int i;
  365. struct dss_module_power *mp = &power->parser->mp[DP_CORE_PM];
  366. struct dss_gpio *config = mp->gpio_config;
  367. for (i = 0; i < mp->num_gpio; i++) {
  368. if (dp_power_find_gpio(config->gpio_name, "aux-sel"))
  369. config->value = flip;
  370. if (gpio_is_valid(config->gpio)) {
  371. DP_DEBUG("gpio %s, value %d\n", config->gpio_name,
  372. config->value);
  373. if (dp_power_find_gpio(config->gpio_name, "aux-en") ||
  374. dp_power_find_gpio(config->gpio_name, "aux-sel"))
  375. gpio_direction_output(config->gpio,
  376. config->value);
  377. else
  378. gpio_set_value(config->gpio, config->value);
  379. }
  380. config++;
  381. }
  382. }
  383. static int dp_power_config_gpios(struct dp_power_private *power, bool flip,
  384. bool enable)
  385. {
  386. int rc = 0, i;
  387. struct dss_module_power *mp;
  388. struct dss_gpio *config;
  389. if (power->parser->no_aux_switch)
  390. return 0;
  391. mp = &power->parser->mp[DP_CORE_PM];
  392. config = mp->gpio_config;
  393. if (enable) {
  394. rc = dp_power_request_gpios(power);
  395. if (rc) {
  396. DP_ERR("gpio request failed\n");
  397. return rc;
  398. }
  399. dp_power_set_gpio(power, flip);
  400. } else {
  401. for (i = 0; i < mp->num_gpio; i++) {
  402. if (gpio_is_valid(config[i].gpio)) {
  403. gpio_set_value(config[i].gpio, 0);
  404. gpio_free(config[i].gpio);
  405. }
  406. }
  407. }
  408. return 0;
  409. }
  410. static int dp_power_mmrm_init(struct dp_power *dp_power, struct sde_power_handle *phandle, void *dp,
  411. int (*dp_display_mmrm_callback)(struct mmrm_client_notifier_data *notifier_data))
  412. {
  413. int rc = 0;
  414. enum dp_pm_type module;
  415. struct dp_power_private *power = container_of(dp_power, struct dp_power_private, dp_power);
  416. struct device *dev = &power->pdev->dev;
  417. for (module = DP_CORE_PM; module < DP_MAX_PM; module++) {
  418. struct dss_module_power *pm = &power->parser->mp[module];
  419. if (!pm->num_clk)
  420. continue;
  421. rc = msm_dss_mmrm_register(dev, pm, dp_display_mmrm_callback,
  422. dp, &phandle->mmrm_enable);
  423. if (rc)
  424. DP_ERR("mmrm register failed rc=%d\n", rc);
  425. }
  426. return rc;
  427. }
  428. static int dp_power_client_init(struct dp_power *dp_power,
  429. struct sde_power_handle *phandle, struct drm_device *drm_dev)
  430. {
  431. int rc = 0;
  432. struct dp_power_private *power;
  433. if (!drm_dev) {
  434. DP_ERR("invalid drm_dev\n");
  435. return -EINVAL;
  436. }
  437. power = container_of(dp_power, struct dp_power_private, dp_power);
  438. rc = dp_power_regulator_init(power);
  439. if (rc) {
  440. DP_ERR("failed to init regulators\n");
  441. goto error_power;
  442. }
  443. rc = dp_power_clk_init(power, true);
  444. if (rc) {
  445. DP_ERR("failed to init clocks\n");
  446. goto error_clk;
  447. }
  448. dp_power->phandle = phandle;
  449. dp_power->drm_dev = drm_dev;
  450. return 0;
  451. error_clk:
  452. dp_power_regulator_deinit(power);
  453. error_power:
  454. return rc;
  455. }
  456. static void dp_power_client_deinit(struct dp_power *dp_power)
  457. {
  458. struct dp_power_private *power;
  459. if (!dp_power) {
  460. DP_ERR("invalid power data\n");
  461. return;
  462. }
  463. power = container_of(dp_power, struct dp_power_private, dp_power);
  464. dp_power_clk_init(power, false);
  465. dp_power_regulator_deinit(power);
  466. }
  467. static int dp_power_set_pixel_clk_parent(struct dp_power *dp_power, u32 strm_id)
  468. {
  469. int rc = 0;
  470. struct dp_power_private *power;
  471. if (!dp_power || strm_id >= DP_STREAM_MAX) {
  472. DP_ERR("invalid power data. stream %d\n", strm_id);
  473. rc = -EINVAL;
  474. goto exit;
  475. }
  476. power = container_of(dp_power, struct dp_power_private, dp_power);
  477. if (strm_id == DP_STREAM_0) {
  478. if (power->pixel_clk_rcg && power->pixel_parent)
  479. rc = clk_set_parent(power->pixel_clk_rcg,
  480. power->pixel_parent);
  481. else
  482. DP_WARN("skipped for strm_id=%d\n", strm_id);
  483. } else if (strm_id == DP_STREAM_1) {
  484. if (power->pixel1_clk_rcg && power->pixel_parent)
  485. rc = clk_set_parent(power->pixel1_clk_rcg,
  486. power->pixel_parent);
  487. else
  488. DP_WARN("skipped for strm_id=%d\n", strm_id);
  489. }
  490. if (rc)
  491. DP_ERR("failed. strm_id=%d, rc=%d\n", strm_id, rc);
  492. exit:
  493. return rc;
  494. }
  495. static u64 dp_power_clk_get_rate(struct dp_power *dp_power, char *clk_name)
  496. {
  497. size_t i;
  498. enum dp_pm_type j;
  499. struct dss_module_power *mp;
  500. struct dp_power_private *power;
  501. bool clk_found = false;
  502. u64 rate = 0;
  503. if (!clk_name) {
  504. DP_ERR("invalid pointer for clk_name\n");
  505. return 0;
  506. }
  507. power = container_of(dp_power, struct dp_power_private, dp_power);
  508. mp = &dp_power->phandle->mp;
  509. for (i = 0; i < mp->num_clk; i++) {
  510. if (!strcmp(mp->clk_config[i].clk_name, clk_name)) {
  511. rate = clk_get_rate(mp->clk_config[i].clk);
  512. clk_found = true;
  513. break;
  514. }
  515. }
  516. for (j = DP_CORE_PM; j < DP_MAX_PM && !clk_found; j++) {
  517. mp = &power->parser->mp[j];
  518. for (i = 0; i < mp->num_clk; i++) {
  519. if (!strcmp(mp->clk_config[i].clk_name, clk_name)) {
  520. rate = clk_get_rate(mp->clk_config[i].clk);
  521. clk_found = true;
  522. break;
  523. }
  524. }
  525. }
  526. return rate;
  527. }
  528. static int dp_power_init(struct dp_power *dp_power, bool flip)
  529. {
  530. int rc = 0;
  531. struct dp_power_private *power;
  532. if (!dp_power) {
  533. DP_ERR("invalid power data\n");
  534. rc = -EINVAL;
  535. goto exit;
  536. }
  537. power = container_of(dp_power, struct dp_power_private, dp_power);
  538. rc = dp_power_regulator_ctrl(power, true);
  539. if (rc) {
  540. DP_ERR("failed to enable regulators\n");
  541. goto exit;
  542. }
  543. rc = dp_power_pinctrl_set(power, true);
  544. if (rc) {
  545. DP_ERR("failed to set pinctrl state\n");
  546. goto err_pinctrl;
  547. }
  548. rc = dp_power_config_gpios(power, flip, true);
  549. if (rc) {
  550. DP_ERR("failed to enable gpios\n");
  551. goto err_gpio;
  552. }
  553. rc = pm_runtime_get_sync(dp_power->drm_dev->dev);
  554. if (rc < 0) {
  555. DP_ERR("Power resource enable failed\n");
  556. goto err_sde_power;
  557. }
  558. rc = dp_power_clk_enable(dp_power, DP_CORE_PM, true);
  559. if (rc) {
  560. DP_ERR("failed to enable DP core clocks\n");
  561. goto err_clk;
  562. }
  563. return 0;
  564. err_clk:
  565. pm_runtime_put_sync(dp_power->drm_dev->dev);
  566. err_sde_power:
  567. dp_power_config_gpios(power, flip, false);
  568. err_gpio:
  569. dp_power_pinctrl_set(power, false);
  570. err_pinctrl:
  571. dp_power_regulator_ctrl(power, false);
  572. exit:
  573. return rc;
  574. }
  575. static int dp_power_deinit(struct dp_power *dp_power)
  576. {
  577. int rc = 0;
  578. struct dp_power_private *power;
  579. if (!dp_power) {
  580. DP_ERR("invalid power data\n");
  581. rc = -EINVAL;
  582. goto exit;
  583. }
  584. power = container_of(dp_power, struct dp_power_private, dp_power);
  585. if (power->link_clks_on)
  586. dp_power_clk_enable(dp_power, DP_LINK_PM, false);
  587. dp_power_clk_enable(dp_power, DP_CORE_PM, false);
  588. pm_runtime_put_sync(dp_power->drm_dev->dev);
  589. dp_power_config_gpios(power, false, false);
  590. dp_power_pinctrl_set(power, false);
  591. dp_power_regulator_ctrl(power, false);
  592. exit:
  593. return rc;
  594. }
  595. struct dp_power *dp_power_get(struct dp_parser *parser, struct dp_pll *pll)
  596. {
  597. int rc = 0;
  598. struct dp_power_private *power;
  599. struct dp_power *dp_power;
  600. if (!parser || !pll) {
  601. DP_ERR("invalid input\n");
  602. rc = -EINVAL;
  603. goto error;
  604. }
  605. power = kzalloc(sizeof(*power), GFP_KERNEL);
  606. if (!power) {
  607. rc = -ENOMEM;
  608. goto error;
  609. }
  610. power->parser = parser;
  611. power->pll = pll;
  612. power->pdev = parser->pdev;
  613. dp_power = &power->dp_power;
  614. dp_power->init = dp_power_init;
  615. dp_power->deinit = dp_power_deinit;
  616. dp_power->clk_enable = dp_power_clk_enable;
  617. dp_power->set_pixel_clk_parent = dp_power_set_pixel_clk_parent;
  618. dp_power->clk_get_rate = dp_power_clk_get_rate;
  619. dp_power->power_client_init = dp_power_client_init;
  620. dp_power->power_client_deinit = dp_power_client_deinit;
  621. dp_power->power_mmrm_init = dp_power_mmrm_init;
  622. return dp_power;
  623. error:
  624. return ERR_PTR(rc);
  625. }
  626. void dp_power_put(struct dp_power *dp_power)
  627. {
  628. struct dp_power_private *power = NULL;
  629. if (!dp_power)
  630. return;
  631. power = container_of(dp_power, struct dp_power_private, dp_power);
  632. kfree(power);
  633. }