wcd937x.c 96 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <linux/regmap.h>
  13. #include <linux/pm_runtime.h>
  14. #include <sound/soc.h>
  15. #include <sound/tlv.h>
  16. #include <soc/soundwire.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <asoc/wcdcal-hwdep.h>
  20. #include <asoc/msm-cdc-pinctrl.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include <asoc/msm-cdc-supply.h>
  23. #include "wcd937x-registers.h"
  24. #include "wcd937x.h"
  25. #include "internal.h"
  26. #include "asoc/bolero-slave-internal.h"
  27. #define WCD9370_VARIANT 0
  28. #define WCD9375_VARIANT 5
  29. #define WCD937X_VARIANT_ENTRY_SIZE 32
  30. #define NUM_SWRS_DT_PARAMS 5
  31. #define WCD937X_VERSION_1_0 1
  32. #define WCD937X_VERSION_ENTRY_SIZE 32
  33. #define EAR_RX_PATH_AUX 1
  34. #define NUM_ATTEMPTS 5
  35. #define WCD937X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  36. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  37. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  38. SNDRV_PCM_RATE_384000)
  39. /* Fractional Rates */
  40. #define WCD937X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  41. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  42. #define WCD937X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  43. SNDRV_PCM_FMTBIT_S24_LE |\
  44. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  45. enum {
  46. CODEC_TX = 0,
  47. CODEC_RX,
  48. };
  49. enum {
  50. ALLOW_BUCK_DISABLE,
  51. HPH_COMP_DELAY,
  52. HPH_PA_DELAY,
  53. AMIC2_BCS_ENABLE,
  54. };
  55. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  56. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  57. static int wcd937x_handle_post_irq(void *data);
  58. static int wcd937x_reset(struct device *dev);
  59. static int wcd937x_reset_low(struct device *dev);
  60. static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
  61. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  62. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  63. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  64. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  65. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, 0x10),
  66. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, 0x20),
  67. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, 0x40),
  68. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, 0x80),
  69. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, 0x01),
  70. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, 0x02),
  71. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, 0x04),
  72. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, 0x08),
  73. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, 0x10),
  74. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  75. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  76. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  77. REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, 0x01),
  78. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  79. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  80. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  81. };
  82. static struct regmap_irq_chip wcd937x_regmap_irq_chip = {
  83. .name = "wcd937x",
  84. .irqs = wcd937x_irqs,
  85. .num_irqs = ARRAY_SIZE(wcd937x_irqs),
  86. .num_regs = 3,
  87. .status_base = WCD937X_DIGITAL_INTR_STATUS_0,
  88. .mask_base = WCD937X_DIGITAL_INTR_MASK_0,
  89. .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
  90. .use_ack = 1,
  91. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  92. .clear_ack = 1,
  93. #endif
  94. .type_base = WCD937X_DIGITAL_INTR_LEVEL_0,
  95. .runtime_pm = false,
  96. .handle_post_irq = wcd937x_handle_post_irq,
  97. .irq_drv_data = NULL,
  98. };
  99. static struct snd_soc_dai_driver wcd937x_dai[] = {
  100. {
  101. .name = "wcd937x_cdc",
  102. .playback = {
  103. .stream_name = "WCD937X_AIF Playback",
  104. .rates = WCD937X_RATES | WCD937X_FRAC_RATES,
  105. .formats = WCD937X_FORMATS,
  106. .rate_max = 384000,
  107. .rate_min = 8000,
  108. .channels_min = 1,
  109. .channels_max = 4,
  110. },
  111. .capture = {
  112. .stream_name = "WCD937X_AIF Capture",
  113. .rates = WCD937X_RATES,
  114. .formats = WCD937X_FORMATS,
  115. .rate_max = 192000,
  116. .rate_min = 8000,
  117. .channels_min = 1,
  118. .channels_max = 4,
  119. },
  120. },
  121. };
  122. static int wcd937x_handle_post_irq(void *data)
  123. {
  124. struct wcd937x_priv *wcd937x = data;
  125. u32 status1 = 0, status2 = 0, status3 = 0;
  126. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_0, &status1);
  127. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_1, &status2);
  128. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_2, &status3);
  129. wcd937x->tx_swr_dev->slave_irq_pending =
  130. ((status1 || status2 || status3) ? true : false);
  131. return IRQ_HANDLED;
  132. }
  133. static int wcd937x_init_reg(struct snd_soc_component *component)
  134. {
  135. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  136. 0x0E, 0x0E);
  137. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  138. 0x80, 0x80);
  139. usleep_range(1000, 1010);
  140. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  141. 0x40, 0x40);
  142. usleep_range(1000, 1010);
  143. snd_soc_component_update_bits(component, WCD937X_LDORXTX_CONFIG,
  144. 0x10, 0x00);
  145. snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ,
  146. 0xF0, 0x80);
  147. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  148. 0x80, 0x80);
  149. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  150. 0x40, 0x40);
  151. usleep_range(10000, 10010);
  152. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  153. 0x40, 0x00);
  154. snd_soc_component_update_bits(component,
  155. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  156. 0xFF, 0xD9);
  157. snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_1,
  158. 0xFF, 0xFA);
  159. snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_1,
  160. 0xFF, 0xFA);
  161. snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1,
  162. 0xFF, 0xFA);
  163. return 0;
  164. }
  165. static int wcd937x_set_port_params(struct snd_soc_component *component,
  166. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  167. u8 *ch_mask, u32 *ch_rate,
  168. u8 *port_type, u8 path)
  169. {
  170. int i, j;
  171. u8 num_ports = 0;
  172. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  173. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  174. switch (path) {
  175. case CODEC_RX:
  176. map = &wcd937x->rx_port_mapping;
  177. num_ports = wcd937x->num_rx_ports;
  178. break;
  179. case CODEC_TX:
  180. map = &wcd937x->tx_port_mapping;
  181. num_ports = wcd937x->num_tx_ports;
  182. break;
  183. default:
  184. dev_err(component->dev, "%s Invalid path selected %u\n",
  185. __func__, path);
  186. return -EINVAL;
  187. }
  188. for (i = 0; i <= num_ports; i++) {
  189. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  190. if ((*map)[i][j].slave_port_type == slv_prt_type)
  191. goto found;
  192. }
  193. }
  194. found:
  195. if (i > num_ports || j == MAX_CH_PER_PORT) {
  196. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  197. __func__, slv_prt_type);
  198. return -EINVAL;
  199. }
  200. *port_id = i;
  201. *num_ch = (*map)[i][j].num_ch;
  202. *ch_mask = (*map)[i][j].ch_mask;
  203. *ch_rate = (*map)[i][j].ch_rate;
  204. *port_type = (*map)[i][j].master_port_type;
  205. return 0;
  206. }
  207. static int wcd937x_parse_port_mapping(struct device *dev,
  208. char *prop, u8 path)
  209. {
  210. u32 *dt_array, map_size, map_length;
  211. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  212. u32 slave_port_type, master_port_type;
  213. u32 i, ch_iter = 0;
  214. int ret = 0;
  215. u8 *num_ports = NULL;
  216. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  217. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  218. switch (path) {
  219. case CODEC_RX:
  220. map = &wcd937x->rx_port_mapping;
  221. num_ports = &wcd937x->num_rx_ports;
  222. break;
  223. case CODEC_TX:
  224. map = &wcd937x->tx_port_mapping;
  225. num_ports = &wcd937x->num_tx_ports;
  226. break;
  227. default:
  228. dev_err(dev, "%s Invalid path selected %u\n",
  229. __func__, path);
  230. return -EINVAL;
  231. }
  232. if (!of_find_property(dev->of_node, prop,
  233. &map_size)) {
  234. dev_err(dev, "missing port mapping prop %s\n", prop);
  235. ret = -EINVAL;
  236. goto err;
  237. }
  238. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  239. dt_array = kzalloc(map_size, GFP_KERNEL);
  240. if (!dt_array) {
  241. ret = -ENOMEM;
  242. goto err;
  243. }
  244. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  245. NUM_SWRS_DT_PARAMS * map_length);
  246. if (ret) {
  247. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  248. __func__, prop);
  249. ret = -EINVAL;
  250. goto err_pdata_fail;
  251. }
  252. for (i = 0; i < map_length; i++) {
  253. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  254. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  255. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  256. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  257. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  258. if (port_num != old_port_num)
  259. ch_iter = 0;
  260. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  261. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  262. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  263. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  264. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  265. old_port_num = port_num;
  266. }
  267. *num_ports = port_num;
  268. kfree(dt_array);
  269. return 0;
  270. err_pdata_fail:
  271. kfree(dt_array);
  272. err:
  273. return ret;
  274. }
  275. static int wcd937x_tx_connect_port(struct snd_soc_component *component,
  276. u8 slv_port_type, u8 enable)
  277. {
  278. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  279. u8 port_id;
  280. u8 num_ch;
  281. u8 ch_mask;
  282. u32 ch_rate;
  283. u8 ch_type = 0;
  284. int slave_ch_idx;
  285. u8 num_port = 1;
  286. int ret = 0;
  287. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  288. &num_ch, &ch_mask, &ch_rate,
  289. &ch_type, CODEC_TX);
  290. if (ret)
  291. return ret;
  292. slave_ch_idx = wcd937x_slave_get_slave_ch_val(slv_port_type);
  293. if (slave_ch_idx != -EINVAL)
  294. ch_type = wcd937x->tx_master_ch_map[slave_ch_idx];
  295. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  296. __func__, slave_ch_idx, ch_type);
  297. if (enable)
  298. ret = swr_connect_port(wcd937x->tx_swr_dev, &port_id,
  299. num_port, &ch_mask, &ch_rate,
  300. &num_ch, &ch_type);
  301. else
  302. ret = swr_disconnect_port(wcd937x->tx_swr_dev, &port_id,
  303. num_port, &ch_mask, &ch_type);
  304. return ret;
  305. }
  306. static int wcd937x_rx_connect_port(struct snd_soc_component *component,
  307. u8 slv_port_type, u8 enable)
  308. {
  309. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  310. u8 port_id;
  311. u8 num_ch;
  312. u8 ch_mask;
  313. u32 ch_rate;
  314. u8 port_type;
  315. u8 num_port = 1;
  316. int ret = 0;
  317. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  318. &num_ch, &ch_mask, &ch_rate,
  319. &port_type, CODEC_RX);
  320. if (ret)
  321. return ret;
  322. if (enable)
  323. ret = swr_connect_port(wcd937x->rx_swr_dev, &port_id,
  324. num_port, &ch_mask, &ch_rate,
  325. &num_ch, &port_type);
  326. else
  327. ret = swr_disconnect_port(wcd937x->rx_swr_dev, &port_id,
  328. num_port, &ch_mask, &port_type);
  329. return ret;
  330. }
  331. static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
  332. {
  333. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  334. if (wcd937x->rx_clk_cnt == 0) {
  335. snd_soc_component_update_bits(component,
  336. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  337. snd_soc_component_update_bits(component,
  338. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  339. snd_soc_component_update_bits(component,
  340. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x01);
  341. snd_soc_component_update_bits(component,
  342. WCD937X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  343. snd_soc_component_update_bits(component,
  344. WCD937X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  345. snd_soc_component_update_bits(component,
  346. WCD937X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  347. snd_soc_component_update_bits(component,
  348. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  349. }
  350. wcd937x->rx_clk_cnt++;
  351. return 0;
  352. }
  353. static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
  354. {
  355. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  356. if (wcd937x->rx_clk_cnt == 0) {
  357. dev_dbg(wcd937x->dev, "%s:clk already disabled\n", __func__);
  358. return 0;
  359. }
  360. wcd937x->rx_clk_cnt--;
  361. if (wcd937x->rx_clk_cnt == 0) {
  362. snd_soc_component_update_bits(component,
  363. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x00);
  364. snd_soc_component_update_bits(component,
  365. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  366. 0x02, 0x00);
  367. snd_soc_component_update_bits(component,
  368. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  369. 0x01, 0x00);
  370. }
  371. return 0;
  372. }
  373. /*
  374. * wcd937x_soc_get_mbhc: get wcd937x_mbhc handle of corresponding component
  375. * @component: handle to snd_soc_component *
  376. *
  377. * return wcd937x_mbhc handle or error code in case of failure
  378. */
  379. struct wcd937x_mbhc *wcd937x_soc_get_mbhc(struct snd_soc_component *component)
  380. {
  381. struct wcd937x_priv *wcd937x;
  382. if (!component) {
  383. pr_err("%s: Invalid params, NULL component\n", __func__);
  384. return NULL;
  385. }
  386. wcd937x = snd_soc_component_get_drvdata(component);
  387. if (!wcd937x) {
  388. pr_err("%s: Invalid params, NULL tavil\n", __func__);
  389. return NULL;
  390. }
  391. return wcd937x->mbhc;
  392. }
  393. EXPORT_SYMBOL(wcd937x_soc_get_mbhc);
  394. static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  395. struct snd_kcontrol *kcontrol,
  396. int event)
  397. {
  398. struct snd_soc_component *component =
  399. snd_soc_dapm_to_component(w->dapm);
  400. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  401. int hph_mode = wcd937x->hph_mode;
  402. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  403. w->name, event);
  404. switch (event) {
  405. case SND_SOC_DAPM_PRE_PMU:
  406. wcd937x_rx_clk_enable(component);
  407. snd_soc_component_update_bits(component,
  408. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  409. 0x01, 0x01);
  410. snd_soc_component_update_bits(component,
  411. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  412. 0x04, 0x04);
  413. snd_soc_component_update_bits(component,
  414. WCD937X_HPH_RDAC_CLK_CTL1,
  415. 0x80, 0x00);
  416. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  417. break;
  418. case SND_SOC_DAPM_POST_PMU:
  419. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  420. snd_soc_component_update_bits(component,
  421. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  422. 0x0F, 0x02);
  423. else if (hph_mode == CLS_H_LOHIFI)
  424. snd_soc_component_update_bits(component,
  425. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  426. 0x0F, 0x06);
  427. if (wcd937x->comp1_enable) {
  428. snd_soc_component_update_bits(component,
  429. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  430. 0x02, 0x02);
  431. snd_soc_component_update_bits(component,
  432. WCD937X_HPH_L_EN, 0x20, 0x00);
  433. if (wcd937x->comp2_enable) {
  434. snd_soc_component_update_bits(component,
  435. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  436. 0x01, 0x01);
  437. snd_soc_component_update_bits(component,
  438. WCD937X_HPH_R_EN, 0x20, 0x00);
  439. }
  440. /*
  441. * 5ms sleep is required after COMP is enabled as per
  442. * HW requirement
  443. */
  444. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  445. usleep_range(5000, 5100);
  446. clear_bit(HPH_COMP_DELAY,
  447. &wcd937x->status_mask);
  448. }
  449. } else {
  450. snd_soc_component_update_bits(component,
  451. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  452. 0x02, 0x00);
  453. snd_soc_component_update_bits(component,
  454. WCD937X_HPH_L_EN, 0x20, 0x20);
  455. }
  456. snd_soc_component_update_bits(component,
  457. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  458. break;
  459. case SND_SOC_DAPM_POST_PMD:
  460. snd_soc_component_update_bits(component,
  461. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  462. 0x0F, 0x01);
  463. break;
  464. }
  465. return 0;
  466. }
  467. static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  468. struct snd_kcontrol *kcontrol,
  469. int event)
  470. {
  471. struct snd_soc_component *component =
  472. snd_soc_dapm_to_component(w->dapm);
  473. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  474. int hph_mode = wcd937x->hph_mode;
  475. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  476. w->name, event);
  477. switch (event) {
  478. case SND_SOC_DAPM_PRE_PMU:
  479. wcd937x_rx_clk_enable(component);
  480. snd_soc_component_update_bits(component,
  481. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  482. snd_soc_component_update_bits(component,
  483. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  484. snd_soc_component_update_bits(component,
  485. WCD937X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  486. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  487. break;
  488. case SND_SOC_DAPM_POST_PMU:
  489. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  490. snd_soc_component_update_bits(component,
  491. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  492. 0x0F, 0x02);
  493. else if (hph_mode == CLS_H_LOHIFI)
  494. snd_soc_component_update_bits(component,
  495. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  496. 0x0F, 0x06);
  497. if (wcd937x->comp2_enable) {
  498. snd_soc_component_update_bits(component,
  499. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  500. 0x01, 0x01);
  501. snd_soc_component_update_bits(component,
  502. WCD937X_HPH_R_EN, 0x20, 0x00);
  503. if (wcd937x->comp1_enable) {
  504. snd_soc_component_update_bits(component,
  505. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  506. 0x02, 0x02);
  507. snd_soc_component_update_bits(component,
  508. WCD937X_HPH_L_EN, 0x20, 0x00);
  509. }
  510. /*
  511. * 5ms sleep is required after COMP is enabled as per
  512. * HW requirement
  513. */
  514. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  515. usleep_range(5000, 5100);
  516. clear_bit(HPH_COMP_DELAY,
  517. &wcd937x->status_mask);
  518. }
  519. } else {
  520. snd_soc_component_update_bits(component,
  521. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  522. 0x01, 0x00);
  523. snd_soc_component_update_bits(component,
  524. WCD937X_HPH_R_EN, 0x20, 0x20);
  525. }
  526. snd_soc_component_update_bits(component,
  527. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  528. break;
  529. case SND_SOC_DAPM_POST_PMD:
  530. snd_soc_component_update_bits(component,
  531. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  532. 0x0F, 0x01);
  533. break;
  534. }
  535. return 0;
  536. }
  537. static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  538. struct snd_kcontrol *kcontrol,
  539. int event)
  540. {
  541. struct snd_soc_component *component =
  542. snd_soc_dapm_to_component(w->dapm);
  543. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  544. int hph_mode = wcd937x->hph_mode;
  545. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  546. w->name, event);
  547. switch (event) {
  548. case SND_SOC_DAPM_PRE_PMU:
  549. wcd937x_rx_clk_enable(component);
  550. snd_soc_component_update_bits(component,
  551. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  552. 0x04, 0x04);
  553. snd_soc_component_update_bits(component,
  554. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  555. 0x01, 0x01);
  556. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  557. snd_soc_component_update_bits(component,
  558. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  559. 0x0F, 0x02);
  560. else if (hph_mode == CLS_H_LOHIFI)
  561. snd_soc_component_update_bits(component,
  562. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  563. 0x0F, 0x06);
  564. if (wcd937x->comp1_enable)
  565. snd_soc_component_update_bits(component,
  566. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  567. 0x02, 0x02);
  568. usleep_range(5000, 5010);
  569. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  570. 0x04, 0x00);
  571. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  572. WCD_CLSH_EVENT_PRE_DAC,
  573. WCD_CLSH_STATE_EAR,
  574. hph_mode);
  575. break;
  576. case SND_SOC_DAPM_POST_PMD:
  577. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
  578. hph_mode == CLS_H_HIFI)
  579. snd_soc_component_update_bits(component,
  580. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  581. 0x0F, 0x01);
  582. if (wcd937x->comp1_enable)
  583. snd_soc_component_update_bits(component,
  584. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  585. 0x02, 0x00);
  586. break;
  587. };
  588. return 0;
  589. }
  590. static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  591. struct snd_kcontrol *kcontrol,
  592. int event)
  593. {
  594. struct snd_soc_component *component =
  595. snd_soc_dapm_to_component(w->dapm);
  596. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  597. int hph_mode = wcd937x->hph_mode;
  598. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  599. w->name, event);
  600. switch (event) {
  601. case SND_SOC_DAPM_PRE_PMU:
  602. wcd937x_rx_clk_enable(component);
  603. snd_soc_component_update_bits(component,
  604. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  605. 0x04, 0x04);
  606. snd_soc_component_update_bits(component,
  607. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  608. 0x04, 0x04);
  609. snd_soc_component_update_bits(component,
  610. WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
  611. 0x01, 0x01);
  612. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  613. WCD_CLSH_EVENT_PRE_DAC,
  614. WCD_CLSH_STATE_AUX,
  615. hph_mode);
  616. break;
  617. case SND_SOC_DAPM_POST_PMD:
  618. snd_soc_component_update_bits(component,
  619. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  620. 0x04, 0x00);
  621. break;
  622. };
  623. return 0;
  624. }
  625. static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  626. struct snd_kcontrol *kcontrol,
  627. int event)
  628. {
  629. struct snd_soc_component *component =
  630. snd_soc_dapm_to_component(w->dapm);
  631. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  632. int ret = 0;
  633. int hph_mode = wcd937x->hph_mode;
  634. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  635. w->name, event);
  636. switch (event) {
  637. case SND_SOC_DAPM_PRE_PMU:
  638. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  639. wcd937x->rx_swr_dev->dev_num,
  640. true);
  641. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  642. WCD_CLSH_EVENT_PRE_DAC,
  643. WCD_CLSH_STATE_HPHR,
  644. hph_mode);
  645. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  646. 0x10, 0x10);
  647. usleep_range(100, 110);
  648. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  649. snd_soc_component_update_bits(component,
  650. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  651. break;
  652. case SND_SOC_DAPM_POST_PMU:
  653. /*
  654. * 7ms sleep is required after PA is enabled as per
  655. * HW requirement. If compander is disabled, then
  656. * 20ms delay is required.
  657. */
  658. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  659. if (!wcd937x->comp2_enable)
  660. usleep_range(20000, 20100);
  661. else
  662. usleep_range(7000, 7100);
  663. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  664. }
  665. snd_soc_component_update_bits(component,
  666. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  667. 0x02, 0x02);
  668. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  669. snd_soc_component_update_bits(component,
  670. WCD937X_ANA_RX_SUPPLIES,
  671. 0x02, 0x02);
  672. if (wcd937x->update_wcd_event)
  673. wcd937x->update_wcd_event(wcd937x->handle,
  674. SLV_BOLERO_EVT_RX_MUTE,
  675. (WCD_RX2 << 0x10));
  676. wcd_enable_irq(&wcd937x->irq_info,
  677. WCD937X_IRQ_HPHR_PDM_WD_INT);
  678. break;
  679. case SND_SOC_DAPM_PRE_PMD:
  680. wcd_disable_irq(&wcd937x->irq_info,
  681. WCD937X_IRQ_HPHR_PDM_WD_INT);
  682. if (wcd937x->update_wcd_event)
  683. wcd937x->update_wcd_event(wcd937x->handle,
  684. SLV_BOLERO_EVT_RX_MUTE,
  685. (WCD_RX2 << 0x10 | 0x1));
  686. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  687. WCD_EVENT_PRE_HPHR_PA_OFF,
  688. &wcd937x->mbhc->wcd_mbhc);
  689. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  690. break;
  691. case SND_SOC_DAPM_POST_PMD:
  692. /*
  693. * 7ms sleep is required after PA is disabled as per
  694. * HW requirement. If compander is disabled, then
  695. * 20ms delay is required.
  696. */
  697. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  698. if (!wcd937x->comp2_enable)
  699. usleep_range(20000, 20100);
  700. else
  701. usleep_range(7000, 7100);
  702. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  703. }
  704. snd_soc_component_update_bits(component,
  705. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  706. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  707. WCD_EVENT_POST_HPHR_PA_OFF,
  708. &wcd937x->mbhc->wcd_mbhc);
  709. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  710. 0x10, 0x00);
  711. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  712. WCD_CLSH_EVENT_POST_PA,
  713. WCD_CLSH_STATE_HPHR,
  714. hph_mode);
  715. break;
  716. };
  717. return ret;
  718. }
  719. static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  720. struct snd_kcontrol *kcontrol,
  721. int event)
  722. {
  723. struct snd_soc_component *component =
  724. snd_soc_dapm_to_component(w->dapm);
  725. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  726. int ret = 0;
  727. int hph_mode = wcd937x->hph_mode;
  728. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  729. w->name, event);
  730. switch (event) {
  731. case SND_SOC_DAPM_PRE_PMU:
  732. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  733. wcd937x->rx_swr_dev->dev_num,
  734. true);
  735. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  736. WCD_CLSH_EVENT_PRE_DAC,
  737. WCD_CLSH_STATE_HPHL,
  738. hph_mode);
  739. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  740. 0x20, 0x20);
  741. usleep_range(100, 110);
  742. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  743. snd_soc_component_update_bits(component,
  744. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  745. break;
  746. case SND_SOC_DAPM_POST_PMU:
  747. /*
  748. * 7ms sleep is required after PA is enabled as per
  749. * HW requirement. If compander is disabled, then
  750. * 20ms delay is required.
  751. */
  752. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  753. if (!wcd937x->comp1_enable)
  754. usleep_range(20000, 20100);
  755. else
  756. usleep_range(7000, 7100);
  757. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  758. }
  759. snd_soc_component_update_bits(component,
  760. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  761. 0x02, 0x02);
  762. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  763. snd_soc_component_update_bits(component,
  764. WCD937X_ANA_RX_SUPPLIES,
  765. 0x02, 0x02);
  766. if (wcd937x->update_wcd_event)
  767. wcd937x->update_wcd_event(wcd937x->handle,
  768. SLV_BOLERO_EVT_RX_MUTE,
  769. (WCD_RX1 << 0x10));
  770. wcd_enable_irq(&wcd937x->irq_info,
  771. WCD937X_IRQ_HPHL_PDM_WD_INT);
  772. break;
  773. case SND_SOC_DAPM_PRE_PMD:
  774. wcd_disable_irq(&wcd937x->irq_info,
  775. WCD937X_IRQ_HPHL_PDM_WD_INT);
  776. if (wcd937x->update_wcd_event)
  777. wcd937x->update_wcd_event(wcd937x->handle,
  778. SLV_BOLERO_EVT_RX_MUTE,
  779. (WCD_RX1 << 0x10 | 0x1));
  780. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  781. WCD_EVENT_PRE_HPHL_PA_OFF,
  782. &wcd937x->mbhc->wcd_mbhc);
  783. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  784. break;
  785. case SND_SOC_DAPM_POST_PMD:
  786. /*
  787. * 7ms sleep is required after PA is disabled as per
  788. * HW requirement. If compander is disabled, then
  789. * 20ms delay is required.
  790. */
  791. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  792. if (!wcd937x->comp1_enable)
  793. usleep_range(20000, 20100);
  794. else
  795. usleep_range(7000, 7100);
  796. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  797. }
  798. snd_soc_component_update_bits(component,
  799. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  800. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  801. WCD_EVENT_POST_HPHL_PA_OFF,
  802. &wcd937x->mbhc->wcd_mbhc);
  803. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  804. 0x20, 0x00);
  805. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  806. WCD_CLSH_EVENT_POST_PA,
  807. WCD_CLSH_STATE_HPHL,
  808. hph_mode);
  809. break;
  810. };
  811. return ret;
  812. }
  813. static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  814. struct snd_kcontrol *kcontrol,
  815. int event)
  816. {
  817. struct snd_soc_component *component =
  818. snd_soc_dapm_to_component(w->dapm);
  819. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  820. int hph_mode = wcd937x->hph_mode;
  821. int ret = 0;
  822. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  823. w->name, event);
  824. switch (event) {
  825. case SND_SOC_DAPM_PRE_PMU:
  826. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  827. wcd937x->rx_swr_dev->dev_num,
  828. true);
  829. snd_soc_component_update_bits(component,
  830. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  831. break;
  832. case SND_SOC_DAPM_POST_PMU:
  833. usleep_range(1000, 1010);
  834. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  835. snd_soc_component_update_bits(component,
  836. WCD937X_ANA_RX_SUPPLIES,
  837. 0x02, 0x02);
  838. if (wcd937x->update_wcd_event)
  839. wcd937x->update_wcd_event(wcd937x->handle,
  840. SLV_BOLERO_EVT_RX_MUTE,
  841. (WCD_RX3 << 0x10));
  842. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  843. break;
  844. case SND_SOC_DAPM_PRE_PMD:
  845. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  846. if (wcd937x->update_wcd_event)
  847. wcd937x->update_wcd_event(wcd937x->handle,
  848. SLV_BOLERO_EVT_RX_MUTE,
  849. (WCD_RX3 << 0x10 | 0x1));
  850. break;
  851. case SND_SOC_DAPM_POST_PMD:
  852. /* Add delay as per hw requirement */
  853. usleep_range(2000, 2010);
  854. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  855. WCD_CLSH_EVENT_POST_PA,
  856. WCD_CLSH_STATE_AUX,
  857. hph_mode);
  858. snd_soc_component_update_bits(component,
  859. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  860. break;
  861. };
  862. return ret;
  863. }
  864. static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  865. struct snd_kcontrol *kcontrol,
  866. int event)
  867. {
  868. struct snd_soc_component *component =
  869. snd_soc_dapm_to_component(w->dapm);
  870. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  871. int hph_mode = wcd937x->hph_mode;
  872. int ret = 0;
  873. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  874. w->name, event);
  875. switch (event) {
  876. case SND_SOC_DAPM_PRE_PMU:
  877. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  878. wcd937x->rx_swr_dev->dev_num,
  879. true);
  880. /*
  881. * Enable watchdog interrupt for HPHL or AUX
  882. * depending on mux value
  883. */
  884. wcd937x->ear_rx_path =
  885. snd_soc_component_read32(
  886. component, WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
  887. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  888. snd_soc_component_update_bits(component,
  889. WCD937X_DIGITAL_PDM_WD_CTL2,
  890. 0x05, 0x05);
  891. else
  892. snd_soc_component_update_bits(component,
  893. WCD937X_DIGITAL_PDM_WD_CTL0,
  894. 0x17, 0x13);
  895. if (!wcd937x->comp1_enable)
  896. snd_soc_component_update_bits(component,
  897. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  898. break;
  899. case SND_SOC_DAPM_POST_PMU:
  900. usleep_range(6000, 6010);
  901. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  902. snd_soc_component_update_bits(component,
  903. WCD937X_ANA_RX_SUPPLIES,
  904. 0x02, 0x02);
  905. if (wcd937x->update_wcd_event)
  906. wcd937x->update_wcd_event(wcd937x->handle,
  907. SLV_BOLERO_EVT_RX_MUTE,
  908. (WCD_RX1 << 0x10));
  909. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  910. wcd_enable_irq(&wcd937x->irq_info,
  911. WCD937X_IRQ_AUX_PDM_WD_INT);
  912. else
  913. wcd_enable_irq(&wcd937x->irq_info,
  914. WCD937X_IRQ_HPHL_PDM_WD_INT);
  915. break;
  916. case SND_SOC_DAPM_PRE_PMD:
  917. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  918. wcd_disable_irq(&wcd937x->irq_info,
  919. WCD937X_IRQ_AUX_PDM_WD_INT);
  920. else
  921. wcd_disable_irq(&wcd937x->irq_info,
  922. WCD937X_IRQ_HPHL_PDM_WD_INT);
  923. if (wcd937x->update_wcd_event)
  924. wcd937x->update_wcd_event(wcd937x->handle,
  925. SLV_BOLERO_EVT_RX_MUTE,
  926. (WCD_RX1 << 0x10 | 0x1));
  927. break;
  928. case SND_SOC_DAPM_POST_PMD:
  929. if (!wcd937x->comp1_enable)
  930. snd_soc_component_update_bits(component,
  931. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  932. usleep_range(7000, 7010);
  933. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  934. WCD_CLSH_EVENT_POST_PA,
  935. WCD_CLSH_STATE_EAR,
  936. hph_mode);
  937. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  938. 0x04, 0x04);
  939. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  940. snd_soc_component_update_bits(component,
  941. WCD937X_DIGITAL_PDM_WD_CTL2,
  942. 0x05, 0x00);
  943. else
  944. snd_soc_component_update_bits(component,
  945. WCD937X_DIGITAL_PDM_WD_CTL0,
  946. 0x17, 0x00);
  947. break;
  948. };
  949. return ret;
  950. }
  951. static int wcd937x_enable_clsh(struct snd_soc_dapm_widget *w,
  952. struct snd_kcontrol *kcontrol,
  953. int event)
  954. {
  955. struct snd_soc_component *component =
  956. snd_soc_dapm_to_component(w->dapm);
  957. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  958. int mode = wcd937x->hph_mode;
  959. int ret = 0;
  960. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  961. w->name, event);
  962. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  963. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  964. wcd937x_rx_connect_port(component, CLSH,
  965. SND_SOC_DAPM_EVENT_ON(event));
  966. }
  967. if (SND_SOC_DAPM_EVENT_OFF(event))
  968. ret = swr_slvdev_datapath_control(
  969. wcd937x->rx_swr_dev,
  970. wcd937x->rx_swr_dev->dev_num,
  971. false);
  972. return ret;
  973. }
  974. static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
  975. struct snd_kcontrol *kcontrol,
  976. int event)
  977. {
  978. struct snd_soc_component *component =
  979. snd_soc_dapm_to_component(w->dapm);
  980. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  981. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  982. w->name, event);
  983. switch (event) {
  984. case SND_SOC_DAPM_PRE_PMU:
  985. wcd937x_rx_connect_port(component, HPH_L, true);
  986. if (wcd937x->comp1_enable)
  987. wcd937x_rx_connect_port(component, COMP_L, true);
  988. break;
  989. case SND_SOC_DAPM_POST_PMD:
  990. wcd937x_rx_connect_port(component, HPH_L, false);
  991. if (wcd937x->comp1_enable)
  992. wcd937x_rx_connect_port(component, COMP_L, false);
  993. wcd937x_rx_clk_disable(component);
  994. snd_soc_component_update_bits(component,
  995. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  996. 0x01, 0x00);
  997. break;
  998. };
  999. return 0;
  1000. }
  1001. static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
  1002. struct snd_kcontrol *kcontrol, int event)
  1003. {
  1004. struct snd_soc_component *component =
  1005. snd_soc_dapm_to_component(w->dapm);
  1006. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1007. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1008. w->name, event);
  1009. switch (event) {
  1010. case SND_SOC_DAPM_PRE_PMU:
  1011. wcd937x_rx_connect_port(component, HPH_R, true);
  1012. if (wcd937x->comp2_enable)
  1013. wcd937x_rx_connect_port(component, COMP_R, true);
  1014. break;
  1015. case SND_SOC_DAPM_POST_PMD:
  1016. wcd937x_rx_connect_port(component, HPH_R, false);
  1017. if (wcd937x->comp2_enable)
  1018. wcd937x_rx_connect_port(component, COMP_R, false);
  1019. wcd937x_rx_clk_disable(component);
  1020. snd_soc_component_update_bits(component,
  1021. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  1022. 0x02, 0x00);
  1023. break;
  1024. };
  1025. return 0;
  1026. }
  1027. static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
  1028. struct snd_kcontrol *kcontrol,
  1029. int event)
  1030. {
  1031. struct snd_soc_component *component =
  1032. snd_soc_dapm_to_component(w->dapm);
  1033. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1034. w->name, event);
  1035. switch (event) {
  1036. case SND_SOC_DAPM_PRE_PMU:
  1037. wcd937x_rx_connect_port(component, LO, true);
  1038. break;
  1039. case SND_SOC_DAPM_POST_PMD:
  1040. wcd937x_rx_connect_port(component, LO, false);
  1041. usleep_range(6000, 6010);
  1042. wcd937x_rx_clk_disable(component);
  1043. snd_soc_component_update_bits(component,
  1044. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1045. break;
  1046. }
  1047. return 0;
  1048. }
  1049. static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1050. struct snd_kcontrol *kcontrol,
  1051. int event)
  1052. {
  1053. struct snd_soc_component *component =
  1054. snd_soc_dapm_to_component(w->dapm);
  1055. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1056. u16 dmic_clk_reg;
  1057. s32 *dmic_clk_cnt;
  1058. unsigned int dmic;
  1059. char *wname;
  1060. int ret = 0;
  1061. wname = strpbrk(w->name, "012345");
  1062. if (!wname) {
  1063. dev_err(component->dev, "%s: widget not found\n", __func__);
  1064. return -EINVAL;
  1065. }
  1066. ret = kstrtouint(wname, 10, &dmic);
  1067. if (ret < 0) {
  1068. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  1069. __func__);
  1070. return -EINVAL;
  1071. }
  1072. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1073. w->name, event);
  1074. switch (dmic) {
  1075. case 0:
  1076. case 1:
  1077. dmic_clk_cnt = &(wcd937x->dmic_0_1_clk_cnt);
  1078. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
  1079. break;
  1080. case 2:
  1081. case 3:
  1082. dmic_clk_cnt = &(wcd937x->dmic_2_3_clk_cnt);
  1083. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
  1084. break;
  1085. case 4:
  1086. case 5:
  1087. dmic_clk_cnt = &(wcd937x->dmic_4_5_clk_cnt);
  1088. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL;
  1089. break;
  1090. default:
  1091. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1092. __func__);
  1093. return -EINVAL;
  1094. };
  1095. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1096. __func__, event, dmic, *dmic_clk_cnt);
  1097. switch (event) {
  1098. case SND_SOC_DAPM_PRE_PMU:
  1099. snd_soc_component_update_bits(component,
  1100. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1101. snd_soc_component_update_bits(component,
  1102. dmic_clk_reg, 0x07, 0x02);
  1103. snd_soc_component_update_bits(component,
  1104. dmic_clk_reg, 0x08, 0x08);
  1105. snd_soc_component_update_bits(component,
  1106. dmic_clk_reg, 0x70, 0x20);
  1107. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1108. wcd937x->tx_swr_dev->dev_num,
  1109. true);
  1110. break;
  1111. case SND_SOC_DAPM_POST_PMD:
  1112. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1113. break;
  1114. };
  1115. return 0;
  1116. }
  1117. /*
  1118. * wcd937x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1119. * @micb_mv: micbias in mv
  1120. *
  1121. * return register value converted
  1122. */
  1123. int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
  1124. {
  1125. /* min micbias voltage is 1V and maximum is 2.85V */
  1126. if (micb_mv < 1000 || micb_mv > 2850) {
  1127. pr_err("%s: unsupported micbias voltage\n", __func__);
  1128. return -EINVAL;
  1129. }
  1130. return (micb_mv - 1000) / 50;
  1131. }
  1132. EXPORT_SYMBOL(wcd937x_get_micb_vout_ctl_val);
  1133. /*
  1134. * wcd937x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1135. * @component: handle to snd_soc_component *
  1136. * @req_volt: micbias voltage to be set
  1137. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1138. *
  1139. * return 0 if adjustment is success or error code in case of failure
  1140. */
  1141. int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1142. int req_volt, int micb_num)
  1143. {
  1144. struct wcd937x_priv *wcd937x =
  1145. snd_soc_component_get_drvdata(component);
  1146. int cur_vout_ctl, req_vout_ctl;
  1147. int micb_reg, micb_val, micb_en;
  1148. int ret = 0;
  1149. switch (micb_num) {
  1150. case MIC_BIAS_1:
  1151. micb_reg = WCD937X_ANA_MICB1;
  1152. break;
  1153. case MIC_BIAS_2:
  1154. micb_reg = WCD937X_ANA_MICB2;
  1155. break;
  1156. case MIC_BIAS_3:
  1157. micb_reg = WCD937X_ANA_MICB3;
  1158. break;
  1159. default:
  1160. return -EINVAL;
  1161. }
  1162. mutex_lock(&wcd937x->micb_lock);
  1163. /*
  1164. * If requested micbias voltage is same as current micbias
  1165. * voltage, then just return. Otherwise, adjust voltage as
  1166. * per requested value. If micbias is already enabled, then
  1167. * to avoid slow micbias ramp-up or down enable pull-up
  1168. * momentarily, change the micbias value and then re-enable
  1169. * micbias.
  1170. */
  1171. micb_val = snd_soc_component_read32(component, micb_reg);
  1172. micb_en = (micb_val & 0xC0) >> 6;
  1173. cur_vout_ctl = micb_val & 0x3F;
  1174. req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
  1175. if (req_vout_ctl < 0) {
  1176. ret = -EINVAL;
  1177. goto exit;
  1178. }
  1179. if (cur_vout_ctl == req_vout_ctl) {
  1180. ret = 0;
  1181. goto exit;
  1182. }
  1183. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1184. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1185. req_volt, micb_en);
  1186. if (micb_en == 0x1)
  1187. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1188. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1189. if (micb_en == 0x1) {
  1190. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1191. /*
  1192. * Add 2ms delay as per HW requirement after enabling
  1193. * micbias
  1194. */
  1195. usleep_range(2000, 2100);
  1196. }
  1197. exit:
  1198. mutex_unlock(&wcd937x->micb_lock);
  1199. return ret;
  1200. }
  1201. EXPORT_SYMBOL(wcd937x_mbhc_micb_adjust_voltage);
  1202. static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1203. struct snd_kcontrol *kcontrol,
  1204. int event)
  1205. {
  1206. struct snd_soc_component *component =
  1207. snd_soc_dapm_to_component(w->dapm);
  1208. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1209. int ret = 0;
  1210. switch (event) {
  1211. case SND_SOC_DAPM_PRE_PMU:
  1212. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1213. /* Enable BCS for Headset mic */
  1214. if (w->shift == 1 && !(snd_soc_component_read32(component,
  1215. WCD937X_TX_NEW_TX_CH2_SEL) & 0x80)) {
  1216. wcd937x_tx_connect_port(component, MBHC, true);
  1217. set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1218. }
  1219. wcd937x_tx_connect_port(component, ADC1 + (w->shift), true);
  1220. } else {
  1221. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1222. }
  1223. break;
  1224. case SND_SOC_DAPM_POST_PMD:
  1225. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1226. wcd937x->tx_swr_dev->dev_num,
  1227. false);
  1228. break;
  1229. };
  1230. return ret;
  1231. }
  1232. static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1233. struct snd_kcontrol *kcontrol,
  1234. int event){
  1235. struct snd_soc_component *component =
  1236. snd_soc_dapm_to_component(w->dapm);
  1237. struct wcd937x_priv *wcd937x =
  1238. snd_soc_component_get_drvdata(component);
  1239. int ret = 0;
  1240. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1241. w->name, event);
  1242. switch (event) {
  1243. case SND_SOC_DAPM_PRE_PMU:
  1244. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1245. wcd937x->ana_clk_count++;
  1246. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1247. snd_soc_component_update_bits(component,
  1248. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1249. snd_soc_component_update_bits(component,
  1250. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1251. snd_soc_component_update_bits(component,
  1252. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1253. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1254. wcd937x->tx_swr_dev->dev_num,
  1255. true);
  1256. break;
  1257. case SND_SOC_DAPM_POST_PMD:
  1258. wcd937x_tx_connect_port(component, ADC1 + (w->shift), false);
  1259. if (w->shift == 1 &&
  1260. test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) {
  1261. wcd937x_tx_connect_port(component, MBHC, false);
  1262. clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1263. }
  1264. snd_soc_component_update_bits(component,
  1265. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1266. break;
  1267. };
  1268. return ret;
  1269. }
  1270. static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
  1271. struct snd_kcontrol *kcontrol, int event)
  1272. {
  1273. struct snd_soc_component *component =
  1274. snd_soc_dapm_to_component(w->dapm);
  1275. struct wcd937x_priv *wcd937x =
  1276. snd_soc_component_get_drvdata(component);
  1277. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1278. w->name, event);
  1279. switch (event) {
  1280. case SND_SOC_DAPM_PRE_PMU:
  1281. snd_soc_component_update_bits(component,
  1282. WCD937X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1283. snd_soc_component_update_bits(component,
  1284. WCD937X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1285. snd_soc_component_update_bits(component,
  1286. WCD937X_ANA_TX_CH2, 0x40, 0x40);
  1287. snd_soc_component_update_bits(component,
  1288. WCD937X_ANA_TX_CH3_HPF, 0x40, 0x40);
  1289. snd_soc_component_update_bits(component,
  1290. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70);
  1291. snd_soc_component_update_bits(component,
  1292. WCD937X_ANA_TX_CH1, 0x80, 0x80);
  1293. snd_soc_component_update_bits(component,
  1294. WCD937X_ANA_TX_CH2, 0x40, 0x00);
  1295. snd_soc_component_update_bits(component,
  1296. WCD937X_ANA_TX_CH2, 0x80, 0x80);
  1297. snd_soc_component_update_bits(component,
  1298. WCD937X_ANA_TX_CH3, 0x80, 0x80);
  1299. break;
  1300. case SND_SOC_DAPM_POST_PMD:
  1301. snd_soc_component_update_bits(component,
  1302. WCD937X_ANA_TX_CH1, 0x80, 0x00);
  1303. snd_soc_component_update_bits(component,
  1304. WCD937X_ANA_TX_CH2, 0x80, 0x00);
  1305. snd_soc_component_update_bits(component,
  1306. WCD937X_ANA_TX_CH3, 0x80, 0x00);
  1307. snd_soc_component_update_bits(component,
  1308. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1309. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1310. wcd937x->ana_clk_count--;
  1311. if (wcd937x->ana_clk_count <= 0) {
  1312. snd_soc_component_update_bits(component,
  1313. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1314. wcd937x->ana_clk_count = 0;
  1315. }
  1316. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1317. snd_soc_component_update_bits(component,
  1318. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1319. break;
  1320. };
  1321. return 0;
  1322. }
  1323. int wcd937x_micbias_control(struct snd_soc_component *component,
  1324. int micb_num, int req, bool is_dapm)
  1325. {
  1326. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1327. int micb_index = micb_num - 1;
  1328. u16 micb_reg;
  1329. int pre_off_event = 0, post_off_event = 0;
  1330. int post_on_event = 0, post_dapm_off = 0;
  1331. int post_dapm_on = 0;
  1332. if ((micb_index < 0) || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
  1333. dev_err(component->dev, "%s: Invalid micbias index, micb_ind:%d\n",
  1334. __func__, micb_index);
  1335. return -EINVAL;
  1336. }
  1337. switch (micb_num) {
  1338. case MIC_BIAS_1:
  1339. micb_reg = WCD937X_ANA_MICB1;
  1340. break;
  1341. case MIC_BIAS_2:
  1342. micb_reg = WCD937X_ANA_MICB2;
  1343. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1344. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1345. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1346. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1347. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1348. break;
  1349. case MIC_BIAS_3:
  1350. micb_reg = WCD937X_ANA_MICB3;
  1351. break;
  1352. default:
  1353. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1354. __func__, micb_num);
  1355. return -EINVAL;
  1356. };
  1357. mutex_lock(&wcd937x->micb_lock);
  1358. switch (req) {
  1359. case MICB_PULLUP_ENABLE:
  1360. wcd937x->pullup_ref[micb_index]++;
  1361. if ((wcd937x->pullup_ref[micb_index] == 1) &&
  1362. (wcd937x->micb_ref[micb_index] == 0))
  1363. snd_soc_component_update_bits(component, micb_reg,
  1364. 0xC0, 0x80);
  1365. break;
  1366. case MICB_PULLUP_DISABLE:
  1367. if (wcd937x->pullup_ref[micb_index] > 0)
  1368. wcd937x->pullup_ref[micb_index]--;
  1369. if ((wcd937x->pullup_ref[micb_index] == 0) &&
  1370. (wcd937x->micb_ref[micb_index] == 0))
  1371. snd_soc_component_update_bits(component, micb_reg,
  1372. 0xC0, 0x00);
  1373. break;
  1374. case MICB_ENABLE:
  1375. wcd937x->micb_ref[micb_index]++;
  1376. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1377. wcd937x->ana_clk_count++;
  1378. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1379. if (wcd937x->micb_ref[micb_index] == 1) {
  1380. snd_soc_component_update_bits(component,
  1381. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1382. snd_soc_component_update_bits(component,
  1383. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1384. snd_soc_component_update_bits(component,
  1385. WCD937X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1386. snd_soc_component_update_bits(component,
  1387. WCD937X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1388. snd_soc_component_update_bits(component,
  1389. WCD937X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1390. snd_soc_component_update_bits(component,
  1391. micb_reg, 0xC0, 0x40);
  1392. if (post_on_event)
  1393. blocking_notifier_call_chain(
  1394. &wcd937x->mbhc->notifier, post_on_event,
  1395. &wcd937x->mbhc->wcd_mbhc);
  1396. }
  1397. if (is_dapm && post_dapm_on && wcd937x->mbhc)
  1398. blocking_notifier_call_chain(
  1399. &wcd937x->mbhc->notifier, post_dapm_on,
  1400. &wcd937x->mbhc->wcd_mbhc);
  1401. break;
  1402. case MICB_DISABLE:
  1403. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1404. wcd937x->ana_clk_count--;
  1405. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1406. if (wcd937x->micb_ref[micb_index] > 0)
  1407. wcd937x->micb_ref[micb_index]--;
  1408. if ((wcd937x->micb_ref[micb_index] == 0) &&
  1409. (wcd937x->pullup_ref[micb_index] > 0))
  1410. snd_soc_component_update_bits(component, micb_reg,
  1411. 0xC0, 0x80);
  1412. else if ((wcd937x->micb_ref[micb_index] == 0) &&
  1413. (wcd937x->pullup_ref[micb_index] == 0)) {
  1414. if (pre_off_event && wcd937x->mbhc)
  1415. blocking_notifier_call_chain(
  1416. &wcd937x->mbhc->notifier, pre_off_event,
  1417. &wcd937x->mbhc->wcd_mbhc);
  1418. snd_soc_component_update_bits(component, micb_reg,
  1419. 0xC0, 0x00);
  1420. if (post_off_event && wcd937x->mbhc)
  1421. blocking_notifier_call_chain(
  1422. &wcd937x->mbhc->notifier,
  1423. post_off_event,
  1424. &wcd937x->mbhc->wcd_mbhc);
  1425. }
  1426. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1427. if (wcd937x->ana_clk_count <= 0) {
  1428. snd_soc_component_update_bits(component,
  1429. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  1430. 0x10, 0x00);
  1431. wcd937x->ana_clk_count = 0;
  1432. }
  1433. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1434. if (is_dapm && post_dapm_off && wcd937x->mbhc)
  1435. blocking_notifier_call_chain(
  1436. &wcd937x->mbhc->notifier, post_dapm_off,
  1437. &wcd937x->mbhc->wcd_mbhc);
  1438. break;
  1439. };
  1440. dev_dbg(component->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1441. __func__, micb_num, wcd937x->micb_ref[micb_index],
  1442. wcd937x->pullup_ref[micb_index]);
  1443. mutex_unlock(&wcd937x->micb_lock);
  1444. return 0;
  1445. }
  1446. EXPORT_SYMBOL(wcd937x_micbias_control);
  1447. void wcd937x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1448. bool bcs_disable)
  1449. {
  1450. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1451. if (wcd937x->update_wcd_event) {
  1452. if (bcs_disable)
  1453. wcd937x->update_wcd_event(wcd937x->handle,
  1454. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  1455. else
  1456. wcd937x->update_wcd_event(wcd937x->handle,
  1457. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  1458. }
  1459. }
  1460. static int wcd937x_get_logical_addr(struct swr_device *swr_dev)
  1461. {
  1462. int ret = 0;
  1463. uint8_t devnum = 0;
  1464. int num_retry = NUM_ATTEMPTS;
  1465. do {
  1466. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1467. if (ret) {
  1468. dev_err(&swr_dev->dev,
  1469. "%s get devnum %d for dev addr %lx failed\n",
  1470. __func__, devnum, swr_dev->addr);
  1471. /* retry after 1ms */
  1472. usleep_range(1000, 1010);
  1473. }
  1474. } while (ret && --num_retry);
  1475. swr_dev->dev_num = devnum;
  1476. return 0;
  1477. }
  1478. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1479. struct wcd_mbhc_config *mbhc_cfg)
  1480. {
  1481. if (mbhc_cfg->enable_usbc_analog) {
  1482. if (!(snd_soc_component_read32(component, WCD937X_ANA_MBHC_MECH)
  1483. & 0x20))
  1484. return true;
  1485. }
  1486. return false;
  1487. }
  1488. static int wcd937x_event_notify(struct notifier_block *block,
  1489. unsigned long val,
  1490. void *data)
  1491. {
  1492. u16 event = (val & 0xffff);
  1493. u16 amic = (val >> 0x10);
  1494. u16 mask = 0x40, reg = 0x0;
  1495. int ret = 0;
  1496. struct wcd937x_priv *wcd937x = dev_get_drvdata((struct device *)data);
  1497. struct snd_soc_component *component = wcd937x->component;
  1498. struct wcd_mbhc *mbhc;
  1499. switch (event) {
  1500. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  1501. if (amic == 0x1 || amic == 0x2)
  1502. reg = WCD937X_ANA_TX_CH2;
  1503. else if (amic == 0x3)
  1504. reg = WCD937X_ANA_TX_CH3_HPF;
  1505. else
  1506. return 0;
  1507. if (amic == 0x2)
  1508. mask = 0x20;
  1509. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1510. break;
  1511. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1512. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  1513. 0xC0, 0x00);
  1514. snd_soc_component_update_bits(component, WCD937X_ANA_EAR,
  1515. 0x80, 0x00);
  1516. snd_soc_component_update_bits(component, WCD937X_AUX_AUXPA,
  1517. 0x80, 0x00);
  1518. break;
  1519. case BOLERO_SLV_EVT_SSR_DOWN:
  1520. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = true;
  1521. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1522. wcd937x->usbc_hs_status = get_usbc_hs_status(component,
  1523. mbhc->mbhc_cfg);
  1524. wcd937x_mbhc_ssr_down(wcd937x->mbhc, component);
  1525. wcd937x_reset_low(wcd937x->dev);
  1526. break;
  1527. case BOLERO_SLV_EVT_SSR_UP:
  1528. wcd937x_reset(wcd937x->dev);
  1529. /* allow reset to take effect */
  1530. usleep_range(10000, 10010);
  1531. wcd937x_get_logical_addr(wcd937x->tx_swr_dev);
  1532. wcd937x_get_logical_addr(wcd937x->rx_swr_dev);
  1533. wcd937x_init_reg(component);
  1534. regcache_mark_dirty(wcd937x->regmap);
  1535. regcache_sync(wcd937x->regmap);
  1536. /* Initialize MBHC module */
  1537. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1538. ret = wcd937x_mbhc_post_ssr_init(wcd937x->mbhc, component);
  1539. if (ret) {
  1540. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1541. __func__);
  1542. } else {
  1543. wcd937x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1544. if (wcd937x->usbc_hs_status)
  1545. mdelay(500);
  1546. }
  1547. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = false;
  1548. break;
  1549. default:
  1550. dev_err(component->dev, "%s: invalid event %d\n", __func__,
  1551. event);
  1552. break;
  1553. }
  1554. return 0;
  1555. }
  1556. static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1557. int event)
  1558. {
  1559. struct snd_soc_component *component =
  1560. snd_soc_dapm_to_component(w->dapm);
  1561. int micb_num;
  1562. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1563. __func__, w->name, event);
  1564. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1565. micb_num = MIC_BIAS_1;
  1566. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1567. micb_num = MIC_BIAS_2;
  1568. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1569. micb_num = MIC_BIAS_3;
  1570. else
  1571. return -EINVAL;
  1572. switch (event) {
  1573. case SND_SOC_DAPM_PRE_PMU:
  1574. wcd937x_micbias_control(component, micb_num,
  1575. MICB_ENABLE, true);
  1576. break;
  1577. case SND_SOC_DAPM_POST_PMU:
  1578. usleep_range(1000, 1100);
  1579. break;
  1580. case SND_SOC_DAPM_POST_PMD:
  1581. wcd937x_micbias_control(component, micb_num,
  1582. MICB_DISABLE, true);
  1583. break;
  1584. };
  1585. return 0;
  1586. }
  1587. static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1588. struct snd_kcontrol *kcontrol,
  1589. int event)
  1590. {
  1591. return __wcd937x_codec_enable_micbias(w, event);
  1592. }
  1593. static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1594. int event)
  1595. {
  1596. struct snd_soc_component *component =
  1597. snd_soc_dapm_to_component(w->dapm);
  1598. int micb_num;
  1599. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1600. __func__, w->name, event);
  1601. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1602. micb_num = MIC_BIAS_1;
  1603. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1604. micb_num = MIC_BIAS_2;
  1605. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1606. micb_num = MIC_BIAS_3;
  1607. else
  1608. return -EINVAL;
  1609. switch (event) {
  1610. case SND_SOC_DAPM_PRE_PMU:
  1611. wcd937x_micbias_control(component, micb_num,
  1612. MICB_PULLUP_ENABLE, true);
  1613. break;
  1614. case SND_SOC_DAPM_POST_PMU:
  1615. /* 1 msec delay as per HW requirement */
  1616. usleep_range(1000, 1100);
  1617. break;
  1618. case SND_SOC_DAPM_POST_PMD:
  1619. wcd937x_micbias_control(component, micb_num,
  1620. MICB_PULLUP_DISABLE, true);
  1621. break;
  1622. };
  1623. return 0;
  1624. }
  1625. static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1626. struct snd_kcontrol *kcontrol,
  1627. int event)
  1628. {
  1629. return __wcd937x_codec_enable_micbias_pullup(w, event);
  1630. }
  1631. static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1632. struct snd_ctl_elem_value *ucontrol)
  1633. {
  1634. struct snd_soc_component *component =
  1635. snd_soc_kcontrol_component(kcontrol);
  1636. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1637. ucontrol->value.integer.value[0] = wcd937x->hph_mode;
  1638. return 0;
  1639. }
  1640. static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1641. struct snd_ctl_elem_value *ucontrol)
  1642. {
  1643. struct snd_soc_component *component =
  1644. snd_soc_kcontrol_component(kcontrol);
  1645. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1646. u32 mode_val;
  1647. mode_val = ucontrol->value.enumerated.item[0];
  1648. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1649. if (mode_val == 0) {
  1650. dev_warn(component->dev, "%s:Invalid HPH Mode, default to class_AB\n",
  1651. __func__);
  1652. mode_val = 3; /* enum will be updated later */
  1653. }
  1654. wcd937x->hph_mode = mode_val;
  1655. return 0;
  1656. }
  1657. static int wcd937x_tx_ch_pwr_level_get(struct snd_kcontrol *kcontrol,
  1658. struct snd_ctl_elem_value *ucontrol)
  1659. {
  1660. struct snd_soc_component *component =
  1661. snd_soc_kcontrol_component(kcontrol);
  1662. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1663. if (strnstr(kcontrol->id.name, "CH1", sizeof(kcontrol->id.name)))
  1664. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[0];
  1665. else if (strnstr(kcontrol->id.name, "CH3", sizeof(kcontrol->id.name)))
  1666. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[1];
  1667. return 0;
  1668. }
  1669. static int wcd937x_tx_ch_pwr_level_put(struct snd_kcontrol *kcontrol,
  1670. struct snd_ctl_elem_value *ucontrol)
  1671. {
  1672. struct snd_soc_component *component =
  1673. snd_soc_kcontrol_component(kcontrol);
  1674. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1675. u32 pwr_level = ucontrol->value.enumerated.item[0];
  1676. dev_dbg(component->dev, "%s: tx ch pwr_level: %d\n",
  1677. __func__, pwr_level);
  1678. if (strnstr(kcontrol->id.name, "CH1",
  1679. sizeof(kcontrol->id.name))) {
  1680. snd_soc_component_update_bits(component,
  1681. WCD937X_ANA_TX_CH1, 0x60,
  1682. pwr_level << 0x5);
  1683. wcd937x->tx_ch_pwr[0] = pwr_level;
  1684. } else if (strnstr(kcontrol->id.name, "CH3",
  1685. sizeof(kcontrol->id.name))) {
  1686. snd_soc_component_update_bits(component,
  1687. WCD937X_ANA_TX_CH3, 0x60,
  1688. pwr_level << 0x5);
  1689. wcd937x->tx_ch_pwr[1] = pwr_level;
  1690. }
  1691. return 0;
  1692. }
  1693. static int wcd937x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  1694. struct snd_ctl_elem_value *ucontrol)
  1695. {
  1696. u8 ear_pa_gain = 0;
  1697. struct snd_soc_component *component =
  1698. snd_soc_kcontrol_component(kcontrol);
  1699. ear_pa_gain = snd_soc_component_read32(component,
  1700. WCD937X_ANA_EAR_COMPANDER_CTL);
  1701. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  1702. ucontrol->value.integer.value[0] = ear_pa_gain;
  1703. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  1704. ear_pa_gain);
  1705. return 0;
  1706. }
  1707. static int wcd937x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  1708. struct snd_ctl_elem_value *ucontrol)
  1709. {
  1710. u8 ear_pa_gain = 0;
  1711. struct snd_soc_component *component =
  1712. snd_soc_kcontrol_component(kcontrol);
  1713. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1714. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1715. __func__, ucontrol->value.integer.value[0]);
  1716. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  1717. if (!wcd937x->comp1_enable) {
  1718. snd_soc_component_update_bits(component,
  1719. WCD937X_ANA_EAR_COMPANDER_CTL,
  1720. 0x7C, ear_pa_gain);
  1721. }
  1722. return 0;
  1723. }
  1724. static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
  1725. struct snd_ctl_elem_value *ucontrol)
  1726. {
  1727. struct snd_soc_component *component =
  1728. snd_soc_kcontrol_component(kcontrol);
  1729. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1730. bool hphr;
  1731. struct soc_multi_mixer_control *mc;
  1732. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1733. hphr = mc->shift;
  1734. ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
  1735. wcd937x->comp1_enable;
  1736. return 0;
  1737. }
  1738. static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
  1739. struct snd_ctl_elem_value *ucontrol)
  1740. {
  1741. struct snd_soc_component *component =
  1742. snd_soc_kcontrol_component(kcontrol);
  1743. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1744. int value = ucontrol->value.integer.value[0];
  1745. bool hphr;
  1746. struct soc_multi_mixer_control *mc;
  1747. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1748. hphr = mc->shift;
  1749. if (hphr)
  1750. wcd937x->comp2_enable = value;
  1751. else
  1752. wcd937x->comp1_enable = value;
  1753. return 0;
  1754. }
  1755. static int wcd937x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1756. struct snd_kcontrol *kcontrol,
  1757. int event)
  1758. {
  1759. struct snd_soc_component *component =
  1760. snd_soc_dapm_to_component(w->dapm);
  1761. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1762. struct wcd937x_pdata *pdata = NULL;
  1763. int ret = 0;
  1764. pdata = dev_get_platdata(wcd937x->dev);
  1765. if (!pdata) {
  1766. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1767. return -EINVAL;
  1768. }
  1769. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1770. w->name, event);
  1771. switch (event) {
  1772. case SND_SOC_DAPM_PRE_PMU:
  1773. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  1774. dev_dbg(component->dev,
  1775. "%s: buck already in enabled state\n",
  1776. __func__);
  1777. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1778. return 0;
  1779. }
  1780. ret = msm_cdc_enable_ondemand_supply(wcd937x->dev,
  1781. wcd937x->supplies,
  1782. pdata->regulator,
  1783. pdata->num_supplies,
  1784. "cdc-vdd-buck");
  1785. if (ret == -EINVAL) {
  1786. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1787. __func__);
  1788. return ret;
  1789. }
  1790. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1791. /*
  1792. * 200us sleep is required after LDO15 is enabled as per
  1793. * HW requirement
  1794. */
  1795. usleep_range(200, 250);
  1796. break;
  1797. case SND_SOC_DAPM_POST_PMD:
  1798. set_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1799. break;
  1800. }
  1801. return 0;
  1802. }
  1803. static const char * const rx_hph_mode_mux_text[] = {
  1804. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1805. "CLS_H_ULP", "CLS_AB_HIFI",
  1806. };
  1807. const char * const tx_master_ch_text[] = {
  1808. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  1809. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  1810. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  1811. "SWRM_PCM_IN",
  1812. };
  1813. const struct soc_enum tx_master_ch_enum =
  1814. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  1815. tx_master_ch_text);
  1816. static void wcd937x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  1817. {
  1818. u8 ch_type = 0;
  1819. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  1820. ch_type = ADC1;
  1821. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  1822. ch_type = ADC2;
  1823. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  1824. ch_type = ADC3;
  1825. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  1826. ch_type = DMIC0;
  1827. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  1828. ch_type = DMIC1;
  1829. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  1830. ch_type = MBHC;
  1831. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  1832. ch_type = DMIC2;
  1833. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  1834. ch_type = DMIC3;
  1835. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  1836. ch_type = DMIC4;
  1837. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  1838. ch_type = DMIC5;
  1839. else
  1840. pr_err("%s: ch name: %s is not listed\n", __func__, wname);
  1841. if (ch_type)
  1842. *ch_idx = wcd937x_slave_get_slave_ch_val(ch_type);
  1843. else
  1844. *ch_idx = -EINVAL;
  1845. }
  1846. static int wcd937x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  1847. struct snd_ctl_elem_value *ucontrol)
  1848. {
  1849. struct snd_soc_component *component =
  1850. snd_soc_kcontrol_component(kcontrol);
  1851. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1852. int slave_ch_idx;
  1853. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1854. if (slave_ch_idx != -EINVAL)
  1855. ucontrol->value.integer.value[0] =
  1856. wcd937x_slave_get_master_ch_val(
  1857. wcd937x->tx_master_ch_map[slave_ch_idx]);
  1858. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1859. __func__, ucontrol->value.integer.value[0]);
  1860. return 0;
  1861. }
  1862. static int wcd937x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  1863. struct snd_ctl_elem_value *ucontrol)
  1864. {
  1865. struct snd_soc_component *component =
  1866. snd_soc_kcontrol_component(kcontrol);
  1867. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1868. int slave_ch_idx;
  1869. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1870. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  1871. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  1872. __func__, ucontrol->value.enumerated.item[0]);
  1873. if (slave_ch_idx != -EINVAL)
  1874. wcd937x->tx_master_ch_map[slave_ch_idx] =
  1875. wcd937x_slave_get_master_ch(
  1876. ucontrol->value.enumerated.item[0]);
  1877. return 0;
  1878. }
  1879. static const char * const wcd937x_tx_ch_pwr_level_text[] = {
  1880. "L0", "L1", "L2", "L3",
  1881. };
  1882. static const char * const wcd937x_ear_pa_gain_text[] = {
  1883. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  1884. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  1885. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  1886. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  1887. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  1888. };
  1889. static const struct soc_enum rx_hph_mode_mux_enum =
  1890. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1891. rx_hph_mode_mux_text);
  1892. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_ear_pa_gain_enum,
  1893. wcd937x_ear_pa_gain_text);
  1894. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_tx_ch_pwr_level_enum,
  1895. wcd937x_tx_ch_pwr_level_text);
  1896. static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
  1897. SOC_ENUM_EXT("EAR PA GAIN", wcd937x_ear_pa_gain_enum,
  1898. wcd937x_ear_pa_gain_get, wcd937x_ear_pa_gain_put),
  1899. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1900. wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
  1901. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1902. wcd937x_get_compander, wcd937x_set_compander),
  1903. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1904. wcd937x_get_compander, wcd937x_set_compander),
  1905. SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
  1906. SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
  1907. SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0,
  1908. analog_gain),
  1909. SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0,
  1910. analog_gain),
  1911. SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0,
  1912. analog_gain),
  1913. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  1914. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1915. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  1916. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1917. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  1918. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1919. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  1920. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1921. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  1922. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1923. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  1924. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1925. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  1926. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1927. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  1928. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1929. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  1930. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1931. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  1932. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1933. SOC_ENUM_EXT("TX CH1 PWR", wcd937x_tx_ch_pwr_level_enum,
  1934. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  1935. SOC_ENUM_EXT("TX CH3 PWR", wcd937x_tx_ch_pwr_level_enum,
  1936. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  1937. };
  1938. static const struct snd_kcontrol_new adc1_switch[] = {
  1939. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1940. };
  1941. static const struct snd_kcontrol_new adc2_switch[] = {
  1942. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1943. };
  1944. static const struct snd_kcontrol_new adc3_switch[] = {
  1945. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1946. };
  1947. static const struct snd_kcontrol_new dmic1_switch[] = {
  1948. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1949. };
  1950. static const struct snd_kcontrol_new dmic2_switch[] = {
  1951. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1952. };
  1953. static const struct snd_kcontrol_new dmic3_switch[] = {
  1954. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1955. };
  1956. static const struct snd_kcontrol_new dmic4_switch[] = {
  1957. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1958. };
  1959. static const struct snd_kcontrol_new dmic5_switch[] = {
  1960. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1961. };
  1962. static const struct snd_kcontrol_new dmic6_switch[] = {
  1963. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1964. };
  1965. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1966. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1967. };
  1968. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1969. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1970. };
  1971. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1972. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1973. };
  1974. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1975. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1976. };
  1977. static const char * const adc2_mux_text[] = {
  1978. "INP2", "INP3"
  1979. };
  1980. static const char * const rdac3_mux_text[] = {
  1981. "RX1", "RX3"
  1982. };
  1983. static const struct soc_enum adc2_enum =
  1984. SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
  1985. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1986. static const struct soc_enum rdac3_enum =
  1987. SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  1988. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  1989. static const struct snd_kcontrol_new tx_adc2_mux =
  1990. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1991. static const struct snd_kcontrol_new rx_rdac3_mux =
  1992. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  1993. static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
  1994. /*input widgets*/
  1995. SND_SOC_DAPM_INPUT("AMIC1"),
  1996. SND_SOC_DAPM_INPUT("AMIC2"),
  1997. SND_SOC_DAPM_INPUT("AMIC3"),
  1998. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  1999. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2000. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2001. /*
  2002. * These dummy widgets are null connected to WCD937x dapm input and
  2003. * output widgets which are not actual path endpoints. This ensures
  2004. * dapm doesnt set these dapm input and output widgets as endpoints.
  2005. */
  2006. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  2007. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  2008. /*tx widgets*/
  2009. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2010. wcd937x_codec_enable_adc,
  2011. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2012. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2013. wcd937x_codec_enable_adc,
  2014. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2015. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2016. NULL, 0, wcd937x_enable_req,
  2017. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2018. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  2019. NULL, 0, wcd937x_enable_req,
  2020. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2021. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2022. &tx_adc2_mux),
  2023. /*tx mixers*/
  2024. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2025. adc1_switch, ARRAY_SIZE(adc1_switch),
  2026. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2027. SND_SOC_DAPM_POST_PMD),
  2028. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 1, 0,
  2029. adc2_switch, ARRAY_SIZE(adc2_switch),
  2030. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2031. SND_SOC_DAPM_POST_PMD),
  2032. /* micbias widgets*/
  2033. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2034. wcd937x_codec_enable_micbias,
  2035. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2036. SND_SOC_DAPM_POST_PMD),
  2037. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2038. wcd937x_codec_enable_micbias,
  2039. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2040. SND_SOC_DAPM_POST_PMD),
  2041. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2042. wcd937x_codec_enable_micbias,
  2043. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2044. SND_SOC_DAPM_POST_PMD),
  2045. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2046. wcd937x_codec_enable_vdd_buck,
  2047. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2048. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2049. wcd937x_enable_clsh,
  2050. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2051. /*rx widgets*/
  2052. SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
  2053. wcd937x_codec_enable_ear_pa,
  2054. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2055. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2056. SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
  2057. wcd937x_codec_enable_aux_pa,
  2058. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2059. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2060. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
  2061. wcd937x_codec_enable_hphl_pa,
  2062. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2063. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2064. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
  2065. wcd937x_codec_enable_hphr_pa,
  2066. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2067. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2068. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2069. wcd937x_codec_hphl_dac_event,
  2070. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2071. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2072. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2073. wcd937x_codec_hphr_dac_event,
  2074. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2075. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2076. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2077. wcd937x_codec_ear_dac_event,
  2078. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2079. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2080. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2081. wcd937x_codec_aux_dac_event,
  2082. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2083. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2084. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2085. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2086. wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2087. SND_SOC_DAPM_POST_PMD),
  2088. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2089. wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2090. SND_SOC_DAPM_POST_PMD),
  2091. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2092. wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2093. SND_SOC_DAPM_POST_PMD),
  2094. /* rx mixer widgets*/
  2095. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2096. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2097. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2098. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2099. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2100. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2101. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2102. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2103. /*output widgets tx*/
  2104. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  2105. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  2106. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2107. /*output widgets rx*/
  2108. SND_SOC_DAPM_OUTPUT("EAR"),
  2109. SND_SOC_DAPM_OUTPUT("AUX"),
  2110. SND_SOC_DAPM_OUTPUT("HPHL"),
  2111. SND_SOC_DAPM_OUTPUT("HPHR"),
  2112. /* micbias pull up widgets*/
  2113. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2114. wcd937x_codec_enable_micbias_pullup,
  2115. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2116. SND_SOC_DAPM_POST_PMD),
  2117. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2118. wcd937x_codec_enable_micbias_pullup,
  2119. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2120. SND_SOC_DAPM_POST_PMD),
  2121. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2122. wcd937x_codec_enable_micbias_pullup,
  2123. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2124. SND_SOC_DAPM_POST_PMD),
  2125. };
  2126. static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
  2127. /*input widgets*/
  2128. SND_SOC_DAPM_INPUT("AMIC4"),
  2129. /*tx widgets*/
  2130. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2131. wcd937x_codec_enable_adc,
  2132. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2133. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  2134. NULL, 0, wcd937x_enable_req,
  2135. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2136. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2137. wcd937x_codec_enable_dmic,
  2138. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2139. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2140. wcd937x_codec_enable_dmic,
  2141. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2142. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2143. wcd937x_codec_enable_dmic,
  2144. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2145. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2146. wcd937x_codec_enable_dmic,
  2147. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2148. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2149. wcd937x_codec_enable_dmic,
  2150. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2151. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2152. wcd937x_codec_enable_dmic,
  2153. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2154. /*tx mixer widgets*/
  2155. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2156. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2157. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2158. SND_SOC_DAPM_POST_PMD),
  2159. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 1,
  2160. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2161. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2162. SND_SOC_DAPM_POST_PMD),
  2163. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 2,
  2164. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2165. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2166. SND_SOC_DAPM_POST_PMD),
  2167. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 3,
  2168. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2169. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2170. SND_SOC_DAPM_POST_PMD),
  2171. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 4,
  2172. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2173. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2174. SND_SOC_DAPM_POST_PMD),
  2175. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 5,
  2176. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2177. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2178. SND_SOC_DAPM_POST_PMD),
  2179. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 2, 0, adc3_switch,
  2180. ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
  2181. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2182. /*output widgets*/
  2183. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  2184. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  2185. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  2186. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  2187. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  2188. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  2189. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  2190. };
  2191. static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
  2192. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  2193. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2194. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2195. {"ADC1 REQ", NULL, "ADC1"},
  2196. {"ADC1", NULL, "AMIC1"},
  2197. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2198. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2199. {"ADC2 REQ", NULL, "ADC2"},
  2200. {"ADC2", NULL, "ADC2 MUX"},
  2201. {"ADC2 MUX", "INP3", "AMIC3"},
  2202. {"ADC2 MUX", "INP2", "AMIC2"},
  2203. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  2204. {"IN1_HPHL", NULL, "VDD_BUCK"},
  2205. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2206. {"RX1", NULL, "IN1_HPHL"},
  2207. {"RDAC1", NULL, "RX1"},
  2208. {"HPHL_RDAC", "Switch", "RDAC1"},
  2209. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2210. {"HPHL", NULL, "HPHL PGA"},
  2211. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  2212. {"IN2_HPHR", NULL, "VDD_BUCK"},
  2213. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2214. {"RX2", NULL, "IN2_HPHR"},
  2215. {"RDAC2", NULL, "RX2"},
  2216. {"HPHR_RDAC", "Switch", "RDAC2"},
  2217. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2218. {"HPHR", NULL, "HPHR PGA"},
  2219. {"IN3_AUX", NULL, "WCD_RX_DUMMY"},
  2220. {"IN3_AUX", NULL, "VDD_BUCK"},
  2221. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2222. {"RX3", NULL, "IN3_AUX"},
  2223. {"RDAC4", NULL, "RX3"},
  2224. {"AUX_RDAC", "Switch", "RDAC4"},
  2225. {"AUX PGA", NULL, "AUX_RDAC"},
  2226. {"AUX", NULL, "AUX PGA"},
  2227. {"RDAC3_MUX", "RX3", "RX3"},
  2228. {"RDAC3_MUX", "RX1", "RX1"},
  2229. {"RDAC3", NULL, "RDAC3_MUX"},
  2230. {"EAR_RDAC", "Switch", "RDAC3"},
  2231. {"EAR PGA", NULL, "EAR_RDAC"},
  2232. {"EAR", NULL, "EAR PGA"},
  2233. };
  2234. static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
  2235. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  2236. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2237. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  2238. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2239. {"ADC3 REQ", NULL, "ADC3"},
  2240. {"ADC3", NULL, "AMIC4"},
  2241. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2242. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  2243. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2244. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2245. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  2246. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2247. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2248. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  2249. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2250. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2251. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  2252. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2253. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2254. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  2255. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2256. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2257. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  2258. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2259. };
  2260. static ssize_t wcd937x_version_read(struct snd_info_entry *entry,
  2261. void *file_private_data,
  2262. struct file *file,
  2263. char __user *buf, size_t count,
  2264. loff_t pos)
  2265. {
  2266. struct wcd937x_priv *priv;
  2267. char buffer[WCD937X_VERSION_ENTRY_SIZE];
  2268. int len = 0;
  2269. priv = (struct wcd937x_priv *) entry->private_data;
  2270. if (!priv) {
  2271. pr_err("%s: wcd937x priv is null\n", __func__);
  2272. return -EINVAL;
  2273. }
  2274. switch (priv->version) {
  2275. case WCD937X_VERSION_1_0:
  2276. len = snprintf(buffer, sizeof(buffer), "WCD937X_1_0\n");
  2277. break;
  2278. default:
  2279. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2280. }
  2281. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2282. }
  2283. static struct snd_info_entry_ops wcd937x_info_ops = {
  2284. .read = wcd937x_version_read,
  2285. };
  2286. static ssize_t wcd937x_variant_read(struct snd_info_entry *entry,
  2287. void *file_private_data,
  2288. struct file *file,
  2289. char __user *buf, size_t count,
  2290. loff_t pos)
  2291. {
  2292. struct wcd937x_priv *priv;
  2293. char buffer[WCD937X_VARIANT_ENTRY_SIZE];
  2294. int len = 0;
  2295. priv = (struct wcd937x_priv *) entry->private_data;
  2296. if (!priv) {
  2297. pr_err("%s: wcd937x priv is null\n", __func__);
  2298. return -EINVAL;
  2299. }
  2300. switch (priv->variant) {
  2301. case WCD9370_VARIANT:
  2302. len = snprintf(buffer, sizeof(buffer), "WCD9370\n");
  2303. break;
  2304. case WCD9375_VARIANT:
  2305. len = snprintf(buffer, sizeof(buffer), "WCD9375\n");
  2306. break;
  2307. default:
  2308. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2309. }
  2310. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2311. }
  2312. static struct snd_info_entry_ops wcd937x_variant_ops = {
  2313. .read = wcd937x_variant_read,
  2314. };
  2315. /*
  2316. * wcd937x_info_create_codec_entry - creates wcd937x module
  2317. * @codec_root: The parent directory
  2318. * @component: component instance
  2319. *
  2320. * Creates wcd937x module, variant and version entry under the given
  2321. * parent directory.
  2322. *
  2323. * Return: 0 on success or negative error code on failure.
  2324. */
  2325. int wcd937x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2326. struct snd_soc_component *component)
  2327. {
  2328. struct snd_info_entry *version_entry;
  2329. struct snd_info_entry *variant_entry;
  2330. struct wcd937x_priv *priv;
  2331. struct snd_soc_card *card;
  2332. if (!codec_root || !component)
  2333. return -EINVAL;
  2334. priv = snd_soc_component_get_drvdata(component);
  2335. if (priv->entry) {
  2336. dev_dbg(priv->dev,
  2337. "%s:wcd937x module already created\n", __func__);
  2338. return 0;
  2339. }
  2340. card = component->card;
  2341. priv->entry = snd_info_create_module_entry(codec_root->module,
  2342. "wcd937x", codec_root);
  2343. if (!priv->entry) {
  2344. dev_dbg(component->dev, "%s: failed to create wcd937x entry\n",
  2345. __func__);
  2346. return -ENOMEM;
  2347. }
  2348. priv->entry->mode = S_IFDIR | 0555;
  2349. if (snd_info_register(priv->entry) < 0) {
  2350. snd_info_free_entry(priv->entry);
  2351. return -ENOMEM;
  2352. }
  2353. version_entry = snd_info_create_card_entry(card->snd_card,
  2354. "version",
  2355. priv->entry);
  2356. if (!version_entry) {
  2357. dev_dbg(component->dev, "%s: failed to create wcd937x version entry\n",
  2358. __func__);
  2359. snd_info_free_entry(priv->entry);
  2360. return -ENOMEM;
  2361. }
  2362. version_entry->private_data = priv;
  2363. version_entry->size = WCD937X_VERSION_ENTRY_SIZE;
  2364. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2365. version_entry->c.ops = &wcd937x_info_ops;
  2366. if (snd_info_register(version_entry) < 0) {
  2367. snd_info_free_entry(version_entry);
  2368. snd_info_free_entry(priv->entry);
  2369. return -ENOMEM;
  2370. }
  2371. priv->version_entry = version_entry;
  2372. variant_entry = snd_info_create_card_entry(card->snd_card,
  2373. "variant",
  2374. priv->entry);
  2375. if (!variant_entry) {
  2376. dev_dbg(component->dev,
  2377. "%s: failed to create wcd937x variant entry\n",
  2378. __func__);
  2379. snd_info_free_entry(version_entry);
  2380. snd_info_free_entry(priv->entry);
  2381. return -ENOMEM;
  2382. }
  2383. variant_entry->private_data = priv;
  2384. variant_entry->size = WCD937X_VARIANT_ENTRY_SIZE;
  2385. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2386. variant_entry->c.ops = &wcd937x_variant_ops;
  2387. if (snd_info_register(variant_entry) < 0) {
  2388. snd_info_free_entry(variant_entry);
  2389. snd_info_free_entry(version_entry);
  2390. snd_info_free_entry(priv->entry);
  2391. return -ENOMEM;
  2392. }
  2393. priv->variant_entry = variant_entry;
  2394. return 0;
  2395. }
  2396. EXPORT_SYMBOL(wcd937x_info_create_codec_entry);
  2397. static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x,
  2398. struct wcd937x_pdata *pdata)
  2399. {
  2400. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0;
  2401. int rc = 0;
  2402. if (!pdata) {
  2403. dev_err(wcd937x->dev, "%s: NULL pdata\n", __func__);
  2404. return -ENODEV;
  2405. }
  2406. /* set micbias voltage */
  2407. vout_ctl_1 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2408. vout_ctl_2 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2409. vout_ctl_3 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2410. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0) {
  2411. rc = -EINVAL;
  2412. goto done;
  2413. }
  2414. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, 0x3F,
  2415. vout_ctl_1);
  2416. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, 0x3F,
  2417. vout_ctl_2);
  2418. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, 0x3F,
  2419. vout_ctl_3);
  2420. done:
  2421. return rc;
  2422. }
  2423. static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
  2424. {
  2425. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2426. struct snd_soc_dapm_context *dapm =
  2427. snd_soc_component_get_dapm(component);
  2428. int variant;
  2429. int ret = -EINVAL;
  2430. dev_info(component->dev, "%s()\n", __func__);
  2431. wcd937x = snd_soc_component_get_drvdata(component);
  2432. if (!wcd937x)
  2433. return -EINVAL;
  2434. wcd937x->component = component;
  2435. snd_soc_component_init_regmap(component, wcd937x->regmap);
  2436. variant = (snd_soc_component_read32(
  2437. component, WCD937X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2438. wcd937x->variant = variant;
  2439. wcd937x->fw_data = devm_kzalloc(component->dev,
  2440. sizeof(*(wcd937x->fw_data)),
  2441. GFP_KERNEL);
  2442. if (!wcd937x->fw_data) {
  2443. dev_err(component->dev, "Failed to allocate fw_data\n");
  2444. ret = -ENOMEM;
  2445. goto err;
  2446. }
  2447. set_bit(WCD9XXX_MBHC_CAL, wcd937x->fw_data->cal_bit);
  2448. ret = wcd_cal_create_hwdep(wcd937x->fw_data,
  2449. WCD9XXX_CODEC_HWDEP_NODE, component);
  2450. if (ret < 0) {
  2451. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2452. goto err_hwdep;
  2453. }
  2454. ret = wcd937x_mbhc_init(&wcd937x->mbhc, component, wcd937x->fw_data);
  2455. if (ret) {
  2456. pr_err("%s: mbhc initialization failed\n", __func__);
  2457. goto err_hwdep;
  2458. }
  2459. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2460. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2461. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2462. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2463. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2464. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2465. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2466. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2467. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  2468. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2469. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2470. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2471. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2472. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  2473. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  2474. snd_soc_dapm_sync(dapm);
  2475. wcd_cls_h_init(&wcd937x->clsh_info);
  2476. wcd937x_init_reg(component);
  2477. if (wcd937x->variant == WCD9375_VARIANT) {
  2478. ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
  2479. ARRAY_SIZE(wcd9375_dapm_widgets));
  2480. if (ret < 0) {
  2481. dev_err(component->dev, "%s: Failed to add snd_ctls\n",
  2482. __func__);
  2483. goto err_hwdep;
  2484. }
  2485. ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
  2486. ARRAY_SIZE(wcd9375_audio_map));
  2487. if (ret < 0) {
  2488. dev_err(component->dev, "%s: Failed to add routes\n",
  2489. __func__);
  2490. goto err_hwdep;
  2491. }
  2492. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2493. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2494. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2495. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2496. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2497. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2498. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2499. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2500. snd_soc_dapm_sync(dapm);
  2501. }
  2502. wcd937x->version = WCD937X_VERSION_1_0;
  2503. /* Register event notifier */
  2504. wcd937x->nblock.notifier_call = wcd937x_event_notify;
  2505. if (wcd937x->register_notifier) {
  2506. ret = wcd937x->register_notifier(wcd937x->handle,
  2507. &wcd937x->nblock,
  2508. true);
  2509. if (ret) {
  2510. dev_err(component->dev,
  2511. "%s: Failed to register notifier %d\n",
  2512. __func__, ret);
  2513. return ret;
  2514. }
  2515. }
  2516. return ret;
  2517. err_hwdep:
  2518. wcd937x->fw_data = NULL;
  2519. err:
  2520. return ret;
  2521. }
  2522. static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
  2523. {
  2524. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2525. if (!wcd937x)
  2526. return;
  2527. if (wcd937x->register_notifier)
  2528. wcd937x->register_notifier(wcd937x->handle,
  2529. &wcd937x->nblock,
  2530. false);
  2531. return;
  2532. }
  2533. static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
  2534. .name = WCD937X_DRV_NAME,
  2535. .probe = wcd937x_soc_codec_probe,
  2536. .remove = wcd937x_soc_codec_remove,
  2537. .controls = wcd937x_snd_controls,
  2538. .num_controls = ARRAY_SIZE(wcd937x_snd_controls),
  2539. .dapm_widgets = wcd937x_dapm_widgets,
  2540. .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
  2541. .dapm_routes = wcd937x_audio_map,
  2542. .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
  2543. };
  2544. #ifdef CONFIG_PM_SLEEP
  2545. static int wcd937x_suspend(struct device *dev)
  2546. {
  2547. struct wcd937x_priv *wcd937x = NULL;
  2548. int ret = 0;
  2549. struct wcd937x_pdata *pdata = NULL;
  2550. if (!dev)
  2551. return -ENODEV;
  2552. wcd937x = dev_get_drvdata(dev);
  2553. if (!wcd937x)
  2554. return -EINVAL;
  2555. pdata = dev_get_platdata(wcd937x->dev);
  2556. if (!pdata) {
  2557. dev_err(dev, "%s: pdata is NULL\n", __func__);
  2558. return -EINVAL;
  2559. }
  2560. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  2561. ret = msm_cdc_disable_ondemand_supply(wcd937x->dev,
  2562. wcd937x->supplies,
  2563. pdata->regulator,
  2564. pdata->num_supplies,
  2565. "cdc-vdd-buck");
  2566. if (ret == -EINVAL) {
  2567. dev_err(dev, "%s: vdd buck is not disabled\n",
  2568. __func__);
  2569. return 0;
  2570. }
  2571. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  2572. }
  2573. return 0;
  2574. }
  2575. static int wcd937x_resume(struct device *dev)
  2576. {
  2577. return 0;
  2578. }
  2579. #endif
  2580. static int wcd937x_reset(struct device *dev)
  2581. {
  2582. struct wcd937x_priv *wcd937x = NULL;
  2583. int rc = 0;
  2584. int value = 0;
  2585. if (!dev)
  2586. return -ENODEV;
  2587. wcd937x = dev_get_drvdata(dev);
  2588. if (!wcd937x)
  2589. return -EINVAL;
  2590. if (!wcd937x->rst_np) {
  2591. dev_err(dev, "%s: reset gpio device node not specified\n",
  2592. __func__);
  2593. return -EINVAL;
  2594. }
  2595. value = msm_cdc_pinctrl_get_state(wcd937x->rst_np);
  2596. if (value > 0)
  2597. return 0;
  2598. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2599. if (rc) {
  2600. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2601. __func__);
  2602. return rc;
  2603. }
  2604. /* 20ms sleep required after pulling the reset gpio to LOW */
  2605. usleep_range(20, 30);
  2606. rc = msm_cdc_pinctrl_select_active_state(wcd937x->rst_np);
  2607. if (rc) {
  2608. dev_err(dev, "%s: wcd active state request fail!\n",
  2609. __func__);
  2610. return rc;
  2611. }
  2612. /* 20ms sleep required after pulling the reset gpio to HIGH */
  2613. usleep_range(20, 30);
  2614. return rc;
  2615. }
  2616. static int wcd937x_read_of_property_u32(struct device *dev, const char *name,
  2617. u32 *val)
  2618. {
  2619. int rc = 0;
  2620. rc = of_property_read_u32(dev->of_node, name, val);
  2621. if (rc)
  2622. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2623. __func__, name, dev->of_node->full_name);
  2624. return rc;
  2625. }
  2626. static void wcd937x_dt_parse_micbias_info(struct device *dev,
  2627. struct wcd937x_micbias_setting *mb)
  2628. {
  2629. u32 prop_val = 0;
  2630. int rc = 0;
  2631. /* MB1 */
  2632. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2633. NULL)) {
  2634. rc = wcd937x_read_of_property_u32(dev,
  2635. "qcom,cdc-micbias1-mv",
  2636. &prop_val);
  2637. if (!rc)
  2638. mb->micb1_mv = prop_val;
  2639. } else {
  2640. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2641. __func__);
  2642. }
  2643. /* MB2 */
  2644. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2645. NULL)) {
  2646. rc = wcd937x_read_of_property_u32(dev,
  2647. "qcom,cdc-micbias2-mv",
  2648. &prop_val);
  2649. if (!rc)
  2650. mb->micb2_mv = prop_val;
  2651. } else {
  2652. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2653. __func__);
  2654. }
  2655. /* MB3 */
  2656. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2657. NULL)) {
  2658. rc = wcd937x_read_of_property_u32(dev,
  2659. "qcom,cdc-micbias3-mv",
  2660. &prop_val);
  2661. if (!rc)
  2662. mb->micb3_mv = prop_val;
  2663. } else {
  2664. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2665. __func__);
  2666. }
  2667. }
  2668. static int wcd937x_reset_low(struct device *dev)
  2669. {
  2670. struct wcd937x_priv *wcd937x = NULL;
  2671. int rc = 0;
  2672. if (!dev)
  2673. return -ENODEV;
  2674. wcd937x = dev_get_drvdata(dev);
  2675. if (!wcd937x)
  2676. return -EINVAL;
  2677. if (!wcd937x->rst_np) {
  2678. dev_err(dev, "%s: reset gpio device node not specified\n",
  2679. __func__);
  2680. return -EINVAL;
  2681. }
  2682. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2683. if (rc) {
  2684. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2685. __func__);
  2686. return rc;
  2687. }
  2688. /* 20ms sleep required after pulling the reset gpio to LOW */
  2689. usleep_range(20, 30);
  2690. return rc;
  2691. }
  2692. struct wcd937x_pdata *wcd937x_populate_dt_data(struct device *dev)
  2693. {
  2694. struct wcd937x_pdata *pdata = NULL;
  2695. pdata = kzalloc(sizeof(struct wcd937x_pdata),
  2696. GFP_KERNEL);
  2697. if (!pdata)
  2698. return NULL;
  2699. pdata->rst_np = of_parse_phandle(dev->of_node,
  2700. "qcom,wcd-rst-gpio-node", 0);
  2701. if (!pdata->rst_np) {
  2702. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2703. __func__, "qcom,wcd-rst-gpio-node",
  2704. dev->of_node->full_name);
  2705. return NULL;
  2706. }
  2707. /* Parse power supplies */
  2708. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2709. &pdata->num_supplies);
  2710. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2711. dev_err(dev, "%s: no power supplies defined for codec\n",
  2712. __func__);
  2713. return NULL;
  2714. }
  2715. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2716. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2717. wcd937x_dt_parse_micbias_info(dev, &pdata->micbias);
  2718. return pdata;
  2719. }
  2720. static int wcd937x_wakeup(void *handle, bool enable)
  2721. {
  2722. struct wcd937x_priv *priv;
  2723. if (!handle) {
  2724. pr_err("%s: NULL handle\n", __func__);
  2725. return -EINVAL;
  2726. }
  2727. priv = (struct wcd937x_priv *)handle;
  2728. if (!priv->tx_swr_dev) {
  2729. pr_err("%s: tx swr dev is NULL\n", __func__);
  2730. return -EINVAL;
  2731. }
  2732. if (enable)
  2733. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2734. else
  2735. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2736. }
  2737. static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
  2738. {
  2739. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2740. __func__, irq);
  2741. return IRQ_HANDLED;
  2742. }
  2743. static int wcd937x_bind(struct device *dev)
  2744. {
  2745. int ret = 0, i = 0;
  2746. struct wcd937x_priv *wcd937x = NULL;
  2747. struct wcd937x_pdata *pdata = NULL;
  2748. struct wcd_ctrl_platform_data *plat_data = NULL;
  2749. wcd937x = kzalloc(sizeof(struct wcd937x_priv), GFP_KERNEL);
  2750. if (!wcd937x)
  2751. return -ENOMEM;
  2752. dev_set_drvdata(dev, wcd937x);
  2753. pdata = wcd937x_populate_dt_data(dev);
  2754. if (!pdata) {
  2755. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2756. return -EINVAL;
  2757. }
  2758. wcd937x->dev = dev;
  2759. wcd937x->dev->platform_data = pdata;
  2760. wcd937x->rst_np = pdata->rst_np;
  2761. ret = msm_cdc_init_supplies(dev, &wcd937x->supplies,
  2762. pdata->regulator, pdata->num_supplies);
  2763. if (!wcd937x->supplies) {
  2764. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2765. __func__);
  2766. goto err_bind_all;
  2767. }
  2768. plat_data = dev_get_platdata(dev->parent);
  2769. if (!plat_data) {
  2770. dev_err(dev, "%s: platform data from parent is NULL\n",
  2771. __func__);
  2772. ret = -EINVAL;
  2773. goto err_bind_all;
  2774. }
  2775. wcd937x->handle = (void *)plat_data->handle;
  2776. if (!wcd937x->handle) {
  2777. dev_err(dev, "%s: handle is NULL\n", __func__);
  2778. ret = -EINVAL;
  2779. goto err_bind_all;
  2780. }
  2781. wcd937x->update_wcd_event = plat_data->update_wcd_event;
  2782. if (!wcd937x->update_wcd_event) {
  2783. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2784. __func__);
  2785. ret = -EINVAL;
  2786. goto err_bind_all;
  2787. }
  2788. wcd937x->register_notifier = plat_data->register_notifier;
  2789. if (!wcd937x->register_notifier) {
  2790. dev_err(dev, "%s: register_notifier api is null!\n",
  2791. __func__);
  2792. ret = -EINVAL;
  2793. goto err_bind_all;
  2794. }
  2795. ret = msm_cdc_enable_static_supplies(dev, wcd937x->supplies,
  2796. pdata->regulator,
  2797. pdata->num_supplies);
  2798. if (ret) {
  2799. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2800. __func__);
  2801. goto err_bind_all;
  2802. }
  2803. wcd937x_reset(dev);
  2804. /*
  2805. * Add 5msec delay to provide sufficient time for
  2806. * soundwire auto enumeration of slave devices as
  2807. * as per HW requirement.
  2808. */
  2809. usleep_range(5000, 5010);
  2810. wcd937x->wakeup = wcd937x_wakeup;
  2811. ret = component_bind_all(dev, wcd937x);
  2812. if (ret) {
  2813. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2814. __func__, ret);
  2815. goto err_bind_all;
  2816. }
  2817. ret = wcd937x_parse_port_mapping(dev, "qcom,rx_swr_ch_map", CODEC_RX);
  2818. ret |= wcd937x_parse_port_mapping(dev, "qcom,tx_swr_ch_map", CODEC_TX);
  2819. if (ret) {
  2820. dev_err(dev, "Failed to read port mapping\n");
  2821. goto err;
  2822. }
  2823. wcd937x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2824. if (!wcd937x->rx_swr_dev) {
  2825. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2826. __func__);
  2827. ret = -ENODEV;
  2828. goto err;
  2829. }
  2830. wcd937x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2831. if (!wcd937x->tx_swr_dev) {
  2832. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2833. __func__);
  2834. ret = -ENODEV;
  2835. goto err;
  2836. }
  2837. wcd937x->regmap = devm_regmap_init_swr(wcd937x->tx_swr_dev,
  2838. &wcd937x_regmap_config);
  2839. if (!wcd937x->regmap) {
  2840. dev_err(dev, "%s: Regmap init failed\n",
  2841. __func__);
  2842. goto err;
  2843. }
  2844. /* Set all interupts as edge triggered */
  2845. for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
  2846. regmap_write(wcd937x->regmap,
  2847. (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2848. wcd937x_regmap_irq_chip.irq_drv_data = wcd937x;
  2849. wcd937x->irq_info.wcd_regmap_irq_chip = &wcd937x_regmap_irq_chip;
  2850. wcd937x->irq_info.codec_name = "WCD937X";
  2851. wcd937x->irq_info.regmap = wcd937x->regmap;
  2852. wcd937x->irq_info.dev = dev;
  2853. ret = wcd_irq_init(&wcd937x->irq_info, &wcd937x->virq);
  2854. if (ret) {
  2855. dev_err(dev, "%s: IRQ init failed: %d\n",
  2856. __func__, ret);
  2857. goto err;
  2858. }
  2859. wcd937x->tx_swr_dev->slave_irq = wcd937x->virq;
  2860. ret = wcd937x_set_micbias_data(wcd937x, pdata);
  2861. if (ret < 0) {
  2862. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  2863. goto err_irq;
  2864. }
  2865. /* default L1 power setting */
  2866. wcd937x->tx_ch_pwr[0] = 1;
  2867. wcd937x->tx_ch_pwr[1] = 1;
  2868. mutex_init(&wcd937x->micb_lock);
  2869. mutex_init(&wcd937x->ana_tx_clk_lock);
  2870. /* Request for watchdog interrupt */
  2871. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT,
  2872. "HPHR PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2873. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT,
  2874. "HPHL PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2875. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT,
  2876. "AUX PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2877. /* Disable watchdog interrupt for HPH and AUX */
  2878. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT);
  2879. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT);
  2880. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  2881. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
  2882. wcd937x_dai, ARRAY_SIZE(wcd937x_dai));
  2883. if (ret) {
  2884. dev_err(dev, "%s: Codec registration failed\n",
  2885. __func__);
  2886. goto err_irq;
  2887. }
  2888. return ret;
  2889. err_irq:
  2890. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2891. err:
  2892. component_unbind_all(dev, wcd937x);
  2893. err_bind_all:
  2894. dev_set_drvdata(dev, NULL);
  2895. kfree(pdata);
  2896. kfree(wcd937x);
  2897. return ret;
  2898. }
  2899. static void wcd937x_unbind(struct device *dev)
  2900. {
  2901. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  2902. struct wcd937x_pdata *pdata = dev_get_platdata(wcd937x->dev);
  2903. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2904. snd_soc_unregister_component(dev);
  2905. component_unbind_all(dev, wcd937x);
  2906. mutex_destroy(&wcd937x->micb_lock);
  2907. mutex_destroy(&wcd937x->ana_tx_clk_lock);
  2908. dev_set_drvdata(dev, NULL);
  2909. kfree(pdata);
  2910. kfree(wcd937x);
  2911. }
  2912. static const struct of_device_id wcd937x_dt_match[] = {
  2913. { .compatible = "qcom,wcd937x-codec" , .data = "wcd937x" },
  2914. {}
  2915. };
  2916. static const struct component_master_ops wcd937x_comp_ops = {
  2917. .bind = wcd937x_bind,
  2918. .unbind = wcd937x_unbind,
  2919. };
  2920. static int wcd937x_compare_of(struct device *dev, void *data)
  2921. {
  2922. return dev->of_node == data;
  2923. }
  2924. static void wcd937x_release_of(struct device *dev, void *data)
  2925. {
  2926. of_node_put(data);
  2927. }
  2928. static int wcd937x_add_slave_components(struct device *dev,
  2929. struct component_match **matchptr)
  2930. {
  2931. struct device_node *np, *rx_node, *tx_node;
  2932. np = dev->of_node;
  2933. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2934. if (!rx_node) {
  2935. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2936. return -ENODEV;
  2937. }
  2938. of_node_get(rx_node);
  2939. component_match_add_release(dev, matchptr,
  2940. wcd937x_release_of,
  2941. wcd937x_compare_of,
  2942. rx_node);
  2943. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  2944. if (!tx_node) {
  2945. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2946. return -ENODEV;
  2947. }
  2948. of_node_get(tx_node);
  2949. component_match_add_release(dev, matchptr,
  2950. wcd937x_release_of,
  2951. wcd937x_compare_of,
  2952. tx_node);
  2953. return 0;
  2954. }
  2955. static int wcd937x_probe(struct platform_device *pdev)
  2956. {
  2957. struct component_match *match = NULL;
  2958. int ret;
  2959. ret = wcd937x_add_slave_components(&pdev->dev, &match);
  2960. if (ret)
  2961. return ret;
  2962. return component_master_add_with_match(&pdev->dev,
  2963. &wcd937x_comp_ops, match);
  2964. }
  2965. static int wcd937x_remove(struct platform_device *pdev)
  2966. {
  2967. component_master_del(&pdev->dev, &wcd937x_comp_ops);
  2968. dev_set_drvdata(&pdev->dev, NULL);
  2969. return 0;
  2970. }
  2971. #ifdef CONFIG_PM_SLEEP
  2972. static const struct dev_pm_ops wcd937x_dev_pm_ops = {
  2973. SET_SYSTEM_SLEEP_PM_OPS(
  2974. wcd937x_suspend,
  2975. wcd937x_resume
  2976. )
  2977. };
  2978. #endif
  2979. static struct platform_driver wcd937x_codec_driver = {
  2980. .probe = wcd937x_probe,
  2981. .remove = wcd937x_remove,
  2982. .driver = {
  2983. .name = "wcd937x_codec",
  2984. .owner = THIS_MODULE,
  2985. .of_match_table = of_match_ptr(wcd937x_dt_match),
  2986. #ifdef CONFIG_PM_SLEEP
  2987. .pm = &wcd937x_dev_pm_ops,
  2988. #endif
  2989. .suppress_bind_attrs = true,
  2990. },
  2991. };
  2992. module_platform_driver(wcd937x_codec_driver);
  2993. MODULE_DESCRIPTION("WCD937X Codec driver");
  2994. MODULE_LICENSE("GPL v2");