wcd-clsh.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <sound/soc.h>
  8. #include <linux/kernel.h>
  9. #include <linux/delay.h>
  10. #include <asoc/wcd9xxx_registers.h>
  11. #include <asoc/wcd-clsh.h>
  12. #define WCD_USLEEP_RANGE 50
  13. static void (*clsh_state_fp[NUM_CLSH_STATES])(struct snd_soc_component *,
  14. struct wcd_clsh_cdc_info *,
  15. u8 req_state, bool en, int mode);
  16. static const char *mode_to_str(int mode)
  17. {
  18. switch (mode) {
  19. case CLS_H_NORMAL:
  20. return WCD_CLSH_STRINGIFY(CLS_H_NORMAL);
  21. case CLS_H_HIFI:
  22. return WCD_CLSH_STRINGIFY(CLS_H_HIFI);
  23. case CLS_H_LOHIFI:
  24. return WCD_CLSH_STRINGIFY(CLS_H_LOHIFI);
  25. case CLS_H_LP:
  26. return WCD_CLSH_STRINGIFY(CLS_H_LP);
  27. case CLS_H_ULP:
  28. return WCD_CLSH_STRINGIFY(CLS_H_ULP);
  29. case CLS_AB:
  30. return WCD_CLSH_STRINGIFY(CLS_AB);
  31. case CLS_AB_HIFI:
  32. return WCD_CLSH_STRINGIFY(CLS_AB_HIFI);
  33. case CLS_AB_LP:
  34. return WCD_CLSH_STRINGIFY(CLS_AB_LP);
  35. case CLS_AB_LOHIFI:
  36. return WCD_CLSH_STRINGIFY(CLS_AB_LOHIFI);
  37. default:
  38. return WCD_CLSH_STRINGIFY(CLS_H_INVALID);
  39. };
  40. }
  41. static const char *state_to_str(u8 state, char *buf, size_t buflen)
  42. {
  43. int i;
  44. int cnt = 0;
  45. /*
  46. * This array of strings should match with enum wcd_clsh_state_bit.
  47. */
  48. static const char *const states[] = {
  49. "STATE_EAR",
  50. "STATE_HPH_L",
  51. "STATE_HPH_R",
  52. "STATE_AUX",
  53. };
  54. if (state == WCD_CLSH_STATE_IDLE) {
  55. snprintf(buf, buflen, "[STATE_IDLE]");
  56. goto done;
  57. }
  58. buf[0] = '\0';
  59. for (i = 0; i < ARRAY_SIZE(states); i++) {
  60. if (!(state & (1 << i)))
  61. continue;
  62. cnt = snprintf(buf, buflen - cnt - 1, "%s%s%s", buf,
  63. buf[0] == '\0' ? "[" : "|",
  64. states[i]);
  65. }
  66. if (cnt > 0)
  67. strlcat(buf + cnt, "]", buflen);
  68. done:
  69. if (buf[0] == '\0')
  70. snprintf(buf, buflen, "[STATE_UNKNOWN]");
  71. return buf;
  72. }
  73. static inline int wcd_clsh_get_int_mode(struct wcd_clsh_cdc_info *clsh_d,
  74. int clsh_state)
  75. {
  76. int mode;
  77. if ((clsh_state != WCD_CLSH_STATE_EAR) &&
  78. (clsh_state != WCD_CLSH_STATE_HPHL) &&
  79. (clsh_state != WCD_CLSH_STATE_HPHR) &&
  80. (clsh_state != WCD_CLSH_STATE_AUX))
  81. mode = CLS_NONE;
  82. else
  83. mode = clsh_d->interpolator_modes[ffs(clsh_state)];
  84. return mode;
  85. }
  86. static inline void wcd_clsh_set_int_mode(struct wcd_clsh_cdc_info *clsh_d,
  87. int clsh_state, int mode)
  88. {
  89. if ((clsh_state != WCD_CLSH_STATE_EAR) &&
  90. (clsh_state != WCD_CLSH_STATE_HPHL) &&
  91. (clsh_state != WCD_CLSH_STATE_HPHR) &&
  92. (clsh_state != WCD_CLSH_STATE_AUX))
  93. return;
  94. clsh_d->interpolator_modes[ffs(clsh_state)] = mode;
  95. }
  96. static inline void wcd_clsh_set_buck_mode(struct snd_soc_component *component,
  97. int mode)
  98. {
  99. if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI ||
  100. mode == CLS_AB_HIFI || mode == CLS_AB_LOHIFI)
  101. snd_soc_component_update_bits(component,
  102. WCD9XXX_ANA_RX_SUPPLIES,
  103. 0x08, 0x08); /* set to HIFI */
  104. else
  105. snd_soc_component_update_bits(component,
  106. WCD9XXX_ANA_RX_SUPPLIES,
  107. 0x08, 0x00); /* set to default */
  108. }
  109. static inline void wcd_clsh_set_flyback_mode(
  110. struct snd_soc_component *component,
  111. int mode)
  112. {
  113. if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI ||
  114. mode == CLS_AB_HIFI || mode == CLS_AB_LOHIFI) {
  115. snd_soc_component_update_bits(component,
  116. WCD9XXX_ANA_RX_SUPPLIES,
  117. 0x04, 0x04);
  118. snd_soc_component_update_bits(component,
  119. WCD9XXX_FLYBACK_VNEG_CTRL_4,
  120. 0xF0, 0x80);
  121. } else {
  122. snd_soc_component_update_bits(component,
  123. WCD9XXX_ANA_RX_SUPPLIES,
  124. 0x04, 0x00); /* set to Default */
  125. snd_soc_component_update_bits(component,
  126. WCD9XXX_FLYBACK_VNEG_CTRL_4,
  127. 0xF0, 0x70);
  128. }
  129. }
  130. static inline void wcd_clsh_force_iq_ctl(struct snd_soc_component *component,
  131. int mode, bool enable)
  132. {
  133. if (enable) {
  134. snd_soc_component_update_bits(component,
  135. WCD9XXX_FLYBACK_VNEGDAC_CTRL_2,
  136. 0xE0, 0xA0);
  137. /* 100usec delay is needed as per HW requirement */
  138. usleep_range(100, 110);
  139. snd_soc_component_update_bits(component,
  140. WCD9XXX_CLASSH_MODE_3,
  141. 0x02, 0x02);
  142. snd_soc_component_update_bits(component,
  143. WCD9XXX_CLASSH_MODE_2,
  144. 0xFF, 0x1C);
  145. if (mode == CLS_H_LOHIFI || mode == CLS_AB_LOHIFI) {
  146. snd_soc_component_update_bits(component,
  147. WCD9XXX_HPH_NEW_INT_PA_MISC2,
  148. 0x20, 0x20);
  149. snd_soc_component_update_bits(component,
  150. WCD9XXX_RX_BIAS_HPH_LOWPOWER,
  151. 0xF0, 0xC0);
  152. snd_soc_component_update_bits(component,
  153. WCD9XXX_HPH_PA_CTL1,
  154. 0x0E, 0x02);
  155. }
  156. } else {
  157. snd_soc_component_update_bits(component,
  158. WCD9XXX_HPH_NEW_INT_PA_MISC2,
  159. 0x20, 0x00);
  160. snd_soc_component_update_bits(component,
  161. WCD9XXX_RX_BIAS_HPH_LOWPOWER,
  162. 0xF0, 0x80);
  163. snd_soc_component_update_bits(component,
  164. WCD9XXX_HPH_PA_CTL1,
  165. 0x0E, 0x06);
  166. }
  167. }
  168. static void wcd_clsh_buck_ctrl(struct snd_soc_component *component,
  169. struct wcd_clsh_cdc_info *clsh_d,
  170. int mode,
  171. bool enable)
  172. {
  173. /* enable/disable buck */
  174. if ((enable && (++clsh_d->buck_users == 1)) ||
  175. (!enable && (--clsh_d->buck_users == 0))) {
  176. snd_soc_component_update_bits(component,
  177. WCD9XXX_ANA_RX_SUPPLIES,
  178. (1 << 7), (enable << 7));
  179. /*
  180. * 500us sleep is required after buck enable/disable
  181. * as per HW requirement
  182. */
  183. usleep_range(500, 510);
  184. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  185. mode == CLS_H_HIFI || mode == CLS_H_LP)
  186. snd_soc_component_update_bits(component,
  187. WCD9XXX_CLASSH_MODE_3,
  188. 0x02, 0x00);
  189. snd_soc_component_update_bits(component,
  190. WCD9XXX_CLASSH_MODE_2,
  191. 0xFF, 0x3A);
  192. /* 500usec delay is needed as per HW requirement */
  193. usleep_range(500, 500 + WCD_USLEEP_RANGE);
  194. }
  195. dev_dbg(component->dev, "%s: buck_users %d, enable %d, mode: %s\n",
  196. __func__, clsh_d->buck_users, enable, mode_to_str(mode));
  197. }
  198. static void wcd_clsh_flyback_ctrl(struct snd_soc_component *component,
  199. struct wcd_clsh_cdc_info *clsh_d,
  200. int mode,
  201. bool enable)
  202. {
  203. /* enable/disable flyback */
  204. if ((enable && (++clsh_d->flyback_users == 1)) ||
  205. (!enable && (--clsh_d->flyback_users == 0))) {
  206. snd_soc_component_update_bits(component,
  207. WCD9XXX_FLYBACK_VNEG_CTRL_1,
  208. 0xE0, 0xE0);
  209. snd_soc_component_update_bits(component,
  210. WCD9XXX_ANA_RX_SUPPLIES,
  211. (1 << 6), (enable << 6));
  212. /*
  213. * 100us sleep is required after flyback enable/disable
  214. * as per HW requirement
  215. */
  216. usleep_range(100, 110);
  217. snd_soc_component_update_bits(component,
  218. WCD9XXX_FLYBACK_VNEGDAC_CTRL_2,
  219. 0xE0, 0xE0);
  220. /* 500usec delay is needed as per HW requirement */
  221. usleep_range(500, 500 + WCD_USLEEP_RANGE);
  222. }
  223. dev_dbg(component->dev, "%s: flyback_users %d, enable %d, mode: %s\n",
  224. __func__, clsh_d->flyback_users, enable, mode_to_str(mode));
  225. }
  226. /*
  227. * Function: wcd_clsh_set_hph_mode
  228. * Params: soc component, hph mode class
  229. * Description:
  230. * This function updates class H mode configuration based on
  231. * the input mode.
  232. */
  233. void wcd_clsh_set_hph_mode(struct snd_soc_component *component,
  234. int mode)
  235. {
  236. u8 val = 0;
  237. switch (mode) {
  238. case CLS_H_NORMAL:
  239. val = 0x00;
  240. break;
  241. case CLS_AB:
  242. case CLS_H_ULP:
  243. val = 0x0C;
  244. break;
  245. case CLS_AB_HIFI:
  246. case CLS_H_HIFI:
  247. val = 0x08;
  248. break;
  249. case CLS_H_LP:
  250. case CLS_H_LOHIFI:
  251. case CLS_AB_LP:
  252. case CLS_AB_LOHIFI:
  253. val = 0x04;
  254. break;
  255. default:
  256. dev_err(component->dev, "%s:Invalid mode %d\n", __func__, mode);
  257. return;
  258. };
  259. snd_soc_component_update_bits(component, WCD9XXX_ANA_HPH, 0x0C, val);
  260. }
  261. EXPORT_SYMBOL(wcd_clsh_set_hph_mode);
  262. static void wcd_clsh_set_flyback_current(struct snd_soc_component *component,
  263. int mode)
  264. {
  265. snd_soc_component_update_bits(component, WCD9XXX_RX_BIAS_FLYB_BUFF,
  266. 0x0F, 0x0A);
  267. snd_soc_component_update_bits(component, WCD9XXX_RX_BIAS_FLYB_BUFF,
  268. 0xF0, 0xA0);
  269. /* Sleep needed to avoid click and pop as per HW requirement */
  270. usleep_range(100, 110);
  271. }
  272. static void wcd_clsh_set_buck_regulator_mode(
  273. struct snd_soc_component *component,
  274. int mode)
  275. {
  276. snd_soc_component_update_bits(component, WCD9XXX_ANA_RX_SUPPLIES,
  277. 0x02, 0x00);
  278. }
  279. static void wcd_clsh_state_ear_aux(struct snd_soc_component *component,
  280. struct wcd_clsh_cdc_info *clsh_d,
  281. u8 req_state, bool is_enable, int mode)
  282. {
  283. dev_dbg(component->dev, "%s: mode: %s, %s\n", __func__,
  284. mode_to_str(mode), is_enable ? "enable" : "disable");
  285. }
  286. static void wcd_clsh_state_hph_aux(struct snd_soc_component *component,
  287. struct wcd_clsh_cdc_info *clsh_d,
  288. u8 req_state, bool is_enable, int mode)
  289. {
  290. dev_dbg(component->dev, "%s: mode: %s, %s\n", __func__,
  291. mode_to_str(mode), is_enable ? "enable" : "disable");
  292. }
  293. static void wcd_clsh_state_hph_ear(struct snd_soc_component *component,
  294. struct wcd_clsh_cdc_info *clsh_d,
  295. u8 req_state, bool is_enable, int mode)
  296. {
  297. dev_dbg(component->dev, "%s: mode: %s, %s\n", __func__,
  298. mode_to_str(mode), is_enable ? "enable" : "disable");
  299. }
  300. static void wcd_clsh_state_hph_st(struct snd_soc_component *component,
  301. struct wcd_clsh_cdc_info *clsh_d,
  302. u8 req_state, bool is_enable, int mode)
  303. {
  304. dev_dbg(component->dev, "%s: mode: %s, %s\n", __func__,
  305. mode_to_str(mode), is_enable ? "enable" : "disable");
  306. }
  307. static void wcd_clsh_state_hph_r(struct snd_soc_component *component,
  308. struct wcd_clsh_cdc_info *clsh_d,
  309. u8 req_state, bool is_enable, int mode)
  310. {
  311. dev_dbg(component->dev, "%s: mode: %s, %s\n", __func__,
  312. mode_to_str(mode), is_enable ? "enable" : "disable");
  313. if (mode == CLS_H_NORMAL) {
  314. dev_dbg(component->dev, "%s: Normal mode not applicable for hph_r\n",
  315. __func__);
  316. return;
  317. }
  318. if (is_enable) {
  319. wcd_clsh_set_buck_regulator_mode(component, mode);
  320. wcd_clsh_set_flyback_mode(component, mode);
  321. wcd_clsh_force_iq_ctl(component, mode, true);
  322. wcd_clsh_flyback_ctrl(component, clsh_d, mode, true);
  323. wcd_clsh_set_flyback_current(component, mode);
  324. wcd_clsh_set_buck_mode(component, mode);
  325. wcd_clsh_buck_ctrl(component, clsh_d, mode, true);
  326. wcd_clsh_set_hph_mode(component, mode);
  327. } else {
  328. wcd_clsh_set_hph_mode(component, CLS_H_NORMAL);
  329. /* buck and flyback set to default mode and disable */
  330. wcd_clsh_flyback_ctrl(component, clsh_d, CLS_H_NORMAL, false);
  331. wcd_clsh_buck_ctrl(component, clsh_d, CLS_H_NORMAL, false);
  332. wcd_clsh_force_iq_ctl(component, CLS_H_NORMAL, false);
  333. wcd_clsh_set_flyback_mode(component, CLS_H_NORMAL);
  334. wcd_clsh_set_buck_mode(component, CLS_H_NORMAL);
  335. }
  336. }
  337. static void wcd_clsh_state_hph_l(struct snd_soc_component *component,
  338. struct wcd_clsh_cdc_info *clsh_d,
  339. u8 req_state, bool is_enable, int mode)
  340. {
  341. dev_dbg(component->dev, "%s: mode: %s, %s\n", __func__,
  342. mode_to_str(mode), is_enable ? "enable" : "disable");
  343. if (mode == CLS_H_NORMAL) {
  344. dev_dbg(component->dev, "%s: Normal mode not applicable for hph_l\n",
  345. __func__);
  346. return;
  347. }
  348. if (is_enable) {
  349. wcd_clsh_set_buck_regulator_mode(component, mode);
  350. wcd_clsh_set_flyback_mode(component, mode);
  351. wcd_clsh_force_iq_ctl(component, mode, true);
  352. wcd_clsh_flyback_ctrl(component, clsh_d, mode, true);
  353. wcd_clsh_set_flyback_current(component, mode);
  354. wcd_clsh_set_buck_mode(component, mode);
  355. wcd_clsh_buck_ctrl(component, clsh_d, mode, true);
  356. wcd_clsh_set_hph_mode(component, mode);
  357. } else {
  358. wcd_clsh_set_hph_mode(component, CLS_H_NORMAL);
  359. /* set buck and flyback to Default Mode */
  360. wcd_clsh_flyback_ctrl(component, clsh_d, CLS_H_NORMAL, false);
  361. wcd_clsh_buck_ctrl(component, clsh_d, CLS_H_NORMAL, false);
  362. wcd_clsh_force_iq_ctl(component, CLS_H_NORMAL, false);
  363. wcd_clsh_set_flyback_mode(component, CLS_H_NORMAL);
  364. wcd_clsh_set_buck_mode(component, CLS_H_NORMAL);
  365. }
  366. }
  367. static void wcd_clsh_state_aux(struct snd_soc_component *component,
  368. struct wcd_clsh_cdc_info *clsh_d,
  369. u8 req_state, bool is_enable, int mode)
  370. {
  371. dev_dbg(component->dev, "%s: mode: %s, %s\n", __func__,
  372. mode_to_str(mode), is_enable ? "enable" : "disable");
  373. if (is_enable) {
  374. wcd_clsh_set_buck_mode(component, mode);
  375. wcd_clsh_set_flyback_mode(component, mode);
  376. wcd_clsh_flyback_ctrl(component, clsh_d, mode, true);
  377. wcd_clsh_set_flyback_current(component, mode);
  378. wcd_clsh_buck_ctrl(component, clsh_d, mode, true);
  379. } else {
  380. wcd_clsh_buck_ctrl(component, clsh_d, mode, false);
  381. wcd_clsh_flyback_ctrl(component, clsh_d, mode, false);
  382. wcd_clsh_set_flyback_mode(component, CLS_H_NORMAL);
  383. wcd_clsh_set_buck_mode(component, CLS_H_NORMAL);
  384. }
  385. }
  386. static void wcd_clsh_state_ear(struct snd_soc_component *component,
  387. struct wcd_clsh_cdc_info *clsh_d,
  388. u8 req_state, bool is_enable, int mode)
  389. {
  390. dev_dbg(component->dev, "%s: mode: %s, %s\n", __func__,
  391. mode_to_str(mode),
  392. is_enable ? "enable" : "disable");
  393. if (is_enable) {
  394. wcd_clsh_set_buck_regulator_mode(component, mode);
  395. wcd_clsh_set_flyback_mode(component, mode);
  396. wcd_clsh_force_iq_ctl(component, mode, true);
  397. wcd_clsh_flyback_ctrl(component, clsh_d, mode, true);
  398. wcd_clsh_set_flyback_current(component, mode);
  399. wcd_clsh_set_buck_mode(component, mode);
  400. wcd_clsh_buck_ctrl(component, clsh_d, mode, true);
  401. wcd_clsh_set_hph_mode(component, mode);
  402. } else {
  403. wcd_clsh_set_hph_mode(component, CLS_H_NORMAL);
  404. /* set buck and flyback to Default Mode */
  405. wcd_clsh_flyback_ctrl(component, clsh_d, CLS_H_NORMAL, false);
  406. wcd_clsh_buck_ctrl(component, clsh_d, CLS_H_NORMAL, false);
  407. wcd_clsh_force_iq_ctl(component, CLS_H_NORMAL, false);
  408. wcd_clsh_set_flyback_mode(component, CLS_H_NORMAL);
  409. wcd_clsh_set_buck_mode(component, CLS_H_NORMAL);
  410. }
  411. }
  412. static void wcd_clsh_state_err(struct snd_soc_component *component,
  413. struct wcd_clsh_cdc_info *clsh_d,
  414. u8 req_state, bool is_enable, int mode)
  415. {
  416. char msg[128];
  417. dev_err(component->dev,
  418. "%s Wrong request for class H state machine requested to %s %s\n",
  419. __func__, is_enable ? "enable" : "disable",
  420. state_to_str(req_state, msg, sizeof(msg)));
  421. }
  422. /*
  423. * Function: wcd_clsh_is_state_valid
  424. * Params: state
  425. * Description:
  426. * Provides information on valid states of Class H configuration
  427. */
  428. static bool wcd_clsh_is_state_valid(u8 state)
  429. {
  430. switch (state) {
  431. case WCD_CLSH_STATE_IDLE:
  432. case WCD_CLSH_STATE_EAR:
  433. case WCD_CLSH_STATE_HPHL:
  434. case WCD_CLSH_STATE_HPHR:
  435. case WCD_CLSH_STATE_HPH_ST:
  436. case WCD_CLSH_STATE_AUX:
  437. case WCD_CLSH_STATE_HPHL_AUX:
  438. case WCD_CLSH_STATE_HPHR_AUX:
  439. case WCD_CLSH_STATE_HPH_ST_AUX:
  440. case WCD_CLSH_STATE_EAR_AUX:
  441. case WCD_CLSH_STATE_HPHL_EAR:
  442. case WCD_CLSH_STATE_HPHR_EAR:
  443. case WCD_CLSH_STATE_HPH_ST_EAR:
  444. return true;
  445. default:
  446. return false;
  447. };
  448. }
  449. /*
  450. * Function: wcd_cls_h_fsm
  451. * Params: component, cdc_clsh_d, req_state, req_type, clsh_event
  452. * Description:
  453. * This function handles PRE DAC and POST DAC conditions of different devices
  454. * and updates class H configuration of different combination of devices
  455. * based on validity of their states. cdc_clsh_d will contain current
  456. * class h state information
  457. */
  458. void wcd_cls_h_fsm(struct snd_soc_component *component,
  459. struct wcd_clsh_cdc_info *cdc_clsh_d,
  460. u8 clsh_event, u8 req_state,
  461. int int_mode)
  462. {
  463. u8 old_state, new_state;
  464. char msg0[128], msg1[128];
  465. switch (clsh_event) {
  466. case WCD_CLSH_EVENT_PRE_DAC:
  467. old_state = cdc_clsh_d->state;
  468. new_state = old_state | req_state;
  469. if (!wcd_clsh_is_state_valid(new_state)) {
  470. dev_err(component->dev,
  471. "%s: Class-H not a valid new state: %s\n",
  472. __func__,
  473. state_to_str(new_state, msg0, sizeof(msg0)));
  474. return;
  475. }
  476. if (new_state == old_state) {
  477. dev_err(component->dev,
  478. "%s: Class-H already in requested state: %s\n",
  479. __func__,
  480. state_to_str(new_state, msg0, sizeof(msg0)));
  481. return;
  482. }
  483. cdc_clsh_d->state = new_state;
  484. wcd_clsh_set_int_mode(cdc_clsh_d, req_state, int_mode);
  485. (*clsh_state_fp[new_state]) (component, cdc_clsh_d, req_state,
  486. CLSH_REQ_ENABLE, int_mode);
  487. dev_dbg(component->dev,
  488. "%s: ClassH state transition from %s to %s\n",
  489. __func__, state_to_str(old_state, msg0, sizeof(msg0)),
  490. state_to_str(cdc_clsh_d->state, msg1, sizeof(msg1)));
  491. break;
  492. case WCD_CLSH_EVENT_POST_PA:
  493. old_state = cdc_clsh_d->state;
  494. new_state = old_state & (~req_state);
  495. if (new_state < NUM_CLSH_STATES) {
  496. if (!wcd_clsh_is_state_valid(old_state)) {
  497. dev_err(component->dev,
  498. "%s:Invalid old state:%s\n",
  499. __func__,
  500. state_to_str(old_state, msg0,
  501. sizeof(msg0)));
  502. return;
  503. }
  504. if (new_state == old_state) {
  505. dev_err(component->dev,
  506. "%s: Class-H already in requested state: %s\n",
  507. __func__,
  508. state_to_str(new_state, msg0,
  509. sizeof(msg0)));
  510. return;
  511. }
  512. (*clsh_state_fp[old_state]) (component, cdc_clsh_d,
  513. req_state, CLSH_REQ_DISABLE,
  514. int_mode);
  515. cdc_clsh_d->state = new_state;
  516. wcd_clsh_set_int_mode(cdc_clsh_d, req_state, CLS_NONE);
  517. dev_dbg(component->dev, "%s: ClassH state transition from %s to %s\n",
  518. __func__, state_to_str(old_state, msg0,
  519. sizeof(msg0)),
  520. state_to_str(cdc_clsh_d->state, msg1,
  521. sizeof(msg1)));
  522. }
  523. break;
  524. };
  525. }
  526. EXPORT_SYMBOL(wcd_cls_h_fsm);
  527. /*
  528. * wcd_cls_h_init: Called to init clsh info
  529. *
  530. * @clsh: pointer for clsh state information.
  531. */
  532. void wcd_cls_h_init(struct wcd_clsh_cdc_info *clsh)
  533. {
  534. int i;
  535. clsh->state = WCD_CLSH_STATE_IDLE;
  536. for (i = 0; i < NUM_CLSH_STATES; i++)
  537. clsh_state_fp[i] = wcd_clsh_state_err;
  538. clsh_state_fp[WCD_CLSH_STATE_EAR] = wcd_clsh_state_ear;
  539. clsh_state_fp[WCD_CLSH_STATE_HPHL] = wcd_clsh_state_hph_l;
  540. clsh_state_fp[WCD_CLSH_STATE_HPHR] = wcd_clsh_state_hph_r;
  541. clsh_state_fp[WCD_CLSH_STATE_HPH_ST] = wcd_clsh_state_hph_st;
  542. clsh_state_fp[WCD_CLSH_STATE_AUX] = wcd_clsh_state_aux;
  543. clsh_state_fp[WCD_CLSH_STATE_HPHL_AUX] = wcd_clsh_state_hph_aux;
  544. clsh_state_fp[WCD_CLSH_STATE_HPHR_AUX] = wcd_clsh_state_hph_aux;
  545. clsh_state_fp[WCD_CLSH_STATE_HPH_ST_AUX] =
  546. wcd_clsh_state_hph_aux;
  547. clsh_state_fp[WCD_CLSH_STATE_EAR_AUX] = wcd_clsh_state_ear_aux;
  548. clsh_state_fp[WCD_CLSH_STATE_HPHL_EAR] = wcd_clsh_state_hph_ear;
  549. clsh_state_fp[WCD_CLSH_STATE_HPHR_EAR] = wcd_clsh_state_hph_ear;
  550. clsh_state_fp[WCD_CLSH_STATE_HPH_ST_EAR] = wcd_clsh_state_hph_ear;
  551. /* Set interpolaotr modes to NONE */
  552. wcd_clsh_set_int_mode(clsh, WCD_CLSH_STATE_EAR, CLS_NONE);
  553. wcd_clsh_set_int_mode(clsh, WCD_CLSH_STATE_HPHL, CLS_NONE);
  554. wcd_clsh_set_int_mode(clsh, WCD_CLSH_STATE_HPHR, CLS_NONE);
  555. wcd_clsh_set_int_mode(clsh, WCD_CLSH_STATE_AUX, CLS_NONE);
  556. clsh->flyback_users = 0;
  557. clsh->buck_users = 0;
  558. }
  559. EXPORT_SYMBOL(wcd_cls_h_init);
  560. MODULE_DESCRIPTION("WCD Class-H Driver");
  561. MODULE_LICENSE("GPL v2");