cam_soc_util.c 95 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/of.h>
  7. #include <linux/clk.h>
  8. #include <linux/slab.h>
  9. #include <linux/gpio.h>
  10. #include <linux/of_gpio.h>
  11. #include "cam_soc_util.h"
  12. #include "cam_debug_util.h"
  13. #include "cam_cx_ipeak.h"
  14. #include "cam_mem_mgr.h"
  15. #include "cam_presil_hw_access.h"
  16. #include "cam_compat.h"
  17. #define CAM_TO_MASK(bitn) (1 << (int)(bitn))
  18. #define CAM_IS_BIT_SET(mask, bit) ((mask) & CAM_TO_MASK(bit))
  19. #define CAM_SET_BIT(mask, bit) ((mask) |= CAM_TO_MASK(bit))
  20. #define CAM_CLEAR_BIT(mask, bit) ((mask) &= ~CAM_TO_MASK(bit))
  21. #define CAM_SS_START_PRESIL 0x08c00000
  22. #define CAM_SS_START 0x0ac00000
  23. #define CAM_CLK_DIRNAME "clk"
  24. static uint skip_mmrm_set_rate;
  25. module_param(skip_mmrm_set_rate, uint, 0644);
  26. /**
  27. * struct cam_clk_wrapper_clk: This represents an entry corresponding to a
  28. * shared clock in Clk wrapper. Clients that share
  29. * the same clock are registered to this clk entry
  30. * and set rate from them is consolidated before
  31. * setting it to clk driver.
  32. *
  33. * @list: List pointer to point to next shared clk entry
  34. * @clk_id: Clk Id of this clock
  35. * @curr_clk_rate: Current clock rate set for this clock
  36. * @client_list: List of clients registered to this shared clock entry
  37. * @num_clients: Number of registered clients
  38. * @active_clients: Number of active clients
  39. * @mmrm_client: MMRM Client handle for src clock
  40. * @soc_info: soc_info of client with which mmrm handle is created.
  41. * This is used as unique identifier for a client and mmrm
  42. * callback data. When client corresponds to this soc_info is
  43. * unregistered, need to unregister mmrm handle as well.
  44. * @is_nrt_dev: Whether this clock corresponds to NRT device
  45. * @min_clk_rate: Minimum clk rate that this clock supports
  46. **/
  47. struct cam_clk_wrapper_clk {
  48. struct list_head list;
  49. uint32_t clk_id;
  50. int64_t curr_clk_rate;
  51. struct list_head client_list;
  52. uint32_t num_clients;
  53. uint32_t active_clients;
  54. void *mmrm_handle;
  55. struct cam_hw_soc_info *soc_info;
  56. bool is_nrt_dev;
  57. int64_t min_clk_rate;
  58. };
  59. /**
  60. * struct cam_clk_wrapper_client: This represents a client (device) that wants
  61. * to share the clock with some other client.
  62. *
  63. * @list: List pointer to point to next client that share the
  64. * same clock
  65. * @soc_info: soc_info of client. This is used as unique identifier
  66. * for a client
  67. * @clk: Clk handle
  68. * @curr_clk_rate: Current clock rate set for this client
  69. **/
  70. struct cam_clk_wrapper_client {
  71. struct list_head list;
  72. struct cam_hw_soc_info *soc_info;
  73. struct clk *clk;
  74. int64_t curr_clk_rate;
  75. };
  76. static char supported_clk_info[256];
  77. static DEFINE_MUTEX(wrapper_lock);
  78. static LIST_HEAD(wrapper_clk_list);
  79. #if IS_REACHABLE(CONFIG_MSM_MMRM)
  80. bool cam_is_mmrm_supported_on_current_chip(void)
  81. {
  82. bool is_supported;
  83. is_supported = mmrm_client_check_scaling_supported(MMRM_CLIENT_CLOCK,
  84. MMRM_CLIENT_DOMAIN_CAMERA);
  85. CAM_DBG(CAM_UTIL, "is mmrm supported: %s",
  86. CAM_BOOL_TO_YESNO(is_supported));;
  87. return is_supported;
  88. }
  89. int cam_mmrm_notifier_callback(
  90. struct mmrm_client_notifier_data *notifier_data)
  91. {
  92. if (!notifier_data) {
  93. CAM_ERR(CAM_UTIL, "Invalid notifier data");
  94. return -EBADR;
  95. }
  96. if (notifier_data->cb_type == MMRM_CLIENT_RESOURCE_VALUE_CHANGE) {
  97. struct cam_hw_soc_info *soc_info = notifier_data->pvt_data;
  98. CAM_WARN(CAM_UTIL, "Dev %s Clk %s value change from %ld to %ld",
  99. soc_info->dev_name,
  100. (soc_info->src_clk_idx == -1) ? "No src clk" :
  101. soc_info->clk_name[soc_info->src_clk_idx],
  102. notifier_data->cb_data.val_chng.old_val,
  103. notifier_data->cb_data.val_chng.new_val);
  104. }
  105. return 0;
  106. }
  107. int cam_soc_util_register_mmrm_client(
  108. uint32_t clk_id, struct clk *clk, bool is_nrt_dev,
  109. struct cam_hw_soc_info *soc_info, const char *clk_name,
  110. void **mmrm_handle)
  111. {
  112. struct mmrm_client *mmrm_client;
  113. struct mmrm_client_desc desc = { };
  114. if (!mmrm_handle) {
  115. CAM_ERR(CAM_UTIL, "Invalid mmrm input");
  116. return -EINVAL;
  117. }
  118. *mmrm_handle = (void *)NULL;
  119. if (!cam_is_mmrm_supported_on_current_chip())
  120. return 0;
  121. desc.client_type = MMRM_CLIENT_CLOCK;
  122. desc.client_info.desc.client_domain = MMRM_CLIENT_DOMAIN_CAMERA;
  123. desc.client_info.desc.client_id = clk_id;
  124. desc.client_info.desc.clk = clk;
  125. snprintf((char *)desc.client_info.desc.name,
  126. sizeof(desc.client_info.desc.name), "%s_%s",
  127. soc_info->dev_name, clk_name);
  128. desc.priority = is_nrt_dev ?
  129. MMRM_CLIENT_PRIOR_LOW : MMRM_CLIENT_PRIOR_HIGH;
  130. desc.pvt_data = soc_info;
  131. desc.notifier_callback_fn = cam_mmrm_notifier_callback;
  132. mmrm_client = mmrm_client_register(&desc);
  133. if (!mmrm_client) {
  134. CAM_ERR(CAM_UTIL, "MMRM Register failed Dev %s clk %s id %d",
  135. soc_info->dev_name, clk_name, clk_id);
  136. return -EINVAL;
  137. }
  138. CAM_DBG(CAM_UTIL,
  139. "MMRM Register success Dev %s is_nrt_dev %d clk %s id %d handle=%pK",
  140. soc_info->dev_name, is_nrt_dev, clk_name, clk_id, mmrm_client);
  141. *mmrm_handle = (void *)mmrm_client;
  142. return 0;
  143. }
  144. int cam_soc_util_unregister_mmrm_client(
  145. void *mmrm_handle)
  146. {
  147. int rc = 0;
  148. CAM_DBG(CAM_UTIL, "MMRM UnRegister handle=%pK", mmrm_handle);
  149. if (mmrm_handle) {
  150. rc = mmrm_client_deregister((struct mmrm_client *)mmrm_handle);
  151. if (rc)
  152. CAM_ERR(CAM_UTIL,
  153. "Failed in deregister handle=%pK, rc %d",
  154. mmrm_handle, rc);
  155. }
  156. return rc;
  157. }
  158. static int cam_soc_util_set_rate_through_mmrm(
  159. void *mmrm_handle, bool is_nrt_dev, long min_rate,
  160. long req_rate, uint32_t num_hw_blocks)
  161. {
  162. int rc = 0;
  163. struct mmrm_client_data client_data;
  164. struct mmrm_client_res_value val;
  165. client_data.num_hw_blocks = num_hw_blocks;
  166. client_data.flags = 0;
  167. CAM_DBG(CAM_UTIL,
  168. "mmrm=%pK, nrt=%d, min_rate=%ld req_rate %ld, num_blocks=%d",
  169. mmrm_handle, is_nrt_dev, min_rate, req_rate, num_hw_blocks);
  170. if (is_nrt_dev) {
  171. val.min = min_rate;
  172. val.cur = req_rate;
  173. rc = mmrm_client_set_value_in_range(
  174. (struct mmrm_client *)mmrm_handle, &client_data, &val);
  175. } else {
  176. rc = mmrm_client_set_value(
  177. (struct mmrm_client *)mmrm_handle,
  178. &client_data, req_rate);
  179. }
  180. if (rc)
  181. CAM_ERR(CAM_UTIL, "Set rate failed rate %ld rc %d",
  182. req_rate, rc);
  183. return rc;
  184. }
  185. #else
  186. int cam_soc_util_register_mmrm_client(
  187. uint32_t clk_id, struct clk *clk, bool is_nrt_dev,
  188. struct cam_hw_soc_info *soc_info, const char *clk_name,
  189. void **mmrm_handle)
  190. {
  191. if (!mmrm_handle) {
  192. CAM_ERR(CAM_UTIL, "Invalid mmrm input");
  193. return -EINVAL;
  194. }
  195. *mmrm_handle = NULL;
  196. return 0;
  197. }
  198. int cam_soc_util_unregister_mmrm_client(
  199. void *mmrm_handle)
  200. {
  201. return 0;
  202. }
  203. static int cam_soc_util_set_rate_through_mmrm(
  204. void *mmrm_handle, bool is_nrt_dev, long min_rate,
  205. long req_rate, uint32_t num_hw_blocks)
  206. {
  207. return 0;
  208. }
  209. #endif
  210. static int cam_soc_util_clk_wrapper_register_entry(
  211. uint32_t clk_id, struct clk *clk, bool is_src_clk,
  212. struct cam_hw_soc_info *soc_info, int64_t min_clk_rate,
  213. const char *clk_name)
  214. {
  215. struct cam_clk_wrapper_clk *wrapper_clk;
  216. struct cam_clk_wrapper_client *wrapper_client;
  217. bool clock_found = false;
  218. int rc = 0;
  219. mutex_lock(&wrapper_lock);
  220. list_for_each_entry(wrapper_clk, &wrapper_clk_list, list) {
  221. CAM_DBG(CAM_UTIL, "Clk list id %d num clients %d",
  222. wrapper_clk->clk_id, wrapper_clk->num_clients);
  223. if (wrapper_clk->clk_id == clk_id) {
  224. clock_found = true;
  225. list_for_each_entry(wrapper_client,
  226. &wrapper_clk->client_list, list) {
  227. CAM_DBG(CAM_UTIL,
  228. "Clk id %d entry client %s",
  229. wrapper_clk->clk_id,
  230. wrapper_client->soc_info->dev_name);
  231. if (wrapper_client->soc_info == soc_info) {
  232. CAM_ERR(CAM_UTIL,
  233. "Register with same soc info, clk id %d, client %s",
  234. clk_id, soc_info->dev_name);
  235. rc = -EINVAL;
  236. goto end;
  237. }
  238. }
  239. break;
  240. }
  241. }
  242. if (!clock_found) {
  243. CAM_DBG(CAM_UTIL, "Adding new entry for clk id %d", clk_id);
  244. wrapper_clk = kzalloc(sizeof(struct cam_clk_wrapper_clk),
  245. GFP_KERNEL);
  246. if (!wrapper_clk) {
  247. CAM_ERR(CAM_UTIL,
  248. "Failed in allocating new clk entry %d",
  249. clk_id);
  250. rc = -ENOMEM;
  251. goto end;
  252. }
  253. wrapper_clk->clk_id = clk_id;
  254. INIT_LIST_HEAD(&wrapper_clk->list);
  255. INIT_LIST_HEAD(&wrapper_clk->client_list);
  256. list_add_tail(&wrapper_clk->list, &wrapper_clk_list);
  257. }
  258. wrapper_client = kzalloc(sizeof(struct cam_clk_wrapper_client),
  259. GFP_KERNEL);
  260. if (!wrapper_client) {
  261. CAM_ERR(CAM_UTIL, "Failed in allocating new client entry %d",
  262. clk_id);
  263. rc = -ENOMEM;
  264. goto end;
  265. }
  266. wrapper_client->soc_info = soc_info;
  267. wrapper_client->clk = clk;
  268. if (is_src_clk && !wrapper_clk->mmrm_handle) {
  269. wrapper_clk->is_nrt_dev = soc_info->is_nrt_dev;
  270. wrapper_clk->min_clk_rate = min_clk_rate;
  271. wrapper_clk->soc_info = soc_info;
  272. rc = cam_soc_util_register_mmrm_client(clk_id, clk,
  273. wrapper_clk->is_nrt_dev, soc_info, clk_name,
  274. &wrapper_clk->mmrm_handle);
  275. if (rc) {
  276. CAM_ERR(CAM_UTIL,
  277. "Failed in register mmrm client Dev %s clk id %d",
  278. soc_info->dev_name, clk_id);
  279. kfree(wrapper_client);
  280. goto end;
  281. }
  282. }
  283. INIT_LIST_HEAD(&wrapper_client->list);
  284. list_add_tail(&wrapper_client->list, &wrapper_clk->client_list);
  285. wrapper_clk->num_clients++;
  286. CAM_DBG(CAM_UTIL,
  287. "Adding new client %s for clk[%s] id %d, num clients %d",
  288. soc_info->dev_name, clk_name, clk_id, wrapper_clk->num_clients);
  289. end:
  290. mutex_unlock(&wrapper_lock);
  291. return rc;
  292. }
  293. static int cam_soc_util_clk_wrapper_unregister_entry(
  294. uint32_t clk_id, struct cam_hw_soc_info *soc_info)
  295. {
  296. struct cam_clk_wrapper_clk *wrapper_clk;
  297. struct cam_clk_wrapper_client *wrapper_client;
  298. bool clock_found = false;
  299. bool client_found = false;
  300. int rc = 0;
  301. mutex_lock(&wrapper_lock);
  302. list_for_each_entry(wrapper_clk, &wrapper_clk_list, list) {
  303. CAM_DBG(CAM_UTIL, "Clk list id %d num clients %d",
  304. wrapper_clk->clk_id, wrapper_clk->num_clients);
  305. if (wrapper_clk->clk_id == clk_id) {
  306. clock_found = true;
  307. list_for_each_entry(wrapper_client,
  308. &wrapper_clk->client_list, list) {
  309. CAM_DBG(CAM_UTIL, "Clk id %d entry client %s",
  310. wrapper_clk->clk_id,
  311. wrapper_client->soc_info->dev_name);
  312. if (wrapper_client->soc_info == soc_info) {
  313. client_found = true;
  314. break;
  315. }
  316. }
  317. break;
  318. }
  319. }
  320. if (!clock_found) {
  321. CAM_ERR(CAM_UTIL, "Shared clk id %d entry not found", clk_id);
  322. rc = -EINVAL;
  323. goto end;
  324. }
  325. if (!client_found) {
  326. CAM_ERR(CAM_UTIL,
  327. "Client %pK for Shared clk id %d entry not found",
  328. soc_info, clk_id);
  329. rc = -EINVAL;
  330. goto end;
  331. }
  332. wrapper_clk->num_clients--;
  333. if (wrapper_clk->mmrm_handle && (wrapper_clk->soc_info == soc_info)) {
  334. cam_soc_util_unregister_mmrm_client(wrapper_clk->mmrm_handle);
  335. wrapper_clk->mmrm_handle = NULL;
  336. wrapper_clk->soc_info = NULL;
  337. }
  338. list_del_init(&wrapper_client->list);
  339. kfree(wrapper_client);
  340. CAM_DBG(CAM_UTIL, "Unregister client %s for clk id %d, num clients %d",
  341. soc_info->dev_name, clk_id, wrapper_clk->num_clients);
  342. if (!wrapper_clk->num_clients) {
  343. list_del_init(&wrapper_clk->list);
  344. kfree(wrapper_clk);
  345. }
  346. end:
  347. mutex_unlock(&wrapper_lock);
  348. return rc;
  349. }
  350. static int cam_soc_util_clk_wrapper_set_clk_rate(
  351. uint32_t clk_id, struct cam_hw_soc_info *soc_info,
  352. struct clk *clk, int64_t clk_rate)
  353. {
  354. struct cam_clk_wrapper_clk *wrapper_clk;
  355. struct cam_clk_wrapper_client *wrapper_client;
  356. bool clk_found = false;
  357. bool client_found = false;
  358. int rc = 0;
  359. int64_t final_clk_rate = 0;
  360. uint32_t active_clients = 0;
  361. if (!soc_info || !clk) {
  362. CAM_ERR(CAM_UTIL, "Invalid param soc_info %pK clk %pK",
  363. soc_info, clk);
  364. return -EINVAL;
  365. }
  366. mutex_lock(&wrapper_lock);
  367. list_for_each_entry(wrapper_clk, &wrapper_clk_list, list) {
  368. CAM_DBG(CAM_UTIL, "Clk list id %d num clients %d",
  369. wrapper_clk->clk_id, wrapper_clk->num_clients);
  370. if (wrapper_clk->clk_id == clk_id) {
  371. clk_found = true;
  372. break;
  373. }
  374. }
  375. if (!clk_found) {
  376. CAM_ERR(CAM_UTIL, "Clk entry not found id %d client %s",
  377. clk_id, soc_info->dev_name);
  378. rc = -EINVAL;
  379. goto end;
  380. }
  381. list_for_each_entry(wrapper_client, &wrapper_clk->client_list, list) {
  382. CAM_DBG(CAM_UTIL, "Clk id %d client %s, clk rate %lld",
  383. wrapper_clk->clk_id, wrapper_client->soc_info->dev_name,
  384. wrapper_client->curr_clk_rate);
  385. if (wrapper_client->soc_info == soc_info) {
  386. client_found = true;
  387. CAM_DBG(CAM_UTIL,
  388. "Clk enable clk id %d, client %s curr %ld new %ld",
  389. clk_id, wrapper_client->soc_info->dev_name,
  390. wrapper_client->curr_clk_rate, clk_rate);
  391. wrapper_client->curr_clk_rate = clk_rate;
  392. }
  393. if (wrapper_client->curr_clk_rate > 0)
  394. active_clients++;
  395. if (final_clk_rate < wrapper_client->curr_clk_rate)
  396. final_clk_rate = wrapper_client->curr_clk_rate;
  397. }
  398. if (!client_found) {
  399. CAM_ERR(CAM_UTIL,
  400. "Wrapper clk enable without client entry clk id %d client %s",
  401. clk_id, soc_info->dev_name);
  402. rc = -EINVAL;
  403. goto end;
  404. }
  405. CAM_DBG(CAM_UTIL,
  406. "Clk id %d, client %s, clients rate %ld, curr %ld final %ld",
  407. wrapper_clk->clk_id, soc_info->dev_name, clk_rate,
  408. wrapper_clk->curr_clk_rate, final_clk_rate);
  409. if ((final_clk_rate != wrapper_clk->curr_clk_rate) ||
  410. (active_clients != wrapper_clk->active_clients)) {
  411. bool set_rate_finish = false;
  412. if (!skip_mmrm_set_rate && wrapper_clk->mmrm_handle) {
  413. rc = cam_soc_util_set_rate_through_mmrm(
  414. wrapper_clk->mmrm_handle,
  415. wrapper_clk->is_nrt_dev,
  416. wrapper_clk->min_clk_rate,
  417. final_clk_rate, active_clients);
  418. if (rc) {
  419. CAM_ERR(CAM_UTIL,
  420. "set_rate through mmrm failed clk_id %d, rate=%ld",
  421. wrapper_clk->clk_id, final_clk_rate);
  422. goto end;
  423. }
  424. set_rate_finish = true;
  425. }
  426. if (!set_rate_finish && final_clk_rate &&
  427. (final_clk_rate != wrapper_clk->curr_clk_rate)) {
  428. rc = clk_set_rate(clk, final_clk_rate);
  429. if (rc) {
  430. CAM_ERR(CAM_UTIL, "set_rate failed on clk %d",
  431. wrapper_clk->clk_id);
  432. goto end;
  433. }
  434. }
  435. wrapper_clk->curr_clk_rate = final_clk_rate;
  436. wrapper_clk->active_clients = active_clients;
  437. }
  438. end:
  439. mutex_unlock(&wrapper_lock);
  440. return rc;
  441. }
  442. int cam_soc_util_get_clk_level(struct cam_hw_soc_info *soc_info,
  443. int64_t clk_rate, int clk_idx, int32_t *clk_lvl)
  444. {
  445. int i;
  446. long clk_rate_round;
  447. if (!soc_info || (clk_idx < 0) || (clk_idx >= CAM_SOC_MAX_CLK)) {
  448. CAM_ERR(CAM_UTIL, "Invalid src_clk_idx: %d", clk_idx);
  449. *clk_lvl = -1;
  450. return -EINVAL;
  451. }
  452. clk_rate_round = clk_round_rate(soc_info->clk[clk_idx], clk_rate);
  453. if (clk_rate_round < 0) {
  454. CAM_ERR(CAM_UTIL, "round failed rc = %ld",
  455. clk_rate_round);
  456. *clk_lvl = -1;
  457. return -EINVAL;
  458. }
  459. for (i = 0; i < CAM_MAX_VOTE; i++) {
  460. if ((soc_info->clk_level_valid[i]) &&
  461. (soc_info->clk_rate[i][clk_idx] >=
  462. clk_rate_round)) {
  463. CAM_DBG(CAM_UTIL,
  464. "soc = %d round rate = %ld actual = %lld",
  465. soc_info->clk_rate[i][clk_idx],
  466. clk_rate_round, clk_rate);
  467. *clk_lvl = i;
  468. return 0;
  469. }
  470. }
  471. CAM_WARN(CAM_UTIL, "Invalid clock rate %ld", clk_rate_round);
  472. *clk_lvl = -1;
  473. return -EINVAL;
  474. }
  475. /**
  476. * cam_soc_util_get_string_from_level()
  477. *
  478. * @brief: Returns the string for a given clk level
  479. *
  480. * @level: Clock level
  481. *
  482. * @return: String corresponding to the clk level
  483. */
  484. static const char *cam_soc_util_get_string_from_level(
  485. enum cam_vote_level level)
  486. {
  487. switch (level) {
  488. case CAM_SUSPEND_VOTE:
  489. return "";
  490. case CAM_MINSVS_VOTE:
  491. return "MINSVS[1]";
  492. case CAM_LOWSVS_VOTE:
  493. return "LOWSVS[2]";
  494. case CAM_SVS_VOTE:
  495. return "SVS[3]";
  496. case CAM_SVSL1_VOTE:
  497. return "SVSL1[4]";
  498. case CAM_NOMINAL_VOTE:
  499. return "NOM[5]";
  500. case CAM_NOMINALL1_VOTE:
  501. return "NOML1[6]";
  502. case CAM_TURBO_VOTE:
  503. return "TURBO[7]";
  504. default:
  505. return "";
  506. }
  507. }
  508. /**
  509. * cam_soc_util_get_supported_clk_levels()
  510. *
  511. * @brief: Returns the string of all the supported clk levels for
  512. * the given device
  513. *
  514. * @soc_info: Device soc information
  515. *
  516. * @return: String containing all supported clk levels
  517. */
  518. static const char *cam_soc_util_get_supported_clk_levels(
  519. struct cam_hw_soc_info *soc_info)
  520. {
  521. int i = 0;
  522. scnprintf(supported_clk_info, sizeof(supported_clk_info), "Supported levels: ");
  523. for (i = 0; i < CAM_MAX_VOTE; i++) {
  524. if (soc_info->clk_level_valid[i] == true) {
  525. strlcat(supported_clk_info,
  526. cam_soc_util_get_string_from_level(i),
  527. sizeof(supported_clk_info));
  528. strlcat(supported_clk_info, " ",
  529. sizeof(supported_clk_info));
  530. }
  531. }
  532. strlcat(supported_clk_info, "\n", sizeof(supported_clk_info));
  533. return supported_clk_info;
  534. }
  535. static int cam_soc_util_clk_lvl_options_open(struct inode *inode,
  536. struct file *file)
  537. {
  538. file->private_data = inode->i_private;
  539. return 0;
  540. }
  541. static ssize_t cam_soc_util_clk_lvl_options_read(struct file *file,
  542. char __user *clk_info, size_t size_t, loff_t *loff_t)
  543. {
  544. struct cam_hw_soc_info *soc_info =
  545. (struct cam_hw_soc_info *)file->private_data;
  546. const char *display_string =
  547. cam_soc_util_get_supported_clk_levels(soc_info);
  548. return simple_read_from_buffer(clk_info, size_t, loff_t, display_string,
  549. strlen(display_string));
  550. }
  551. static const struct file_operations cam_soc_util_clk_lvl_options = {
  552. .open = cam_soc_util_clk_lvl_options_open,
  553. .read = cam_soc_util_clk_lvl_options_read,
  554. };
  555. static int cam_soc_util_set_clk_lvl(void *data, u64 val)
  556. {
  557. struct cam_hw_soc_info *soc_info = (struct cam_hw_soc_info *)data;
  558. if (val <= CAM_SUSPEND_VOTE || val >= CAM_MAX_VOTE)
  559. return 0;
  560. if (soc_info->clk_level_valid[val] == true)
  561. soc_info->clk_level_override = val;
  562. else
  563. soc_info->clk_level_override = 0;
  564. return 0;
  565. }
  566. static int cam_soc_util_get_clk_lvl(void *data, u64 *val)
  567. {
  568. struct cam_hw_soc_info *soc_info = (struct cam_hw_soc_info *)data;
  569. *val = soc_info->clk_level_override;
  570. return 0;
  571. }
  572. DEFINE_SIMPLE_ATTRIBUTE(cam_soc_util_clk_lvl_control,
  573. cam_soc_util_get_clk_lvl, cam_soc_util_set_clk_lvl, "%08llu");
  574. /**
  575. * cam_soc_util_create_clk_lvl_debugfs()
  576. *
  577. * @brief: Creates debugfs files to view/control device clk rates
  578. *
  579. * @soc_info: Device soc information
  580. *
  581. * @return: Success or failure
  582. */
  583. static int cam_soc_util_create_clk_lvl_debugfs(struct cam_hw_soc_info *soc_info)
  584. {
  585. int rc = 0;
  586. struct dentry *dbgfileptr = NULL, *clkdirptr = NULL;
  587. if (!cam_debugfs_available())
  588. return 0;
  589. if (soc_info->dentry) {
  590. CAM_DBG(CAM_UTIL, "Debugfs entry for %s already exists",
  591. soc_info->dev_name);
  592. goto end;
  593. }
  594. rc = cam_debugfs_lookup_subdir(CAM_CLK_DIRNAME, &clkdirptr);
  595. if (rc) {
  596. rc = cam_debugfs_create_subdir(CAM_CLK_DIRNAME, &clkdirptr);
  597. if (rc) {
  598. CAM_ERR(CAM_UTIL, "DebugFS could not create clk directory!");
  599. rc = -ENOENT;
  600. goto end;
  601. }
  602. }
  603. dbgfileptr = debugfs_create_dir(soc_info->dev_name, clkdirptr);
  604. if (IS_ERR_OR_NULL(dbgfileptr)) {
  605. CAM_ERR(CAM_UTIL, "DebugFS could not create directory for dev:%s!",
  606. soc_info->dev_name);
  607. rc = -ENOENT;
  608. goto end;
  609. }
  610. /* Store parent inode for cleanup in caller */
  611. soc_info->dentry = dbgfileptr;
  612. dbgfileptr = debugfs_create_file("clk_lvl_options", 0444,
  613. soc_info->dentry, soc_info, &cam_soc_util_clk_lvl_options);
  614. dbgfileptr = debugfs_create_file("clk_lvl_control", 0644,
  615. soc_info->dentry, soc_info, &cam_soc_util_clk_lvl_control);
  616. rc = PTR_ERR_OR_ZERO(dbgfileptr);
  617. end:
  618. return rc;
  619. }
  620. int cam_soc_util_get_level_from_string(const char *string,
  621. enum cam_vote_level *level)
  622. {
  623. if (!level)
  624. return -EINVAL;
  625. if (!strcmp(string, "suspend")) {
  626. *level = CAM_SUSPEND_VOTE;
  627. } else if (!strcmp(string, "minsvs")) {
  628. *level = CAM_MINSVS_VOTE;
  629. } else if (!strcmp(string, "lowsvs")) {
  630. *level = CAM_LOWSVS_VOTE;
  631. } else if (!strcmp(string, "svs")) {
  632. *level = CAM_SVS_VOTE;
  633. } else if (!strcmp(string, "svs_l1")) {
  634. *level = CAM_SVSL1_VOTE;
  635. } else if (!strcmp(string, "nominal")) {
  636. *level = CAM_NOMINAL_VOTE;
  637. } else if (!strcmp(string, "nominal_l1")) {
  638. *level = CAM_NOMINALL1_VOTE;
  639. } else if (!strcmp(string, "turbo")) {
  640. *level = CAM_TURBO_VOTE;
  641. } else {
  642. CAM_ERR(CAM_UTIL, "Invalid string %s", string);
  643. return -EINVAL;
  644. }
  645. return 0;
  646. }
  647. /**
  648. * cam_soc_util_get_clk_level_to_apply()
  649. *
  650. * @brief: Get the clock level to apply. If the requested level
  651. * is not valid, bump the level to next available valid
  652. * level. If no higher level found, return failure.
  653. *
  654. * @soc_info: Device soc struct to be populated
  655. * @req_level: Requested level
  656. * @apply_level Level to apply
  657. *
  658. * @return: success or failure
  659. */
  660. static int cam_soc_util_get_clk_level_to_apply(
  661. struct cam_hw_soc_info *soc_info, enum cam_vote_level req_level,
  662. enum cam_vote_level *apply_level)
  663. {
  664. if (req_level >= CAM_MAX_VOTE) {
  665. CAM_ERR(CAM_UTIL, "Invalid clock level parameter %d",
  666. req_level);
  667. return -EINVAL;
  668. }
  669. if (soc_info->clk_level_valid[req_level] == true) {
  670. *apply_level = req_level;
  671. } else {
  672. int i;
  673. for (i = (req_level + 1); i < CAM_MAX_VOTE; i++)
  674. if (soc_info->clk_level_valid[i] == true) {
  675. *apply_level = i;
  676. break;
  677. }
  678. if (i == CAM_MAX_VOTE) {
  679. CAM_ERR(CAM_UTIL,
  680. "No valid clock level found to apply, req=%d",
  681. req_level);
  682. return -EINVAL;
  683. }
  684. }
  685. CAM_DBG(CAM_UTIL, "Req level %d, Applying %d",
  686. req_level, *apply_level);
  687. return 0;
  688. }
  689. int cam_soc_util_irq_enable(struct cam_hw_soc_info *soc_info)
  690. {
  691. if (!soc_info) {
  692. CAM_ERR(CAM_UTIL, "Invalid arguments");
  693. return -EINVAL;
  694. }
  695. if (soc_info->irq_num < 0) {
  696. CAM_ERR(CAM_UTIL, "No IRQ line available");
  697. return -ENODEV;
  698. }
  699. enable_irq(soc_info->irq_num);
  700. return 0;
  701. }
  702. int cam_soc_util_irq_disable(struct cam_hw_soc_info *soc_info)
  703. {
  704. if (!soc_info) {
  705. CAM_ERR(CAM_UTIL, "Invalid arguments");
  706. return -EINVAL;
  707. }
  708. if (soc_info->irq_num < 0) {
  709. CAM_ERR(CAM_UTIL, "No IRQ line available");
  710. return -ENODEV;
  711. }
  712. disable_irq(soc_info->irq_num);
  713. return 0;
  714. }
  715. long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info,
  716. uint32_t clk_index, unsigned long clk_rate)
  717. {
  718. if (!soc_info || (clk_index >= soc_info->num_clk) || (clk_rate == 0)) {
  719. CAM_ERR(CAM_UTIL, "Invalid input params %pK, %d %lu",
  720. soc_info, clk_index, clk_rate);
  721. return clk_rate;
  722. }
  723. return clk_round_rate(soc_info->clk[clk_index], clk_rate);
  724. }
  725. /**
  726. * cam_soc_util_set_clk_rate()
  727. *
  728. * @brief: Sets the given rate for the clk requested for
  729. *
  730. * @clk: Clock structure information for which rate is to be set
  731. * @clk_name: Name of the clock for which rate is being set
  732. * @clk_rate: Clock rate to be set
  733. * @shared_clk: Whether this is a shared clk
  734. * @is_src_clk: Whether this is source clk
  735. * @clk_id: Clock ID
  736. * @applied_clk_rate: Final clock rate set to the clk
  737. *
  738. * @return: Success or failure
  739. */
  740. static int cam_soc_util_set_clk_rate(struct cam_hw_soc_info *soc_info,
  741. struct clk *clk, const char *clk_name,
  742. int64_t clk_rate, bool shared_clk, bool is_src_clk, uint32_t clk_id,
  743. unsigned long *applied_clk_rate)
  744. {
  745. int rc = 0;
  746. long clk_rate_round = -1;
  747. bool set_rate = false;
  748. if (!clk || !clk_name) {
  749. CAM_ERR(CAM_UTIL, "Invalid input clk %pK clk_name %pK",
  750. clk, clk_name);
  751. return -EINVAL;
  752. }
  753. CAM_DBG(CAM_UTIL, "set %s, rate %lld", clk_name, clk_rate);
  754. if (clk_rate > 0) {
  755. clk_rate_round = clk_round_rate(clk, clk_rate);
  756. CAM_DBG(CAM_UTIL, "new_rate %ld", clk_rate_round);
  757. if (clk_rate_round < 0) {
  758. CAM_ERR(CAM_UTIL, "round failed for clock %s rc = %ld",
  759. clk_name, clk_rate_round);
  760. return clk_rate_round;
  761. }
  762. set_rate = true;
  763. } else if (clk_rate == INIT_RATE) {
  764. clk_rate_round = clk_get_rate(clk);
  765. CAM_DBG(CAM_UTIL, "init new_rate %ld", clk_rate_round);
  766. if (clk_rate_round == 0) {
  767. clk_rate_round = clk_round_rate(clk, 0);
  768. if (clk_rate_round <= 0) {
  769. CAM_ERR(CAM_UTIL, "round rate failed on %s",
  770. clk_name);
  771. return clk_rate_round;
  772. }
  773. }
  774. set_rate = true;
  775. }
  776. if (set_rate) {
  777. if (shared_clk) {
  778. CAM_DBG(CAM_UTIL,
  779. "Dev %s clk %s id %d Set Shared clk %ld",
  780. soc_info->dev_name, clk_name, clk_id,
  781. clk_rate_round);
  782. cam_soc_util_clk_wrapper_set_clk_rate(
  783. clk_id, soc_info, clk, clk_rate_round);
  784. } else {
  785. bool set_rate_finish = false;
  786. CAM_DBG(CAM_UTIL,
  787. "Dev %s clk %s clk_id %d src_idx %d src_clk_id %d",
  788. soc_info->dev_name, clk_name, clk_id,
  789. soc_info->src_clk_idx,
  790. (soc_info->src_clk_idx == -1) ? -1 :
  791. soc_info->clk_id[soc_info->src_clk_idx]);
  792. if (is_src_clk && soc_info->mmrm_handle &&
  793. !skip_mmrm_set_rate) {
  794. uint32_t idx = soc_info->src_clk_idx;
  795. uint32_t min_level = soc_info->lowest_clk_level;
  796. rc = cam_soc_util_set_rate_through_mmrm(
  797. soc_info->mmrm_handle,
  798. soc_info->is_nrt_dev,
  799. soc_info->clk_rate[min_level][idx],
  800. clk_rate_round, 1);
  801. if (rc) {
  802. CAM_ERR(CAM_UTIL,
  803. "set_rate through mmrm failed on %s clk_id %d, rate=%ld",
  804. clk_name, clk_id,
  805. clk_rate_round);
  806. return rc;
  807. }
  808. set_rate_finish = true;
  809. }
  810. if (!set_rate_finish) {
  811. rc = clk_set_rate(clk, clk_rate_round);
  812. if (rc) {
  813. CAM_ERR(CAM_UTIL, "set_rate failed on %s", clk_name);
  814. return rc;
  815. }
  816. }
  817. }
  818. }
  819. if (applied_clk_rate)
  820. *applied_clk_rate = clk_rate_round;
  821. return rc;
  822. }
  823. int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info,
  824. int64_t clk_rate)
  825. {
  826. int rc = 0;
  827. int i = 0;
  828. int32_t src_clk_idx;
  829. int32_t scl_clk_idx;
  830. struct clk *clk = NULL;
  831. int32_t apply_level;
  832. uint32_t clk_level_override = 0;
  833. if (!soc_info || (soc_info->src_clk_idx < 0) ||
  834. (soc_info->src_clk_idx >= CAM_SOC_MAX_CLK)) {
  835. CAM_ERR(CAM_UTIL, "Invalid src_clk_idx: %d",
  836. soc_info ? soc_info->src_clk_idx : -1);
  837. return -EINVAL;
  838. }
  839. src_clk_idx = soc_info->src_clk_idx;
  840. clk_level_override = soc_info->clk_level_override;
  841. if (clk_level_override && clk_rate)
  842. clk_rate =
  843. soc_info->clk_rate[clk_level_override][src_clk_idx];
  844. clk = soc_info->clk[src_clk_idx];
  845. rc = cam_soc_util_get_clk_level(soc_info, clk_rate, src_clk_idx,
  846. &apply_level);
  847. if (rc || (apply_level < 0) || (apply_level >= CAM_MAX_VOTE)) {
  848. CAM_ERR(CAM_UTIL,
  849. "set %s, rate %lld dev_name = %s apply level = %d",
  850. soc_info->clk_name[src_clk_idx], clk_rate,
  851. soc_info->dev_name, apply_level);
  852. return -EINVAL;
  853. }
  854. CAM_DBG(CAM_UTIL, "set %s, rate %lld dev_name = %s apply level = %d",
  855. soc_info->clk_name[src_clk_idx], clk_rate,
  856. soc_info->dev_name, apply_level);
  857. if ((soc_info->cam_cx_ipeak_enable) && (clk_rate >= 0)) {
  858. cam_cx_ipeak_update_vote_cx_ipeak(soc_info,
  859. apply_level);
  860. }
  861. rc = cam_soc_util_set_clk_rate(soc_info, clk,
  862. soc_info->clk_name[src_clk_idx], clk_rate,
  863. CAM_IS_BIT_SET(soc_info->shared_clk_mask, src_clk_idx),
  864. true, soc_info->clk_id[src_clk_idx],
  865. &soc_info->applied_src_clk_rate);
  866. if (rc) {
  867. CAM_ERR(CAM_UTIL,
  868. "SET_RATE Failed: src clk: %s, rate %lld, dev_name = %s rc: %d",
  869. soc_info->clk_name[src_clk_idx], clk_rate,
  870. soc_info->dev_name, rc);
  871. return rc;
  872. }
  873. /* set clk rate for scalable clk if available */
  874. for (i = 0; i < soc_info->scl_clk_count; i++) {
  875. scl_clk_idx = soc_info->scl_clk_idx[i];
  876. if (scl_clk_idx < 0) {
  877. CAM_DBG(CAM_UTIL, "Scl clk index invalid");
  878. continue;
  879. }
  880. clk = soc_info->clk[scl_clk_idx];
  881. rc = cam_soc_util_set_clk_rate(soc_info, clk,
  882. soc_info->clk_name[scl_clk_idx],
  883. soc_info->clk_rate[apply_level][scl_clk_idx],
  884. CAM_IS_BIT_SET(soc_info->shared_clk_mask, scl_clk_idx),
  885. false, soc_info->clk_id[scl_clk_idx],
  886. NULL);
  887. if (rc) {
  888. CAM_WARN(CAM_UTIL,
  889. "SET_RATE Failed: scl clk: %s, rate %d dev_name = %s, rc: %d",
  890. soc_info->clk_name[scl_clk_idx],
  891. soc_info->clk_rate[apply_level][scl_clk_idx],
  892. soc_info->dev_name, rc);
  893. }
  894. }
  895. return 0;
  896. }
  897. int cam_soc_util_put_optional_clk(struct cam_hw_soc_info *soc_info,
  898. int32_t clk_indx)
  899. {
  900. if (clk_indx < 0) {
  901. CAM_ERR(CAM_UTIL, "Invalid params clk %d", clk_indx);
  902. return -EINVAL;
  903. }
  904. if (CAM_IS_BIT_SET(soc_info->optional_shared_clk_mask, clk_indx))
  905. cam_soc_util_clk_wrapper_unregister_entry(
  906. soc_info->optional_clk_id[clk_indx], soc_info);
  907. clk_put(soc_info->optional_clk[clk_indx]);
  908. soc_info->optional_clk[clk_indx] = NULL;
  909. return 0;
  910. }
  911. static struct clk *cam_soc_util_option_clk_get(struct device_node *np,
  912. int index, uint32_t *clk_id)
  913. {
  914. struct of_phandle_args clkspec;
  915. struct clk *clk;
  916. int rc;
  917. if (index < 0)
  918. return ERR_PTR(-EINVAL);
  919. rc = of_parse_phandle_with_args(np, "clocks-option", "#clock-cells",
  920. index, &clkspec);
  921. if (rc)
  922. return ERR_PTR(rc);
  923. clk = of_clk_get_from_provider(&clkspec);
  924. *clk_id = clkspec.args[0];
  925. of_node_put(clkspec.np);
  926. return clk;
  927. }
  928. int cam_soc_util_get_option_clk_by_name(struct cam_hw_soc_info *soc_info,
  929. const char *clk_name, int32_t *clk_index)
  930. {
  931. int index = 0;
  932. int rc = 0;
  933. struct device_node *of_node = NULL;
  934. uint32_t shared_clk_val;
  935. if (!soc_info || !clk_name || !clk_index) {
  936. CAM_ERR(CAM_UTIL,
  937. "Invalid params soc_info %pK clk_name %s clk_index %pK",
  938. soc_info, clk_name, clk_index);
  939. return -EINVAL;
  940. }
  941. of_node = soc_info->dev->of_node;
  942. index = of_property_match_string(of_node, "clock-names-option",
  943. clk_name);
  944. if (index < 0) {
  945. CAM_DBG(CAM_UTIL, "No clk data for %s", clk_name);
  946. *clk_index = -1;
  947. return -EINVAL;
  948. }
  949. if (index >= CAM_SOC_MAX_OPT_CLK) {
  950. CAM_ERR(CAM_UTIL, "Insufficient optional clk entries %d %d",
  951. index, CAM_SOC_MAX_OPT_CLK);
  952. return -EINVAL;
  953. }
  954. of_property_read_string_index(of_node, "clock-names-option",
  955. index, &(soc_info->optional_clk_name[index]));
  956. soc_info->optional_clk[index] = cam_soc_util_option_clk_get(of_node,
  957. index, &soc_info->optional_clk_id[index]);
  958. if (IS_ERR(soc_info->optional_clk[index])) {
  959. CAM_ERR(CAM_UTIL, "No clk named %s found. Dev %s", clk_name,
  960. soc_info->dev_name);
  961. *clk_index = -1;
  962. return -EFAULT;
  963. }
  964. *clk_index = index;
  965. rc = of_property_read_u32_index(of_node, "clock-rates-option",
  966. index, &soc_info->optional_clk_rate[index]);
  967. if (rc) {
  968. CAM_ERR(CAM_UTIL,
  969. "Error reading clock-rates clk_name %s index %d",
  970. clk_name, index);
  971. goto error;
  972. }
  973. /*
  974. * Option clocks are assumed to be available to single Device here.
  975. * Hence use INIT_RATE instead of NO_SET_RATE.
  976. */
  977. soc_info->optional_clk_rate[index] =
  978. (soc_info->optional_clk_rate[index] == 0) ?
  979. (int32_t)INIT_RATE : soc_info->optional_clk_rate[index];
  980. CAM_DBG(CAM_UTIL, "clk_name %s index %d clk_rate %d",
  981. clk_name, *clk_index, soc_info->optional_clk_rate[index]);
  982. rc = of_property_read_u32_index(of_node, "shared-clks-option",
  983. index, &shared_clk_val);
  984. if (rc) {
  985. CAM_DBG(CAM_UTIL, "Not shared clk %s index %d",
  986. clk_name, index);
  987. } else if (shared_clk_val > 1) {
  988. CAM_WARN(CAM_UTIL, "Invalid shared clk val %d", shared_clk_val);
  989. } else {
  990. CAM_DBG(CAM_UTIL,
  991. "Dev %s shared clk %s index %d, clk id %d, shared_clk_val %d",
  992. soc_info->dev_name, clk_name, index,
  993. soc_info->optional_clk_id[index], shared_clk_val);
  994. if (shared_clk_val) {
  995. CAM_SET_BIT(soc_info->optional_shared_clk_mask, index);
  996. /* Create a wrapper entry if this is a shared clock */
  997. CAM_DBG(CAM_UTIL,
  998. "Dev %s, clk %s, id %d register wrapper entry for shared clk",
  999. soc_info->dev_name,
  1000. soc_info->optional_clk_name[index],
  1001. soc_info->optional_clk_id[index]);
  1002. rc = cam_soc_util_clk_wrapper_register_entry(
  1003. soc_info->optional_clk_id[index],
  1004. soc_info->optional_clk[index], false,
  1005. soc_info,
  1006. soc_info->optional_clk_rate[index],
  1007. soc_info->optional_clk_name[index]);
  1008. if (rc) {
  1009. CAM_ERR(CAM_UTIL,
  1010. "Failed in registering shared clk Dev %s id %d",
  1011. soc_info->dev_name,
  1012. soc_info->optional_clk_id[index]);
  1013. goto error;
  1014. }
  1015. }
  1016. }
  1017. return 0;
  1018. error:
  1019. clk_put(soc_info->optional_clk[index]);
  1020. soc_info->optional_clk_rate[index] = 0;
  1021. soc_info->optional_clk[index] = NULL;
  1022. *clk_index = -1;
  1023. return rc;
  1024. }
  1025. int cam_soc_util_clk_enable(struct cam_hw_soc_info *soc_info,
  1026. bool optional_clk, int32_t clk_idx, int32_t apply_level,
  1027. unsigned long *applied_clock_rate)
  1028. {
  1029. int rc = 0;
  1030. struct clk *clk;
  1031. const char *clk_name;
  1032. int32_t clk_rate;
  1033. uint32_t shared_clk_mask;
  1034. uint32_t clk_id;
  1035. bool is_src_clk = false;
  1036. if (!soc_info || (clk_idx < 0) || (apply_level >= CAM_MAX_VOTE)) {
  1037. CAM_ERR(CAM_UTIL, "Invalid param %d %d", clk_idx, apply_level);
  1038. return -EINVAL;
  1039. }
  1040. if (optional_clk) {
  1041. clk = soc_info->optional_clk[clk_idx];
  1042. clk_name = soc_info->optional_clk_name[clk_idx];
  1043. clk_rate = (apply_level == -1) ?
  1044. 0 : soc_info->optional_clk_rate[clk_idx];
  1045. shared_clk_mask = soc_info->optional_shared_clk_mask;
  1046. clk_id = soc_info->optional_clk_id[clk_idx];
  1047. } else {
  1048. clk = soc_info->clk[clk_idx];
  1049. clk_name = soc_info->clk_name[clk_idx];
  1050. clk_rate = (apply_level == -1) ?
  1051. 0 : soc_info->clk_rate[apply_level][clk_idx];
  1052. shared_clk_mask = soc_info->shared_clk_mask;
  1053. clk_id = soc_info->clk_id[clk_idx];
  1054. if (clk_idx == soc_info->src_clk_idx)
  1055. is_src_clk = true;
  1056. }
  1057. rc = cam_soc_util_set_clk_rate(soc_info, clk, clk_name, clk_rate,
  1058. CAM_IS_BIT_SET(shared_clk_mask, clk_idx), is_src_clk, clk_id,
  1059. applied_clock_rate);
  1060. if (rc)
  1061. return rc;
  1062. rc = clk_prepare_enable(clk);
  1063. if (rc) {
  1064. CAM_ERR(CAM_UTIL, "enable failed for %s: rc(%d)", clk_name, rc);
  1065. return rc;
  1066. }
  1067. return rc;
  1068. }
  1069. int cam_soc_util_clk_disable(struct cam_hw_soc_info *soc_info,
  1070. bool optional_clk, int32_t clk_idx)
  1071. {
  1072. struct clk *clk;
  1073. const char *clk_name;
  1074. uint32_t shared_clk_mask;
  1075. uint32_t clk_id;
  1076. if (!soc_info || (clk_idx < 0)) {
  1077. CAM_ERR(CAM_UTIL, "Invalid param %d", clk_idx);
  1078. return -EINVAL;
  1079. }
  1080. if (optional_clk) {
  1081. clk = soc_info->optional_clk[clk_idx];
  1082. clk_name = soc_info->optional_clk_name[clk_idx];
  1083. shared_clk_mask = soc_info->optional_shared_clk_mask;
  1084. clk_id = soc_info->optional_clk_id[clk_idx];
  1085. } else {
  1086. clk = soc_info->clk[clk_idx];
  1087. clk_name = soc_info->clk_name[clk_idx];
  1088. shared_clk_mask = soc_info->shared_clk_mask;
  1089. clk_id = soc_info->clk_id[clk_idx];
  1090. }
  1091. CAM_DBG(CAM_UTIL, "disable %s", clk_name);
  1092. clk_disable_unprepare(clk);
  1093. if (CAM_IS_BIT_SET(shared_clk_mask, clk_idx)) {
  1094. CAM_DBG(CAM_UTIL,
  1095. "Dev %s clk %s Disabling Shared clk, set 0 rate",
  1096. soc_info->dev_name, clk_name);
  1097. cam_soc_util_clk_wrapper_set_clk_rate(clk_id, soc_info, clk, 0);
  1098. } else if (soc_info->mmrm_handle && (!skip_mmrm_set_rate) &&
  1099. (soc_info->src_clk_idx == clk_idx)) {
  1100. CAM_DBG(CAM_UTIL,
  1101. "Dev %s Disabling %s clk, set 0 rate", soc_info->dev_name, clk_name);
  1102. cam_soc_util_set_rate_through_mmrm(
  1103. soc_info->mmrm_handle,
  1104. soc_info->is_nrt_dev,
  1105. 0, 0, 1);
  1106. }
  1107. return 0;
  1108. }
  1109. /**
  1110. * cam_soc_util_clk_enable_default()
  1111. *
  1112. * @brief: This function enables the default clocks present
  1113. * in soc_info
  1114. *
  1115. * @soc_info: Device soc struct to be populated
  1116. * @clk_level: Clk level to apply while enabling
  1117. *
  1118. * @return: success or failure
  1119. */
  1120. int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info,
  1121. enum cam_vote_level clk_level)
  1122. {
  1123. int i, rc = 0;
  1124. enum cam_vote_level apply_level;
  1125. unsigned long applied_clk_rate;
  1126. if ((soc_info->num_clk == 0) ||
  1127. (soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
  1128. CAM_ERR(CAM_UTIL, "Invalid number of clock %d",
  1129. soc_info->num_clk);
  1130. return -EINVAL;
  1131. }
  1132. rc = cam_soc_util_get_clk_level_to_apply(soc_info, clk_level,
  1133. &apply_level);
  1134. if (rc)
  1135. return rc;
  1136. if (soc_info->cam_cx_ipeak_enable)
  1137. cam_cx_ipeak_update_vote_cx_ipeak(soc_info, apply_level);
  1138. for (i = 0; i < soc_info->num_clk; i++) {
  1139. rc = cam_soc_util_clk_enable(soc_info, false, i, apply_level,
  1140. &applied_clk_rate);
  1141. if (rc)
  1142. goto clk_disable;
  1143. if (i == soc_info->src_clk_idx)
  1144. soc_info->applied_src_clk_rate = applied_clk_rate;
  1145. if (soc_info->cam_cx_ipeak_enable) {
  1146. CAM_DBG(CAM_UTIL,
  1147. "dev name = %s clk name = %s idx = %d\n"
  1148. "apply_level = %d clc idx = %d",
  1149. soc_info->dev_name, soc_info->clk_name[i], i,
  1150. apply_level, i);
  1151. }
  1152. }
  1153. return rc;
  1154. clk_disable:
  1155. if (soc_info->cam_cx_ipeak_enable)
  1156. cam_cx_ipeak_update_vote_cx_ipeak(soc_info, 0);
  1157. for (i--; i >= 0; i--) {
  1158. cam_soc_util_clk_disable(soc_info, false, i);
  1159. }
  1160. return rc;
  1161. }
  1162. /**
  1163. * cam_soc_util_clk_disable_default()
  1164. *
  1165. * @brief: This function disables the default clocks present
  1166. * in soc_info
  1167. *
  1168. * @soc_info: device soc struct to be populated
  1169. *
  1170. * @return: success or failure
  1171. */
  1172. void cam_soc_util_clk_disable_default(struct cam_hw_soc_info *soc_info)
  1173. {
  1174. int i;
  1175. if (soc_info->num_clk == 0)
  1176. return;
  1177. if (soc_info->cam_cx_ipeak_enable)
  1178. cam_cx_ipeak_unvote_cx_ipeak(soc_info);
  1179. for (i = soc_info->num_clk - 1; i >= 0; i--)
  1180. cam_soc_util_clk_disable(soc_info, false, i);
  1181. }
  1182. /**
  1183. * cam_soc_util_get_dt_clk_info()
  1184. *
  1185. * @brief: Parse the DT and populate the Clock properties
  1186. *
  1187. * @soc_info: device soc struct to be populated
  1188. * @src_clk_str name of src clock that has rate control
  1189. *
  1190. * @return: success or failure
  1191. */
  1192. static int cam_soc_util_get_dt_clk_info(struct cam_hw_soc_info *soc_info)
  1193. {
  1194. struct device_node *of_node = NULL;
  1195. int count;
  1196. int num_clk_rates, num_clk_levels;
  1197. int i, j, rc;
  1198. int32_t num_clk_level_strings;
  1199. const char *src_clk_str = NULL;
  1200. const char *scl_clk_str = NULL;
  1201. const char *clk_control_debugfs = NULL;
  1202. const char *clk_cntl_lvl_string = NULL;
  1203. enum cam_vote_level level;
  1204. int shared_clk_cnt;
  1205. struct of_phandle_args clk_args = {0};
  1206. if (!soc_info || !soc_info->dev)
  1207. return -EINVAL;
  1208. of_node = soc_info->dev->of_node;
  1209. if (!of_property_read_bool(of_node, "use-shared-clk")) {
  1210. CAM_DBG(CAM_UTIL, "No shared clk parameter defined");
  1211. soc_info->use_shared_clk = false;
  1212. } else {
  1213. soc_info->use_shared_clk = true;
  1214. }
  1215. count = of_property_count_strings(of_node, "clock-names");
  1216. CAM_DBG(CAM_UTIL, "E: dev_name = %s count = %d",
  1217. soc_info->dev_name, count);
  1218. if (count > CAM_SOC_MAX_CLK) {
  1219. CAM_ERR(CAM_UTIL, "invalid count of clocks, count=%d", count);
  1220. rc = -EINVAL;
  1221. return rc;
  1222. }
  1223. if (count <= 0) {
  1224. CAM_DBG(CAM_UTIL, "No clock-names found");
  1225. count = 0;
  1226. soc_info->num_clk = count;
  1227. return 0;
  1228. }
  1229. soc_info->num_clk = count;
  1230. for (i = 0; i < count; i++) {
  1231. rc = of_property_read_string_index(of_node, "clock-names",
  1232. i, &(soc_info->clk_name[i]));
  1233. CAM_DBG(CAM_UTIL, "clock-names[%d] = %s",
  1234. i, soc_info->clk_name[i]);
  1235. if (rc) {
  1236. CAM_ERR(CAM_UTIL,
  1237. "i= %d count= %d reading clock-names failed",
  1238. i, count);
  1239. return rc;
  1240. }
  1241. }
  1242. num_clk_rates = of_property_count_u32_elems(of_node, "clock-rates");
  1243. if (num_clk_rates <= 0) {
  1244. CAM_ERR(CAM_UTIL, "reading clock-rates count failed");
  1245. return -EINVAL;
  1246. }
  1247. if ((num_clk_rates % soc_info->num_clk) != 0) {
  1248. CAM_ERR(CAM_UTIL,
  1249. "mismatch clk/rates, No of clocks=%d, No of rates=%d",
  1250. soc_info->num_clk, num_clk_rates);
  1251. return -EINVAL;
  1252. }
  1253. num_clk_levels = (num_clk_rates / soc_info->num_clk);
  1254. num_clk_level_strings = of_property_count_strings(of_node,
  1255. "clock-cntl-level");
  1256. if (num_clk_level_strings != num_clk_levels) {
  1257. CAM_ERR(CAM_UTIL,
  1258. "Mismatch No of levels=%d, No of level string=%d",
  1259. num_clk_levels, num_clk_level_strings);
  1260. return -EINVAL;
  1261. }
  1262. soc_info->lowest_clk_level = CAM_TURBO_VOTE;
  1263. for (i = 0; i < num_clk_levels; i++) {
  1264. rc = of_property_read_string_index(of_node,
  1265. "clock-cntl-level", i, &clk_cntl_lvl_string);
  1266. if (rc) {
  1267. CAM_ERR(CAM_UTIL,
  1268. "Error reading clock-cntl-level, rc=%d", rc);
  1269. return rc;
  1270. }
  1271. rc = cam_soc_util_get_level_from_string(clk_cntl_lvl_string,
  1272. &level);
  1273. if (rc)
  1274. return rc;
  1275. CAM_DBG(CAM_UTIL,
  1276. "[%d] : %s %d", i, clk_cntl_lvl_string, level);
  1277. soc_info->clk_level_valid[level] = true;
  1278. for (j = 0; j < soc_info->num_clk; j++) {
  1279. rc = of_property_read_u32_index(of_node, "clock-rates",
  1280. ((i * soc_info->num_clk) + j),
  1281. &soc_info->clk_rate[level][j]);
  1282. if (rc) {
  1283. CAM_ERR(CAM_UTIL,
  1284. "Error reading clock-rates, rc=%d",
  1285. rc);
  1286. return rc;
  1287. }
  1288. soc_info->clk_rate[level][j] =
  1289. (soc_info->clk_rate[level][j] == 0) ?
  1290. (int32_t)NO_SET_RATE :
  1291. soc_info->clk_rate[level][j];
  1292. CAM_DBG(CAM_UTIL, "soc_info->clk_rate[%d][%d] = %d",
  1293. level, j,
  1294. soc_info->clk_rate[level][j]);
  1295. }
  1296. if ((level > CAM_MINSVS_VOTE) &&
  1297. (level < soc_info->lowest_clk_level))
  1298. soc_info->lowest_clk_level = level;
  1299. }
  1300. soc_info->src_clk_idx = -1;
  1301. rc = of_property_read_string_index(of_node, "src-clock-name", 0,
  1302. &src_clk_str);
  1303. if (rc || !src_clk_str) {
  1304. CAM_DBG(CAM_UTIL, "No src_clk_str found");
  1305. rc = 0;
  1306. goto end;
  1307. }
  1308. for (i = 0; i < soc_info->num_clk; i++) {
  1309. if (strcmp(soc_info->clk_name[i], src_clk_str) == 0) {
  1310. soc_info->src_clk_idx = i;
  1311. CAM_DBG(CAM_UTIL, "src clock = %s, index = %d",
  1312. src_clk_str, i);
  1313. }
  1314. rc = of_parse_phandle_with_args(of_node, "clocks",
  1315. "#clock-cells", i, &clk_args);
  1316. if (rc) {
  1317. CAM_ERR(CAM_CPAS,
  1318. "failed to clock info rc=%d", rc);
  1319. rc = -EINVAL;
  1320. goto end;
  1321. }
  1322. soc_info->clk_id[i] = clk_args.args[0];
  1323. of_node_put(clk_args.np);
  1324. CAM_DBG(CAM_UTIL, "Dev %s clk %s id %d",
  1325. soc_info->dev_name, soc_info->clk_name[i],
  1326. soc_info->clk_id[i]);
  1327. }
  1328. CAM_DBG(CAM_UTIL, "Dev %s src_clk_idx %d, lowest_clk_level %d",
  1329. soc_info->dev_name, soc_info->src_clk_idx,
  1330. soc_info->lowest_clk_level);
  1331. soc_info->shared_clk_mask = 0;
  1332. shared_clk_cnt = of_property_count_u32_elems(of_node, "shared-clks");
  1333. if (shared_clk_cnt <= 0) {
  1334. CAM_DBG(CAM_UTIL, "Dev %s, no shared clks", soc_info->dev_name);
  1335. } else if (shared_clk_cnt != count) {
  1336. CAM_ERR(CAM_UTIL, "Dev %s, incorrect shared clock count %d %d",
  1337. soc_info->dev_name, shared_clk_cnt, count);
  1338. rc = -EINVAL;
  1339. goto end;
  1340. } else {
  1341. uint32_t shared_clk_val;
  1342. for (i = 0; i < shared_clk_cnt; i++) {
  1343. rc = of_property_read_u32_index(of_node,
  1344. "shared-clks", i, &shared_clk_val);
  1345. if (rc || (shared_clk_val > 1)) {
  1346. CAM_ERR(CAM_UTIL,
  1347. "Incorrect shared clk info at %d, val=%d, count=%d",
  1348. i, shared_clk_val, shared_clk_cnt);
  1349. rc = -EINVAL;
  1350. goto end;
  1351. }
  1352. if (shared_clk_val)
  1353. CAM_SET_BIT(soc_info->shared_clk_mask, i);
  1354. }
  1355. CAM_DBG(CAM_UTIL, "Dev %s shared clk mask 0x%x",
  1356. soc_info->dev_name, soc_info->shared_clk_mask);
  1357. }
  1358. /* scalable clk info parsing */
  1359. soc_info->scl_clk_count = 0;
  1360. soc_info->scl_clk_count = of_property_count_strings(of_node,
  1361. "scl-clk-names");
  1362. if ((soc_info->scl_clk_count <= 0) ||
  1363. (soc_info->scl_clk_count > CAM_SOC_MAX_CLK)) {
  1364. if (soc_info->scl_clk_count == -EINVAL) {
  1365. CAM_DBG(CAM_UTIL, "scl_clk_name prop not avialable");
  1366. } else if ((soc_info->scl_clk_count == -ENODATA) ||
  1367. (soc_info->scl_clk_count > CAM_SOC_MAX_CLK)) {
  1368. CAM_ERR(CAM_UTIL, "Invalid scl_clk_count: %d",
  1369. soc_info->scl_clk_count);
  1370. return -EINVAL;
  1371. }
  1372. CAM_DBG(CAM_UTIL, "Invalid scl_clk count: %d",
  1373. soc_info->scl_clk_count);
  1374. soc_info->scl_clk_count = -1;
  1375. } else {
  1376. CAM_DBG(CAM_UTIL, "No of scalable clocks: %d",
  1377. soc_info->scl_clk_count);
  1378. for (i = 0; i < soc_info->scl_clk_count; i++) {
  1379. rc = of_property_read_string_index(of_node,
  1380. "scl-clk-names", i,
  1381. (const char **)&scl_clk_str);
  1382. if (rc || !scl_clk_str) {
  1383. CAM_WARN(CAM_UTIL, "scl_clk_str is NULL");
  1384. soc_info->scl_clk_idx[i] = -1;
  1385. continue;
  1386. }
  1387. for (j = 0; j < soc_info->num_clk; j++) {
  1388. if (strnstr(scl_clk_str, soc_info->clk_name[j],
  1389. strlen(scl_clk_str))) {
  1390. soc_info->scl_clk_idx[i] = j;
  1391. CAM_DBG(CAM_UTIL,
  1392. "scl clock = %s, index = %d",
  1393. scl_clk_str, j);
  1394. break;
  1395. }
  1396. }
  1397. }
  1398. }
  1399. rc = of_property_read_string_index(of_node,
  1400. "clock-control-debugfs", 0, &clk_control_debugfs);
  1401. if (rc || !clk_control_debugfs) {
  1402. CAM_DBG(CAM_UTIL, "No clock_control_debugfs property found");
  1403. rc = 0;
  1404. goto end;
  1405. }
  1406. if (strcmp("true", clk_control_debugfs) == 0)
  1407. soc_info->clk_control_enable = true;
  1408. CAM_DBG(CAM_UTIL, "X: dev_name = %s count = %d",
  1409. soc_info->dev_name, count);
  1410. end:
  1411. return rc;
  1412. }
  1413. int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info,
  1414. enum cam_vote_level clk_level, bool do_not_set_src_clk)
  1415. {
  1416. int i, rc = 0;
  1417. enum cam_vote_level apply_level;
  1418. unsigned long applied_clk_rate;
  1419. if ((soc_info->num_clk == 0) ||
  1420. (soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
  1421. CAM_ERR(CAM_UTIL, "Invalid number of clock %d",
  1422. soc_info->num_clk);
  1423. return -EINVAL;
  1424. }
  1425. rc = cam_soc_util_get_clk_level_to_apply(soc_info, clk_level,
  1426. &apply_level);
  1427. if (rc)
  1428. return rc;
  1429. if (soc_info->cam_cx_ipeak_enable)
  1430. cam_cx_ipeak_update_vote_cx_ipeak(soc_info, apply_level);
  1431. for (i = 0; i < soc_info->num_clk; i++) {
  1432. if (do_not_set_src_clk && (i == soc_info->src_clk_idx)) {
  1433. CAM_DBG(CAM_UTIL, "Skipping set rate for src clk %s",
  1434. soc_info->clk_name[i]);
  1435. continue;
  1436. }
  1437. CAM_DBG(CAM_UTIL, "Set rate for clk %s rate %d",
  1438. soc_info->clk_name[i],
  1439. soc_info->clk_rate[apply_level][i]);
  1440. rc = cam_soc_util_set_clk_rate(soc_info, soc_info->clk[i],
  1441. soc_info->clk_name[i],
  1442. soc_info->clk_rate[apply_level][i],
  1443. CAM_IS_BIT_SET(soc_info->shared_clk_mask, i),
  1444. (i == soc_info->src_clk_idx) ? true : false,
  1445. soc_info->clk_id[i],
  1446. &applied_clk_rate);
  1447. if (rc < 0) {
  1448. CAM_DBG(CAM_UTIL,
  1449. "dev name = %s clk_name = %s idx = %d\n"
  1450. "apply_level = %d",
  1451. soc_info->dev_name, soc_info->clk_name[i],
  1452. i, apply_level);
  1453. if (soc_info->cam_cx_ipeak_enable)
  1454. cam_cx_ipeak_update_vote_cx_ipeak(soc_info, 0);
  1455. break;
  1456. }
  1457. if (i == soc_info->src_clk_idx)
  1458. soc_info->applied_src_clk_rate = applied_clk_rate;
  1459. }
  1460. return rc;
  1461. };
  1462. static int cam_soc_util_get_dt_gpio_req_tbl(struct device_node *of_node,
  1463. struct cam_soc_gpio_data *gconf, uint16_t *gpio_array,
  1464. uint16_t gpio_array_size)
  1465. {
  1466. int32_t rc = 0, i = 0;
  1467. uint32_t count = 0;
  1468. uint32_t *val_array = NULL;
  1469. if (!of_get_property(of_node, "gpio-req-tbl-num", &count))
  1470. return 0;
  1471. count /= sizeof(uint32_t);
  1472. if (!count) {
  1473. CAM_ERR(CAM_UTIL, "gpio-req-tbl-num 0");
  1474. return 0;
  1475. }
  1476. val_array = kcalloc(count, sizeof(uint32_t), GFP_KERNEL);
  1477. if (!val_array)
  1478. return -ENOMEM;
  1479. gconf->cam_gpio_req_tbl = kcalloc(count, sizeof(struct gpio),
  1480. GFP_KERNEL);
  1481. if (!gconf->cam_gpio_req_tbl) {
  1482. rc = -ENOMEM;
  1483. goto free_val_array;
  1484. }
  1485. gconf->cam_gpio_req_tbl_size = count;
  1486. rc = of_property_read_u32_array(of_node, "gpio-req-tbl-num",
  1487. val_array, count);
  1488. if (rc) {
  1489. CAM_ERR(CAM_UTIL, "failed in reading gpio-req-tbl-num, rc = %d",
  1490. rc);
  1491. goto free_gpio_req_tbl;
  1492. }
  1493. for (i = 0; i < count; i++) {
  1494. if (val_array[i] >= gpio_array_size) {
  1495. CAM_ERR(CAM_UTIL, "gpio req tbl index %d invalid",
  1496. val_array[i]);
  1497. goto free_gpio_req_tbl;
  1498. }
  1499. gconf->cam_gpio_req_tbl[i].gpio = gpio_array[val_array[i]];
  1500. CAM_DBG(CAM_UTIL, "cam_gpio_req_tbl[%d].gpio = %d", i,
  1501. gconf->cam_gpio_req_tbl[i].gpio);
  1502. }
  1503. rc = of_property_read_u32_array(of_node, "gpio-req-tbl-flags",
  1504. val_array, count);
  1505. if (rc) {
  1506. CAM_ERR(CAM_UTIL, "Failed in gpio-req-tbl-flags, rc %d", rc);
  1507. goto free_gpio_req_tbl;
  1508. }
  1509. for (i = 0; i < count; i++) {
  1510. gconf->cam_gpio_req_tbl[i].flags = val_array[i];
  1511. CAM_DBG(CAM_UTIL, "cam_gpio_req_tbl[%d].flags = %ld", i,
  1512. gconf->cam_gpio_req_tbl[i].flags);
  1513. }
  1514. for (i = 0; i < count; i++) {
  1515. rc = of_property_read_string_index(of_node,
  1516. "gpio-req-tbl-label", i,
  1517. &gconf->cam_gpio_req_tbl[i].label);
  1518. if (rc) {
  1519. CAM_ERR(CAM_UTIL, "Failed rc %d", rc);
  1520. goto free_gpio_req_tbl;
  1521. }
  1522. CAM_DBG(CAM_UTIL, "cam_gpio_req_tbl[%d].label = %s", i,
  1523. gconf->cam_gpio_req_tbl[i].label);
  1524. }
  1525. kfree(val_array);
  1526. return rc;
  1527. free_gpio_req_tbl:
  1528. kfree(gconf->cam_gpio_req_tbl);
  1529. free_val_array:
  1530. kfree(val_array);
  1531. gconf->cam_gpio_req_tbl_size = 0;
  1532. return rc;
  1533. }
  1534. static int cam_soc_util_get_gpio_info(struct cam_hw_soc_info *soc_info)
  1535. {
  1536. int32_t rc = 0, i = 0;
  1537. uint16_t *gpio_array = NULL;
  1538. int16_t gpio_array_size = 0;
  1539. struct cam_soc_gpio_data *gconf = NULL;
  1540. struct device_node *of_node = NULL;
  1541. if (!soc_info || !soc_info->dev)
  1542. return -EINVAL;
  1543. of_node = soc_info->dev->of_node;
  1544. /* Validate input parameters */
  1545. if (!of_node) {
  1546. CAM_ERR(CAM_UTIL, "Invalid param of_node");
  1547. return -EINVAL;
  1548. }
  1549. gpio_array_size = of_gpio_count(of_node);
  1550. if (gpio_array_size <= 0)
  1551. return 0;
  1552. CAM_DBG(CAM_UTIL, "gpio count %d", gpio_array_size);
  1553. gpio_array = kcalloc(gpio_array_size, sizeof(uint16_t), GFP_KERNEL);
  1554. if (!gpio_array)
  1555. goto free_gpio_conf;
  1556. for (i = 0; i < gpio_array_size; i++) {
  1557. gpio_array[i] = of_get_gpio(of_node, i);
  1558. CAM_DBG(CAM_UTIL, "gpio_array[%d] = %d", i, gpio_array[i]);
  1559. }
  1560. gconf = kzalloc(sizeof(*gconf), GFP_KERNEL);
  1561. if (!gconf)
  1562. return -ENOMEM;
  1563. rc = cam_soc_util_get_dt_gpio_req_tbl(of_node, gconf, gpio_array,
  1564. gpio_array_size);
  1565. if (rc) {
  1566. CAM_ERR(CAM_UTIL, "failed in msm_camera_get_dt_gpio_req_tbl");
  1567. goto free_gpio_array;
  1568. }
  1569. gconf->cam_gpio_common_tbl = kcalloc(gpio_array_size,
  1570. sizeof(struct gpio), GFP_KERNEL);
  1571. if (!gconf->cam_gpio_common_tbl) {
  1572. rc = -ENOMEM;
  1573. goto free_gpio_array;
  1574. }
  1575. for (i = 0; i < gpio_array_size; i++)
  1576. gconf->cam_gpio_common_tbl[i].gpio = gpio_array[i];
  1577. gconf->cam_gpio_common_tbl_size = gpio_array_size;
  1578. soc_info->gpio_data = gconf;
  1579. kfree(gpio_array);
  1580. return rc;
  1581. free_gpio_array:
  1582. kfree(gpio_array);
  1583. free_gpio_conf:
  1584. kfree(gconf);
  1585. soc_info->gpio_data = NULL;
  1586. return rc;
  1587. }
  1588. static int cam_soc_util_request_gpio_table(
  1589. struct cam_hw_soc_info *soc_info, bool gpio_en)
  1590. {
  1591. int rc = 0, i = 0;
  1592. uint8_t size = 0;
  1593. struct cam_soc_gpio_data *gpio_conf =
  1594. soc_info->gpio_data;
  1595. struct gpio *gpio_tbl = NULL;
  1596. if (!gpio_conf) {
  1597. CAM_DBG(CAM_UTIL, "No GPIO entry");
  1598. return 0;
  1599. }
  1600. if (gpio_conf->cam_gpio_common_tbl_size <= 0) {
  1601. CAM_ERR(CAM_UTIL, "GPIO table size is invalid");
  1602. return -EINVAL;
  1603. }
  1604. size = gpio_conf->cam_gpio_req_tbl_size;
  1605. gpio_tbl = gpio_conf->cam_gpio_req_tbl;
  1606. if (!gpio_tbl || !size) {
  1607. CAM_ERR(CAM_UTIL, "Invalid gpio_tbl %pK / size %d",
  1608. gpio_tbl, size);
  1609. return -EINVAL;
  1610. }
  1611. for (i = 0; i < size; i++) {
  1612. CAM_DBG(CAM_UTIL, "i=%d, gpio=%d dir=%ld", i,
  1613. gpio_tbl[i].gpio, gpio_tbl[i].flags);
  1614. }
  1615. if (gpio_en) {
  1616. for (i = 0; i < size; i++) {
  1617. rc = gpio_request_one(gpio_tbl[i].gpio,
  1618. gpio_tbl[i].flags, gpio_tbl[i].label);
  1619. if (rc) {
  1620. /*
  1621. * After GPIO request fails, contine to
  1622. * apply new gpios, outout a error message
  1623. * for driver bringup debug
  1624. */
  1625. CAM_ERR(CAM_UTIL, "gpio %d:%s request fails",
  1626. gpio_tbl[i].gpio, gpio_tbl[i].label);
  1627. }
  1628. }
  1629. } else {
  1630. gpio_free_array(gpio_tbl, size);
  1631. }
  1632. return rc;
  1633. }
  1634. static int cam_soc_util_get_dt_regulator_info
  1635. (struct cam_hw_soc_info *soc_info)
  1636. {
  1637. int rc = 0, count = 0, i = 0;
  1638. struct device_node *of_node = NULL;
  1639. if (!soc_info || !soc_info->dev) {
  1640. CAM_ERR(CAM_UTIL, "Invalid parameters");
  1641. return -EINVAL;
  1642. }
  1643. of_node = soc_info->dev->of_node;
  1644. soc_info->num_rgltr = 0;
  1645. count = of_property_count_strings(of_node, "regulator-names");
  1646. if (count != -EINVAL) {
  1647. if (count <= 0) {
  1648. CAM_ERR(CAM_UTIL, "no regulators found");
  1649. count = 0;
  1650. return -EINVAL;
  1651. }
  1652. soc_info->num_rgltr = count;
  1653. } else {
  1654. CAM_DBG(CAM_UTIL, "No regulators node found");
  1655. return 0;
  1656. }
  1657. if (soc_info->num_rgltr > CAM_SOC_MAX_REGULATOR) {
  1658. CAM_ERR(CAM_UTIL, "Invalid regulator count:%d",
  1659. soc_info->num_rgltr);
  1660. return -EINVAL;
  1661. }
  1662. for (i = 0; i < soc_info->num_rgltr; i++) {
  1663. rc = of_property_read_string_index(of_node,
  1664. "regulator-names", i, &soc_info->rgltr_name[i]);
  1665. CAM_DBG(CAM_UTIL, "rgltr_name[%d] = %s",
  1666. i, soc_info->rgltr_name[i]);
  1667. if (rc) {
  1668. CAM_ERR(CAM_UTIL, "no regulator resource at cnt=%d", i);
  1669. return -ENODEV;
  1670. }
  1671. }
  1672. if (!of_property_read_bool(of_node, "rgltr-cntrl-support")) {
  1673. CAM_DBG(CAM_UTIL, "No regulator control parameter defined");
  1674. soc_info->rgltr_ctrl_support = false;
  1675. return 0;
  1676. }
  1677. soc_info->rgltr_ctrl_support = true;
  1678. rc = of_property_read_u32_array(of_node, "rgltr-min-voltage",
  1679. soc_info->rgltr_min_volt, soc_info->num_rgltr);
  1680. if (rc) {
  1681. CAM_ERR(CAM_UTIL, "No minimum volatage value found, rc=%d", rc);
  1682. return -EINVAL;
  1683. }
  1684. rc = of_property_read_u32_array(of_node, "rgltr-max-voltage",
  1685. soc_info->rgltr_max_volt, soc_info->num_rgltr);
  1686. if (rc) {
  1687. CAM_ERR(CAM_UTIL, "No maximum volatage value found, rc=%d", rc);
  1688. return -EINVAL;
  1689. }
  1690. rc = of_property_read_u32_array(of_node, "rgltr-load-current",
  1691. soc_info->rgltr_op_mode, soc_info->num_rgltr);
  1692. if (rc) {
  1693. CAM_ERR(CAM_UTIL, "No Load curent found rc=%d", rc);
  1694. return -EINVAL;
  1695. }
  1696. return rc;
  1697. }
  1698. #ifdef CONFIG_CAM_PRESIL
  1699. static uint32_t next_dummy_irq_line_num = 0x000f;
  1700. struct resource dummy_irq_line[512];
  1701. #endif
  1702. int cam_soc_util_get_dt_properties(struct cam_hw_soc_info *soc_info)
  1703. {
  1704. struct device_node *of_node = NULL;
  1705. int count = 0, i = 0, rc = 0;
  1706. if (!soc_info || !soc_info->dev)
  1707. return -EINVAL;
  1708. of_node = soc_info->dev->of_node;
  1709. rc = of_property_read_u32(of_node, "cell-index", &soc_info->index);
  1710. if (rc) {
  1711. CAM_ERR(CAM_UTIL, "device %s failed to read cell-index",
  1712. soc_info->dev_name);
  1713. return rc;
  1714. }
  1715. count = of_property_count_strings(of_node, "reg-names");
  1716. if (count <= 0) {
  1717. CAM_DBG(CAM_UTIL, "no reg-names found for: %s",
  1718. soc_info->dev_name);
  1719. count = 0;
  1720. }
  1721. soc_info->num_mem_block = count;
  1722. for (i = 0; i < soc_info->num_mem_block; i++) {
  1723. rc = of_property_read_string_index(of_node, "reg-names", i,
  1724. &soc_info->mem_block_name[i]);
  1725. if (rc) {
  1726. CAM_ERR(CAM_UTIL, "failed to read reg-names at %d", i);
  1727. return rc;
  1728. }
  1729. soc_info->mem_block[i] =
  1730. platform_get_resource_byname(soc_info->pdev,
  1731. IORESOURCE_MEM, soc_info->mem_block_name[i]);
  1732. if (!soc_info->mem_block[i]) {
  1733. CAM_ERR(CAM_UTIL, "no mem resource by name %s",
  1734. soc_info->mem_block_name[i]);
  1735. rc = -ENODEV;
  1736. return rc;
  1737. }
  1738. }
  1739. rc = of_property_read_string(of_node, "label", &soc_info->label_name);
  1740. if (rc)
  1741. CAM_DBG(CAM_UTIL, "Label is not available in the node: %d", rc);
  1742. if (soc_info->num_mem_block > 0) {
  1743. rc = of_property_read_u32_array(of_node, "reg-cam-base",
  1744. soc_info->mem_block_cam_base, soc_info->num_mem_block);
  1745. if (rc) {
  1746. CAM_ERR(CAM_UTIL, "Error reading register offsets");
  1747. return rc;
  1748. }
  1749. }
  1750. rc = of_property_read_string_index(of_node, "interrupt-names", 0,
  1751. &soc_info->irq_name);
  1752. if (rc) {
  1753. CAM_DBG(CAM_UTIL, "No interrupt line preset for: %s",
  1754. soc_info->dev_name);
  1755. rc = 0;
  1756. } else {
  1757. rc = cam_compat_util_get_irq(soc_info);
  1758. if (rc < 0) {
  1759. CAM_ERR(CAM_UTIL, "get irq resource failed: %d", rc);
  1760. #ifndef CONFIG_CAM_PRESIL
  1761. return rc;
  1762. #else
  1763. /* Pre-sil for new devices not present on old */
  1764. soc_info->irq_line =
  1765. &dummy_irq_line[next_dummy_irq_line_num++];
  1766. CAM_DBG(CAM_PRESIL, "interrupt line for dev %s irq name %s number %d",
  1767. soc_info->dev_name, soc_info->irq_name,
  1768. soc_info->irq_line->start);
  1769. #endif
  1770. }
  1771. }
  1772. rc = of_property_read_string_index(of_node, "compatible", 0,
  1773. (const char **)&soc_info->compatible);
  1774. if (rc) {
  1775. CAM_DBG(CAM_UTIL, "No compatible string present for: %s",
  1776. soc_info->dev_name);
  1777. rc = 0;
  1778. }
  1779. soc_info->is_nrt_dev = false;
  1780. if (of_property_read_bool(of_node, "nrt-device"))
  1781. soc_info->is_nrt_dev = true;
  1782. CAM_DBG(CAM_UTIL, "Dev %s, nrt_dev %d",
  1783. soc_info->dev_name, soc_info->is_nrt_dev);
  1784. rc = cam_soc_util_get_dt_regulator_info(soc_info);
  1785. if (rc)
  1786. return rc;
  1787. rc = cam_soc_util_get_dt_clk_info(soc_info);
  1788. if (rc)
  1789. return rc;
  1790. rc = cam_soc_util_get_gpio_info(soc_info);
  1791. if (rc)
  1792. return rc;
  1793. if (of_find_property(of_node, "qcom,cam-cx-ipeak", NULL))
  1794. rc = cam_cx_ipeak_register_cx_ipeak(soc_info);
  1795. return rc;
  1796. }
  1797. /**
  1798. * cam_soc_util_get_regulator()
  1799. *
  1800. * @brief: Get regulator resource named vdd
  1801. *
  1802. * @dev: Device associated with regulator
  1803. * @reg: Return pointer to be filled with regulator on success
  1804. * @rgltr_name: Name of regulator to get
  1805. *
  1806. * @return: 0 for Success, negative value for failure
  1807. */
  1808. static int cam_soc_util_get_regulator(struct device *dev,
  1809. struct regulator **reg, const char *rgltr_name)
  1810. {
  1811. int rc = 0;
  1812. *reg = regulator_get(dev, rgltr_name);
  1813. if (IS_ERR_OR_NULL(*reg)) {
  1814. rc = PTR_ERR(*reg);
  1815. rc = rc ? rc : -EINVAL;
  1816. CAM_ERR(CAM_UTIL, "Regulator %s get failed %d", rgltr_name, rc);
  1817. *reg = NULL;
  1818. }
  1819. return rc;
  1820. }
  1821. int cam_soc_util_regulator_disable(struct regulator *rgltr,
  1822. const char *rgltr_name, uint32_t rgltr_min_volt,
  1823. uint32_t rgltr_max_volt, uint32_t rgltr_op_mode,
  1824. uint32_t rgltr_delay_ms)
  1825. {
  1826. int32_t rc = 0;
  1827. if (!rgltr) {
  1828. CAM_ERR(CAM_UTIL, "Invalid NULL parameter");
  1829. return -EINVAL;
  1830. }
  1831. rc = regulator_disable(rgltr);
  1832. if (rc) {
  1833. CAM_ERR(CAM_UTIL, "%s regulator disable failed", rgltr_name);
  1834. return rc;
  1835. }
  1836. if (rgltr_delay_ms > 20)
  1837. msleep(rgltr_delay_ms);
  1838. else if (rgltr_delay_ms)
  1839. usleep_range(rgltr_delay_ms * 1000,
  1840. (rgltr_delay_ms * 1000) + 1000);
  1841. if (regulator_count_voltages(rgltr) > 0) {
  1842. regulator_set_load(rgltr, 0);
  1843. regulator_set_voltage(rgltr, 0, rgltr_max_volt);
  1844. }
  1845. return rc;
  1846. }
  1847. int cam_soc_util_regulator_enable(struct regulator *rgltr,
  1848. const char *rgltr_name,
  1849. uint32_t rgltr_min_volt, uint32_t rgltr_max_volt,
  1850. uint32_t rgltr_op_mode, uint32_t rgltr_delay)
  1851. {
  1852. int32_t rc = 0;
  1853. if (!rgltr) {
  1854. CAM_ERR(CAM_UTIL, "Invalid NULL parameter");
  1855. return -EINVAL;
  1856. }
  1857. if (regulator_count_voltages(rgltr) > 0) {
  1858. CAM_DBG(CAM_UTIL, "voltage min=%d, max=%d",
  1859. rgltr_min_volt, rgltr_max_volt);
  1860. rc = regulator_set_voltage(
  1861. rgltr, rgltr_min_volt, rgltr_max_volt);
  1862. if (rc) {
  1863. CAM_ERR(CAM_UTIL, "%s set voltage failed", rgltr_name);
  1864. return rc;
  1865. }
  1866. rc = regulator_set_load(rgltr, rgltr_op_mode);
  1867. if (rc) {
  1868. CAM_ERR(CAM_UTIL, "%s set optimum mode failed",
  1869. rgltr_name);
  1870. return rc;
  1871. }
  1872. }
  1873. rc = regulator_enable(rgltr);
  1874. if (rc) {
  1875. CAM_ERR(CAM_UTIL, "%s regulator_enable failed", rgltr_name);
  1876. return rc;
  1877. }
  1878. if (rgltr_delay > 20)
  1879. msleep(rgltr_delay);
  1880. else if (rgltr_delay)
  1881. usleep_range(rgltr_delay * 1000,
  1882. (rgltr_delay * 1000) + 1000);
  1883. return rc;
  1884. }
  1885. int cam_soc_util_select_pinctrl_state(struct cam_hw_soc_info *soc_info,
  1886. int pctrl_idx, bool active)
  1887. {
  1888. int rc = 0;
  1889. struct cam_soc_pinctrl_info *pctrl_info = &soc_info->pinctrl_info;
  1890. if (pctrl_idx >= CAM_SOC_MAX_PINCTRL_MAP) {
  1891. CAM_ERR(CAM_UTIL, "Invalid Map idx: %d max supported: %d",
  1892. pctrl_idx, CAM_SOC_MAX_PINCTRL_MAP);
  1893. return -EINVAL;
  1894. }
  1895. if (pctrl_info->pctrl_state[pctrl_idx].gpio_state_active &&
  1896. active &&
  1897. !pctrl_info->pctrl_state[pctrl_idx].is_active) {
  1898. rc = pinctrl_select_state(pctrl_info->pinctrl,
  1899. pctrl_info->pctrl_state[pctrl_idx].gpio_state_active);
  1900. if (rc)
  1901. CAM_ERR(CAM_UTIL,
  1902. "Pinctrl active state transition failed: rc: %d",
  1903. rc);
  1904. else {
  1905. pctrl_info->pctrl_state[pctrl_idx].is_active = true;
  1906. CAM_DBG(CAM_UTIL, "Pctrl_idx: %d is in active state",
  1907. pctrl_idx);
  1908. }
  1909. }
  1910. if (pctrl_info->pctrl_state[pctrl_idx].gpio_state_suspend &&
  1911. !active &&
  1912. pctrl_info->pctrl_state[pctrl_idx].is_active) {
  1913. rc = pinctrl_select_state(pctrl_info->pinctrl,
  1914. pctrl_info->pctrl_state[pctrl_idx].gpio_state_suspend);
  1915. if (rc)
  1916. CAM_ERR(CAM_UTIL,
  1917. "Pinctrl suspend state transition failed: rc: %d",
  1918. rc);
  1919. else {
  1920. pctrl_info->pctrl_state[pctrl_idx].is_active = false;
  1921. CAM_DBG(CAM_UTIL, "Pctrl_idx: %d is in suspend state",
  1922. pctrl_idx);
  1923. }
  1924. }
  1925. return rc;
  1926. }
  1927. static int cam_soc_util_request_pinctrl(
  1928. struct cam_hw_soc_info *soc_info)
  1929. {
  1930. struct cam_soc_pinctrl_info *device_pctrl = &soc_info->pinctrl_info;
  1931. struct device *dev = soc_info->dev;
  1932. struct device_node *of_node = dev->of_node;
  1933. uint32_t i = 0;
  1934. int rc = 0;
  1935. const char *name;
  1936. uint32_t idx;
  1937. char pctrl_active[50];
  1938. char pctrl_suspend[50];
  1939. int32_t num_of_map_idx = 0;
  1940. int32_t num_of_string = 0;
  1941. device_pctrl->pinctrl = devm_pinctrl_get(dev);
  1942. if (IS_ERR_OR_NULL(device_pctrl->pinctrl)) {
  1943. CAM_DBG(CAM_UTIL, "Pinctrl not available");
  1944. device_pctrl->pinctrl = NULL;
  1945. return 0;
  1946. }
  1947. num_of_map_idx = of_property_count_u32_elems(
  1948. of_node, "pctrl-idx-mapping");
  1949. if (num_of_map_idx <= 0) {
  1950. CAM_ERR(CAM_UTIL,
  1951. "Reading pctrl-idx-mapping failed");
  1952. return -EINVAL;
  1953. }
  1954. num_of_string = of_property_count_strings(
  1955. of_node, "pctrl-map-names");
  1956. if (num_of_string <= 0) {
  1957. CAM_ERR(CAM_UTIL, "no pinctrl-mapping found for: %s",
  1958. soc_info->dev_name);
  1959. device_pctrl->pinctrl = NULL;
  1960. return -EINVAL;
  1961. }
  1962. if (num_of_map_idx != num_of_string) {
  1963. CAM_ERR(CAM_UTIL,
  1964. "Incorrect inputs mapping-idx count: %d mapping-names: %d",
  1965. num_of_map_idx, num_of_string);
  1966. device_pctrl->pinctrl = NULL;
  1967. return -EINVAL;
  1968. }
  1969. if (num_of_map_idx > CAM_SOC_MAX_PINCTRL_MAP) {
  1970. CAM_ERR(CAM_UTIL, "Invalid mapping %u max supported: %d",
  1971. num_of_map_idx, CAM_SOC_MAX_PINCTRL_MAP);
  1972. return -EINVAL;
  1973. }
  1974. for (i = 0; i < num_of_map_idx; i++) {
  1975. of_property_read_u32_index(of_node,
  1976. "pctrl-idx-mapping", i, &idx);
  1977. if (idx >= CAM_SOC_MAX_PINCTRL_MAP) {
  1978. CAM_ERR(CAM_UTIL, "Invalid Index: %d max supported: %d",
  1979. idx, CAM_SOC_MAX_PINCTRL_MAP);
  1980. return -EINVAL;
  1981. }
  1982. rc = of_property_read_string_index(
  1983. of_node, "pctrl-map-names", i, &name);
  1984. if (rc) {
  1985. CAM_ERR(CAM_UTIL,
  1986. "failed to read pinctrl-mapping at %d", i);
  1987. return rc;
  1988. }
  1989. snprintf(pctrl_active, sizeof(pctrl_active),
  1990. "%s%s", name, "_active");
  1991. CAM_DBG(CAM_UTIL, "pctrl_active at index: %d name: %s",
  1992. i, pctrl_active);
  1993. snprintf(pctrl_suspend, sizeof(pctrl_suspend),
  1994. "%s%s", name, "_suspend");
  1995. CAM_DBG(CAM_UTIL, "pctrl_suspend at index: %d name: %s",
  1996. i, pctrl_suspend);
  1997. device_pctrl->pctrl_state[idx].gpio_state_active =
  1998. pinctrl_lookup_state(device_pctrl->pinctrl,
  1999. pctrl_active);
  2000. if (IS_ERR_OR_NULL(
  2001. device_pctrl->pctrl_state[idx].gpio_state_active)) {
  2002. CAM_ERR(CAM_UTIL,
  2003. "Failed to get the active state pinctrl handle");
  2004. device_pctrl->pctrl_state[idx].gpio_state_active =
  2005. NULL;
  2006. return -EINVAL;
  2007. }
  2008. device_pctrl->pctrl_state[idx].gpio_state_suspend =
  2009. pinctrl_lookup_state(device_pctrl->pinctrl,
  2010. pctrl_suspend);
  2011. if (IS_ERR_OR_NULL(
  2012. device_pctrl->pctrl_state[idx].gpio_state_suspend)) {
  2013. CAM_ERR(CAM_UTIL,
  2014. "Failed to get the active state pinctrl handle");
  2015. device_pctrl->pctrl_state[idx].gpio_state_suspend = NULL;
  2016. return -EINVAL;
  2017. }
  2018. }
  2019. return 0;
  2020. }
  2021. static void cam_soc_util_release_pinctrl(struct cam_hw_soc_info *soc_info)
  2022. {
  2023. if (soc_info->pinctrl_info.pinctrl)
  2024. devm_pinctrl_put(soc_info->pinctrl_info.pinctrl);
  2025. }
  2026. static void cam_soc_util_regulator_disable_default(
  2027. struct cam_hw_soc_info *soc_info)
  2028. {
  2029. int j = 0;
  2030. uint32_t num_rgltr = soc_info->num_rgltr;
  2031. for (j = num_rgltr-1; j >= 0; j--) {
  2032. if (soc_info->rgltr_ctrl_support == true) {
  2033. cam_soc_util_regulator_disable(soc_info->rgltr[j],
  2034. soc_info->rgltr_name[j],
  2035. soc_info->rgltr_min_volt[j],
  2036. soc_info->rgltr_max_volt[j],
  2037. soc_info->rgltr_op_mode[j],
  2038. soc_info->rgltr_delay[j]);
  2039. } else {
  2040. if (soc_info->rgltr[j])
  2041. regulator_disable(soc_info->rgltr[j]);
  2042. }
  2043. }
  2044. }
  2045. static int cam_soc_util_regulator_enable_default(
  2046. struct cam_hw_soc_info *soc_info)
  2047. {
  2048. int j = 0, rc = 0;
  2049. uint32_t num_rgltr = soc_info->num_rgltr;
  2050. if (num_rgltr > CAM_SOC_MAX_REGULATOR) {
  2051. CAM_ERR(CAM_UTIL,
  2052. "%s has invalid regulator number %d",
  2053. soc_info->dev_name, num_rgltr);
  2054. return -EINVAL;
  2055. }
  2056. for (j = 0; j < num_rgltr; j++) {
  2057. if (soc_info->rgltr_ctrl_support == true) {
  2058. rc = cam_soc_util_regulator_enable(soc_info->rgltr[j],
  2059. soc_info->rgltr_name[j],
  2060. soc_info->rgltr_min_volt[j],
  2061. soc_info->rgltr_max_volt[j],
  2062. soc_info->rgltr_op_mode[j],
  2063. soc_info->rgltr_delay[j]);
  2064. } else {
  2065. if (soc_info->rgltr[j])
  2066. rc = regulator_enable(soc_info->rgltr[j]);
  2067. }
  2068. if (rc) {
  2069. CAM_ERR(CAM_UTIL, "%s enable failed",
  2070. soc_info->rgltr_name[j]);
  2071. goto disable_rgltr;
  2072. }
  2073. }
  2074. return rc;
  2075. disable_rgltr:
  2076. for (j--; j >= 0; j--) {
  2077. if (soc_info->rgltr_ctrl_support == true) {
  2078. cam_soc_util_regulator_disable(soc_info->rgltr[j],
  2079. soc_info->rgltr_name[j],
  2080. soc_info->rgltr_min_volt[j],
  2081. soc_info->rgltr_max_volt[j],
  2082. soc_info->rgltr_op_mode[j],
  2083. soc_info->rgltr_delay[j]);
  2084. } else {
  2085. if (soc_info->rgltr[j])
  2086. regulator_disable(soc_info->rgltr[j]);
  2087. }
  2088. }
  2089. return rc;
  2090. }
  2091. static bool cam_soc_util_is_presil_address_space(unsigned long mem_block_start)
  2092. {
  2093. if(mem_block_start >= CAM_SS_START_PRESIL && mem_block_start < CAM_SS_START)
  2094. return true;
  2095. return false;
  2096. }
  2097. #ifndef CONFIG_CAM_PRESIL
  2098. void __iomem * cam_soc_util_get_mem_base(
  2099. unsigned long mem_block_start,
  2100. unsigned long mem_block_size,
  2101. const char *mem_block_name,
  2102. uint32_t reserve_mem)
  2103. {
  2104. void __iomem * mem_base;
  2105. if (reserve_mem) {
  2106. if (!request_mem_region(mem_block_start,
  2107. mem_block_size,
  2108. mem_block_name)) {
  2109. CAM_ERR(CAM_UTIL,
  2110. "Error Mem region request Failed:%s",
  2111. mem_block_name);
  2112. return NULL;
  2113. }
  2114. }
  2115. mem_base = ioremap(mem_block_start, mem_block_size);
  2116. if (!mem_base) {
  2117. CAM_ERR(CAM_UTIL, "get mem base failed");
  2118. }
  2119. return mem_base;
  2120. }
  2121. int cam_soc_util_request_irq(struct device *dev,
  2122. unsigned int irq_line_start,
  2123. irq_handler_t handler,
  2124. unsigned long irqflags,
  2125. const char *irq_name,
  2126. void *irq_data,
  2127. unsigned long mem_block_start)
  2128. {
  2129. int rc;
  2130. rc = devm_request_irq(dev,
  2131. irq_line_start,
  2132. handler,
  2133. IRQF_TRIGGER_RISING,
  2134. irq_name,
  2135. irq_data);
  2136. if (rc) {
  2137. CAM_ERR(CAM_UTIL, "irq request fail rc %d", rc);
  2138. return -EBUSY;
  2139. }
  2140. disable_irq(irq_line_start);
  2141. return rc;
  2142. }
  2143. #else
  2144. void __iomem * cam_soc_util_get_mem_base(
  2145. unsigned long mem_block_start,
  2146. unsigned long mem_block_size,
  2147. const char *mem_block_name,
  2148. uint32_t reserve_mem)
  2149. {
  2150. void __iomem * mem_base;
  2151. if(cam_soc_util_is_presil_address_space(mem_block_start))
  2152. mem_base = (void __iomem *)mem_block_start;
  2153. else {
  2154. if (reserve_mem) {
  2155. if (!request_mem_region(mem_block_start,
  2156. mem_block_size,
  2157. mem_block_name)) {
  2158. CAM_ERR(CAM_UTIL,
  2159. "Error Mem region request Failed:%s",
  2160. mem_block_name);
  2161. return NULL;
  2162. }
  2163. }
  2164. mem_base = ioremap(mem_block_start, mem_block_size);
  2165. }
  2166. if (!mem_base) {
  2167. CAM_ERR(CAM_UTIL, "get mem base failed");
  2168. }
  2169. return mem_base;
  2170. }
  2171. int cam_soc_util_request_irq(struct device *dev,
  2172. unsigned int irq_line_start,
  2173. irq_handler_t handler,
  2174. unsigned long irqflags,
  2175. const char *irq_name,
  2176. void *irq_data,
  2177. unsigned long mem_block_start)
  2178. {
  2179. int rc;
  2180. if(cam_soc_util_is_presil_address_space(mem_block_start)) {
  2181. rc = devm_request_irq(dev,
  2182. irq_line_start,
  2183. handler,
  2184. irqflags,
  2185. irq_name,
  2186. irq_data);
  2187. if (rc) {
  2188. CAM_ERR(CAM_UTIL, "presil irq request fail");
  2189. return -EBUSY;
  2190. }
  2191. disable_irq(irq_line_start);
  2192. rc = !(cam_presil_subscribe_device_irq(irq_line_start,
  2193. handler, irq_data, irq_name));
  2194. CAM_DBG(CAM_PRESIL, "Subscribe presil IRQ: rc=%d NUM=%d Name=%s handler=0x%x",
  2195. rc, irq_line_start, irq_name, handler);
  2196. if (rc) {
  2197. CAM_ERR(CAM_UTIL, "presil irq request fail");
  2198. return -EBUSY;
  2199. }
  2200. } else {
  2201. rc = devm_request_irq(dev,
  2202. irq_line_start,
  2203. handler,
  2204. irqflags,
  2205. irq_name,
  2206. irq_data);
  2207. if (rc) {
  2208. CAM_ERR(CAM_UTIL, "irq request fail");
  2209. return -EBUSY;
  2210. }
  2211. disable_irq(irq_line_start);
  2212. CAM_INFO(CAM_UTIL, "Subscribe for non-presil IRQ success");
  2213. }
  2214. CAM_INFO(CAM_UTIL, "returning IRQ for mem_block_start 0x%0x rc %d",
  2215. mem_block_start, rc);
  2216. return rc;
  2217. }
  2218. #endif
  2219. int cam_soc_util_request_platform_resource(
  2220. struct cam_hw_soc_info *soc_info,
  2221. irq_handler_t handler, void *irq_data)
  2222. {
  2223. int i = 0, rc = 0;
  2224. if (!soc_info || !soc_info->dev) {
  2225. CAM_ERR(CAM_UTIL, "Invalid parameters");
  2226. return -EINVAL;
  2227. }
  2228. for (i = 0; i < soc_info->num_mem_block; i++) {
  2229. soc_info->reg_map[i].mem_base = cam_soc_util_get_mem_base(
  2230. soc_info->mem_block[i]->start,
  2231. resource_size(soc_info->mem_block[i]),
  2232. soc_info->mem_block_name[i],
  2233. soc_info->reserve_mem);
  2234. if (!soc_info->reg_map[i].mem_base) {
  2235. CAM_ERR(CAM_UTIL, "i= %d base NULL", i);
  2236. rc = -ENOMEM;
  2237. goto unmap_base;
  2238. }
  2239. soc_info->reg_map[i].mem_cam_base =
  2240. soc_info->mem_block_cam_base[i];
  2241. soc_info->reg_map[i].size =
  2242. resource_size(soc_info->mem_block[i]);
  2243. soc_info->num_reg_map++;
  2244. }
  2245. for (i = 0; i < soc_info->num_rgltr; i++) {
  2246. if (soc_info->rgltr_name[i] == NULL) {
  2247. CAM_ERR(CAM_UTIL, "can't find regulator name");
  2248. goto put_regulator;
  2249. }
  2250. rc = cam_soc_util_get_regulator(soc_info->dev,
  2251. &soc_info->rgltr[i],
  2252. soc_info->rgltr_name[i]);
  2253. if (rc)
  2254. goto put_regulator;
  2255. }
  2256. if (soc_info->irq_num > 0) {
  2257. rc = cam_soc_util_request_irq(soc_info->dev,
  2258. soc_info->irq_num,
  2259. handler, IRQF_TRIGGER_RISING,
  2260. soc_info->irq_name, irq_data,
  2261. soc_info->mem_block[0]->start);
  2262. if (rc) {
  2263. CAM_ERR(CAM_UTIL, "irq request fail");
  2264. rc = -EBUSY;
  2265. goto put_regulator;
  2266. }
  2267. soc_info->irq_data = irq_data;
  2268. }
  2269. /* Get Clock */
  2270. for (i = 0; i < soc_info->num_clk; i++) {
  2271. soc_info->clk[i] = clk_get(soc_info->dev,
  2272. soc_info->clk_name[i]);
  2273. if (!soc_info->clk[i]) {
  2274. CAM_ERR(CAM_UTIL, "get failed for %s",
  2275. soc_info->clk_name[i]);
  2276. rc = -ENOENT;
  2277. goto put_clk;
  2278. }
  2279. /* Create a wrapper entry if this is a shared clock */
  2280. if (CAM_IS_BIT_SET(soc_info->shared_clk_mask, i)) {
  2281. uint32_t min_level = soc_info->lowest_clk_level;
  2282. CAM_DBG(CAM_UTIL,
  2283. "Dev %s, clk %s, id %d register wrapper entry for shared clk",
  2284. soc_info->dev_name, soc_info->clk_name[i],
  2285. soc_info->clk_id[i]);
  2286. rc = cam_soc_util_clk_wrapper_register_entry(
  2287. soc_info->clk_id[i], soc_info->clk[i],
  2288. (i == soc_info->src_clk_idx) ? true : false,
  2289. soc_info, soc_info->clk_rate[min_level][i],
  2290. soc_info->clk_name[i]);
  2291. if (rc) {
  2292. CAM_ERR(CAM_UTIL,
  2293. "Failed in registering shared clk Dev %s id %d",
  2294. soc_info->dev_name,
  2295. soc_info->clk_id[i]);
  2296. clk_put(soc_info->clk[i]);
  2297. soc_info->clk[i] = NULL;
  2298. goto put_clk;
  2299. }
  2300. } else if (i == soc_info->src_clk_idx) {
  2301. rc = cam_soc_util_register_mmrm_client(
  2302. soc_info->clk_id[i], soc_info->clk[i],
  2303. soc_info->is_nrt_dev,
  2304. soc_info, soc_info->clk_name[i],
  2305. &soc_info->mmrm_handle);
  2306. if (rc) {
  2307. CAM_ERR(CAM_UTIL,
  2308. "Failed in register mmrm client Dev %s clk id %d",
  2309. soc_info->dev_name,
  2310. soc_info->clk_id[i]);
  2311. clk_put(soc_info->clk[i]);
  2312. soc_info->clk[i] = NULL;
  2313. goto put_clk;
  2314. }
  2315. }
  2316. }
  2317. rc = cam_soc_util_request_pinctrl(soc_info);
  2318. if (rc) {
  2319. CAM_ERR(CAM_UTIL, "Failed in requesting Pinctrl, rc: %d", rc);
  2320. goto put_clk;
  2321. }
  2322. rc = cam_soc_util_request_gpio_table(soc_info, true);
  2323. if (rc) {
  2324. CAM_ERR(CAM_UTIL, "Failed in request gpio table, rc=%d", rc);
  2325. goto put_clk;
  2326. }
  2327. if (soc_info->clk_control_enable)
  2328. cam_soc_util_create_clk_lvl_debugfs(soc_info);
  2329. return rc;
  2330. put_clk:
  2331. if (soc_info->mmrm_handle) {
  2332. cam_soc_util_unregister_mmrm_client(soc_info->mmrm_handle);
  2333. soc_info->mmrm_handle = NULL;
  2334. }
  2335. if (i == -1)
  2336. i = soc_info->num_clk;
  2337. for (i = i - 1; i >= 0; i--) {
  2338. if (soc_info->clk[i]) {
  2339. if (CAM_IS_BIT_SET(soc_info->shared_clk_mask, i))
  2340. cam_soc_util_clk_wrapper_unregister_entry(
  2341. soc_info->clk_id[i], soc_info);
  2342. clk_put(soc_info->clk[i]);
  2343. soc_info->clk[i] = NULL;
  2344. }
  2345. }
  2346. if (soc_info->irq_num > 0) {
  2347. disable_irq(soc_info->irq_num);
  2348. devm_free_irq(soc_info->dev,
  2349. soc_info->irq_num, irq_data);
  2350. }
  2351. put_regulator:
  2352. if (i == -1)
  2353. i = soc_info->num_rgltr;
  2354. for (i = i - 1; i >= 0; i--) {
  2355. if (soc_info->rgltr[i]) {
  2356. regulator_disable(soc_info->rgltr[i]);
  2357. regulator_put(soc_info->rgltr[i]);
  2358. soc_info->rgltr[i] = NULL;
  2359. }
  2360. }
  2361. unmap_base:
  2362. if (i == -1)
  2363. i = soc_info->num_reg_map;
  2364. for (i = i - 1; i >= 0; i--) {
  2365. if (soc_info->reserve_mem)
  2366. release_mem_region(soc_info->mem_block[i]->start,
  2367. resource_size(soc_info->mem_block[i]));
  2368. iounmap(soc_info->reg_map[i].mem_base);
  2369. soc_info->reg_map[i].mem_base = NULL;
  2370. soc_info->reg_map[i].size = 0;
  2371. }
  2372. return rc;
  2373. }
  2374. int cam_soc_util_release_platform_resource(struct cam_hw_soc_info *soc_info)
  2375. {
  2376. int i;
  2377. bool b_ret = false;
  2378. if (!soc_info || !soc_info->dev) {
  2379. CAM_ERR(CAM_UTIL, "Invalid parameter");
  2380. return -EINVAL;
  2381. }
  2382. if (soc_info->mmrm_handle) {
  2383. cam_soc_util_unregister_mmrm_client(soc_info->mmrm_handle);
  2384. soc_info->mmrm_handle = NULL;
  2385. }
  2386. for (i = soc_info->num_clk - 1; i >= 0; i--) {
  2387. if (CAM_IS_BIT_SET(soc_info->shared_clk_mask, i))
  2388. cam_soc_util_clk_wrapper_unregister_entry(
  2389. soc_info->clk_id[i], soc_info);
  2390. clk_put(soc_info->clk[i]);
  2391. soc_info->clk[i] = NULL;
  2392. }
  2393. for (i = soc_info->num_rgltr - 1; i >= 0; i--) {
  2394. if (soc_info->rgltr[i]) {
  2395. regulator_put(soc_info->rgltr[i]);
  2396. soc_info->rgltr[i] = NULL;
  2397. }
  2398. }
  2399. for (i = soc_info->num_reg_map - 1; i >= 0; i--) {
  2400. iounmap(soc_info->reg_map[i].mem_base);
  2401. soc_info->reg_map[i].mem_base = NULL;
  2402. soc_info->reg_map[i].size = 0;
  2403. }
  2404. if (soc_info->irq_num > 0) {
  2405. if (cam_presil_mode_enabled()) {
  2406. if (cam_soc_util_is_presil_address_space(soc_info->mem_block[0]->start)) {
  2407. b_ret = cam_presil_unsubscribe_device_irq(
  2408. soc_info->irq_line->start);
  2409. CAM_DBG(CAM_PRESIL, "UnSubscribe IRQ: Ret=%d NUM=%d Name=%s",
  2410. b_ret, soc_info->irq_line->start, soc_info->irq_name);
  2411. }
  2412. }
  2413. disable_irq(soc_info->irq_num);
  2414. devm_free_irq(soc_info->dev,
  2415. soc_info->irq_num, soc_info->irq_data);
  2416. }
  2417. cam_soc_util_release_pinctrl(soc_info);
  2418. /* release for gpio */
  2419. cam_soc_util_request_gpio_table(soc_info, false);
  2420. soc_info->dentry = NULL;
  2421. return 0;
  2422. }
  2423. int cam_soc_util_enable_platform_resource(struct cam_hw_soc_info *soc_info,
  2424. bool enable_clocks, enum cam_vote_level clk_level, bool enable_irq)
  2425. {
  2426. int rc = 0;
  2427. if (!soc_info)
  2428. return -EINVAL;
  2429. rc = cam_soc_util_regulator_enable_default(soc_info);
  2430. if (rc) {
  2431. CAM_ERR(CAM_UTIL, "Regulators enable failed");
  2432. return rc;
  2433. }
  2434. if (enable_clocks) {
  2435. rc = cam_soc_util_clk_enable_default(soc_info, clk_level);
  2436. if (rc)
  2437. goto disable_regulator;
  2438. }
  2439. if (enable_irq) {
  2440. rc = cam_soc_util_irq_enable(soc_info);
  2441. if (rc)
  2442. goto disable_clk;
  2443. }
  2444. return rc;
  2445. disable_clk:
  2446. if (enable_clocks)
  2447. cam_soc_util_clk_disable_default(soc_info);
  2448. disable_regulator:
  2449. cam_soc_util_regulator_disable_default(soc_info);
  2450. return rc;
  2451. }
  2452. int cam_soc_util_disable_platform_resource(struct cam_hw_soc_info *soc_info,
  2453. bool disable_clocks, bool disable_irq)
  2454. {
  2455. int rc = 0;
  2456. if (!soc_info)
  2457. return -EINVAL;
  2458. if (disable_irq)
  2459. rc |= cam_soc_util_irq_disable(soc_info);
  2460. if (disable_clocks)
  2461. cam_soc_util_clk_disable_default(soc_info);
  2462. cam_soc_util_regulator_disable_default(soc_info);
  2463. return rc;
  2464. }
  2465. int cam_soc_util_reg_dump(struct cam_hw_soc_info *soc_info,
  2466. uint32_t base_index, uint32_t offset, int size)
  2467. {
  2468. void __iomem *base_addr = NULL;
  2469. CAM_DBG(CAM_UTIL, "base_idx %u size=%d", base_index, size);
  2470. if (!soc_info || base_index >= soc_info->num_reg_map ||
  2471. size <= 0 || (offset + size) >=
  2472. CAM_SOC_GET_REG_MAP_SIZE(soc_info, base_index))
  2473. return -EINVAL;
  2474. base_addr = CAM_SOC_GET_REG_MAP_START(soc_info, base_index);
  2475. /*
  2476. * All error checking already done above,
  2477. * hence ignoring the return value below.
  2478. */
  2479. cam_io_dump(base_addr, offset, size);
  2480. return 0;
  2481. }
  2482. static int cam_soc_util_dump_cont_reg_range(
  2483. struct cam_hw_soc_info *soc_info,
  2484. struct cam_reg_range_read_desc *reg_read, uint32_t base_idx,
  2485. struct cam_reg_dump_out_buffer *dump_out_buf, uintptr_t cmd_buf_end)
  2486. {
  2487. int i = 0, rc = 0;
  2488. uint32_t write_idx = 0;
  2489. if (!soc_info || !dump_out_buf || !reg_read || !cmd_buf_end) {
  2490. CAM_ERR(CAM_UTIL,
  2491. "Invalid input args soc_info: %pK, dump_out_buffer: %pK reg_read: %pK cmd_buf_end: %pK",
  2492. soc_info, dump_out_buf, reg_read, cmd_buf_end);
  2493. rc = -EINVAL;
  2494. goto end;
  2495. }
  2496. if ((reg_read->num_values) && ((reg_read->num_values > U32_MAX / 2) ||
  2497. (sizeof(uint32_t) > ((U32_MAX -
  2498. sizeof(struct cam_reg_dump_out_buffer) -
  2499. dump_out_buf->bytes_written) /
  2500. (reg_read->num_values * 2))))) {
  2501. CAM_ERR(CAM_UTIL,
  2502. "Integer Overflow bytes_written: [%u] num_values: [%u]",
  2503. dump_out_buf->bytes_written, reg_read->num_values);
  2504. rc = -EOVERFLOW;
  2505. goto end;
  2506. }
  2507. if ((cmd_buf_end - (uintptr_t)dump_out_buf) <=
  2508. (uintptr_t)(sizeof(struct cam_reg_dump_out_buffer)
  2509. - sizeof(uint32_t) + dump_out_buf->bytes_written +
  2510. (reg_read->num_values * 2 * sizeof(uint32_t)))) {
  2511. CAM_ERR(CAM_UTIL,
  2512. "Insufficient space in out buffer num_values: [%d] cmd_buf_end: %pK dump_out_buf: %pK",
  2513. reg_read->num_values, cmd_buf_end,
  2514. (uintptr_t)dump_out_buf);
  2515. rc = -EINVAL;
  2516. goto end;
  2517. }
  2518. write_idx = dump_out_buf->bytes_written / sizeof(uint32_t);
  2519. for (i = 0; i < reg_read->num_values; i++) {
  2520. if ((reg_read->offset + (i * sizeof(uint32_t))) >
  2521. (uint32_t)soc_info->reg_map[base_idx].size) {
  2522. CAM_ERR(CAM_UTIL,
  2523. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2524. (reg_read->offset + (i * sizeof(uint32_t))),
  2525. (uint32_t)soc_info->reg_map[base_idx].size);
  2526. rc = -EINVAL;
  2527. goto end;
  2528. }
  2529. dump_out_buf->dump_data[write_idx++] = reg_read->offset +
  2530. (i * sizeof(uint32_t));
  2531. dump_out_buf->dump_data[write_idx++] =
  2532. cam_soc_util_r(soc_info, base_idx,
  2533. (reg_read->offset + (i * sizeof(uint32_t))));
  2534. dump_out_buf->bytes_written += (2 * sizeof(uint32_t));
  2535. }
  2536. end:
  2537. return rc;
  2538. }
  2539. static int cam_soc_util_dump_dmi_reg_range(
  2540. struct cam_hw_soc_info *soc_info,
  2541. struct cam_dmi_read_desc *dmi_read, uint32_t base_idx,
  2542. struct cam_reg_dump_out_buffer *dump_out_buf, uintptr_t cmd_buf_end)
  2543. {
  2544. int i = 0, rc = 0;
  2545. uint32_t write_idx = 0;
  2546. if (!soc_info || !dump_out_buf || !dmi_read || !cmd_buf_end) {
  2547. CAM_ERR(CAM_UTIL,
  2548. "Invalid input args soc_info: %pK, dump_out_buffer: %pK",
  2549. soc_info, dump_out_buf);
  2550. rc = -EINVAL;
  2551. goto end;
  2552. }
  2553. if (dmi_read->num_pre_writes > CAM_REG_DUMP_DMI_CONFIG_MAX ||
  2554. dmi_read->num_post_writes > CAM_REG_DUMP_DMI_CONFIG_MAX) {
  2555. CAM_ERR(CAM_UTIL,
  2556. "Invalid number of requested writes, pre: %d post: %d",
  2557. dmi_read->num_pre_writes, dmi_read->num_post_writes);
  2558. rc = -EINVAL;
  2559. goto end;
  2560. }
  2561. if ((dmi_read->num_pre_writes + dmi_read->dmi_data_read.num_values)
  2562. && ((dmi_read->num_pre_writes > U32_MAX / 2) ||
  2563. (dmi_read->dmi_data_read.num_values > U32_MAX / 2) ||
  2564. ((dmi_read->num_pre_writes * 2) > U32_MAX -
  2565. (dmi_read->dmi_data_read.num_values * 2)) ||
  2566. (sizeof(uint32_t) > ((U32_MAX -
  2567. sizeof(struct cam_reg_dump_out_buffer) -
  2568. dump_out_buf->bytes_written) / ((dmi_read->num_pre_writes +
  2569. dmi_read->dmi_data_read.num_values) * 2))))) {
  2570. CAM_ERR(CAM_UTIL,
  2571. "Integer Overflow bytes_written: [%u] num_pre_writes: [%u] num_values: [%u]",
  2572. dump_out_buf->bytes_written, dmi_read->num_pre_writes,
  2573. dmi_read->dmi_data_read.num_values);
  2574. rc = -EOVERFLOW;
  2575. goto end;
  2576. }
  2577. if ((cmd_buf_end - (uintptr_t)dump_out_buf) <=
  2578. (uintptr_t)(
  2579. sizeof(struct cam_reg_dump_out_buffer) - sizeof(uint32_t) +
  2580. (dump_out_buf->bytes_written +
  2581. (dmi_read->num_pre_writes * 2 * sizeof(uint32_t)) +
  2582. (dmi_read->dmi_data_read.num_values * 2 *
  2583. sizeof(uint32_t))))) {
  2584. CAM_ERR(CAM_UTIL,
  2585. "Insufficient space in out buffer num_read_val: [%d] num_write_val: [%d] cmd_buf_end: %pK dump_out_buf: %pK",
  2586. dmi_read->dmi_data_read.num_values,
  2587. dmi_read->num_pre_writes, cmd_buf_end,
  2588. (uintptr_t)dump_out_buf);
  2589. rc = -EINVAL;
  2590. goto end;
  2591. }
  2592. write_idx = dump_out_buf->bytes_written / sizeof(uint32_t);
  2593. for (i = 0; i < dmi_read->num_pre_writes; i++) {
  2594. if (dmi_read->pre_read_config[i].offset >
  2595. (uint32_t)soc_info->reg_map[base_idx].size) {
  2596. CAM_ERR(CAM_UTIL,
  2597. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2598. dmi_read->pre_read_config[i].offset,
  2599. (uint32_t)soc_info->reg_map[base_idx].size);
  2600. rc = -EINVAL;
  2601. goto end;
  2602. }
  2603. cam_soc_util_w_mb(soc_info, base_idx,
  2604. dmi_read->pre_read_config[i].offset,
  2605. dmi_read->pre_read_config[i].value);
  2606. dump_out_buf->dump_data[write_idx++] =
  2607. dmi_read->pre_read_config[i].offset;
  2608. dump_out_buf->dump_data[write_idx++] =
  2609. dmi_read->pre_read_config[i].value;
  2610. dump_out_buf->bytes_written += (2 * sizeof(uint32_t));
  2611. }
  2612. if (dmi_read->dmi_data_read.offset >
  2613. (uint32_t)soc_info->reg_map[base_idx].size) {
  2614. CAM_ERR(CAM_UTIL,
  2615. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2616. dmi_read->dmi_data_read.offset,
  2617. (uint32_t)soc_info->reg_map[base_idx].size);
  2618. rc = -EINVAL;
  2619. goto end;
  2620. }
  2621. for (i = 0; i < dmi_read->dmi_data_read.num_values; i++) {
  2622. dump_out_buf->dump_data[write_idx++] =
  2623. dmi_read->dmi_data_read.offset;
  2624. dump_out_buf->dump_data[write_idx++] =
  2625. cam_soc_util_r_mb(soc_info, base_idx,
  2626. dmi_read->dmi_data_read.offset);
  2627. dump_out_buf->bytes_written += (2 * sizeof(uint32_t));
  2628. }
  2629. for (i = 0; i < dmi_read->num_post_writes; i++) {
  2630. if (dmi_read->post_read_config[i].offset >
  2631. (uint32_t)soc_info->reg_map[base_idx].size) {
  2632. CAM_ERR(CAM_UTIL,
  2633. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2634. dmi_read->post_read_config[i].offset,
  2635. (uint32_t)soc_info->reg_map[base_idx].size);
  2636. rc = -EINVAL;
  2637. goto end;
  2638. }
  2639. cam_soc_util_w_mb(soc_info, base_idx,
  2640. dmi_read->post_read_config[i].offset,
  2641. dmi_read->post_read_config[i].value);
  2642. }
  2643. end:
  2644. return rc;
  2645. }
  2646. static int cam_soc_util_dump_dmi_reg_range_user_buf(
  2647. struct cam_hw_soc_info *soc_info,
  2648. struct cam_dmi_read_desc *dmi_read, uint32_t base_idx,
  2649. struct cam_hw_soc_dump_args *dump_args)
  2650. {
  2651. int i;
  2652. int rc;
  2653. size_t buf_len = 0;
  2654. uint8_t *dst;
  2655. size_t remain_len;
  2656. uint32_t min_len;
  2657. uint32_t *waddr, *start;
  2658. uintptr_t cpu_addr;
  2659. struct cam_hw_soc_dump_header *hdr;
  2660. if (!soc_info || !dump_args || !dmi_read) {
  2661. CAM_ERR(CAM_UTIL,
  2662. "Invalid input args soc_info: %pK, dump_args: %pK",
  2663. soc_info, dump_args);
  2664. rc = -EINVAL;
  2665. goto end;
  2666. }
  2667. if (dmi_read->num_pre_writes > CAM_REG_DUMP_DMI_CONFIG_MAX ||
  2668. dmi_read->num_post_writes > CAM_REG_DUMP_DMI_CONFIG_MAX) {
  2669. CAM_ERR(CAM_UTIL,
  2670. "Invalid number of requested writes, pre: %d post: %d",
  2671. dmi_read->num_pre_writes, dmi_read->num_post_writes);
  2672. rc = -EINVAL;
  2673. goto end;
  2674. }
  2675. rc = cam_mem_get_cpu_buf(dump_args->buf_handle, &cpu_addr, &buf_len);
  2676. if (rc) {
  2677. CAM_ERR(CAM_UTIL, "Invalid handle %u rc %d",
  2678. dump_args->buf_handle, rc);
  2679. goto end;
  2680. }
  2681. if (buf_len <= dump_args->offset) {
  2682. CAM_WARN(CAM_UTIL, "Dump offset overshoot offset %zu len %zu",
  2683. dump_args->offset, buf_len);
  2684. rc = -ENOSPC;
  2685. goto end;
  2686. }
  2687. remain_len = buf_len - dump_args->offset;
  2688. min_len = (dmi_read->num_pre_writes * 2 * sizeof(uint32_t)) +
  2689. (dmi_read->dmi_data_read.num_values * 2 * sizeof(uint32_t)) +
  2690. sizeof(uint32_t);
  2691. if (remain_len < min_len) {
  2692. CAM_WARN(CAM_UTIL,
  2693. "Dump Buffer exhaust read %d write %d remain %zu min %u",
  2694. dmi_read->dmi_data_read.num_values,
  2695. dmi_read->num_pre_writes, remain_len,
  2696. min_len);
  2697. rc = -ENOSPC;
  2698. goto end;
  2699. }
  2700. dst = (uint8_t *)cpu_addr + dump_args->offset;
  2701. hdr = (struct cam_hw_soc_dump_header *)dst;
  2702. memset(hdr, 0, sizeof(struct cam_hw_soc_dump_header));
  2703. scnprintf(hdr->tag, CAM_SOC_HW_DUMP_TAG_MAX_LEN,
  2704. "DMI_DUMP:");
  2705. waddr = (uint32_t *)(dst + sizeof(struct cam_hw_soc_dump_header));
  2706. start = waddr;
  2707. hdr->word_size = sizeof(uint32_t);
  2708. *waddr = soc_info->index;
  2709. waddr++;
  2710. for (i = 0; i < dmi_read->num_pre_writes; i++) {
  2711. if (dmi_read->pre_read_config[i].offset >
  2712. (uint32_t)soc_info->reg_map[base_idx].size) {
  2713. CAM_ERR(CAM_UTIL,
  2714. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2715. dmi_read->pre_read_config[i].offset,
  2716. (uint32_t)soc_info->reg_map[base_idx].size);
  2717. rc = -EINVAL;
  2718. goto end;
  2719. }
  2720. cam_soc_util_w_mb(soc_info, base_idx,
  2721. dmi_read->pre_read_config[i].offset,
  2722. dmi_read->pre_read_config[i].value);
  2723. *waddr++ = dmi_read->pre_read_config[i].offset;
  2724. *waddr++ = dmi_read->pre_read_config[i].value;
  2725. }
  2726. if (dmi_read->dmi_data_read.offset >
  2727. (uint32_t)soc_info->reg_map[base_idx].size) {
  2728. CAM_ERR(CAM_UTIL,
  2729. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2730. dmi_read->dmi_data_read.offset,
  2731. (uint32_t)soc_info->reg_map[base_idx].size);
  2732. rc = -EINVAL;
  2733. goto end;
  2734. }
  2735. for (i = 0; i < dmi_read->dmi_data_read.num_values; i++) {
  2736. *waddr++ = dmi_read->dmi_data_read.offset;
  2737. *waddr++ = cam_soc_util_r_mb(soc_info, base_idx,
  2738. dmi_read->dmi_data_read.offset);
  2739. }
  2740. for (i = 0; i < dmi_read->num_post_writes; i++) {
  2741. if (dmi_read->post_read_config[i].offset >
  2742. (uint32_t)soc_info->reg_map[base_idx].size) {
  2743. CAM_ERR(CAM_UTIL,
  2744. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2745. dmi_read->post_read_config[i].offset,
  2746. (uint32_t)soc_info->reg_map[base_idx].size);
  2747. rc = -EINVAL;
  2748. goto end;
  2749. }
  2750. cam_soc_util_w_mb(soc_info, base_idx,
  2751. dmi_read->post_read_config[i].offset,
  2752. dmi_read->post_read_config[i].value);
  2753. }
  2754. hdr->size = (waddr - start) * hdr->word_size;
  2755. dump_args->offset += hdr->size +
  2756. sizeof(struct cam_hw_soc_dump_header);
  2757. end:
  2758. return rc;
  2759. }
  2760. static int cam_soc_util_dump_cont_reg_range_user_buf(
  2761. struct cam_hw_soc_info *soc_info,
  2762. struct cam_reg_range_read_desc *reg_read,
  2763. uint32_t base_idx,
  2764. struct cam_hw_soc_dump_args *dump_args)
  2765. {
  2766. int i;
  2767. int rc = 0;
  2768. size_t buf_len;
  2769. uint8_t *dst;
  2770. size_t remain_len;
  2771. uint32_t min_len;
  2772. uint32_t *waddr, *start;
  2773. uintptr_t cpu_addr;
  2774. struct cam_hw_soc_dump_header *hdr;
  2775. if (!soc_info || !dump_args || !reg_read) {
  2776. CAM_ERR(CAM_UTIL,
  2777. "Invalid input args soc_info: %pK, dump_out_buffer: %pK reg_read: %pK",
  2778. soc_info, dump_args, reg_read);
  2779. rc = -EINVAL;
  2780. goto end;
  2781. }
  2782. rc = cam_mem_get_cpu_buf(dump_args->buf_handle, &cpu_addr, &buf_len);
  2783. if (rc) {
  2784. CAM_ERR(CAM_UTIL, "Invalid handle %u rc %d",
  2785. dump_args->buf_handle, rc);
  2786. goto end;
  2787. }
  2788. if (buf_len <= dump_args->offset) {
  2789. CAM_WARN(CAM_UTIL, "Dump offset overshoot %zu %zu",
  2790. dump_args->offset, buf_len);
  2791. rc = -ENOSPC;
  2792. goto end;
  2793. }
  2794. remain_len = buf_len - dump_args->offset;
  2795. min_len = (reg_read->num_values * 2 * sizeof(uint32_t)) +
  2796. sizeof(struct cam_hw_soc_dump_header) + sizeof(uint32_t);
  2797. if (remain_len < min_len) {
  2798. CAM_WARN(CAM_UTIL,
  2799. "Dump Buffer exhaust read_values %d remain %zu min %u",
  2800. reg_read->num_values,
  2801. remain_len,
  2802. min_len);
  2803. rc = -ENOSPC;
  2804. goto end;
  2805. }
  2806. dst = (uint8_t *)cpu_addr + dump_args->offset;
  2807. hdr = (struct cam_hw_soc_dump_header *)dst;
  2808. memset(hdr, 0, sizeof(struct cam_hw_soc_dump_header));
  2809. scnprintf(hdr->tag, CAM_SOC_HW_DUMP_TAG_MAX_LEN, "%s_REG:",
  2810. soc_info->dev_name);
  2811. waddr = (uint32_t *)(dst + sizeof(struct cam_hw_soc_dump_header));
  2812. start = waddr;
  2813. hdr->word_size = sizeof(uint32_t);
  2814. *waddr = soc_info->index;
  2815. waddr++;
  2816. for (i = 0; i < reg_read->num_values; i++) {
  2817. if ((reg_read->offset + (i * sizeof(uint32_t))) >
  2818. (uint32_t)soc_info->reg_map[base_idx].size) {
  2819. CAM_ERR(CAM_UTIL,
  2820. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2821. (reg_read->offset + (i * sizeof(uint32_t))),
  2822. (uint32_t)soc_info->reg_map[base_idx].size);
  2823. rc = -EINVAL;
  2824. goto end;
  2825. }
  2826. waddr[0] = reg_read->offset + (i * sizeof(uint32_t));
  2827. waddr[1] = cam_soc_util_r(soc_info, base_idx,
  2828. (reg_read->offset + (i * sizeof(uint32_t))));
  2829. waddr += 2;
  2830. }
  2831. hdr->size = (waddr - start) * hdr->word_size;
  2832. dump_args->offset += hdr->size +
  2833. sizeof(struct cam_hw_soc_dump_header);
  2834. end:
  2835. return rc;
  2836. }
  2837. static int cam_soc_util_user_reg_dump(
  2838. struct cam_reg_dump_desc *reg_dump_desc,
  2839. struct cam_hw_soc_dump_args *dump_args,
  2840. struct cam_hw_soc_info *soc_info,
  2841. uint32_t reg_base_idx)
  2842. {
  2843. int rc = 0;
  2844. int i;
  2845. struct cam_reg_read_info *reg_read_info = NULL;
  2846. if (!dump_args || !reg_dump_desc || !soc_info) {
  2847. CAM_ERR(CAM_UTIL,
  2848. "Invalid input parameters %pK %pK %pK",
  2849. dump_args, reg_dump_desc, soc_info);
  2850. return -EINVAL;
  2851. }
  2852. for (i = 0; i < reg_dump_desc->num_read_range; i++) {
  2853. reg_read_info = &reg_dump_desc->read_range[i];
  2854. if (reg_read_info->type ==
  2855. CAM_REG_DUMP_READ_TYPE_CONT_RANGE) {
  2856. rc = cam_soc_util_dump_cont_reg_range_user_buf(
  2857. soc_info,
  2858. &reg_read_info->reg_read,
  2859. reg_base_idx,
  2860. dump_args);
  2861. } else if (reg_read_info->type ==
  2862. CAM_REG_DUMP_READ_TYPE_DMI) {
  2863. rc = cam_soc_util_dump_dmi_reg_range_user_buf(
  2864. soc_info,
  2865. &reg_read_info->dmi_read,
  2866. reg_base_idx,
  2867. dump_args);
  2868. } else {
  2869. CAM_ERR(CAM_UTIL,
  2870. "Invalid Reg dump read type: %d",
  2871. reg_read_info->type);
  2872. rc = -EINVAL;
  2873. goto end;
  2874. }
  2875. if (rc) {
  2876. CAM_ERR(CAM_UTIL,
  2877. "Reg range read failed rc: %d reg_base_idx: %d",
  2878. rc, reg_base_idx);
  2879. goto end;
  2880. }
  2881. }
  2882. end:
  2883. return rc;
  2884. }
  2885. int cam_soc_util_reg_dump_to_cmd_buf(void *ctx,
  2886. struct cam_cmd_buf_desc *cmd_desc, uint64_t req_id,
  2887. cam_soc_util_regspace_data_cb reg_data_cb,
  2888. struct cam_hw_soc_dump_args *soc_dump_args,
  2889. bool user_triggered_dump)
  2890. {
  2891. int rc = 0, i, j;
  2892. uintptr_t cpu_addr = 0;
  2893. uintptr_t cmd_buf_start = 0;
  2894. uintptr_t cmd_in_data_end = 0;
  2895. uintptr_t cmd_buf_end = 0;
  2896. uint32_t reg_base_type = 0;
  2897. size_t buf_size = 0, remain_len = 0;
  2898. struct cam_reg_dump_input_info *reg_input_info = NULL;
  2899. struct cam_reg_dump_desc *reg_dump_desc = NULL;
  2900. struct cam_reg_dump_out_buffer *dump_out_buf = NULL;
  2901. struct cam_reg_read_info *reg_read_info = NULL;
  2902. struct cam_hw_soc_info *soc_info;
  2903. uint32_t reg_base_idx = 0;
  2904. if (!ctx || !cmd_desc || !reg_data_cb) {
  2905. CAM_ERR(CAM_UTIL, "Invalid args to reg dump [%pK] [%pK]",
  2906. cmd_desc, reg_data_cb);
  2907. return -EINVAL;
  2908. }
  2909. if (!cmd_desc->length || !cmd_desc->size) {
  2910. CAM_ERR(CAM_UTIL, "Invalid cmd buf size %d %d",
  2911. cmd_desc->length, cmd_desc->size);
  2912. return -EINVAL;
  2913. }
  2914. rc = cam_mem_get_cpu_buf(cmd_desc->mem_handle, &cpu_addr, &buf_size);
  2915. if (rc || !cpu_addr || (buf_size == 0)) {
  2916. CAM_ERR(CAM_UTIL, "Failed in Get cpu addr, rc=%d, cpu_addr=%pK",
  2917. rc, (void *)cpu_addr);
  2918. goto end;
  2919. }
  2920. CAM_DBG(CAM_UTIL, "Get cpu buf success req_id: %llu buf_size: %zu",
  2921. req_id, buf_size);
  2922. if ((buf_size < sizeof(uint32_t)) ||
  2923. ((size_t)cmd_desc->offset > (buf_size - sizeof(uint32_t)))) {
  2924. CAM_ERR(CAM_UTIL, "Invalid offset for cmd buf: %zu",
  2925. (size_t)cmd_desc->offset);
  2926. rc = -EINVAL;
  2927. goto end;
  2928. }
  2929. remain_len = buf_size - (size_t)cmd_desc->offset;
  2930. if ((remain_len < (size_t)cmd_desc->size) || (cmd_desc->size <
  2931. cmd_desc->length)) {
  2932. CAM_ERR(CAM_UTIL,
  2933. "Invalid params for cmd buf len: %zu size: %zu remain_len: %zu",
  2934. (size_t)cmd_desc->length, (size_t)cmd_desc->length,
  2935. remain_len);
  2936. rc = -EINVAL;
  2937. goto end;
  2938. }
  2939. cmd_buf_start = cpu_addr + (uintptr_t)cmd_desc->offset;
  2940. cmd_in_data_end = cmd_buf_start + (uintptr_t)cmd_desc->length;
  2941. cmd_buf_end = cmd_buf_start + (uintptr_t)cmd_desc->size;
  2942. if ((cmd_buf_end <= cmd_buf_start) ||
  2943. (cmd_in_data_end <= cmd_buf_start)) {
  2944. CAM_ERR(CAM_UTIL,
  2945. "Invalid length or size for cmd buf: [%zu] [%zu]",
  2946. (size_t)cmd_desc->length, (size_t)cmd_desc->size);
  2947. rc = -EINVAL;
  2948. goto end;
  2949. }
  2950. CAM_DBG(CAM_UTIL,
  2951. "Buffer params start [%pK] input_end [%pK] buf_end [%pK]",
  2952. cmd_buf_start, cmd_in_data_end, cmd_buf_end);
  2953. reg_input_info = (struct cam_reg_dump_input_info *) cmd_buf_start;
  2954. if ((reg_input_info->num_dump_sets > 1) && (sizeof(uint32_t) >
  2955. ((U32_MAX - sizeof(struct cam_reg_dump_input_info)) /
  2956. (reg_input_info->num_dump_sets - 1)))) {
  2957. CAM_ERR(CAM_UTIL,
  2958. "Integer Overflow req_id: [%llu] num_dump_sets: [%u]",
  2959. req_id, reg_input_info->num_dump_sets);
  2960. rc = -EOVERFLOW;
  2961. goto end;
  2962. }
  2963. if ((!reg_input_info->num_dump_sets) ||
  2964. ((cmd_in_data_end - cmd_buf_start) <= (uintptr_t)
  2965. (sizeof(struct cam_reg_dump_input_info) +
  2966. ((reg_input_info->num_dump_sets - 1) * sizeof(uint32_t))))) {
  2967. CAM_ERR(CAM_UTIL,
  2968. "Invalid number of dump sets, req_id: [%llu] num_dump_sets: [%u]",
  2969. req_id, reg_input_info->num_dump_sets);
  2970. rc = -EINVAL;
  2971. goto end;
  2972. }
  2973. CAM_DBG(CAM_UTIL,
  2974. "reg_input_info req_id: %llu ctx %pK num_dump_sets: %d",
  2975. req_id, ctx, reg_input_info->num_dump_sets);
  2976. for (i = 0; i < reg_input_info->num_dump_sets; i++) {
  2977. if ((cmd_in_data_end - cmd_buf_start) <= (uintptr_t)
  2978. reg_input_info->dump_set_offsets[i]) {
  2979. CAM_ERR(CAM_UTIL,
  2980. "Invalid dump set offset: [%pK], cmd_buf_start: [%pK] cmd_in_data_end: [%pK]",
  2981. (uintptr_t)reg_input_info->dump_set_offsets[i],
  2982. cmd_buf_start, cmd_in_data_end);
  2983. rc = -EINVAL;
  2984. goto end;
  2985. }
  2986. reg_dump_desc = (struct cam_reg_dump_desc *)
  2987. (cmd_buf_start +
  2988. (uintptr_t)reg_input_info->dump_set_offsets[i]);
  2989. if ((reg_dump_desc->num_read_range > 1) &&
  2990. (sizeof(struct cam_reg_read_info) > ((U32_MAX -
  2991. sizeof(struct cam_reg_dump_desc)) /
  2992. (reg_dump_desc->num_read_range - 1)))) {
  2993. CAM_ERR(CAM_UTIL,
  2994. "Integer Overflow req_id: [%llu] num_read_range: [%u]",
  2995. req_id, reg_dump_desc->num_read_range);
  2996. rc = -EOVERFLOW;
  2997. goto end;
  2998. }
  2999. if ((!reg_dump_desc->num_read_range) ||
  3000. ((cmd_in_data_end - (uintptr_t)reg_dump_desc) <=
  3001. (uintptr_t)(sizeof(struct cam_reg_dump_desc) +
  3002. ((reg_dump_desc->num_read_range - 1) *
  3003. sizeof(struct cam_reg_read_info))))) {
  3004. CAM_ERR(CAM_UTIL,
  3005. "Invalid number of read ranges, req_id: [%llu] num_read_range: [%d]",
  3006. req_id, reg_dump_desc->num_read_range);
  3007. rc = -EINVAL;
  3008. goto end;
  3009. }
  3010. if ((cmd_buf_end - cmd_buf_start) <= (uintptr_t)
  3011. (reg_dump_desc->dump_buffer_offset +
  3012. sizeof(struct cam_reg_dump_out_buffer))) {
  3013. CAM_ERR(CAM_UTIL,
  3014. "Invalid out buffer offset: [%pK], cmd_buf_start: [%pK] cmd_buf_end: [%pK]",
  3015. (uintptr_t)reg_dump_desc->dump_buffer_offset,
  3016. cmd_buf_start, cmd_buf_end);
  3017. rc = -EINVAL;
  3018. goto end;
  3019. }
  3020. reg_base_type = reg_dump_desc->reg_base_type;
  3021. if (reg_base_type == 0 || reg_base_type >
  3022. CAM_REG_DUMP_BASE_TYPE_SFE_RIGHT) {
  3023. CAM_ERR(CAM_UTIL,
  3024. "Invalid Reg dump base type: %d",
  3025. reg_base_type);
  3026. rc = -EINVAL;
  3027. goto end;
  3028. }
  3029. rc = reg_data_cb(reg_base_type, ctx, &soc_info, &reg_base_idx);
  3030. if (rc || !soc_info) {
  3031. CAM_ERR(CAM_UTIL,
  3032. "Reg space data callback failed rc: %d soc_info: [%pK]",
  3033. rc, soc_info);
  3034. rc = -EINVAL;
  3035. goto end;
  3036. }
  3037. if (reg_base_idx > soc_info->num_reg_map) {
  3038. CAM_ERR(CAM_UTIL,
  3039. "Invalid reg base idx: %d num reg map: %d",
  3040. reg_base_idx, soc_info->num_reg_map);
  3041. rc = -EINVAL;
  3042. goto end;
  3043. }
  3044. CAM_DBG(CAM_UTIL,
  3045. "Reg data callback success req_id: %llu base_type: %d base_idx: %d num_read_range: %d",
  3046. req_id, reg_base_type, reg_base_idx,
  3047. reg_dump_desc->num_read_range);
  3048. /* If the dump request is triggered by user space
  3049. * buffer will be different from the buffer which is received
  3050. * in init packet. In this case, dump the data to the
  3051. * user provided buffer and exit.
  3052. */
  3053. if (user_triggered_dump) {
  3054. rc = cam_soc_util_user_reg_dump(reg_dump_desc,
  3055. soc_dump_args, soc_info, reg_base_idx);
  3056. CAM_INFO(CAM_UTIL,
  3057. "%s reg_base_idx %d dumped offset %u",
  3058. soc_info->dev_name, reg_base_idx,
  3059. soc_dump_args->offset);
  3060. goto end;
  3061. }
  3062. /* Below code is executed when data is dumped to the
  3063. * out buffer received in init packet
  3064. */
  3065. dump_out_buf = (struct cam_reg_dump_out_buffer *)
  3066. (cmd_buf_start +
  3067. (uintptr_t)reg_dump_desc->dump_buffer_offset);
  3068. dump_out_buf->req_id = req_id;
  3069. dump_out_buf->bytes_written = 0;
  3070. for (j = 0; j < reg_dump_desc->num_read_range; j++) {
  3071. CAM_DBG(CAM_UTIL,
  3072. "Number of bytes written to cmd buffer: %u req_id: %llu",
  3073. dump_out_buf->bytes_written, req_id);
  3074. reg_read_info = &reg_dump_desc->read_range[j];
  3075. if (reg_read_info->type ==
  3076. CAM_REG_DUMP_READ_TYPE_CONT_RANGE) {
  3077. rc = cam_soc_util_dump_cont_reg_range(soc_info,
  3078. &reg_read_info->reg_read, reg_base_idx,
  3079. dump_out_buf, cmd_buf_end);
  3080. } else if (reg_read_info->type ==
  3081. CAM_REG_DUMP_READ_TYPE_DMI) {
  3082. rc = cam_soc_util_dump_dmi_reg_range(soc_info,
  3083. &reg_read_info->dmi_read, reg_base_idx,
  3084. dump_out_buf, cmd_buf_end);
  3085. } else {
  3086. CAM_ERR(CAM_UTIL,
  3087. "Invalid Reg dump read type: %d",
  3088. reg_read_info->type);
  3089. rc = -EINVAL;
  3090. goto end;
  3091. }
  3092. if (rc) {
  3093. CAM_ERR(CAM_UTIL,
  3094. "Reg range read failed rc: %d reg_base_idx: %d dump_out_buf: %pK",
  3095. rc, reg_base_idx, dump_out_buf);
  3096. goto end;
  3097. }
  3098. }
  3099. }
  3100. end:
  3101. return rc;
  3102. }
  3103. /**
  3104. * cam_soc_util_print_clk_freq()
  3105. *
  3106. * @brief: This function gets the clk rates for each clk from clk
  3107. * driver and prints in log
  3108. *
  3109. * @soc_info: Device soc struct to be populated
  3110. *
  3111. * @return: success or failure
  3112. */
  3113. int cam_soc_util_print_clk_freq(struct cam_hw_soc_info *soc_info)
  3114. {
  3115. int i;
  3116. unsigned long clk_rate = 0;
  3117. if (!soc_info) {
  3118. CAM_ERR(CAM_UTIL, "Invalid soc info");
  3119. return -EINVAL;
  3120. }
  3121. if ((soc_info->num_clk == 0) ||
  3122. (soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
  3123. CAM_ERR(CAM_UTIL, "[%s] Invalid number of clock %d",
  3124. soc_info->dev_name, soc_info->num_clk);
  3125. return -EINVAL;
  3126. }
  3127. for (i = 0; i < soc_info->num_clk; i++) {
  3128. clk_rate = clk_get_rate(soc_info->clk[i]);
  3129. CAM_INFO(CAM_UTIL,
  3130. "[%s] idx = %d clk name = %s clk_rate=%lld",
  3131. soc_info->dev_name, i, soc_info->clk_name[i],
  3132. clk_rate);
  3133. }
  3134. return 0;
  3135. }
  3136. int cam_soc_util_regulators_enabled(struct cam_hw_soc_info *soc_info)
  3137. {
  3138. int j = 0, rc = 0;
  3139. int enabled_cnt = 0;
  3140. for (j = 0; j < soc_info->num_rgltr; j++) {
  3141. if (soc_info->rgltr[j]) {
  3142. rc = regulator_is_enabled(soc_info->rgltr[j]);
  3143. if (rc < 0) {
  3144. CAM_ERR(CAM_UTIL, "%s regulator_is_enabled failed",
  3145. soc_info->rgltr_name[j]);
  3146. } else if (rc > 0) {
  3147. CAM_DBG(CAM_UTIL, "%s regulator enabled",
  3148. soc_info->rgltr_name[j]);
  3149. enabled_cnt++;
  3150. } else {
  3151. CAM_DBG(CAM_UTIL, "%s regulator is disabled",
  3152. soc_info->rgltr_name[j]);
  3153. }
  3154. }
  3155. }
  3156. return enabled_cnt;
  3157. }