dp_parser.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2012-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/of_gpio.h>
  6. #include <linux/of_platform.h>
  7. #include "dp_parser.h"
  8. #include "dp_debug.h"
  9. static void dp_parser_unmap_io_resources(struct dp_parser *parser)
  10. {
  11. int i = 0;
  12. struct dp_io *io = &parser->io;
  13. for (i = 0; i < io->len; i++)
  14. msm_dss_iounmap(&io->data[i].io);
  15. }
  16. static int dp_parser_reg(struct dp_parser *parser)
  17. {
  18. int rc = 0, i = 0;
  19. u32 reg_count;
  20. struct platform_device *pdev = parser->pdev;
  21. struct dp_io *io = &parser->io;
  22. struct device *dev = &pdev->dev;
  23. reg_count = of_property_count_strings(dev->of_node, "reg-names");
  24. if (reg_count <= 0) {
  25. DP_ERR("no reg defined\n");
  26. return -EINVAL;
  27. }
  28. io->len = reg_count;
  29. io->data = devm_kzalloc(dev, sizeof(struct dp_io_data) * reg_count,
  30. GFP_KERNEL);
  31. if (!io->data)
  32. return -ENOMEM;
  33. for (i = 0; i < reg_count; i++) {
  34. of_property_read_string_index(dev->of_node,
  35. "reg-names", i, &io->data[i].name);
  36. rc = msm_dss_ioremap_byname(pdev, &io->data[i].io,
  37. io->data[i].name);
  38. if (rc) {
  39. DP_ERR("unable to remap %s resources\n",
  40. io->data[i].name);
  41. goto err;
  42. }
  43. }
  44. return 0;
  45. err:
  46. dp_parser_unmap_io_resources(parser);
  47. return rc;
  48. }
  49. static const char *dp_get_phy_aux_config_property(u32 cfg_type)
  50. {
  51. switch (cfg_type) {
  52. case PHY_AUX_CFG0:
  53. return "qcom,aux-cfg0-settings";
  54. case PHY_AUX_CFG1:
  55. return "qcom,aux-cfg1-settings";
  56. case PHY_AUX_CFG2:
  57. return "qcom,aux-cfg2-settings";
  58. case PHY_AUX_CFG3:
  59. return "qcom,aux-cfg3-settings";
  60. case PHY_AUX_CFG4:
  61. return "qcom,aux-cfg4-settings";
  62. case PHY_AUX_CFG5:
  63. return "qcom,aux-cfg5-settings";
  64. case PHY_AUX_CFG6:
  65. return "qcom,aux-cfg6-settings";
  66. case PHY_AUX_CFG7:
  67. return "qcom,aux-cfg7-settings";
  68. case PHY_AUX_CFG8:
  69. return "qcom,aux-cfg8-settings";
  70. case PHY_AUX_CFG9:
  71. return "qcom,aux-cfg9-settings";
  72. default:
  73. return "unknown";
  74. }
  75. }
  76. static void dp_parser_phy_aux_cfg_reset(struct dp_parser *parser)
  77. {
  78. int i = 0;
  79. for (i = 0; i < PHY_AUX_CFG_MAX; i++)
  80. parser->aux_cfg[i] = (const struct dp_aux_cfg){ 0 };
  81. }
  82. static int dp_parser_aux(struct dp_parser *parser)
  83. {
  84. struct device_node *of_node = parser->pdev->dev.of_node;
  85. int len = 0, i = 0, j = 0, config_count = 0;
  86. const char *data;
  87. int const minimum_config_count = 1;
  88. for (i = 0; i < PHY_AUX_CFG_MAX; i++) {
  89. const char *property = dp_get_phy_aux_config_property(i);
  90. data = of_get_property(of_node, property, &len);
  91. if (!data) {
  92. DP_ERR("Unable to read %s\n", property);
  93. goto error;
  94. }
  95. config_count = len - 1;
  96. if ((config_count < minimum_config_count) ||
  97. (config_count > DP_AUX_CFG_MAX_VALUE_CNT)) {
  98. DP_ERR("Invalid config count (%d) configs for %s\n",
  99. config_count, property);
  100. goto error;
  101. }
  102. parser->aux_cfg[i].offset = data[0];
  103. parser->aux_cfg[i].cfg_cnt = config_count;
  104. DP_DEBUG("%s offset=0x%x, cfg_cnt=%d\n",
  105. property,
  106. parser->aux_cfg[i].offset,
  107. parser->aux_cfg[i].cfg_cnt);
  108. for (j = 1; j < len; j++) {
  109. parser->aux_cfg[i].lut[j - 1] = data[j];
  110. DP_DEBUG("%s lut[%d]=0x%x\n",
  111. property,
  112. i,
  113. parser->aux_cfg[i].lut[j - 1]);
  114. }
  115. }
  116. return 0;
  117. error:
  118. dp_parser_phy_aux_cfg_reset(parser);
  119. return -EINVAL;
  120. }
  121. static int dp_parser_misc(struct dp_parser *parser)
  122. {
  123. int rc = 0, len = 0, i = 0;
  124. const char *data = NULL;
  125. struct device_node *of_node = parser->pdev->dev.of_node;
  126. data = of_get_property(of_node, "qcom,logical2physical-lane-map", &len);
  127. if (data && (len == DP_MAX_PHY_LN)) {
  128. for (i = 0; i < len; i++)
  129. parser->l_map[i] = data[i];
  130. }
  131. data = of_get_property(of_node, "qcom,pn-swap-lane-map", &len);
  132. if (data && (len == DP_MAX_PHY_LN)) {
  133. for (i = 0; i < len; i++)
  134. parser->l_pnswap |= (data[i] & 0x01) << i;
  135. }
  136. rc = of_property_read_u32(of_node,
  137. "qcom,max-pclk-frequency-khz", &parser->max_pclk_khz);
  138. if (rc)
  139. parser->max_pclk_khz = DP_MAX_PIXEL_CLK_KHZ;
  140. rc = of_property_read_u32(of_node,
  141. "qcom,max-lclk-frequency-khz", &parser->max_lclk_khz);
  142. if (rc)
  143. parser->max_lclk_khz = DP_MAX_LINK_CLK_KHZ;
  144. return 0;
  145. }
  146. static int dp_parser_msm_hdcp_dev(struct dp_parser *parser)
  147. {
  148. struct device_node *node;
  149. struct platform_device *pdev;
  150. node = of_find_compatible_node(NULL, NULL, "qcom,msm-hdcp");
  151. if (!node) {
  152. // This is a non-fatal error, module initialization can proceed
  153. DP_WARN("couldn't find msm-hdcp node\n");
  154. return 0;
  155. }
  156. pdev = of_find_device_by_node(node);
  157. if (!pdev) {
  158. // This is a non-fatal error, module initialization can proceed
  159. DP_WARN("couldn't find msm-hdcp pdev\n");
  160. return 0;
  161. }
  162. parser->msm_hdcp_dev = &pdev->dev;
  163. return 0;
  164. }
  165. static int dp_parser_pinctrl(struct dp_parser *parser)
  166. {
  167. int rc = 0;
  168. struct dp_pinctrl *pinctrl = &parser->pinctrl;
  169. pinctrl->pin = devm_pinctrl_get(&parser->pdev->dev);
  170. if (IS_ERR_OR_NULL(pinctrl->pin)) {
  171. DP_DEBUG("failed to get pinctrl, rc=%d\n", rc);
  172. goto error;
  173. }
  174. if (parser->no_aux_switch && parser->lphw_hpd) {
  175. pinctrl->state_hpd_tlmm = pinctrl->state_hpd_ctrl = NULL;
  176. pinctrl->state_hpd_tlmm = pinctrl_lookup_state(pinctrl->pin,
  177. "mdss_dp_hpd_tlmm");
  178. if (!IS_ERR_OR_NULL(pinctrl->state_hpd_tlmm)) {
  179. pinctrl->state_hpd_ctrl = pinctrl_lookup_state(
  180. pinctrl->pin, "mdss_dp_hpd_ctrl");
  181. }
  182. if (!pinctrl->state_hpd_tlmm || !pinctrl->state_hpd_ctrl) {
  183. pinctrl->state_hpd_tlmm = NULL;
  184. pinctrl->state_hpd_ctrl = NULL;
  185. DP_DEBUG("tlmm or ctrl pinctrl state does not exist\n");
  186. }
  187. }
  188. pinctrl->state_active = pinctrl_lookup_state(pinctrl->pin,
  189. "mdss_dp_active");
  190. if (IS_ERR_OR_NULL(pinctrl->state_active)) {
  191. rc = PTR_ERR(pinctrl->state_active);
  192. DP_ERR("failed to get pinctrl active state, rc=%d\n", rc);
  193. goto error;
  194. }
  195. pinctrl->state_suspend = pinctrl_lookup_state(pinctrl->pin,
  196. "mdss_dp_sleep");
  197. if (IS_ERR_OR_NULL(pinctrl->state_suspend)) {
  198. rc = PTR_ERR(pinctrl->state_suspend);
  199. DP_ERR("failed to get pinctrl suspend state, rc=%d\n", rc);
  200. goto error;
  201. }
  202. error:
  203. return rc;
  204. }
  205. static int dp_parser_gpio(struct dp_parser *parser)
  206. {
  207. int i = 0;
  208. struct device *dev = &parser->pdev->dev;
  209. struct device_node *of_node = dev->of_node;
  210. struct dss_module_power *mp = &parser->mp[DP_CORE_PM];
  211. static const char * const dp_gpios[] = {
  212. "qcom,aux-en-gpio",
  213. "qcom,aux-sel-gpio",
  214. "qcom,usbplug-cc-gpio",
  215. };
  216. if (of_find_property(of_node, "qcom,dp-hpd-gpio", NULL)) {
  217. parser->no_aux_switch = true;
  218. parser->lphw_hpd = of_find_property(of_node,
  219. "qcom,dp-low-power-hw-hpd", NULL);
  220. return 0;
  221. }
  222. if (of_find_property(of_node, "qcom,dp-gpio-aux-switch", NULL))
  223. parser->gpio_aux_switch = true;
  224. mp->gpio_config = devm_kzalloc(dev,
  225. sizeof(struct dss_gpio) * ARRAY_SIZE(dp_gpios), GFP_KERNEL);
  226. if (!mp->gpio_config)
  227. return -ENOMEM;
  228. mp->num_gpio = ARRAY_SIZE(dp_gpios);
  229. for (i = 0; i < ARRAY_SIZE(dp_gpios); i++) {
  230. mp->gpio_config[i].gpio = of_get_named_gpio(of_node,
  231. dp_gpios[i], 0);
  232. if (!gpio_is_valid(mp->gpio_config[i].gpio)) {
  233. DP_DEBUG("%s gpio not specified\n", dp_gpios[i]);
  234. /* In case any gpio was not specified, we think gpio
  235. * aux switch also was not specified.
  236. */
  237. parser->gpio_aux_switch = false;
  238. continue;
  239. }
  240. strlcpy(mp->gpio_config[i].gpio_name, dp_gpios[i],
  241. sizeof(mp->gpio_config[i].gpio_name));
  242. mp->gpio_config[i].value = 0;
  243. }
  244. return 0;
  245. }
  246. static const char *dp_parser_supply_node_name(enum dp_pm_type module)
  247. {
  248. switch (module) {
  249. case DP_CORE_PM: return "qcom,core-supply-entries";
  250. case DP_CTRL_PM: return "qcom,ctrl-supply-entries";
  251. case DP_PHY_PM: return "qcom,phy-supply-entries";
  252. default: return "???";
  253. }
  254. }
  255. static int dp_parser_get_vreg(struct dp_parser *parser,
  256. enum dp_pm_type module)
  257. {
  258. int i = 0, rc = 0;
  259. u32 tmp = 0;
  260. const char *pm_supply_name = NULL;
  261. struct device_node *supply_node = NULL;
  262. struct device_node *of_node = parser->pdev->dev.of_node;
  263. struct device_node *supply_root_node = NULL;
  264. struct dss_module_power *mp = &parser->mp[module];
  265. mp->num_vreg = 0;
  266. pm_supply_name = dp_parser_supply_node_name(module);
  267. supply_root_node = of_get_child_by_name(of_node, pm_supply_name);
  268. if (!supply_root_node) {
  269. DP_WARN("no supply entry present: %s\n", pm_supply_name);
  270. goto novreg;
  271. }
  272. mp->num_vreg = of_get_available_child_count(supply_root_node);
  273. if (mp->num_vreg == 0) {
  274. DP_DEBUG("no vreg\n");
  275. goto novreg;
  276. } else {
  277. DP_DEBUG("vreg found. count=%d\n", mp->num_vreg);
  278. }
  279. mp->vreg_config = devm_kzalloc(&parser->pdev->dev,
  280. sizeof(struct dss_vreg) * mp->num_vreg, GFP_KERNEL);
  281. if (!mp->vreg_config) {
  282. rc = -ENOMEM;
  283. goto error;
  284. }
  285. for_each_child_of_node(supply_root_node, supply_node) {
  286. const char *st = NULL;
  287. /* vreg-name */
  288. rc = of_property_read_string(supply_node,
  289. "qcom,supply-name", &st);
  290. if (rc) {
  291. DP_ERR("error reading name. rc=%d\n",
  292. rc);
  293. goto error;
  294. }
  295. snprintf(mp->vreg_config[i].vreg_name,
  296. ARRAY_SIZE((mp->vreg_config[i].vreg_name)), "%s", st);
  297. /* vreg-min-voltage */
  298. rc = of_property_read_u32(supply_node,
  299. "qcom,supply-min-voltage", &tmp);
  300. if (rc) {
  301. DP_ERR("error reading min volt. rc=%d\n",
  302. rc);
  303. goto error;
  304. }
  305. mp->vreg_config[i].min_voltage = tmp;
  306. /* vreg-max-voltage */
  307. rc = of_property_read_u32(supply_node,
  308. "qcom,supply-max-voltage", &tmp);
  309. if (rc) {
  310. DP_ERR("error reading max volt. rc=%d\n",
  311. rc);
  312. goto error;
  313. }
  314. mp->vreg_config[i].max_voltage = tmp;
  315. /* enable-load */
  316. rc = of_property_read_u32(supply_node,
  317. "qcom,supply-enable-load", &tmp);
  318. if (rc) {
  319. DP_ERR("error reading enable load. rc=%d\n",
  320. rc);
  321. goto error;
  322. }
  323. mp->vreg_config[i].enable_load = tmp;
  324. /* disable-load */
  325. rc = of_property_read_u32(supply_node,
  326. "qcom,supply-disable-load", &tmp);
  327. if (rc) {
  328. DP_ERR("error reading disable load. rc=%d\n",
  329. rc);
  330. goto error;
  331. }
  332. mp->vreg_config[i].disable_load = tmp;
  333. DP_DEBUG("%s min=%d, max=%d, enable=%d, disable=%d\n",
  334. mp->vreg_config[i].vreg_name,
  335. mp->vreg_config[i].min_voltage,
  336. mp->vreg_config[i].max_voltage,
  337. mp->vreg_config[i].enable_load,
  338. mp->vreg_config[i].disable_load
  339. );
  340. ++i;
  341. }
  342. return rc;
  343. error:
  344. if (mp->vreg_config) {
  345. devm_kfree(&parser->pdev->dev, mp->vreg_config);
  346. mp->vreg_config = NULL;
  347. }
  348. novreg:
  349. mp->num_vreg = 0;
  350. return rc;
  351. }
  352. static void dp_parser_put_vreg_data(struct device *dev,
  353. struct dss_module_power *mp)
  354. {
  355. if (!mp) {
  356. DEV_ERR("invalid input\n");
  357. return;
  358. }
  359. if (mp->vreg_config) {
  360. devm_kfree(dev, mp->vreg_config);
  361. mp->vreg_config = NULL;
  362. }
  363. mp->num_vreg = 0;
  364. }
  365. static int dp_parser_regulator(struct dp_parser *parser)
  366. {
  367. int i, rc = 0;
  368. struct platform_device *pdev = parser->pdev;
  369. /* Parse the regulator information */
  370. for (i = DP_CORE_PM; i < DP_MAX_PM; i++) {
  371. rc = dp_parser_get_vreg(parser, i);
  372. if (rc) {
  373. DP_ERR("get_dt_vreg_data failed for %s. rc=%d\n",
  374. dp_parser_pm_name(i), rc);
  375. i--;
  376. for (; i >= DP_CORE_PM; i--)
  377. dp_parser_put_vreg_data(&pdev->dev,
  378. &parser->mp[i]);
  379. break;
  380. }
  381. }
  382. return rc;
  383. }
  384. static bool dp_parser_check_prefix(const char *clk_prefix, const char *clk_name)
  385. {
  386. return !!strnstr(clk_name, clk_prefix, strlen(clk_name));
  387. }
  388. static void dp_parser_put_clk_data(struct device *dev,
  389. struct dss_module_power *mp)
  390. {
  391. if (!mp) {
  392. DEV_ERR("%s: invalid input\n", __func__);
  393. return;
  394. }
  395. if (mp->clk_config) {
  396. devm_kfree(dev, mp->clk_config);
  397. mp->clk_config = NULL;
  398. }
  399. mp->num_clk = 0;
  400. }
  401. static void dp_parser_put_gpio_data(struct device *dev,
  402. struct dss_module_power *mp)
  403. {
  404. if (!mp) {
  405. DEV_ERR("%s: invalid input\n", __func__);
  406. return;
  407. }
  408. if (mp->gpio_config) {
  409. devm_kfree(dev, mp->gpio_config);
  410. mp->gpio_config = NULL;
  411. }
  412. mp->num_gpio = 0;
  413. }
  414. static int dp_parser_init_clk_data(struct dp_parser *parser)
  415. {
  416. int num_clk = 0, i = 0, rc = 0;
  417. int core_clk_count = 0, link_clk_count = 0;
  418. int strm0_clk_count = 0, strm1_clk_count = 0;
  419. const char *core_clk = "core";
  420. const char *strm0_clk = "strm0";
  421. const char *strm1_clk = "strm1";
  422. const char *link_clk = "link";
  423. const char *clk_name;
  424. struct device *dev = &parser->pdev->dev;
  425. struct dss_module_power *core_power = &parser->mp[DP_CORE_PM];
  426. struct dss_module_power *strm0_power = &parser->mp[DP_STREAM0_PM];
  427. struct dss_module_power *strm1_power = &parser->mp[DP_STREAM1_PM];
  428. struct dss_module_power *link_power = &parser->mp[DP_LINK_PM];
  429. num_clk = of_property_count_strings(dev->of_node, "clock-names");
  430. if (num_clk <= 0) {
  431. DP_ERR("no clocks are defined\n");
  432. rc = -EINVAL;
  433. goto exit;
  434. }
  435. for (i = 0; i < num_clk; i++) {
  436. of_property_read_string_index(dev->of_node,
  437. "clock-names", i, &clk_name);
  438. if (dp_parser_check_prefix(core_clk, clk_name))
  439. core_clk_count++;
  440. if (dp_parser_check_prefix(strm0_clk, clk_name))
  441. strm0_clk_count++;
  442. if (dp_parser_check_prefix(strm1_clk, clk_name))
  443. strm1_clk_count++;
  444. if (dp_parser_check_prefix(link_clk, clk_name))
  445. link_clk_count++;
  446. }
  447. /* Initialize the CORE power module */
  448. if (core_clk_count <= 0) {
  449. DP_ERR("no core clocks are defined\n");
  450. rc = -EINVAL;
  451. goto exit;
  452. }
  453. core_power->num_clk = core_clk_count;
  454. core_power->clk_config = devm_kzalloc(dev,
  455. sizeof(struct dss_clk) * core_power->num_clk,
  456. GFP_KERNEL);
  457. if (!core_power->clk_config) {
  458. rc = -EINVAL;
  459. goto exit;
  460. }
  461. /* Initialize the STREAM0 power module */
  462. if (strm0_clk_count <= 0) {
  463. DP_DEBUG("no strm0 clocks are defined\n");
  464. } else {
  465. strm0_power->num_clk = strm0_clk_count;
  466. strm0_power->clk_config = devm_kzalloc(dev,
  467. sizeof(struct dss_clk) * strm0_power->num_clk,
  468. GFP_KERNEL);
  469. if (!strm0_power->clk_config) {
  470. strm0_power->num_clk = 0;
  471. rc = -EINVAL;
  472. goto strm0_clock_error;
  473. }
  474. }
  475. /* Initialize the STREAM1 power module */
  476. if (strm1_clk_count <= 0) {
  477. DP_DEBUG("no strm1 clocks are defined\n");
  478. } else {
  479. strm1_power->num_clk = strm1_clk_count;
  480. strm1_power->clk_config = devm_kzalloc(dev,
  481. sizeof(struct dss_clk) * strm1_power->num_clk,
  482. GFP_KERNEL);
  483. if (!strm1_power->clk_config) {
  484. strm1_power->num_clk = 0;
  485. rc = -EINVAL;
  486. goto strm1_clock_error;
  487. }
  488. }
  489. /* Initialize the link power module */
  490. if (link_clk_count <= 0) {
  491. DP_ERR("no link clocks are defined\n");
  492. rc = -EINVAL;
  493. goto link_clock_error;
  494. }
  495. link_power->num_clk = link_clk_count;
  496. link_power->clk_config = devm_kzalloc(dev,
  497. sizeof(struct dss_clk) * link_power->num_clk,
  498. GFP_KERNEL);
  499. if (!link_power->clk_config) {
  500. link_power->num_clk = 0;
  501. rc = -EINVAL;
  502. goto link_clock_error;
  503. }
  504. return rc;
  505. link_clock_error:
  506. dp_parser_put_clk_data(dev, strm1_power);
  507. strm1_clock_error:
  508. dp_parser_put_clk_data(dev, strm0_power);
  509. strm0_clock_error:
  510. dp_parser_put_clk_data(dev, core_power);
  511. exit:
  512. return rc;
  513. }
  514. static int dp_parser_clock(struct dp_parser *parser)
  515. {
  516. int rc = 0, i = 0;
  517. int num_clk = 0;
  518. int core_clk_index = 0, link_clk_index = 0;
  519. int core_clk_count = 0, link_clk_count = 0;
  520. int strm0_clk_index = 0, strm1_clk_index = 0;
  521. int strm0_clk_count = 0, strm1_clk_count = 0;
  522. const char *clk_name;
  523. const char *core_clk = "core";
  524. const char *strm0_clk = "strm0";
  525. const char *strm1_clk = "strm1";
  526. const char *link_clk = "link";
  527. struct device *dev = &parser->pdev->dev;
  528. struct dss_module_power *core_power;
  529. struct dss_module_power *strm0_power;
  530. struct dss_module_power *strm1_power;
  531. struct dss_module_power *link_power;
  532. core_power = &parser->mp[DP_CORE_PM];
  533. strm0_power = &parser->mp[DP_STREAM0_PM];
  534. strm1_power = &parser->mp[DP_STREAM1_PM];
  535. link_power = &parser->mp[DP_LINK_PM];
  536. rc = dp_parser_init_clk_data(parser);
  537. if (rc) {
  538. DP_ERR("failed to initialize power data\n");
  539. rc = -EINVAL;
  540. goto exit;
  541. }
  542. core_clk_count = core_power->num_clk;
  543. link_clk_count = link_power->num_clk;
  544. strm0_clk_count = strm0_power->num_clk;
  545. strm1_clk_count = strm1_power->num_clk;
  546. num_clk = of_property_count_strings(dev->of_node, "clock-names");
  547. for (i = 0; i < num_clk; i++) {
  548. of_property_read_string_index(dev->of_node, "clock-names",
  549. i, &clk_name);
  550. if (dp_parser_check_prefix(core_clk, clk_name) &&
  551. core_clk_index < core_clk_count) {
  552. struct dss_clk *clk =
  553. &core_power->clk_config[core_clk_index];
  554. strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
  555. clk->type = DSS_CLK_AHB;
  556. core_clk_index++;
  557. } else if (dp_parser_check_prefix(link_clk, clk_name) &&
  558. link_clk_index < link_clk_count) {
  559. struct dss_clk *clk =
  560. &link_power->clk_config[link_clk_index];
  561. strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
  562. link_clk_index++;
  563. if (!strcmp(clk_name, "link_clk"))
  564. clk->type = DSS_CLK_PCLK;
  565. else
  566. clk->type = DSS_CLK_AHB;
  567. } else if (dp_parser_check_prefix(strm0_clk, clk_name) &&
  568. strm0_clk_index < strm0_clk_count) {
  569. struct dss_clk *clk =
  570. &strm0_power->clk_config[strm0_clk_index];
  571. strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
  572. strm0_clk_index++;
  573. clk->type = DSS_CLK_PCLK;
  574. } else if (dp_parser_check_prefix(strm1_clk, clk_name) &&
  575. strm1_clk_index < strm1_clk_count) {
  576. struct dss_clk *clk =
  577. &strm1_power->clk_config[strm1_clk_index];
  578. strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
  579. strm1_clk_index++;
  580. clk->type = DSS_CLK_PCLK;
  581. }
  582. }
  583. DP_DEBUG("clock parsing successful\n");
  584. exit:
  585. return rc;
  586. }
  587. static int dp_parser_catalog(struct dp_parser *parser)
  588. {
  589. int rc;
  590. u32 version;
  591. struct device *dev = &parser->pdev->dev;
  592. rc = of_property_read_u32(dev->of_node, "qcom,phy-version", &version);
  593. if (!rc)
  594. parser->hw_cfg.phy_version = version;
  595. return 0;
  596. }
  597. static int dp_parser_mst(struct dp_parser *parser)
  598. {
  599. struct device *dev = &parser->pdev->dev;
  600. int i;
  601. parser->has_mst = of_property_read_bool(dev->of_node,
  602. "qcom,mst-enable");
  603. parser->has_mst_sideband = parser->has_mst;
  604. DP_DEBUG("mst parsing successful. mst:%d\n", parser->has_mst);
  605. for (i = 0; i < MAX_DP_MST_STREAMS; i++) {
  606. of_property_read_u32_index(dev->of_node,
  607. "qcom,mst-fixed-topology-ports", i,
  608. &parser->mst_fixed_port[i]);
  609. }
  610. return 0;
  611. }
  612. static void dp_parser_dsc(struct dp_parser *parser)
  613. {
  614. int rc;
  615. struct device *dev = &parser->pdev->dev;
  616. parser->dsc_feature_enable = of_property_read_bool(dev->of_node,
  617. "qcom,dsc-feature-enable");
  618. rc = of_property_read_u32(dev->of_node,
  619. "qcom,max-dp-dsc-blks", &parser->max_dp_dsc_blks);
  620. if (rc || !parser->max_dp_dsc_blks)
  621. parser->dsc_feature_enable = false;
  622. rc = of_property_read_u32(dev->of_node,
  623. "qcom,max-dp-dsc-input-width-pixs",
  624. &parser->max_dp_dsc_input_width_pixs);
  625. if (rc || !parser->max_dp_dsc_input_width_pixs)
  626. parser->dsc_feature_enable = false;
  627. DP_DEBUG("dsc parsing successful. dsc:%d, blks:%d, width:%d\n",
  628. parser->dsc_feature_enable,
  629. parser->max_dp_dsc_blks,
  630. parser->max_dp_dsc_input_width_pixs);
  631. }
  632. static void dp_parser_fec(struct dp_parser *parser)
  633. {
  634. struct device *dev = &parser->pdev->dev;
  635. parser->fec_feature_enable = of_property_read_bool(dev->of_node,
  636. "qcom,fec-feature-enable");
  637. DP_DEBUG("fec parsing successful. fec:%d\n",
  638. parser->fec_feature_enable);
  639. }
  640. static void dp_parser_widebus(struct dp_parser *parser)
  641. {
  642. struct device *dev = &parser->pdev->dev;
  643. parser->has_widebus = of_property_read_bool(dev->of_node,
  644. "qcom,widebus-enable");
  645. DP_DEBUG("widebus parsing successful. widebus:%d\n",
  646. parser->has_widebus);
  647. }
  648. static int dp_parser_parse(struct dp_parser *parser)
  649. {
  650. int rc = 0;
  651. if (!parser) {
  652. DP_ERR("invalid input\n");
  653. rc = -EINVAL;
  654. goto err;
  655. }
  656. rc = dp_parser_reg(parser);
  657. if (rc)
  658. goto err;
  659. rc = dp_parser_aux(parser);
  660. if (rc)
  661. goto err;
  662. rc = dp_parser_misc(parser);
  663. if (rc)
  664. goto err;
  665. rc = dp_parser_clock(parser);
  666. if (rc)
  667. goto err;
  668. rc = dp_parser_regulator(parser);
  669. if (rc)
  670. goto err;
  671. rc = dp_parser_gpio(parser);
  672. if (rc)
  673. goto err;
  674. rc = dp_parser_catalog(parser);
  675. if (rc)
  676. goto err;
  677. rc = dp_parser_pinctrl(parser);
  678. if (rc)
  679. goto err;
  680. rc = dp_parser_msm_hdcp_dev(parser);
  681. if (rc)
  682. goto err;
  683. rc = dp_parser_mst(parser);
  684. if (rc)
  685. goto err;
  686. dp_parser_dsc(parser);
  687. dp_parser_fec(parser);
  688. dp_parser_widebus(parser);
  689. err:
  690. return rc;
  691. }
  692. static struct dp_io_data *dp_parser_get_io(struct dp_parser *dp_parser,
  693. char *name)
  694. {
  695. int i = 0;
  696. struct dp_io *io;
  697. if (!dp_parser) {
  698. DP_ERR("invalid input\n");
  699. goto err;
  700. }
  701. io = &dp_parser->io;
  702. for (i = 0; i < io->len; i++) {
  703. struct dp_io_data *data = &io->data[i];
  704. if (!strcmp(data->name, name))
  705. return data;
  706. }
  707. err:
  708. return NULL;
  709. }
  710. static void dp_parser_get_io_buf(struct dp_parser *dp_parser, char *name)
  711. {
  712. int i = 0;
  713. struct dp_io *io;
  714. if (!dp_parser) {
  715. DP_ERR("invalid input\n");
  716. return;
  717. }
  718. io = &dp_parser->io;
  719. for (i = 0; i < io->len; i++) {
  720. struct dp_io_data *data = &io->data[i];
  721. if (!strcmp(data->name, name)) {
  722. if (!data->buf)
  723. data->buf = devm_kzalloc(&dp_parser->pdev->dev,
  724. data->io.len, GFP_KERNEL);
  725. }
  726. }
  727. }
  728. static void dp_parser_clear_io_buf(struct dp_parser *dp_parser)
  729. {
  730. int i = 0;
  731. struct dp_io *io;
  732. if (!dp_parser) {
  733. DP_ERR("invalid input\n");
  734. return;
  735. }
  736. io = &dp_parser->io;
  737. for (i = 0; i < io->len; i++) {
  738. struct dp_io_data *data = &io->data[i];
  739. if (data->buf)
  740. devm_kfree(&dp_parser->pdev->dev, data->buf);
  741. data->buf = NULL;
  742. }
  743. }
  744. struct dp_parser *dp_parser_get(struct platform_device *pdev)
  745. {
  746. struct dp_parser *parser;
  747. parser = devm_kzalloc(&pdev->dev, sizeof(*parser), GFP_KERNEL);
  748. if (!parser)
  749. return ERR_PTR(-ENOMEM);
  750. parser->parse = dp_parser_parse;
  751. parser->get_io = dp_parser_get_io;
  752. parser->get_io_buf = dp_parser_get_io_buf;
  753. parser->clear_io_buf = dp_parser_clear_io_buf;
  754. parser->pdev = pdev;
  755. return parser;
  756. }
  757. void dp_parser_put(struct dp_parser *parser)
  758. {
  759. int i = 0;
  760. struct dss_module_power *power = NULL;
  761. if (!parser) {
  762. DP_ERR("invalid parser module\n");
  763. return;
  764. }
  765. power = parser->mp;
  766. for (i = 0; i < DP_MAX_PM; i++) {
  767. dp_parser_put_clk_data(&parser->pdev->dev, &power[i]);
  768. dp_parser_put_vreg_data(&parser->pdev->dev, &power[i]);
  769. dp_parser_put_gpio_data(&parser->pdev->dev, &power[i]);
  770. }
  771. dp_parser_clear_io_buf(parser);
  772. devm_kfree(&parser->pdev->dev, parser->io.data);
  773. devm_kfree(&parser->pdev->dev, parser);
  774. }