cam_soc_util.h 31 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #ifndef _CAM_SOC_UTIL_H_
  7. #define _CAM_SOC_UTIL_H_
  8. #include <linux/version.h>
  9. #include <linux/types.h>
  10. #include <linux/slab.h>
  11. #include <linux/clk.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/delay.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/i2c.h>
  17. #include <linux/regulator/consumer.h>
  18. #include <linux/debugfs.h>
  19. #include <linux/of_fdt.h>
  20. #include "cam_io_util.h"
  21. #include <media/cam_defs.h>
  22. #if IS_REACHABLE(CONFIG_MSM_MMRM)
  23. #include <linux/soc/qcom/msm_mmrm.h>
  24. #endif
  25. #define NO_SET_RATE -1
  26. #define INIT_RATE -2
  27. /* maximum number of device block */
  28. #define CAM_SOC_MAX_BLOCK 8
  29. /* maximum number of device base */
  30. #define CAM_SOC_MAX_BASE CAM_SOC_MAX_BLOCK
  31. /* maximum number of device regulator */
  32. #define CAM_SOC_MAX_REGULATOR 10
  33. /* maximum number of device clock */
  34. #define CAM_SOC_MAX_CLK 32
  35. /* maximum number of optional device clock */
  36. #define CAM_SOC_MAX_OPT_CLK 7
  37. /* maximum number of pinctrl mapping */
  38. #define CAM_SOC_MAX_PINCTRL_MAP 2
  39. /* DDR device types */
  40. #define DDR_TYPE_LPDDR4 6
  41. #define DDR_TYPE_LPDDR4X 7
  42. #define DDR_TYPE_LPDDR5 8
  43. #define DDR_TYPE_LPDDR5X 9
  44. /* Maximum length of tag while dumping */
  45. #define CAM_SOC_HW_DUMP_TAG_MAX_LEN 32
  46. /* Client index to be used to vote clk frequency through sw client */
  47. #define CAM_CLK_SW_CLIENT_IDX -1
  48. /**
  49. * enum cam_vote_level - Enum for voting level
  50. *
  51. * @CAM_SUSPEND_VOTE : Suspend vote
  52. * @CAM_MINSVS_VOTE : Min SVS vote
  53. * @CAM_LOWSVS_VOTE : Low SVS vote
  54. * @CAM_SVS_VOTE : SVS vote
  55. * @CAM_SVSL1_VOTE : SVS Plus vote
  56. * @CAM_NOMINAL_VOTE : Nominal vote
  57. * @CAM_NOMINALL1_VOTE: Nominal plus vote
  58. * @CAM_TURBO_VOTE : Turbo vote
  59. * @CAM_MAX_VOTE : Max voting level, This is invalid level.
  60. */
  61. enum cam_vote_level {
  62. CAM_SUSPEND_VOTE,
  63. CAM_MINSVS_VOTE,
  64. CAM_LOWSVS_VOTE,
  65. CAM_SVS_VOTE,
  66. CAM_SVSL1_VOTE,
  67. CAM_NOMINAL_VOTE,
  68. CAM_NOMINALL1_VOTE,
  69. CAM_TURBO_VOTE,
  70. CAM_MAX_VOTE,
  71. };
  72. /* pinctrl states */
  73. #define CAM_SOC_PINCTRL_STATE_SLEEP "cam_suspend"
  74. #define CAM_SOC_PINCTRL_STATE_DEFAULT "cam_default"
  75. #define CAM_CESTA_MAX_CLIENTS 3
  76. /**
  77. * struct cam_soc_util_hw_client_clk_rates: Information about HW client clock vote
  78. *
  79. * @high: HW client clock vote high value
  80. * @low: HW client clock vote low value
  81. **/
  82. struct cam_soc_util_hw_client_clk_rates {
  83. unsigned long high;
  84. unsigned long low;
  85. };
  86. /**
  87. * struct cam_soc_util_clk_rates: Information about clock vote for SW and HW clients
  88. *
  89. * @sw_client: SW client clock vote
  90. * @hw_client: HW client clock vote
  91. **/
  92. struct cam_soc_util_clk_rates {
  93. unsigned long sw_client;
  94. struct cam_soc_util_hw_client_clk_rates hw_client[CAM_CESTA_MAX_CLIENTS];
  95. };
  96. /**
  97. * struct cam_soc_reg_map: Information about the mapped register space
  98. *
  99. * @mem_base: Starting location of MAPPED register space
  100. * @mem_cam_base: Starting offset of this register space compared
  101. * to ENTIRE Camera register space
  102. * @size: Size of register space
  103. **/
  104. struct cam_soc_reg_map {
  105. void __iomem *mem_base;
  106. uint32_t mem_cam_base;
  107. resource_size_t size;
  108. };
  109. /**
  110. * struct cam_soc_pinctrl_state: Information about pinctrl state
  111. *
  112. * @gpio_state_active: default pinctrl state
  113. * @gpio_state_suspend: suspend state of pinctrl
  114. * @is_active: to identify if pinctrl is in use.
  115. **/
  116. struct cam_soc_pinctrl_state {
  117. struct pinctrl_state *gpio_state_active;
  118. struct pinctrl_state *gpio_state_suspend;
  119. bool is_active;
  120. };
  121. /**
  122. * struct cam_soc_pinctrl_info: Information about pinctrl data
  123. *
  124. * @pinctrl: pintrl object
  125. * @pctrl_state: pinctrl state montior map
  126. **/
  127. struct cam_soc_pinctrl_info {
  128. struct pinctrl *pinctrl;
  129. struct cam_soc_pinctrl_state pctrl_state[
  130. CAM_SOC_MAX_PINCTRL_MAP];
  131. };
  132. /**
  133. * struct cam_soc_gpio_data: Information about the gpio pins
  134. *
  135. * @cam_gpio_common_tbl: It is list of al the gpios present in gpios node
  136. * @cam_gpio_common_tbl_size: It is equal to number of gpios prsent in
  137. * gpios node in DTSI
  138. * @cam_gpio_req_tbl It is list of al the requesetd gpios
  139. * @cam_gpio_req_tbl_size: It is size of requested gpios
  140. **/
  141. struct cam_soc_gpio_data {
  142. struct gpio *cam_gpio_common_tbl;
  143. uint8_t cam_gpio_common_tbl_size;
  144. struct gpio *cam_gpio_req_tbl;
  145. uint8_t cam_gpio_req_tbl_size;
  146. };
  147. /**
  148. * struct cam_hw_soc_info: Soc information pertaining to specific instance of
  149. * Camera hardware driver module
  150. *
  151. * @pdev: Platform device pointer
  152. * @device: Device pointer
  153. * @hw_version: Camera device version
  154. * @index: Instance id for the camera device
  155. * @dev_name: Device Name
  156. * @is_nrt_dev: Whether this is a non-real time device
  157. * @irq_name: Name of the irq associated with the device
  158. * @label_name: label name
  159. * @irq_line: Irq resource
  160. * @irq_num: Irq number
  161. * @irq_data: Private data that is passed when IRQ is requested
  162. * @compatible: Compatible string associated with the device
  163. * @num_mem_block: Number of entry in the "reg-names"
  164. * @mem_block_name: Array of the reg block name
  165. * @mem_block_cam_base: Array of offset of this register space compared
  166. * to ENTIRE Camera register space
  167. * @mem_block: Associated resource structs
  168. * @reg_map: Array of Mapped register info for the "reg-names"
  169. * @num_reg_map: Number of mapped register space associated
  170. * with mem_block. num_reg_map = num_mem_block in
  171. * most cases
  172. * @reserve_mem: Whether to reserve memory for Mem blocks
  173. * @num_rgltr: Number of regulators
  174. * @rgltr_name: Array of regulator names
  175. * @rgltr_ctrl_support: Whether regulator control is supported
  176. * @rgltr_min_volt: Array of minimum regulator voltage
  177. * @rgltr_max_volt: Array of maximum regulator voltage
  178. * @rgltr_op_mode: Array of regulator operation mode
  179. * @rgltr_type: Array of regulator names
  180. * @rgltr: Array of associated regulator resources
  181. * @rgltr_delay: Array of regulator delay values
  182. * @num_clk: Number of clocks
  183. * @clk_name: Array of clock names
  184. * @clk: Array of associated clock resources
  185. * @clk_rate: 2D array of clock rates representing clock rate
  186. * values at different vote levels
  187. * @clk_id Clock IDs
  188. * @shared_clk_mask Mask indicating which of the clocks are shared with
  189. * other devices. Set rate on these clocks needs to go
  190. * through camera clk wrapper for aggregation.
  191. * @prev_clk_level Last vote level
  192. * @src_clk_idx: Source clock index that is rate-controllable
  193. * @applied_src_clk_rates: Applied src clock rates for SW and HW client
  194. * @clk_level_valid: Indicates whether corresponding level is valid
  195. * @lowest_clk_level: Lowest clock level that has valid freq info
  196. * @scl_clk_count: Number of scalable clocks present
  197. * @scl_clk_idx: Index of scalable clocks
  198. * @optional_clk_name: Array of clock names
  199. * @optional_clk: Array of associated clock resources
  200. * @optional_clk_rate: Optional clock's clk rate
  201. * @optional_clk_id Clock IDs
  202. * @optional_shared_clk_mask Mask indicating which of the clocks are shared with
  203. * other devices. Set rate on these clocks needs to go
  204. * through camera clk wrapper for aggregation.
  205. * @gpio_data: Pointer to gpio info
  206. * @mmrm_handle: MMRM Client handle for src clock
  207. * @is_clk_drv_en: If clock drv is enabled in hw
  208. * @pinctrl_info: Pointer to pinctrl info
  209. * @dentry: Debugfs entry
  210. * @clk_level_override_high:Clk level set from debugfs. When cesta is enabled, used to override
  211. * high clk value
  212. * @clk_level_override_high:Low clk level set from debugfs when cesta is enabled, used to override
  213. * low clk value
  214. * @clk_control: Enable/disable clk rate control through debugfs
  215. * @cam_cx_ipeak_enable cx-ipeak enable/disable flag
  216. * @cam_cx_ipeak_bit cx-ipeak mask for driver
  217. * @soc_private: Soc private data
  218. */
  219. struct cam_hw_soc_info {
  220. struct platform_device *pdev;
  221. struct device *dev;
  222. uint32_t hw_version;
  223. uint32_t index;
  224. const char *dev_name;
  225. bool is_nrt_dev;
  226. const char *irq_name;
  227. const char *label_name;
  228. struct resource *irq_line;
  229. int irq_num;
  230. void *irq_data;
  231. const char *compatible;
  232. uint32_t num_mem_block;
  233. const char *mem_block_name[CAM_SOC_MAX_BLOCK];
  234. uint32_t mem_block_cam_base[CAM_SOC_MAX_BLOCK];
  235. struct resource *mem_block[CAM_SOC_MAX_BLOCK];
  236. struct cam_soc_reg_map reg_map[CAM_SOC_MAX_BASE];
  237. uint32_t num_reg_map;
  238. uint32_t reserve_mem;
  239. uint32_t num_rgltr;
  240. const char *rgltr_name[CAM_SOC_MAX_REGULATOR];
  241. uint32_t rgltr_ctrl_support;
  242. uint32_t rgltr_min_volt[CAM_SOC_MAX_REGULATOR];
  243. uint32_t rgltr_max_volt[CAM_SOC_MAX_REGULATOR];
  244. uint32_t rgltr_op_mode[CAM_SOC_MAX_REGULATOR];
  245. uint32_t rgltr_type[CAM_SOC_MAX_REGULATOR];
  246. struct regulator *rgltr[CAM_SOC_MAX_REGULATOR];
  247. uint32_t rgltr_delay[CAM_SOC_MAX_REGULATOR];
  248. uint32_t use_shared_clk;
  249. uint32_t num_clk;
  250. const char *clk_name[CAM_SOC_MAX_CLK];
  251. struct clk *clk[CAM_SOC_MAX_CLK];
  252. int32_t clk_rate[CAM_MAX_VOTE][CAM_SOC_MAX_CLK];
  253. uint32_t clk_id[CAM_SOC_MAX_CLK];
  254. uint32_t shared_clk_mask;
  255. int32_t prev_clk_level;
  256. int32_t src_clk_idx;
  257. struct cam_soc_util_clk_rates applied_src_clk_rates;
  258. bool clk_level_valid[CAM_MAX_VOTE];
  259. uint32_t lowest_clk_level;
  260. int32_t scl_clk_count;
  261. int32_t scl_clk_idx[CAM_SOC_MAX_CLK];
  262. const char *optional_clk_name[CAM_SOC_MAX_OPT_CLK];
  263. struct clk *optional_clk[CAM_SOC_MAX_OPT_CLK];
  264. int32_t optional_clk_rate[CAM_SOC_MAX_OPT_CLK];
  265. uint32_t optional_clk_id[CAM_SOC_MAX_OPT_CLK];
  266. uint32_t optional_shared_clk_mask;
  267. void *mmrm_handle;
  268. bool is_clk_drv_en;
  269. struct cam_soc_gpio_data *gpio_data;
  270. struct cam_soc_pinctrl_info pinctrl_info;
  271. struct dentry *dentry;
  272. uint32_t clk_level_override_high;
  273. uint32_t clk_level_override_low;
  274. bool clk_control_enable;
  275. bool cam_cx_ipeak_enable;
  276. int32_t cam_cx_ipeak_bit;
  277. void *soc_private;
  278. };
  279. /**
  280. * struct cam_hw_soc_dump_header - SOC dump header
  281. *
  282. * @Brief: soc hw dump header
  283. *
  284. * @tag: Tag name for the header
  285. * @word_size: Size of each word
  286. * @size: Total size of dumped data
  287. */
  288. struct cam_hw_soc_dump_header {
  289. uint8_t tag[CAM_SOC_HW_DUMP_TAG_MAX_LEN];
  290. uint64_t size;
  291. uint32_t word_size;
  292. };
  293. /**
  294. * struct cam_hw_soc_dump_args: SOC Dump args
  295. *
  296. * @request_id: Issue request id
  297. * @offset: Buffer offset, updated as the informaton is dumped
  298. * @buf_handle: Buffer handle of the out buffer
  299. */
  300. struct cam_hw_soc_dump_args {
  301. uint64_t request_id;
  302. size_t offset;
  303. uint32_t buf_handle;
  304. };
  305. /*
  306. * CAM_SOC_GET_REG_MAP_START
  307. *
  308. * @brief: This MACRO will get the mapped starting address
  309. * where the register space can be accessed
  310. *
  311. * @__soc_info: Device soc information
  312. * @__base_index: Index of register space in the HW block
  313. *
  314. * @return: Returns a pointer to the mapped register memory
  315. */
  316. #define CAM_SOC_GET_REG_MAP_START(__soc_info, __base_index) \
  317. ((!__soc_info || __base_index >= __soc_info->num_reg_map) ? \
  318. NULL : __soc_info->reg_map[__base_index].mem_base)
  319. /*
  320. * CAM_SOC_GET_REG_MAP_CAM_BASE
  321. *
  322. * @brief: This MACRO will get the cam_base of the
  323. * register space
  324. *
  325. * @__soc_info: Device soc information
  326. * @__base_index: Index of register space in the HW block
  327. *
  328. * @return: Returns an int32_t value.
  329. * Failure: -1
  330. * Success: Starting offset of register space compared
  331. * to entire Camera Register Map
  332. */
  333. #define CAM_SOC_GET_REG_MAP_CAM_BASE(__soc_info, __base_index) \
  334. ((!__soc_info || __base_index >= __soc_info->num_reg_map) ? \
  335. -1 : __soc_info->reg_map[__base_index].mem_cam_base)
  336. /*
  337. * CAM_SOC_GET_REG_MAP_SIZE
  338. *
  339. * @brief: This MACRO will get the size of the mapped
  340. * register space
  341. *
  342. * @__soc_info: Device soc information
  343. * @__base_index: Index of register space in the HW block
  344. *
  345. * @return: Returns a uint32_t value.
  346. * Failure: 0
  347. * Success: Non-zero size of mapped register space
  348. */
  349. #define CAM_SOC_GET_REG_MAP_SIZE(__soc_info, __base_index) \
  350. ((!__soc_info || __base_index >= __soc_info->num_reg_map) ? \
  351. 0 : __soc_info->reg_map[__base_index].size)
  352. /**
  353. * cam_soc_util_get_level_from_string()
  354. *
  355. * @brief: Get the associated vote level for the input string
  356. *
  357. * @string: Input string to compare with.
  358. * @level: Vote level corresponds to input string.
  359. *
  360. * @return: Success or failure
  361. */
  362. int cam_soc_util_get_level_from_string(const char *string,
  363. enum cam_vote_level *level);
  364. /**
  365. * cam_soc_util_get_dt_properties()
  366. *
  367. * @brief: Parse the DT and populate the common properties that
  368. * are part of the soc_info structure - register map,
  369. * clocks, regulators, irq, etc.
  370. *
  371. * @soc_info: Device soc struct to be populated
  372. *
  373. * @return: Success or failure
  374. */
  375. int cam_soc_util_get_dt_properties(struct cam_hw_soc_info *soc_info);
  376. /**
  377. * cam_soc_util_request_platform_resource()
  378. *
  379. * @brief: Request regulator, irq, and clock resources
  380. *
  381. * @soc_info: Device soc information
  382. * @handler: Irq handler function pointer
  383. * @irq_data: Irq handler function CB data
  384. *
  385. * @return: Success or failure
  386. */
  387. int cam_soc_util_request_platform_resource(struct cam_hw_soc_info *soc_info,
  388. irq_handler_t handler, void *irq_data);
  389. /**
  390. * cam_soc_util_release_platform_resource()
  391. *
  392. * @brief: Release regulator, irq, and clock resources
  393. *
  394. * @soc_info: Device soc information
  395. *
  396. * @return: Success or failure
  397. */
  398. int cam_soc_util_release_platform_resource(struct cam_hw_soc_info *soc_info);
  399. /**
  400. * cam_soc_util_enable_platform_resource()
  401. *
  402. * @brief: Enable regulator, irq resources
  403. *
  404. * @soc_info: Device soc information
  405. * @cesta_client_idx: CESTA Client idx for hw client based src clocks
  406. * @enable_clocks: Boolean flag:
  407. * TRUE: Enable all clocks in soc_info Now.
  408. * False: Don't enable clocks Now. Driver will
  409. * enable independently.
  410. * @clk_level: Clock level to be applied.
  411. * Applicable only if enable_clocks is true
  412. * Valid range : 0 to (CAM_MAX_VOTE - 1)
  413. * @enable_irq: Boolean flag:
  414. * TRUE: Enable IRQ in soc_info Now.
  415. * False: Don't enable IRQ Now. Driver will
  416. * enable independently.
  417. *
  418. * @return: Success or failure
  419. */
  420. int cam_soc_util_enable_platform_resource(struct cam_hw_soc_info *soc_info,
  421. int cesta_client_idx, bool enable_clocks, enum cam_vote_level clk_level,
  422. bool enable_irq);
  423. /**
  424. * cam_soc_util_disable_platform_resource()
  425. *
  426. * @brief: Disable regulator, irq resources
  427. *
  428. * @soc_info: Device soc information
  429. * @cesta_client_idx: CESTA Client idx for hw client based src clocks
  430. * @disable_irq: Boolean flag:
  431. * TRUE: Disable IRQ in soc_info Now.
  432. * False: Don't disable IRQ Now. Driver will
  433. * disable independently.
  434. *
  435. * @return: Success or failure
  436. */
  437. int cam_soc_util_disable_platform_resource(struct cam_hw_soc_info *soc_info,
  438. int cesta_client_idx, bool disable_clocks, bool disable_irq);
  439. /**
  440. * cam_soc_util_get_clk_round_rate()
  441. *
  442. * @brief: Get the rounded clock rate for the given clock's
  443. * clock rate value
  444. *
  445. * @soc_info: Device soc information
  446. * @clk_index: Clock index in soc_info for which round rate is needed
  447. * @clk_rate: Input clock rate for which rounded rate is needed
  448. *
  449. * @return: Rounded clock rate
  450. */
  451. long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info,
  452. uint32_t clk_index, unsigned long clk_rate);
  453. /**
  454. * cam_soc_util_set_src_clk_rate()
  455. *
  456. * @brief: Set the rate on the source clock for sw or hw clients. Requires a valid
  457. * CESTA client idx for hw client voting.
  458. *
  459. * @soc_info: Device soc information
  460. * @cesta_client_idx: CESTA client idx if src clock belongs to cesta client, otherwise -1
  461. * @clk_rate_high: High clock rate associated with the src clk, applies to sw client vote
  462. * if not cesta client
  463. * @clk_rate_low: Low clock rate associated with the src clk, only applies to cesta based
  464. * hw client vote
  465. *
  466. * @return: success or failure
  467. */
  468. int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info, int cesta_client_idx,
  469. unsigned long clk_rate_high, unsigned long clk_rate_low);
  470. /**
  471. * cam_soc_util_get_option_clk_by_name()
  472. *
  473. * @brief: Get reference to optional clk using name
  474. *
  475. * @soc_info: Device soc information
  476. * @clk_name: Name of clock to find reference for
  477. * @clk_index: Clk index in the option clk array to be returned
  478. *
  479. * @return: 0: Success
  480. * Negative: Failure
  481. */
  482. int cam_soc_util_get_option_clk_by_name(struct cam_hw_soc_info *soc_info,
  483. const char *clk_name, int32_t *clk_index);
  484. /**
  485. * cam_soc_util_put_optional_clk()
  486. *
  487. * @brief: Put clock corresponding to index specified in params
  488. *
  489. * @soc_info: Device soc information
  490. * @clk_idx: Clock index in optional clocks to put
  491. *
  492. * @return: Success or failure
  493. */
  494. int cam_soc_util_put_optional_clk(struct cam_hw_soc_info *soc_info,
  495. int32_t clk_idx);
  496. /**
  497. * cam_soc_util_clk_enable()
  498. *
  499. * @brief: Enable clock specified in params
  500. *
  501. * @soc_info: Device soc information
  502. * @cesta_client_idx: CESTA Client idx for hw client based src clocks
  503. * @optional_clk: Whether to set optional clk or normal clk with
  504. * the idx given
  505. * @clk_idx: Clock index to set
  506. * @apply_level: Apply level.
  507. * -1 for 0 rate
  508. * any other value indicate level for normal clocks
  509. * For optional clocks any other value means the rate saved
  510. * in soc_info
  511. *
  512. * @return: Success or failure
  513. */
  514. int cam_soc_util_clk_enable(struct cam_hw_soc_info *soc_info, int cesta_client_idx,
  515. bool optional_clk, int32_t clk_idx, int32_t apply_level);
  516. /**
  517. * cam_soc_util_set_clk_rate_level()
  518. *
  519. * @brief: Apply clock rates for the requested level.
  520. * This applies the new requested level for all
  521. * the clocks listed in DT based on their values.
  522. *
  523. * @soc_info: Device soc information
  524. * @cesta_client_idx: CESTA client idx for HW client based src clocks
  525. * @clk_level_high: Clock level number to set, high value if crm based src clock
  526. * @clk_level_low: Low clock level value if crm based src clock
  527. * @do_not_set_src_clk: If true, set clock rates except the src clk
  528. *
  529. * @return: Success or failure
  530. */
  531. int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info,
  532. int cesta_client_idx, enum cam_vote_level clk_level_high,
  533. enum cam_vote_level clk_level_low, bool do_not_set_src_clk);
  534. /**
  535. * cam_soc_util_clk_disable()
  536. *
  537. * @brief: Disable clock specified in params
  538. *
  539. * @soc_info: Device soc information
  540. * @cesta_client_idx: CESTA Client idx for hw client based src clocks
  541. * @optional_clk: Whether to set optional clk or normal clk with
  542. * the idx given
  543. * @clk_idx: Clock index to disable
  544. *
  545. * @return: Success or failure
  546. */
  547. int cam_soc_util_clk_disable(struct cam_hw_soc_info *soc_info, int cesta_client_idx,
  548. bool optional_clk, int32_t clk_idx);
  549. /**
  550. * cam_soc_util_irq_enable()
  551. *
  552. * @brief: Enable IRQ in SOC
  553. *
  554. * @soc_info: Device soc information
  555. *
  556. * @return: Success or failure
  557. */
  558. int cam_soc_util_irq_enable(struct cam_hw_soc_info *soc_info);
  559. /**
  560. * cam_soc_util_irq_disable()
  561. *
  562. * @brief: Disable IRQ in SOC
  563. *
  564. * @soc_info: Device soc information
  565. *
  566. * @return: Success or failure
  567. */
  568. int cam_soc_util_irq_disable(struct cam_hw_soc_info *soc_info);
  569. /**
  570. * cam_soc_util_regulator_enable()
  571. *
  572. * @brief: Enable single regulator
  573. *
  574. * @rgltr Regulator that needs to be turned ON
  575. * @rgltr_name Associated Regulator name
  576. * @rgltr_min_volt: Requested minimum volatage
  577. * @rgltr_max_volt: Requested maximum volatage
  578. * @rgltr_op_mode: Requested Load
  579. * @rgltr_delay: Requested delay needed aaftre enabling regulator
  580. *
  581. * @return: Success or failure
  582. */
  583. int cam_soc_util_regulator_enable(struct regulator *rgltr,
  584. const char *rgltr_name,
  585. uint32_t rgltr_min_volt, uint32_t rgltr_max_volt,
  586. uint32_t rgltr_op_mode, uint32_t rgltr_delay);
  587. /**
  588. * cam_soc_util_regulator_enable()
  589. *
  590. * @brief: Disable single regulator
  591. *
  592. * @rgltr Regulator that needs to be turned ON
  593. * @rgltr_name Associated Regulator name
  594. * @rgltr_min_volt: Requested minimum volatage
  595. * @rgltr_max_volt: Requested maximum volatage
  596. * @rgltr_op_mode: Requested Load
  597. * @rgltr_delay: Requested delay needed aaftre enabling regulator
  598. *
  599. * @return: Success or failure
  600. */
  601. int cam_soc_util_regulator_disable(struct regulator *rgltr,
  602. const char *rgltr_name,
  603. uint32_t rgltr_min_volt, uint32_t rgltr_max_volt,
  604. uint32_t rgltr_op_mode, uint32_t rgltr_delay);
  605. /**
  606. * cam_soc_util_w()
  607. *
  608. * @brief: Camera SOC util for register write
  609. *
  610. * @soc_info: Device soc information
  611. * @base_index: Index of register space in the HW block
  612. * @offset: Offset of register to be read
  613. * @data: Value to be written
  614. *
  615. * @return: Success or Failure
  616. */
  617. static inline int cam_soc_util_w(struct cam_hw_soc_info *soc_info,
  618. uint32_t base_index, uint32_t offset, uint32_t data)
  619. {
  620. if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index))
  621. return -EINVAL;
  622. return cam_io_w(data,
  623. CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset);
  624. }
  625. /**
  626. * cam_soc_util_w_mb()
  627. *
  628. * @brief: Camera SOC util for register write with memory barrier.
  629. * Memory Barrier is only before the write to ensure the
  630. * order. If need to ensure this write is also flushed
  631. * call wmb() independently in the caller.
  632. *
  633. * @soc_info: Device soc information
  634. * @base_index: Index of register space in the HW block
  635. * @offset: Offset of register to be read
  636. * @data: Value to be written
  637. *
  638. * @return: Success or Failure
  639. */
  640. static inline int cam_soc_util_w_mb(struct cam_hw_soc_info *soc_info,
  641. uint32_t base_index, uint32_t offset, uint32_t data)
  642. {
  643. if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index))
  644. return -EINVAL;
  645. return cam_io_w_mb(data,
  646. CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset);
  647. }
  648. /**
  649. * cam_soc_util_r()
  650. *
  651. * @brief: Camera SOC util for register read
  652. *
  653. * @soc_info: Device soc information
  654. * @base_index: Index of register space in the HW block
  655. * @offset: Offset of register to be read
  656. *
  657. * @return: Value read from the register address
  658. */
  659. static inline uint32_t cam_soc_util_r(struct cam_hw_soc_info *soc_info,
  660. uint32_t base_index, uint32_t offset)
  661. {
  662. if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index))
  663. return 0;
  664. return cam_io_r(
  665. CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset);
  666. }
  667. /**
  668. * cam_soc_util_r_mb()
  669. *
  670. * @brief: Camera SOC util for register read with memory barrier.
  671. * Memory Barrier is only before the write to ensure the
  672. * order. If need to ensure this write is also flushed
  673. * call rmb() independently in the caller.
  674. *
  675. * @soc_info: Device soc information
  676. * @base_index: Index of register space in the HW block
  677. * @offset: Offset of register to be read
  678. *
  679. * @return: Value read from the register address
  680. */
  681. static inline uint32_t cam_soc_util_r_mb(struct cam_hw_soc_info *soc_info,
  682. uint32_t base_index, uint32_t offset)
  683. {
  684. if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index))
  685. return 0;
  686. return cam_io_r_mb(
  687. CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset);
  688. }
  689. /**
  690. * cam_soc_util_reg_dump()
  691. *
  692. * @brief: Camera SOC util for dumping a range of register
  693. *
  694. * @soc_info: Device soc information
  695. * @base_index: Index of register space in the HW block
  696. * @offset: Start register offset for the dump
  697. * @size: Size specifying the range for dump
  698. *
  699. * @return: Success or Failure
  700. */
  701. int cam_soc_util_reg_dump(struct cam_hw_soc_info *soc_info,
  702. uint32_t base_index, uint32_t offset, int size);
  703. void cam_soc_util_clk_disable_default(struct cam_hw_soc_info *soc_info,
  704. int cesta_client_idx);
  705. int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info, int cesta_client_idx,
  706. enum cam_vote_level clk_level);
  707. int cam_soc_util_get_clk_level(struct cam_hw_soc_info *soc_info,
  708. int64_t clk_rate, int clk_idx, int32_t *clk_lvl);
  709. /* Callback to get reg space data for specific HW */
  710. typedef int (*cam_soc_util_regspace_data_cb)(uint32_t reg_base_type,
  711. void *ctx, struct cam_hw_soc_info **soc_info_ptr,
  712. uint32_t *reg_base_idx);
  713. /**
  714. * cam_soc_util_reg_dump_to_cmd_buf()
  715. *
  716. * @brief: Camera SOC util for dumping sets of register ranges
  717. * command buffer
  718. *
  719. * @ctx: Context info from specific hardware manager
  720. * @cmd_desc: Command buffer descriptor
  721. * @req_id: Last applied req id for which reg dump is required
  722. * @reg_data_cb: Callback function to get reg space info based on type
  723. * in command buffer
  724. * @soc_dump_args: Dump buffer args to dump the soc information.
  725. * @user_triggered_dump: Flag to indicate if the dump request is issued by
  726. * user.
  727. * @return: Success or Failure
  728. */
  729. int cam_soc_util_reg_dump_to_cmd_buf(void *ctx,
  730. struct cam_cmd_buf_desc *cmd_desc, uint64_t req_id,
  731. cam_soc_util_regspace_data_cb reg_data_cb,
  732. struct cam_hw_soc_dump_args *soc_dump_args,
  733. bool user_triggered_dump);
  734. /**
  735. * cam_soc_util_print_clk_freq()
  736. *
  737. * @brief: This function gets the clk rates for each clk from clk
  738. * driver and prints in log
  739. *
  740. * @soc_info: Device soc struct to be populated
  741. *
  742. * @return: success or failure
  743. */
  744. int cam_soc_util_print_clk_freq(struct cam_hw_soc_info *soc_info);
  745. /**
  746. * cam_soc_util_select_pinctrl_state()
  747. *
  748. * @brief: This function gets the pinctrl handle
  749. *
  750. * @soc_info: Device soc struct to be populated
  751. * @active: True for active and false for suspend state
  752. *
  753. * @return: success or failure
  754. */
  755. int cam_soc_util_select_pinctrl_state(
  756. struct cam_hw_soc_info *soc_info, int idx, bool active);
  757. /**
  758. * cam_soc_util_print_clk_freq()
  759. *
  760. * @brief: This function checks whether regulators of this device are enabled at this
  761. * time.
  762. *
  763. * @soc_info: Device soc struct to be populated
  764. *
  765. * @return: Number of regulators enabled
  766. */
  767. int cam_soc_util_regulators_enabled(struct cam_hw_soc_info *soc_info);
  768. /**
  769. * cam_soc_util_cesta_populate_crm_device()
  770. *
  771. * @brief: This function populates the camera cesta crm device in soc util
  772. *
  773. * @return: success or failure
  774. */
  775. inline int cam_soc_util_cesta_populate_crm_device(void);
  776. /**
  777. * cam_soc_util_cesta_channel_switch()
  778. *
  779. * @brief: This function triggers the application of power states to crm
  780. * and channel switch operation in hw. Also, for camera it applies
  781. * the high vote of the active channel
  782. * @cesta_client_idx: CESTA client index through which power states need to be applied
  783. * @identifier: Identifying the caller triggerring channel switch
  784. *
  785. * @return: success or failure
  786. */
  787. int cam_soc_util_cesta_channel_switch(uint32_t cesta_client_idx, const char *identifier);
  788. /**
  789. * cam_soc_util_get_applied_src_clk()
  790. *
  791. * @brief: Inline function to get applied src clk rate.
  792. * @soc_info: Device soc struct to be populated
  793. * @is_max: Is max of all hw clients if cesta is enabled
  794. *
  795. * @return: success or failure
  796. */
  797. inline unsigned long cam_soc_util_get_applied_src_clk(
  798. struct cam_hw_soc_info *soc_info, bool is_max);
  799. /**
  800. * cam_soc_util_get_string_from_level()
  801. *
  802. * @brief: Returns the string for a given clk level
  803. *
  804. * @level: Clock level
  805. *
  806. * @return: String corresponding to the clk level
  807. */
  808. const char *cam_soc_util_get_string_from_level(enum cam_vote_level level);
  809. #endif /* _CAM_SOC_UTIL_H_ */