cam_soc_util.c 106 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/of.h>
  7. #include <linux/clk.h>
  8. #include <linux/slab.h>
  9. #include <linux/gpio.h>
  10. #include <linux/of_gpio.h>
  11. #include "cam_soc_util.h"
  12. #include "cam_debug_util.h"
  13. #include "cam_cx_ipeak.h"
  14. #include "cam_mem_mgr.h"
  15. #include "cam_presil_hw_access.h"
  16. #include "cam_compat.h"
  17. #if IS_ENABLED(CONFIG_QCOM_CRM)
  18. #include <soc/qcom/crm.h>
  19. #include <linux/clk/qcom.h>
  20. #endif
  21. #define CAM_TO_MASK(bitn) (1 << (int)(bitn))
  22. #define CAM_IS_BIT_SET(mask, bit) ((mask) & CAM_TO_MASK(bit))
  23. #define CAM_SET_BIT(mask, bit) ((mask) |= CAM_TO_MASK(bit))
  24. #define CAM_CLEAR_BIT(mask, bit) ((mask) &= ~CAM_TO_MASK(bit))
  25. #define CAM_SS_START_PRESIL 0x08c00000
  26. #define CAM_SS_START 0x0ac00000
  27. #define CAM_CLK_DIRNAME "clk"
  28. static uint skip_mmrm_set_rate;
  29. module_param(skip_mmrm_set_rate, uint, 0644);
  30. /**
  31. * struct cam_clk_wrapper_clk: This represents an entry corresponding to a
  32. * shared clock in Clk wrapper. Clients that share
  33. * the same clock are registered to this clk entry
  34. * and set rate from them is consolidated before
  35. * setting it to clk driver.
  36. *
  37. * @list: List pointer to point to next shared clk entry
  38. * @clk_id: Clk Id of this clock
  39. * @curr_clk_rate: Current clock rate set for this clock
  40. * @client_list: List of clients registered to this shared clock entry
  41. * @num_clients: Number of registered clients
  42. * @active_clients: Number of active clients
  43. * @mmrm_client: MMRM Client handle for src clock
  44. * @soc_info: soc_info of client with which mmrm handle is created.
  45. * This is used as unique identifier for a client and mmrm
  46. * callback data. When client corresponds to this soc_info is
  47. * unregistered, need to unregister mmrm handle as well.
  48. * @is_nrt_dev: Whether this clock corresponds to NRT device
  49. * @min_clk_rate: Minimum clk rate that this clock supports
  50. **/
  51. struct cam_clk_wrapper_clk {
  52. struct list_head list;
  53. uint32_t clk_id;
  54. int64_t curr_clk_rate;
  55. struct list_head client_list;
  56. uint32_t num_clients;
  57. uint32_t active_clients;
  58. void *mmrm_handle;
  59. struct cam_hw_soc_info *soc_info;
  60. bool is_nrt_dev;
  61. int64_t min_clk_rate;
  62. };
  63. /**
  64. * struct cam_clk_wrapper_client: This represents a client (device) that wants
  65. * to share the clock with some other client.
  66. *
  67. * @list: List pointer to point to next client that share the
  68. * same clock
  69. * @soc_info: soc_info of client. This is used as unique identifier
  70. * for a client
  71. * @clk: Clk handle
  72. * @curr_clk_rate: Current clock rate set for this client
  73. **/
  74. struct cam_clk_wrapper_client {
  75. struct list_head list;
  76. struct cam_hw_soc_info *soc_info;
  77. struct clk *clk;
  78. int64_t curr_clk_rate;
  79. };
  80. static char supported_clk_info[256];
  81. static DEFINE_MUTEX(wrapper_lock);
  82. static LIST_HEAD(wrapper_clk_list);
  83. #define CAM_IS_VALID_CESTA_IDX(idx) ((idx >= 0) && (idx < CAM_CESTA_MAX_CLIENTS))
  84. #define CAM_CRM_DEV_IDENTIFIER "cam_crm"
  85. const struct device *cam_cesta_crm_dev;
  86. #if IS_ENABLED(CONFIG_QCOM_CRM)
  87. inline int cam_soc_util_cesta_populate_crm_device(void)
  88. {
  89. cam_cesta_crm_dev = crm_get_device(CAM_CRM_DEV_IDENTIFIER);
  90. if (!cam_cesta_crm_dev) {
  91. CAM_ERR(CAM_UTIL, "Failed to get cesta crm dev for %s", CAM_CRM_DEV_IDENTIFIER);
  92. return -ENODEV;
  93. }
  94. return 0;
  95. }
  96. int cam_soc_util_cesta_channel_switch(uint32_t cesta_client_idx, const char *identifier)
  97. {
  98. int rc = 0;
  99. if (!cam_cesta_crm_dev) {
  100. CAM_ERR(CAM_UTIL, "camera cesta crm device is null");
  101. return -EINVAL;
  102. }
  103. if (!CAM_IS_VALID_CESTA_IDX(cesta_client_idx)) {
  104. CAM_ERR(CAM_UTIL, "Invalid client index for camera cesta idx: %d max: %d",
  105. cesta_client_idx, CAM_CESTA_MAX_CLIENTS);
  106. return -EINVAL;
  107. }
  108. CAM_DBG(CAM_PERF, "CESTA Channel switch : hw client idx %d identifier=%s",
  109. cesta_client_idx, identifier);
  110. rc = crm_write_pwr_states(cam_cesta_crm_dev, cesta_client_idx);
  111. if (rc) {
  112. CAM_ERR(CAM_UTIL,
  113. "Failed to trigger cesta channel switch cesta_client_idx: %u rc: %d",
  114. cesta_client_idx, rc);
  115. return rc;
  116. }
  117. return rc;
  118. }
  119. #else
  120. inline int cam_soc_util_cesta_populate_crm_device(void)
  121. {
  122. CAM_ERR(CAM_UTIL, "Not supported");
  123. return -EOPNOTSUPP;
  124. }
  125. inline int cam_soc_util_cesta_channel_switch(uint32_t cesta_client_idx, const char *identifier)
  126. {
  127. CAM_ERR(CAM_UTIL, "Not supported, cesta_client_idx=%d, identifier=%s",
  128. cesta_client_idx, identifier);
  129. return -EOPNOTSUPP;
  130. }
  131. #endif
  132. #if IS_ENABLED(CONFIG_QCOM_CRM) && IS_ENABLED(CONFIG_SPECTRA_USE_CLK_CRM_API)
  133. static int cam_soc_util_set_cesta_clk_rate(struct cam_hw_soc_info *soc_info,
  134. uint32_t cesta_client_idx, unsigned long high_val, unsigned long low_val,
  135. unsigned long *applied_high_val, unsigned long *applied_low_val)
  136. {
  137. int32_t src_clk_idx;
  138. struct clk *clk = NULL;
  139. int rc = 0;
  140. if (!soc_info || (soc_info->src_clk_idx < 0) ||
  141. (soc_info->src_clk_idx >= CAM_SOC_MAX_CLK)) {
  142. CAM_ERR(CAM_UTIL, "Invalid src_clk_idx: %d",
  143. soc_info ? soc_info->src_clk_idx : -1);
  144. return -EINVAL;
  145. }
  146. if (!CAM_IS_VALID_CESTA_IDX(cesta_client_idx)) {
  147. CAM_ERR(CAM_UTIL, "Invalid client index for camera cesta idx: %d max: %d",
  148. cesta_client_idx, CAM_CESTA_MAX_CLIENTS);
  149. return -EINVAL;
  150. }
  151. /* Only source clocks are supported by this API to set HW client clock votes */
  152. src_clk_idx = soc_info->src_clk_idx;
  153. clk = soc_info->clk[src_clk_idx];
  154. CAM_DBG(CAM_UTIL, "%s Requested clk rate [high low]: [%llu %llu] cesta_client_idx: %d",
  155. soc_info->clk_name[src_clk_idx], high_val, low_val, cesta_client_idx);
  156. rc = qcom_clk_crm_set_rate(clk, CRM_HW_DRV, cesta_client_idx, CRM_PWR_STATE1, high_val);
  157. if (rc) {
  158. CAM_ERR(CAM_UTIL,
  159. "Failed in setting cesta high clk rate, client idx: %u pwr state: %u clk_val: %llu rc: %d",
  160. cesta_client_idx, CRM_PWR_STATE1, high_val, rc);
  161. return rc;
  162. }
  163. rc = qcom_clk_crm_set_rate(clk, CRM_HW_DRV, cesta_client_idx, CRM_PWR_STATE0, low_val);
  164. if (rc) {
  165. CAM_ERR(CAM_UTIL,
  166. "Failed in setting cesta low clk rate, client idx: %u pwr state: %u clk_val: %llu rc: %d",
  167. cesta_client_idx, CRM_PWR_STATE0, low_val, rc);
  168. return rc;
  169. }
  170. if (applied_high_val)
  171. *applied_high_val = high_val;
  172. if (applied_low_val)
  173. *applied_low_val = low_val;
  174. return rc;
  175. }
  176. #else
  177. static inline int cam_soc_util_set_cesta_clk_rate(struct cam_hw_soc_info *soc_info,
  178. uint32_t cesta_client_idx, unsigned long high_val, unsigned long low_val,
  179. unsigned long *applied_high_val, unsigned long *applied_low_val)
  180. {
  181. CAM_ERR(CAM_UTIL, "Not supported, dev=%s, cesta_client_idx=%d, high_val=%ld, low_val=%ld",
  182. soc_info->dev_name, cesta_client_idx, high_val, low_val);
  183. return -EOPNOTSUPP;
  184. }
  185. #endif
  186. #if IS_REACHABLE(CONFIG_MSM_MMRM)
  187. bool cam_is_mmrm_supported_on_current_chip(void)
  188. {
  189. bool is_supported;
  190. is_supported = mmrm_client_check_scaling_supported(MMRM_CLIENT_CLOCK,
  191. MMRM_CLIENT_DOMAIN_CAMERA);
  192. CAM_DBG(CAM_UTIL, "is mmrm supported: %s",
  193. CAM_BOOL_TO_YESNO(is_supported));;
  194. return is_supported;
  195. }
  196. int cam_mmrm_notifier_callback(
  197. struct mmrm_client_notifier_data *notifier_data)
  198. {
  199. if (!notifier_data) {
  200. CAM_ERR(CAM_UTIL, "Invalid notifier data");
  201. return -EBADR;
  202. }
  203. if (notifier_data->cb_type == MMRM_CLIENT_RESOURCE_VALUE_CHANGE) {
  204. struct cam_hw_soc_info *soc_info = notifier_data->pvt_data;
  205. CAM_WARN(CAM_UTIL, "Dev %s Clk %s value change from %ld to %ld",
  206. soc_info->dev_name,
  207. (soc_info->src_clk_idx == -1) ? "No src clk" :
  208. soc_info->clk_name[soc_info->src_clk_idx],
  209. notifier_data->cb_data.val_chng.old_val,
  210. notifier_data->cb_data.val_chng.new_val);
  211. }
  212. return 0;
  213. }
  214. int cam_soc_util_register_mmrm_client(
  215. uint32_t clk_id, struct clk *clk, bool is_nrt_dev,
  216. struct cam_hw_soc_info *soc_info, const char *clk_name,
  217. void **mmrm_handle)
  218. {
  219. struct mmrm_client *mmrm_client;
  220. struct mmrm_client_desc desc = { };
  221. if (!mmrm_handle) {
  222. CAM_ERR(CAM_UTIL, "Invalid mmrm input");
  223. return -EINVAL;
  224. }
  225. *mmrm_handle = (void *)NULL;
  226. if (!cam_is_mmrm_supported_on_current_chip())
  227. return 0;
  228. desc.client_type = MMRM_CLIENT_CLOCK;
  229. desc.client_info.desc.client_domain = MMRM_CLIENT_DOMAIN_CAMERA;
  230. desc.client_info.desc.client_id = clk_id;
  231. desc.client_info.desc.clk = clk;
  232. snprintf((char *)desc.client_info.desc.name,
  233. sizeof(desc.client_info.desc.name), "%s_%s",
  234. soc_info->dev_name, clk_name);
  235. desc.priority = is_nrt_dev ?
  236. MMRM_CLIENT_PRIOR_LOW : MMRM_CLIENT_PRIOR_HIGH;
  237. desc.pvt_data = soc_info;
  238. desc.notifier_callback_fn = cam_mmrm_notifier_callback;
  239. mmrm_client = mmrm_client_register(&desc);
  240. if (!mmrm_client) {
  241. CAM_ERR(CAM_UTIL, "MMRM Register failed Dev %s clk %s id %d",
  242. soc_info->dev_name, clk_name, clk_id);
  243. return -EINVAL;
  244. }
  245. CAM_DBG(CAM_UTIL,
  246. "MMRM Register success Dev %s is_nrt_dev %d clk %s id %d handle=%pK",
  247. soc_info->dev_name, is_nrt_dev, clk_name, clk_id, mmrm_client);
  248. *mmrm_handle = (void *)mmrm_client;
  249. return 0;
  250. }
  251. int cam_soc_util_unregister_mmrm_client(
  252. void *mmrm_handle)
  253. {
  254. int rc = 0;
  255. CAM_DBG(CAM_UTIL, "MMRM UnRegister handle=%pK", mmrm_handle);
  256. if (mmrm_handle) {
  257. rc = mmrm_client_deregister((struct mmrm_client *)mmrm_handle);
  258. if (rc)
  259. CAM_ERR(CAM_UTIL,
  260. "Failed in deregister handle=%pK, rc %d",
  261. mmrm_handle, rc);
  262. }
  263. return rc;
  264. }
  265. static int cam_soc_util_set_rate_through_mmrm(
  266. void *mmrm_handle, bool is_nrt_dev, long min_rate,
  267. long req_rate, uint32_t num_hw_blocks)
  268. {
  269. int rc = 0;
  270. struct mmrm_client_data client_data;
  271. struct mmrm_client_res_value val;
  272. client_data.num_hw_blocks = num_hw_blocks;
  273. client_data.flags = 0;
  274. CAM_DBG(CAM_UTIL,
  275. "mmrm=%pK, nrt=%d, min_rate=%ld req_rate %ld, num_blocks=%d",
  276. mmrm_handle, is_nrt_dev, min_rate, req_rate, num_hw_blocks);
  277. if (is_nrt_dev) {
  278. val.min = min_rate;
  279. val.cur = req_rate;
  280. rc = mmrm_client_set_value_in_range(
  281. (struct mmrm_client *)mmrm_handle, &client_data, &val);
  282. } else {
  283. rc = mmrm_client_set_value(
  284. (struct mmrm_client *)mmrm_handle,
  285. &client_data, req_rate);
  286. }
  287. if (rc)
  288. CAM_ERR(CAM_UTIL, "Set rate failed rate %ld rc %d",
  289. req_rate, rc);
  290. return rc;
  291. }
  292. #else
  293. int cam_soc_util_register_mmrm_client(
  294. uint32_t clk_id, struct clk *clk, bool is_nrt_dev,
  295. struct cam_hw_soc_info *soc_info, const char *clk_name,
  296. void **mmrm_handle)
  297. {
  298. if (!mmrm_handle) {
  299. CAM_ERR(CAM_UTIL, "Invalid mmrm input");
  300. return -EINVAL;
  301. }
  302. *mmrm_handle = NULL;
  303. return 0;
  304. }
  305. int cam_soc_util_unregister_mmrm_client(
  306. void *mmrm_handle)
  307. {
  308. return 0;
  309. }
  310. static int cam_soc_util_set_rate_through_mmrm(
  311. void *mmrm_handle, bool is_nrt_dev, long min_rate,
  312. long req_rate, uint32_t num_hw_blocks)
  313. {
  314. return 0;
  315. }
  316. #endif
  317. static int cam_soc_util_clk_wrapper_register_entry(
  318. uint32_t clk_id, struct clk *clk, bool is_src_clk,
  319. struct cam_hw_soc_info *soc_info, int64_t min_clk_rate,
  320. const char *clk_name)
  321. {
  322. struct cam_clk_wrapper_clk *wrapper_clk;
  323. struct cam_clk_wrapper_client *wrapper_client;
  324. bool clock_found = false;
  325. int rc = 0;
  326. mutex_lock(&wrapper_lock);
  327. list_for_each_entry(wrapper_clk, &wrapper_clk_list, list) {
  328. CAM_DBG(CAM_UTIL, "Clk list id %d num clients %d",
  329. wrapper_clk->clk_id, wrapper_clk->num_clients);
  330. if (wrapper_clk->clk_id == clk_id) {
  331. clock_found = true;
  332. list_for_each_entry(wrapper_client,
  333. &wrapper_clk->client_list, list) {
  334. CAM_DBG(CAM_UTIL,
  335. "Clk id %d entry client %s",
  336. wrapper_clk->clk_id,
  337. wrapper_client->soc_info->dev_name);
  338. if (wrapper_client->soc_info == soc_info) {
  339. CAM_ERR(CAM_UTIL,
  340. "Register with same soc info, clk id %d, client %s",
  341. clk_id, soc_info->dev_name);
  342. rc = -EINVAL;
  343. goto end;
  344. }
  345. }
  346. break;
  347. }
  348. }
  349. if (!clock_found) {
  350. CAM_DBG(CAM_UTIL, "Adding new entry for clk id %d", clk_id);
  351. wrapper_clk = kzalloc(sizeof(struct cam_clk_wrapper_clk),
  352. GFP_KERNEL);
  353. if (!wrapper_clk) {
  354. CAM_ERR(CAM_UTIL,
  355. "Failed in allocating new clk entry %d",
  356. clk_id);
  357. rc = -ENOMEM;
  358. goto end;
  359. }
  360. wrapper_clk->clk_id = clk_id;
  361. INIT_LIST_HEAD(&wrapper_clk->list);
  362. INIT_LIST_HEAD(&wrapper_clk->client_list);
  363. list_add_tail(&wrapper_clk->list, &wrapper_clk_list);
  364. }
  365. wrapper_client = kzalloc(sizeof(struct cam_clk_wrapper_client),
  366. GFP_KERNEL);
  367. if (!wrapper_client) {
  368. CAM_ERR(CAM_UTIL, "Failed in allocating new client entry %d",
  369. clk_id);
  370. rc = -ENOMEM;
  371. goto end;
  372. }
  373. wrapper_client->soc_info = soc_info;
  374. wrapper_client->clk = clk;
  375. if (is_src_clk && !wrapper_clk->mmrm_handle) {
  376. wrapper_clk->is_nrt_dev = soc_info->is_nrt_dev;
  377. wrapper_clk->min_clk_rate = min_clk_rate;
  378. wrapper_clk->soc_info = soc_info;
  379. rc = cam_soc_util_register_mmrm_client(clk_id, clk,
  380. wrapper_clk->is_nrt_dev, soc_info, clk_name,
  381. &wrapper_clk->mmrm_handle);
  382. if (rc) {
  383. CAM_ERR(CAM_UTIL,
  384. "Failed in register mmrm client Dev %s clk id %d",
  385. soc_info->dev_name, clk_id);
  386. kfree(wrapper_client);
  387. goto end;
  388. }
  389. }
  390. INIT_LIST_HEAD(&wrapper_client->list);
  391. list_add_tail(&wrapper_client->list, &wrapper_clk->client_list);
  392. wrapper_clk->num_clients++;
  393. CAM_DBG(CAM_UTIL,
  394. "Adding new client %s for clk[%s] id %d, num clients %d",
  395. soc_info->dev_name, clk_name, clk_id, wrapper_clk->num_clients);
  396. end:
  397. mutex_unlock(&wrapper_lock);
  398. return rc;
  399. }
  400. static int cam_soc_util_clk_wrapper_unregister_entry(
  401. uint32_t clk_id, struct cam_hw_soc_info *soc_info)
  402. {
  403. struct cam_clk_wrapper_clk *wrapper_clk;
  404. struct cam_clk_wrapper_client *wrapper_client;
  405. bool clock_found = false;
  406. bool client_found = false;
  407. int rc = 0;
  408. mutex_lock(&wrapper_lock);
  409. list_for_each_entry(wrapper_clk, &wrapper_clk_list, list) {
  410. CAM_DBG(CAM_UTIL, "Clk list id %d num clients %d",
  411. wrapper_clk->clk_id, wrapper_clk->num_clients);
  412. if (wrapper_clk->clk_id == clk_id) {
  413. clock_found = true;
  414. list_for_each_entry(wrapper_client,
  415. &wrapper_clk->client_list, list) {
  416. CAM_DBG(CAM_UTIL, "Clk id %d entry client %s",
  417. wrapper_clk->clk_id,
  418. wrapper_client->soc_info->dev_name);
  419. if (wrapper_client->soc_info == soc_info) {
  420. client_found = true;
  421. break;
  422. }
  423. }
  424. break;
  425. }
  426. }
  427. if (!clock_found) {
  428. CAM_ERR(CAM_UTIL, "Shared clk id %d entry not found", clk_id);
  429. rc = -EINVAL;
  430. goto end;
  431. }
  432. if (!client_found) {
  433. CAM_ERR(CAM_UTIL,
  434. "Client %pK for Shared clk id %d entry not found",
  435. soc_info, clk_id);
  436. rc = -EINVAL;
  437. goto end;
  438. }
  439. wrapper_clk->num_clients--;
  440. if (wrapper_clk->mmrm_handle && (wrapper_clk->soc_info == soc_info)) {
  441. cam_soc_util_unregister_mmrm_client(wrapper_clk->mmrm_handle);
  442. wrapper_clk->mmrm_handle = NULL;
  443. wrapper_clk->soc_info = NULL;
  444. }
  445. list_del_init(&wrapper_client->list);
  446. kfree(wrapper_client);
  447. CAM_DBG(CAM_UTIL, "Unregister client %s for clk id %d, num clients %d",
  448. soc_info->dev_name, clk_id, wrapper_clk->num_clients);
  449. if (!wrapper_clk->num_clients) {
  450. list_del_init(&wrapper_clk->list);
  451. kfree(wrapper_clk);
  452. }
  453. end:
  454. mutex_unlock(&wrapper_lock);
  455. return rc;
  456. }
  457. static int cam_soc_util_clk_wrapper_set_clk_rate(
  458. uint32_t clk_id, struct cam_hw_soc_info *soc_info,
  459. struct clk *clk, int64_t clk_rate)
  460. {
  461. struct cam_clk_wrapper_clk *wrapper_clk;
  462. struct cam_clk_wrapper_client *wrapper_client;
  463. bool clk_found = false;
  464. bool client_found = false;
  465. int rc = 0;
  466. int64_t final_clk_rate = 0;
  467. uint32_t active_clients = 0;
  468. if (!soc_info || !clk) {
  469. CAM_ERR(CAM_UTIL, "Invalid param soc_info %pK clk %pK",
  470. soc_info, clk);
  471. return -EINVAL;
  472. }
  473. mutex_lock(&wrapper_lock);
  474. list_for_each_entry(wrapper_clk, &wrapper_clk_list, list) {
  475. CAM_DBG(CAM_UTIL, "Clk list id %d num clients %d",
  476. wrapper_clk->clk_id, wrapper_clk->num_clients);
  477. if (wrapper_clk->clk_id == clk_id) {
  478. clk_found = true;
  479. break;
  480. }
  481. }
  482. if (!clk_found) {
  483. CAM_ERR(CAM_UTIL, "Clk entry not found id %d client %s",
  484. clk_id, soc_info->dev_name);
  485. rc = -EINVAL;
  486. goto end;
  487. }
  488. list_for_each_entry(wrapper_client, &wrapper_clk->client_list, list) {
  489. CAM_DBG(CAM_UTIL, "Clk id %d client %s, clk rate %lld",
  490. wrapper_clk->clk_id, wrapper_client->soc_info->dev_name,
  491. wrapper_client->curr_clk_rate);
  492. if (wrapper_client->soc_info == soc_info) {
  493. client_found = true;
  494. CAM_DBG(CAM_UTIL,
  495. "Clk enable clk id %d, client %s curr %ld new %ld",
  496. clk_id, wrapper_client->soc_info->dev_name,
  497. wrapper_client->curr_clk_rate, clk_rate);
  498. wrapper_client->curr_clk_rate = clk_rate;
  499. }
  500. if (wrapper_client->curr_clk_rate > 0)
  501. active_clients++;
  502. if (final_clk_rate < wrapper_client->curr_clk_rate)
  503. final_clk_rate = wrapper_client->curr_clk_rate;
  504. }
  505. if (!client_found) {
  506. CAM_ERR(CAM_UTIL,
  507. "Wrapper clk enable without client entry clk id %d client %s",
  508. clk_id, soc_info->dev_name);
  509. rc = -EINVAL;
  510. goto end;
  511. }
  512. CAM_DBG(CAM_UTIL,
  513. "Clk id %d, client %s, clients rate %ld, curr %ld final %ld",
  514. wrapper_clk->clk_id, soc_info->dev_name, clk_rate,
  515. wrapper_clk->curr_clk_rate, final_clk_rate);
  516. if ((final_clk_rate != wrapper_clk->curr_clk_rate) ||
  517. (active_clients != wrapper_clk->active_clients)) {
  518. bool set_rate_finish = false;
  519. if (!skip_mmrm_set_rate && wrapper_clk->mmrm_handle) {
  520. rc = cam_soc_util_set_rate_through_mmrm(
  521. wrapper_clk->mmrm_handle,
  522. wrapper_clk->is_nrt_dev,
  523. wrapper_clk->min_clk_rate,
  524. final_clk_rate, active_clients);
  525. if (rc) {
  526. CAM_ERR(CAM_UTIL,
  527. "set_rate through mmrm failed clk_id %d, rate=%ld",
  528. wrapper_clk->clk_id, final_clk_rate);
  529. goto end;
  530. }
  531. set_rate_finish = true;
  532. }
  533. if (!set_rate_finish && final_clk_rate &&
  534. (final_clk_rate != wrapper_clk->curr_clk_rate)) {
  535. rc = clk_set_rate(clk, final_clk_rate);
  536. if (rc) {
  537. CAM_ERR(CAM_UTIL, "set_rate failed on clk %d",
  538. wrapper_clk->clk_id);
  539. goto end;
  540. }
  541. }
  542. wrapper_clk->curr_clk_rate = final_clk_rate;
  543. wrapper_clk->active_clients = active_clients;
  544. }
  545. end:
  546. mutex_unlock(&wrapper_lock);
  547. return rc;
  548. }
  549. int cam_soc_util_get_clk_level(struct cam_hw_soc_info *soc_info,
  550. int64_t clk_rate, int clk_idx, int32_t *clk_lvl)
  551. {
  552. int i;
  553. long clk_rate_round;
  554. if (!soc_info || (clk_idx < 0) || (clk_idx >= CAM_SOC_MAX_CLK)) {
  555. CAM_ERR(CAM_UTIL, "Invalid src_clk_idx: %d", clk_idx);
  556. *clk_lvl = -1;
  557. return -EINVAL;
  558. }
  559. clk_rate_round = clk_round_rate(soc_info->clk[clk_idx], clk_rate);
  560. if (clk_rate_round < 0) {
  561. CAM_ERR(CAM_UTIL, "round failed rc = %ld",
  562. clk_rate_round);
  563. *clk_lvl = -1;
  564. return -EINVAL;
  565. }
  566. for (i = 0; i < CAM_MAX_VOTE; i++) {
  567. if ((soc_info->clk_level_valid[i]) &&
  568. (soc_info->clk_rate[i][clk_idx] >=
  569. clk_rate_round)) {
  570. CAM_DBG(CAM_UTIL,
  571. "soc = %d round rate = %ld actual = %lld",
  572. soc_info->clk_rate[i][clk_idx],
  573. clk_rate_round, clk_rate);
  574. *clk_lvl = i;
  575. return 0;
  576. }
  577. }
  578. CAM_WARN(CAM_UTIL, "Invalid clock rate %ld", clk_rate_round);
  579. *clk_lvl = -1;
  580. return -EINVAL;
  581. }
  582. const char *cam_soc_util_get_string_from_level(enum cam_vote_level level)
  583. {
  584. switch (level) {
  585. case CAM_SUSPEND_VOTE:
  586. return "";
  587. case CAM_MINSVS_VOTE:
  588. return "MINSVS[1]";
  589. case CAM_LOWSVS_VOTE:
  590. return "LOWSVS[2]";
  591. case CAM_SVS_VOTE:
  592. return "SVS[3]";
  593. case CAM_SVSL1_VOTE:
  594. return "SVSL1[4]";
  595. case CAM_NOMINAL_VOTE:
  596. return "NOM[5]";
  597. case CAM_NOMINALL1_VOTE:
  598. return "NOML1[6]";
  599. case CAM_TURBO_VOTE:
  600. return "TURBO[7]";
  601. default:
  602. return "";
  603. }
  604. }
  605. /**
  606. * cam_soc_util_get_supported_clk_levels()
  607. *
  608. * @brief: Returns the string of all the supported clk levels for
  609. * the given device
  610. *
  611. * @soc_info: Device soc information
  612. *
  613. * @return: String containing all supported clk levels
  614. */
  615. static const char *cam_soc_util_get_supported_clk_levels(
  616. struct cam_hw_soc_info *soc_info)
  617. {
  618. int i = 0;
  619. scnprintf(supported_clk_info, sizeof(supported_clk_info), "Supported levels: ");
  620. for (i = 0; i < CAM_MAX_VOTE; i++) {
  621. if (soc_info->clk_level_valid[i] == true) {
  622. strlcat(supported_clk_info,
  623. cam_soc_util_get_string_from_level(i),
  624. sizeof(supported_clk_info));
  625. strlcat(supported_clk_info, " ",
  626. sizeof(supported_clk_info));
  627. }
  628. }
  629. strlcat(supported_clk_info, "\n", sizeof(supported_clk_info));
  630. return supported_clk_info;
  631. }
  632. static int cam_soc_util_clk_lvl_options_open(struct inode *inode,
  633. struct file *file)
  634. {
  635. file->private_data = inode->i_private;
  636. return 0;
  637. }
  638. static ssize_t cam_soc_util_clk_lvl_options_read(struct file *file,
  639. char __user *clk_info, size_t size_t, loff_t *loff_t)
  640. {
  641. struct cam_hw_soc_info *soc_info =
  642. (struct cam_hw_soc_info *)file->private_data;
  643. const char *display_string =
  644. cam_soc_util_get_supported_clk_levels(soc_info);
  645. return simple_read_from_buffer(clk_info, size_t, loff_t, display_string,
  646. strlen(display_string));
  647. }
  648. static const struct file_operations cam_soc_util_clk_lvl_options = {
  649. .open = cam_soc_util_clk_lvl_options_open,
  650. .read = cam_soc_util_clk_lvl_options_read,
  651. };
  652. static int cam_soc_util_set_clk_lvl_override(void *data, u64 val)
  653. {
  654. struct cam_hw_soc_info *soc_info = (struct cam_hw_soc_info *)data;
  655. if ((val <= CAM_SUSPEND_VOTE) || (val >= CAM_MAX_VOTE)) {
  656. CAM_WARN(CAM_UTIL, "Invalid clk lvl override %d", val);
  657. return 0;
  658. }
  659. if (soc_info->clk_level_valid[val])
  660. soc_info->clk_level_override_high = val;
  661. else
  662. soc_info->clk_level_override_high = 0;
  663. return 0;
  664. }
  665. static int cam_soc_util_get_clk_lvl_override(void *data, u64 *val)
  666. {
  667. struct cam_hw_soc_info *soc_info = (struct cam_hw_soc_info *)data;
  668. *val = soc_info->clk_level_override_high;
  669. return 0;
  670. }
  671. static int cam_soc_util_set_clk_lvl_override_low(void *data, u64 val)
  672. {
  673. struct cam_hw_soc_info *soc_info = (struct cam_hw_soc_info *)data;
  674. if ((val <= CAM_SUSPEND_VOTE) || (val >= CAM_MAX_VOTE)) {
  675. CAM_WARN(CAM_UTIL, "Invalid clk lvl override %d", val);
  676. return 0;
  677. }
  678. if (soc_info->clk_level_valid[val])
  679. soc_info->clk_level_override_low = val;
  680. else
  681. soc_info->clk_level_override_low = 0;
  682. return 0;
  683. }
  684. static int cam_soc_util_get_clk_lvl_override_low(void *data, u64 *val)
  685. {
  686. struct cam_hw_soc_info *soc_info = (struct cam_hw_soc_info *)data;
  687. *val = soc_info->clk_level_override_low;
  688. return 0;
  689. }
  690. DEFINE_SIMPLE_ATTRIBUTE(cam_soc_util_clk_lvl_control,
  691. cam_soc_util_get_clk_lvl_override, cam_soc_util_set_clk_lvl_override, "%08llu");
  692. DEFINE_SIMPLE_ATTRIBUTE(cam_soc_util_clk_lvl_control_low,
  693. cam_soc_util_get_clk_lvl_override_low, cam_soc_util_set_clk_lvl_override_low, "%08llu");
  694. /**
  695. * cam_soc_util_create_clk_lvl_debugfs()
  696. *
  697. * @brief: Creates debugfs files to view/control device clk rates
  698. *
  699. * @soc_info: Device soc information
  700. *
  701. * @return: Success or failure
  702. */
  703. static int cam_soc_util_create_clk_lvl_debugfs(struct cam_hw_soc_info *soc_info)
  704. {
  705. int rc = 0;
  706. struct dentry *dbgfileptr = NULL, *clkdirptr = NULL;
  707. if (!cam_debugfs_available())
  708. return 0;
  709. if (soc_info->dentry) {
  710. CAM_DBG(CAM_UTIL, "Debugfs entry for %s already exists",
  711. soc_info->dev_name);
  712. goto end;
  713. }
  714. rc = cam_debugfs_lookup_subdir(CAM_CLK_DIRNAME, &clkdirptr);
  715. if (rc) {
  716. rc = cam_debugfs_create_subdir(CAM_CLK_DIRNAME, &clkdirptr);
  717. if (rc) {
  718. CAM_ERR(CAM_UTIL, "DebugFS could not create clk directory!");
  719. rc = -ENOENT;
  720. goto end;
  721. }
  722. }
  723. dbgfileptr = debugfs_create_dir(soc_info->dev_name, clkdirptr);
  724. if (IS_ERR_OR_NULL(dbgfileptr)) {
  725. CAM_ERR(CAM_UTIL, "DebugFS could not create directory for dev:%s!",
  726. soc_info->dev_name);
  727. rc = -ENOENT;
  728. goto end;
  729. }
  730. /* Store parent inode for cleanup in caller */
  731. soc_info->dentry = dbgfileptr;
  732. dbgfileptr = debugfs_create_file("clk_lvl_options", 0444,
  733. soc_info->dentry, soc_info, &cam_soc_util_clk_lvl_options);
  734. dbgfileptr = debugfs_create_file("clk_lvl_control", 0644,
  735. soc_info->dentry, soc_info, &cam_soc_util_clk_lvl_control);
  736. dbgfileptr = debugfs_create_file("clk_lvl_control_low", 0644,
  737. soc_info->dentry, soc_info, &cam_soc_util_clk_lvl_control_low);
  738. rc = PTR_ERR_OR_ZERO(dbgfileptr);
  739. end:
  740. return rc;
  741. }
  742. int cam_soc_util_get_level_from_string(const char *string,
  743. enum cam_vote_level *level)
  744. {
  745. if (!level)
  746. return -EINVAL;
  747. if (!strcmp(string, "suspend")) {
  748. *level = CAM_SUSPEND_VOTE;
  749. } else if (!strcmp(string, "minsvs")) {
  750. *level = CAM_MINSVS_VOTE;
  751. } else if (!strcmp(string, "lowsvs")) {
  752. *level = CAM_LOWSVS_VOTE;
  753. } else if (!strcmp(string, "svs")) {
  754. *level = CAM_SVS_VOTE;
  755. } else if (!strcmp(string, "svs_l1")) {
  756. *level = CAM_SVSL1_VOTE;
  757. } else if (!strcmp(string, "nominal")) {
  758. *level = CAM_NOMINAL_VOTE;
  759. } else if (!strcmp(string, "nominal_l1")) {
  760. *level = CAM_NOMINALL1_VOTE;
  761. } else if (!strcmp(string, "turbo")) {
  762. *level = CAM_TURBO_VOTE;
  763. } else {
  764. CAM_ERR(CAM_UTIL, "Invalid string %s", string);
  765. return -EINVAL;
  766. }
  767. return 0;
  768. }
  769. /**
  770. * cam_soc_util_get_clk_level_to_apply()
  771. *
  772. * @brief: Get the clock level to apply. If the requested level
  773. * is not valid, bump the level to next available valid
  774. * level. If no higher level found, return failure.
  775. *
  776. * @soc_info: Device soc struct to be populated
  777. * @req_level: Requested level
  778. * @apply_level Level to apply
  779. *
  780. * @return: success or failure
  781. */
  782. static int cam_soc_util_get_clk_level_to_apply(
  783. struct cam_hw_soc_info *soc_info, enum cam_vote_level req_level,
  784. enum cam_vote_level *apply_level)
  785. {
  786. if (req_level >= CAM_MAX_VOTE) {
  787. CAM_ERR(CAM_UTIL, "Invalid clock level parameter %d",
  788. req_level);
  789. return -EINVAL;
  790. }
  791. if (soc_info->clk_level_valid[req_level] == true) {
  792. *apply_level = req_level;
  793. } else {
  794. int i;
  795. for (i = (req_level + 1); i < CAM_MAX_VOTE; i++)
  796. if (soc_info->clk_level_valid[i] == true) {
  797. *apply_level = i;
  798. break;
  799. }
  800. if (i == CAM_MAX_VOTE) {
  801. CAM_ERR(CAM_UTIL,
  802. "No valid clock level found to apply, req=%d",
  803. req_level);
  804. return -EINVAL;
  805. }
  806. }
  807. CAM_DBG(CAM_UTIL, "Req level %s, Applying %s",
  808. cam_soc_util_get_string_from_level(req_level),
  809. cam_soc_util_get_string_from_level(*apply_level));
  810. return 0;
  811. }
  812. int cam_soc_util_irq_enable(struct cam_hw_soc_info *soc_info)
  813. {
  814. if (!soc_info) {
  815. CAM_ERR(CAM_UTIL, "Invalid arguments");
  816. return -EINVAL;
  817. }
  818. if (soc_info->irq_num < 0) {
  819. CAM_ERR(CAM_UTIL, "No IRQ line available");
  820. return -ENODEV;
  821. }
  822. enable_irq(soc_info->irq_num);
  823. return 0;
  824. }
  825. int cam_soc_util_irq_disable(struct cam_hw_soc_info *soc_info)
  826. {
  827. if (!soc_info) {
  828. CAM_ERR(CAM_UTIL, "Invalid arguments");
  829. return -EINVAL;
  830. }
  831. if (soc_info->irq_num < 0) {
  832. CAM_ERR(CAM_UTIL, "No IRQ line available");
  833. return -ENODEV;
  834. }
  835. disable_irq(soc_info->irq_num);
  836. return 0;
  837. }
  838. long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info,
  839. uint32_t clk_index, unsigned long clk_rate)
  840. {
  841. if (!soc_info || (clk_index >= soc_info->num_clk) || (clk_rate == 0)) {
  842. CAM_ERR(CAM_UTIL, "Invalid input params %pK, %d %lu",
  843. soc_info, clk_index, clk_rate);
  844. return clk_rate;
  845. }
  846. return clk_round_rate(soc_info->clk[clk_index], clk_rate);
  847. }
  848. /**
  849. * cam_soc_util_set_clk_rate()
  850. *
  851. * @brief: Sets the given rate for the clk requested for
  852. *
  853. * @clk: Clock structure information for which rate is to be set
  854. * @clk_name: Name of the clock for which rate is being set
  855. * @clk_rate: Clock rate to be set
  856. * @shared_clk: Whether this is a shared clk
  857. * @is_src_clk: Whether this is source clk
  858. * @clk_id: Clock ID
  859. * @applied_clk_rate: Final clock rate set to the clk
  860. *
  861. * @return: Success or failure
  862. */
  863. static int cam_soc_util_set_clk_rate(struct cam_hw_soc_info *soc_info,
  864. struct clk *clk, const char *clk_name,
  865. int64_t clk_rate, bool shared_clk, bool is_src_clk, uint32_t clk_id,
  866. unsigned long *applied_clk_rate)
  867. {
  868. int rc = 0;
  869. long clk_rate_round = -1;
  870. bool set_rate = false;
  871. if (!clk_name) {
  872. CAM_ERR(CAM_UTIL, "Invalid input clk %pK clk_name %pK",
  873. clk, clk_name);
  874. return -EINVAL;
  875. }
  876. CAM_DBG(CAM_UTIL, "set %s, rate %lld", clk_name, clk_rate);
  877. if (!clk)
  878. return 0;
  879. if (clk_rate > 0) {
  880. clk_rate_round = clk_round_rate(clk, clk_rate);
  881. CAM_DBG(CAM_UTIL, "new_rate %ld", clk_rate_round);
  882. if (clk_rate_round < 0) {
  883. CAM_ERR(CAM_UTIL, "round failed for clock %s rc = %ld",
  884. clk_name, clk_rate_round);
  885. return clk_rate_round;
  886. }
  887. set_rate = true;
  888. } else if (clk_rate == INIT_RATE) {
  889. clk_rate_round = clk_get_rate(clk);
  890. CAM_DBG(CAM_UTIL, "init new_rate %ld", clk_rate_round);
  891. if (clk_rate_round == 0) {
  892. clk_rate_round = clk_round_rate(clk, 0);
  893. if (clk_rate_round <= 0) {
  894. CAM_ERR(CAM_UTIL, "round rate failed on %s",
  895. clk_name);
  896. return clk_rate_round;
  897. }
  898. }
  899. set_rate = true;
  900. }
  901. if (set_rate) {
  902. if (shared_clk) {
  903. CAM_DBG(CAM_UTIL,
  904. "Dev %s clk %s id %d Set Shared clk %ld",
  905. soc_info->dev_name, clk_name, clk_id,
  906. clk_rate_round);
  907. cam_soc_util_clk_wrapper_set_clk_rate(
  908. clk_id, soc_info, clk, clk_rate_round);
  909. } else {
  910. bool set_rate_finish = false;
  911. CAM_DBG(CAM_UTIL,
  912. "Dev %s clk %s clk_id %d src_idx %d src_clk_id %d",
  913. soc_info->dev_name, clk_name, clk_id,
  914. soc_info->src_clk_idx,
  915. (soc_info->src_clk_idx == -1) ? -1 :
  916. soc_info->clk_id[soc_info->src_clk_idx]);
  917. if (is_src_clk && soc_info->mmrm_handle &&
  918. !skip_mmrm_set_rate) {
  919. uint32_t idx = soc_info->src_clk_idx;
  920. uint32_t min_level = soc_info->lowest_clk_level;
  921. rc = cam_soc_util_set_rate_through_mmrm(
  922. soc_info->mmrm_handle,
  923. soc_info->is_nrt_dev,
  924. soc_info->clk_rate[min_level][idx],
  925. clk_rate_round, 1);
  926. if (rc) {
  927. CAM_ERR(CAM_UTIL,
  928. "set_rate through mmrm failed on %s clk_id %d, rate=%ld",
  929. clk_name, clk_id,
  930. clk_rate_round);
  931. return rc;
  932. }
  933. set_rate_finish = true;
  934. }
  935. if (!set_rate_finish) {
  936. rc = clk_set_rate(clk, clk_rate_round);
  937. if (rc) {
  938. CAM_ERR(CAM_UTIL, "set_rate failed on %s", clk_name);
  939. return rc;
  940. }
  941. }
  942. }
  943. }
  944. if (applied_clk_rate)
  945. *applied_clk_rate = clk_rate_round;
  946. return rc;
  947. }
  948. int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info, int cesta_client_idx,
  949. unsigned long clk_rate_high, unsigned long clk_rate_low)
  950. {
  951. int rc = 0;
  952. int i = 0;
  953. int32_t src_clk_idx;
  954. int32_t scl_clk_idx;
  955. struct clk *clk = NULL;
  956. int32_t apply_level;
  957. uint32_t clk_level_override_high = 0, clk_level_override_low = 0;
  958. if (!soc_info || (soc_info->src_clk_idx < 0) ||
  959. (soc_info->src_clk_idx >= CAM_SOC_MAX_CLK)) {
  960. CAM_ERR(CAM_UTIL, "Invalid src_clk_idx: %d",
  961. soc_info ? soc_info->src_clk_idx : -1);
  962. return -EINVAL;
  963. }
  964. src_clk_idx = soc_info->src_clk_idx;
  965. clk_level_override_high = soc_info->clk_level_override_high;
  966. clk_level_override_low = soc_info->clk_level_override_low;
  967. if (clk_level_override_high && clk_rate_high)
  968. clk_rate_high = soc_info->clk_rate[clk_level_override_high][src_clk_idx];
  969. if (clk_level_override_low && clk_rate_low)
  970. clk_rate_low = soc_info->clk_rate[clk_level_override_low][src_clk_idx];
  971. clk = soc_info->clk[src_clk_idx];
  972. rc = cam_soc_util_get_clk_level(soc_info, clk_rate_high, src_clk_idx,
  973. &apply_level);
  974. if (rc || (apply_level < 0) || (apply_level >= CAM_MAX_VOTE)) {
  975. CAM_ERR(CAM_UTIL,
  976. "set %s, rate %lld dev_name = %s apply level = %d",
  977. soc_info->clk_name[src_clk_idx], clk_rate_high,
  978. soc_info->dev_name, apply_level);
  979. return -EINVAL;
  980. }
  981. CAM_DBG(CAM_UTIL,
  982. "set %s, cesta_client_idx: %d rate [%ld %ld] dev_name = %s apply level = %d",
  983. soc_info->clk_name[src_clk_idx], cesta_client_idx, clk_rate_high, clk_rate_low,
  984. soc_info->dev_name, apply_level);
  985. if ((soc_info->cam_cx_ipeak_enable) && (clk_rate_high > 0)) {
  986. cam_cx_ipeak_update_vote_cx_ipeak(soc_info,
  987. apply_level);
  988. }
  989. if (soc_info->is_clk_drv_en && CAM_IS_VALID_CESTA_IDX(cesta_client_idx)) {
  990. rc = cam_soc_util_set_cesta_clk_rate(soc_info, cesta_client_idx, clk_rate_high,
  991. clk_rate_low,
  992. &soc_info->applied_src_clk_rates.hw_client[cesta_client_idx].high,
  993. &soc_info->applied_src_clk_rates.hw_client[cesta_client_idx].low);
  994. if (rc) {
  995. CAM_ERR(CAM_UTIL,
  996. "Failed in setting cesta clk rates[high low]:[%ld %ld] client_idx:%d rc:%d",
  997. clk_rate_high, clk_rate_low, cesta_client_idx, rc);
  998. return rc;
  999. }
  1000. goto end;
  1001. }
  1002. rc = cam_soc_util_set_clk_rate(soc_info, clk,
  1003. soc_info->clk_name[src_clk_idx], clk_rate_high,
  1004. CAM_IS_BIT_SET(soc_info->shared_clk_mask, src_clk_idx),
  1005. true, soc_info->clk_id[src_clk_idx],
  1006. &soc_info->applied_src_clk_rates.sw_client);
  1007. if (rc) {
  1008. CAM_ERR(CAM_UTIL,
  1009. "SET_RATE Failed: src clk: %s, rate %lld, dev_name = %s rc: %d",
  1010. soc_info->clk_name[src_clk_idx], clk_rate_high,
  1011. soc_info->dev_name, rc);
  1012. return rc;
  1013. }
  1014. /* set clk rate for scalable clk if available */
  1015. for (i = 0; i < soc_info->scl_clk_count; i++) {
  1016. scl_clk_idx = soc_info->scl_clk_idx[i];
  1017. if (scl_clk_idx < 0) {
  1018. CAM_DBG(CAM_UTIL, "Scl clk index invalid");
  1019. continue;
  1020. }
  1021. clk = soc_info->clk[scl_clk_idx];
  1022. rc = cam_soc_util_set_clk_rate(soc_info, clk,
  1023. soc_info->clk_name[scl_clk_idx],
  1024. soc_info->clk_rate[apply_level][scl_clk_idx],
  1025. CAM_IS_BIT_SET(soc_info->shared_clk_mask, scl_clk_idx),
  1026. false, soc_info->clk_id[scl_clk_idx],
  1027. NULL);
  1028. if (rc) {
  1029. CAM_WARN(CAM_UTIL,
  1030. "SET_RATE Failed: scl clk: %s, rate %d dev_name = %s, rc: %d",
  1031. soc_info->clk_name[scl_clk_idx],
  1032. soc_info->clk_rate[apply_level][scl_clk_idx],
  1033. soc_info->dev_name, rc);
  1034. }
  1035. }
  1036. end:
  1037. return 0;
  1038. }
  1039. int cam_soc_util_put_optional_clk(struct cam_hw_soc_info *soc_info,
  1040. int32_t clk_indx)
  1041. {
  1042. if (clk_indx < 0) {
  1043. CAM_ERR(CAM_UTIL, "Invalid params clk %d", clk_indx);
  1044. return -EINVAL;
  1045. }
  1046. if (CAM_IS_BIT_SET(soc_info->optional_shared_clk_mask, clk_indx))
  1047. cam_soc_util_clk_wrapper_unregister_entry(
  1048. soc_info->optional_clk_id[clk_indx], soc_info);
  1049. clk_put(soc_info->optional_clk[clk_indx]);
  1050. soc_info->optional_clk[clk_indx] = NULL;
  1051. return 0;
  1052. }
  1053. static struct clk *cam_soc_util_option_clk_get(struct device_node *np,
  1054. int index, uint32_t *clk_id)
  1055. {
  1056. struct of_phandle_args clkspec;
  1057. struct clk *clk;
  1058. int rc;
  1059. if (index < 0)
  1060. return ERR_PTR(-EINVAL);
  1061. rc = of_parse_phandle_with_args(np, "clocks-option", "#clock-cells",
  1062. index, &clkspec);
  1063. if (rc)
  1064. return ERR_PTR(rc);
  1065. clk = of_clk_get_from_provider(&clkspec);
  1066. *clk_id = clkspec.args[0];
  1067. of_node_put(clkspec.np);
  1068. return clk;
  1069. }
  1070. int cam_soc_util_get_option_clk_by_name(struct cam_hw_soc_info *soc_info,
  1071. const char *clk_name, int32_t *clk_index)
  1072. {
  1073. int index = 0;
  1074. int rc = 0;
  1075. struct device_node *of_node = NULL;
  1076. uint32_t shared_clk_val;
  1077. if (!soc_info || !clk_name || !clk_index) {
  1078. CAM_ERR(CAM_UTIL,
  1079. "Invalid params soc_info %pK clk_name %s clk_index %pK",
  1080. soc_info, clk_name, clk_index);
  1081. return -EINVAL;
  1082. }
  1083. of_node = soc_info->dev->of_node;
  1084. index = of_property_match_string(of_node, "clock-names-option",
  1085. clk_name);
  1086. if (index < 0) {
  1087. CAM_DBG(CAM_UTIL, "No clk data for %s", clk_name);
  1088. *clk_index = -1;
  1089. return -EINVAL;
  1090. }
  1091. if (index >= CAM_SOC_MAX_OPT_CLK) {
  1092. CAM_ERR(CAM_UTIL, "Insufficient optional clk entries %d %d",
  1093. index, CAM_SOC_MAX_OPT_CLK);
  1094. return -EINVAL;
  1095. }
  1096. of_property_read_string_index(of_node, "clock-names-option",
  1097. index, &(soc_info->optional_clk_name[index]));
  1098. soc_info->optional_clk[index] = cam_soc_util_option_clk_get(of_node,
  1099. index, &soc_info->optional_clk_id[index]);
  1100. if (IS_ERR(soc_info->optional_clk[index])) {
  1101. CAM_ERR(CAM_UTIL, "No clk named %s found. Dev %s", clk_name,
  1102. soc_info->dev_name);
  1103. *clk_index = -1;
  1104. return -EFAULT;
  1105. }
  1106. *clk_index = index;
  1107. rc = of_property_read_u32_index(of_node, "clock-rates-option",
  1108. index, &soc_info->optional_clk_rate[index]);
  1109. if (rc) {
  1110. CAM_ERR(CAM_UTIL,
  1111. "Error reading clock-rates clk_name %s index %d",
  1112. clk_name, index);
  1113. goto error;
  1114. }
  1115. /*
  1116. * Option clocks are assumed to be available to single Device here.
  1117. * Hence use INIT_RATE instead of NO_SET_RATE.
  1118. */
  1119. soc_info->optional_clk_rate[index] =
  1120. (soc_info->optional_clk_rate[index] == 0) ?
  1121. (int32_t)INIT_RATE : soc_info->optional_clk_rate[index];
  1122. CAM_DBG(CAM_UTIL, "clk_name %s index %d clk_rate %d",
  1123. clk_name, *clk_index, soc_info->optional_clk_rate[index]);
  1124. rc = of_property_read_u32_index(of_node, "shared-clks-option",
  1125. index, &shared_clk_val);
  1126. if (rc) {
  1127. CAM_DBG(CAM_UTIL, "Not shared clk %s index %d",
  1128. clk_name, index);
  1129. } else if (shared_clk_val > 1) {
  1130. CAM_WARN(CAM_UTIL, "Invalid shared clk val %d", shared_clk_val);
  1131. } else {
  1132. CAM_DBG(CAM_UTIL,
  1133. "Dev %s shared clk %s index %d, clk id %d, shared_clk_val %d",
  1134. soc_info->dev_name, clk_name, index,
  1135. soc_info->optional_clk_id[index], shared_clk_val);
  1136. if (shared_clk_val) {
  1137. CAM_SET_BIT(soc_info->optional_shared_clk_mask, index);
  1138. /* Create a wrapper entry if this is a shared clock */
  1139. CAM_DBG(CAM_UTIL,
  1140. "Dev %s, clk %s, id %d register wrapper entry for shared clk",
  1141. soc_info->dev_name,
  1142. soc_info->optional_clk_name[index],
  1143. soc_info->optional_clk_id[index]);
  1144. rc = cam_soc_util_clk_wrapper_register_entry(
  1145. soc_info->optional_clk_id[index],
  1146. soc_info->optional_clk[index], false,
  1147. soc_info,
  1148. soc_info->optional_clk_rate[index],
  1149. soc_info->optional_clk_name[index]);
  1150. if (rc) {
  1151. CAM_ERR(CAM_UTIL,
  1152. "Failed in registering shared clk Dev %s id %d",
  1153. soc_info->dev_name,
  1154. soc_info->optional_clk_id[index]);
  1155. goto error;
  1156. }
  1157. }
  1158. }
  1159. return 0;
  1160. error:
  1161. clk_put(soc_info->optional_clk[index]);
  1162. soc_info->optional_clk_rate[index] = 0;
  1163. soc_info->optional_clk[index] = NULL;
  1164. *clk_index = -1;
  1165. return rc;
  1166. }
  1167. int cam_soc_util_clk_enable(struct cam_hw_soc_info *soc_info, int cesta_client_idx,
  1168. bool optional_clk, int32_t clk_idx, int32_t apply_level)
  1169. {
  1170. int rc = 0;
  1171. struct clk *clk;
  1172. const char *clk_name;
  1173. unsigned long clk_rate;
  1174. uint32_t shared_clk_mask;
  1175. uint32_t clk_id;
  1176. bool is_src_clk = false;
  1177. if (!soc_info || (clk_idx < 0) || (apply_level >= CAM_MAX_VOTE)) {
  1178. CAM_ERR(CAM_UTIL, "Invalid param %d %d", clk_idx, apply_level);
  1179. return -EINVAL;
  1180. }
  1181. if (optional_clk) {
  1182. clk = soc_info->optional_clk[clk_idx];
  1183. clk_name = soc_info->optional_clk_name[clk_idx];
  1184. clk_rate = (apply_level == -1) ?
  1185. 0 : soc_info->optional_clk_rate[clk_idx];
  1186. shared_clk_mask = soc_info->optional_shared_clk_mask;
  1187. clk_id = soc_info->optional_clk_id[clk_idx];
  1188. } else {
  1189. clk = soc_info->clk[clk_idx];
  1190. clk_name = soc_info->clk_name[clk_idx];
  1191. clk_rate = (apply_level == -1) ?
  1192. 0 : soc_info->clk_rate[apply_level][clk_idx];
  1193. shared_clk_mask = soc_info->shared_clk_mask;
  1194. clk_id = soc_info->clk_id[clk_idx];
  1195. if (clk_idx == soc_info->src_clk_idx)
  1196. is_src_clk = true;
  1197. }
  1198. if (!clk)
  1199. return 0;
  1200. if (is_src_clk && soc_info->is_clk_drv_en && CAM_IS_VALID_CESTA_IDX(cesta_client_idx)) {
  1201. rc = cam_soc_util_set_cesta_clk_rate(soc_info, cesta_client_idx, clk_rate, clk_rate,
  1202. &soc_info->applied_src_clk_rates.hw_client[cesta_client_idx].high,
  1203. &soc_info->applied_src_clk_rates.hw_client[cesta_client_idx].low);
  1204. if (rc) {
  1205. CAM_ERR(CAM_UTIL,
  1206. "[%s] Failed in setting cesta clk rates[high low]:[%ld %ld] client_idx:%d rc:%d",
  1207. soc_info->dev_name, clk_rate, clk_rate, cesta_client_idx, rc);
  1208. return rc;
  1209. }
  1210. rc = cam_soc_util_cesta_channel_switch(cesta_client_idx, soc_info->dev_name);
  1211. if (rc) {
  1212. CAM_ERR(CAM_UTIL,
  1213. "[%s] Failed to apply power states for cesta client:%d rc:%d",
  1214. soc_info->dev_name, cesta_client_idx, rc);
  1215. return rc;
  1216. }
  1217. } else {
  1218. rc = cam_soc_util_set_clk_rate(soc_info, clk, clk_name, clk_rate,
  1219. CAM_IS_BIT_SET(shared_clk_mask, clk_idx), is_src_clk, clk_id,
  1220. &soc_info->applied_src_clk_rates.sw_client);
  1221. if (rc) {
  1222. CAM_ERR(CAM_UTIL, "[%s] Failed in setting clk rate %ld rc:%d",
  1223. soc_info->dev_name, clk_rate, rc);
  1224. return rc;
  1225. }
  1226. }
  1227. CAM_DBG(CAM_UTIL, "[%s] : clk enable %s", soc_info->dev_name, clk_name);
  1228. rc = clk_prepare_enable(clk);
  1229. if (rc) {
  1230. CAM_ERR(CAM_UTIL, "enable failed for %s: rc(%d)", clk_name, rc);
  1231. return rc;
  1232. }
  1233. return rc;
  1234. }
  1235. int cam_soc_util_clk_disable(struct cam_hw_soc_info *soc_info, int cesta_client_idx,
  1236. bool optional_clk, int32_t clk_idx)
  1237. {
  1238. int rc = 0;
  1239. struct clk *clk;
  1240. const char *clk_name;
  1241. uint32_t shared_clk_mask;
  1242. uint32_t clk_id;
  1243. if (!soc_info || (clk_idx < 0)) {
  1244. CAM_ERR(CAM_UTIL, "Invalid param %d", clk_idx);
  1245. return -EINVAL;
  1246. }
  1247. if (optional_clk) {
  1248. clk = soc_info->optional_clk[clk_idx];
  1249. clk_name = soc_info->optional_clk_name[clk_idx];
  1250. shared_clk_mask = soc_info->optional_shared_clk_mask;
  1251. clk_id = soc_info->optional_clk_id[clk_idx];
  1252. } else {
  1253. clk = soc_info->clk[clk_idx];
  1254. clk_name = soc_info->clk_name[clk_idx];
  1255. shared_clk_mask = soc_info->shared_clk_mask;
  1256. clk_id = soc_info->clk_id[clk_idx];
  1257. }
  1258. CAM_DBG(CAM_UTIL, "disable %s", clk_name);
  1259. if (!clk)
  1260. return 0;
  1261. clk_disable_unprepare(clk);
  1262. if ((clk_idx == soc_info->src_clk_idx) && soc_info->is_clk_drv_en &&
  1263. CAM_IS_VALID_CESTA_IDX(cesta_client_idx)) {
  1264. rc = cam_soc_util_set_cesta_clk_rate(soc_info, cesta_client_idx, 0, 0,
  1265. &soc_info->applied_src_clk_rates.hw_client[cesta_client_idx].high,
  1266. &soc_info->applied_src_clk_rates.hw_client[cesta_client_idx].low);
  1267. if (rc) {
  1268. CAM_ERR(CAM_UTIL,
  1269. "Failed in setting cesta clk rates[high low]:[0 0] client_idx:%d rc:%d",
  1270. cesta_client_idx, rc);
  1271. return rc;
  1272. }
  1273. rc = cam_soc_util_cesta_channel_switch(cesta_client_idx, soc_info->dev_name);
  1274. if (rc) {
  1275. CAM_ERR(CAM_CSIPHY,
  1276. "Failed to apply power states for cesta_client_idx:%d rc:%d",
  1277. cesta_client_idx, rc);
  1278. return rc;
  1279. }
  1280. } else {
  1281. if (CAM_IS_BIT_SET(shared_clk_mask, clk_idx)) {
  1282. CAM_DBG(CAM_UTIL,
  1283. "Dev %s clk %s Disabling Shared clk, set 0 rate",
  1284. soc_info->dev_name, clk_name);
  1285. cam_soc_util_clk_wrapper_set_clk_rate(clk_id, soc_info, clk, 0);
  1286. } else if (soc_info->mmrm_handle && (!skip_mmrm_set_rate) &&
  1287. (soc_info->src_clk_idx == clk_idx)) {
  1288. CAM_DBG(CAM_UTIL, "Dev %s Disabling %s clk, set 0 rate",
  1289. soc_info->dev_name, clk_name);
  1290. cam_soc_util_set_rate_through_mmrm(
  1291. soc_info->mmrm_handle,
  1292. soc_info->is_nrt_dev,
  1293. 0, 0, 1);
  1294. }
  1295. }
  1296. return 0;
  1297. }
  1298. /**
  1299. * cam_soc_util_clk_enable_default()
  1300. *
  1301. * @brief: This function enables the default clocks present
  1302. * in soc_info
  1303. *
  1304. * @soc_info: Device soc struct to be populated
  1305. * @cesta_client_idx: CESTA Client idx for hw client based src clocks
  1306. * @clk_level: Clk level to apply while enabling
  1307. *
  1308. * @return: success or failure
  1309. */
  1310. int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info,
  1311. int cesta_client_idx, enum cam_vote_level clk_level)
  1312. {
  1313. int i, rc = 0;
  1314. enum cam_vote_level apply_level;
  1315. if ((soc_info->num_clk == 0) ||
  1316. (soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
  1317. CAM_ERR(CAM_UTIL, "Invalid number of clock %d",
  1318. soc_info->num_clk);
  1319. return -EINVAL;
  1320. }
  1321. rc = cam_soc_util_get_clk_level_to_apply(soc_info, clk_level,
  1322. &apply_level);
  1323. if (rc) {
  1324. CAM_ERR(CAM_UTIL, "[%s] : failed to get level clk_level=%d, rc=%d",
  1325. soc_info->dev_name, clk_level, rc);
  1326. return rc;
  1327. }
  1328. if (soc_info->cam_cx_ipeak_enable)
  1329. cam_cx_ipeak_update_vote_cx_ipeak(soc_info, apply_level);
  1330. CAM_DBG(CAM_UTIL, "Dev[%s] : cesta client %d, request level %s, apply level %s",
  1331. soc_info->dev_name, cesta_client_idx,
  1332. cam_soc_util_get_string_from_level(clk_level),
  1333. cam_soc_util_get_string_from_level(apply_level));
  1334. memset(&soc_info->applied_src_clk_rates, 0, sizeof(struct cam_soc_util_clk_rates));
  1335. for (i = 0; i < soc_info->num_clk; i++) {
  1336. rc = cam_soc_util_clk_enable(soc_info, cesta_client_idx, false, i, apply_level);
  1337. if (rc) {
  1338. CAM_ERR(CAM_UTIL,
  1339. "[%s] : failed to enable clk apply_level=%d, rc=%d, cesta_client_idx=%d",
  1340. soc_info->dev_name, apply_level, rc, cesta_client_idx);
  1341. goto clk_disable;
  1342. }
  1343. if (soc_info->cam_cx_ipeak_enable)
  1344. CAM_DBG(CAM_UTIL,
  1345. "dev name = %s clk name = %s idx = %d apply_level = %d clc idx = %d",
  1346. soc_info->dev_name, soc_info->clk_name[i], i, apply_level, i);
  1347. }
  1348. return rc;
  1349. clk_disable:
  1350. if (soc_info->cam_cx_ipeak_enable)
  1351. cam_cx_ipeak_update_vote_cx_ipeak(soc_info, 0);
  1352. for (i--; i >= 0; i--) {
  1353. cam_soc_util_clk_disable(soc_info, cesta_client_idx, false, i);
  1354. }
  1355. return rc;
  1356. }
  1357. /**
  1358. * cam_soc_util_clk_disable_default()
  1359. *
  1360. * @brief: This function disables the default clocks present
  1361. * in soc_info
  1362. *
  1363. * @soc_info: device soc struct to be populated
  1364. * @cesta_client_idx: CESTA Client idx for hw client based src clocks
  1365. *
  1366. * @return: success or failure
  1367. */
  1368. void cam_soc_util_clk_disable_default(struct cam_hw_soc_info *soc_info,
  1369. int cesta_client_idx)
  1370. {
  1371. int i;
  1372. if (soc_info->num_clk == 0)
  1373. return;
  1374. if (soc_info->cam_cx_ipeak_enable)
  1375. cam_cx_ipeak_unvote_cx_ipeak(soc_info);
  1376. for (i = soc_info->num_clk - 1; i >= 0; i--)
  1377. cam_soc_util_clk_disable(soc_info, cesta_client_idx, false, i);
  1378. }
  1379. /**
  1380. * cam_soc_util_get_dt_clk_info()
  1381. *
  1382. * @brief: Parse the DT and populate the Clock properties
  1383. *
  1384. * @soc_info: device soc struct to be populated
  1385. * @src_clk_str name of src clock that has rate control
  1386. *
  1387. * @return: success or failure
  1388. */
  1389. static int cam_soc_util_get_dt_clk_info(struct cam_hw_soc_info *soc_info)
  1390. {
  1391. struct device_node *of_node = NULL;
  1392. int count;
  1393. int num_clk_rates, num_clk_levels;
  1394. int i, j, rc;
  1395. int32_t num_clk_level_strings;
  1396. const char *src_clk_str = NULL;
  1397. const char *scl_clk_str = NULL;
  1398. const char *clk_control_debugfs = NULL;
  1399. const char *clk_cntl_lvl_string = NULL;
  1400. enum cam_vote_level level;
  1401. int shared_clk_cnt;
  1402. struct of_phandle_args clk_args = {0};
  1403. if (!soc_info || !soc_info->dev)
  1404. return -EINVAL;
  1405. of_node = soc_info->dev->of_node;
  1406. if (!of_property_read_bool(of_node, "use-shared-clk")) {
  1407. CAM_DBG(CAM_UTIL, "No shared clk parameter defined");
  1408. soc_info->use_shared_clk = false;
  1409. } else {
  1410. soc_info->use_shared_clk = true;
  1411. }
  1412. count = of_property_count_strings(of_node, "clock-names");
  1413. CAM_DBG(CAM_UTIL, "E: dev_name = %s count = %d",
  1414. soc_info->dev_name, count);
  1415. if (count > CAM_SOC_MAX_CLK) {
  1416. CAM_ERR(CAM_UTIL, "invalid count of clocks, count=%d", count);
  1417. rc = -EINVAL;
  1418. return rc;
  1419. }
  1420. if (count <= 0) {
  1421. CAM_DBG(CAM_UTIL, "No clock-names found");
  1422. count = 0;
  1423. soc_info->num_clk = count;
  1424. return 0;
  1425. }
  1426. soc_info->num_clk = count;
  1427. for (i = 0; i < count; i++) {
  1428. rc = of_property_read_string_index(of_node, "clock-names",
  1429. i, &(soc_info->clk_name[i]));
  1430. CAM_DBG(CAM_UTIL, "clock-names[%d] = %s",
  1431. i, soc_info->clk_name[i]);
  1432. if (rc) {
  1433. CAM_ERR(CAM_UTIL,
  1434. "i= %d count= %d reading clock-names failed",
  1435. i, count);
  1436. return rc;
  1437. }
  1438. }
  1439. num_clk_rates = of_property_count_u32_elems(of_node, "clock-rates");
  1440. if (num_clk_rates <= 0) {
  1441. CAM_ERR(CAM_UTIL, "reading clock-rates count failed");
  1442. return -EINVAL;
  1443. }
  1444. if ((num_clk_rates % soc_info->num_clk) != 0) {
  1445. CAM_ERR(CAM_UTIL,
  1446. "mismatch clk/rates, No of clocks=%d, No of rates=%d",
  1447. soc_info->num_clk, num_clk_rates);
  1448. return -EINVAL;
  1449. }
  1450. num_clk_levels = (num_clk_rates / soc_info->num_clk);
  1451. num_clk_level_strings = of_property_count_strings(of_node,
  1452. "clock-cntl-level");
  1453. if (num_clk_level_strings != num_clk_levels) {
  1454. CAM_ERR(CAM_UTIL,
  1455. "Mismatch No of levels=%d, No of level string=%d",
  1456. num_clk_levels, num_clk_level_strings);
  1457. return -EINVAL;
  1458. }
  1459. soc_info->lowest_clk_level = CAM_TURBO_VOTE;
  1460. for (i = 0; i < num_clk_levels; i++) {
  1461. rc = of_property_read_string_index(of_node,
  1462. "clock-cntl-level", i, &clk_cntl_lvl_string);
  1463. if (rc) {
  1464. CAM_ERR(CAM_UTIL,
  1465. "Error reading clock-cntl-level, rc=%d", rc);
  1466. return rc;
  1467. }
  1468. rc = cam_soc_util_get_level_from_string(clk_cntl_lvl_string,
  1469. &level);
  1470. if (rc)
  1471. return rc;
  1472. CAM_DBG(CAM_UTIL,
  1473. "[%d] : %s %d", i, clk_cntl_lvl_string, level);
  1474. soc_info->clk_level_valid[level] = true;
  1475. for (j = 0; j < soc_info->num_clk; j++) {
  1476. rc = of_property_read_u32_index(of_node, "clock-rates",
  1477. ((i * soc_info->num_clk) + j),
  1478. &soc_info->clk_rate[level][j]);
  1479. if (rc) {
  1480. CAM_ERR(CAM_UTIL,
  1481. "Error reading clock-rates, rc=%d",
  1482. rc);
  1483. return rc;
  1484. }
  1485. soc_info->clk_rate[level][j] =
  1486. (soc_info->clk_rate[level][j] == 0) ?
  1487. (int32_t)NO_SET_RATE :
  1488. soc_info->clk_rate[level][j];
  1489. CAM_DBG(CAM_UTIL, "soc_info->clk_rate[%d][%d] = %d",
  1490. level, j,
  1491. soc_info->clk_rate[level][j]);
  1492. }
  1493. if ((level > CAM_MINSVS_VOTE) &&
  1494. (level < soc_info->lowest_clk_level))
  1495. soc_info->lowest_clk_level = level;
  1496. }
  1497. soc_info->src_clk_idx = -1;
  1498. rc = of_property_read_string_index(of_node, "src-clock-name", 0,
  1499. &src_clk_str);
  1500. if (rc || !src_clk_str) {
  1501. CAM_DBG(CAM_UTIL, "No src_clk_str found");
  1502. rc = 0;
  1503. goto end;
  1504. }
  1505. for (i = 0; i < soc_info->num_clk; i++) {
  1506. if (strcmp(soc_info->clk_name[i], src_clk_str) == 0) {
  1507. soc_info->src_clk_idx = i;
  1508. CAM_DBG(CAM_UTIL, "src clock = %s, index = %d",
  1509. src_clk_str, i);
  1510. }
  1511. rc = of_parse_phandle_with_args(of_node, "clocks",
  1512. "#clock-cells", i, &clk_args);
  1513. if (rc) {
  1514. CAM_ERR(CAM_CPAS,
  1515. "failed to clock info rc=%d", rc);
  1516. rc = -EINVAL;
  1517. goto end;
  1518. }
  1519. soc_info->clk_id[i] = clk_args.args[0];
  1520. of_node_put(clk_args.np);
  1521. CAM_DBG(CAM_UTIL, "Dev %s clk %s id %d",
  1522. soc_info->dev_name, soc_info->clk_name[i],
  1523. soc_info->clk_id[i]);
  1524. }
  1525. CAM_DBG(CAM_UTIL, "Dev %s src_clk_idx %d, lowest_clk_level %d",
  1526. soc_info->dev_name, soc_info->src_clk_idx,
  1527. soc_info->lowest_clk_level);
  1528. soc_info->shared_clk_mask = 0;
  1529. shared_clk_cnt = of_property_count_u32_elems(of_node, "shared-clks");
  1530. if (shared_clk_cnt <= 0) {
  1531. CAM_DBG(CAM_UTIL, "Dev %s, no shared clks", soc_info->dev_name);
  1532. } else if (shared_clk_cnt != count) {
  1533. CAM_ERR(CAM_UTIL, "Dev %s, incorrect shared clock count %d %d",
  1534. soc_info->dev_name, shared_clk_cnt, count);
  1535. rc = -EINVAL;
  1536. goto end;
  1537. } else {
  1538. uint32_t shared_clk_val;
  1539. for (i = 0; i < shared_clk_cnt; i++) {
  1540. rc = of_property_read_u32_index(of_node,
  1541. "shared-clks", i, &shared_clk_val);
  1542. if (rc || (shared_clk_val > 1)) {
  1543. CAM_ERR(CAM_UTIL,
  1544. "Incorrect shared clk info at %d, val=%d, count=%d",
  1545. i, shared_clk_val, shared_clk_cnt);
  1546. rc = -EINVAL;
  1547. goto end;
  1548. }
  1549. if (shared_clk_val)
  1550. CAM_SET_BIT(soc_info->shared_clk_mask, i);
  1551. }
  1552. CAM_DBG(CAM_UTIL, "Dev %s shared clk mask 0x%x",
  1553. soc_info->dev_name, soc_info->shared_clk_mask);
  1554. }
  1555. /* scalable clk info parsing */
  1556. soc_info->scl_clk_count = 0;
  1557. soc_info->scl_clk_count = of_property_count_strings(of_node,
  1558. "scl-clk-names");
  1559. if ((soc_info->scl_clk_count <= 0) ||
  1560. (soc_info->scl_clk_count > CAM_SOC_MAX_CLK)) {
  1561. if (soc_info->scl_clk_count == -EINVAL) {
  1562. CAM_DBG(CAM_UTIL, "scl_clk_name prop not avialable");
  1563. } else if ((soc_info->scl_clk_count == -ENODATA) ||
  1564. (soc_info->scl_clk_count > CAM_SOC_MAX_CLK)) {
  1565. CAM_ERR(CAM_UTIL, "Invalid scl_clk_count: %d",
  1566. soc_info->scl_clk_count);
  1567. return -EINVAL;
  1568. }
  1569. CAM_DBG(CAM_UTIL, "Invalid scl_clk count: %d",
  1570. soc_info->scl_clk_count);
  1571. soc_info->scl_clk_count = -1;
  1572. } else {
  1573. CAM_DBG(CAM_UTIL, "No of scalable clocks: %d",
  1574. soc_info->scl_clk_count);
  1575. for (i = 0; i < soc_info->scl_clk_count; i++) {
  1576. rc = of_property_read_string_index(of_node,
  1577. "scl-clk-names", i,
  1578. (const char **)&scl_clk_str);
  1579. if (rc || !scl_clk_str) {
  1580. CAM_WARN(CAM_UTIL, "scl_clk_str is NULL");
  1581. soc_info->scl_clk_idx[i] = -1;
  1582. continue;
  1583. }
  1584. for (j = 0; j < soc_info->num_clk; j++) {
  1585. if (strnstr(scl_clk_str, soc_info->clk_name[j],
  1586. strlen(scl_clk_str))) {
  1587. soc_info->scl_clk_idx[i] = j;
  1588. CAM_DBG(CAM_UTIL,
  1589. "scl clock = %s, index = %d",
  1590. scl_clk_str, j);
  1591. break;
  1592. }
  1593. }
  1594. }
  1595. }
  1596. rc = of_property_read_string_index(of_node,
  1597. "clock-control-debugfs", 0, &clk_control_debugfs);
  1598. if (rc || !clk_control_debugfs) {
  1599. CAM_DBG(CAM_UTIL, "No clock_control_debugfs property found");
  1600. rc = 0;
  1601. goto end;
  1602. }
  1603. if (strcmp("true", clk_control_debugfs) == 0)
  1604. soc_info->clk_control_enable = true;
  1605. CAM_DBG(CAM_UTIL, "X: dev_name = %s count = %d",
  1606. soc_info->dev_name, count);
  1607. end:
  1608. return rc;
  1609. }
  1610. int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info,
  1611. int cesta_client_idx, enum cam_vote_level clk_level_high,
  1612. enum cam_vote_level clk_level_low, bool do_not_set_src_clk)
  1613. {
  1614. int i, rc = 0;
  1615. enum cam_vote_level apply_level_high;
  1616. enum cam_vote_level apply_level_low = CAM_LOWSVS_VOTE;
  1617. unsigned long applied_clk_rate;
  1618. if ((soc_info->num_clk == 0) ||
  1619. (soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
  1620. CAM_ERR(CAM_UTIL, "Invalid number of clock %d", soc_info->num_clk);
  1621. return -EINVAL;
  1622. }
  1623. rc = cam_soc_util_get_clk_level_to_apply(soc_info, clk_level_high,
  1624. &apply_level_high);
  1625. if (rc) {
  1626. CAM_ERR(CAM_UTIL, "[%s] : failed to get level clk_level_high=%d, rc=%d",
  1627. soc_info->dev_name, clk_level_high, rc);
  1628. return rc;
  1629. }
  1630. if (soc_info->is_clk_drv_en && CAM_IS_VALID_CESTA_IDX(cesta_client_idx)) {
  1631. rc = cam_soc_util_get_clk_level_to_apply(soc_info, clk_level_low,
  1632. &apply_level_low);
  1633. if (rc) {
  1634. CAM_ERR(CAM_UTIL, "[%s] : failed to get level clk_level_low=%d, rc=%d",
  1635. soc_info->dev_name, clk_level_low, rc);
  1636. return rc;
  1637. }
  1638. }
  1639. if (soc_info->cam_cx_ipeak_enable)
  1640. cam_cx_ipeak_update_vote_cx_ipeak(soc_info, apply_level_high);
  1641. for (i = 0; i < soc_info->num_clk; i++) {
  1642. if (do_not_set_src_clk && (i == soc_info->src_clk_idx)) {
  1643. CAM_DBG(CAM_UTIL, "Skipping set rate for src clk %s",
  1644. soc_info->clk_name[i]);
  1645. continue;
  1646. }
  1647. if (soc_info->is_clk_drv_en && CAM_IS_VALID_CESTA_IDX(cesta_client_idx) &&
  1648. (i == soc_info->src_clk_idx)) {
  1649. rc = cam_soc_util_set_cesta_clk_rate(soc_info, cesta_client_idx,
  1650. soc_info->clk_rate[apply_level_high][i],
  1651. soc_info->clk_rate[apply_level_low][i],
  1652. &soc_info->applied_src_clk_rates.hw_client[cesta_client_idx].high,
  1653. &soc_info->applied_src_clk_rates.hw_client[cesta_client_idx].low);
  1654. if (rc) {
  1655. CAM_ERR(CAM_UTIL,
  1656. "Failed to set the req clk level[high low]: [%s %s] cesta_client_idx: %d",
  1657. cam_soc_util_get_string_from_level(apply_level_high),
  1658. cam_soc_util_get_string_from_level(apply_level_low),
  1659. cesta_client_idx);
  1660. break;
  1661. }
  1662. continue;
  1663. }
  1664. CAM_DBG(CAM_UTIL, "Set rate for clk %s rate %d", soc_info->clk_name[i],
  1665. soc_info->clk_rate[apply_level_high][i]);
  1666. rc = cam_soc_util_set_clk_rate(soc_info, soc_info->clk[i],
  1667. soc_info->clk_name[i],
  1668. soc_info->clk_rate[apply_level_high][i],
  1669. CAM_IS_BIT_SET(soc_info->shared_clk_mask, i),
  1670. (i == soc_info->src_clk_idx) ? true : false,
  1671. soc_info->clk_id[i],
  1672. &applied_clk_rate);
  1673. if (rc < 0) {
  1674. CAM_DBG(CAM_UTIL,
  1675. "dev name = %s clk_name = %s idx = %d apply_level = %s",
  1676. soc_info->dev_name, soc_info->clk_name[i],
  1677. i, cam_soc_util_get_string_from_level(apply_level_high));
  1678. if (soc_info->cam_cx_ipeak_enable)
  1679. cam_cx_ipeak_update_vote_cx_ipeak(soc_info, 0);
  1680. break;
  1681. }
  1682. if (i == soc_info->src_clk_idx)
  1683. soc_info->applied_src_clk_rates.sw_client = applied_clk_rate;
  1684. }
  1685. return rc;
  1686. };
  1687. static int cam_soc_util_get_dt_gpio_req_tbl(struct device_node *of_node,
  1688. struct cam_soc_gpio_data *gconf, uint16_t *gpio_array,
  1689. uint16_t gpio_array_size)
  1690. {
  1691. int32_t rc = 0, i = 0;
  1692. uint32_t count = 0;
  1693. uint32_t *val_array = NULL;
  1694. if (!of_get_property(of_node, "gpio-req-tbl-num", &count))
  1695. return 0;
  1696. count /= sizeof(uint32_t);
  1697. if (!count) {
  1698. CAM_ERR(CAM_UTIL, "gpio-req-tbl-num 0");
  1699. return 0;
  1700. }
  1701. val_array = kcalloc(count, sizeof(uint32_t), GFP_KERNEL);
  1702. if (!val_array)
  1703. return -ENOMEM;
  1704. gconf->cam_gpio_req_tbl = kcalloc(count, sizeof(struct gpio),
  1705. GFP_KERNEL);
  1706. if (!gconf->cam_gpio_req_tbl) {
  1707. rc = -ENOMEM;
  1708. goto free_val_array;
  1709. }
  1710. gconf->cam_gpio_req_tbl_size = count;
  1711. rc = of_property_read_u32_array(of_node, "gpio-req-tbl-num",
  1712. val_array, count);
  1713. if (rc) {
  1714. CAM_ERR(CAM_UTIL, "failed in reading gpio-req-tbl-num, rc = %d",
  1715. rc);
  1716. goto free_gpio_req_tbl;
  1717. }
  1718. for (i = 0; i < count; i++) {
  1719. if (val_array[i] >= gpio_array_size) {
  1720. CAM_ERR(CAM_UTIL, "gpio req tbl index %d invalid",
  1721. val_array[i]);
  1722. goto free_gpio_req_tbl;
  1723. }
  1724. gconf->cam_gpio_req_tbl[i].gpio = gpio_array[val_array[i]];
  1725. CAM_DBG(CAM_UTIL, "cam_gpio_req_tbl[%d].gpio = %d", i,
  1726. gconf->cam_gpio_req_tbl[i].gpio);
  1727. }
  1728. rc = of_property_read_u32_array(of_node, "gpio-req-tbl-flags",
  1729. val_array, count);
  1730. if (rc) {
  1731. CAM_ERR(CAM_UTIL, "Failed in gpio-req-tbl-flags, rc %d", rc);
  1732. goto free_gpio_req_tbl;
  1733. }
  1734. for (i = 0; i < count; i++) {
  1735. gconf->cam_gpio_req_tbl[i].flags = val_array[i];
  1736. CAM_DBG(CAM_UTIL, "cam_gpio_req_tbl[%d].flags = %ld", i,
  1737. gconf->cam_gpio_req_tbl[i].flags);
  1738. }
  1739. for (i = 0; i < count; i++) {
  1740. rc = of_property_read_string_index(of_node,
  1741. "gpio-req-tbl-label", i,
  1742. &gconf->cam_gpio_req_tbl[i].label);
  1743. if (rc) {
  1744. CAM_ERR(CAM_UTIL, "Failed rc %d", rc);
  1745. goto free_gpio_req_tbl;
  1746. }
  1747. CAM_DBG(CAM_UTIL, "cam_gpio_req_tbl[%d].label = %s", i,
  1748. gconf->cam_gpio_req_tbl[i].label);
  1749. }
  1750. kfree(val_array);
  1751. return rc;
  1752. free_gpio_req_tbl:
  1753. kfree(gconf->cam_gpio_req_tbl);
  1754. free_val_array:
  1755. kfree(val_array);
  1756. gconf->cam_gpio_req_tbl_size = 0;
  1757. return rc;
  1758. }
  1759. static int cam_soc_util_get_gpio_info(struct cam_hw_soc_info *soc_info)
  1760. {
  1761. int32_t rc = 0, i = 0;
  1762. uint16_t *gpio_array = NULL;
  1763. int16_t gpio_array_size = 0;
  1764. struct cam_soc_gpio_data *gconf = NULL;
  1765. struct device_node *of_node = NULL;
  1766. if (!soc_info || !soc_info->dev)
  1767. return -EINVAL;
  1768. of_node = soc_info->dev->of_node;
  1769. /* Validate input parameters */
  1770. if (!of_node) {
  1771. CAM_ERR(CAM_UTIL, "Invalid param of_node");
  1772. return -EINVAL;
  1773. }
  1774. gpio_array_size = of_gpio_count(of_node);
  1775. if (gpio_array_size <= 0)
  1776. return 0;
  1777. CAM_DBG(CAM_UTIL, "gpio count %d", gpio_array_size);
  1778. gpio_array = kcalloc(gpio_array_size, sizeof(uint16_t), GFP_KERNEL);
  1779. if (!gpio_array)
  1780. goto free_gpio_conf;
  1781. for (i = 0; i < gpio_array_size; i++) {
  1782. gpio_array[i] = of_get_gpio(of_node, i);
  1783. CAM_DBG(CAM_UTIL, "gpio_array[%d] = %d", i, gpio_array[i]);
  1784. }
  1785. gconf = kzalloc(sizeof(*gconf), GFP_KERNEL);
  1786. if (!gconf)
  1787. return -ENOMEM;
  1788. rc = cam_soc_util_get_dt_gpio_req_tbl(of_node, gconf, gpio_array,
  1789. gpio_array_size);
  1790. if (rc) {
  1791. CAM_ERR(CAM_UTIL, "failed in msm_camera_get_dt_gpio_req_tbl");
  1792. goto free_gpio_array;
  1793. }
  1794. gconf->cam_gpio_common_tbl = kcalloc(gpio_array_size,
  1795. sizeof(struct gpio), GFP_KERNEL);
  1796. if (!gconf->cam_gpio_common_tbl) {
  1797. rc = -ENOMEM;
  1798. goto free_gpio_array;
  1799. }
  1800. for (i = 0; i < gpio_array_size; i++)
  1801. gconf->cam_gpio_common_tbl[i].gpio = gpio_array[i];
  1802. gconf->cam_gpio_common_tbl_size = gpio_array_size;
  1803. soc_info->gpio_data = gconf;
  1804. kfree(gpio_array);
  1805. return rc;
  1806. free_gpio_array:
  1807. kfree(gpio_array);
  1808. free_gpio_conf:
  1809. kfree(gconf);
  1810. soc_info->gpio_data = NULL;
  1811. return rc;
  1812. }
  1813. static int cam_soc_util_request_gpio_table(
  1814. struct cam_hw_soc_info *soc_info, bool gpio_en)
  1815. {
  1816. int rc = 0, i = 0;
  1817. uint8_t size = 0;
  1818. struct cam_soc_gpio_data *gpio_conf =
  1819. soc_info->gpio_data;
  1820. struct gpio *gpio_tbl = NULL;
  1821. if (!gpio_conf) {
  1822. CAM_DBG(CAM_UTIL, "No GPIO entry");
  1823. return 0;
  1824. }
  1825. if (gpio_conf->cam_gpio_common_tbl_size <= 0) {
  1826. CAM_ERR(CAM_UTIL, "GPIO table size is invalid");
  1827. return -EINVAL;
  1828. }
  1829. size = gpio_conf->cam_gpio_req_tbl_size;
  1830. gpio_tbl = gpio_conf->cam_gpio_req_tbl;
  1831. if (!gpio_tbl || !size) {
  1832. CAM_ERR(CAM_UTIL, "Invalid gpio_tbl %pK / size %d",
  1833. gpio_tbl, size);
  1834. return -EINVAL;
  1835. }
  1836. for (i = 0; i < size; i++) {
  1837. CAM_DBG(CAM_UTIL, "i=%d, gpio=%d dir=%ld", i,
  1838. gpio_tbl[i].gpio, gpio_tbl[i].flags);
  1839. }
  1840. if (gpio_en) {
  1841. for (i = 0; i < size; i++) {
  1842. rc = gpio_request_one(gpio_tbl[i].gpio,
  1843. gpio_tbl[i].flags, gpio_tbl[i].label);
  1844. if (rc) {
  1845. /*
  1846. * After GPIO request fails, contine to
  1847. * apply new gpios, outout a error message
  1848. * for driver bringup debug
  1849. */
  1850. CAM_ERR(CAM_UTIL, "gpio %d:%s request fails",
  1851. gpio_tbl[i].gpio, gpio_tbl[i].label);
  1852. }
  1853. }
  1854. } else {
  1855. gpio_free_array(gpio_tbl, size);
  1856. }
  1857. return rc;
  1858. }
  1859. static int cam_soc_util_get_dt_regulator_info
  1860. (struct cam_hw_soc_info *soc_info)
  1861. {
  1862. int rc = 0, count = 0, i = 0;
  1863. struct device_node *of_node = NULL;
  1864. if (!soc_info || !soc_info->dev) {
  1865. CAM_ERR(CAM_UTIL, "Invalid parameters");
  1866. return -EINVAL;
  1867. }
  1868. of_node = soc_info->dev->of_node;
  1869. soc_info->num_rgltr = 0;
  1870. count = of_property_count_strings(of_node, "regulator-names");
  1871. if (count != -EINVAL) {
  1872. if (count <= 0) {
  1873. CAM_ERR(CAM_UTIL, "no regulators found");
  1874. count = 0;
  1875. return -EINVAL;
  1876. }
  1877. soc_info->num_rgltr = count;
  1878. } else {
  1879. CAM_DBG(CAM_UTIL, "No regulators node found");
  1880. return 0;
  1881. }
  1882. if (soc_info->num_rgltr > CAM_SOC_MAX_REGULATOR) {
  1883. CAM_ERR(CAM_UTIL, "Invalid regulator count:%d",
  1884. soc_info->num_rgltr);
  1885. return -EINVAL;
  1886. }
  1887. for (i = 0; i < soc_info->num_rgltr; i++) {
  1888. rc = of_property_read_string_index(of_node,
  1889. "regulator-names", i, &soc_info->rgltr_name[i]);
  1890. CAM_DBG(CAM_UTIL, "rgltr_name[%d] = %s",
  1891. i, soc_info->rgltr_name[i]);
  1892. if (rc) {
  1893. CAM_ERR(CAM_UTIL, "no regulator resource at cnt=%d", i);
  1894. return -ENODEV;
  1895. }
  1896. }
  1897. if (!of_property_read_bool(of_node, "rgltr-cntrl-support")) {
  1898. CAM_DBG(CAM_UTIL, "No regulator control parameter defined");
  1899. soc_info->rgltr_ctrl_support = false;
  1900. return 0;
  1901. }
  1902. soc_info->rgltr_ctrl_support = true;
  1903. rc = of_property_read_u32_array(of_node, "rgltr-min-voltage",
  1904. soc_info->rgltr_min_volt, soc_info->num_rgltr);
  1905. if (rc) {
  1906. CAM_ERR(CAM_UTIL, "No minimum volatage value found, rc=%d", rc);
  1907. return -EINVAL;
  1908. }
  1909. rc = of_property_read_u32_array(of_node, "rgltr-max-voltage",
  1910. soc_info->rgltr_max_volt, soc_info->num_rgltr);
  1911. if (rc) {
  1912. CAM_ERR(CAM_UTIL, "No maximum volatage value found, rc=%d", rc);
  1913. return -EINVAL;
  1914. }
  1915. rc = of_property_read_u32_array(of_node, "rgltr-load-current",
  1916. soc_info->rgltr_op_mode, soc_info->num_rgltr);
  1917. if (rc) {
  1918. CAM_ERR(CAM_UTIL, "No Load curent found rc=%d", rc);
  1919. return -EINVAL;
  1920. }
  1921. return rc;
  1922. }
  1923. #ifdef CONFIG_CAM_PRESIL
  1924. static uint32_t next_dummy_irq_line_num = 0x000f;
  1925. struct resource dummy_irq_line[512];
  1926. #endif
  1927. int cam_soc_util_get_dt_properties(struct cam_hw_soc_info *soc_info)
  1928. {
  1929. struct device_node *of_node = NULL;
  1930. int count = 0, i = 0, rc = 0;
  1931. if (!soc_info || !soc_info->dev)
  1932. return -EINVAL;
  1933. of_node = soc_info->dev->of_node;
  1934. rc = of_property_read_u32(of_node, "cell-index", &soc_info->index);
  1935. if (rc) {
  1936. CAM_ERR(CAM_UTIL, "device %s failed to read cell-index",
  1937. soc_info->dev_name);
  1938. return rc;
  1939. }
  1940. count = of_property_count_strings(of_node, "reg-names");
  1941. if (count <= 0) {
  1942. CAM_DBG(CAM_UTIL, "no reg-names found for: %s",
  1943. soc_info->dev_name);
  1944. count = 0;
  1945. }
  1946. soc_info->num_mem_block = count;
  1947. for (i = 0; i < soc_info->num_mem_block; i++) {
  1948. rc = of_property_read_string_index(of_node, "reg-names", i,
  1949. &soc_info->mem_block_name[i]);
  1950. if (rc) {
  1951. CAM_ERR(CAM_UTIL, "failed to read reg-names at %d", i);
  1952. return rc;
  1953. }
  1954. soc_info->mem_block[i] =
  1955. platform_get_resource_byname(soc_info->pdev,
  1956. IORESOURCE_MEM, soc_info->mem_block_name[i]);
  1957. if (!soc_info->mem_block[i]) {
  1958. CAM_ERR(CAM_UTIL, "no mem resource by name %s",
  1959. soc_info->mem_block_name[i]);
  1960. rc = -ENODEV;
  1961. return rc;
  1962. }
  1963. }
  1964. rc = of_property_read_string(of_node, "label", &soc_info->label_name);
  1965. if (rc)
  1966. CAM_DBG(CAM_UTIL, "Label is not available in the node: %d", rc);
  1967. if (soc_info->num_mem_block > 0) {
  1968. rc = of_property_read_u32_array(of_node, "reg-cam-base",
  1969. soc_info->mem_block_cam_base, soc_info->num_mem_block);
  1970. if (rc) {
  1971. CAM_ERR(CAM_UTIL, "Error reading register offsets");
  1972. return rc;
  1973. }
  1974. }
  1975. rc = of_property_read_string_index(of_node, "interrupt-names", 0,
  1976. &soc_info->irq_name);
  1977. if (rc) {
  1978. CAM_DBG(CAM_UTIL, "No interrupt line preset for: %s",
  1979. soc_info->dev_name);
  1980. rc = 0;
  1981. } else {
  1982. rc = cam_compat_util_get_irq(soc_info);
  1983. if (rc < 0) {
  1984. CAM_ERR(CAM_UTIL, "get irq resource failed: %d", rc);
  1985. #ifndef CONFIG_CAM_PRESIL
  1986. return rc;
  1987. #else
  1988. /* Pre-sil for new devices not present on old */
  1989. soc_info->irq_line =
  1990. &dummy_irq_line[next_dummy_irq_line_num++];
  1991. CAM_DBG(CAM_PRESIL, "interrupt line for dev %s irq name %s number %d",
  1992. soc_info->dev_name, soc_info->irq_name,
  1993. soc_info->irq_line->start);
  1994. #endif
  1995. }
  1996. }
  1997. rc = of_property_read_string_index(of_node, "compatible", 0,
  1998. (const char **)&soc_info->compatible);
  1999. if (rc) {
  2000. CAM_DBG(CAM_UTIL, "No compatible string present for: %s",
  2001. soc_info->dev_name);
  2002. rc = 0;
  2003. }
  2004. soc_info->is_nrt_dev = false;
  2005. if (of_property_read_bool(of_node, "nrt-device"))
  2006. soc_info->is_nrt_dev = true;
  2007. CAM_DBG(CAM_UTIL, "Dev %s, nrt_dev %d",
  2008. soc_info->dev_name, soc_info->is_nrt_dev);
  2009. rc = cam_soc_util_get_dt_regulator_info(soc_info);
  2010. if (rc)
  2011. return rc;
  2012. rc = cam_soc_util_get_dt_clk_info(soc_info);
  2013. if (rc)
  2014. return rc;
  2015. rc = cam_soc_util_get_gpio_info(soc_info);
  2016. if (rc)
  2017. return rc;
  2018. if (of_find_property(of_node, "qcom,cam-cx-ipeak", NULL))
  2019. rc = cam_cx_ipeak_register_cx_ipeak(soc_info);
  2020. return rc;
  2021. }
  2022. /**
  2023. * cam_soc_util_get_regulator()
  2024. *
  2025. * @brief: Get regulator resource named vdd
  2026. *
  2027. * @dev: Device associated with regulator
  2028. * @reg: Return pointer to be filled with regulator on success
  2029. * @rgltr_name: Name of regulator to get
  2030. *
  2031. * @return: 0 for Success, negative value for failure
  2032. */
  2033. static int cam_soc_util_get_regulator(struct device *dev,
  2034. struct regulator **reg, const char *rgltr_name)
  2035. {
  2036. int rc = 0;
  2037. *reg = regulator_get(dev, rgltr_name);
  2038. if (IS_ERR_OR_NULL(*reg)) {
  2039. rc = PTR_ERR(*reg);
  2040. rc = rc ? rc : -EINVAL;
  2041. CAM_ERR(CAM_UTIL, "Regulator %s get failed %d", rgltr_name, rc);
  2042. *reg = NULL;
  2043. }
  2044. return rc;
  2045. }
  2046. int cam_soc_util_regulator_disable(struct regulator *rgltr,
  2047. const char *rgltr_name, uint32_t rgltr_min_volt,
  2048. uint32_t rgltr_max_volt, uint32_t rgltr_op_mode,
  2049. uint32_t rgltr_delay_ms)
  2050. {
  2051. int32_t rc = 0;
  2052. if (!rgltr) {
  2053. CAM_ERR(CAM_UTIL, "Invalid NULL parameter");
  2054. return -EINVAL;
  2055. }
  2056. rc = regulator_disable(rgltr);
  2057. if (rc) {
  2058. CAM_ERR(CAM_UTIL, "%s regulator disable failed", rgltr_name);
  2059. return rc;
  2060. }
  2061. if (rgltr_delay_ms > 20)
  2062. msleep(rgltr_delay_ms);
  2063. else if (rgltr_delay_ms)
  2064. usleep_range(rgltr_delay_ms * 1000,
  2065. (rgltr_delay_ms * 1000) + 1000);
  2066. if (regulator_count_voltages(rgltr) > 0) {
  2067. regulator_set_load(rgltr, 0);
  2068. regulator_set_voltage(rgltr, 0, rgltr_max_volt);
  2069. }
  2070. return rc;
  2071. }
  2072. int cam_soc_util_regulator_enable(struct regulator *rgltr,
  2073. const char *rgltr_name,
  2074. uint32_t rgltr_min_volt, uint32_t rgltr_max_volt,
  2075. uint32_t rgltr_op_mode, uint32_t rgltr_delay)
  2076. {
  2077. int32_t rc = 0;
  2078. if (!rgltr) {
  2079. CAM_ERR(CAM_UTIL, "Invalid NULL parameter");
  2080. return -EINVAL;
  2081. }
  2082. if (regulator_count_voltages(rgltr) > 0) {
  2083. CAM_DBG(CAM_UTIL, "[%s] voltage min=%d, max=%d",
  2084. rgltr_name, rgltr_min_volt, rgltr_max_volt);
  2085. rc = regulator_set_voltage(
  2086. rgltr, rgltr_min_volt, rgltr_max_volt);
  2087. if (rc) {
  2088. CAM_ERR(CAM_UTIL, "%s set voltage failed", rgltr_name);
  2089. return rc;
  2090. }
  2091. rc = regulator_set_load(rgltr, rgltr_op_mode);
  2092. if (rc) {
  2093. CAM_ERR(CAM_UTIL, "%s set optimum mode failed",
  2094. rgltr_name);
  2095. return rc;
  2096. }
  2097. }
  2098. rc = regulator_enable(rgltr);
  2099. if (rc) {
  2100. CAM_ERR(CAM_UTIL, "%s regulator_enable failed", rgltr_name);
  2101. return rc;
  2102. }
  2103. if (rgltr_delay > 20)
  2104. msleep(rgltr_delay);
  2105. else if (rgltr_delay)
  2106. usleep_range(rgltr_delay * 1000,
  2107. (rgltr_delay * 1000) + 1000);
  2108. return rc;
  2109. }
  2110. int cam_soc_util_select_pinctrl_state(struct cam_hw_soc_info *soc_info,
  2111. int pctrl_idx, bool active)
  2112. {
  2113. int rc = 0;
  2114. struct cam_soc_pinctrl_info *pctrl_info = &soc_info->pinctrl_info;
  2115. if (pctrl_idx >= CAM_SOC_MAX_PINCTRL_MAP) {
  2116. CAM_ERR(CAM_UTIL, "Invalid Map idx: %d max supported: %d",
  2117. pctrl_idx, CAM_SOC_MAX_PINCTRL_MAP);
  2118. return -EINVAL;
  2119. }
  2120. if (pctrl_info->pctrl_state[pctrl_idx].gpio_state_active &&
  2121. active &&
  2122. !pctrl_info->pctrl_state[pctrl_idx].is_active) {
  2123. rc = pinctrl_select_state(pctrl_info->pinctrl,
  2124. pctrl_info->pctrl_state[pctrl_idx].gpio_state_active);
  2125. if (rc)
  2126. CAM_ERR(CAM_UTIL,
  2127. "Pinctrl active state transition failed: rc: %d",
  2128. rc);
  2129. else {
  2130. pctrl_info->pctrl_state[pctrl_idx].is_active = true;
  2131. CAM_DBG(CAM_UTIL, "Pctrl_idx: %d is in active state",
  2132. pctrl_idx);
  2133. }
  2134. }
  2135. if (pctrl_info->pctrl_state[pctrl_idx].gpio_state_suspend &&
  2136. !active &&
  2137. pctrl_info->pctrl_state[pctrl_idx].is_active) {
  2138. rc = pinctrl_select_state(pctrl_info->pinctrl,
  2139. pctrl_info->pctrl_state[pctrl_idx].gpio_state_suspend);
  2140. if (rc)
  2141. CAM_ERR(CAM_UTIL,
  2142. "Pinctrl suspend state transition failed: rc: %d",
  2143. rc);
  2144. else {
  2145. pctrl_info->pctrl_state[pctrl_idx].is_active = false;
  2146. CAM_DBG(CAM_UTIL, "Pctrl_idx: %d is in suspend state",
  2147. pctrl_idx);
  2148. }
  2149. }
  2150. return rc;
  2151. }
  2152. static int cam_soc_util_request_pinctrl(
  2153. struct cam_hw_soc_info *soc_info)
  2154. {
  2155. struct cam_soc_pinctrl_info *device_pctrl = &soc_info->pinctrl_info;
  2156. struct device *dev = soc_info->dev;
  2157. struct device_node *of_node = dev->of_node;
  2158. uint32_t i = 0;
  2159. int rc = 0;
  2160. const char *name;
  2161. uint32_t idx;
  2162. char pctrl_active[50];
  2163. char pctrl_suspend[50];
  2164. int32_t num_of_map_idx = 0;
  2165. int32_t num_of_string = 0;
  2166. device_pctrl->pinctrl = devm_pinctrl_get(dev);
  2167. if (IS_ERR_OR_NULL(device_pctrl->pinctrl)) {
  2168. CAM_DBG(CAM_UTIL, "Pinctrl not available");
  2169. device_pctrl->pinctrl = NULL;
  2170. return 0;
  2171. }
  2172. num_of_map_idx = of_property_count_u32_elems(
  2173. of_node, "pctrl-idx-mapping");
  2174. if (num_of_map_idx <= 0) {
  2175. CAM_ERR(CAM_UTIL,
  2176. "Reading pctrl-idx-mapping failed");
  2177. return -EINVAL;
  2178. }
  2179. num_of_string = of_property_count_strings(
  2180. of_node, "pctrl-map-names");
  2181. if (num_of_string <= 0) {
  2182. CAM_ERR(CAM_UTIL, "no pinctrl-mapping found for: %s",
  2183. soc_info->dev_name);
  2184. device_pctrl->pinctrl = NULL;
  2185. return -EINVAL;
  2186. }
  2187. if (num_of_map_idx != num_of_string) {
  2188. CAM_ERR(CAM_UTIL,
  2189. "Incorrect inputs mapping-idx count: %d mapping-names: %d",
  2190. num_of_map_idx, num_of_string);
  2191. device_pctrl->pinctrl = NULL;
  2192. return -EINVAL;
  2193. }
  2194. if (num_of_map_idx > CAM_SOC_MAX_PINCTRL_MAP) {
  2195. CAM_ERR(CAM_UTIL, "Invalid mapping %u max supported: %d",
  2196. num_of_map_idx, CAM_SOC_MAX_PINCTRL_MAP);
  2197. return -EINVAL;
  2198. }
  2199. for (i = 0; i < num_of_map_idx; i++) {
  2200. of_property_read_u32_index(of_node,
  2201. "pctrl-idx-mapping", i, &idx);
  2202. if (idx >= CAM_SOC_MAX_PINCTRL_MAP) {
  2203. CAM_ERR(CAM_UTIL, "Invalid Index: %d max supported: %d",
  2204. idx, CAM_SOC_MAX_PINCTRL_MAP);
  2205. return -EINVAL;
  2206. }
  2207. rc = of_property_read_string_index(
  2208. of_node, "pctrl-map-names", i, &name);
  2209. if (rc) {
  2210. CAM_ERR(CAM_UTIL,
  2211. "failed to read pinctrl-mapping at %d", i);
  2212. return rc;
  2213. }
  2214. snprintf(pctrl_active, sizeof(pctrl_active),
  2215. "%s%s", name, "_active");
  2216. CAM_DBG(CAM_UTIL, "pctrl_active at index: %d name: %s",
  2217. i, pctrl_active);
  2218. snprintf(pctrl_suspend, sizeof(pctrl_suspend),
  2219. "%s%s", name, "_suspend");
  2220. CAM_DBG(CAM_UTIL, "pctrl_suspend at index: %d name: %s",
  2221. i, pctrl_suspend);
  2222. device_pctrl->pctrl_state[idx].gpio_state_active =
  2223. pinctrl_lookup_state(device_pctrl->pinctrl,
  2224. pctrl_active);
  2225. if (IS_ERR_OR_NULL(
  2226. device_pctrl->pctrl_state[idx].gpio_state_active)) {
  2227. CAM_ERR(CAM_UTIL,
  2228. "Failed to get the active state pinctrl handle");
  2229. device_pctrl->pctrl_state[idx].gpio_state_active =
  2230. NULL;
  2231. return -EINVAL;
  2232. }
  2233. device_pctrl->pctrl_state[idx].gpio_state_suspend =
  2234. pinctrl_lookup_state(device_pctrl->pinctrl,
  2235. pctrl_suspend);
  2236. if (IS_ERR_OR_NULL(
  2237. device_pctrl->pctrl_state[idx].gpio_state_suspend)) {
  2238. CAM_ERR(CAM_UTIL,
  2239. "Failed to get the active state pinctrl handle");
  2240. device_pctrl->pctrl_state[idx].gpio_state_suspend = NULL;
  2241. return -EINVAL;
  2242. }
  2243. }
  2244. return 0;
  2245. }
  2246. static void cam_soc_util_release_pinctrl(struct cam_hw_soc_info *soc_info)
  2247. {
  2248. if (soc_info->pinctrl_info.pinctrl)
  2249. devm_pinctrl_put(soc_info->pinctrl_info.pinctrl);
  2250. }
  2251. static void cam_soc_util_regulator_disable_default(
  2252. struct cam_hw_soc_info *soc_info)
  2253. {
  2254. int j = 0;
  2255. uint32_t num_rgltr = soc_info->num_rgltr;
  2256. for (j = num_rgltr-1; j >= 0; j--) {
  2257. if (soc_info->rgltr_ctrl_support == true) {
  2258. cam_soc_util_regulator_disable(soc_info->rgltr[j],
  2259. soc_info->rgltr_name[j],
  2260. soc_info->rgltr_min_volt[j],
  2261. soc_info->rgltr_max_volt[j],
  2262. soc_info->rgltr_op_mode[j],
  2263. soc_info->rgltr_delay[j]);
  2264. } else {
  2265. if (soc_info->rgltr[j])
  2266. regulator_disable(soc_info->rgltr[j]);
  2267. }
  2268. }
  2269. }
  2270. static int cam_soc_util_regulator_enable_default(
  2271. struct cam_hw_soc_info *soc_info)
  2272. {
  2273. int j = 0, rc = 0;
  2274. uint32_t num_rgltr = soc_info->num_rgltr;
  2275. if (num_rgltr > CAM_SOC_MAX_REGULATOR) {
  2276. CAM_ERR(CAM_UTIL,
  2277. "%s has invalid regulator number %d",
  2278. soc_info->dev_name, num_rgltr);
  2279. return -EINVAL;
  2280. }
  2281. for (j = 0; j < num_rgltr; j++) {
  2282. CAM_DBG(CAM_UTIL, "[%s] : start regulator %s enable, rgltr_ctrl_support %d",
  2283. soc_info->dev_name, soc_info->rgltr_name[j], soc_info->rgltr_ctrl_support);
  2284. if (soc_info->rgltr_ctrl_support == true) {
  2285. rc = cam_soc_util_regulator_enable(soc_info->rgltr[j],
  2286. soc_info->rgltr_name[j],
  2287. soc_info->rgltr_min_volt[j],
  2288. soc_info->rgltr_max_volt[j],
  2289. soc_info->rgltr_op_mode[j],
  2290. soc_info->rgltr_delay[j]);
  2291. } else {
  2292. if (soc_info->rgltr[j])
  2293. rc = regulator_enable(soc_info->rgltr[j]);
  2294. }
  2295. if (rc) {
  2296. CAM_ERR(CAM_UTIL, "%s enable failed",
  2297. soc_info->rgltr_name[j]);
  2298. goto disable_rgltr;
  2299. }
  2300. }
  2301. return rc;
  2302. disable_rgltr:
  2303. for (j--; j >= 0; j--) {
  2304. if (soc_info->rgltr_ctrl_support == true) {
  2305. cam_soc_util_regulator_disable(soc_info->rgltr[j],
  2306. soc_info->rgltr_name[j],
  2307. soc_info->rgltr_min_volt[j],
  2308. soc_info->rgltr_max_volt[j],
  2309. soc_info->rgltr_op_mode[j],
  2310. soc_info->rgltr_delay[j]);
  2311. } else {
  2312. if (soc_info->rgltr[j])
  2313. regulator_disable(soc_info->rgltr[j]);
  2314. }
  2315. }
  2316. return rc;
  2317. }
  2318. static bool cam_soc_util_is_presil_address_space(unsigned long mem_block_start)
  2319. {
  2320. if(mem_block_start >= CAM_SS_START_PRESIL && mem_block_start < CAM_SS_START)
  2321. return true;
  2322. return false;
  2323. }
  2324. #ifndef CONFIG_CAM_PRESIL
  2325. void __iomem * cam_soc_util_get_mem_base(
  2326. unsigned long mem_block_start,
  2327. unsigned long mem_block_size,
  2328. const char *mem_block_name,
  2329. uint32_t reserve_mem)
  2330. {
  2331. void __iomem * mem_base;
  2332. if (reserve_mem) {
  2333. if (!request_mem_region(mem_block_start,
  2334. mem_block_size,
  2335. mem_block_name)) {
  2336. CAM_ERR(CAM_UTIL,
  2337. "Error Mem region request Failed:%s",
  2338. mem_block_name);
  2339. return NULL;
  2340. }
  2341. }
  2342. mem_base = ioremap(mem_block_start, mem_block_size);
  2343. if (!mem_base) {
  2344. CAM_ERR(CAM_UTIL, "get mem base failed");
  2345. }
  2346. return mem_base;
  2347. }
  2348. int cam_soc_util_request_irq(struct device *dev,
  2349. unsigned int irq_line_start,
  2350. irq_handler_t handler,
  2351. unsigned long irqflags,
  2352. const char *irq_name,
  2353. void *irq_data,
  2354. unsigned long mem_block_start)
  2355. {
  2356. int rc;
  2357. rc = devm_request_irq(dev,
  2358. irq_line_start,
  2359. handler,
  2360. IRQF_TRIGGER_RISING,
  2361. irq_name,
  2362. irq_data);
  2363. if (rc) {
  2364. CAM_ERR(CAM_UTIL, "irq request fail rc %d", rc);
  2365. return -EBUSY;
  2366. }
  2367. disable_irq(irq_line_start);
  2368. return rc;
  2369. }
  2370. #else
  2371. void __iomem * cam_soc_util_get_mem_base(
  2372. unsigned long mem_block_start,
  2373. unsigned long mem_block_size,
  2374. const char *mem_block_name,
  2375. uint32_t reserve_mem)
  2376. {
  2377. void __iomem * mem_base;
  2378. if(cam_soc_util_is_presil_address_space(mem_block_start))
  2379. mem_base = (void __iomem *)mem_block_start;
  2380. else {
  2381. if (reserve_mem) {
  2382. if (!request_mem_region(mem_block_start,
  2383. mem_block_size,
  2384. mem_block_name)) {
  2385. CAM_ERR(CAM_UTIL,
  2386. "Error Mem region request Failed:%s",
  2387. mem_block_name);
  2388. return NULL;
  2389. }
  2390. }
  2391. mem_base = ioremap(mem_block_start, mem_block_size);
  2392. }
  2393. if (!mem_base) {
  2394. CAM_ERR(CAM_UTIL, "get mem base failed");
  2395. }
  2396. return mem_base;
  2397. }
  2398. int cam_soc_util_request_irq(struct device *dev,
  2399. unsigned int irq_line_start,
  2400. irq_handler_t handler,
  2401. unsigned long irqflags,
  2402. const char *irq_name,
  2403. void *irq_data,
  2404. unsigned long mem_block_start)
  2405. {
  2406. int rc;
  2407. if(cam_soc_util_is_presil_address_space(mem_block_start)) {
  2408. rc = devm_request_irq(dev,
  2409. irq_line_start,
  2410. handler,
  2411. irqflags,
  2412. irq_name,
  2413. irq_data);
  2414. if (rc) {
  2415. CAM_ERR(CAM_UTIL, "presil irq request fail");
  2416. return -EBUSY;
  2417. }
  2418. disable_irq(irq_line_start);
  2419. rc = !(cam_presil_subscribe_device_irq(irq_line_start,
  2420. handler, irq_data, irq_name));
  2421. CAM_DBG(CAM_PRESIL, "Subscribe presil IRQ: rc=%d NUM=%d Name=%s handler=0x%x",
  2422. rc, irq_line_start, irq_name, handler);
  2423. if (rc) {
  2424. CAM_ERR(CAM_UTIL, "presil irq request fail");
  2425. return -EBUSY;
  2426. }
  2427. } else {
  2428. rc = devm_request_irq(dev,
  2429. irq_line_start,
  2430. handler,
  2431. irqflags,
  2432. irq_name,
  2433. irq_data);
  2434. if (rc) {
  2435. CAM_ERR(CAM_UTIL, "irq request fail");
  2436. return -EBUSY;
  2437. }
  2438. disable_irq(irq_line_start);
  2439. CAM_INFO(CAM_UTIL, "Subscribe for non-presil IRQ success");
  2440. }
  2441. CAM_INFO(CAM_UTIL, "returning IRQ for mem_block_start 0x%0x rc %d",
  2442. mem_block_start, rc);
  2443. return rc;
  2444. }
  2445. #endif
  2446. int cam_soc_util_request_platform_resource(
  2447. struct cam_hw_soc_info *soc_info,
  2448. irq_handler_t handler, void *irq_data)
  2449. {
  2450. int i = 0, rc = 0;
  2451. if (!soc_info || !soc_info->dev) {
  2452. CAM_ERR(CAM_UTIL, "Invalid parameters");
  2453. return -EINVAL;
  2454. }
  2455. for (i = 0; i < soc_info->num_mem_block; i++) {
  2456. soc_info->reg_map[i].mem_base = cam_soc_util_get_mem_base(
  2457. soc_info->mem_block[i]->start,
  2458. resource_size(soc_info->mem_block[i]),
  2459. soc_info->mem_block_name[i],
  2460. soc_info->reserve_mem);
  2461. if (!soc_info->reg_map[i].mem_base) {
  2462. CAM_ERR(CAM_UTIL, "i= %d base NULL", i);
  2463. rc = -ENOMEM;
  2464. goto unmap_base;
  2465. }
  2466. soc_info->reg_map[i].mem_cam_base =
  2467. soc_info->mem_block_cam_base[i];
  2468. soc_info->reg_map[i].size =
  2469. resource_size(soc_info->mem_block[i]);
  2470. soc_info->num_reg_map++;
  2471. }
  2472. for (i = 0; i < soc_info->num_rgltr; i++) {
  2473. if (soc_info->rgltr_name[i] == NULL) {
  2474. CAM_ERR(CAM_UTIL, "can't find regulator name");
  2475. goto put_regulator;
  2476. }
  2477. rc = cam_soc_util_get_regulator(soc_info->dev,
  2478. &soc_info->rgltr[i],
  2479. soc_info->rgltr_name[i]);
  2480. if (rc)
  2481. goto put_regulator;
  2482. }
  2483. if (soc_info->irq_num > 0) {
  2484. rc = cam_soc_util_request_irq(soc_info->dev,
  2485. soc_info->irq_num,
  2486. handler, IRQF_TRIGGER_RISING,
  2487. soc_info->irq_name, irq_data,
  2488. soc_info->mem_block[0]->start);
  2489. if (rc) {
  2490. CAM_ERR(CAM_UTIL, "irq request fail");
  2491. rc = -EBUSY;
  2492. goto put_regulator;
  2493. }
  2494. soc_info->irq_data = irq_data;
  2495. }
  2496. /* Get Clock */
  2497. for (i = 0; i < soc_info->num_clk; i++) {
  2498. soc_info->clk[i] = clk_get(soc_info->dev,
  2499. soc_info->clk_name[i]);
  2500. if (IS_ERR(soc_info->clk[i])) {
  2501. CAM_ERR(CAM_UTIL, "get failed for %s",
  2502. soc_info->clk_name[i]);
  2503. rc = -ENOENT;
  2504. goto put_clk;
  2505. } else if (!soc_info->clk[i]) {
  2506. CAM_DBG(CAM_UTIL, "%s handle is NULL skip get",
  2507. soc_info->clk_name[i]);
  2508. continue;
  2509. }
  2510. /* Create a wrapper entry if this is a shared clock */
  2511. if (CAM_IS_BIT_SET(soc_info->shared_clk_mask, i)) {
  2512. uint32_t min_level = soc_info->lowest_clk_level;
  2513. CAM_DBG(CAM_UTIL,
  2514. "Dev %s, clk %s, id %d register wrapper entry for shared clk",
  2515. soc_info->dev_name, soc_info->clk_name[i],
  2516. soc_info->clk_id[i]);
  2517. rc = cam_soc_util_clk_wrapper_register_entry(
  2518. soc_info->clk_id[i], soc_info->clk[i],
  2519. (i == soc_info->src_clk_idx) ? true : false,
  2520. soc_info, soc_info->clk_rate[min_level][i],
  2521. soc_info->clk_name[i]);
  2522. if (rc) {
  2523. CAM_ERR(CAM_UTIL,
  2524. "Failed in registering shared clk Dev %s id %d",
  2525. soc_info->dev_name,
  2526. soc_info->clk_id[i]);
  2527. clk_put(soc_info->clk[i]);
  2528. soc_info->clk[i] = NULL;
  2529. goto put_clk;
  2530. }
  2531. } else if (i == soc_info->src_clk_idx) {
  2532. rc = cam_soc_util_register_mmrm_client(
  2533. soc_info->clk_id[i], soc_info->clk[i],
  2534. soc_info->is_nrt_dev,
  2535. soc_info, soc_info->clk_name[i],
  2536. &soc_info->mmrm_handle);
  2537. if (rc) {
  2538. CAM_ERR(CAM_UTIL,
  2539. "Failed in register mmrm client Dev %s clk id %d",
  2540. soc_info->dev_name,
  2541. soc_info->clk_id[i]);
  2542. clk_put(soc_info->clk[i]);
  2543. soc_info->clk[i] = NULL;
  2544. goto put_clk;
  2545. }
  2546. }
  2547. }
  2548. rc = cam_soc_util_request_pinctrl(soc_info);
  2549. if (rc) {
  2550. CAM_ERR(CAM_UTIL, "Failed in requesting Pinctrl, rc: %d", rc);
  2551. goto put_clk;
  2552. }
  2553. rc = cam_soc_util_request_gpio_table(soc_info, true);
  2554. if (rc) {
  2555. CAM_ERR(CAM_UTIL, "Failed in request gpio table, rc=%d", rc);
  2556. goto put_clk;
  2557. }
  2558. if (soc_info->clk_control_enable)
  2559. cam_soc_util_create_clk_lvl_debugfs(soc_info);
  2560. return rc;
  2561. put_clk:
  2562. if (soc_info->mmrm_handle) {
  2563. cam_soc_util_unregister_mmrm_client(soc_info->mmrm_handle);
  2564. soc_info->mmrm_handle = NULL;
  2565. }
  2566. for (i = i - 1; i >= 0; i--) {
  2567. if (soc_info->clk[i]) {
  2568. if (CAM_IS_BIT_SET(soc_info->shared_clk_mask, i))
  2569. cam_soc_util_clk_wrapper_unregister_entry(
  2570. soc_info->clk_id[i], soc_info);
  2571. clk_put(soc_info->clk[i]);
  2572. soc_info->clk[i] = NULL;
  2573. }
  2574. }
  2575. if (soc_info->irq_num > 0) {
  2576. disable_irq(soc_info->irq_num);
  2577. devm_free_irq(soc_info->dev,
  2578. soc_info->irq_num, irq_data);
  2579. }
  2580. put_regulator:
  2581. if (i == -1)
  2582. i = soc_info->num_rgltr;
  2583. for (i = i - 1; i >= 0; i--) {
  2584. if (soc_info->rgltr[i]) {
  2585. regulator_disable(soc_info->rgltr[i]);
  2586. regulator_put(soc_info->rgltr[i]);
  2587. soc_info->rgltr[i] = NULL;
  2588. }
  2589. }
  2590. unmap_base:
  2591. if (i == -1)
  2592. i = soc_info->num_reg_map;
  2593. for (i = i - 1; i >= 0; i--) {
  2594. if (soc_info->reserve_mem)
  2595. release_mem_region(soc_info->mem_block[i]->start,
  2596. resource_size(soc_info->mem_block[i]));
  2597. iounmap(soc_info->reg_map[i].mem_base);
  2598. soc_info->reg_map[i].mem_base = NULL;
  2599. soc_info->reg_map[i].size = 0;
  2600. }
  2601. return rc;
  2602. }
  2603. int cam_soc_util_release_platform_resource(struct cam_hw_soc_info *soc_info)
  2604. {
  2605. int i;
  2606. bool b_ret = false;
  2607. if (!soc_info || !soc_info->dev) {
  2608. CAM_ERR(CAM_UTIL, "Invalid parameter");
  2609. return -EINVAL;
  2610. }
  2611. if (soc_info->mmrm_handle) {
  2612. cam_soc_util_unregister_mmrm_client(soc_info->mmrm_handle);
  2613. soc_info->mmrm_handle = NULL;
  2614. }
  2615. for (i = soc_info->num_clk - 1; i >= 0; i--) {
  2616. if (CAM_IS_BIT_SET(soc_info->shared_clk_mask, i))
  2617. cam_soc_util_clk_wrapper_unregister_entry(
  2618. soc_info->clk_id[i], soc_info);
  2619. if (!soc_info->clk[i]) {
  2620. CAM_DBG(CAM_UTIL, "%s handle is NULL skip put",
  2621. soc_info->clk_name[i]);
  2622. continue;
  2623. }
  2624. clk_put(soc_info->clk[i]);
  2625. soc_info->clk[i] = NULL;
  2626. }
  2627. for (i = soc_info->num_rgltr - 1; i >= 0; i--) {
  2628. if (soc_info->rgltr[i]) {
  2629. regulator_put(soc_info->rgltr[i]);
  2630. soc_info->rgltr[i] = NULL;
  2631. }
  2632. }
  2633. for (i = soc_info->num_reg_map - 1; i >= 0; i--) {
  2634. iounmap(soc_info->reg_map[i].mem_base);
  2635. soc_info->reg_map[i].mem_base = NULL;
  2636. soc_info->reg_map[i].size = 0;
  2637. }
  2638. if (soc_info->irq_num > 0) {
  2639. if (cam_presil_mode_enabled()) {
  2640. if (cam_soc_util_is_presil_address_space(soc_info->mem_block[0]->start)) {
  2641. b_ret = cam_presil_unsubscribe_device_irq(
  2642. soc_info->irq_line->start);
  2643. CAM_DBG(CAM_PRESIL, "UnSubscribe IRQ: Ret=%d NUM=%d Name=%s",
  2644. b_ret, soc_info->irq_line->start, soc_info->irq_name);
  2645. }
  2646. }
  2647. disable_irq(soc_info->irq_num);
  2648. devm_free_irq(soc_info->dev,
  2649. soc_info->irq_num, soc_info->irq_data);
  2650. }
  2651. cam_soc_util_release_pinctrl(soc_info);
  2652. /* release for gpio */
  2653. cam_soc_util_request_gpio_table(soc_info, false);
  2654. soc_info->dentry = NULL;
  2655. return 0;
  2656. }
  2657. int cam_soc_util_enable_platform_resource(struct cam_hw_soc_info *soc_info,
  2658. int cesta_client_idx, bool enable_clocks, enum cam_vote_level clk_level,
  2659. bool enable_irq)
  2660. {
  2661. int rc = 0;
  2662. if (!soc_info)
  2663. return -EINVAL;
  2664. rc = cam_soc_util_regulator_enable_default(soc_info);
  2665. if (rc) {
  2666. CAM_ERR(CAM_UTIL, "Regulators enable failed");
  2667. return rc;
  2668. }
  2669. if (enable_clocks) {
  2670. rc = cam_soc_util_clk_enable_default(soc_info, cesta_client_idx, clk_level);
  2671. if (rc)
  2672. goto disable_regulator;
  2673. }
  2674. if (enable_irq) {
  2675. rc = cam_soc_util_irq_enable(soc_info);
  2676. if (rc)
  2677. goto disable_clk;
  2678. }
  2679. return rc;
  2680. disable_clk:
  2681. if (enable_clocks)
  2682. cam_soc_util_clk_disable_default(soc_info, cesta_client_idx);
  2683. disable_regulator:
  2684. cam_soc_util_regulator_disable_default(soc_info);
  2685. return rc;
  2686. }
  2687. int cam_soc_util_disable_platform_resource(struct cam_hw_soc_info *soc_info,
  2688. int cesta_client_idx, bool disable_clocks, bool disable_irq)
  2689. {
  2690. int rc = 0;
  2691. if (!soc_info)
  2692. return -EINVAL;
  2693. if (disable_irq)
  2694. rc |= cam_soc_util_irq_disable(soc_info);
  2695. if (disable_clocks)
  2696. cam_soc_util_clk_disable_default(soc_info, cesta_client_idx);
  2697. cam_soc_util_regulator_disable_default(soc_info);
  2698. return rc;
  2699. }
  2700. int cam_soc_util_reg_dump(struct cam_hw_soc_info *soc_info,
  2701. uint32_t base_index, uint32_t offset, int size)
  2702. {
  2703. void __iomem *base_addr = NULL;
  2704. CAM_DBG(CAM_UTIL, "base_idx %u size=%d", base_index, size);
  2705. if (!soc_info || base_index >= soc_info->num_reg_map ||
  2706. size <= 0 || (offset + size) >=
  2707. CAM_SOC_GET_REG_MAP_SIZE(soc_info, base_index))
  2708. return -EINVAL;
  2709. base_addr = CAM_SOC_GET_REG_MAP_START(soc_info, base_index);
  2710. /*
  2711. * All error checking already done above,
  2712. * hence ignoring the return value below.
  2713. */
  2714. cam_io_dump(base_addr, offset, size);
  2715. return 0;
  2716. }
  2717. static int cam_soc_util_dump_cont_reg_range(
  2718. struct cam_hw_soc_info *soc_info,
  2719. struct cam_reg_range_read_desc *reg_read, uint32_t base_idx,
  2720. struct cam_reg_dump_out_buffer *dump_out_buf, uintptr_t cmd_buf_end)
  2721. {
  2722. int i = 0, rc = 0;
  2723. uint32_t write_idx = 0;
  2724. if (!soc_info || !dump_out_buf || !reg_read || !cmd_buf_end) {
  2725. CAM_ERR(CAM_UTIL,
  2726. "Invalid input args soc_info: %pK, dump_out_buffer: %pK reg_read: %pK cmd_buf_end: %pK",
  2727. soc_info, dump_out_buf, reg_read, cmd_buf_end);
  2728. rc = -EINVAL;
  2729. goto end;
  2730. }
  2731. if ((reg_read->num_values) && ((reg_read->num_values > U32_MAX / 2) ||
  2732. (sizeof(uint32_t) > ((U32_MAX -
  2733. sizeof(struct cam_reg_dump_out_buffer) -
  2734. dump_out_buf->bytes_written) /
  2735. (reg_read->num_values * 2))))) {
  2736. CAM_ERR(CAM_UTIL,
  2737. "Integer Overflow bytes_written: [%u] num_values: [%u]",
  2738. dump_out_buf->bytes_written, reg_read->num_values);
  2739. rc = -EOVERFLOW;
  2740. goto end;
  2741. }
  2742. if ((cmd_buf_end - (uintptr_t)dump_out_buf) <=
  2743. (uintptr_t)(sizeof(struct cam_reg_dump_out_buffer)
  2744. - sizeof(uint32_t) + dump_out_buf->bytes_written +
  2745. (reg_read->num_values * 2 * sizeof(uint32_t)))) {
  2746. CAM_ERR(CAM_UTIL,
  2747. "Insufficient space in out buffer num_values: [%d] cmd_buf_end: %pK dump_out_buf: %pK",
  2748. reg_read->num_values, cmd_buf_end,
  2749. (uintptr_t)dump_out_buf);
  2750. rc = -EINVAL;
  2751. goto end;
  2752. }
  2753. write_idx = dump_out_buf->bytes_written / sizeof(uint32_t);
  2754. for (i = 0; i < reg_read->num_values; i++) {
  2755. if ((reg_read->offset + (i * sizeof(uint32_t))) >
  2756. (uint32_t)soc_info->reg_map[base_idx].size) {
  2757. CAM_ERR(CAM_UTIL,
  2758. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2759. (reg_read->offset + (i * sizeof(uint32_t))),
  2760. (uint32_t)soc_info->reg_map[base_idx].size);
  2761. rc = -EINVAL;
  2762. goto end;
  2763. }
  2764. dump_out_buf->dump_data[write_idx++] = reg_read->offset +
  2765. (i * sizeof(uint32_t));
  2766. dump_out_buf->dump_data[write_idx++] =
  2767. cam_soc_util_r(soc_info, base_idx,
  2768. (reg_read->offset + (i * sizeof(uint32_t))));
  2769. dump_out_buf->bytes_written += (2 * sizeof(uint32_t));
  2770. }
  2771. end:
  2772. return rc;
  2773. }
  2774. static int cam_soc_util_dump_dmi_reg_range(
  2775. struct cam_hw_soc_info *soc_info,
  2776. struct cam_dmi_read_desc *dmi_read, uint32_t base_idx,
  2777. struct cam_reg_dump_out_buffer *dump_out_buf, uintptr_t cmd_buf_end)
  2778. {
  2779. int i = 0, rc = 0;
  2780. uint32_t write_idx = 0;
  2781. if (!soc_info || !dump_out_buf || !dmi_read || !cmd_buf_end) {
  2782. CAM_ERR(CAM_UTIL,
  2783. "Invalid input args soc_info: %pK, dump_out_buffer: %pK",
  2784. soc_info, dump_out_buf);
  2785. rc = -EINVAL;
  2786. goto end;
  2787. }
  2788. if (dmi_read->num_pre_writes > CAM_REG_DUMP_DMI_CONFIG_MAX ||
  2789. dmi_read->num_post_writes > CAM_REG_DUMP_DMI_CONFIG_MAX) {
  2790. CAM_ERR(CAM_UTIL,
  2791. "Invalid number of requested writes, pre: %d post: %d",
  2792. dmi_read->num_pre_writes, dmi_read->num_post_writes);
  2793. rc = -EINVAL;
  2794. goto end;
  2795. }
  2796. if ((dmi_read->num_pre_writes + dmi_read->dmi_data_read.num_values)
  2797. && ((dmi_read->num_pre_writes > U32_MAX / 2) ||
  2798. (dmi_read->dmi_data_read.num_values > U32_MAX / 2) ||
  2799. ((dmi_read->num_pre_writes * 2) > U32_MAX -
  2800. (dmi_read->dmi_data_read.num_values * 2)) ||
  2801. (sizeof(uint32_t) > ((U32_MAX -
  2802. sizeof(struct cam_reg_dump_out_buffer) -
  2803. dump_out_buf->bytes_written) / ((dmi_read->num_pre_writes +
  2804. dmi_read->dmi_data_read.num_values) * 2))))) {
  2805. CAM_ERR(CAM_UTIL,
  2806. "Integer Overflow bytes_written: [%u] num_pre_writes: [%u] num_values: [%u]",
  2807. dump_out_buf->bytes_written, dmi_read->num_pre_writes,
  2808. dmi_read->dmi_data_read.num_values);
  2809. rc = -EOVERFLOW;
  2810. goto end;
  2811. }
  2812. if ((cmd_buf_end - (uintptr_t)dump_out_buf) <=
  2813. (uintptr_t)(
  2814. sizeof(struct cam_reg_dump_out_buffer) - sizeof(uint32_t) +
  2815. (dump_out_buf->bytes_written +
  2816. (dmi_read->num_pre_writes * 2 * sizeof(uint32_t)) +
  2817. (dmi_read->dmi_data_read.num_values * 2 *
  2818. sizeof(uint32_t))))) {
  2819. CAM_ERR(CAM_UTIL,
  2820. "Insufficient space in out buffer num_read_val: [%d] num_write_val: [%d] cmd_buf_end: %pK dump_out_buf: %pK",
  2821. dmi_read->dmi_data_read.num_values,
  2822. dmi_read->num_pre_writes, cmd_buf_end,
  2823. (uintptr_t)dump_out_buf);
  2824. rc = -EINVAL;
  2825. goto end;
  2826. }
  2827. write_idx = dump_out_buf->bytes_written / sizeof(uint32_t);
  2828. for (i = 0; i < dmi_read->num_pre_writes; i++) {
  2829. if (dmi_read->pre_read_config[i].offset >
  2830. (uint32_t)soc_info->reg_map[base_idx].size) {
  2831. CAM_ERR(CAM_UTIL,
  2832. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2833. dmi_read->pre_read_config[i].offset,
  2834. (uint32_t)soc_info->reg_map[base_idx].size);
  2835. rc = -EINVAL;
  2836. goto end;
  2837. }
  2838. cam_soc_util_w_mb(soc_info, base_idx,
  2839. dmi_read->pre_read_config[i].offset,
  2840. dmi_read->pre_read_config[i].value);
  2841. dump_out_buf->dump_data[write_idx++] =
  2842. dmi_read->pre_read_config[i].offset;
  2843. dump_out_buf->dump_data[write_idx++] =
  2844. dmi_read->pre_read_config[i].value;
  2845. dump_out_buf->bytes_written += (2 * sizeof(uint32_t));
  2846. }
  2847. if (dmi_read->dmi_data_read.offset >
  2848. (uint32_t)soc_info->reg_map[base_idx].size) {
  2849. CAM_ERR(CAM_UTIL,
  2850. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2851. dmi_read->dmi_data_read.offset,
  2852. (uint32_t)soc_info->reg_map[base_idx].size);
  2853. rc = -EINVAL;
  2854. goto end;
  2855. }
  2856. for (i = 0; i < dmi_read->dmi_data_read.num_values; i++) {
  2857. dump_out_buf->dump_data[write_idx++] =
  2858. dmi_read->dmi_data_read.offset;
  2859. dump_out_buf->dump_data[write_idx++] =
  2860. cam_soc_util_r_mb(soc_info, base_idx,
  2861. dmi_read->dmi_data_read.offset);
  2862. dump_out_buf->bytes_written += (2 * sizeof(uint32_t));
  2863. }
  2864. for (i = 0; i < dmi_read->num_post_writes; i++) {
  2865. if (dmi_read->post_read_config[i].offset >
  2866. (uint32_t)soc_info->reg_map[base_idx].size) {
  2867. CAM_ERR(CAM_UTIL,
  2868. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2869. dmi_read->post_read_config[i].offset,
  2870. (uint32_t)soc_info->reg_map[base_idx].size);
  2871. rc = -EINVAL;
  2872. goto end;
  2873. }
  2874. cam_soc_util_w_mb(soc_info, base_idx,
  2875. dmi_read->post_read_config[i].offset,
  2876. dmi_read->post_read_config[i].value);
  2877. }
  2878. end:
  2879. return rc;
  2880. }
  2881. static int cam_soc_util_dump_dmi_reg_range_user_buf(
  2882. struct cam_hw_soc_info *soc_info,
  2883. struct cam_dmi_read_desc *dmi_read, uint32_t base_idx,
  2884. struct cam_hw_soc_dump_args *dump_args)
  2885. {
  2886. int i;
  2887. int rc;
  2888. size_t buf_len = 0;
  2889. uint8_t *dst;
  2890. size_t remain_len;
  2891. uint32_t min_len;
  2892. uint32_t *waddr, *start;
  2893. uintptr_t cpu_addr;
  2894. struct cam_hw_soc_dump_header *hdr;
  2895. if (!soc_info || !dump_args || !dmi_read) {
  2896. CAM_ERR(CAM_UTIL,
  2897. "Invalid input args soc_info: %pK, dump_args: %pK",
  2898. soc_info, dump_args);
  2899. rc = -EINVAL;
  2900. goto end;
  2901. }
  2902. if (dmi_read->num_pre_writes > CAM_REG_DUMP_DMI_CONFIG_MAX ||
  2903. dmi_read->num_post_writes > CAM_REG_DUMP_DMI_CONFIG_MAX) {
  2904. CAM_ERR(CAM_UTIL,
  2905. "Invalid number of requested writes, pre: %d post: %d",
  2906. dmi_read->num_pre_writes, dmi_read->num_post_writes);
  2907. rc = -EINVAL;
  2908. goto end;
  2909. }
  2910. rc = cam_mem_get_cpu_buf(dump_args->buf_handle, &cpu_addr, &buf_len);
  2911. if (rc) {
  2912. CAM_ERR(CAM_UTIL, "Invalid handle %u rc %d",
  2913. dump_args->buf_handle, rc);
  2914. goto end;
  2915. }
  2916. if (buf_len <= dump_args->offset) {
  2917. CAM_WARN(CAM_UTIL, "Dump offset overshoot offset %zu len %zu",
  2918. dump_args->offset, buf_len);
  2919. rc = -ENOSPC;
  2920. goto end;
  2921. }
  2922. remain_len = buf_len - dump_args->offset;
  2923. min_len = (dmi_read->num_pre_writes * 2 * sizeof(uint32_t)) +
  2924. (dmi_read->dmi_data_read.num_values * 2 * sizeof(uint32_t)) +
  2925. sizeof(uint32_t);
  2926. if (remain_len < min_len) {
  2927. CAM_WARN(CAM_UTIL,
  2928. "Dump Buffer exhaust read %d write %d remain %zu min %u",
  2929. dmi_read->dmi_data_read.num_values,
  2930. dmi_read->num_pre_writes, remain_len,
  2931. min_len);
  2932. rc = -ENOSPC;
  2933. goto end;
  2934. }
  2935. dst = (uint8_t *)cpu_addr + dump_args->offset;
  2936. hdr = (struct cam_hw_soc_dump_header *)dst;
  2937. memset(hdr, 0, sizeof(struct cam_hw_soc_dump_header));
  2938. scnprintf(hdr->tag, CAM_SOC_HW_DUMP_TAG_MAX_LEN,
  2939. "DMI_DUMP:");
  2940. waddr = (uint32_t *)(dst + sizeof(struct cam_hw_soc_dump_header));
  2941. start = waddr;
  2942. hdr->word_size = sizeof(uint32_t);
  2943. *waddr = soc_info->index;
  2944. waddr++;
  2945. for (i = 0; i < dmi_read->num_pre_writes; i++) {
  2946. if (dmi_read->pre_read_config[i].offset >
  2947. (uint32_t)soc_info->reg_map[base_idx].size) {
  2948. CAM_ERR(CAM_UTIL,
  2949. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2950. dmi_read->pre_read_config[i].offset,
  2951. (uint32_t)soc_info->reg_map[base_idx].size);
  2952. rc = -EINVAL;
  2953. goto end;
  2954. }
  2955. cam_soc_util_w_mb(soc_info, base_idx,
  2956. dmi_read->pre_read_config[i].offset,
  2957. dmi_read->pre_read_config[i].value);
  2958. *waddr++ = dmi_read->pre_read_config[i].offset;
  2959. *waddr++ = dmi_read->pre_read_config[i].value;
  2960. }
  2961. if (dmi_read->dmi_data_read.offset >
  2962. (uint32_t)soc_info->reg_map[base_idx].size) {
  2963. CAM_ERR(CAM_UTIL,
  2964. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2965. dmi_read->dmi_data_read.offset,
  2966. (uint32_t)soc_info->reg_map[base_idx].size);
  2967. rc = -EINVAL;
  2968. goto end;
  2969. }
  2970. for (i = 0; i < dmi_read->dmi_data_read.num_values; i++) {
  2971. *waddr++ = dmi_read->dmi_data_read.offset;
  2972. *waddr++ = cam_soc_util_r_mb(soc_info, base_idx,
  2973. dmi_read->dmi_data_read.offset);
  2974. }
  2975. for (i = 0; i < dmi_read->num_post_writes; i++) {
  2976. if (dmi_read->post_read_config[i].offset >
  2977. (uint32_t)soc_info->reg_map[base_idx].size) {
  2978. CAM_ERR(CAM_UTIL,
  2979. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2980. dmi_read->post_read_config[i].offset,
  2981. (uint32_t)soc_info->reg_map[base_idx].size);
  2982. rc = -EINVAL;
  2983. goto end;
  2984. }
  2985. cam_soc_util_w_mb(soc_info, base_idx,
  2986. dmi_read->post_read_config[i].offset,
  2987. dmi_read->post_read_config[i].value);
  2988. }
  2989. hdr->size = (waddr - start) * hdr->word_size;
  2990. dump_args->offset += hdr->size +
  2991. sizeof(struct cam_hw_soc_dump_header);
  2992. end:
  2993. return rc;
  2994. }
  2995. static int cam_soc_util_dump_cont_reg_range_user_buf(
  2996. struct cam_hw_soc_info *soc_info,
  2997. struct cam_reg_range_read_desc *reg_read,
  2998. uint32_t base_idx,
  2999. struct cam_hw_soc_dump_args *dump_args)
  3000. {
  3001. int i;
  3002. int rc = 0;
  3003. size_t buf_len;
  3004. uint8_t *dst;
  3005. size_t remain_len;
  3006. uint32_t min_len;
  3007. uint32_t *waddr, *start;
  3008. uintptr_t cpu_addr;
  3009. struct cam_hw_soc_dump_header *hdr;
  3010. if (!soc_info || !dump_args || !reg_read) {
  3011. CAM_ERR(CAM_UTIL,
  3012. "Invalid input args soc_info: %pK, dump_out_buffer: %pK reg_read: %pK",
  3013. soc_info, dump_args, reg_read);
  3014. rc = -EINVAL;
  3015. goto end;
  3016. }
  3017. rc = cam_mem_get_cpu_buf(dump_args->buf_handle, &cpu_addr, &buf_len);
  3018. if (rc) {
  3019. CAM_ERR(CAM_UTIL, "Invalid handle %u rc %d",
  3020. dump_args->buf_handle, rc);
  3021. goto end;
  3022. }
  3023. if (buf_len <= dump_args->offset) {
  3024. CAM_WARN(CAM_UTIL, "Dump offset overshoot %zu %zu",
  3025. dump_args->offset, buf_len);
  3026. rc = -ENOSPC;
  3027. goto end;
  3028. }
  3029. remain_len = buf_len - dump_args->offset;
  3030. min_len = (reg_read->num_values * 2 * sizeof(uint32_t)) +
  3031. sizeof(struct cam_hw_soc_dump_header) + sizeof(uint32_t);
  3032. if (remain_len < min_len) {
  3033. CAM_WARN(CAM_UTIL,
  3034. "Dump Buffer exhaust read_values %d remain %zu min %u",
  3035. reg_read->num_values,
  3036. remain_len,
  3037. min_len);
  3038. rc = -ENOSPC;
  3039. goto end;
  3040. }
  3041. dst = (uint8_t *)cpu_addr + dump_args->offset;
  3042. hdr = (struct cam_hw_soc_dump_header *)dst;
  3043. memset(hdr, 0, sizeof(struct cam_hw_soc_dump_header));
  3044. scnprintf(hdr->tag, CAM_SOC_HW_DUMP_TAG_MAX_LEN, "%s_REG:",
  3045. soc_info->dev_name);
  3046. waddr = (uint32_t *)(dst + sizeof(struct cam_hw_soc_dump_header));
  3047. start = waddr;
  3048. hdr->word_size = sizeof(uint32_t);
  3049. *waddr = soc_info->index;
  3050. waddr++;
  3051. for (i = 0; i < reg_read->num_values; i++) {
  3052. if ((reg_read->offset + (i * sizeof(uint32_t))) >
  3053. (uint32_t)soc_info->reg_map[base_idx].size) {
  3054. CAM_ERR(CAM_UTIL,
  3055. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  3056. (reg_read->offset + (i * sizeof(uint32_t))),
  3057. (uint32_t)soc_info->reg_map[base_idx].size);
  3058. rc = -EINVAL;
  3059. goto end;
  3060. }
  3061. waddr[0] = reg_read->offset + (i * sizeof(uint32_t));
  3062. waddr[1] = cam_soc_util_r(soc_info, base_idx,
  3063. (reg_read->offset + (i * sizeof(uint32_t))));
  3064. waddr += 2;
  3065. }
  3066. hdr->size = (waddr - start) * hdr->word_size;
  3067. dump_args->offset += hdr->size +
  3068. sizeof(struct cam_hw_soc_dump_header);
  3069. end:
  3070. return rc;
  3071. }
  3072. static int cam_soc_util_user_reg_dump(
  3073. struct cam_reg_dump_desc *reg_dump_desc,
  3074. struct cam_hw_soc_dump_args *dump_args,
  3075. struct cam_hw_soc_info *soc_info,
  3076. uint32_t reg_base_idx)
  3077. {
  3078. int rc = 0;
  3079. int i;
  3080. struct cam_reg_read_info *reg_read_info = NULL;
  3081. if (!dump_args || !reg_dump_desc || !soc_info) {
  3082. CAM_ERR(CAM_UTIL,
  3083. "Invalid input parameters %pK %pK %pK",
  3084. dump_args, reg_dump_desc, soc_info);
  3085. return -EINVAL;
  3086. }
  3087. for (i = 0; i < reg_dump_desc->num_read_range; i++) {
  3088. reg_read_info = &reg_dump_desc->read_range[i];
  3089. if (reg_read_info->type ==
  3090. CAM_REG_DUMP_READ_TYPE_CONT_RANGE) {
  3091. rc = cam_soc_util_dump_cont_reg_range_user_buf(
  3092. soc_info,
  3093. &reg_read_info->reg_read,
  3094. reg_base_idx,
  3095. dump_args);
  3096. } else if (reg_read_info->type ==
  3097. CAM_REG_DUMP_READ_TYPE_DMI) {
  3098. rc = cam_soc_util_dump_dmi_reg_range_user_buf(
  3099. soc_info,
  3100. &reg_read_info->dmi_read,
  3101. reg_base_idx,
  3102. dump_args);
  3103. } else {
  3104. CAM_ERR(CAM_UTIL,
  3105. "Invalid Reg dump read type: %d",
  3106. reg_read_info->type);
  3107. rc = -EINVAL;
  3108. goto end;
  3109. }
  3110. if (rc) {
  3111. CAM_ERR(CAM_UTIL,
  3112. "Reg range read failed rc: %d reg_base_idx: %d",
  3113. rc, reg_base_idx);
  3114. goto end;
  3115. }
  3116. }
  3117. end:
  3118. return rc;
  3119. }
  3120. int cam_soc_util_reg_dump_to_cmd_buf(void *ctx,
  3121. struct cam_cmd_buf_desc *cmd_desc, uint64_t req_id,
  3122. cam_soc_util_regspace_data_cb reg_data_cb,
  3123. struct cam_hw_soc_dump_args *soc_dump_args,
  3124. bool user_triggered_dump)
  3125. {
  3126. int rc = 0, i, j;
  3127. uintptr_t cpu_addr = 0;
  3128. uintptr_t cmd_buf_start = 0;
  3129. uintptr_t cmd_in_data_end = 0;
  3130. uintptr_t cmd_buf_end = 0;
  3131. uint32_t reg_base_type = 0;
  3132. size_t buf_size = 0, remain_len = 0;
  3133. struct cam_reg_dump_input_info *reg_input_info = NULL;
  3134. struct cam_reg_dump_desc *reg_dump_desc = NULL;
  3135. struct cam_reg_dump_out_buffer *dump_out_buf = NULL;
  3136. struct cam_reg_read_info *reg_read_info = NULL;
  3137. struct cam_hw_soc_info *soc_info;
  3138. uint32_t reg_base_idx = 0;
  3139. if (!ctx || !cmd_desc || !reg_data_cb) {
  3140. CAM_ERR(CAM_UTIL, "Invalid args to reg dump [%pK] [%pK]",
  3141. cmd_desc, reg_data_cb);
  3142. return -EINVAL;
  3143. }
  3144. if (!cmd_desc->length || !cmd_desc->size) {
  3145. CAM_ERR(CAM_UTIL, "Invalid cmd buf size %d %d",
  3146. cmd_desc->length, cmd_desc->size);
  3147. return -EINVAL;
  3148. }
  3149. rc = cam_mem_get_cpu_buf(cmd_desc->mem_handle, &cpu_addr, &buf_size);
  3150. if (rc || !cpu_addr || (buf_size == 0)) {
  3151. CAM_ERR(CAM_UTIL, "Failed in Get cpu addr, rc=%d, cpu_addr=%pK",
  3152. rc, (void *)cpu_addr);
  3153. goto end;
  3154. }
  3155. CAM_DBG(CAM_UTIL, "Get cpu buf success req_id: %llu buf_size: %zu",
  3156. req_id, buf_size);
  3157. if ((buf_size < sizeof(uint32_t)) ||
  3158. ((size_t)cmd_desc->offset > (buf_size - sizeof(uint32_t)))) {
  3159. CAM_ERR(CAM_UTIL, "Invalid offset for cmd buf: %zu",
  3160. (size_t)cmd_desc->offset);
  3161. rc = -EINVAL;
  3162. goto end;
  3163. }
  3164. remain_len = buf_size - (size_t)cmd_desc->offset;
  3165. if ((remain_len < (size_t)cmd_desc->size) || (cmd_desc->size <
  3166. cmd_desc->length)) {
  3167. CAM_ERR(CAM_UTIL,
  3168. "Invalid params for cmd buf len: %zu size: %zu remain_len: %zu",
  3169. (size_t)cmd_desc->length, (size_t)cmd_desc->length,
  3170. remain_len);
  3171. rc = -EINVAL;
  3172. goto end;
  3173. }
  3174. cmd_buf_start = cpu_addr + (uintptr_t)cmd_desc->offset;
  3175. cmd_in_data_end = cmd_buf_start + (uintptr_t)cmd_desc->length;
  3176. cmd_buf_end = cmd_buf_start + (uintptr_t)cmd_desc->size;
  3177. if ((cmd_buf_end <= cmd_buf_start) ||
  3178. (cmd_in_data_end <= cmd_buf_start)) {
  3179. CAM_ERR(CAM_UTIL,
  3180. "Invalid length or size for cmd buf: [%zu] [%zu]",
  3181. (size_t)cmd_desc->length, (size_t)cmd_desc->size);
  3182. rc = -EINVAL;
  3183. goto end;
  3184. }
  3185. CAM_DBG(CAM_UTIL,
  3186. "Buffer params start [%pK] input_end [%pK] buf_end [%pK]",
  3187. cmd_buf_start, cmd_in_data_end, cmd_buf_end);
  3188. reg_input_info = (struct cam_reg_dump_input_info *) cmd_buf_start;
  3189. if ((reg_input_info->num_dump_sets > 1) && (sizeof(uint32_t) >
  3190. ((U32_MAX - sizeof(struct cam_reg_dump_input_info)) /
  3191. (reg_input_info->num_dump_sets - 1)))) {
  3192. CAM_ERR(CAM_UTIL,
  3193. "Integer Overflow req_id: [%llu] num_dump_sets: [%u]",
  3194. req_id, reg_input_info->num_dump_sets);
  3195. rc = -EOVERFLOW;
  3196. goto end;
  3197. }
  3198. if ((!reg_input_info->num_dump_sets) ||
  3199. ((cmd_in_data_end - cmd_buf_start) <= (uintptr_t)
  3200. (sizeof(struct cam_reg_dump_input_info) +
  3201. ((reg_input_info->num_dump_sets - 1) * sizeof(uint32_t))))) {
  3202. CAM_ERR(CAM_UTIL,
  3203. "Invalid number of dump sets, req_id: [%llu] num_dump_sets: [%u]",
  3204. req_id, reg_input_info->num_dump_sets);
  3205. rc = -EINVAL;
  3206. goto end;
  3207. }
  3208. CAM_DBG(CAM_UTIL,
  3209. "reg_input_info req_id: %llu ctx %pK num_dump_sets: %d",
  3210. req_id, ctx, reg_input_info->num_dump_sets);
  3211. for (i = 0; i < reg_input_info->num_dump_sets; i++) {
  3212. if ((cmd_in_data_end - cmd_buf_start) <= (uintptr_t)
  3213. reg_input_info->dump_set_offsets[i]) {
  3214. CAM_ERR(CAM_UTIL,
  3215. "Invalid dump set offset: [%pK], cmd_buf_start: [%pK] cmd_in_data_end: [%pK]",
  3216. (uintptr_t)reg_input_info->dump_set_offsets[i],
  3217. cmd_buf_start, cmd_in_data_end);
  3218. rc = -EINVAL;
  3219. goto end;
  3220. }
  3221. reg_dump_desc = (struct cam_reg_dump_desc *)
  3222. (cmd_buf_start +
  3223. (uintptr_t)reg_input_info->dump_set_offsets[i]);
  3224. if ((reg_dump_desc->num_read_range > 1) &&
  3225. (sizeof(struct cam_reg_read_info) > ((U32_MAX -
  3226. sizeof(struct cam_reg_dump_desc)) /
  3227. (reg_dump_desc->num_read_range - 1)))) {
  3228. CAM_ERR(CAM_UTIL,
  3229. "Integer Overflow req_id: [%llu] num_read_range: [%u]",
  3230. req_id, reg_dump_desc->num_read_range);
  3231. rc = -EOVERFLOW;
  3232. goto end;
  3233. }
  3234. if ((!reg_dump_desc->num_read_range) ||
  3235. ((cmd_in_data_end - (uintptr_t)reg_dump_desc) <=
  3236. (uintptr_t)(sizeof(struct cam_reg_dump_desc) +
  3237. ((reg_dump_desc->num_read_range - 1) *
  3238. sizeof(struct cam_reg_read_info))))) {
  3239. CAM_ERR(CAM_UTIL,
  3240. "Invalid number of read ranges, req_id: [%llu] num_read_range: [%d]",
  3241. req_id, reg_dump_desc->num_read_range);
  3242. rc = -EINVAL;
  3243. goto end;
  3244. }
  3245. if ((cmd_buf_end - cmd_buf_start) <= (uintptr_t)
  3246. (reg_dump_desc->dump_buffer_offset +
  3247. sizeof(struct cam_reg_dump_out_buffer))) {
  3248. CAM_ERR(CAM_UTIL,
  3249. "Invalid out buffer offset: [%pK], cmd_buf_start: [%pK] cmd_buf_end: [%pK]",
  3250. (uintptr_t)reg_dump_desc->dump_buffer_offset,
  3251. cmd_buf_start, cmd_buf_end);
  3252. rc = -EINVAL;
  3253. goto end;
  3254. }
  3255. reg_base_type = reg_dump_desc->reg_base_type;
  3256. if (reg_base_type == 0 || reg_base_type >
  3257. CAM_REG_DUMP_BASE_TYPE_SFE_RIGHT) {
  3258. CAM_ERR(CAM_UTIL,
  3259. "Invalid Reg dump base type: %d",
  3260. reg_base_type);
  3261. rc = -EINVAL;
  3262. goto end;
  3263. }
  3264. rc = reg_data_cb(reg_base_type, ctx, &soc_info, &reg_base_idx);
  3265. if (rc || !soc_info) {
  3266. CAM_ERR(CAM_UTIL,
  3267. "Reg space data callback failed rc: %d soc_info: [%pK]",
  3268. rc, soc_info);
  3269. rc = -EINVAL;
  3270. goto end;
  3271. }
  3272. if (reg_base_idx > soc_info->num_reg_map) {
  3273. CAM_ERR(CAM_UTIL,
  3274. "Invalid reg base idx: %d num reg map: %d",
  3275. reg_base_idx, soc_info->num_reg_map);
  3276. rc = -EINVAL;
  3277. goto end;
  3278. }
  3279. CAM_DBG(CAM_UTIL,
  3280. "Reg data callback success req_id: %llu base_type: %d base_idx: %d num_read_range: %d",
  3281. req_id, reg_base_type, reg_base_idx,
  3282. reg_dump_desc->num_read_range);
  3283. /* If the dump request is triggered by user space
  3284. * buffer will be different from the buffer which is received
  3285. * in init packet. In this case, dump the data to the
  3286. * user provided buffer and exit.
  3287. */
  3288. if (user_triggered_dump) {
  3289. rc = cam_soc_util_user_reg_dump(reg_dump_desc,
  3290. soc_dump_args, soc_info, reg_base_idx);
  3291. CAM_INFO(CAM_UTIL,
  3292. "%s reg_base_idx %d dumped offset %u",
  3293. soc_info->dev_name, reg_base_idx,
  3294. soc_dump_args->offset);
  3295. goto end;
  3296. }
  3297. /* Below code is executed when data is dumped to the
  3298. * out buffer received in init packet
  3299. */
  3300. dump_out_buf = (struct cam_reg_dump_out_buffer *)
  3301. (cmd_buf_start +
  3302. (uintptr_t)reg_dump_desc->dump_buffer_offset);
  3303. dump_out_buf->req_id = req_id;
  3304. dump_out_buf->bytes_written = 0;
  3305. for (j = 0; j < reg_dump_desc->num_read_range; j++) {
  3306. CAM_DBG(CAM_UTIL,
  3307. "Number of bytes written to cmd buffer: %u req_id: %llu",
  3308. dump_out_buf->bytes_written, req_id);
  3309. reg_read_info = &reg_dump_desc->read_range[j];
  3310. if (reg_read_info->type ==
  3311. CAM_REG_DUMP_READ_TYPE_CONT_RANGE) {
  3312. rc = cam_soc_util_dump_cont_reg_range(soc_info,
  3313. &reg_read_info->reg_read, reg_base_idx,
  3314. dump_out_buf, cmd_buf_end);
  3315. } else if (reg_read_info->type ==
  3316. CAM_REG_DUMP_READ_TYPE_DMI) {
  3317. rc = cam_soc_util_dump_dmi_reg_range(soc_info,
  3318. &reg_read_info->dmi_read, reg_base_idx,
  3319. dump_out_buf, cmd_buf_end);
  3320. } else {
  3321. CAM_ERR(CAM_UTIL,
  3322. "Invalid Reg dump read type: %d",
  3323. reg_read_info->type);
  3324. rc = -EINVAL;
  3325. goto end;
  3326. }
  3327. if (rc) {
  3328. CAM_ERR(CAM_UTIL,
  3329. "Reg range read failed rc: %d reg_base_idx: %d dump_out_buf: %pK",
  3330. rc, reg_base_idx, dump_out_buf);
  3331. goto end;
  3332. }
  3333. }
  3334. }
  3335. end:
  3336. return rc;
  3337. }
  3338. /**
  3339. * cam_soc_util_print_clk_freq()
  3340. *
  3341. * @brief: This function gets the clk rates for each clk from clk
  3342. * driver and prints in log
  3343. *
  3344. * @soc_info: Device soc struct to be populated
  3345. *
  3346. * @return: success or failure
  3347. */
  3348. int cam_soc_util_print_clk_freq(struct cam_hw_soc_info *soc_info)
  3349. {
  3350. int i;
  3351. unsigned long clk_rate = 0;
  3352. if (!soc_info) {
  3353. CAM_ERR(CAM_UTIL, "Invalid soc info");
  3354. return -EINVAL;
  3355. }
  3356. if ((soc_info->num_clk == 0) ||
  3357. (soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
  3358. CAM_ERR(CAM_UTIL, "[%s] Invalid number of clock %d",
  3359. soc_info->dev_name, soc_info->num_clk);
  3360. return -EINVAL;
  3361. }
  3362. for (i = 0; i < soc_info->num_clk; i++) {
  3363. clk_rate = clk_get_rate(soc_info->clk[i]);
  3364. CAM_INFO(CAM_UTIL,
  3365. "[%s] idx = %d clk name = %s clk_rate=%lld",
  3366. soc_info->dev_name, i, soc_info->clk_name[i],
  3367. clk_rate);
  3368. }
  3369. return 0;
  3370. }
  3371. inline unsigned long cam_soc_util_get_applied_src_clk(
  3372. struct cam_hw_soc_info *soc_info, bool is_max)
  3373. {
  3374. unsigned long clk_rate;
  3375. /*
  3376. * For CRMC type, exa - ife, csid, cphy
  3377. * final clk = max(hw_client_0, hw_client_1, hw_client_2, sw_client)
  3378. * For CRMB type, exa - camnoc axi
  3379. * final clk = max(hw_client_0 + hw_client_1 + hw_client_2, sw_client)
  3380. */
  3381. if (is_max) {
  3382. clk_rate = max(soc_info->applied_src_clk_rates.hw_client[0].high,
  3383. soc_info->applied_src_clk_rates.hw_client[1].high);
  3384. clk_rate = max(clk_rate, soc_info->applied_src_clk_rates.hw_client[2].high);
  3385. clk_rate = max(clk_rate, soc_info->applied_src_clk_rates.sw_client);
  3386. } else {
  3387. clk_rate = max((soc_info->applied_src_clk_rates.hw_client[0].high +
  3388. soc_info->applied_src_clk_rates.hw_client[1].high +
  3389. soc_info->applied_src_clk_rates.hw_client[2].high),
  3390. soc_info->applied_src_clk_rates.sw_client);
  3391. }
  3392. return clk_rate;
  3393. }
  3394. int cam_soc_util_regulators_enabled(struct cam_hw_soc_info *soc_info)
  3395. {
  3396. int j = 0, rc = 0;
  3397. int enabled_cnt = 0;
  3398. for (j = 0; j < soc_info->num_rgltr; j++) {
  3399. if (soc_info->rgltr[j]) {
  3400. rc = regulator_is_enabled(soc_info->rgltr[j]);
  3401. if (rc < 0) {
  3402. CAM_ERR(CAM_UTIL, "%s regulator_is_enabled failed",
  3403. soc_info->rgltr_name[j]);
  3404. } else if (rc > 0) {
  3405. CAM_DBG(CAM_UTIL, "%s regulator enabled",
  3406. soc_info->rgltr_name[j]);
  3407. enabled_cnt++;
  3408. } else {
  3409. CAM_DBG(CAM_UTIL, "%s regulator is disabled",
  3410. soc_info->rgltr_name[j]);
  3411. }
  3412. }
  3413. }
  3414. return enabled_cnt;
  3415. }