cfg_fwol_generic.h 15 KB

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  1. /*
  2. * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. /**
  19. * DOC: This file contains centralized definitions of converged configuration.
  20. */
  21. #ifndef __CFG_FWOL_GENERIC_H
  22. #define __CFG_FWOL_GENERIC_H
  23. /*
  24. *
  25. * <ini>
  26. * gEnableANI - Enable Adaptive Noise Immunity
  27. * @Min: 0
  28. * @Max: 1
  29. * @Default: 1
  30. *
  31. * This ini is used to enable or disable Adaptive Noise Immunity.
  32. *
  33. * Related: None
  34. *
  35. * Supported Feature: ANI
  36. *
  37. * Usage: External
  38. *
  39. * </ini>
  40. */
  41. #define CFG_ENABLE_ANI CFG_INI_BOOL( \
  42. "gEnableANI", \
  43. 1, \
  44. "Enable/Disable Adaptive Noise Immunity")
  45. /*
  46. * <ini>
  47. * gSetRTSForSIFSBursting - set rts for sifs bursting
  48. * @Min: 0
  49. * @Max: 1
  50. * @Default: 0
  51. *
  52. * This ini set rts for sifs bursting
  53. *
  54. * Usage: External
  55. *
  56. * </ini>
  57. */
  58. #define CFG_SET_RTS_FOR_SIFS_BURSTING CFG_INI_BOOL( \
  59. "gSetRTSForSIFSBursting", \
  60. 0, \
  61. "Set rts for sifs bursting")
  62. /*
  63. * <ini>
  64. * gMaxMPDUsInAMPDU - max mpdus in ampdu
  65. * @Min: 0
  66. * @Max: 64
  67. * @Default: 0
  68. *
  69. * This ini configure max mpdus in ampdu
  70. *
  71. * Usage: External
  72. *
  73. * </ini>
  74. */
  75. #define CFG_MAX_MPDUS_IN_AMPDU CFG_INI_INT( \
  76. "gMaxMPDUsInAMPDU", \
  77. 0, \
  78. 64, \
  79. 0, \
  80. CFG_VALUE_OR_DEFAULT, \
  81. "This ini configure max mpdus in ampdu")
  82. /*
  83. * <ini>
  84. * arp_ac_category - ARP access category
  85. * @Min: 0
  86. * @Max: 3
  87. * @Default: 3
  88. *
  89. * Firmware by default categorizes ARP packets with VOICE TID.
  90. * This ini shall be used to override the default configuration.
  91. * Access category enums are referenced in qca-vendor.h
  92. * QCA_WLAN_AC_BE = 0 (Best effort)
  93. * QCA_WLAN_AC_BK = 1 (Background)
  94. * QCA_WLAN_AC_VI = 2 (Video)
  95. * QCA_WLAN_AC_VO = 3 (Voice)
  96. *
  97. * Related: none
  98. *
  99. * Usage: Internal/External
  100. *
  101. * </ini>
  102. */
  103. #define CFG_ARP_AC_CATEGORY CFG_INI_INT( \
  104. "arp_ac_category", \
  105. 0, \
  106. 3, \
  107. 3, \
  108. CFG_VALUE_OR_DEFAULT, \
  109. "Override the default ARP AC configuration")
  110. /*
  111. * <ini>
  112. * gEnableFastPwrTransition - Configuration for fast power transition
  113. * @Min: 0
  114. * @Max: 2
  115. * @Default: 0
  116. *
  117. * This ini supported values:
  118. * 0x0: Phy register retention disabled (Higher timeline, Good for power)
  119. * 0x1: Phy register retention statically enabled
  120. * 0x2: Phy register retention enabled/disabled dynamically
  121. *
  122. * Usage: Internal
  123. *
  124. * </ini>
  125. */
  126. #define CFG_ENABLE_PHY_REG CFG_INI_UINT( \
  127. "gEnableFastPwrTransition", \
  128. 0x0, \
  129. 0x2, \
  130. 0x0, \
  131. CFG_VALUE_OR_DEFAULT, \
  132. "Configuration for fast power transition")
  133. /*
  134. * <ini>
  135. * gUpperBrssiThresh - Sets Upper threshold for beacon RSSI
  136. * @Min: 36
  137. * @Max: 66
  138. * @Default: 46
  139. *
  140. * This ini sets Upper beacon threshold for beacon RSSI in FW
  141. * Used to reduced RX chainmask in FW, once this threshold is
  142. * reached FW will switch to 1X1 (Single chain).
  143. *
  144. * Supported Feature: STA
  145. *
  146. * Usage: External
  147. *
  148. * </ini>
  149. */
  150. #define CFG_UPPER_BRSSI_THRESH CFG_INI_UINT( \
  151. "gUpperBrssiThresh", \
  152. 36, \
  153. 66, \
  154. 46, \
  155. CFG_VALUE_OR_DEFAULT, \
  156. "Sets Upper threshold for beacon RSSI")
  157. /*
  158. * <ini>
  159. * gLowerBrssiThresh - Sets Lower threshold for beacon RSSI
  160. * @Min: 6
  161. * @Max: 36
  162. * @Default: 26
  163. *
  164. * This ini sets Lower beacon threshold for beacon RSSI in FW
  165. * Used to increase RX chainmask in FW, once this threshold is
  166. * reached FW will switch to 2X2 chain.
  167. *
  168. * Supported Feature: STA
  169. *
  170. * Usage: External
  171. *
  172. * </ini>
  173. */
  174. #define CFG_LOWER_BRSSI_THRESH CFG_INI_UINT( \
  175. "gLowerBrssiThresh", \
  176. 6, \
  177. 36, \
  178. 26, \
  179. CFG_VALUE_OR_DEFAULT, \
  180. "Sets Lower threshold for beacon RSSI")
  181. /*
  182. * <ini>
  183. * gDtim1ChRxEnable - Enable/Disable DTIM 1Chrx feature
  184. * @Min: 0
  185. * @Max: 1
  186. * @Default: 1
  187. *
  188. * This ini Enables or Disables DTIM 1CHRX feature in FW
  189. * If this flag is set FW enables shutting off one chain
  190. * while going to power save.
  191. *
  192. * Supported Feature: STA
  193. *
  194. * Usage: External
  195. *
  196. * </ini>
  197. */
  198. #define CFG_DTIM_1CHRX_ENABLE CFG_INI_BOOL( \
  199. "gDtim1ChRxEnable", \
  200. 1, \
  201. "Enable/Disable DTIM 1Chrx feature")
  202. /*
  203. * <ini>
  204. * gEnableAlternativeChainmask - Enable Co-Ex Alternative Chainmask
  205. * @Min: 0
  206. * @Max: 1
  207. * @Default: 0
  208. *
  209. * This ini is used to enable/disable the Co-ex Alternative Chainmask
  210. * feature via the WMI_PDEV_PARAM_ALTERNATIVE_CHAINMASK_SCHEME
  211. * firmware parameter.
  212. *
  213. * Related: None
  214. *
  215. * Supported Feature: STA
  216. *
  217. * Usage: Internal/External
  218. *
  219. * </ini>
  220. */
  221. #define CFG_ENABLE_COEX_ALT_CHAINMASK CFG_INI_BOOL( \
  222. "gEnableAlternativeChainmask", \
  223. 0, \
  224. "Enable Co-Ex Alternative Chainmask")
  225. /*
  226. * <ini>
  227. * gEnableSmartChainmask - Enable Smart Chainmask
  228. * @Min: 0
  229. * @Max: 1
  230. * @Default: 0
  231. *
  232. * This ini is used to enable/disable the Smart Chainmask feature via
  233. * the WMI_PDEV_PARAM_SMART_CHAINMASK_SCHEME firmware parameter.
  234. *
  235. * Related: None
  236. *
  237. * Supported Feature: STA
  238. *
  239. * Usage: Internal/External
  240. *
  241. * </ini>
  242. */
  243. #define CFG_ENABLE_SMART_CHAINMASK CFG_INI_BOOL( \
  244. "gEnableSmartChainmask", \
  245. 0, \
  246. "Enable/disable the Smart Chainmask feature")
  247. /*
  248. * <ini>
  249. * gEnableRTSProfiles - It will use configuring different RTS profiles
  250. * @Min: 0
  251. * @Max: 66
  252. * @Default: 33
  253. *
  254. * This ini used for configuring different RTS profiles
  255. * to firmware.
  256. * Following are the valid values for the rts profile:
  257. * RTSCTS_DISABLED 0
  258. * NOT_ALLOWED 1
  259. * NOT_ALLOWED 2
  260. * RTSCTS_DISABLED 16
  261. * RTSCTS_ENABLED_4_SECOND_RATESERIES 17
  262. * CTS2SELF_ENABLED_4_SECOND_RATESERIES 18
  263. * RTSCTS_DISABLED 32
  264. * RTSCTS_ENABLED_4_SWRETRIES 33
  265. * CTS2SELF_ENABLED_4_SWRETRIES 34
  266. * NOT_ALLOWED 48
  267. * NOT_ALLOWED 49
  268. * NOT_ALLOWED 50
  269. * RTSCTS_DISABLED 64
  270. * RTSCTS_ENABLED_4_ALL_RATESERIES 65
  271. * CTS2SELF_ENABLED_4_ALL_RATESERIES 66
  272. *
  273. * Related: None
  274. *
  275. * Supported Feature: STA
  276. *
  277. * Usage: Internal/External
  278. *
  279. * </ini>
  280. */
  281. #define CFG_ENABLE_FW_RTS_PROFILE CFG_INI_INT( \
  282. "gEnableRTSProfiles", \
  283. 0, \
  284. 66, \
  285. 33, \
  286. CFG_VALUE_OR_DEFAULT, \
  287. "It is used to configure different RTS profiles")
  288. /* <ini>
  289. * gFwDebugLogLevel - Firmware debug log level
  290. * @Min: 0
  291. * @Max: 255
  292. * @Default: 3
  293. *
  294. * This option controls the level of firmware debug log. Default value is
  295. * DBGLOG_WARN, which is to enable error and warning logs.
  296. *
  297. * Related: None
  298. *
  299. * Supported Features: Debugging
  300. *
  301. * Usage: Internal
  302. *
  303. * </ini>
  304. */
  305. #define CFG_ENABLE_FW_DEBUG_LOG_LEVEL CFG_INI_INT( \
  306. "gFwDebugLogLevel", \
  307. 0, \
  308. 255, \
  309. 3, \
  310. CFG_VALUE_OR_DEFAULT, \
  311. "enable error and warning logs by default")
  312. /* <ini>
  313. * gFwDebugLogType - Firmware debug log type
  314. * @Min: 0
  315. * @Max: 255
  316. * @Default: 3
  317. *
  318. * This option controls how driver is to give the firmware logs to net link
  319. * when cnss_diag service is started.
  320. *
  321. * Related: None
  322. *
  323. * Supported Features: Debugging
  324. *
  325. * Usage: Internal
  326. *
  327. * </ini>
  328. */
  329. #define CFG_ENABLE_FW_LOG_TYPE CFG_INI_INT( \
  330. "gFwDebugLogType", \
  331. 0, \
  332. 255, \
  333. 3, \
  334. CFG_VALUE_OR_DEFAULT, \
  335. "Default value to be given to the net link cnss_diag service")
  336. /*
  337. * <ini>
  338. * gFwDebugModuleLoglevel - modulized firmware debug log level
  339. * @Min: N/A
  340. * @Max: N/A
  341. * @Default: N/A
  342. *
  343. * This ini is used to set modulized firmware debug log level.
  344. * FW module log level input string format looks like below:
  345. * gFwDebugModuleLoglevel="<FW Module ID>,<Log Level>,..."
  346. * For example:
  347. * gFwDebugModuleLoglevel="1,0,2,1,3,2,4,3,5,4,6,5,7,6"
  348. * The above input string means:
  349. * For FW module ID 1 enable log level 0
  350. * For FW module ID 2 enable log level 1
  351. * For FW module ID 3 enable log level 2
  352. * For FW module ID 4 enable log level 3
  353. * For FW module ID 5 enable log level 4
  354. * For FW module ID 6 enable log level 5
  355. * For FW module ID 7 enable log level 6
  356. * For valid values of log levels check enum DBGLOG_LOG_LVL and
  357. * for valid values of module ids check enum WLAN_MODULE_ID.
  358. *
  359. * Related: None
  360. *
  361. * Supported Feature: Debugging
  362. *
  363. * Usage: Internal/External
  364. *
  365. * </ini>
  366. */
  367. #define FW_MODULE_LOG_LEVEL_STRING_LENGTH (512)
  368. #define CFG_ENABLE_FW_MODULE_LOG_LEVEL CFG_INI_STRING( \
  369. "gFwDebugModuleLoglevel", \
  370. 0, \
  371. FW_MODULE_LOG_LEVEL_STRING_LENGTH, \
  372. "2,1,3,1,5,1,9,1,13,1,14,1,18,1,19,1,26,1,28,1,29,1,31,1,36,1,38,1,"\
  373. "46,1,47,1,50,1,52,1,53,1,56,1,60,1,61,1,4,1", \
  374. "Set modulized firmware debug log level")
  375. #ifdef FEATURE_WLAN_RA_FILTERING
  376. /* <ini>
  377. * gRAFilterEnable
  378. * @Min: 0
  379. * @Max: 1
  380. * @Default: 1
  381. *
  382. * Related: None
  383. *
  384. * Usage: Internal
  385. *
  386. * </ini>
  387. */
  388. #define CFG_RA_FILTER_ENABLE CFG_INI_BOOL( \
  389. "gRAFilterEnable", \
  390. 1, \
  391. "Enable RA Filter")
  392. #else
  393. #define CFG_RA_FILTER_ENABLE
  394. #endif
  395. /* <ini>
  396. * gtsf_gpio_pin
  397. * @Min: 0
  398. * @Max: 254
  399. * @Default: 255
  400. *
  401. * GPIO pin to toggle when capture tsf
  402. *
  403. * Related: None
  404. *
  405. * Usage: Internal
  406. *
  407. * </ini>
  408. */
  409. #define CFG_SET_TSF_GPIO_PIN CFG_INI_INT( \
  410. "gtsf_gpio_pin", \
  411. 0, \
  412. 254, \
  413. 255, \
  414. CFG_VALUE_OR_DEFAULT, \
  415. "GPIO pin to toggle when capture tsf")
  416. #ifdef WLAN_FEATURE_TSF_PLUS_EXT_GPIO_IRQ
  417. /* <ini>
  418. * gtsf_irq_host_gpio_pin
  419. * @Min: 0
  420. * @Max: 254
  421. * @Default: 255
  422. *
  423. * TSF irq GPIO pin of host platform
  424. *
  425. * Related: None
  426. *
  427. * Usage: Internal
  428. *
  429. * </ini>
  430. */
  431. #define CFG_SET_TSF_IRQ_HOST_GPIO_PIN CFG_INI_INT( \
  432. "gtsf_irq_host_gpio_pin", \
  433. 0, \
  434. 254, \
  435. 255, \
  436. CFG_VALUE_OR_DEFAULT, \
  437. "TSF irq GPIO pin of host platform")
  438. #define __CFG_SET_TSF_IRQ_HOST_GPIO_PIN CFG(CFG_SET_TSF_IRQ_HOST_GPIO_PIN)
  439. #else
  440. #define __CFG_SET_TSF_IRQ_HOST_GPIO_PIN
  441. #endif
  442. #ifdef WLAN_FEATURE_TSF_PLUS_EXT_GPIO_SYNC
  443. /*
  444. * <ini>
  445. * gtsf_sync_host_gpio_pin
  446. * @Min: 0
  447. * @Max: 254
  448. * @Default: 255
  449. *
  450. * TSF sync GPIO pin of host platform
  451. *
  452. * The driver will use this gpio on host platform
  453. * to drive the TSF sync pin on wlan chip.
  454. * Toggling this gpio will generate a strobe to fw
  455. * for latching TSF.
  456. *
  457. * Related: None
  458. *
  459. * Usage: External
  460. *
  461. * </ini>
  462. */
  463. #define CFG_SET_TSF_SYNC_HOST_GPIO_PIN CFG_INI_UINT( \
  464. "gtsf_sync_host_gpio_pin", \
  465. 0, \
  466. 254, \
  467. 255, \
  468. CFG_VALUE_OR_DEFAULT, \
  469. "TSF sync GPIO pin of host platform")
  470. #define __CFG_SET_TSF_SYNC_HOST_GPIO_PIN CFG(CFG_SET_TSF_SYNC_HOST_GPIO_PIN)
  471. #else
  472. #define __CFG_SET_TSF_SYNC_HOST_GPIO_PIN
  473. #endif
  474. #if defined(WLAN_FEATURE_TSF) && defined(WLAN_FEATURE_TSF_PLUS)
  475. /* <ini>
  476. * gtsf_ptp_options: TSF Plus feature options
  477. * @Min: 0
  478. * @Max: 0xff
  479. * @Default: 0xf
  480. *
  481. * CFG_SET_TSF_PTP_OPT_RX (0x1)
  482. * CFG_SET_TSF_PTP_OPT_TX (0x2)
  483. * CFG_SET_TSF_PTP_OPT_RAW (0x4)
  484. * CFG_SET_TSF_DBG_FS (0x8)
  485. * CFG_SET_TSF_PTP_OPT_TSF64_TX (0x10)
  486. *
  487. * Related: None
  488. *
  489. * Usage: Internal
  490. *
  491. * </ini>
  492. */
  493. #define CFG_SET_TSF_PTP_OPT_RX (0x1)
  494. #define CFG_SET_TSF_PTP_OPT_TX (0x2)
  495. #define CFG_SET_TSF_PTP_OPT_RAW (0x4)
  496. #define CFG_SET_TSF_DBG_FS (0x8)
  497. #define CFG_SET_TSF_PTP_OPT_TSF64_TX (0x10)
  498. #define CFG_SET_TSF_PTP_OPT CFG_INI_UINT( \
  499. "gtsf_ptp_options", \
  500. 0, \
  501. 0xff, \
  502. 0xf, \
  503. CFG_VALUE_OR_DEFAULT, \
  504. "TSF Plus feature options")
  505. #define __CFG_SET_TSF_PTP_OPT CFG(CFG_SET_TSF_PTP_OPT)
  506. #else
  507. #define __CFG_SET_TSF_PTP_OPT
  508. #endif
  509. #ifdef DHCP_SERVER_OFFLOAD
  510. /* <ini>
  511. * gDHCPServerOffloadEnable
  512. * @Min: 0
  513. * @Max: 1
  514. * @Default: 0
  515. *
  516. * DHCP Server offload support
  517. *
  518. * Related: None
  519. *
  520. * Usage: Internal
  521. *
  522. * </ini>
  523. */
  524. #define CFG_DHCP_SERVER_OFFLOAD_SUPPORT CFG_INI_BOOL( \
  525. "gDHCPServerOffloadEnable", \
  526. 0, \
  527. "DHCP Server offload support")
  528. /* <ini>
  529. * gDHCPMaxNumClients
  530. * @Min: 1
  531. * @Max: 8
  532. * @Default: 8
  533. *
  534. * Number of DHCP server offload clients
  535. *
  536. * Related: None
  537. *
  538. * Usage: Internal
  539. *
  540. * </ini>
  541. */
  542. #define CFG_DHCP_SERVER_OFFLOAD_NUM_CLIENT CFG_INI_INT( \
  543. "gDHCPMaxNumClients", \
  544. 1, \
  545. 8, \
  546. 8, \
  547. CFG_VALUE_OR_DEFAULT, \
  548. "Number of DHCP server offload clients")
  549. #define CFG_FWOL_DHCP \
  550. CFG(CFG_DHCP_SERVER_OFFLOAD_SUPPORT) \
  551. CFG(CFG_DHCP_SERVER_OFFLOAD_NUM_CLIENT)
  552. #else
  553. #define CFG_FWOL_DHCP
  554. #endif
  555. /*
  556. * <ini>
  557. * gEnableLPRx - Enable/Disable LPRx
  558. * @Min: 0
  559. * @Max: 1
  560. * @Default: 1
  561. *
  562. * This ini Enables or disables the LPRx in FW
  563. *
  564. * Usage: External
  565. *
  566. * </ini>
  567. */
  568. #define CFG_LPRX CFG_INI_BOOL( \
  569. "gEnableLPRx", \
  570. 1, \
  571. "LPRx control")
  572. #ifdef WLAN_FEATURE_SAE
  573. /*
  574. * <ini>
  575. * sae_enabled - Enable/Disable SAE support in driver
  576. * @Min: 0
  577. * @Max: 1
  578. * @Default: 1
  579. *
  580. * This ini is used to enable/disable SAE support in driver
  581. * Driver will update config to supplicant based on this config.
  582. *
  583. * Related: None
  584. *
  585. * Supported Feature: SAE
  586. * Usage: External
  587. *
  588. * </ini>
  589. */
  590. #define CFG_IS_SAE_ENABLED CFG_INI_BOOL( \
  591. "sae_enabled", \
  592. 1, \
  593. "SAE feature control")
  594. #define __CFG_IS_SAE_ENABLED CFG(CFG_IS_SAE_ENABLED)
  595. #else
  596. #define __CFG_IS_SAE_ENABLED
  597. #endif
  598. /*
  599. * <ini>
  600. * gcmp_enabled - ini to enable/disable GCMP
  601. * @Min: 0
  602. * @Max: 1
  603. * @Default: 1
  604. *
  605. * Currently Firmware update the sequence number for each TID with 2^3
  606. * because of security issues. But with this PN mechanism, throughput drop
  607. * is observed. With this ini FW takes the decision to trade off between
  608. * security and throughput
  609. *
  610. * Supported Feature: STA/SAP/P2P
  611. *
  612. * Usage: External
  613. *
  614. * </ini>
  615. */
  616. #define CFG_ENABLE_GCMP CFG_INI_BOOL( \
  617. "gcmp_enabled", \
  618. 1, \
  619. "GCMP Feature control param")
  620. /*
  621. * <ini>
  622. * gTxSchDelay - Enable/Disable Tx sch delay
  623. * @Min: 0
  624. * @Max: 5
  625. * @Default: 0
  626. *
  627. * Usage: Internal/External
  628. *
  629. * </ini>
  630. */
  631. #define CFG_TX_SCH_DELAY CFG_INI_UINT( \
  632. "gTxSchDelay", \
  633. 0, \
  634. 5, \
  635. 0, \
  636. CFG_VALUE_OR_DEFAULT, \
  637. "Enable/Disable Tx sch delay")
  638. /*
  639. * <ini>
  640. * gEnableSecondaryRate - Enable/Disable Secondary Retry Rate feature subset
  641. *
  642. * @Min: 0x0
  643. * @Max: 0x3F
  644. * @Default: 0x17
  645. *
  646. * It is a 32 bit value such that the various bits represent as below -
  647. * Bit-0 : is Enable/Disable Control for "PPDU Secondary Retry Support"
  648. * Bit-1 : is Enable/Disable Control for "RTS Black/White-listing Support"
  649. * Bit-2 : is Enable/Disable Control for "Higher MCS retry restriction
  650. * on XRETRY failures"
  651. * Bit 3-5 : is "Xretry threshold" to use
  652. * Bit 3~31 : reserved for future use.
  653. *
  654. * Usage: External
  655. *
  656. * </ini>
  657. */
  658. #define CFG_ENABLE_SECONDARY_RATE CFG_INI_UINT( \
  659. "gEnableSecondaryRate", \
  660. 0, \
  661. 0x3f, \
  662. 0x17, \
  663. CFG_VALUE_OR_DEFAULT, \
  664. "Secondary Retry Rate feature subset control")
  665. #define CFG_FWOL_GENERIC_ALL \
  666. CFG_FWOL_DHCP \
  667. CFG(CFG_ENABLE_ANI) \
  668. CFG(CFG_SET_RTS_FOR_SIFS_BURSTING) \
  669. CFG(CFG_MAX_MPDUS_IN_AMPDU) \
  670. CFG(CFG_ARP_AC_CATEGORY) \
  671. CFG(CFG_ENABLE_PHY_REG) \
  672. CFG(CFG_UPPER_BRSSI_THRESH) \
  673. CFG(CFG_LOWER_BRSSI_THRESH) \
  674. CFG(CFG_DTIM_1CHRX_ENABLE) \
  675. CFG(CFG_ENABLE_COEX_ALT_CHAINMASK) \
  676. CFG(CFG_ENABLE_SMART_CHAINMASK) \
  677. CFG(CFG_ENABLE_FW_RTS_PROFILE) \
  678. CFG(CFG_ENABLE_FW_DEBUG_LOG_LEVEL) \
  679. CFG(CFG_ENABLE_FW_LOG_TYPE) \
  680. CFG(CFG_ENABLE_FW_MODULE_LOG_LEVEL) \
  681. CFG(CFG_RA_FILTER_ENABLE) \
  682. CFG(CFG_SET_TSF_GPIO_PIN) \
  683. __CFG_SET_TSF_IRQ_HOST_GPIO_PIN \
  684. __CFG_SET_TSF_SYNC_HOST_GPIO_PIN \
  685. __CFG_SET_TSF_PTP_OPT \
  686. CFG(CFG_LPRX) \
  687. __CFG_IS_SAE_ENABLED \
  688. CFG(CFG_ENABLE_GCMP) \
  689. CFG(CFG_TX_SCH_DELAY) \
  690. CFG(CFG_ENABLE_SECONDARY_RATE)
  691. #endif