dp_tx.c 170 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <wlan_dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. #ifdef CONFIG_SAWF
  53. #include <dp_sawf.h>
  54. #endif
  55. /* Flag to skip CCE classify when mesh or tid override enabled */
  56. #define DP_TX_SKIP_CCE_CLASSIFY \
  57. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  58. /* TODO Add support in TSO */
  59. #define DP_DESC_NUM_FRAG(x) 0
  60. /* disable TQM_BYPASS */
  61. #define TQM_BYPASS_WAR 0
  62. /* invalid peer id for reinject*/
  63. #define DP_INVALID_PEER 0XFFFE
  64. #define DP_RETRY_COUNT 7
  65. #ifdef WLAN_PEER_JITTER
  66. #define DP_AVG_JITTER_WEIGHT_DENOM 4
  67. #define DP_AVG_DELAY_WEIGHT_DENOM 3
  68. #endif
  69. #ifdef QCA_DP_TX_FW_METADATA_V2
  70. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  71. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  74. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  75. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  76. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  77. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  78. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  79. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  80. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  81. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  82. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  83. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  84. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  85. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  86. #else
  87. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  88. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  91. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  92. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  93. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  94. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  95. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  96. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  97. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  98. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  99. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  100. HTT_TCL_METADATA_TYPE_PEER_BASED
  101. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  102. HTT_TCL_METADATA_TYPE_VDEV_BASED
  103. #endif
  104. /*mapping between hal encrypt type and cdp_sec_type*/
  105. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  106. HAL_TX_ENCRYPT_TYPE_WEP_128,
  107. HAL_TX_ENCRYPT_TYPE_WEP_104,
  108. HAL_TX_ENCRYPT_TYPE_WEP_40,
  109. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  110. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  111. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  112. HAL_TX_ENCRYPT_TYPE_WAPI,
  113. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  114. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  115. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  116. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  117. qdf_export_symbol(sec_type_map);
  118. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  119. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  120. {
  121. enum dp_tx_event_type type;
  122. if (flags & DP_TX_DESC_FLAG_FLUSH)
  123. type = DP_TX_DESC_FLUSH;
  124. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  125. type = DP_TX_COMP_UNMAP_ERR;
  126. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  127. type = DP_TX_COMP_UNMAP;
  128. else
  129. type = DP_TX_DESC_UNMAP;
  130. return type;
  131. }
  132. static inline void
  133. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  134. qdf_nbuf_t skb, uint32_t sw_cookie,
  135. enum dp_tx_event_type type)
  136. {
  137. struct dp_tx_tcl_history *tx_tcl_history = &soc->tx_tcl_history;
  138. struct dp_tx_comp_history *tx_comp_history = &soc->tx_comp_history;
  139. struct dp_tx_desc_event *entry;
  140. uint32_t idx;
  141. uint16_t slot;
  142. switch (type) {
  143. case DP_TX_COMP_UNMAP:
  144. case DP_TX_COMP_UNMAP_ERR:
  145. case DP_TX_COMP_MSDU_EXT:
  146. if (qdf_unlikely(!tx_comp_history->allocated))
  147. return;
  148. dp_get_frag_hist_next_atomic_idx(&tx_comp_history->index, &idx,
  149. &slot,
  150. DP_TX_COMP_HIST_SLOT_SHIFT,
  151. DP_TX_COMP_HIST_PER_SLOT_MAX,
  152. DP_TX_COMP_HISTORY_SIZE);
  153. entry = &tx_comp_history->entry[slot][idx];
  154. break;
  155. case DP_TX_DESC_MAP:
  156. case DP_TX_DESC_UNMAP:
  157. case DP_TX_DESC_COOKIE:
  158. case DP_TX_DESC_FLUSH:
  159. if (qdf_unlikely(!tx_tcl_history->allocated))
  160. return;
  161. dp_get_frag_hist_next_atomic_idx(&tx_tcl_history->index, &idx,
  162. &slot,
  163. DP_TX_TCL_HIST_SLOT_SHIFT,
  164. DP_TX_TCL_HIST_PER_SLOT_MAX,
  165. DP_TX_TCL_HISTORY_SIZE);
  166. entry = &tx_tcl_history->entry[slot][idx];
  167. break;
  168. default:
  169. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  170. return;
  171. }
  172. entry->skb = skb;
  173. entry->paddr = paddr;
  174. entry->sw_cookie = sw_cookie;
  175. entry->type = type;
  176. entry->ts = qdf_get_log_timestamp();
  177. }
  178. static inline void
  179. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  180. struct qdf_tso_seg_elem_t *tso_seg,
  181. qdf_nbuf_t skb, uint32_t sw_cookie,
  182. enum dp_tx_event_type type)
  183. {
  184. int i;
  185. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  186. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  187. skb, sw_cookie, type);
  188. }
  189. if (!tso_seg->next)
  190. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  191. skb, 0xFFFFFFFF, type);
  192. }
  193. static inline void
  194. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  195. qdf_nbuf_t skb, uint32_t sw_cookie,
  196. enum dp_tx_event_type type)
  197. {
  198. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  199. uint32_t num_segs = tso_info.num_segs;
  200. while (num_segs) {
  201. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  202. curr_seg = curr_seg->next;
  203. num_segs--;
  204. }
  205. }
  206. #else
  207. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  208. {
  209. return DP_TX_DESC_INVAL_EVT;
  210. }
  211. static inline void
  212. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  213. qdf_nbuf_t skb, uint32_t sw_cookie,
  214. enum dp_tx_event_type type)
  215. {
  216. }
  217. static inline void
  218. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  219. struct qdf_tso_seg_elem_t *tso_seg,
  220. qdf_nbuf_t skb, uint32_t sw_cookie,
  221. enum dp_tx_event_type type)
  222. {
  223. }
  224. static inline void
  225. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  226. qdf_nbuf_t skb, uint32_t sw_cookie,
  227. enum dp_tx_event_type type)
  228. {
  229. }
  230. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  231. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  232. /**
  233. * dp_is_tput_high() - Check if throughput is high
  234. *
  235. * @soc - core txrx main context
  236. *
  237. * The current function is based of the RTPM tput policy variable where RTPM is
  238. * avoided based on throughput.
  239. */
  240. static inline int dp_is_tput_high(struct dp_soc *soc)
  241. {
  242. return dp_get_rtpm_tput_policy_requirement(soc);
  243. }
  244. #if defined(FEATURE_TSO)
  245. /**
  246. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  247. *
  248. * @soc - core txrx main context
  249. * @seg_desc - tso segment descriptor
  250. * @num_seg_desc - tso number segment descriptor
  251. */
  252. static void dp_tx_tso_unmap_segment(
  253. struct dp_soc *soc,
  254. struct qdf_tso_seg_elem_t *seg_desc,
  255. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  256. {
  257. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  258. if (qdf_unlikely(!seg_desc)) {
  259. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  260. __func__, __LINE__);
  261. qdf_assert(0);
  262. } else if (qdf_unlikely(!num_seg_desc)) {
  263. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  264. __func__, __LINE__);
  265. qdf_assert(0);
  266. } else {
  267. bool is_last_seg;
  268. /* no tso segment left to do dma unmap */
  269. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  270. return;
  271. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  272. true : false;
  273. qdf_nbuf_unmap_tso_segment(soc->osdev,
  274. seg_desc, is_last_seg);
  275. num_seg_desc->num_seg.tso_cmn_num_seg--;
  276. }
  277. }
  278. /**
  279. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  280. * back to the freelist
  281. *
  282. * @soc - soc device handle
  283. * @tx_desc - Tx software descriptor
  284. */
  285. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  286. struct dp_tx_desc_s *tx_desc)
  287. {
  288. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  289. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  290. dp_tx_err("SO desc is NULL!");
  291. qdf_assert(0);
  292. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  293. dp_tx_err("TSO num desc is NULL!");
  294. qdf_assert(0);
  295. } else {
  296. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  297. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  298. msdu_ext_desc->tso_num_desc;
  299. /* Add the tso num segment into the free list */
  300. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  301. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  302. tx_desc->msdu_ext_desc->
  303. tso_num_desc);
  304. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  305. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  306. }
  307. /* Add the tso segment into the free list*/
  308. dp_tx_tso_desc_free(soc,
  309. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  310. tso_desc);
  311. tx_desc->msdu_ext_desc->tso_desc = NULL;
  312. }
  313. }
  314. #else
  315. static void dp_tx_tso_unmap_segment(
  316. struct dp_soc *soc,
  317. struct qdf_tso_seg_elem_t *seg_desc,
  318. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  319. {
  320. }
  321. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  322. struct dp_tx_desc_s *tx_desc)
  323. {
  324. }
  325. #endif
  326. /**
  327. * dp_tx_desc_release() - Release Tx Descriptor
  328. * @tx_desc : Tx Descriptor
  329. * @desc_pool_id: Descriptor Pool ID
  330. *
  331. * Deallocate all resources attached to Tx descriptor and free the Tx
  332. * descriptor.
  333. *
  334. * Return:
  335. */
  336. void
  337. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  338. {
  339. struct dp_pdev *pdev = tx_desc->pdev;
  340. struct dp_soc *soc;
  341. uint8_t comp_status = 0;
  342. qdf_assert(pdev);
  343. soc = pdev->soc;
  344. dp_tx_outstanding_dec(pdev);
  345. if (tx_desc->msdu_ext_desc) {
  346. if (tx_desc->frm_type == dp_tx_frm_tso)
  347. dp_tx_tso_desc_release(soc, tx_desc);
  348. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  349. dp_tx_me_free_buf(tx_desc->pdev,
  350. tx_desc->msdu_ext_desc->me_buffer);
  351. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  352. }
  353. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  354. qdf_atomic_dec(&soc->num_tx_exception);
  355. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  356. tx_desc->buffer_src)
  357. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  358. soc->hal_soc);
  359. else
  360. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  361. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  362. tx_desc->id, comp_status,
  363. qdf_atomic_read(&pdev->num_tx_outstanding));
  364. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  365. return;
  366. }
  367. /**
  368. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  369. * @vdev: DP vdev Handle
  370. * @nbuf: skb
  371. * @msdu_info: msdu_info required to create HTT metadata
  372. *
  373. * Prepares and fills HTT metadata in the frame pre-header for special frames
  374. * that should be transmitted using varying transmit parameters.
  375. * There are 2 VDEV modes that currently needs this special metadata -
  376. * 1) Mesh Mode
  377. * 2) DSRC Mode
  378. *
  379. * Return: HTT metadata size
  380. *
  381. */
  382. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  383. struct dp_tx_msdu_info_s *msdu_info)
  384. {
  385. uint32_t *meta_data = msdu_info->meta_data;
  386. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  387. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  388. uint8_t htt_desc_size;
  389. /* Size rounded of multiple of 8 bytes */
  390. uint8_t htt_desc_size_aligned;
  391. uint8_t *hdr = NULL;
  392. /*
  393. * Metadata - HTT MSDU Extension header
  394. */
  395. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  396. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  397. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  398. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  399. meta_data[0]) ||
  400. msdu_info->exception_fw) {
  401. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  402. htt_desc_size_aligned)) {
  403. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  404. htt_desc_size_aligned);
  405. if (!nbuf) {
  406. /*
  407. * qdf_nbuf_realloc_headroom won't do skb_clone
  408. * as skb_realloc_headroom does. so, no free is
  409. * needed here.
  410. */
  411. DP_STATS_INC(vdev,
  412. tx_i.dropped.headroom_insufficient,
  413. 1);
  414. qdf_print(" %s[%d] skb_realloc_headroom failed",
  415. __func__, __LINE__);
  416. return 0;
  417. }
  418. }
  419. /* Fill and add HTT metaheader */
  420. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  421. if (!hdr) {
  422. dp_tx_err("Error in filling HTT metadata");
  423. return 0;
  424. }
  425. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  426. } else if (vdev->opmode == wlan_op_mode_ocb) {
  427. /* Todo - Add support for DSRC */
  428. }
  429. return htt_desc_size_aligned;
  430. }
  431. /**
  432. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  433. * @tso_seg: TSO segment to process
  434. * @ext_desc: Pointer to MSDU extension descriptor
  435. *
  436. * Return: void
  437. */
  438. #if defined(FEATURE_TSO)
  439. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  440. void *ext_desc)
  441. {
  442. uint8_t num_frag;
  443. uint32_t tso_flags;
  444. /*
  445. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  446. * tcp_flag_mask
  447. *
  448. * Checksum enable flags are set in TCL descriptor and not in Extension
  449. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  450. */
  451. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  452. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  453. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  454. tso_seg->tso_flags.ip_len);
  455. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  456. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  457. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  458. uint32_t lo = 0;
  459. uint32_t hi = 0;
  460. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  461. (tso_seg->tso_frags[num_frag].length));
  462. qdf_dmaaddr_to_32s(
  463. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  464. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  465. tso_seg->tso_frags[num_frag].length);
  466. }
  467. return;
  468. }
  469. #else
  470. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  471. void *ext_desc)
  472. {
  473. return;
  474. }
  475. #endif
  476. #if defined(FEATURE_TSO)
  477. /**
  478. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  479. * allocated and free them
  480. *
  481. * @soc: soc handle
  482. * @free_seg: list of tso segments
  483. * @msdu_info: msdu descriptor
  484. *
  485. * Return - void
  486. */
  487. static void dp_tx_free_tso_seg_list(
  488. struct dp_soc *soc,
  489. struct qdf_tso_seg_elem_t *free_seg,
  490. struct dp_tx_msdu_info_s *msdu_info)
  491. {
  492. struct qdf_tso_seg_elem_t *next_seg;
  493. while (free_seg) {
  494. next_seg = free_seg->next;
  495. dp_tx_tso_desc_free(soc,
  496. msdu_info->tx_queue.desc_pool_id,
  497. free_seg);
  498. free_seg = next_seg;
  499. }
  500. }
  501. /**
  502. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  503. * allocated and free them
  504. *
  505. * @soc: soc handle
  506. * @free_num_seg: list of tso number segments
  507. * @msdu_info: msdu descriptor
  508. * Return - void
  509. */
  510. static void dp_tx_free_tso_num_seg_list(
  511. struct dp_soc *soc,
  512. struct qdf_tso_num_seg_elem_t *free_num_seg,
  513. struct dp_tx_msdu_info_s *msdu_info)
  514. {
  515. struct qdf_tso_num_seg_elem_t *next_num_seg;
  516. while (free_num_seg) {
  517. next_num_seg = free_num_seg->next;
  518. dp_tso_num_seg_free(soc,
  519. msdu_info->tx_queue.desc_pool_id,
  520. free_num_seg);
  521. free_num_seg = next_num_seg;
  522. }
  523. }
  524. /**
  525. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  526. * do dma unmap for each segment
  527. *
  528. * @soc: soc handle
  529. * @free_seg: list of tso segments
  530. * @num_seg_desc: tso number segment descriptor
  531. *
  532. * Return - void
  533. */
  534. static void dp_tx_unmap_tso_seg_list(
  535. struct dp_soc *soc,
  536. struct qdf_tso_seg_elem_t *free_seg,
  537. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  538. {
  539. struct qdf_tso_seg_elem_t *next_seg;
  540. if (qdf_unlikely(!num_seg_desc)) {
  541. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  542. return;
  543. }
  544. while (free_seg) {
  545. next_seg = free_seg->next;
  546. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  547. free_seg = next_seg;
  548. }
  549. }
  550. #ifdef FEATURE_TSO_STATS
  551. /**
  552. * dp_tso_get_stats_idx: Retrieve the tso packet id
  553. * @pdev - pdev handle
  554. *
  555. * Return: id
  556. */
  557. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  558. {
  559. uint32_t stats_idx;
  560. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  561. % CDP_MAX_TSO_PACKETS);
  562. return stats_idx;
  563. }
  564. #else
  565. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  566. {
  567. return 0;
  568. }
  569. #endif /* FEATURE_TSO_STATS */
  570. /**
  571. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  572. * free the tso segments descriptor and
  573. * tso num segments descriptor
  574. *
  575. * @soc: soc handle
  576. * @msdu_info: msdu descriptor
  577. * @tso_seg_unmap: flag to show if dma unmap is necessary
  578. *
  579. * Return - void
  580. */
  581. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  582. struct dp_tx_msdu_info_s *msdu_info,
  583. bool tso_seg_unmap)
  584. {
  585. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  586. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  587. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  588. tso_info->tso_num_seg_list;
  589. /* do dma unmap for each segment */
  590. if (tso_seg_unmap)
  591. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  592. /* free all tso number segment descriptor though looks only have 1 */
  593. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  594. /* free all tso segment descriptor */
  595. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  596. }
  597. /**
  598. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  599. * @vdev: virtual device handle
  600. * @msdu: network buffer
  601. * @msdu_info: meta data associated with the msdu
  602. *
  603. * Return: QDF_STATUS_SUCCESS success
  604. */
  605. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  606. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  607. {
  608. struct qdf_tso_seg_elem_t *tso_seg;
  609. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  610. struct dp_soc *soc = vdev->pdev->soc;
  611. struct dp_pdev *pdev = vdev->pdev;
  612. struct qdf_tso_info_t *tso_info;
  613. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  614. tso_info = &msdu_info->u.tso_info;
  615. tso_info->curr_seg = NULL;
  616. tso_info->tso_seg_list = NULL;
  617. tso_info->num_segs = num_seg;
  618. msdu_info->frm_type = dp_tx_frm_tso;
  619. tso_info->tso_num_seg_list = NULL;
  620. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  621. while (num_seg) {
  622. tso_seg = dp_tx_tso_desc_alloc(
  623. soc, msdu_info->tx_queue.desc_pool_id);
  624. if (tso_seg) {
  625. tso_seg->next = tso_info->tso_seg_list;
  626. tso_info->tso_seg_list = tso_seg;
  627. num_seg--;
  628. } else {
  629. dp_err_rl("Failed to alloc tso seg desc");
  630. DP_STATS_INC_PKT(vdev->pdev,
  631. tso_stats.tso_no_mem_dropped, 1,
  632. qdf_nbuf_len(msdu));
  633. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  634. return QDF_STATUS_E_NOMEM;
  635. }
  636. }
  637. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  638. tso_num_seg = dp_tso_num_seg_alloc(soc,
  639. msdu_info->tx_queue.desc_pool_id);
  640. if (tso_num_seg) {
  641. tso_num_seg->next = tso_info->tso_num_seg_list;
  642. tso_info->tso_num_seg_list = tso_num_seg;
  643. } else {
  644. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  645. __func__);
  646. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  647. return QDF_STATUS_E_NOMEM;
  648. }
  649. msdu_info->num_seg =
  650. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  651. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  652. msdu_info->num_seg);
  653. if (!(msdu_info->num_seg)) {
  654. /*
  655. * Free allocated TSO seg desc and number seg desc,
  656. * do unmap for segments if dma map has done.
  657. */
  658. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  659. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  660. return QDF_STATUS_E_INVAL;
  661. }
  662. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  663. msdu, 0, DP_TX_DESC_MAP);
  664. tso_info->curr_seg = tso_info->tso_seg_list;
  665. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  666. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  667. msdu, msdu_info->num_seg);
  668. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  669. tso_info->msdu_stats_idx);
  670. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  671. return QDF_STATUS_SUCCESS;
  672. }
  673. #else
  674. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  675. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  676. {
  677. return QDF_STATUS_E_NOMEM;
  678. }
  679. #endif
  680. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  681. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  682. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  683. /**
  684. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  685. * @vdev: DP Vdev handle
  686. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  687. * @desc_pool_id: Descriptor Pool ID
  688. *
  689. * Return:
  690. */
  691. static
  692. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  693. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  694. {
  695. uint8_t i;
  696. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  697. struct dp_tx_seg_info_s *seg_info;
  698. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  699. struct dp_soc *soc = vdev->pdev->soc;
  700. /* Allocate an extension descriptor */
  701. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  702. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  703. if (!msdu_ext_desc) {
  704. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  705. return NULL;
  706. }
  707. if (msdu_info->exception_fw &&
  708. qdf_unlikely(vdev->mesh_vdev)) {
  709. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  710. &msdu_info->meta_data[0],
  711. sizeof(struct htt_tx_msdu_desc_ext2_t));
  712. qdf_atomic_inc(&soc->num_tx_exception);
  713. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  714. }
  715. switch (msdu_info->frm_type) {
  716. case dp_tx_frm_sg:
  717. case dp_tx_frm_me:
  718. case dp_tx_frm_raw:
  719. seg_info = msdu_info->u.sg_info.curr_seg;
  720. /* Update the buffer pointers in MSDU Extension Descriptor */
  721. for (i = 0; i < seg_info->frag_cnt; i++) {
  722. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  723. seg_info->frags[i].paddr_lo,
  724. seg_info->frags[i].paddr_hi,
  725. seg_info->frags[i].len);
  726. }
  727. break;
  728. case dp_tx_frm_tso:
  729. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  730. &cached_ext_desc[0]);
  731. break;
  732. default:
  733. break;
  734. }
  735. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  736. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  737. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  738. msdu_ext_desc->vaddr);
  739. return msdu_ext_desc;
  740. }
  741. /**
  742. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  743. *
  744. * @skb: skb to be traced
  745. * @msdu_id: msdu_id of the packet
  746. * @vdev_id: vdev_id of the packet
  747. *
  748. * Return: None
  749. */
  750. #ifdef DP_DISABLE_TX_PKT_TRACE
  751. static void dp_tx_trace_pkt(struct dp_soc *soc,
  752. qdf_nbuf_t skb, uint16_t msdu_id,
  753. uint8_t vdev_id)
  754. {
  755. }
  756. #else
  757. static void dp_tx_trace_pkt(struct dp_soc *soc,
  758. qdf_nbuf_t skb, uint16_t msdu_id,
  759. uint8_t vdev_id)
  760. {
  761. if (dp_is_tput_high(soc))
  762. return;
  763. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  764. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  765. DPTRACE(qdf_dp_trace_ptr(skb,
  766. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  767. QDF_TRACE_DEFAULT_PDEV_ID,
  768. qdf_nbuf_data_addr(skb),
  769. sizeof(qdf_nbuf_data(skb)),
  770. msdu_id, vdev_id, 0));
  771. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  772. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  773. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  774. msdu_id, QDF_TX));
  775. }
  776. #endif
  777. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  778. /**
  779. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  780. * exception by the upper layer (OS_IF)
  781. * @soc: DP soc handle
  782. * @nbuf: packet to be transmitted
  783. *
  784. * Returns: 1 if the packet is marked as exception,
  785. * 0, if the packet is not marked as exception.
  786. */
  787. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  788. qdf_nbuf_t nbuf)
  789. {
  790. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  791. }
  792. #else
  793. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  794. qdf_nbuf_t nbuf)
  795. {
  796. return 0;
  797. }
  798. #endif
  799. #ifdef DP_TRAFFIC_END_INDICATION
  800. /**
  801. * dp_tx_get_traffic_end_indication_pkt() - Allocate and prepare packet to send
  802. * as indication to fw to inform that
  803. * data stream has ended
  804. * @vdev: DP vdev handle
  805. * @nbuf: original buffer from network stack
  806. *
  807. * Return: NULL on failure,
  808. * nbuf on success
  809. */
  810. static inline qdf_nbuf_t
  811. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  812. qdf_nbuf_t nbuf)
  813. {
  814. /* Packet length should be enough to copy upto L3 header */
  815. uint8_t end_nbuf_len = 64;
  816. uint8_t htt_desc_size_aligned;
  817. uint8_t htt_desc_size;
  818. qdf_nbuf_t end_nbuf;
  819. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  820. QDF_NBUF_CB_PACKET_TYPE_END_INDICATION)) {
  821. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  822. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  823. end_nbuf = qdf_nbuf_queue_remove(&vdev->end_ind_pkt_q);
  824. if (!end_nbuf) {
  825. end_nbuf = qdf_nbuf_alloc(NULL,
  826. (htt_desc_size_aligned +
  827. end_nbuf_len),
  828. htt_desc_size_aligned,
  829. 8, false);
  830. if (!end_nbuf) {
  831. dp_err("Packet allocation failed");
  832. goto out;
  833. }
  834. } else {
  835. qdf_nbuf_reset(end_nbuf, htt_desc_size_aligned, 8);
  836. }
  837. qdf_mem_copy(qdf_nbuf_data(end_nbuf), qdf_nbuf_data(nbuf),
  838. end_nbuf_len);
  839. qdf_nbuf_set_pktlen(end_nbuf, end_nbuf_len);
  840. return end_nbuf;
  841. }
  842. out:
  843. return NULL;
  844. }
  845. /**
  846. * dp_tx_send_traffic_end_indication_pkt() - Send indication packet to FW
  847. * via exception path.
  848. * @vdev: DP vdev handle
  849. * @end_nbuf: skb to send as indication
  850. * @msdu_info: msdu_info of original nbuf
  851. * @peer_id: peer id
  852. *
  853. * Return: None
  854. */
  855. static inline void
  856. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  857. qdf_nbuf_t end_nbuf,
  858. struct dp_tx_msdu_info_s *msdu_info,
  859. uint16_t peer_id)
  860. {
  861. struct dp_tx_msdu_info_s e_msdu_info = {0};
  862. qdf_nbuf_t nbuf;
  863. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  864. (struct htt_tx_msdu_desc_ext2_t *)(e_msdu_info.meta_data);
  865. e_msdu_info.tx_queue = msdu_info->tx_queue;
  866. e_msdu_info.tid = msdu_info->tid;
  867. e_msdu_info.exception_fw = 1;
  868. desc_ext->host_tx_desc_pool = 1;
  869. desc_ext->traffic_end_indication = 1;
  870. nbuf = dp_tx_send_msdu_single(vdev, end_nbuf, &e_msdu_info,
  871. peer_id, NULL);
  872. if (nbuf) {
  873. dp_err("Traffic end indication packet tx failed");
  874. qdf_nbuf_free(nbuf);
  875. }
  876. }
  877. /**
  878. * dp_tx_traffic_end_indication_set_desc_flag() - Set tx descriptor flag to
  879. * mark it traffic end indication
  880. * packet.
  881. * @tx_desc: Tx descriptor pointer
  882. * @msdu_info: msdu_info structure pointer
  883. *
  884. * Return: None
  885. */
  886. static inline void
  887. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  888. struct dp_tx_msdu_info_s *msdu_info)
  889. {
  890. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  891. (struct htt_tx_msdu_desc_ext2_t *)(msdu_info->meta_data);
  892. if (qdf_unlikely(desc_ext->traffic_end_indication))
  893. tx_desc->flags |= DP_TX_DESC_FLAG_TRAFFIC_END_IND;
  894. }
  895. /**
  896. * dp_tx_traffic_end_indication_enq_ind_pkt() - Enqueue the packet instead of
  897. * freeing which are associated
  898. * with traffic end indication
  899. * flagged descriptor.
  900. * @soc: dp soc handle
  901. * @desc: Tx descriptor pointer
  902. * @nbuf: buffer pointer
  903. *
  904. * Return: True if packet gets enqueued else false
  905. */
  906. static bool
  907. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  908. struct dp_tx_desc_s *desc,
  909. qdf_nbuf_t nbuf)
  910. {
  911. struct dp_vdev *vdev = NULL;
  912. if (qdf_unlikely((desc->flags &
  913. DP_TX_DESC_FLAG_TRAFFIC_END_IND) != 0)) {
  914. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  915. DP_MOD_ID_TX_COMP);
  916. if (vdev) {
  917. qdf_nbuf_queue_add(&vdev->end_ind_pkt_q, nbuf);
  918. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_COMP);
  919. return true;
  920. }
  921. }
  922. return false;
  923. }
  924. /**
  925. * dp_tx_traffic_end_indication_is_enabled() - get the feature
  926. * enable/disable status
  927. * @vdev: dp vdev handle
  928. *
  929. * Return: True if feature is enable else false
  930. */
  931. static inline bool
  932. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  933. {
  934. return qdf_unlikely(vdev->traffic_end_ind_en);
  935. }
  936. static inline qdf_nbuf_t
  937. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  938. struct dp_tx_msdu_info_s *msdu_info,
  939. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  940. {
  941. if (dp_tx_traffic_end_indication_is_enabled(vdev))
  942. end_nbuf = dp_tx_get_traffic_end_indication_pkt(vdev, nbuf);
  943. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  944. if (qdf_unlikely(end_nbuf))
  945. dp_tx_send_traffic_end_indication_pkt(vdev, end_nbuf,
  946. msdu_info, peer_id);
  947. return nbuf;
  948. }
  949. #else
  950. static inline qdf_nbuf_t
  951. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  952. qdf_nbuf_t nbuf)
  953. {
  954. return NULL;
  955. }
  956. static inline void
  957. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  958. qdf_nbuf_t end_nbuf,
  959. struct dp_tx_msdu_info_s *msdu_info,
  960. uint16_t peer_id)
  961. {}
  962. static inline void
  963. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  964. struct dp_tx_msdu_info_s *msdu_info)
  965. {}
  966. static inline bool
  967. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  968. struct dp_tx_desc_s *desc,
  969. qdf_nbuf_t nbuf)
  970. {
  971. return false;
  972. }
  973. static inline bool
  974. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  975. {
  976. return false;
  977. }
  978. static inline qdf_nbuf_t
  979. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  980. struct dp_tx_msdu_info_s *msdu_info,
  981. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  982. {
  983. return dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  984. }
  985. #endif
  986. /**
  987. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  988. * @vdev: DP vdev handle
  989. * @nbuf: skb
  990. * @desc_pool_id: Descriptor pool ID
  991. * @meta_data: Metadata to the fw
  992. * @tx_exc_metadata: Handle that holds exception path metadata
  993. * Allocate and prepare Tx descriptor with msdu information.
  994. *
  995. * Return: Pointer to Tx Descriptor on success,
  996. * NULL on failure
  997. */
  998. static
  999. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  1000. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  1001. struct dp_tx_msdu_info_s *msdu_info,
  1002. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1003. {
  1004. uint8_t align_pad;
  1005. uint8_t is_exception = 0;
  1006. uint8_t htt_hdr_size;
  1007. struct dp_tx_desc_s *tx_desc;
  1008. struct dp_pdev *pdev = vdev->pdev;
  1009. struct dp_soc *soc = pdev->soc;
  1010. if (dp_tx_limit_check(vdev))
  1011. return NULL;
  1012. /* Allocate software Tx descriptor */
  1013. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1014. if (qdf_unlikely(!tx_desc)) {
  1015. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1016. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  1017. return NULL;
  1018. }
  1019. dp_tx_outstanding_inc(pdev);
  1020. /* Initialize the SW tx descriptor */
  1021. tx_desc->nbuf = nbuf;
  1022. tx_desc->frm_type = dp_tx_frm_std;
  1023. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  1024. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  1025. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  1026. tx_desc->vdev_id = vdev->vdev_id;
  1027. tx_desc->pdev = pdev;
  1028. tx_desc->msdu_ext_desc = NULL;
  1029. tx_desc->pkt_offset = 0;
  1030. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1031. tx_desc->shinfo_addr = skb_end_pointer(nbuf);
  1032. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1033. if (qdf_unlikely(vdev->multipass_en)) {
  1034. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  1035. goto failure;
  1036. }
  1037. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  1038. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  1039. is_exception = 1;
  1040. /*
  1041. * For special modes (vdev_type == ocb or mesh), data frames should be
  1042. * transmitted using varying transmit parameters (tx spec) which include
  1043. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  1044. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  1045. * These frames are sent as exception packets to firmware.
  1046. *
  1047. * HW requirement is that metadata should always point to a
  1048. * 8-byte aligned address. So we add alignment pad to start of buffer.
  1049. * HTT Metadata should be ensured to be multiple of 8-bytes,
  1050. * to get 8-byte aligned start address along with align_pad added
  1051. *
  1052. * |-----------------------------|
  1053. * | |
  1054. * |-----------------------------| <-----Buffer Pointer Address given
  1055. * | | ^ in HW descriptor (aligned)
  1056. * | HTT Metadata | |
  1057. * | | |
  1058. * | | | Packet Offset given in descriptor
  1059. * | | |
  1060. * |-----------------------------| |
  1061. * | Alignment Pad | v
  1062. * |-----------------------------| <----- Actual buffer start address
  1063. * | SKB Data | (Unaligned)
  1064. * | |
  1065. * | |
  1066. * | |
  1067. * | |
  1068. * | |
  1069. * |-----------------------------|
  1070. */
  1071. if (qdf_unlikely((msdu_info->exception_fw)) ||
  1072. (vdev->opmode == wlan_op_mode_ocb) ||
  1073. (tx_exc_metadata &&
  1074. tx_exc_metadata->is_tx_sniffer)) {
  1075. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  1076. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1077. DP_STATS_INC(vdev,
  1078. tx_i.dropped.headroom_insufficient, 1);
  1079. goto failure;
  1080. }
  1081. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1082. dp_tx_err("qdf_nbuf_push_head failed");
  1083. goto failure;
  1084. }
  1085. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1086. msdu_info);
  1087. if (htt_hdr_size == 0)
  1088. goto failure;
  1089. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1090. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1091. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1092. dp_tx_traffic_end_indication_set_desc_flag(tx_desc,
  1093. msdu_info);
  1094. is_exception = 1;
  1095. tx_desc->length -= tx_desc->pkt_offset;
  1096. }
  1097. #if !TQM_BYPASS_WAR
  1098. if (is_exception || tx_exc_metadata)
  1099. #endif
  1100. {
  1101. /* Temporary WAR due to TQM VP issues */
  1102. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1103. qdf_atomic_inc(&soc->num_tx_exception);
  1104. }
  1105. return tx_desc;
  1106. failure:
  1107. dp_tx_desc_release(tx_desc, desc_pool_id);
  1108. return NULL;
  1109. }
  1110. /**
  1111. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  1112. * @vdev: DP vdev handle
  1113. * @nbuf: skb
  1114. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1115. * @desc_pool_id : Descriptor Pool ID
  1116. *
  1117. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1118. * information. For frames with fragments, allocate and prepare
  1119. * an MSDU extension descriptor
  1120. *
  1121. * Return: Pointer to Tx Descriptor on success,
  1122. * NULL on failure
  1123. */
  1124. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1125. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1126. uint8_t desc_pool_id)
  1127. {
  1128. struct dp_tx_desc_s *tx_desc;
  1129. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1130. struct dp_pdev *pdev = vdev->pdev;
  1131. struct dp_soc *soc = pdev->soc;
  1132. if (dp_tx_limit_check(vdev))
  1133. return NULL;
  1134. /* Allocate software Tx descriptor */
  1135. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1136. if (!tx_desc) {
  1137. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1138. return NULL;
  1139. }
  1140. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1141. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1142. dp_tx_outstanding_inc(pdev);
  1143. /* Initialize the SW tx descriptor */
  1144. tx_desc->nbuf = nbuf;
  1145. tx_desc->frm_type = msdu_info->frm_type;
  1146. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1147. tx_desc->vdev_id = vdev->vdev_id;
  1148. tx_desc->pdev = pdev;
  1149. tx_desc->pkt_offset = 0;
  1150. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1151. /* Handle scattered frames - TSO/SG/ME */
  1152. /* Allocate and prepare an extension descriptor for scattered frames */
  1153. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1154. if (!msdu_ext_desc) {
  1155. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1156. goto failure;
  1157. }
  1158. #if TQM_BYPASS_WAR
  1159. /* Temporary WAR due to TQM VP issues */
  1160. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1161. qdf_atomic_inc(&soc->num_tx_exception);
  1162. #endif
  1163. if (qdf_unlikely(msdu_info->exception_fw))
  1164. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1165. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1166. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1167. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1168. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1169. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1170. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1171. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1172. else
  1173. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1174. return tx_desc;
  1175. failure:
  1176. dp_tx_desc_release(tx_desc, desc_pool_id);
  1177. return NULL;
  1178. }
  1179. /**
  1180. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1181. * @vdev: DP vdev handle
  1182. * @nbuf: buffer pointer
  1183. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1184. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1185. * descriptor
  1186. *
  1187. * Return:
  1188. */
  1189. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1190. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1191. {
  1192. qdf_nbuf_t curr_nbuf = NULL;
  1193. uint16_t total_len = 0;
  1194. qdf_dma_addr_t paddr;
  1195. int32_t i;
  1196. int32_t mapped_buf_num = 0;
  1197. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1198. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1199. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1200. /* Continue only if frames are of DATA type */
  1201. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1202. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1203. dp_tx_debug("Pkt. recd is of not data type");
  1204. goto error;
  1205. }
  1206. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1207. if (vdev->raw_mode_war &&
  1208. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1209. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1210. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1211. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1212. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1213. /*
  1214. * Number of nbuf's must not exceed the size of the frags
  1215. * array in seg_info.
  1216. */
  1217. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1218. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1219. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1220. goto error;
  1221. }
  1222. if (QDF_STATUS_SUCCESS !=
  1223. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1224. curr_nbuf,
  1225. QDF_DMA_TO_DEVICE,
  1226. curr_nbuf->len)) {
  1227. dp_tx_err("%s dma map error ", __func__);
  1228. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1229. goto error;
  1230. }
  1231. /* Update the count of mapped nbuf's */
  1232. mapped_buf_num++;
  1233. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1234. seg_info->frags[i].paddr_lo = paddr;
  1235. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1236. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1237. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1238. total_len += qdf_nbuf_len(curr_nbuf);
  1239. }
  1240. seg_info->frag_cnt = i;
  1241. seg_info->total_len = total_len;
  1242. seg_info->next = NULL;
  1243. sg_info->curr_seg = seg_info;
  1244. msdu_info->frm_type = dp_tx_frm_raw;
  1245. msdu_info->num_seg = 1;
  1246. return nbuf;
  1247. error:
  1248. i = 0;
  1249. while (nbuf) {
  1250. curr_nbuf = nbuf;
  1251. if (i < mapped_buf_num) {
  1252. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1253. QDF_DMA_TO_DEVICE,
  1254. curr_nbuf->len);
  1255. i++;
  1256. }
  1257. nbuf = qdf_nbuf_next(nbuf);
  1258. qdf_nbuf_free(curr_nbuf);
  1259. }
  1260. return NULL;
  1261. }
  1262. /**
  1263. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1264. * @soc: DP soc handle
  1265. * @nbuf: Buffer pointer
  1266. *
  1267. * unmap the chain of nbufs that belong to this RAW frame.
  1268. *
  1269. * Return: None
  1270. */
  1271. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1272. qdf_nbuf_t nbuf)
  1273. {
  1274. qdf_nbuf_t cur_nbuf = nbuf;
  1275. do {
  1276. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1277. QDF_DMA_TO_DEVICE,
  1278. cur_nbuf->len);
  1279. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1280. } while (cur_nbuf);
  1281. }
  1282. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1283. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1284. qdf_nbuf_t nbuf)
  1285. {
  1286. qdf_nbuf_t nbuf_local;
  1287. struct dp_vdev *vdev_local = vdev_hdl;
  1288. do {
  1289. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1290. break;
  1291. nbuf_local = nbuf;
  1292. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1293. htt_cmn_pkt_type_raw))
  1294. break;
  1295. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1296. break;
  1297. else if (qdf_nbuf_is_tso((nbuf_local)))
  1298. break;
  1299. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1300. (nbuf_local),
  1301. NULL, 1, 0);
  1302. } while (0);
  1303. }
  1304. #endif
  1305. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1306. /**
  1307. * dp_tx_update_stats() - Update soc level tx stats
  1308. * @soc: DP soc handle
  1309. * @tx_desc: TX descriptor reference
  1310. * @ring_id: TCL ring id
  1311. *
  1312. * Returns: none
  1313. */
  1314. void dp_tx_update_stats(struct dp_soc *soc,
  1315. struct dp_tx_desc_s *tx_desc,
  1316. uint8_t ring_id)
  1317. {
  1318. uint32_t stats_len = 0;
  1319. if (tx_desc->frm_type == dp_tx_frm_tso)
  1320. stats_len = tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1321. else
  1322. stats_len = qdf_nbuf_len(tx_desc->nbuf);
  1323. DP_STATS_INC_PKT(soc, tx.egress[ring_id], 1, stats_len);
  1324. }
  1325. int
  1326. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1327. struct dp_tx_desc_s *tx_desc,
  1328. uint8_t tid,
  1329. struct dp_tx_msdu_info_s *msdu_info,
  1330. uint8_t ring_id)
  1331. {
  1332. struct dp_swlm *swlm = &soc->swlm;
  1333. union swlm_data swlm_query_data;
  1334. struct dp_swlm_tcl_data tcl_data;
  1335. QDF_STATUS status;
  1336. int ret;
  1337. if (!swlm->is_enabled)
  1338. return msdu_info->skip_hp_update;
  1339. tcl_data.nbuf = tx_desc->nbuf;
  1340. tcl_data.tid = tid;
  1341. tcl_data.ring_id = ring_id;
  1342. if (tx_desc->frm_type == dp_tx_frm_tso) {
  1343. tcl_data.pkt_len =
  1344. tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1345. } else {
  1346. tcl_data.pkt_len = qdf_nbuf_len(tx_desc->nbuf);
  1347. }
  1348. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1349. swlm_query_data.tcl_data = &tcl_data;
  1350. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1351. if (QDF_IS_STATUS_ERROR(status)) {
  1352. dp_swlm_tcl_reset_session_data(soc, ring_id);
  1353. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1354. return 0;
  1355. }
  1356. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1357. if (ret) {
  1358. DP_STATS_INC(swlm, tcl[ring_id].coalesce_success, 1);
  1359. } else {
  1360. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1361. }
  1362. return ret;
  1363. }
  1364. void
  1365. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1366. int coalesce)
  1367. {
  1368. if (coalesce)
  1369. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1370. else
  1371. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1372. }
  1373. static inline void
  1374. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1375. {
  1376. if (((i + 1) < msdu_info->num_seg))
  1377. msdu_info->skip_hp_update = 1;
  1378. else
  1379. msdu_info->skip_hp_update = 0;
  1380. }
  1381. static inline void
  1382. dp_flush_tcp_hp(struct dp_soc *soc, uint8_t ring_id)
  1383. {
  1384. hal_ring_handle_t hal_ring_hdl =
  1385. dp_tx_get_hal_ring_hdl(soc, ring_id);
  1386. if (dp_tx_hal_ring_access_start(soc, hal_ring_hdl)) {
  1387. dp_err("Fillmore: SRNG access start failed");
  1388. return;
  1389. }
  1390. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1391. }
  1392. static inline void
  1393. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1394. QDF_STATUS status,
  1395. struct dp_tx_msdu_info_s *msdu_info)
  1396. {
  1397. if (QDF_IS_STATUS_ERROR(status) && !msdu_info->skip_hp_update) {
  1398. dp_flush_tcp_hp(soc,
  1399. (msdu_info->tx_queue.ring_id & DP_TX_QUEUE_MASK));
  1400. }
  1401. }
  1402. #else
  1403. static inline void
  1404. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1405. {
  1406. }
  1407. static inline void
  1408. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1409. QDF_STATUS status,
  1410. struct dp_tx_msdu_info_s *msdu_info)
  1411. {
  1412. }
  1413. #endif
  1414. #ifdef FEATURE_RUNTIME_PM
  1415. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1416. {
  1417. int ret;
  1418. ret = qdf_atomic_read(&soc->rtpm_high_tput_flag) &&
  1419. (hif_rtpm_get_state() <= HIF_RTPM_STATE_ON);
  1420. return ret;
  1421. }
  1422. /**
  1423. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1424. * @soc: Datapath soc handle
  1425. * @hal_ring_hdl: HAL ring handle
  1426. * @coalesce: Coalesce the current write or not
  1427. *
  1428. * Wrapper for HAL ring access end for data transmission for
  1429. * FEATURE_RUNTIME_PM
  1430. *
  1431. * Returns: none
  1432. */
  1433. void
  1434. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1435. hal_ring_handle_t hal_ring_hdl,
  1436. int coalesce)
  1437. {
  1438. int ret;
  1439. /*
  1440. * Avoid runtime get and put APIs under high throughput scenarios.
  1441. */
  1442. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1443. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1444. return;
  1445. }
  1446. ret = hif_rtpm_get(HIF_RTPM_GET_ASYNC, HIF_RTPM_ID_DP);
  1447. if (QDF_IS_STATUS_SUCCESS(ret)) {
  1448. if (hif_system_pm_state_check(soc->hif_handle) ||
  1449. qdf_unlikely(soc->is_tx_pause)) {
  1450. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1451. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1452. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1453. } else {
  1454. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1455. }
  1456. hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_DP);
  1457. } else {
  1458. dp_runtime_get(soc);
  1459. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1460. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1461. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1462. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1463. dp_runtime_put(soc);
  1464. }
  1465. }
  1466. #else
  1467. #ifdef DP_POWER_SAVE
  1468. void
  1469. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1470. hal_ring_handle_t hal_ring_hdl,
  1471. int coalesce)
  1472. {
  1473. if (hif_system_pm_state_check(soc->hif_handle) ||
  1474. qdf_unlikely(soc->is_tx_pause)) {
  1475. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1476. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1477. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1478. } else {
  1479. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1480. }
  1481. }
  1482. #endif
  1483. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1484. {
  1485. return 0;
  1486. }
  1487. #endif
  1488. /**
  1489. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1490. * @vdev: DP vdev handle
  1491. * @nbuf: skb
  1492. *
  1493. * Extract the DSCP or PCP information from frame and map into TID value.
  1494. *
  1495. * Return: void
  1496. */
  1497. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1498. struct dp_tx_msdu_info_s *msdu_info)
  1499. {
  1500. uint8_t tos = 0, dscp_tid_override = 0;
  1501. uint8_t *hdr_ptr, *L3datap;
  1502. uint8_t is_mcast = 0;
  1503. qdf_ether_header_t *eh = NULL;
  1504. qdf_ethervlan_header_t *evh = NULL;
  1505. uint16_t ether_type;
  1506. qdf_llc_t *llcHdr;
  1507. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1508. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1509. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1510. eh = (qdf_ether_header_t *)nbuf->data;
  1511. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1512. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1513. } else {
  1514. qdf_dot3_qosframe_t *qos_wh =
  1515. (qdf_dot3_qosframe_t *) nbuf->data;
  1516. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1517. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1518. return;
  1519. }
  1520. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1521. ether_type = eh->ether_type;
  1522. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1523. /*
  1524. * Check if packet is dot3 or eth2 type.
  1525. */
  1526. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1527. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1528. sizeof(*llcHdr));
  1529. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1530. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1531. sizeof(*llcHdr);
  1532. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1533. + sizeof(*llcHdr) +
  1534. sizeof(qdf_net_vlanhdr_t));
  1535. } else {
  1536. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1537. sizeof(*llcHdr);
  1538. }
  1539. } else {
  1540. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1541. evh = (qdf_ethervlan_header_t *) eh;
  1542. ether_type = evh->ether_type;
  1543. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1544. }
  1545. }
  1546. /*
  1547. * Find priority from IP TOS DSCP field
  1548. */
  1549. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1550. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1551. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1552. /* Only for unicast frames */
  1553. if (!is_mcast) {
  1554. /* send it on VO queue */
  1555. msdu_info->tid = DP_VO_TID;
  1556. }
  1557. } else {
  1558. /*
  1559. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1560. * from TOS byte.
  1561. */
  1562. tos = ip->ip_tos;
  1563. dscp_tid_override = 1;
  1564. }
  1565. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1566. /* TODO
  1567. * use flowlabel
  1568. *igmpmld cases to be handled in phase 2
  1569. */
  1570. unsigned long ver_pri_flowlabel;
  1571. unsigned long pri;
  1572. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1573. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1574. DP_IPV6_PRIORITY_SHIFT;
  1575. tos = pri;
  1576. dscp_tid_override = 1;
  1577. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1578. msdu_info->tid = DP_VO_TID;
  1579. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1580. /* Only for unicast frames */
  1581. if (!is_mcast) {
  1582. /* send ucast arp on VO queue */
  1583. msdu_info->tid = DP_VO_TID;
  1584. }
  1585. }
  1586. /*
  1587. * Assign all MCAST packets to BE
  1588. */
  1589. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1590. if (is_mcast) {
  1591. tos = 0;
  1592. dscp_tid_override = 1;
  1593. }
  1594. }
  1595. if (dscp_tid_override == 1) {
  1596. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1597. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1598. }
  1599. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1600. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1601. return;
  1602. }
  1603. /**
  1604. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1605. * @vdev: DP vdev handle
  1606. * @nbuf: skb
  1607. *
  1608. * Software based TID classification is required when more than 2 DSCP-TID
  1609. * mapping tables are needed.
  1610. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1611. *
  1612. * Return: void
  1613. */
  1614. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1615. struct dp_tx_msdu_info_s *msdu_info)
  1616. {
  1617. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1618. /*
  1619. * skip_sw_tid_classification flag will set in below cases-
  1620. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1621. * 2. hlos_tid_override enabled for vdev
  1622. * 3. mesh mode enabled for vdev
  1623. */
  1624. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1625. /* Update tid in msdu_info from skb priority */
  1626. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1627. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1628. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1629. if (tid == DP_TX_INVALID_QOS_TAG)
  1630. return;
  1631. msdu_info->tid = tid;
  1632. return;
  1633. }
  1634. return;
  1635. }
  1636. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1637. }
  1638. #ifdef FEATURE_WLAN_TDLS
  1639. /**
  1640. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1641. * @soc: datapath SOC
  1642. * @vdev: datapath vdev
  1643. * @tx_desc: TX descriptor
  1644. *
  1645. * Return: None
  1646. */
  1647. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1648. struct dp_vdev *vdev,
  1649. struct dp_tx_desc_s *tx_desc)
  1650. {
  1651. if (vdev) {
  1652. if (vdev->is_tdls_frame) {
  1653. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1654. vdev->is_tdls_frame = false;
  1655. }
  1656. }
  1657. }
  1658. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1659. {
  1660. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1661. switch (soc->arch_id) {
  1662. case CDP_ARCH_TYPE_LI:
  1663. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1664. break;
  1665. case CDP_ARCH_TYPE_BE:
  1666. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1667. break;
  1668. default:
  1669. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1670. QDF_BUG(0);
  1671. }
  1672. return tx_status;
  1673. }
  1674. /**
  1675. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1676. * @soc: dp_soc handle
  1677. * @tx_desc: TX descriptor
  1678. * @vdev: datapath vdev handle
  1679. *
  1680. * Return: None
  1681. */
  1682. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1683. struct dp_tx_desc_s *tx_desc)
  1684. {
  1685. uint8_t tx_status = 0;
  1686. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1687. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1688. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1689. DP_MOD_ID_TDLS);
  1690. if (qdf_unlikely(!vdev)) {
  1691. dp_err_rl("vdev is null!");
  1692. goto error;
  1693. }
  1694. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1695. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1696. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1697. if (vdev->tx_non_std_data_callback.func) {
  1698. qdf_nbuf_set_next(nbuf, NULL);
  1699. vdev->tx_non_std_data_callback.func(
  1700. vdev->tx_non_std_data_callback.ctxt,
  1701. nbuf, tx_status);
  1702. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1703. return;
  1704. } else {
  1705. dp_err_rl("callback func is null");
  1706. }
  1707. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1708. error:
  1709. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1710. qdf_nbuf_free(nbuf);
  1711. }
  1712. /**
  1713. * dp_tx_msdu_single_map() - do nbuf map
  1714. * @vdev: DP vdev handle
  1715. * @tx_desc: DP TX descriptor pointer
  1716. * @nbuf: skb pointer
  1717. *
  1718. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1719. * operation done in other component.
  1720. *
  1721. * Return: QDF_STATUS
  1722. */
  1723. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1724. struct dp_tx_desc_s *tx_desc,
  1725. qdf_nbuf_t nbuf)
  1726. {
  1727. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1728. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1729. nbuf,
  1730. QDF_DMA_TO_DEVICE,
  1731. nbuf->len);
  1732. else
  1733. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1734. QDF_DMA_TO_DEVICE);
  1735. }
  1736. #else
  1737. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1738. struct dp_vdev *vdev,
  1739. struct dp_tx_desc_s *tx_desc)
  1740. {
  1741. }
  1742. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1743. struct dp_tx_desc_s *tx_desc)
  1744. {
  1745. }
  1746. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1747. struct dp_tx_desc_s *tx_desc,
  1748. qdf_nbuf_t nbuf)
  1749. {
  1750. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1751. nbuf,
  1752. QDF_DMA_TO_DEVICE,
  1753. nbuf->len);
  1754. }
  1755. #endif
  1756. static inline
  1757. qdf_dma_addr_t dp_tx_nbuf_map_regular(struct dp_vdev *vdev,
  1758. struct dp_tx_desc_s *tx_desc,
  1759. qdf_nbuf_t nbuf)
  1760. {
  1761. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1762. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1763. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1764. return 0;
  1765. return qdf_nbuf_mapped_paddr_get(nbuf);
  1766. }
  1767. static inline
  1768. void dp_tx_nbuf_unmap_regular(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1769. {
  1770. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1771. desc->nbuf,
  1772. desc->dma_addr,
  1773. QDF_DMA_TO_DEVICE,
  1774. desc->length);
  1775. }
  1776. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1777. static inline
  1778. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1779. struct dp_tx_desc_s *tx_desc,
  1780. qdf_nbuf_t nbuf)
  1781. {
  1782. if (qdf_likely(tx_desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  1783. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1784. (void *)(nbuf->data + nbuf->len));
  1785. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1786. } else {
  1787. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1788. }
  1789. }
  1790. static inline
  1791. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1792. struct dp_tx_desc_s *desc)
  1793. {
  1794. if (qdf_unlikely(!(desc->flags & DP_TX_DESC_FLAG_SIMPLE)))
  1795. return dp_tx_nbuf_unmap_regular(soc, desc);
  1796. }
  1797. #else
  1798. static inline
  1799. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1800. struct dp_tx_desc_s *tx_desc,
  1801. qdf_nbuf_t nbuf)
  1802. {
  1803. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1804. }
  1805. static inline
  1806. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1807. struct dp_tx_desc_s *desc)
  1808. {
  1809. return dp_tx_nbuf_unmap_regular(soc, desc);
  1810. }
  1811. #endif
  1812. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  1813. static inline
  1814. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1815. {
  1816. dp_tx_nbuf_unmap(soc, desc);
  1817. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  1818. }
  1819. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1820. {
  1821. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  1822. dp_tx_nbuf_unmap(soc, desc);
  1823. }
  1824. #else
  1825. static inline
  1826. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1827. {
  1828. }
  1829. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1830. {
  1831. dp_tx_nbuf_unmap(soc, desc);
  1832. }
  1833. #endif
  1834. #ifdef MESH_MODE_SUPPORT
  1835. /**
  1836. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1837. * @soc: datapath SOC
  1838. * @vdev: datapath vdev
  1839. * @tx_desc: TX descriptor
  1840. *
  1841. * Return: None
  1842. */
  1843. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1844. struct dp_vdev *vdev,
  1845. struct dp_tx_desc_s *tx_desc)
  1846. {
  1847. if (qdf_unlikely(vdev->mesh_vdev))
  1848. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1849. }
  1850. /**
  1851. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1852. * @soc: dp_soc handle
  1853. * @tx_desc: TX descriptor
  1854. * @delayed_free: delay the nbuf free
  1855. *
  1856. * Return: nbuf to be freed late
  1857. */
  1858. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1859. struct dp_tx_desc_s *tx_desc,
  1860. bool delayed_free)
  1861. {
  1862. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1863. struct dp_vdev *vdev = NULL;
  1864. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id, DP_MOD_ID_MESH);
  1865. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1866. if (vdev)
  1867. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1868. if (delayed_free)
  1869. return nbuf;
  1870. qdf_nbuf_free(nbuf);
  1871. } else {
  1872. if (vdev && vdev->osif_tx_free_ext) {
  1873. vdev->osif_tx_free_ext((nbuf));
  1874. } else {
  1875. if (delayed_free)
  1876. return nbuf;
  1877. qdf_nbuf_free(nbuf);
  1878. }
  1879. }
  1880. if (vdev)
  1881. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1882. return NULL;
  1883. }
  1884. #else
  1885. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1886. struct dp_vdev *vdev,
  1887. struct dp_tx_desc_s *tx_desc)
  1888. {
  1889. }
  1890. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1891. struct dp_tx_desc_s *tx_desc,
  1892. bool delayed_free)
  1893. {
  1894. return NULL;
  1895. }
  1896. #endif
  1897. /**
  1898. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1899. * @vdev: DP vdev handle
  1900. * @nbuf: skb
  1901. *
  1902. * Return: 1 if frame needs to be dropped else 0
  1903. */
  1904. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1905. {
  1906. struct dp_pdev *pdev = NULL;
  1907. struct dp_ast_entry *src_ast_entry = NULL;
  1908. struct dp_ast_entry *dst_ast_entry = NULL;
  1909. struct dp_soc *soc = NULL;
  1910. qdf_assert(vdev);
  1911. pdev = vdev->pdev;
  1912. qdf_assert(pdev);
  1913. soc = pdev->soc;
  1914. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1915. (soc, dstmac, vdev->pdev->pdev_id);
  1916. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1917. (soc, srcmac, vdev->pdev->pdev_id);
  1918. if (dst_ast_entry && src_ast_entry) {
  1919. if (dst_ast_entry->peer_id ==
  1920. src_ast_entry->peer_id)
  1921. return 1;
  1922. }
  1923. return 0;
  1924. }
  1925. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1926. defined(WLAN_MCAST_MLO)
  1927. /* MLO peer id for reinject*/
  1928. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  1929. /* MLO vdev id inc offset */
  1930. #define DP_MLO_VDEV_ID_OFFSET 0x80
  1931. static inline void
  1932. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  1933. {
  1934. if (!(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)) {
  1935. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1936. qdf_atomic_inc(&soc->num_tx_exception);
  1937. }
  1938. }
  1939. static inline void
  1940. dp_tx_update_mcast_param(uint16_t peer_id,
  1941. uint16_t *htt_tcl_metadata,
  1942. struct dp_vdev *vdev,
  1943. struct dp_tx_msdu_info_s *msdu_info)
  1944. {
  1945. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  1946. *htt_tcl_metadata = 0;
  1947. DP_TX_TCL_METADATA_TYPE_SET(
  1948. *htt_tcl_metadata,
  1949. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  1950. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  1951. msdu_info->gsn);
  1952. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  1953. if (qdf_unlikely(vdev->nawds_enabled))
  1954. HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(
  1955. *htt_tcl_metadata, 1);
  1956. } else {
  1957. msdu_info->vdev_id = vdev->vdev_id;
  1958. }
  1959. }
  1960. #else
  1961. static inline void
  1962. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  1963. {
  1964. }
  1965. static inline void
  1966. dp_tx_update_mcast_param(uint16_t peer_id,
  1967. uint16_t *htt_tcl_metadata,
  1968. struct dp_vdev *vdev,
  1969. struct dp_tx_msdu_info_s *msdu_info)
  1970. {
  1971. }
  1972. #endif
  1973. /**
  1974. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1975. * @vdev: DP vdev handle
  1976. * @nbuf: skb
  1977. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1978. * @meta_data: Metadata to the fw
  1979. * @tx_q: Tx queue to be used for this Tx frame
  1980. * @peer_id: peer_id of the peer in case of NAWDS frames
  1981. * @tx_exc_metadata: Handle that holds exception path metadata
  1982. *
  1983. * Return: NULL on success,
  1984. * nbuf when it fails to send
  1985. */
  1986. qdf_nbuf_t
  1987. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1988. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1989. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1990. {
  1991. struct dp_pdev *pdev = vdev->pdev;
  1992. struct dp_soc *soc = pdev->soc;
  1993. struct dp_tx_desc_s *tx_desc;
  1994. QDF_STATUS status;
  1995. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1996. uint16_t htt_tcl_metadata = 0;
  1997. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1998. uint8_t tid = msdu_info->tid;
  1999. struct cdp_tid_tx_stats *tid_stats = NULL;
  2000. qdf_dma_addr_t paddr;
  2001. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  2002. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  2003. msdu_info, tx_exc_metadata);
  2004. if (!tx_desc) {
  2005. dp_err_rl("Tx_desc prepare Fail vdev_id %d vdev %pK queue %d",
  2006. vdev->vdev_id, vdev, tx_q->desc_pool_id);
  2007. drop_code = TX_DESC_ERR;
  2008. goto fail_return;
  2009. }
  2010. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  2011. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  2012. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2013. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  2014. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  2015. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  2016. DP_TCL_METADATA_TYPE_PEER_BASED);
  2017. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  2018. peer_id);
  2019. dp_tx_bypass_reinjection(soc, tx_desc);
  2020. } else
  2021. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2022. if (msdu_info->exception_fw)
  2023. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2024. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  2025. !pdev->enhanced_stats_en);
  2026. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  2027. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  2028. if (!paddr) {
  2029. /* Handle failure */
  2030. dp_err("qdf_nbuf_map failed");
  2031. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  2032. drop_code = TX_DMA_MAP_ERR;
  2033. goto release_desc;
  2034. }
  2035. tx_desc->dma_addr = paddr;
  2036. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2037. tx_desc->id, DP_TX_DESC_MAP);
  2038. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  2039. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  2040. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2041. htt_tcl_metadata,
  2042. tx_exc_metadata, msdu_info);
  2043. if (status != QDF_STATUS_SUCCESS) {
  2044. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2045. tx_desc, tx_q->ring_id);
  2046. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2047. tx_desc->id, DP_TX_DESC_UNMAP);
  2048. dp_tx_nbuf_unmap(soc, tx_desc);
  2049. drop_code = TX_HW_ENQUEUE;
  2050. goto release_desc;
  2051. }
  2052. return NULL;
  2053. release_desc:
  2054. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2055. fail_return:
  2056. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2057. tid_stats = &pdev->stats.tid_stats.
  2058. tid_tx_stats[tx_q->ring_id][tid];
  2059. tid_stats->swdrop_cnt[drop_code]++;
  2060. return nbuf;
  2061. }
  2062. /**
  2063. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2064. * @soc: Soc handle
  2065. * @desc: software Tx descriptor to be processed
  2066. * @delayed_free: defer freeing of nbuf
  2067. *
  2068. * Return: nbuf to be freed later
  2069. */
  2070. qdf_nbuf_t dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc,
  2071. bool delayed_free)
  2072. {
  2073. qdf_nbuf_t nbuf = desc->nbuf;
  2074. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  2075. /* nbuf already freed in vdev detach path */
  2076. if (!nbuf)
  2077. return NULL;
  2078. /* If it is TDLS mgmt, don't unmap or free the frame */
  2079. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME) {
  2080. dp_non_std_htt_tx_comp_free_buff(soc, desc);
  2081. return NULL;
  2082. }
  2083. /* 0 : MSDU buffer, 1 : MLE */
  2084. if (desc->msdu_ext_desc) {
  2085. /* TSO free */
  2086. if (hal_tx_ext_desc_get_tso_enable(
  2087. desc->msdu_ext_desc->vaddr)) {
  2088. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  2089. desc->id, DP_TX_COMP_MSDU_EXT);
  2090. dp_tx_tso_seg_history_add(soc,
  2091. desc->msdu_ext_desc->tso_desc,
  2092. desc->nbuf, desc->id, type);
  2093. /* unmap eash TSO seg before free the nbuf */
  2094. dp_tx_tso_unmap_segment(soc,
  2095. desc->msdu_ext_desc->tso_desc,
  2096. desc->msdu_ext_desc->
  2097. tso_num_desc);
  2098. goto nbuf_free;
  2099. }
  2100. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  2101. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  2102. qdf_dma_addr_t iova;
  2103. uint32_t frag_len;
  2104. uint32_t i;
  2105. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2106. QDF_DMA_TO_DEVICE,
  2107. qdf_nbuf_headlen(nbuf));
  2108. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  2109. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  2110. &iova,
  2111. &frag_len);
  2112. if (!iova || !frag_len)
  2113. break;
  2114. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  2115. QDF_DMA_TO_DEVICE);
  2116. }
  2117. goto nbuf_free;
  2118. }
  2119. }
  2120. /* If it's ME frame, dont unmap the cloned nbuf's */
  2121. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  2122. goto nbuf_free;
  2123. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  2124. dp_tx_unmap(soc, desc);
  2125. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2126. return dp_mesh_tx_comp_free_buff(soc, desc, delayed_free);
  2127. if (dp_tx_traffic_end_indication_enq_ind_pkt(soc, desc, nbuf))
  2128. return NULL;
  2129. nbuf_free:
  2130. if (delayed_free)
  2131. return nbuf;
  2132. qdf_nbuf_free(nbuf);
  2133. return NULL;
  2134. }
  2135. /**
  2136. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  2137. * @soc: DP soc handle
  2138. * @nbuf: skb
  2139. * @msdu_info: MSDU info
  2140. *
  2141. * Return: None
  2142. */
  2143. static inline void
  2144. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2145. struct dp_tx_msdu_info_s *msdu_info)
  2146. {
  2147. uint32_t cur_idx;
  2148. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  2149. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  2150. qdf_nbuf_headlen(nbuf));
  2151. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  2152. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  2153. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  2154. seg->frags[cur_idx].paddr_hi) << 32),
  2155. seg->frags[cur_idx].len,
  2156. QDF_DMA_TO_DEVICE);
  2157. }
  2158. /**
  2159. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  2160. * @vdev: DP vdev handle
  2161. * @nbuf: skb
  2162. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  2163. *
  2164. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  2165. *
  2166. * Return: NULL on success,
  2167. * nbuf when it fails to send
  2168. */
  2169. #if QDF_LOCK_STATS
  2170. noinline
  2171. #else
  2172. #endif
  2173. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2174. struct dp_tx_msdu_info_s *msdu_info)
  2175. {
  2176. uint32_t i;
  2177. struct dp_pdev *pdev = vdev->pdev;
  2178. struct dp_soc *soc = pdev->soc;
  2179. struct dp_tx_desc_s *tx_desc;
  2180. bool is_cce_classified = false;
  2181. QDF_STATUS status;
  2182. uint16_t htt_tcl_metadata = 0;
  2183. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2184. struct cdp_tid_tx_stats *tid_stats = NULL;
  2185. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2186. if (msdu_info->frm_type == dp_tx_frm_me)
  2187. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2188. i = 0;
  2189. /* Print statement to track i and num_seg */
  2190. /*
  2191. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2192. * descriptors using information in msdu_info
  2193. */
  2194. while (i < msdu_info->num_seg) {
  2195. /*
  2196. * Setup Tx descriptor for an MSDU, and MSDU extension
  2197. * descriptor
  2198. */
  2199. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2200. tx_q->desc_pool_id);
  2201. if (!tx_desc) {
  2202. if (msdu_info->frm_type == dp_tx_frm_me) {
  2203. prep_desc_fail++;
  2204. dp_tx_me_free_buf(pdev,
  2205. (void *)(msdu_info->u.sg_info
  2206. .curr_seg->frags[0].vaddr));
  2207. if (prep_desc_fail == msdu_info->num_seg) {
  2208. /*
  2209. * Unmap is needed only if descriptor
  2210. * preparation failed for all segments.
  2211. */
  2212. qdf_nbuf_unmap(soc->osdev,
  2213. msdu_info->u.sg_info.
  2214. curr_seg->nbuf,
  2215. QDF_DMA_TO_DEVICE);
  2216. }
  2217. /*
  2218. * Free the nbuf for the current segment
  2219. * and make it point to the next in the list.
  2220. * For me, there are as many segments as there
  2221. * are no of clients.
  2222. */
  2223. qdf_nbuf_free(msdu_info->u.sg_info
  2224. .curr_seg->nbuf);
  2225. if (msdu_info->u.sg_info.curr_seg->next) {
  2226. msdu_info->u.sg_info.curr_seg =
  2227. msdu_info->u.sg_info
  2228. .curr_seg->next;
  2229. nbuf = msdu_info->u.sg_info
  2230. .curr_seg->nbuf;
  2231. }
  2232. i++;
  2233. continue;
  2234. }
  2235. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2236. dp_tx_tso_seg_history_add(
  2237. soc,
  2238. msdu_info->u.tso_info.curr_seg,
  2239. nbuf, 0, DP_TX_DESC_UNMAP);
  2240. dp_tx_tso_unmap_segment(soc,
  2241. msdu_info->u.tso_info.
  2242. curr_seg,
  2243. msdu_info->u.tso_info.
  2244. tso_num_seg_list);
  2245. if (msdu_info->u.tso_info.curr_seg->next) {
  2246. msdu_info->u.tso_info.curr_seg =
  2247. msdu_info->u.tso_info.curr_seg->next;
  2248. i++;
  2249. continue;
  2250. }
  2251. }
  2252. if (msdu_info->frm_type == dp_tx_frm_sg)
  2253. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2254. goto done;
  2255. }
  2256. if (msdu_info->frm_type == dp_tx_frm_me) {
  2257. tx_desc->msdu_ext_desc->me_buffer =
  2258. (struct dp_tx_me_buf_t *)msdu_info->
  2259. u.sg_info.curr_seg->frags[0].vaddr;
  2260. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2261. }
  2262. if (is_cce_classified)
  2263. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2264. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2265. if (msdu_info->exception_fw) {
  2266. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2267. }
  2268. dp_tx_is_hp_update_required(i, msdu_info);
  2269. /*
  2270. * For frames with multiple segments (TSO, ME), jump to next
  2271. * segment.
  2272. */
  2273. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2274. if (msdu_info->u.tso_info.curr_seg->next) {
  2275. msdu_info->u.tso_info.curr_seg =
  2276. msdu_info->u.tso_info.curr_seg->next;
  2277. /*
  2278. * If this is a jumbo nbuf, then increment the
  2279. * number of nbuf users for each additional
  2280. * segment of the msdu. This will ensure that
  2281. * the skb is freed only after receiving tx
  2282. * completion for all segments of an nbuf
  2283. */
  2284. qdf_nbuf_inc_users(nbuf);
  2285. /* Check with MCL if this is needed */
  2286. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2287. */
  2288. }
  2289. }
  2290. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2291. &htt_tcl_metadata,
  2292. vdev,
  2293. msdu_info);
  2294. /*
  2295. * Enqueue the Tx MSDU descriptor to HW for transmit
  2296. */
  2297. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2298. htt_tcl_metadata,
  2299. NULL, msdu_info);
  2300. dp_tx_check_and_flush_hp(soc, status, msdu_info);
  2301. if (status != QDF_STATUS_SUCCESS) {
  2302. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2303. tx_desc, tx_q->ring_id);
  2304. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2305. tid_stats = &pdev->stats.tid_stats.
  2306. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2307. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2308. if (msdu_info->frm_type == dp_tx_frm_me) {
  2309. hw_enq_fail++;
  2310. if (hw_enq_fail == msdu_info->num_seg) {
  2311. /*
  2312. * Unmap is needed only if enqueue
  2313. * failed for all segments.
  2314. */
  2315. qdf_nbuf_unmap(soc->osdev,
  2316. msdu_info->u.sg_info.
  2317. curr_seg->nbuf,
  2318. QDF_DMA_TO_DEVICE);
  2319. }
  2320. /*
  2321. * Free the nbuf for the current segment
  2322. * and make it point to the next in the list.
  2323. * For me, there are as many segments as there
  2324. * are no of clients.
  2325. */
  2326. qdf_nbuf_free(msdu_info->u.sg_info
  2327. .curr_seg->nbuf);
  2328. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2329. if (msdu_info->u.sg_info.curr_seg->next) {
  2330. msdu_info->u.sg_info.curr_seg =
  2331. msdu_info->u.sg_info
  2332. .curr_seg->next;
  2333. nbuf = msdu_info->u.sg_info
  2334. .curr_seg->nbuf;
  2335. } else
  2336. break;
  2337. i++;
  2338. continue;
  2339. }
  2340. /*
  2341. * For TSO frames, the nbuf users increment done for
  2342. * the current segment has to be reverted, since the
  2343. * hw enqueue for this segment failed
  2344. */
  2345. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2346. msdu_info->u.tso_info.curr_seg) {
  2347. /*
  2348. * unmap and free current,
  2349. * retransmit remaining segments
  2350. */
  2351. dp_tx_comp_free_buf(soc, tx_desc, false);
  2352. i++;
  2353. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2354. continue;
  2355. }
  2356. if (msdu_info->frm_type == dp_tx_frm_sg)
  2357. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2358. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2359. goto done;
  2360. }
  2361. /*
  2362. * TODO
  2363. * if tso_info structure can be modified to have curr_seg
  2364. * as first element, following 2 blocks of code (for TSO and SG)
  2365. * can be combined into 1
  2366. */
  2367. /*
  2368. * For Multicast-Unicast converted packets,
  2369. * each converted frame (for a client) is represented as
  2370. * 1 segment
  2371. */
  2372. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2373. (msdu_info->frm_type == dp_tx_frm_me)) {
  2374. if (msdu_info->u.sg_info.curr_seg->next) {
  2375. msdu_info->u.sg_info.curr_seg =
  2376. msdu_info->u.sg_info.curr_seg->next;
  2377. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2378. } else
  2379. break;
  2380. }
  2381. i++;
  2382. }
  2383. nbuf = NULL;
  2384. done:
  2385. return nbuf;
  2386. }
  2387. /**
  2388. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2389. * for SG frames
  2390. * @vdev: DP vdev handle
  2391. * @nbuf: skb
  2392. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2393. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2394. *
  2395. * Return: NULL on success,
  2396. * nbuf when it fails to send
  2397. */
  2398. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2399. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2400. {
  2401. uint32_t cur_frag, nr_frags, i;
  2402. qdf_dma_addr_t paddr;
  2403. struct dp_tx_sg_info_s *sg_info;
  2404. sg_info = &msdu_info->u.sg_info;
  2405. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2406. if (QDF_STATUS_SUCCESS !=
  2407. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2408. QDF_DMA_TO_DEVICE,
  2409. qdf_nbuf_headlen(nbuf))) {
  2410. dp_tx_err("dma map error");
  2411. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2412. qdf_nbuf_free(nbuf);
  2413. return NULL;
  2414. }
  2415. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2416. seg_info->frags[0].paddr_lo = paddr;
  2417. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2418. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2419. seg_info->frags[0].vaddr = (void *) nbuf;
  2420. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2421. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2422. nbuf, 0,
  2423. QDF_DMA_TO_DEVICE,
  2424. cur_frag)) {
  2425. dp_tx_err("frag dma map error");
  2426. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2427. goto map_err;
  2428. }
  2429. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2430. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2431. seg_info->frags[cur_frag + 1].paddr_hi =
  2432. ((uint64_t) paddr) >> 32;
  2433. seg_info->frags[cur_frag + 1].len =
  2434. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2435. }
  2436. seg_info->frag_cnt = (cur_frag + 1);
  2437. seg_info->total_len = qdf_nbuf_len(nbuf);
  2438. seg_info->next = NULL;
  2439. sg_info->curr_seg = seg_info;
  2440. msdu_info->frm_type = dp_tx_frm_sg;
  2441. msdu_info->num_seg = 1;
  2442. return nbuf;
  2443. map_err:
  2444. /* restore paddr into nbuf before calling unmap */
  2445. qdf_nbuf_mapped_paddr_set(nbuf,
  2446. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2447. ((uint64_t)
  2448. seg_info->frags[0].paddr_hi) << 32));
  2449. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2450. QDF_DMA_TO_DEVICE,
  2451. seg_info->frags[0].len);
  2452. for (i = 1; i <= cur_frag; i++) {
  2453. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2454. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2455. seg_info->frags[i].paddr_hi) << 32),
  2456. seg_info->frags[i].len,
  2457. QDF_DMA_TO_DEVICE);
  2458. }
  2459. qdf_nbuf_free(nbuf);
  2460. return NULL;
  2461. }
  2462. /**
  2463. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2464. * @vdev: DP vdev handle
  2465. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2466. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2467. *
  2468. * Return: NULL on failure,
  2469. * nbuf when extracted successfully
  2470. */
  2471. static
  2472. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2473. struct dp_tx_msdu_info_s *msdu_info,
  2474. uint16_t ppdu_cookie)
  2475. {
  2476. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2477. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2478. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2479. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2480. (msdu_info->meta_data[5], 1);
  2481. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2482. (msdu_info->meta_data[5], 1);
  2483. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2484. (msdu_info->meta_data[6], ppdu_cookie);
  2485. msdu_info->exception_fw = 1;
  2486. msdu_info->is_tx_sniffer = 1;
  2487. }
  2488. #ifdef MESH_MODE_SUPPORT
  2489. /**
  2490. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2491. and prepare msdu_info for mesh frames.
  2492. * @vdev: DP vdev handle
  2493. * @nbuf: skb
  2494. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2495. *
  2496. * Return: NULL on failure,
  2497. * nbuf when extracted successfully
  2498. */
  2499. static
  2500. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2501. struct dp_tx_msdu_info_s *msdu_info)
  2502. {
  2503. struct meta_hdr_s *mhdr;
  2504. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2505. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2506. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2507. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2508. msdu_info->exception_fw = 0;
  2509. goto remove_meta_hdr;
  2510. }
  2511. msdu_info->exception_fw = 1;
  2512. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2513. meta_data->host_tx_desc_pool = 1;
  2514. meta_data->update_peer_cache = 1;
  2515. meta_data->learning_frame = 1;
  2516. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2517. meta_data->power = mhdr->power;
  2518. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2519. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2520. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2521. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2522. meta_data->dyn_bw = 1;
  2523. meta_data->valid_pwr = 1;
  2524. meta_data->valid_mcs_mask = 1;
  2525. meta_data->valid_nss_mask = 1;
  2526. meta_data->valid_preamble_type = 1;
  2527. meta_data->valid_retries = 1;
  2528. meta_data->valid_bw_info = 1;
  2529. }
  2530. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2531. meta_data->encrypt_type = 0;
  2532. meta_data->valid_encrypt_type = 1;
  2533. meta_data->learning_frame = 0;
  2534. }
  2535. meta_data->valid_key_flags = 1;
  2536. meta_data->key_flags = (mhdr->keyix & 0x3);
  2537. remove_meta_hdr:
  2538. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2539. dp_tx_err("qdf_nbuf_pull_head failed");
  2540. qdf_nbuf_free(nbuf);
  2541. return NULL;
  2542. }
  2543. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2544. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2545. " tid %d to_fw %d",
  2546. msdu_info->meta_data[0],
  2547. msdu_info->meta_data[1],
  2548. msdu_info->meta_data[2],
  2549. msdu_info->meta_data[3],
  2550. msdu_info->meta_data[4],
  2551. msdu_info->meta_data[5],
  2552. msdu_info->tid, msdu_info->exception_fw);
  2553. return nbuf;
  2554. }
  2555. #else
  2556. static
  2557. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2558. struct dp_tx_msdu_info_s *msdu_info)
  2559. {
  2560. return nbuf;
  2561. }
  2562. #endif
  2563. /**
  2564. * dp_check_exc_metadata() - Checks if parameters are valid
  2565. * @tx_exc - holds all exception path parameters
  2566. *
  2567. * Returns true when all the parameters are valid else false
  2568. *
  2569. */
  2570. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2571. {
  2572. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2573. HTT_INVALID_TID);
  2574. bool invalid_encap_type =
  2575. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2576. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2577. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2578. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2579. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2580. tx_exc->ppdu_cookie == 0);
  2581. if (tx_exc->is_intrabss_fwd)
  2582. return true;
  2583. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2584. invalid_cookie) {
  2585. return false;
  2586. }
  2587. return true;
  2588. }
  2589. #ifdef ATH_SUPPORT_IQUE
  2590. /**
  2591. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2592. * @vdev: vdev handle
  2593. * @nbuf: skb
  2594. *
  2595. * Return: true on success,
  2596. * false on failure
  2597. */
  2598. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2599. {
  2600. qdf_ether_header_t *eh;
  2601. /* Mcast to Ucast Conversion*/
  2602. if (qdf_likely(!vdev->mcast_enhancement_en))
  2603. return true;
  2604. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2605. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2606. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2607. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2608. qdf_nbuf_set_next(nbuf, NULL);
  2609. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2610. qdf_nbuf_len(nbuf));
  2611. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2612. QDF_STATUS_SUCCESS) {
  2613. return false;
  2614. }
  2615. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2616. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2617. QDF_STATUS_SUCCESS) {
  2618. return false;
  2619. }
  2620. }
  2621. }
  2622. return true;
  2623. }
  2624. #else
  2625. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2626. {
  2627. return true;
  2628. }
  2629. #endif
  2630. /**
  2631. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2632. * @nbuf: qdf_nbuf_t
  2633. * @vdev: struct dp_vdev *
  2634. *
  2635. * Allow packet for processing only if it is for peer client which is
  2636. * connected with same vap. Drop packet if client is connected to
  2637. * different vap.
  2638. *
  2639. * Return: QDF_STATUS
  2640. */
  2641. static inline QDF_STATUS
  2642. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2643. {
  2644. struct dp_ast_entry *dst_ast_entry = NULL;
  2645. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2646. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2647. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2648. return QDF_STATUS_SUCCESS;
  2649. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2650. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2651. eh->ether_dhost,
  2652. vdev->vdev_id);
  2653. /* If there is no ast entry, return failure */
  2654. if (qdf_unlikely(!dst_ast_entry)) {
  2655. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2656. return QDF_STATUS_E_FAILURE;
  2657. }
  2658. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2659. return QDF_STATUS_SUCCESS;
  2660. }
  2661. /**
  2662. * dp_tx_nawds_handler() - NAWDS handler
  2663. *
  2664. * @soc: DP soc handle
  2665. * @vdev_id: id of DP vdev handle
  2666. * @msdu_info: msdu_info required to create HTT metadata
  2667. * @nbuf: skb
  2668. *
  2669. * This API transfers the multicast frames with the peer id
  2670. * on NAWDS enabled peer.
  2671. * Return: none
  2672. */
  2673. static inline
  2674. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2675. struct dp_tx_msdu_info_s *msdu_info,
  2676. qdf_nbuf_t nbuf, uint16_t sa_peer_id)
  2677. {
  2678. struct dp_peer *peer = NULL;
  2679. qdf_nbuf_t nbuf_clone = NULL;
  2680. uint16_t peer_id = DP_INVALID_PEER;
  2681. struct dp_txrx_peer *txrx_peer;
  2682. /* This check avoids pkt forwarding which is entered
  2683. * in the ast table but still doesn't have valid peerid.
  2684. */
  2685. if (sa_peer_id == HTT_INVALID_PEER)
  2686. return;
  2687. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2688. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2689. txrx_peer = dp_get_txrx_peer(peer);
  2690. if (!txrx_peer)
  2691. continue;
  2692. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2693. peer_id = peer->peer_id;
  2694. if (!dp_peer_is_primary_link_peer(peer))
  2695. continue;
  2696. /* Multicast packets needs to be
  2697. * dropped in case of intra bss forwarding
  2698. */
  2699. if (sa_peer_id == txrx_peer->peer_id) {
  2700. dp_tx_debug("multicast packet");
  2701. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2702. tx.nawds_mcast_drop,
  2703. 1);
  2704. continue;
  2705. }
  2706. nbuf_clone = qdf_nbuf_clone(nbuf);
  2707. if (!nbuf_clone) {
  2708. QDF_TRACE(QDF_MODULE_ID_DP,
  2709. QDF_TRACE_LEVEL_ERROR,
  2710. FL("nbuf clone failed"));
  2711. break;
  2712. }
  2713. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2714. msdu_info, peer_id,
  2715. NULL);
  2716. if (nbuf_clone) {
  2717. dp_tx_debug("pkt send failed");
  2718. qdf_nbuf_free(nbuf_clone);
  2719. } else {
  2720. if (peer_id != DP_INVALID_PEER)
  2721. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2722. tx.nawds_mcast,
  2723. 1, qdf_nbuf_len(nbuf));
  2724. }
  2725. }
  2726. }
  2727. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2728. }
  2729. /**
  2730. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2731. * @soc: DP soc handle
  2732. * @vdev_id: id of DP vdev handle
  2733. * @nbuf: skb
  2734. * @tx_exc_metadata: Handle that holds exception path meta data
  2735. *
  2736. * Entry point for Core Tx layer (DP_TX) invoked from
  2737. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2738. *
  2739. * Return: NULL on success,
  2740. * nbuf when it fails to send
  2741. */
  2742. qdf_nbuf_t
  2743. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2744. qdf_nbuf_t nbuf,
  2745. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2746. {
  2747. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2748. qdf_ether_header_t *eh = NULL;
  2749. struct dp_tx_msdu_info_s msdu_info;
  2750. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2751. DP_MOD_ID_TX_EXCEPTION);
  2752. if (qdf_unlikely(!vdev))
  2753. goto fail;
  2754. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2755. if (!tx_exc_metadata)
  2756. goto fail;
  2757. msdu_info.tid = tx_exc_metadata->tid;
  2758. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2759. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2760. QDF_MAC_ADDR_REF(nbuf->data));
  2761. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2762. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2763. dp_tx_err("Invalid parameters in exception path");
  2764. goto fail;
  2765. }
  2766. /* for peer based metadata check if peer is valid */
  2767. if (tx_exc_metadata->peer_id != CDP_INVALID_PEER) {
  2768. struct dp_peer *peer = NULL;
  2769. peer = dp_peer_get_ref_by_id(vdev->pdev->soc,
  2770. tx_exc_metadata->peer_id,
  2771. DP_MOD_ID_TX_EXCEPTION);
  2772. if (qdf_unlikely(!peer)) {
  2773. DP_STATS_INC(vdev,
  2774. tx_i.dropped.invalid_peer_id_in_exc_path,
  2775. 1);
  2776. goto fail;
  2777. }
  2778. dp_peer_unref_delete(peer, DP_MOD_ID_TX_EXCEPTION);
  2779. }
  2780. /* Basic sanity checks for unsupported packets */
  2781. /* MESH mode */
  2782. if (qdf_unlikely(vdev->mesh_vdev)) {
  2783. dp_tx_err("Mesh mode is not supported in exception path");
  2784. goto fail;
  2785. }
  2786. /*
  2787. * Classify the frame and call corresponding
  2788. * "prepare" function which extracts the segment (TSO)
  2789. * and fragmentation information (for TSO , SG, ME, or Raw)
  2790. * into MSDU_INFO structure which is later used to fill
  2791. * SW and HW descriptors.
  2792. */
  2793. if (qdf_nbuf_is_tso(nbuf)) {
  2794. dp_verbose_debug("TSO frame %pK", vdev);
  2795. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2796. qdf_nbuf_len(nbuf));
  2797. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2798. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2799. qdf_nbuf_len(nbuf));
  2800. goto fail;
  2801. }
  2802. goto send_multiple;
  2803. }
  2804. /* SG */
  2805. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2806. struct dp_tx_seg_info_s seg_info = {0};
  2807. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2808. if (!nbuf)
  2809. goto fail;
  2810. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2811. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2812. qdf_nbuf_len(nbuf));
  2813. goto send_multiple;
  2814. }
  2815. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2816. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2817. qdf_nbuf_len(nbuf));
  2818. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2819. tx_exc_metadata->ppdu_cookie);
  2820. }
  2821. /*
  2822. * Get HW Queue to use for this frame.
  2823. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2824. * dedicated for data and 1 for command.
  2825. * "queue_id" maps to one hardware ring.
  2826. * With each ring, we also associate a unique Tx descriptor pool
  2827. * to minimize lock contention for these resources.
  2828. */
  2829. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2830. if (qdf_likely(tx_exc_metadata->is_intrabss_fwd)) {
  2831. if (qdf_unlikely(vdev->nawds_enabled)) {
  2832. /*
  2833. * This is a multicast packet
  2834. */
  2835. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  2836. tx_exc_metadata->peer_id);
  2837. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2838. 1, qdf_nbuf_len(nbuf));
  2839. }
  2840. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2841. DP_INVALID_PEER, NULL);
  2842. } else {
  2843. /*
  2844. * Check exception descriptors
  2845. */
  2846. if (dp_tx_exception_limit_check(vdev))
  2847. goto fail;
  2848. /* Single linear frame */
  2849. /*
  2850. * If nbuf is a simple linear frame, use send_single function to
  2851. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2852. * SRNG. There is no need to setup a MSDU extension descriptor.
  2853. */
  2854. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2855. tx_exc_metadata->peer_id,
  2856. tx_exc_metadata);
  2857. }
  2858. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2859. return nbuf;
  2860. send_multiple:
  2861. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2862. fail:
  2863. if (vdev)
  2864. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2865. dp_verbose_debug("pkt send failed");
  2866. return nbuf;
  2867. }
  2868. /**
  2869. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2870. * in exception path in special case to avoid regular exception path chk.
  2871. * @soc: DP soc handle
  2872. * @vdev_id: id of DP vdev handle
  2873. * @nbuf: skb
  2874. * @tx_exc_metadata: Handle that holds exception path meta data
  2875. *
  2876. * Entry point for Core Tx layer (DP_TX) invoked from
  2877. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2878. *
  2879. * Return: NULL on success,
  2880. * nbuf when it fails to send
  2881. */
  2882. qdf_nbuf_t
  2883. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2884. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2885. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2886. {
  2887. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2888. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2889. DP_MOD_ID_TX_EXCEPTION);
  2890. if (qdf_unlikely(!vdev))
  2891. goto fail;
  2892. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2893. == QDF_STATUS_E_FAILURE)) {
  2894. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2895. goto fail;
  2896. }
  2897. /* Unref count as it will again be taken inside dp_tx_exception */
  2898. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2899. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2900. fail:
  2901. if (vdev)
  2902. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2903. dp_verbose_debug("pkt send failed");
  2904. return nbuf;
  2905. }
  2906. /**
  2907. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2908. * @soc: DP soc handle
  2909. * @vdev_id: DP vdev handle
  2910. * @nbuf: skb
  2911. *
  2912. * Entry point for Core Tx layer (DP_TX) invoked from
  2913. * hard_start_xmit in OSIF/HDD
  2914. *
  2915. * Return: NULL on success,
  2916. * nbuf when it fails to send
  2917. */
  2918. #ifdef MESH_MODE_SUPPORT
  2919. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2920. qdf_nbuf_t nbuf)
  2921. {
  2922. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2923. struct meta_hdr_s *mhdr;
  2924. qdf_nbuf_t nbuf_mesh = NULL;
  2925. qdf_nbuf_t nbuf_clone = NULL;
  2926. struct dp_vdev *vdev;
  2927. uint8_t no_enc_frame = 0;
  2928. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2929. if (!nbuf_mesh) {
  2930. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2931. "qdf_nbuf_unshare failed");
  2932. return nbuf;
  2933. }
  2934. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2935. if (!vdev) {
  2936. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2937. "vdev is NULL for vdev_id %d", vdev_id);
  2938. return nbuf;
  2939. }
  2940. nbuf = nbuf_mesh;
  2941. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2942. if ((vdev->sec_type != cdp_sec_type_none) &&
  2943. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2944. no_enc_frame = 1;
  2945. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2946. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2947. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2948. !no_enc_frame) {
  2949. nbuf_clone = qdf_nbuf_clone(nbuf);
  2950. if (!nbuf_clone) {
  2951. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2952. "qdf_nbuf_clone failed");
  2953. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2954. return nbuf;
  2955. }
  2956. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2957. }
  2958. if (nbuf_clone) {
  2959. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2960. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2961. } else {
  2962. qdf_nbuf_free(nbuf_clone);
  2963. }
  2964. }
  2965. if (no_enc_frame)
  2966. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2967. else
  2968. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2969. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2970. if ((!nbuf) && no_enc_frame) {
  2971. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2972. }
  2973. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2974. return nbuf;
  2975. }
  2976. #else
  2977. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2978. qdf_nbuf_t nbuf)
  2979. {
  2980. return dp_tx_send(soc, vdev_id, nbuf);
  2981. }
  2982. #endif
  2983. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  2984. static inline
  2985. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  2986. {
  2987. if (nbuf) {
  2988. qdf_prefetch(&nbuf->len);
  2989. qdf_prefetch(&nbuf->data);
  2990. }
  2991. }
  2992. #else
  2993. static inline
  2994. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  2995. {
  2996. }
  2997. #endif
  2998. #ifdef DP_UMAC_HW_RESET_SUPPORT
  2999. /*
  3000. * dp_tx_drop() - Drop the frame on a given VAP
  3001. * @soc: DP soc handle
  3002. * @vdev_id: id of DP vdev handle
  3003. * @nbuf: skb
  3004. *
  3005. * Drop all the incoming packets
  3006. *
  3007. * Return: nbuf
  3008. *
  3009. */
  3010. qdf_nbuf_t dp_tx_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3011. qdf_nbuf_t nbuf)
  3012. {
  3013. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3014. struct dp_vdev *vdev = NULL;
  3015. vdev = soc->vdev_id_map[vdev_id];
  3016. if (qdf_unlikely(!vdev))
  3017. return nbuf;
  3018. DP_STATS_INC(vdev, tx_i.dropped.drop_ingress, 1);
  3019. return nbuf;
  3020. }
  3021. /*
  3022. * dp_tx_exc_drop() - Drop the frame on a given VAP
  3023. * @soc: DP soc handle
  3024. * @vdev_id: id of DP vdev handle
  3025. * @nbuf: skb
  3026. * @tx_exc_metadata: Handle that holds exception path meta data
  3027. *
  3028. * Drop all the incoming packets
  3029. *
  3030. * Return: nbuf
  3031. *
  3032. */
  3033. qdf_nbuf_t dp_tx_exc_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3034. qdf_nbuf_t nbuf,
  3035. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3036. {
  3037. return dp_tx_drop(soc_hdl, vdev_id, nbuf);
  3038. }
  3039. #endif
  3040. /*
  3041. * dp_tx_send() - Transmit a frame on a given VAP
  3042. * @soc: DP soc handle
  3043. * @vdev_id: id of DP vdev handle
  3044. * @nbuf: skb
  3045. *
  3046. * Entry point for Core Tx layer (DP_TX) invoked from
  3047. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  3048. * cases
  3049. *
  3050. * Return: NULL on success,
  3051. * nbuf when it fails to send
  3052. */
  3053. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3054. qdf_nbuf_t nbuf)
  3055. {
  3056. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3057. uint16_t peer_id = HTT_INVALID_PEER;
  3058. /*
  3059. * doing a memzero is causing additional function call overhead
  3060. * so doing static stack clearing
  3061. */
  3062. struct dp_tx_msdu_info_s msdu_info = {0};
  3063. struct dp_vdev *vdev = NULL;
  3064. qdf_nbuf_t end_nbuf = NULL;
  3065. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3066. return nbuf;
  3067. /*
  3068. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3069. * this in per packet path.
  3070. *
  3071. * As in this path vdev memory is already protected with netdev
  3072. * tx lock
  3073. */
  3074. vdev = soc->vdev_id_map[vdev_id];
  3075. if (qdf_unlikely(!vdev))
  3076. return nbuf;
  3077. /*
  3078. * Set Default Host TID value to invalid TID
  3079. * (TID override disabled)
  3080. */
  3081. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  3082. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_headlen(nbuf));
  3083. if (qdf_unlikely(vdev->mesh_vdev)) {
  3084. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  3085. &msdu_info);
  3086. if (!nbuf_mesh) {
  3087. dp_verbose_debug("Extracting mesh metadata failed");
  3088. return nbuf;
  3089. }
  3090. nbuf = nbuf_mesh;
  3091. }
  3092. /*
  3093. * Get HW Queue to use for this frame.
  3094. * TCL supports upto 4 DMA rings, out of which 3 rings are
  3095. * dedicated for data and 1 for command.
  3096. * "queue_id" maps to one hardware ring.
  3097. * With each ring, we also associate a unique Tx descriptor pool
  3098. * to minimize lock contention for these resources.
  3099. */
  3100. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3101. DP_STATS_INC(vdev, tx_i.rcvd_per_core[msdu_info.tx_queue.desc_pool_id],
  3102. 1);
  3103. /*
  3104. * TCL H/W supports 2 DSCP-TID mapping tables.
  3105. * Table 1 - Default DSCP-TID mapping table
  3106. * Table 2 - 1 DSCP-TID override table
  3107. *
  3108. * If we need a different DSCP-TID mapping for this vap,
  3109. * call tid_classify to extract DSCP/ToS from frame and
  3110. * map to a TID and store in msdu_info. This is later used
  3111. * to fill in TCL Input descriptor (per-packet TID override).
  3112. */
  3113. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  3114. /*
  3115. * Classify the frame and call corresponding
  3116. * "prepare" function which extracts the segment (TSO)
  3117. * and fragmentation information (for TSO , SG, ME, or Raw)
  3118. * into MSDU_INFO structure which is later used to fill
  3119. * SW and HW descriptors.
  3120. */
  3121. if (qdf_nbuf_is_tso(nbuf)) {
  3122. dp_verbose_debug("TSO frame %pK", vdev);
  3123. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  3124. qdf_nbuf_len(nbuf));
  3125. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  3126. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  3127. qdf_nbuf_len(nbuf));
  3128. return nbuf;
  3129. }
  3130. goto send_multiple;
  3131. }
  3132. /* SG */
  3133. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  3134. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  3135. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  3136. return nbuf;
  3137. } else {
  3138. struct dp_tx_seg_info_s seg_info = {0};
  3139. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  3140. &msdu_info);
  3141. if (!nbuf)
  3142. return NULL;
  3143. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  3144. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  3145. qdf_nbuf_len(nbuf));
  3146. goto send_multiple;
  3147. }
  3148. }
  3149. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  3150. return NULL;
  3151. /* RAW */
  3152. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  3153. struct dp_tx_seg_info_s seg_info = {0};
  3154. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  3155. if (!nbuf)
  3156. return NULL;
  3157. dp_verbose_debug("Raw frame %pK", vdev);
  3158. goto send_multiple;
  3159. }
  3160. if (qdf_unlikely(vdev->nawds_enabled)) {
  3161. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  3162. qdf_nbuf_data(nbuf);
  3163. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  3164. uint16_t sa_peer_id = DP_INVALID_PEER;
  3165. if (!soc->ast_offload_support) {
  3166. struct dp_ast_entry *ast_entry = NULL;
  3167. qdf_spin_lock_bh(&soc->ast_lock);
  3168. ast_entry = dp_peer_ast_hash_find_by_pdevid
  3169. (soc,
  3170. (uint8_t *)(eh->ether_shost),
  3171. vdev->pdev->pdev_id);
  3172. if (ast_entry)
  3173. sa_peer_id = ast_entry->peer_id;
  3174. qdf_spin_unlock_bh(&soc->ast_lock);
  3175. }
  3176. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3177. sa_peer_id);
  3178. }
  3179. peer_id = DP_INVALID_PEER;
  3180. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3181. 1, qdf_nbuf_len(nbuf));
  3182. }
  3183. /* Single linear frame */
  3184. /*
  3185. * If nbuf is a simple linear frame, use send_single function to
  3186. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3187. * SRNG. There is no need to setup a MSDU extension descriptor.
  3188. */
  3189. dp_tx_prefetch_nbuf_data(nbuf);
  3190. nbuf = dp_tx_send_msdu_single_wrapper(vdev, nbuf, &msdu_info,
  3191. peer_id, end_nbuf);
  3192. return nbuf;
  3193. send_multiple:
  3194. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3195. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  3196. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  3197. return nbuf;
  3198. }
  3199. /**
  3200. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  3201. * case to vaoid check in perpkt path.
  3202. * @soc: DP soc handle
  3203. * @vdev_id: id of DP vdev handle
  3204. * @nbuf: skb
  3205. *
  3206. * Entry point for Core Tx layer (DP_TX) invoked from
  3207. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  3208. * with special condition to avoid per pkt check in dp_tx_send
  3209. *
  3210. * Return: NULL on success,
  3211. * nbuf when it fails to send
  3212. */
  3213. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3214. uint8_t vdev_id, qdf_nbuf_t nbuf)
  3215. {
  3216. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3217. struct dp_vdev *vdev = NULL;
  3218. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3219. return nbuf;
  3220. /*
  3221. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3222. * this in per packet path.
  3223. *
  3224. * As in this path vdev memory is already protected with netdev
  3225. * tx lock
  3226. */
  3227. vdev = soc->vdev_id_map[vdev_id];
  3228. if (qdf_unlikely(!vdev))
  3229. return nbuf;
  3230. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3231. == QDF_STATUS_E_FAILURE)) {
  3232. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3233. return nbuf;
  3234. }
  3235. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3236. }
  3237. #ifdef UMAC_SUPPORT_PROXY_ARP
  3238. /**
  3239. * dp_tx_proxy_arp() - Tx proxy arp handler
  3240. * @vdev: datapath vdev handle
  3241. * @buf: sk buffer
  3242. *
  3243. * Return: status
  3244. */
  3245. static inline
  3246. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3247. {
  3248. if (vdev->osif_proxy_arp)
  3249. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3250. /*
  3251. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3252. * osif_proxy_arp has a valid function pointer assigned
  3253. * to it
  3254. */
  3255. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3256. return QDF_STATUS_NOT_INITIALIZED;
  3257. }
  3258. #else
  3259. /**
  3260. * dp_tx_proxy_arp() - Tx proxy arp handler
  3261. * @vdev: datapath vdev handle
  3262. * @buf: sk buffer
  3263. *
  3264. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  3265. * is not defined.
  3266. *
  3267. * Return: status
  3268. */
  3269. static inline
  3270. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3271. {
  3272. return QDF_STATUS_SUCCESS;
  3273. }
  3274. #endif
  3275. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  3276. #ifdef WLAN_MCAST_MLO
  3277. static bool
  3278. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3279. struct dp_tx_desc_s *tx_desc,
  3280. qdf_nbuf_t nbuf,
  3281. uint8_t reinject_reason)
  3282. {
  3283. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3284. if (soc->arch_ops.dp_tx_mcast_handler)
  3285. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3286. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3287. return true;
  3288. }
  3289. return false;
  3290. }
  3291. #else /* WLAN_MCAST_MLO */
  3292. static inline bool
  3293. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3294. struct dp_tx_desc_s *tx_desc,
  3295. qdf_nbuf_t nbuf,
  3296. uint8_t reinject_reason)
  3297. {
  3298. return false;
  3299. }
  3300. #endif /* WLAN_MCAST_MLO */
  3301. #else
  3302. static inline bool
  3303. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3304. struct dp_tx_desc_s *tx_desc,
  3305. qdf_nbuf_t nbuf,
  3306. uint8_t reinject_reason)
  3307. {
  3308. return false;
  3309. }
  3310. #endif
  3311. /**
  3312. * dp_tx_reinject_handler() - Tx Reinject Handler
  3313. * @soc: datapath soc handle
  3314. * @vdev: datapath vdev handle
  3315. * @tx_desc: software descriptor head pointer
  3316. * @status : Tx completion status from HTT descriptor
  3317. * @reinject_reason : reinject reason from HTT descriptor
  3318. *
  3319. * This function reinjects frames back to Target.
  3320. * Todo - Host queue needs to be added
  3321. *
  3322. * Return: none
  3323. */
  3324. void dp_tx_reinject_handler(struct dp_soc *soc,
  3325. struct dp_vdev *vdev,
  3326. struct dp_tx_desc_s *tx_desc,
  3327. uint8_t *status,
  3328. uint8_t reinject_reason)
  3329. {
  3330. struct dp_peer *peer = NULL;
  3331. uint32_t peer_id = HTT_INVALID_PEER;
  3332. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3333. qdf_nbuf_t nbuf_copy = NULL;
  3334. struct dp_tx_msdu_info_s msdu_info;
  3335. #ifdef WDS_VENDOR_EXTENSION
  3336. int is_mcast = 0, is_ucast = 0;
  3337. int num_peers_3addr = 0;
  3338. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3339. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3340. #endif
  3341. struct dp_txrx_peer *txrx_peer;
  3342. qdf_assert(vdev);
  3343. dp_tx_debug("Tx reinject path");
  3344. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3345. qdf_nbuf_len(tx_desc->nbuf));
  3346. if (dp_tx_reinject_mlo_hdl(soc, vdev, tx_desc, nbuf, reinject_reason))
  3347. return;
  3348. #ifdef WDS_VENDOR_EXTENSION
  3349. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3350. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3351. } else {
  3352. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3353. }
  3354. is_ucast = !is_mcast;
  3355. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3356. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3357. txrx_peer = dp_get_txrx_peer(peer);
  3358. if (!txrx_peer || txrx_peer->bss_peer)
  3359. continue;
  3360. /* Detect wds peers that use 3-addr framing for mcast.
  3361. * if there are any, the bss_peer is used to send the
  3362. * the mcast frame using 3-addr format. all wds enabled
  3363. * peers that use 4-addr framing for mcast frames will
  3364. * be duplicated and sent as 4-addr frames below.
  3365. */
  3366. if (!txrx_peer->wds_enabled ||
  3367. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3368. num_peers_3addr = 1;
  3369. break;
  3370. }
  3371. }
  3372. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3373. #endif
  3374. if (qdf_unlikely(vdev->mesh_vdev)) {
  3375. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3376. } else {
  3377. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3378. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3379. txrx_peer = dp_get_txrx_peer(peer);
  3380. if (!txrx_peer)
  3381. continue;
  3382. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3383. #ifdef WDS_VENDOR_EXTENSION
  3384. /*
  3385. * . if 3-addr STA, then send on BSS Peer
  3386. * . if Peer WDS enabled and accept 4-addr mcast,
  3387. * send mcast on that peer only
  3388. * . if Peer WDS enabled and accept 4-addr ucast,
  3389. * send ucast on that peer only
  3390. */
  3391. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3392. (txrx_peer->wds_enabled &&
  3393. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3394. (is_ucast &&
  3395. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3396. #else
  3397. (txrx_peer->bss_peer &&
  3398. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3399. #endif
  3400. peer_id = DP_INVALID_PEER;
  3401. nbuf_copy = qdf_nbuf_copy(nbuf);
  3402. if (!nbuf_copy) {
  3403. dp_tx_debug("nbuf copy failed");
  3404. break;
  3405. }
  3406. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3407. dp_tx_get_queue(vdev, nbuf,
  3408. &msdu_info.tx_queue);
  3409. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3410. nbuf_copy,
  3411. &msdu_info,
  3412. peer_id,
  3413. NULL);
  3414. if (nbuf_copy) {
  3415. dp_tx_debug("pkt send failed");
  3416. qdf_nbuf_free(nbuf_copy);
  3417. }
  3418. }
  3419. }
  3420. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3421. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  3422. QDF_DMA_TO_DEVICE, nbuf->len);
  3423. qdf_nbuf_free(nbuf);
  3424. }
  3425. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3426. }
  3427. /**
  3428. * dp_tx_inspect_handler() - Tx Inspect Handler
  3429. * @soc: datapath soc handle
  3430. * @vdev: datapath vdev handle
  3431. * @tx_desc: software descriptor head pointer
  3432. * @status : Tx completion status from HTT descriptor
  3433. *
  3434. * Handles Tx frames sent back to Host for inspection
  3435. * (ProxyARP)
  3436. *
  3437. * Return: none
  3438. */
  3439. void dp_tx_inspect_handler(struct dp_soc *soc,
  3440. struct dp_vdev *vdev,
  3441. struct dp_tx_desc_s *tx_desc,
  3442. uint8_t *status)
  3443. {
  3444. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3445. "%s Tx inspect path",
  3446. __func__);
  3447. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3448. qdf_nbuf_len(tx_desc->nbuf));
  3449. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3450. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3451. }
  3452. #ifdef MESH_MODE_SUPPORT
  3453. /**
  3454. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3455. * in mesh meta header
  3456. * @tx_desc: software descriptor head pointer
  3457. * @ts: pointer to tx completion stats
  3458. * Return: none
  3459. */
  3460. static
  3461. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3462. struct hal_tx_completion_status *ts)
  3463. {
  3464. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3465. if (!tx_desc->msdu_ext_desc) {
  3466. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3467. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3468. "netbuf %pK offset %d",
  3469. netbuf, tx_desc->pkt_offset);
  3470. return;
  3471. }
  3472. }
  3473. }
  3474. #else
  3475. static
  3476. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3477. struct hal_tx_completion_status *ts)
  3478. {
  3479. }
  3480. #endif
  3481. #ifdef CONFIG_SAWF
  3482. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3483. struct dp_vdev *vdev,
  3484. struct dp_txrx_peer *txrx_peer,
  3485. struct dp_tx_desc_s *tx_desc,
  3486. struct hal_tx_completion_status *ts,
  3487. uint8_t tid)
  3488. {
  3489. dp_sawf_tx_compl_update_peer_stats(soc, vdev, txrx_peer, tx_desc,
  3490. ts, tid);
  3491. }
  3492. static void dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3493. uint32_t nw_delay,
  3494. uint32_t sw_delay,
  3495. uint32_t hw_delay)
  3496. {
  3497. dp_peer_tid_delay_avg(tx_delay,
  3498. nw_delay,
  3499. sw_delay,
  3500. hw_delay);
  3501. }
  3502. #else
  3503. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3504. struct dp_vdev *vdev,
  3505. struct dp_txrx_peer *txrx_peer,
  3506. struct dp_tx_desc_s *tx_desc,
  3507. struct hal_tx_completion_status *ts,
  3508. uint8_t tid)
  3509. {
  3510. }
  3511. static inline void
  3512. dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3513. uint32_t nw_delay, uint32_t sw_delay,
  3514. uint32_t hw_delay)
  3515. {
  3516. }
  3517. #endif
  3518. #ifdef QCA_PEER_EXT_STATS
  3519. #ifdef WLAN_CONFIG_TX_DELAY
  3520. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3521. struct dp_tx_desc_s *tx_desc,
  3522. struct hal_tx_completion_status *ts,
  3523. struct dp_vdev *vdev)
  3524. {
  3525. struct dp_soc *soc = vdev->pdev->soc;
  3526. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3527. int64_t timestamp_ingress, timestamp_hw_enqueue;
  3528. uint32_t sw_enqueue_delay, fwhw_transmit_delay = 0;
  3529. if (!ts->valid)
  3530. return;
  3531. timestamp_ingress = qdf_nbuf_get_timestamp_us(tx_desc->nbuf);
  3532. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3533. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3534. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3535. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3536. if (!soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3537. &fwhw_transmit_delay))
  3538. dp_hist_update_stats(&tx_delay->hwtx_delay,
  3539. fwhw_transmit_delay);
  3540. dp_tx_compute_delay_avg(tx_delay, 0, sw_enqueue_delay,
  3541. fwhw_transmit_delay);
  3542. }
  3543. #else
  3544. /*
  3545. * dp_tx_compute_tid_delay() - Compute per TID delay
  3546. * @stats: Per TID delay stats
  3547. * @tx_desc: Software Tx descriptor
  3548. * @ts: Tx completion status
  3549. * @vdev: vdev
  3550. *
  3551. * Compute the software enqueue and hw enqueue delays and
  3552. * update the respective histograms
  3553. *
  3554. * Return: void
  3555. */
  3556. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3557. struct dp_tx_desc_s *tx_desc,
  3558. struct hal_tx_completion_status *ts,
  3559. struct dp_vdev *vdev)
  3560. {
  3561. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3562. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3563. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3564. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3565. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3566. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3567. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3568. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3569. timestamp_hw_enqueue);
  3570. /*
  3571. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3572. */
  3573. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3574. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3575. }
  3576. #endif
  3577. /*
  3578. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3579. * @txrx_peer: DP peer context
  3580. * @tx_desc: Tx software descriptor
  3581. * @tid: Transmission ID
  3582. * @ring_id: Rx CPU context ID/CPU_ID
  3583. *
  3584. * Update the peer extended stats. These are enhanced other
  3585. * delay stats per msdu level.
  3586. *
  3587. * Return: void
  3588. */
  3589. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3590. struct dp_tx_desc_s *tx_desc,
  3591. struct hal_tx_completion_status *ts,
  3592. uint8_t ring_id)
  3593. {
  3594. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3595. struct dp_soc *soc = NULL;
  3596. struct dp_peer_delay_stats *delay_stats = NULL;
  3597. uint8_t tid;
  3598. soc = pdev->soc;
  3599. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3600. return;
  3601. tid = ts->tid;
  3602. delay_stats = txrx_peer->delay_stats;
  3603. qdf_assert(delay_stats);
  3604. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3605. /*
  3606. * For non-TID packets use the TID 9
  3607. */
  3608. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3609. tid = CDP_MAX_DATA_TIDS - 1;
  3610. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3611. tx_desc, ts, txrx_peer->vdev);
  3612. }
  3613. #else
  3614. static inline
  3615. void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3616. struct dp_tx_desc_s *tx_desc,
  3617. struct hal_tx_completion_status *ts,
  3618. uint8_t ring_id)
  3619. {
  3620. }
  3621. #endif
  3622. #ifdef WLAN_PEER_JITTER
  3623. /*
  3624. * dp_tx_jitter_get_avg_jitter() - compute the average jitter
  3625. * @curr_delay: Current delay
  3626. * @prev_Delay: Previous delay
  3627. * @avg_jitter: Average Jitter
  3628. * Return: Newly Computed Average Jitter
  3629. */
  3630. static uint32_t dp_tx_jitter_get_avg_jitter(uint32_t curr_delay,
  3631. uint32_t prev_delay,
  3632. uint32_t avg_jitter)
  3633. {
  3634. uint32_t curr_jitter;
  3635. int32_t jitter_diff;
  3636. curr_jitter = qdf_abs(curr_delay - prev_delay);
  3637. if (!avg_jitter)
  3638. return curr_jitter;
  3639. jitter_diff = curr_jitter - avg_jitter;
  3640. if (jitter_diff < 0)
  3641. avg_jitter = avg_jitter -
  3642. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3643. else
  3644. avg_jitter = avg_jitter +
  3645. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3646. return avg_jitter;
  3647. }
  3648. /*
  3649. * dp_tx_jitter_get_avg_delay() - compute the average delay
  3650. * @curr_delay: Current delay
  3651. * @avg_Delay: Average delay
  3652. * Return: Newly Computed Average Delay
  3653. */
  3654. static uint32_t dp_tx_jitter_get_avg_delay(uint32_t curr_delay,
  3655. uint32_t avg_delay)
  3656. {
  3657. int32_t delay_diff;
  3658. if (!avg_delay)
  3659. return curr_delay;
  3660. delay_diff = curr_delay - avg_delay;
  3661. if (delay_diff < 0)
  3662. avg_delay = avg_delay - (qdf_abs(delay_diff) >>
  3663. DP_AVG_DELAY_WEIGHT_DENOM);
  3664. else
  3665. avg_delay = avg_delay + (qdf_abs(delay_diff) >>
  3666. DP_AVG_DELAY_WEIGHT_DENOM);
  3667. return avg_delay;
  3668. }
  3669. #ifdef WLAN_CONFIG_TX_DELAY
  3670. /*
  3671. * dp_tx_compute_cur_delay() - get the current delay
  3672. * @soc: soc handle
  3673. * @vdev: vdev structure for data path state
  3674. * @ts: Tx completion status
  3675. * @curr_delay: current delay
  3676. * @tx_desc: tx descriptor
  3677. * Return: void
  3678. */
  3679. static
  3680. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3681. struct dp_vdev *vdev,
  3682. struct hal_tx_completion_status *ts,
  3683. uint32_t *curr_delay,
  3684. struct dp_tx_desc_s *tx_desc)
  3685. {
  3686. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3687. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3688. status = soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3689. curr_delay);
  3690. return status;
  3691. }
  3692. #else
  3693. static
  3694. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3695. struct dp_vdev *vdev,
  3696. struct hal_tx_completion_status *ts,
  3697. uint32_t *curr_delay,
  3698. struct dp_tx_desc_s *tx_desc)
  3699. {
  3700. int64_t current_timestamp, timestamp_hw_enqueue;
  3701. current_timestamp = qdf_ktime_to_us(qdf_ktime_real_get());
  3702. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3703. *curr_delay = (uint32_t)(current_timestamp - timestamp_hw_enqueue);
  3704. return QDF_STATUS_SUCCESS;
  3705. }
  3706. #endif
  3707. /* dp_tx_compute_tid_jitter() - compute per tid per ring jitter
  3708. * @jiiter - per tid per ring jitter stats
  3709. * @ts: Tx completion status
  3710. * @vdev - vdev structure for data path state
  3711. * @tx_desc - tx descriptor
  3712. * Return: void
  3713. */
  3714. static void dp_tx_compute_tid_jitter(struct cdp_peer_tid_stats *jitter,
  3715. struct hal_tx_completion_status *ts,
  3716. struct dp_vdev *vdev,
  3717. struct dp_tx_desc_s *tx_desc)
  3718. {
  3719. uint32_t curr_delay, avg_delay, avg_jitter, prev_delay;
  3720. struct dp_soc *soc = vdev->pdev->soc;
  3721. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3722. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3723. jitter->tx_drop += 1;
  3724. return;
  3725. }
  3726. status = dp_tx_compute_cur_delay(soc, vdev, ts, &curr_delay,
  3727. tx_desc);
  3728. if (QDF_IS_STATUS_SUCCESS(status)) {
  3729. avg_delay = jitter->tx_avg_delay;
  3730. avg_jitter = jitter->tx_avg_jitter;
  3731. prev_delay = jitter->tx_prev_delay;
  3732. avg_jitter = dp_tx_jitter_get_avg_jitter(curr_delay,
  3733. prev_delay,
  3734. avg_jitter);
  3735. avg_delay = dp_tx_jitter_get_avg_delay(curr_delay, avg_delay);
  3736. jitter->tx_avg_delay = avg_delay;
  3737. jitter->tx_avg_jitter = avg_jitter;
  3738. jitter->tx_prev_delay = curr_delay;
  3739. jitter->tx_total_success += 1;
  3740. } else if (status == QDF_STATUS_E_FAILURE) {
  3741. jitter->tx_avg_err += 1;
  3742. }
  3743. }
  3744. /* dp_tx_update_peer_jitter_stats() - Update the peer jitter stats
  3745. * @txrx_peer: DP peer context
  3746. * @tx_desc: Tx software descriptor
  3747. * @ts: Tx completion status
  3748. * @ring_id: Rx CPU context ID/CPU_ID
  3749. * Return: void
  3750. */
  3751. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3752. struct dp_tx_desc_s *tx_desc,
  3753. struct hal_tx_completion_status *ts,
  3754. uint8_t ring_id)
  3755. {
  3756. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3757. struct dp_soc *soc = pdev->soc;
  3758. struct cdp_peer_tid_stats *jitter_stats = NULL;
  3759. uint8_t tid;
  3760. struct cdp_peer_tid_stats *rx_tid = NULL;
  3761. if (qdf_likely(!wlan_cfg_is_peer_jitter_stats_enabled(soc->wlan_cfg_ctx)))
  3762. return;
  3763. tid = ts->tid;
  3764. jitter_stats = txrx_peer->jitter_stats;
  3765. qdf_assert_always(jitter_stats);
  3766. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3767. /*
  3768. * For non-TID packets use the TID 9
  3769. */
  3770. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3771. tid = CDP_MAX_DATA_TIDS - 1;
  3772. rx_tid = &jitter_stats[tid * CDP_MAX_TXRX_CTX + ring_id];
  3773. dp_tx_compute_tid_jitter(rx_tid,
  3774. ts, txrx_peer->vdev, tx_desc);
  3775. }
  3776. #else
  3777. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3778. struct dp_tx_desc_s *tx_desc,
  3779. struct hal_tx_completion_status *ts,
  3780. uint8_t ring_id)
  3781. {
  3782. }
  3783. #endif
  3784. #ifdef HW_TX_DELAY_STATS_ENABLE
  3785. /**
  3786. * dp_update_tx_delay_stats() - update the delay stats
  3787. * @vdev: vdev handle
  3788. * @delay: delay in ms or us based on the flag delay_in_us
  3789. * @tid: tid value
  3790. * @mode: type of tx delay mode
  3791. * @ring id: ring number
  3792. * @delay_in_us: flag to indicate whether the delay is in ms or us
  3793. *
  3794. * Return: none
  3795. */
  3796. static inline
  3797. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3798. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3799. {
  3800. struct cdp_tid_tx_stats *tstats =
  3801. &vdev->stats.tid_tx_stats[ring_id][tid];
  3802. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3803. delay_in_us);
  3804. }
  3805. #else
  3806. static inline
  3807. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3808. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3809. {
  3810. struct cdp_tid_tx_stats *tstats =
  3811. &vdev->pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3812. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3813. delay_in_us);
  3814. }
  3815. #endif
  3816. /**
  3817. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3818. * to pass in correct fields
  3819. *
  3820. * @vdev: pdev handle
  3821. * @tx_desc: tx descriptor
  3822. * @tid: tid value
  3823. * @ring_id: TCL or WBM ring number for transmit path
  3824. * Return: none
  3825. */
  3826. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  3827. uint8_t tid, uint8_t ring_id)
  3828. {
  3829. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3830. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3831. uint32_t fwhw_transmit_delay_us;
  3832. if (qdf_likely(!vdev->pdev->delay_stats_flag) &&
  3833. qdf_likely(!dp_is_vdev_tx_delay_stats_enabled(vdev)))
  3834. return;
  3835. if (dp_is_vdev_tx_delay_stats_enabled(vdev)) {
  3836. fwhw_transmit_delay_us =
  3837. qdf_ktime_to_us(qdf_ktime_real_get()) -
  3838. qdf_ktime_to_us(tx_desc->timestamp);
  3839. /*
  3840. * Delay between packet enqueued to HW and Tx completion in us
  3841. */
  3842. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay_us, tid,
  3843. CDP_DELAY_STATS_FW_HW_TRANSMIT,
  3844. ring_id, true);
  3845. /*
  3846. * For MCL, only enqueue to completion delay is required
  3847. * so return if the vdev flag is enabled.
  3848. */
  3849. return;
  3850. }
  3851. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3852. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3853. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3854. timestamp_hw_enqueue);
  3855. /*
  3856. * Delay between packet enqueued to HW and Tx completion in ms
  3857. */
  3858. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay, tid,
  3859. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id,
  3860. false);
  3861. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3862. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3863. interframe_delay = (uint32_t)(timestamp_ingress -
  3864. vdev->prev_tx_enq_tstamp);
  3865. /*
  3866. * Delay in software enqueue
  3867. */
  3868. dp_update_tx_delay_stats(vdev, sw_enqueue_delay, tid,
  3869. CDP_DELAY_STATS_SW_ENQ, ring_id,
  3870. false);
  3871. /*
  3872. * Update interframe delay stats calculated at hardstart receive point.
  3873. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3874. * interframe delay will not be calculate correctly for 1st frame.
  3875. * On the other side, this will help in avoiding extra per packet check
  3876. * of !vdev->prev_tx_enq_tstamp.
  3877. */
  3878. dp_update_tx_delay_stats(vdev, interframe_delay, tid,
  3879. CDP_DELAY_STATS_TX_INTERFRAME, ring_id,
  3880. false);
  3881. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3882. }
  3883. #ifdef DISABLE_DP_STATS
  3884. static
  3885. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  3886. struct dp_txrx_peer *txrx_peer)
  3887. {
  3888. }
  3889. #else
  3890. static inline void
  3891. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer)
  3892. {
  3893. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3894. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3895. if (subtype != QDF_PROTO_INVALID)
  3896. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  3897. 1);
  3898. }
  3899. #endif
  3900. #ifndef QCA_ENHANCED_STATS_SUPPORT
  3901. #ifdef DP_PEER_EXTENDED_API
  3902. static inline uint8_t
  3903. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  3904. {
  3905. return txrx_peer->mpdu_retry_threshold;
  3906. }
  3907. #else
  3908. static inline uint8_t
  3909. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  3910. {
  3911. return 0;
  3912. }
  3913. #endif
  3914. /**
  3915. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  3916. *
  3917. * @ts: Tx compltion status
  3918. * @txrx_peer: datapath txrx_peer handle
  3919. *
  3920. * Return: void
  3921. */
  3922. static inline void
  3923. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3924. struct dp_txrx_peer *txrx_peer)
  3925. {
  3926. uint8_t mcs, pkt_type, dst_mcs_idx;
  3927. uint8_t retry_threshold = dp_tx_get_mpdu_retry_threshold(txrx_peer);
  3928. mcs = ts->mcs;
  3929. pkt_type = ts->pkt_type;
  3930. /* do HW to SW pkt type conversion */
  3931. pkt_type = (pkt_type >= HAL_DOT11_MAX ? DOT11_MAX :
  3932. hal_2_dp_pkt_type_map[pkt_type]);
  3933. dst_mcs_idx = dp_get_mcs_array_index_by_pkt_type_mcs(pkt_type, mcs);
  3934. if (MCS_INVALID_ARRAY_INDEX != dst_mcs_idx)
  3935. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3936. tx.pkt_type[pkt_type].mcs_count[dst_mcs_idx],
  3937. 1);
  3938. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1);
  3939. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1);
  3940. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3941. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3942. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3943. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc);
  3944. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc);
  3945. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1);
  3946. if (ts->first_msdu) {
  3947. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  3948. ts->transmit_cnt > 1);
  3949. if (!retry_threshold)
  3950. return;
  3951. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  3952. qdf_do_div(ts->transmit_cnt,
  3953. retry_threshold),
  3954. ts->transmit_cnt > retry_threshold);
  3955. }
  3956. }
  3957. #else
  3958. static inline void
  3959. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3960. struct dp_txrx_peer *txrx_peer)
  3961. {
  3962. }
  3963. #endif
  3964. /**
  3965. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3966. * per wbm ring
  3967. *
  3968. * @tx_desc: software descriptor head pointer
  3969. * @ts: Tx completion status
  3970. * @peer: peer handle
  3971. * @ring_id: ring number
  3972. *
  3973. * Return: None
  3974. */
  3975. static inline void
  3976. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3977. struct hal_tx_completion_status *ts,
  3978. struct dp_txrx_peer *txrx_peer, uint8_t ring_id)
  3979. {
  3980. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3981. uint8_t tid = ts->tid;
  3982. uint32_t length;
  3983. struct cdp_tid_tx_stats *tid_stats;
  3984. if (!pdev)
  3985. return;
  3986. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3987. tid = CDP_MAX_DATA_TIDS - 1;
  3988. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3989. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3990. dp_err_rl("Release source:%d is not from TQM", ts->release_src);
  3991. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.release_src_not_tqm, 1);
  3992. return;
  3993. }
  3994. length = qdf_nbuf_len(tx_desc->nbuf);
  3995. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  3996. if (qdf_unlikely(pdev->delay_stats_flag) ||
  3997. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(txrx_peer->vdev)))
  3998. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  3999. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  4000. tid_stats->tqm_status_cnt[ts->status]++;
  4001. }
  4002. if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
  4003. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  4004. ts->transmit_cnt > 1);
  4005. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
  4006. 1, ts->transmit_cnt > 2);
  4007. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma);
  4008. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  4009. ts->msdu_part_of_amsdu);
  4010. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  4011. !ts->msdu_part_of_amsdu);
  4012. txrx_peer->stats.per_pkt_stats.tx.last_tx_ts =
  4013. qdf_system_ticks();
  4014. dp_tx_update_peer_extd_stats(ts, txrx_peer);
  4015. return;
  4016. }
  4017. /*
  4018. * tx_failed is ideally supposed to be updated from HTT ppdu
  4019. * completion stats. But in IPQ807X/IPQ6018 chipsets owing to
  4020. * hw limitation there are no completions for failed cases.
  4021. * Hence updating tx_failed from data path. Please note that
  4022. * if tx_failed is fixed to be from ppdu, then this has to be
  4023. * removed
  4024. */
  4025. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4026. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  4027. ts->transmit_cnt > DP_RETRY_COUNT);
  4028. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer);
  4029. if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
  4030. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1);
  4031. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
  4032. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
  4033. length);
  4034. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
  4035. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1);
  4036. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
  4037. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1);
  4038. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
  4039. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1);
  4040. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
  4041. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1);
  4042. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
  4043. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1);
  4044. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
  4045. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4046. tx.dropped.fw_rem_queue_disable, 1);
  4047. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
  4048. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4049. tx.dropped.fw_rem_no_match, 1);
  4050. } else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
  4051. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4052. tx.dropped.drop_threshold, 1);
  4053. } else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
  4054. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4055. tx.dropped.drop_link_desc_na, 1);
  4056. } else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
  4057. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4058. tx.dropped.invalid_drop, 1);
  4059. } else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4060. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4061. tx.dropped.mcast_vdev_drop, 1);
  4062. } else {
  4063. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1);
  4064. }
  4065. }
  4066. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4067. /**
  4068. * dp_tx_flow_pool_lock() - take flow pool lock
  4069. * @soc: core txrx main context
  4070. * @tx_desc: tx desc
  4071. *
  4072. * Return: None
  4073. */
  4074. static inline
  4075. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  4076. struct dp_tx_desc_s *tx_desc)
  4077. {
  4078. struct dp_tx_desc_pool_s *pool;
  4079. uint8_t desc_pool_id;
  4080. desc_pool_id = tx_desc->pool_id;
  4081. pool = &soc->tx_desc[desc_pool_id];
  4082. qdf_spin_lock_bh(&pool->flow_pool_lock);
  4083. }
  4084. /**
  4085. * dp_tx_flow_pool_unlock() - release flow pool lock
  4086. * @soc: core txrx main context
  4087. * @tx_desc: tx desc
  4088. *
  4089. * Return: None
  4090. */
  4091. static inline
  4092. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  4093. struct dp_tx_desc_s *tx_desc)
  4094. {
  4095. struct dp_tx_desc_pool_s *pool;
  4096. uint8_t desc_pool_id;
  4097. desc_pool_id = tx_desc->pool_id;
  4098. pool = &soc->tx_desc[desc_pool_id];
  4099. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  4100. }
  4101. #else
  4102. static inline
  4103. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4104. {
  4105. }
  4106. static inline
  4107. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4108. {
  4109. }
  4110. #endif
  4111. /**
  4112. * dp_tx_notify_completion() - Notify tx completion for this desc
  4113. * @soc: core txrx main context
  4114. * @vdev: datapath vdev handle
  4115. * @tx_desc: tx desc
  4116. * @netbuf: buffer
  4117. * @status: tx status
  4118. *
  4119. * Return: none
  4120. */
  4121. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  4122. struct dp_vdev *vdev,
  4123. struct dp_tx_desc_s *tx_desc,
  4124. qdf_nbuf_t netbuf,
  4125. uint8_t status)
  4126. {
  4127. void *osif_dev;
  4128. ol_txrx_completion_fp tx_compl_cbk = NULL;
  4129. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  4130. qdf_assert(tx_desc);
  4131. if (!vdev ||
  4132. !vdev->osif_vdev) {
  4133. return;
  4134. }
  4135. osif_dev = vdev->osif_vdev;
  4136. tx_compl_cbk = vdev->tx_comp;
  4137. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4138. flag |= BIT(QDF_TX_RX_STATUS_OK);
  4139. if (tx_compl_cbk)
  4140. tx_compl_cbk(netbuf, osif_dev, flag);
  4141. }
  4142. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  4143. * @pdev: pdev handle
  4144. * @tid: tid value
  4145. * @txdesc_ts: timestamp from txdesc
  4146. * @ppdu_id: ppdu id
  4147. *
  4148. * Return: none
  4149. */
  4150. #ifdef FEATURE_PERPKT_INFO
  4151. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4152. struct dp_txrx_peer *txrx_peer,
  4153. uint8_t tid,
  4154. uint64_t txdesc_ts,
  4155. uint32_t ppdu_id)
  4156. {
  4157. uint64_t delta_ms;
  4158. struct cdp_tx_sojourn_stats *sojourn_stats;
  4159. struct dp_peer *primary_link_peer = NULL;
  4160. struct dp_soc *link_peer_soc = NULL;
  4161. if (qdf_unlikely(!pdev->enhanced_stats_en))
  4162. return;
  4163. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  4164. tid >= CDP_DATA_TID_MAX))
  4165. return;
  4166. if (qdf_unlikely(!pdev->sojourn_buf))
  4167. return;
  4168. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  4169. txrx_peer->peer_id,
  4170. DP_MOD_ID_TX_COMP);
  4171. if (qdf_unlikely(!primary_link_peer))
  4172. return;
  4173. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  4174. qdf_nbuf_data(pdev->sojourn_buf);
  4175. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  4176. sojourn_stats->cookie = (void *)
  4177. dp_monitor_peer_get_peerstats_ctx(link_peer_soc,
  4178. primary_link_peer);
  4179. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4180. txdesc_ts;
  4181. qdf_ewma_tx_lag_add(&txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid],
  4182. delta_ms);
  4183. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  4184. sojourn_stats->num_msdus[tid] = 1;
  4185. sojourn_stats->avg_sojourn_msdu[tid].internal =
  4186. txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  4187. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  4188. pdev->sojourn_buf, HTT_INVALID_PEER,
  4189. WDI_NO_VAL, pdev->pdev_id);
  4190. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  4191. sojourn_stats->num_msdus[tid] = 0;
  4192. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  4193. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  4194. }
  4195. #else
  4196. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4197. struct dp_txrx_peer *txrx_peer,
  4198. uint8_t tid,
  4199. uint64_t txdesc_ts,
  4200. uint32_t ppdu_id)
  4201. {
  4202. }
  4203. #endif
  4204. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  4205. /**
  4206. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  4207. * @soc: dp_soc handle
  4208. * @desc: Tx Descriptor
  4209. * @ts: HAL Tx completion descriptor contents
  4210. *
  4211. * This function is used to send tx completion to packet capture
  4212. */
  4213. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  4214. struct dp_tx_desc_s *desc,
  4215. struct hal_tx_completion_status *ts)
  4216. {
  4217. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  4218. desc, ts->peer_id,
  4219. WDI_NO_VAL, desc->pdev->pdev_id);
  4220. }
  4221. #endif
  4222. /**
  4223. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  4224. * @soc: DP Soc handle
  4225. * @tx_desc: software Tx descriptor
  4226. * @ts : Tx completion status from HAL/HTT descriptor
  4227. *
  4228. * Return: none
  4229. */
  4230. void
  4231. dp_tx_comp_process_desc(struct dp_soc *soc,
  4232. struct dp_tx_desc_s *desc,
  4233. struct hal_tx_completion_status *ts,
  4234. struct dp_txrx_peer *txrx_peer)
  4235. {
  4236. uint64_t time_latency = 0;
  4237. uint16_t peer_id = DP_INVALID_PEER_ID;
  4238. /*
  4239. * m_copy/tx_capture modes are not supported for
  4240. * scatter gather packets
  4241. */
  4242. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  4243. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4244. qdf_ktime_to_ms(desc->timestamp));
  4245. }
  4246. dp_send_completion_to_pkt_capture(soc, desc, ts);
  4247. if (dp_tx_pkt_tracepoints_enabled())
  4248. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  4249. desc->msdu_ext_desc ?
  4250. desc->msdu_ext_desc->tso_desc : NULL,
  4251. qdf_ktime_to_ms(desc->timestamp));
  4252. if (!(desc->msdu_ext_desc)) {
  4253. dp_tx_enh_unmap(soc, desc);
  4254. if (txrx_peer)
  4255. peer_id = txrx_peer->peer_id;
  4256. if (QDF_STATUS_SUCCESS ==
  4257. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  4258. return;
  4259. }
  4260. if (QDF_STATUS_SUCCESS ==
  4261. dp_get_completion_indication_for_stack(soc,
  4262. desc->pdev,
  4263. txrx_peer, ts,
  4264. desc->nbuf,
  4265. time_latency)) {
  4266. dp_send_completion_to_stack(soc,
  4267. desc->pdev,
  4268. ts->peer_id,
  4269. ts->ppdu_id,
  4270. desc->nbuf);
  4271. return;
  4272. }
  4273. }
  4274. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  4275. dp_tx_comp_free_buf(soc, desc, false);
  4276. }
  4277. #ifdef DISABLE_DP_STATS
  4278. /**
  4279. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  4280. * @soc: core txrx main context
  4281. * @tx_desc: tx desc
  4282. * @status: tx status
  4283. *
  4284. * Return: none
  4285. */
  4286. static inline
  4287. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4288. struct dp_vdev *vdev,
  4289. struct dp_tx_desc_s *tx_desc,
  4290. uint8_t status)
  4291. {
  4292. }
  4293. #else
  4294. static inline
  4295. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4296. struct dp_vdev *vdev,
  4297. struct dp_tx_desc_s *tx_desc,
  4298. uint8_t status)
  4299. {
  4300. void *osif_dev;
  4301. ol_txrx_stats_rx_fp stats_cbk;
  4302. uint8_t pkt_type;
  4303. qdf_assert(tx_desc);
  4304. if (!vdev ||
  4305. !vdev->osif_vdev ||
  4306. !vdev->stats_cb)
  4307. return;
  4308. osif_dev = vdev->osif_vdev;
  4309. stats_cbk = vdev->stats_cb;
  4310. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  4311. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4312. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  4313. &pkt_type);
  4314. }
  4315. #endif
  4316. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  4317. QDF_STATUS
  4318. dp_tx_compute_hw_delay_us(struct hal_tx_completion_status *ts,
  4319. uint32_t delta_tsf,
  4320. uint32_t *delay_us)
  4321. {
  4322. uint32_t buffer_ts;
  4323. uint32_t delay;
  4324. if (!delay_us)
  4325. return QDF_STATUS_E_INVAL;
  4326. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  4327. if (!ts->valid)
  4328. return QDF_STATUS_E_INVAL;
  4329. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  4330. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  4331. * valid up to 29 bits.
  4332. */
  4333. buffer_ts = ts->buffer_timestamp << 10;
  4334. delay = ts->tsf - buffer_ts - delta_tsf;
  4335. if (qdf_unlikely(delay & 0x80000000)) {
  4336. dp_err_rl("delay = 0x%x (-ve)\n"
  4337. "release_src = %d\n"
  4338. "ppdu_id = 0x%x\n"
  4339. "peer_id = 0x%x\n"
  4340. "tid = 0x%x\n"
  4341. "release_reason = %d\n"
  4342. "tsf = %u (0x%x)\n"
  4343. "buffer_timestamp = %u (0x%x)\n"
  4344. "delta_tsf = %u (0x%x)\n",
  4345. delay, ts->release_src, ts->ppdu_id, ts->peer_id,
  4346. ts->tid, ts->status, ts->tsf, ts->tsf,
  4347. ts->buffer_timestamp, ts->buffer_timestamp,
  4348. delta_tsf, delta_tsf);
  4349. delay = 0;
  4350. goto end;
  4351. }
  4352. delay &= 0x1FFFFFFF; /* mask 29 BITS */
  4353. if (delay > 0x1000000) {
  4354. dp_info_rl("----------------------\n"
  4355. "Tx completion status:\n"
  4356. "----------------------\n"
  4357. "release_src = %d\n"
  4358. "ppdu_id = 0x%x\n"
  4359. "release_reason = %d\n"
  4360. "tsf = %u (0x%x)\n"
  4361. "buffer_timestamp = %u (0x%x)\n"
  4362. "delta_tsf = %u (0x%x)\n",
  4363. ts->release_src, ts->ppdu_id, ts->status,
  4364. ts->tsf, ts->tsf, ts->buffer_timestamp,
  4365. ts->buffer_timestamp, delta_tsf, delta_tsf);
  4366. return QDF_STATUS_E_FAILURE;
  4367. }
  4368. end:
  4369. *delay_us = delay;
  4370. return QDF_STATUS_SUCCESS;
  4371. }
  4372. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4373. uint32_t delta_tsf)
  4374. {
  4375. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4376. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4377. DP_MOD_ID_CDP);
  4378. if (!vdev) {
  4379. dp_err_rl("vdev %d does not exist", vdev_id);
  4380. return;
  4381. }
  4382. vdev->delta_tsf = delta_tsf;
  4383. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  4384. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4385. }
  4386. #endif
  4387. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  4388. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  4389. uint8_t vdev_id, bool enable)
  4390. {
  4391. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4392. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4393. DP_MOD_ID_CDP);
  4394. if (!vdev) {
  4395. dp_err_rl("vdev %d does not exist", vdev_id);
  4396. return QDF_STATUS_E_FAILURE;
  4397. }
  4398. qdf_atomic_set(&vdev->ul_delay_report, enable);
  4399. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4400. return QDF_STATUS_SUCCESS;
  4401. }
  4402. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4403. uint32_t *val)
  4404. {
  4405. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4406. struct dp_vdev *vdev;
  4407. uint32_t delay_accum;
  4408. uint32_t pkts_accum;
  4409. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  4410. if (!vdev) {
  4411. dp_err_rl("vdev %d does not exist", vdev_id);
  4412. return QDF_STATUS_E_FAILURE;
  4413. }
  4414. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  4415. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4416. return QDF_STATUS_E_FAILURE;
  4417. }
  4418. /* Average uplink delay based on current accumulated values */
  4419. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  4420. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  4421. *val = delay_accum / pkts_accum;
  4422. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  4423. delay_accum, pkts_accum);
  4424. /* Reset accumulated values to 0 */
  4425. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  4426. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  4427. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4428. return QDF_STATUS_SUCCESS;
  4429. }
  4430. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4431. struct hal_tx_completion_status *ts)
  4432. {
  4433. uint32_t ul_delay;
  4434. if (qdf_unlikely(!vdev)) {
  4435. dp_info_rl("vdev is null or delete in progress");
  4436. return;
  4437. }
  4438. if (!qdf_atomic_read(&vdev->ul_delay_report))
  4439. return;
  4440. if (QDF_IS_STATUS_ERROR(dp_tx_compute_hw_delay_us(ts,
  4441. vdev->delta_tsf,
  4442. &ul_delay)))
  4443. return;
  4444. ul_delay /= 1000; /* in unit of ms */
  4445. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  4446. qdf_atomic_inc(&vdev->ul_pkts_accum);
  4447. }
  4448. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  4449. static inline
  4450. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4451. struct hal_tx_completion_status *ts)
  4452. {
  4453. }
  4454. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  4455. /**
  4456. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  4457. * @soc: DP soc handle
  4458. * @tx_desc: software descriptor head pointer
  4459. * @ts: Tx completion status
  4460. * @txrx_peer: txrx peer handle
  4461. * @ring_id: ring number
  4462. *
  4463. * Return: none
  4464. */
  4465. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  4466. struct dp_tx_desc_s *tx_desc,
  4467. struct hal_tx_completion_status *ts,
  4468. struct dp_txrx_peer *txrx_peer,
  4469. uint8_t ring_id)
  4470. {
  4471. uint32_t length;
  4472. qdf_ether_header_t *eh;
  4473. struct dp_vdev *vdev = NULL;
  4474. qdf_nbuf_t nbuf = tx_desc->nbuf;
  4475. enum qdf_dp_tx_rx_status dp_status;
  4476. if (!nbuf) {
  4477. dp_info_rl("invalid tx descriptor. nbuf NULL");
  4478. goto out;
  4479. }
  4480. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  4481. length = qdf_nbuf_len(nbuf);
  4482. dp_status = dp_tx_hw_to_qdf(ts->status);
  4483. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  4484. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  4485. QDF_TRACE_DEFAULT_PDEV_ID,
  4486. qdf_nbuf_data_addr(nbuf),
  4487. sizeof(qdf_nbuf_data(nbuf)),
  4488. tx_desc->id, ts->status, dp_status));
  4489. dp_tx_comp_debug("-------------------- \n"
  4490. "Tx Completion Stats: \n"
  4491. "-------------------- \n"
  4492. "ack_frame_rssi = %d \n"
  4493. "first_msdu = %d \n"
  4494. "last_msdu = %d \n"
  4495. "msdu_part_of_amsdu = %d \n"
  4496. "rate_stats valid = %d \n"
  4497. "bw = %d \n"
  4498. "pkt_type = %d \n"
  4499. "stbc = %d \n"
  4500. "ldpc = %d \n"
  4501. "sgi = %d \n"
  4502. "mcs = %d \n"
  4503. "ofdma = %d \n"
  4504. "tones_in_ru = %d \n"
  4505. "tsf = %d \n"
  4506. "ppdu_id = %d \n"
  4507. "transmit_cnt = %d \n"
  4508. "tid = %d \n"
  4509. "peer_id = %d\n"
  4510. "tx_status = %d\n",
  4511. ts->ack_frame_rssi, ts->first_msdu,
  4512. ts->last_msdu, ts->msdu_part_of_amsdu,
  4513. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  4514. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  4515. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  4516. ts->transmit_cnt, ts->tid, ts->peer_id,
  4517. ts->status);
  4518. /* Update SoC level stats */
  4519. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  4520. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  4521. if (!txrx_peer) {
  4522. dp_info_rl("peer is null or deletion in progress");
  4523. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  4524. goto out;
  4525. }
  4526. vdev = txrx_peer->vdev;
  4527. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  4528. dp_tx_update_uplink_delay(soc, vdev, ts);
  4529. /* check tx complete notification */
  4530. if (qdf_nbuf_tx_notify_comp_get(nbuf))
  4531. dp_tx_notify_completion(soc, vdev, tx_desc,
  4532. nbuf, ts->status);
  4533. /* Update per-packet stats for mesh mode */
  4534. if (qdf_unlikely(vdev->mesh_vdev) &&
  4535. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  4536. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  4537. /* Update peer level stats */
  4538. if (qdf_unlikely(txrx_peer->bss_peer &&
  4539. vdev->opmode == wlan_op_mode_ap)) {
  4540. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  4541. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  4542. length);
  4543. if (txrx_peer->vdev->tx_encap_type ==
  4544. htt_cmn_pkt_type_ethernet &&
  4545. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  4546. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4547. tx.bcast, 1,
  4548. length);
  4549. }
  4550. }
  4551. } else {
  4552. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length);
  4553. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  4554. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  4555. 1, length);
  4556. if (qdf_unlikely(txrx_peer->in_twt)) {
  4557. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4558. tx.tx_success_twt,
  4559. 1, length);
  4560. }
  4561. }
  4562. }
  4563. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id);
  4564. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts, ring_id);
  4565. dp_tx_update_peer_jitter_stats(txrx_peer, tx_desc, ts, ring_id);
  4566. dp_tx_update_peer_sawf_stats(soc, vdev, txrx_peer, tx_desc,
  4567. ts, ts->tid);
  4568. dp_tx_send_pktlog(soc, vdev->pdev, tx_desc, nbuf, dp_status);
  4569. #ifdef QCA_SUPPORT_RDK_STATS
  4570. if (soc->peerstats_enabled)
  4571. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  4572. qdf_ktime_to_ms(tx_desc->timestamp),
  4573. ts->ppdu_id);
  4574. #endif
  4575. out:
  4576. return;
  4577. }
  4578. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  4579. defined(QCA_ENHANCED_STATS_SUPPORT)
  4580. /*
  4581. * dp_tx_update_peer_basic_stats(): Update peer basic stats
  4582. * @txrx_peer: Datapath txrx_peer handle
  4583. * @length: Length of the packet
  4584. * @tx_status: Tx status from TQM/FW
  4585. * @update: enhanced flag value present in dp_pdev
  4586. *
  4587. * Return: none
  4588. */
  4589. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4590. uint32_t length, uint8_t tx_status,
  4591. bool update)
  4592. {
  4593. if (update || (!txrx_peer->hw_txrx_stats_en)) {
  4594. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4595. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4596. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4597. }
  4598. }
  4599. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  4600. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4601. uint32_t length, uint8_t tx_status,
  4602. bool update)
  4603. {
  4604. if (!txrx_peer->hw_txrx_stats_en) {
  4605. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4606. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4607. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4608. }
  4609. }
  4610. #else
  4611. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4612. uint32_t length, uint8_t tx_status,
  4613. bool update)
  4614. {
  4615. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4616. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4617. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4618. }
  4619. #endif
  4620. /*
  4621. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4622. * @nbuf: skb buffer
  4623. *
  4624. * Return: none
  4625. */
  4626. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4627. static inline
  4628. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4629. {
  4630. qdf_nbuf_t nbuf = NULL;
  4631. if (next)
  4632. nbuf = next->nbuf;
  4633. if (nbuf) {
  4634. /* prefetch skb->next and first few bytes of skb->cb */
  4635. qdf_prefetch(next->shinfo_addr);
  4636. qdf_prefetch(nbuf);
  4637. /* prefetch skb fields present in different cachelines */
  4638. qdf_prefetch(&nbuf->len);
  4639. qdf_prefetch(&nbuf->users);
  4640. }
  4641. }
  4642. #else
  4643. static inline
  4644. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4645. {
  4646. }
  4647. #endif
  4648. /**
  4649. * dp_tx_mcast_reinject_handler() - Tx reinjected multicast packets handler
  4650. * @soc: core txrx main context
  4651. * @desc: software descriptor
  4652. *
  4653. * Return: true when packet is reinjected
  4654. */
  4655. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  4656. defined(WLAN_MCAST_MLO)
  4657. static inline bool
  4658. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4659. {
  4660. struct dp_vdev *vdev = NULL;
  4661. if (desc->tx_status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4662. if (!soc->arch_ops.dp_tx_mcast_handler)
  4663. return false;
  4664. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  4665. DP_MOD_ID_REINJECT);
  4666. if (qdf_unlikely(!vdev)) {
  4667. dp_tx_comp_info_rl("Unable to get vdev ref %d",
  4668. desc->id);
  4669. return false;
  4670. }
  4671. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  4672. qdf_nbuf_len(desc->nbuf));
  4673. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, desc->nbuf);
  4674. dp_tx_desc_release(desc, desc->pool_id);
  4675. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4676. return true;
  4677. }
  4678. return false;
  4679. }
  4680. #else
  4681. static inline bool
  4682. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4683. {
  4684. return false;
  4685. }
  4686. #endif
  4687. /**
  4688. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  4689. * @soc: core txrx main context
  4690. * @comp_head: software descriptor head pointer
  4691. * @ring_id: ring number
  4692. *
  4693. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  4694. * and release the software descriptors after processing is complete
  4695. *
  4696. * Return: none
  4697. */
  4698. static void
  4699. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4700. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4701. {
  4702. struct dp_tx_desc_s *desc;
  4703. struct dp_tx_desc_s *next;
  4704. struct hal_tx_completion_status ts;
  4705. struct dp_txrx_peer *txrx_peer = NULL;
  4706. uint16_t peer_id = DP_INVALID_PEER;
  4707. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4708. desc = comp_head;
  4709. while (desc) {
  4710. next = desc->next;
  4711. dp_tx_prefetch_next_nbuf_data(next);
  4712. if (peer_id != desc->peer_id) {
  4713. if (txrx_peer)
  4714. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4715. DP_MOD_ID_TX_COMP);
  4716. peer_id = desc->peer_id;
  4717. txrx_peer =
  4718. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4719. &txrx_ref_handle,
  4720. DP_MOD_ID_TX_COMP);
  4721. }
  4722. if (dp_tx_mcast_reinject_handler(soc, desc)) {
  4723. desc = next;
  4724. continue;
  4725. }
  4726. if (desc->flags & DP_TX_DESC_FLAG_PPEDS) {
  4727. if (qdf_likely(txrx_peer))
  4728. dp_tx_update_peer_basic_stats(txrx_peer,
  4729. desc->length,
  4730. desc->tx_status,
  4731. false);
  4732. qdf_nbuf_free(desc->nbuf);
  4733. dp_ppeds_tx_desc_free(soc, desc);
  4734. desc = next;
  4735. continue;
  4736. }
  4737. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4738. struct dp_pdev *pdev = desc->pdev;
  4739. if (qdf_likely(txrx_peer))
  4740. dp_tx_update_peer_basic_stats(txrx_peer,
  4741. desc->length,
  4742. desc->tx_status,
  4743. false);
  4744. qdf_assert(pdev);
  4745. dp_tx_outstanding_dec(pdev);
  4746. /*
  4747. * Calling a QDF WRAPPER here is creating significant
  4748. * performance impact so avoided the wrapper call here
  4749. */
  4750. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  4751. desc->id, DP_TX_COMP_UNMAP);
  4752. dp_tx_nbuf_unmap(soc, desc);
  4753. qdf_nbuf_free_simple(desc->nbuf);
  4754. dp_tx_desc_free(soc, desc, desc->pool_id);
  4755. desc = next;
  4756. continue;
  4757. }
  4758. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  4759. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  4760. ring_id);
  4761. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  4762. dp_tx_desc_release(desc, desc->pool_id);
  4763. desc = next;
  4764. }
  4765. if (txrx_peer)
  4766. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  4767. }
  4768. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  4769. static inline
  4770. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4771. int max_reap_limit)
  4772. {
  4773. bool limit_hit = false;
  4774. limit_hit =
  4775. (num_reaped >= max_reap_limit) ? true : false;
  4776. if (limit_hit)
  4777. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  4778. return limit_hit;
  4779. }
  4780. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4781. {
  4782. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  4783. }
  4784. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4785. {
  4786. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  4787. return cfg->tx_comp_loop_pkt_limit;
  4788. }
  4789. #else
  4790. static inline
  4791. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4792. int max_reap_limit)
  4793. {
  4794. return false;
  4795. }
  4796. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4797. {
  4798. return false;
  4799. }
  4800. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4801. {
  4802. return 0;
  4803. }
  4804. #endif
  4805. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  4806. static inline int
  4807. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4808. int *max_reap_limit)
  4809. {
  4810. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  4811. max_reap_limit);
  4812. }
  4813. #else
  4814. static inline int
  4815. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4816. int *max_reap_limit)
  4817. {
  4818. return 0;
  4819. }
  4820. #endif
  4821. #ifdef DP_TX_TRACKING
  4822. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  4823. {
  4824. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  4825. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  4826. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  4827. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  4828. }
  4829. }
  4830. #endif
  4831. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  4832. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  4833. uint32_t quota)
  4834. {
  4835. void *tx_comp_hal_desc;
  4836. void *last_prefetched_hw_desc = NULL;
  4837. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  4838. hal_soc_handle_t hal_soc;
  4839. uint8_t buffer_src;
  4840. struct dp_tx_desc_s *tx_desc = NULL;
  4841. struct dp_tx_desc_s *head_desc = NULL;
  4842. struct dp_tx_desc_s *tail_desc = NULL;
  4843. uint32_t num_processed = 0;
  4844. uint32_t count;
  4845. uint32_t num_avail_for_reap = 0;
  4846. bool force_break = false;
  4847. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  4848. int max_reap_limit, ring_near_full;
  4849. DP_HIST_INIT();
  4850. more_data:
  4851. hal_soc = soc->hal_soc;
  4852. /* Re-initialize local variables to be re-used */
  4853. head_desc = NULL;
  4854. tail_desc = NULL;
  4855. count = 0;
  4856. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  4857. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  4858. &max_reap_limit);
  4859. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  4860. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  4861. return 0;
  4862. }
  4863. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, 0);
  4864. if (num_avail_for_reap >= quota)
  4865. num_avail_for_reap = quota;
  4866. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  4867. last_prefetched_hw_desc = dp_srng_dst_prefetch_32_byte_desc(hal_soc,
  4868. hal_ring_hdl,
  4869. num_avail_for_reap);
  4870. /* Find head descriptor from completion ring */
  4871. while (qdf_likely(num_avail_for_reap--)) {
  4872. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  4873. if (qdf_unlikely(!tx_comp_hal_desc))
  4874. break;
  4875. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  4876. tx_comp_hal_desc);
  4877. /* If this buffer was not released by TQM or FW, then it is not
  4878. * Tx completion indication, assert */
  4879. if (qdf_unlikely(buffer_src !=
  4880. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  4881. (qdf_unlikely(buffer_src !=
  4882. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  4883. uint8_t wbm_internal_error;
  4884. dp_err_rl(
  4885. "Tx comp release_src != TQM | FW but from %d",
  4886. buffer_src);
  4887. hal_dump_comp_desc(tx_comp_hal_desc);
  4888. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  4889. /* When WBM sees NULL buffer_addr_info in any of
  4890. * ingress rings it sends an error indication,
  4891. * with wbm_internal_error=1, to a specific ring.
  4892. * The WBM2SW ring used to indicate these errors is
  4893. * fixed in HW, and that ring is being used as Tx
  4894. * completion ring. These errors are not related to
  4895. * Tx completions, and should just be ignored
  4896. */
  4897. wbm_internal_error = hal_get_wbm_internal_error(
  4898. hal_soc,
  4899. tx_comp_hal_desc);
  4900. if (wbm_internal_error) {
  4901. dp_err_rl("Tx comp wbm_internal_error!!");
  4902. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  4903. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  4904. buffer_src)
  4905. dp_handle_wbm_internal_error(
  4906. soc,
  4907. tx_comp_hal_desc,
  4908. hal_tx_comp_get_buffer_type(
  4909. tx_comp_hal_desc));
  4910. } else {
  4911. dp_err_rl("Tx comp wbm_internal_error false");
  4912. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  4913. }
  4914. continue;
  4915. }
  4916. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  4917. tx_comp_hal_desc,
  4918. &tx_desc);
  4919. if (!tx_desc) {
  4920. dp_err("unable to retrieve tx_desc!");
  4921. QDF_BUG(0);
  4922. continue;
  4923. }
  4924. tx_desc->buffer_src = buffer_src;
  4925. if (tx_desc->flags & DP_TX_DESC_FLAG_PPEDS)
  4926. goto add_to_pool2;
  4927. /*
  4928. * If the release source is FW, process the HTT status
  4929. */
  4930. if (qdf_unlikely(buffer_src ==
  4931. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  4932. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  4933. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  4934. htt_tx_status);
  4935. /* Collect hw completion contents */
  4936. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4937. &tx_desc->comp, 1);
  4938. soc->arch_ops.dp_tx_process_htt_completion(
  4939. soc,
  4940. tx_desc,
  4941. htt_tx_status,
  4942. ring_id);
  4943. } else {
  4944. tx_desc->tx_status =
  4945. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  4946. tx_desc->buffer_src = buffer_src;
  4947. /*
  4948. * If the fast completion mode is enabled extended
  4949. * metadata from descriptor is not copied
  4950. */
  4951. if (qdf_likely(tx_desc->flags &
  4952. DP_TX_DESC_FLAG_SIMPLE))
  4953. goto add_to_pool;
  4954. /*
  4955. * If the descriptor is already freed in vdev_detach,
  4956. * continue to next descriptor
  4957. */
  4958. if (qdf_unlikely
  4959. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4960. !tx_desc->flags)) {
  4961. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  4962. tx_desc->id);
  4963. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  4964. dp_tx_desc_check_corruption(tx_desc);
  4965. continue;
  4966. }
  4967. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4968. dp_tx_comp_info_rl("pdev in down state %d",
  4969. tx_desc->id);
  4970. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  4971. dp_tx_comp_free_buf(soc, tx_desc, false);
  4972. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4973. goto next_desc;
  4974. }
  4975. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4976. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4977. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  4978. tx_desc->flags, tx_desc->id);
  4979. qdf_assert_always(0);
  4980. }
  4981. /* Collect hw completion contents */
  4982. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4983. &tx_desc->comp, 1);
  4984. add_to_pool:
  4985. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4986. add_to_pool2:
  4987. /* First ring descriptor on the cycle */
  4988. if (!head_desc) {
  4989. head_desc = tx_desc;
  4990. tail_desc = tx_desc;
  4991. }
  4992. tail_desc->next = tx_desc;
  4993. tx_desc->next = NULL;
  4994. tail_desc = tx_desc;
  4995. }
  4996. next_desc:
  4997. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4998. /*
  4999. * Processed packet count is more than given quota
  5000. * stop to processing
  5001. */
  5002. count++;
  5003. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  5004. num_avail_for_reap,
  5005. hal_ring_hdl,
  5006. &last_prefetched_hw_desc,
  5007. &last_prefetched_sw_desc);
  5008. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  5009. break;
  5010. }
  5011. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  5012. /* Process the reaped descriptors */
  5013. if (head_desc)
  5014. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  5015. DP_STATS_INC(soc, tx.tx_comp[ring_id], count);
  5016. /*
  5017. * If we are processing in near-full condition, there are 3 scenario
  5018. * 1) Ring entries has reached critical state
  5019. * 2) Ring entries are still near high threshold
  5020. * 3) Ring entries are below the safe level
  5021. *
  5022. * One more loop will move the state to normal processing and yield
  5023. */
  5024. if (ring_near_full)
  5025. goto more_data;
  5026. if (dp_tx_comp_enable_eol_data_check(soc)) {
  5027. if (num_processed >= quota)
  5028. force_break = true;
  5029. if (!force_break &&
  5030. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  5031. hal_ring_hdl)) {
  5032. DP_STATS_INC(soc, tx.hp_oos2, 1);
  5033. if (!hif_exec_should_yield(soc->hif_handle,
  5034. int_ctx->dp_intr_id))
  5035. goto more_data;
  5036. }
  5037. }
  5038. DP_TX_HIST_STATS_PER_PDEV();
  5039. return num_processed;
  5040. }
  5041. #ifdef FEATURE_WLAN_TDLS
  5042. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  5043. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  5044. {
  5045. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  5046. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  5047. DP_MOD_ID_TDLS);
  5048. if (!vdev) {
  5049. dp_err("vdev handle for id %d is NULL", vdev_id);
  5050. return NULL;
  5051. }
  5052. if (tx_spec & OL_TX_SPEC_NO_FREE)
  5053. vdev->is_tdls_frame = true;
  5054. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  5055. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  5056. }
  5057. #endif
  5058. /**
  5059. * dp_tx_vdev_attach() - attach vdev to dp tx
  5060. * @vdev: virtual device instance
  5061. *
  5062. * Return: QDF_STATUS_SUCCESS: success
  5063. * QDF_STATUS_E_RESOURCES: Error return
  5064. */
  5065. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  5066. {
  5067. int pdev_id;
  5068. /*
  5069. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  5070. */
  5071. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  5072. DP_TCL_METADATA_TYPE_VDEV_BASED);
  5073. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  5074. vdev->vdev_id);
  5075. pdev_id =
  5076. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  5077. vdev->pdev->pdev_id);
  5078. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  5079. /*
  5080. * Set HTT Extension Valid bit to 0 by default
  5081. */
  5082. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  5083. dp_tx_vdev_update_search_flags(vdev);
  5084. return QDF_STATUS_SUCCESS;
  5085. }
  5086. #ifndef FEATURE_WDS
  5087. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  5088. {
  5089. return false;
  5090. }
  5091. #endif
  5092. /**
  5093. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  5094. * @vdev: virtual device instance
  5095. *
  5096. * Return: void
  5097. *
  5098. */
  5099. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  5100. {
  5101. struct dp_soc *soc = vdev->pdev->soc;
  5102. /*
  5103. * Enable both AddrY (SA based search) and AddrX (Da based search)
  5104. * for TDLS link
  5105. *
  5106. * Enable AddrY (SA based search) only for non-WDS STA and
  5107. * ProxySTA VAP (in HKv1) modes.
  5108. *
  5109. * In all other VAP modes, only DA based search should be
  5110. * enabled
  5111. */
  5112. if (vdev->opmode == wlan_op_mode_sta &&
  5113. vdev->tdls_link_connected)
  5114. vdev->hal_desc_addr_search_flags =
  5115. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  5116. else if ((vdev->opmode == wlan_op_mode_sta) &&
  5117. !dp_tx_da_search_override(vdev))
  5118. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  5119. else
  5120. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  5121. if (vdev->opmode == wlan_op_mode_sta && !vdev->tdls_link_connected)
  5122. vdev->search_type = soc->sta_mode_search_policy;
  5123. else
  5124. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  5125. }
  5126. static inline bool
  5127. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  5128. struct dp_vdev *vdev,
  5129. struct dp_tx_desc_s *tx_desc)
  5130. {
  5131. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  5132. return false;
  5133. /*
  5134. * if vdev is given, then only check whether desc
  5135. * vdev match. if vdev is NULL, then check whether
  5136. * desc pdev match.
  5137. */
  5138. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  5139. (tx_desc->pdev == pdev);
  5140. }
  5141. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5142. /**
  5143. * dp_tx_desc_flush() - release resources associated
  5144. * to TX Desc
  5145. *
  5146. * @dp_pdev: Handle to DP pdev structure
  5147. * @vdev: virtual device instance
  5148. * NULL: no specific Vdev is required and check all allcated TX desc
  5149. * on this pdev.
  5150. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  5151. *
  5152. * @force_free:
  5153. * true: flush the TX desc.
  5154. * false: only reset the Vdev in each allocated TX desc
  5155. * that associated to current Vdev.
  5156. *
  5157. * This function will go through the TX desc pool to flush
  5158. * the outstanding TX data or reset Vdev to NULL in associated TX
  5159. * Desc.
  5160. */
  5161. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5162. bool force_free)
  5163. {
  5164. uint8_t i;
  5165. uint32_t j;
  5166. uint32_t num_desc, page_id, offset;
  5167. uint16_t num_desc_per_page;
  5168. struct dp_soc *soc = pdev->soc;
  5169. struct dp_tx_desc_s *tx_desc = NULL;
  5170. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5171. if (!vdev && !force_free) {
  5172. dp_err("Reset TX desc vdev, Vdev param is required!");
  5173. return;
  5174. }
  5175. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  5176. tx_desc_pool = &soc->tx_desc[i];
  5177. if (!(tx_desc_pool->pool_size) ||
  5178. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  5179. !(tx_desc_pool->desc_pages.cacheable_pages))
  5180. continue;
  5181. /*
  5182. * Add flow pool lock protection in case pool is freed
  5183. * due to all tx_desc is recycled when handle TX completion.
  5184. * this is not necessary when do force flush as:
  5185. * a. double lock will happen if dp_tx_desc_release is
  5186. * also trying to acquire it.
  5187. * b. dp interrupt has been disabled before do force TX desc
  5188. * flush in dp_pdev_deinit().
  5189. */
  5190. if (!force_free)
  5191. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  5192. num_desc = tx_desc_pool->pool_size;
  5193. num_desc_per_page =
  5194. tx_desc_pool->desc_pages.num_element_per_page;
  5195. for (j = 0; j < num_desc; j++) {
  5196. page_id = j / num_desc_per_page;
  5197. offset = j % num_desc_per_page;
  5198. if (qdf_unlikely(!(tx_desc_pool->
  5199. desc_pages.cacheable_pages)))
  5200. break;
  5201. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5202. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5203. /*
  5204. * Free TX desc if force free is
  5205. * required, otherwise only reset vdev
  5206. * in this TX desc.
  5207. */
  5208. if (force_free) {
  5209. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5210. dp_tx_comp_free_buf(soc, tx_desc,
  5211. false);
  5212. dp_tx_desc_release(tx_desc, i);
  5213. } else {
  5214. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5215. }
  5216. }
  5217. }
  5218. if (!force_free)
  5219. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  5220. }
  5221. }
  5222. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5223. /**
  5224. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  5225. *
  5226. * @soc: Handle to DP soc structure
  5227. * @tx_desc: pointer of one TX desc
  5228. * @desc_pool_id: TX Desc pool id
  5229. */
  5230. static inline void
  5231. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  5232. uint8_t desc_pool_id)
  5233. {
  5234. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  5235. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5236. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  5237. }
  5238. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5239. bool force_free)
  5240. {
  5241. uint8_t i, num_pool;
  5242. uint32_t j;
  5243. uint32_t num_desc, page_id, offset;
  5244. uint16_t num_desc_per_page;
  5245. struct dp_soc *soc = pdev->soc;
  5246. struct dp_tx_desc_s *tx_desc = NULL;
  5247. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5248. if (!vdev && !force_free) {
  5249. dp_err("Reset TX desc vdev, Vdev param is required!");
  5250. return;
  5251. }
  5252. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5253. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5254. for (i = 0; i < num_pool; i++) {
  5255. tx_desc_pool = &soc->tx_desc[i];
  5256. if (!tx_desc_pool->desc_pages.cacheable_pages)
  5257. continue;
  5258. num_desc_per_page =
  5259. tx_desc_pool->desc_pages.num_element_per_page;
  5260. for (j = 0; j < num_desc; j++) {
  5261. page_id = j / num_desc_per_page;
  5262. offset = j % num_desc_per_page;
  5263. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5264. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5265. if (force_free) {
  5266. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5267. dp_tx_comp_free_buf(soc, tx_desc,
  5268. false);
  5269. dp_tx_desc_release(tx_desc, i);
  5270. } else {
  5271. dp_tx_desc_reset_vdev(soc, tx_desc,
  5272. i);
  5273. }
  5274. }
  5275. }
  5276. }
  5277. }
  5278. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5279. /**
  5280. * dp_tx_vdev_detach() - detach vdev from dp tx
  5281. * @vdev: virtual device instance
  5282. *
  5283. * Return: QDF_STATUS_SUCCESS: success
  5284. * QDF_STATUS_E_RESOURCES: Error return
  5285. */
  5286. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  5287. {
  5288. struct dp_pdev *pdev = vdev->pdev;
  5289. /* Reset TX desc associated to this Vdev as NULL */
  5290. dp_tx_desc_flush(pdev, vdev, false);
  5291. return QDF_STATUS_SUCCESS;
  5292. }
  5293. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5294. /* Pools will be allocated dynamically */
  5295. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5296. int num_desc)
  5297. {
  5298. uint8_t i;
  5299. for (i = 0; i < num_pool; i++) {
  5300. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  5301. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  5302. }
  5303. return QDF_STATUS_SUCCESS;
  5304. }
  5305. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5306. uint32_t num_desc)
  5307. {
  5308. return QDF_STATUS_SUCCESS;
  5309. }
  5310. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5311. {
  5312. }
  5313. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5314. {
  5315. uint8_t i;
  5316. for (i = 0; i < num_pool; i++)
  5317. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  5318. }
  5319. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5320. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5321. uint32_t num_desc)
  5322. {
  5323. uint8_t i, count;
  5324. /* Allocate software Tx descriptor pools */
  5325. for (i = 0; i < num_pool; i++) {
  5326. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  5327. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5328. FL("Tx Desc Pool alloc %d failed %pK"),
  5329. i, soc);
  5330. goto fail;
  5331. }
  5332. }
  5333. return QDF_STATUS_SUCCESS;
  5334. fail:
  5335. for (count = 0; count < i; count++)
  5336. dp_tx_desc_pool_free(soc, count);
  5337. return QDF_STATUS_E_NOMEM;
  5338. }
  5339. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5340. uint32_t num_desc)
  5341. {
  5342. uint8_t i;
  5343. for (i = 0; i < num_pool; i++) {
  5344. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  5345. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5346. FL("Tx Desc Pool init %d failed %pK"),
  5347. i, soc);
  5348. return QDF_STATUS_E_NOMEM;
  5349. }
  5350. }
  5351. return QDF_STATUS_SUCCESS;
  5352. }
  5353. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5354. {
  5355. uint8_t i;
  5356. for (i = 0; i < num_pool; i++)
  5357. dp_tx_desc_pool_deinit(soc, i);
  5358. }
  5359. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5360. {
  5361. uint8_t i;
  5362. for (i = 0; i < num_pool; i++)
  5363. dp_tx_desc_pool_free(soc, i);
  5364. }
  5365. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5366. /**
  5367. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  5368. * @soc: core txrx main context
  5369. * @num_pool: number of pools
  5370. *
  5371. */
  5372. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  5373. {
  5374. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  5375. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  5376. }
  5377. /**
  5378. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  5379. * @soc: core txrx main context
  5380. * @num_pool: number of pools
  5381. *
  5382. */
  5383. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  5384. {
  5385. dp_tx_tso_desc_pool_free(soc, num_pool);
  5386. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  5387. }
  5388. /**
  5389. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  5390. * @soc: core txrx main context
  5391. *
  5392. * This function frees all tx related descriptors as below
  5393. * 1. Regular TX descriptors (static pools)
  5394. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5395. * 3. TSO descriptors
  5396. *
  5397. */
  5398. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  5399. {
  5400. uint8_t num_pool;
  5401. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5402. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5403. dp_tx_ext_desc_pool_free(soc, num_pool);
  5404. dp_tx_delete_static_pools(soc, num_pool);
  5405. }
  5406. /**
  5407. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  5408. * @soc: core txrx main context
  5409. *
  5410. * This function de-initializes all tx related descriptors as below
  5411. * 1. Regular TX descriptors (static pools)
  5412. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5413. * 3. TSO descriptors
  5414. *
  5415. */
  5416. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  5417. {
  5418. uint8_t num_pool;
  5419. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5420. dp_tx_flow_control_deinit(soc);
  5421. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5422. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5423. dp_tx_deinit_static_pools(soc, num_pool);
  5424. }
  5425. /**
  5426. * dp_tso_attach() - TSO attach handler
  5427. * @txrx_soc: Opaque Dp handle
  5428. *
  5429. * Reserve TSO descriptor buffers
  5430. *
  5431. * Return: QDF_STATUS_E_FAILURE on failure or
  5432. * QDF_STATUS_SUCCESS on success
  5433. */
  5434. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  5435. uint8_t num_pool,
  5436. uint32_t num_desc)
  5437. {
  5438. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  5439. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5440. return QDF_STATUS_E_FAILURE;
  5441. }
  5442. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  5443. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5444. num_pool, soc);
  5445. return QDF_STATUS_E_FAILURE;
  5446. }
  5447. return QDF_STATUS_SUCCESS;
  5448. }
  5449. /**
  5450. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  5451. * @soc: DP soc handle
  5452. * @num_pool: Number of pools
  5453. * @num_desc: Number of descriptors
  5454. *
  5455. * Initialize TSO descriptor pools
  5456. *
  5457. * Return: QDF_STATUS_E_FAILURE on failure or
  5458. * QDF_STATUS_SUCCESS on success
  5459. */
  5460. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  5461. uint8_t num_pool,
  5462. uint32_t num_desc)
  5463. {
  5464. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  5465. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5466. return QDF_STATUS_E_FAILURE;
  5467. }
  5468. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  5469. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5470. num_pool, soc);
  5471. return QDF_STATUS_E_FAILURE;
  5472. }
  5473. return QDF_STATUS_SUCCESS;
  5474. }
  5475. /**
  5476. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  5477. * @soc: core txrx main context
  5478. *
  5479. * This function allocates memory for following descriptor pools
  5480. * 1. regular sw tx descriptor pools (static pools)
  5481. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5482. * 3. TSO descriptor pools
  5483. *
  5484. * Return: QDF_STATUS_SUCCESS: success
  5485. * QDF_STATUS_E_RESOURCES: Error return
  5486. */
  5487. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  5488. {
  5489. uint8_t num_pool;
  5490. uint32_t num_desc;
  5491. uint32_t num_ext_desc;
  5492. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5493. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5494. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5495. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5496. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  5497. __func__, num_pool, num_desc);
  5498. if ((num_pool > MAX_TXDESC_POOLS) ||
  5499. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  5500. goto fail1;
  5501. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  5502. goto fail1;
  5503. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5504. goto fail2;
  5505. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5506. return QDF_STATUS_SUCCESS;
  5507. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5508. goto fail3;
  5509. return QDF_STATUS_SUCCESS;
  5510. fail3:
  5511. dp_tx_ext_desc_pool_free(soc, num_pool);
  5512. fail2:
  5513. dp_tx_delete_static_pools(soc, num_pool);
  5514. fail1:
  5515. return QDF_STATUS_E_RESOURCES;
  5516. }
  5517. /**
  5518. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  5519. * @soc: core txrx main context
  5520. *
  5521. * This function initializes the following TX descriptor pools
  5522. * 1. regular sw tx descriptor pools (static pools)
  5523. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5524. * 3. TSO descriptor pools
  5525. *
  5526. * Return: QDF_STATUS_SUCCESS: success
  5527. * QDF_STATUS_E_RESOURCES: Error return
  5528. */
  5529. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  5530. {
  5531. uint8_t num_pool;
  5532. uint32_t num_desc;
  5533. uint32_t num_ext_desc;
  5534. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5535. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5536. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5537. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  5538. goto fail1;
  5539. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  5540. goto fail2;
  5541. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5542. return QDF_STATUS_SUCCESS;
  5543. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5544. goto fail3;
  5545. dp_tx_flow_control_init(soc);
  5546. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5547. return QDF_STATUS_SUCCESS;
  5548. fail3:
  5549. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5550. fail2:
  5551. dp_tx_deinit_static_pools(soc, num_pool);
  5552. fail1:
  5553. return QDF_STATUS_E_RESOURCES;
  5554. }
  5555. /**
  5556. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  5557. * @txrx_soc: dp soc handle
  5558. *
  5559. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5560. * QDF_STATUS_E_FAILURE
  5561. */
  5562. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  5563. {
  5564. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5565. uint8_t num_pool;
  5566. uint32_t num_desc;
  5567. uint32_t num_ext_desc;
  5568. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5569. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5570. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5571. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5572. return QDF_STATUS_E_FAILURE;
  5573. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5574. return QDF_STATUS_E_FAILURE;
  5575. return QDF_STATUS_SUCCESS;
  5576. }
  5577. /**
  5578. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  5579. * @txrx_soc: dp soc handle
  5580. *
  5581. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5582. */
  5583. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  5584. {
  5585. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5586. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5587. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5588. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5589. return QDF_STATUS_SUCCESS;
  5590. }
  5591. #ifdef CONFIG_DP_PKT_ADD_TIMESTAMP
  5592. void dp_pkt_add_timestamp(struct dp_vdev *vdev,
  5593. enum qdf_pkt_timestamp_index index, uint64_t time,
  5594. qdf_nbuf_t nbuf)
  5595. {
  5596. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled())) {
  5597. uint64_t tsf_time;
  5598. if (vdev->get_tsf_time) {
  5599. vdev->get_tsf_time(vdev->osif_vdev, time, &tsf_time);
  5600. qdf_add_dp_pkt_timestamp(nbuf, index, tsf_time);
  5601. }
  5602. }
  5603. }
  5604. void dp_pkt_get_timestamp(uint64_t *time)
  5605. {
  5606. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled()))
  5607. *time = qdf_get_log_timestamp();
  5608. }
  5609. #endif