dp_rh.c 27 KB

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  1. /*
  2. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "dp_types.h"
  19. #include <dp_internal.h>
  20. #include <dp_htt.h>
  21. #include "dp_rh.h"
  22. #include "dp_rh_tx.h"
  23. #include "dp_rh_htt.h"
  24. #include "dp_tx_desc.h"
  25. #include "dp_rh_rx.h"
  26. #include "dp_peer.h"
  27. #include <wlan_utility.h>
  28. #include <dp_rings.h>
  29. #include <ce_api.h>
  30. #include <ce_internal.h>
  31. static QDF_STATUS
  32. dp_srng_init_rh(struct dp_soc *soc, struct dp_srng *srng, int ring_type,
  33. int ring_num, int mac_id)
  34. {
  35. hal_soc_handle_t hal_soc = soc->hal_soc;
  36. struct hal_srng_params ring_params;
  37. if (srng->hal_srng) {
  38. dp_init_err("%pK: Ring type: %d, num:%d is already initialized",
  39. soc, ring_type, ring_num);
  40. return QDF_STATUS_SUCCESS;
  41. }
  42. /* memset the srng ring to zero */
  43. qdf_mem_zero(srng->base_vaddr_unaligned, srng->alloc_size);
  44. qdf_mem_zero(&ring_params, sizeof(struct hal_srng_params));
  45. ring_params.ring_base_paddr = srng->base_paddr_aligned;
  46. ring_params.ring_base_vaddr = srng->base_vaddr_aligned;
  47. ring_params.num_entries = srng->num_entries;
  48. dp_info("Ring type: %d, num:%d vaddr %pK paddr %pK entries %u",
  49. ring_type, ring_num,
  50. (void *)ring_params.ring_base_vaddr,
  51. (void *)ring_params.ring_base_paddr,
  52. ring_params.num_entries);
  53. if (soc->cdp_soc.ol_ops->get_con_mode &&
  54. soc->cdp_soc.ol_ops->get_con_mode() ==
  55. QDF_GLOBAL_MONITOR_MODE) {
  56. if (soc->intr_mode == DP_INTR_MSI &&
  57. !dp_skip_msi_cfg(soc, ring_type)) {
  58. dp_srng_msi_setup(soc, srng, &ring_params,
  59. ring_type, ring_num);
  60. dp_verbose_debug("Using MSI for ring_type: %d, ring_num %d",
  61. ring_type, ring_num);
  62. } else {
  63. ring_params.msi_data = 0;
  64. ring_params.msi_addr = 0;
  65. dp_srng_set_msi2_ring_params(soc, &ring_params, 0, 0);
  66. dp_verbose_debug("Skipping MSI for ring_type: %d, ring_num %d",
  67. ring_type, ring_num);
  68. }
  69. dp_srng_configure_interrupt_thresholds(soc, &ring_params,
  70. ring_type, ring_num,
  71. srng->num_entries);
  72. }
  73. srng->hal_srng = hal_srng_setup(hal_soc, ring_type, ring_num,
  74. mac_id, &ring_params, 0);
  75. if (!srng->hal_srng) {
  76. dp_srng_free(soc, srng);
  77. return QDF_STATUS_E_FAILURE;
  78. }
  79. return QDF_STATUS_SUCCESS;
  80. }
  81. static QDF_STATUS
  82. dp_peer_setup_rh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  83. uint8_t *peer_mac,
  84. struct cdp_peer_setup_info *setup_info)
  85. {
  86. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  87. struct dp_pdev *pdev;
  88. QDF_STATUS status = QDF_STATUS_SUCCESS;
  89. struct dp_vdev *vdev = NULL;
  90. struct dp_peer *peer =
  91. dp_peer_find_hash_find(soc, peer_mac, 0, vdev_id,
  92. DP_MOD_ID_CDP);
  93. enum wlan_op_mode vdev_opmode;
  94. if (!peer)
  95. return QDF_STATUS_E_FAILURE;
  96. vdev = peer->vdev;
  97. if (!vdev) {
  98. status = QDF_STATUS_E_FAILURE;
  99. goto fail;
  100. }
  101. /* save vdev related member in case vdev freed */
  102. vdev_opmode = vdev->opmode;
  103. pdev = vdev->pdev;
  104. dp_info("pdev: %d vdev :%d opmode:%u",
  105. pdev->pdev_id, vdev->vdev_id, vdev->opmode);
  106. /*
  107. * There are corner cases where the AD1 = AD2 = "VAPs address"
  108. * i.e both the devices have same MAC address. In these
  109. * cases we want such pkts to be processed in NULL Q handler
  110. * which is REO2TCL ring. for this reason we should
  111. * not setup reo_queues and default route for bss_peer.
  112. */
  113. dp_monitor_peer_tx_init(pdev, peer);
  114. if (!setup_info)
  115. if (dp_peer_legacy_setup(soc, peer) !=
  116. QDF_STATUS_SUCCESS) {
  117. status = QDF_STATUS_E_RESOURCES;
  118. goto fail;
  119. }
  120. if (peer->bss_peer && vdev->opmode == wlan_op_mode_ap) {
  121. status = QDF_STATUS_E_FAILURE;
  122. goto fail;
  123. }
  124. if (vdev_opmode != wlan_op_mode_monitor)
  125. dp_peer_rx_init(pdev, peer);
  126. dp_peer_ppdu_delayed_ba_init(peer);
  127. fail:
  128. dp_peer_unref_delete(peer, DP_MOD_ID_CDP);
  129. return status;
  130. }
  131. #ifdef AST_OFFLOAD_ENABLE
  132. static void dp_peer_map_detach_rh(struct dp_soc *soc)
  133. {
  134. dp_soc_wds_detach(soc);
  135. dp_peer_ast_table_detach(soc);
  136. dp_peer_ast_hash_detach(soc);
  137. dp_peer_mec_hash_detach(soc);
  138. }
  139. static QDF_STATUS dp_peer_map_attach_rh(struct dp_soc *soc)
  140. {
  141. QDF_STATUS status;
  142. soc->max_peer_id = soc->max_peers;
  143. status = dp_peer_ast_table_attach(soc);
  144. if (!QDF_IS_STATUS_SUCCESS(status))
  145. return status;
  146. status = dp_peer_ast_hash_attach(soc);
  147. if (!QDF_IS_STATUS_SUCCESS(status))
  148. goto ast_table_detach;
  149. status = dp_peer_mec_hash_attach(soc);
  150. if (!QDF_IS_STATUS_SUCCESS(status))
  151. goto hash_detach;
  152. dp_soc_wds_attach(soc);
  153. return QDF_STATUS_SUCCESS;
  154. hash_detach:
  155. dp_peer_ast_hash_detach(soc);
  156. ast_table_detach:
  157. dp_peer_ast_table_detach(soc);
  158. return status;
  159. }
  160. #else
  161. static void dp_peer_map_detach_rh(struct dp_soc *soc)
  162. {
  163. }
  164. static QDF_STATUS dp_peer_map_attach_rh(struct dp_soc *soc)
  165. {
  166. soc->max_peer_id = soc->max_peers;
  167. return QDF_STATUS_SUCCESS;
  168. }
  169. #endif
  170. /**
  171. * dp_soc_cfg_init_rh() - initialize target specific configuration
  172. * during dp_soc_init
  173. * @soc: dp soc handle
  174. */
  175. static void dp_soc_cfg_init_rh(struct dp_soc *soc)
  176. {
  177. uint32_t target_type;
  178. target_type = hal_get_target_type(soc->hal_soc);
  179. switch (target_type) {
  180. case TARGET_TYPE_WCN6450:
  181. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, true);
  182. soc->ast_override_support = 1;
  183. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  184. break;
  185. default:
  186. qdf_print("%s: Unknown tgt type %d\n", __func__, target_type);
  187. qdf_assert_always(0);
  188. break;
  189. }
  190. }
  191. static void dp_soc_cfg_attach_rh(struct dp_soc *soc)
  192. {
  193. int target_type;
  194. target_type = hal_get_target_type(soc->hal_soc);
  195. switch (target_type) {
  196. case TARGET_TYPE_WCN6450:
  197. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  198. break;
  199. default:
  200. qdf_print("%s: Unknown tgt type %d\n", __func__, target_type);
  201. qdf_assert_always(0);
  202. break;
  203. }
  204. /*
  205. * keeping TCL and completion rings number, this data
  206. * is equivalent number of TX interface rings.
  207. */
  208. soc->num_tx_comp_rings =
  209. wlan_cfg_num_tx_comp_rings(soc->wlan_cfg_ctx);
  210. soc->num_tcl_data_rings =
  211. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  212. }
  213. qdf_size_t dp_get_context_size_rh(enum dp_context_type context_type)
  214. {
  215. switch (context_type) {
  216. case DP_CONTEXT_TYPE_SOC:
  217. return sizeof(struct dp_soc_rh);
  218. case DP_CONTEXT_TYPE_PDEV:
  219. return sizeof(struct dp_pdev_rh);
  220. case DP_CONTEXT_TYPE_VDEV:
  221. return sizeof(struct dp_vdev_rh);
  222. case DP_CONTEXT_TYPE_PEER:
  223. return sizeof(struct dp_peer_rh);
  224. default:
  225. return 0;
  226. }
  227. }
  228. qdf_size_t dp_mon_get_context_size_rh(enum dp_context_type context_type)
  229. {
  230. switch (context_type) {
  231. case DP_CONTEXT_TYPE_MON_PDEV:
  232. return sizeof(struct dp_mon_pdev_rh);
  233. case DP_CONTEXT_TYPE_MON_SOC:
  234. return sizeof(struct dp_mon_soc_rh);
  235. default:
  236. return 0;
  237. }
  238. }
  239. static QDF_STATUS dp_soc_attach_rh(struct dp_soc *soc,
  240. struct cdp_soc_attach_params *params)
  241. {
  242. soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
  243. return QDF_STATUS_SUCCESS;
  244. }
  245. static QDF_STATUS dp_soc_detach_rh(struct dp_soc *soc)
  246. {
  247. return QDF_STATUS_SUCCESS;
  248. }
  249. static QDF_STATUS dp_soc_deinit_rh(struct dp_soc *soc)
  250. {
  251. struct htt_soc *htt_soc = soc->htt_handle;
  252. qdf_atomic_set(&soc->cmn_init_done, 0);
  253. /*Degister RX offload flush handlers*/
  254. hif_offld_flush_cb_deregister(soc->hif_handle);
  255. dp_monitor_soc_deinit(soc);
  256. /* free peer tables & AST tables allocated during peer_map_attach */
  257. if (soc->peer_map_attach_success) {
  258. dp_peer_find_detach(soc);
  259. dp_peer_map_detach_rh(soc);
  260. soc->peer_map_attach_success = FALSE;
  261. }
  262. qdf_flush_work(&soc->htt_stats.work);
  263. qdf_disable_work(&soc->htt_stats.work);
  264. qdf_spinlock_destroy(&soc->htt_stats.lock);
  265. qdf_spinlock_destroy(&soc->ast_lock);
  266. dp_peer_mec_spinlock_destroy(soc);
  267. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  268. qdf_nbuf_queue_free(&soc->invalid_buf_queue);
  269. qdf_spinlock_destroy(&soc->rx.defrag.defrag_lock);
  270. qdf_spinlock_destroy(&soc->vdev_map_lock);
  271. dp_soc_tx_desc_sw_pools_deinit(soc);
  272. dp_soc_srng_deinit(soc);
  273. dp_hw_link_desc_ring_deinit(soc);
  274. dp_soc_print_inactive_objects(soc);
  275. qdf_spinlock_destroy(&soc->inactive_peer_list_lock);
  276. qdf_spinlock_destroy(&soc->inactive_vdev_list_lock);
  277. htt_soc_htc_dealloc(soc->htt_handle);
  278. htt_soc_detach(htt_soc);
  279. wlan_minidump_remove(soc, sizeof(*soc), soc->ctrl_psoc,
  280. WLAN_MD_DP_SOC, "dp_soc");
  281. return QDF_STATUS_SUCCESS;
  282. }
  283. static void *dp_soc_init_rh(struct dp_soc *soc, HTC_HANDLE htc_handle,
  284. struct hif_opaque_softc *hif_handle)
  285. {
  286. struct htt_soc *htt_soc = (struct htt_soc *)soc->htt_handle;
  287. bool is_monitor_mode = false;
  288. uint8_t i;
  289. wlan_minidump_log(soc, sizeof(*soc), soc->ctrl_psoc,
  290. WLAN_MD_DP_SOC, "dp_soc");
  291. soc->hif_handle = hif_handle;
  292. soc->hal_soc = hif_get_hal_handle(soc->hif_handle);
  293. if (!soc->hal_soc)
  294. goto fail1;
  295. htt_soc = htt_soc_attach(soc, htc_handle);
  296. if (!htt_soc)
  297. goto fail1;
  298. soc->htt_handle = htt_soc;
  299. if (htt_soc_htc_prealloc(htt_soc) != QDF_STATUS_SUCCESS)
  300. goto fail2;
  301. htt_set_htc_handle(htt_soc, htc_handle);
  302. dp_soc_cfg_init_rh(soc);
  303. dp_monitor_soc_cfg_init(soc);
  304. /* Note: Any SRNG ring initialization should happen only after
  305. * Interrupt mode is set and followed by filling up the
  306. * interrupt mask. IT SHOULD ALWAYS BE IN THIS ORDER.
  307. */
  308. dp_soc_set_interrupt_mode(soc);
  309. if (soc->cdp_soc.ol_ops->get_con_mode &&
  310. soc->cdp_soc.ol_ops->get_con_mode() ==
  311. QDF_GLOBAL_MONITOR_MODE)
  312. is_monitor_mode = true;
  313. if (is_monitor_mode)
  314. wlan_cfg_fill_interrupt_mask(soc->wlan_cfg_ctx, 0,
  315. soc->intr_mode, is_monitor_mode,
  316. false, soc->umac_reset_supported);
  317. if (dp_soc_srng_init(soc)) {
  318. dp_init_err("%pK: dp_soc_srng_init failed", soc);
  319. goto fail3;
  320. }
  321. if (dp_htt_soc_initialize_rh(soc->htt_handle, soc->ctrl_psoc,
  322. htt_get_htc_handle(htt_soc),
  323. soc->hal_soc, soc->osdev) == NULL)
  324. goto fail4;
  325. /* Initialize descriptors in TCL Rings */
  326. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  327. hal_tx_init_data_ring(soc->hal_soc,
  328. soc->tcl_data_ring[i].hal_srng);
  329. }
  330. if (dp_soc_tx_desc_sw_pools_init(soc)) {
  331. dp_init_err("%pK: dp_tx_soc_attach failed", soc);
  332. goto fail5;
  333. }
  334. wlan_cfg_set_rx_hash(soc->wlan_cfg_ctx,
  335. cfg_get(soc->ctrl_psoc, CFG_DP_RX_HASH));
  336. soc->cce_disable = false;
  337. soc->max_ast_ageout_count = MAX_AST_AGEOUT_COUNT;
  338. soc->sta_mode_search_policy = DP_TX_ADDR_SEARCH_ADDR_POLICY;
  339. qdf_mem_zero(&soc->vdev_id_map, sizeof(soc->vdev_id_map));
  340. qdf_spinlock_create(&soc->vdev_map_lock);
  341. qdf_atomic_init(&soc->num_tx_outstanding);
  342. qdf_atomic_init(&soc->num_tx_exception);
  343. soc->num_tx_allowed =
  344. wlan_cfg_get_dp_soc_tx_device_limit(soc->wlan_cfg_ctx);
  345. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  346. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc->ctrl_psoc,
  347. CDP_CFG_MAX_PEER_ID);
  348. if (ret != -EINVAL)
  349. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  350. ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc->ctrl_psoc,
  351. CDP_CFG_CCE_DISABLE);
  352. if (ret == 1)
  353. soc->cce_disable = true;
  354. }
  355. /* setup the global rx defrag waitlist */
  356. TAILQ_INIT(&soc->rx.defrag.waitlist);
  357. soc->rx.defrag.timeout_ms =
  358. wlan_cfg_get_rx_defrag_min_timeout(soc->wlan_cfg_ctx);
  359. soc->rx.defrag.next_flush_ms = 0;
  360. soc->rx.flags.defrag_timeout_check =
  361. wlan_cfg_get_defrag_timeout_check(soc->wlan_cfg_ctx);
  362. qdf_spinlock_create(&soc->rx.defrag.defrag_lock);
  363. dp_monitor_soc_init(soc);
  364. qdf_atomic_set(&soc->cmn_init_done, 1);
  365. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  366. qdf_spinlock_create(&soc->ast_lock);
  367. dp_peer_mec_spinlock_create(soc);
  368. qdf_nbuf_queue_init(&soc->invalid_buf_queue);
  369. TAILQ_INIT(&soc->inactive_peer_list);
  370. qdf_spinlock_create(&soc->inactive_peer_list_lock);
  371. TAILQ_INIT(&soc->inactive_vdev_list);
  372. qdf_spinlock_create(&soc->inactive_vdev_list_lock);
  373. qdf_spinlock_create(&soc->htt_stats.lock);
  374. /* initialize work queue for stats processing */
  375. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  376. /*Register RX offload flush handlers*/
  377. hif_offld_flush_cb_register(soc->hif_handle, dp_rx_data_flush);
  378. dp_info("Mem stats: DMA = %u HEAP = %u SKB = %u",
  379. qdf_dma_mem_stats_read(),
  380. qdf_heap_mem_stats_read(),
  381. qdf_skb_total_mem_stats_read());
  382. soc->vdev_stats_id_map = 0;
  383. return soc;
  384. fail5:
  385. htt_soc_htc_dealloc(soc->htt_handle);
  386. fail4:
  387. dp_soc_srng_deinit(soc);
  388. fail3:
  389. htt_htc_pkt_pool_free(htt_soc);
  390. fail2:
  391. htt_soc_detach(htt_soc);
  392. fail1:
  393. return NULL;
  394. }
  395. static void dp_soc_interrupt_detach_rh(struct cdp_soc_t *txrx_soc)
  396. {
  397. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  398. int i;
  399. if (soc->intr_mode == DP_INTR_POLL) {
  400. qdf_timer_free(&soc->int_timer);
  401. } else {
  402. hif_deconfigure_ext_group_interrupts(soc->hif_handle);
  403. hif_deregister_exec_group(soc->hif_handle, "dp_intr");
  404. }
  405. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  406. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  407. soc->intr_ctx[i].rxdma2host_ring_mask = 0;
  408. hif_event_history_deinit(soc->hif_handle, i);
  409. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  410. }
  411. qdf_mem_set(&soc->mon_intr_id_lmac_map,
  412. sizeof(soc->mon_intr_id_lmac_map),
  413. DP_MON_INVALID_LMAC_ID);
  414. }
  415. static QDF_STATUS dp_soc_interrupt_attach_rh(struct cdp_soc_t *txrx_soc)
  416. {
  417. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  418. int i = 0;
  419. int num_irq = 0;
  420. int lmac_id = 0;
  421. int napi_scale;
  422. qdf_mem_set(&soc->mon_intr_id_lmac_map,
  423. sizeof(soc->mon_intr_id_lmac_map), DP_MON_INVALID_LMAC_ID);
  424. if (soc->cdp_soc.ol_ops->get_con_mode &&
  425. soc->cdp_soc.ol_ops->get_con_mode() !=
  426. QDF_GLOBAL_MONITOR_MODE)
  427. return QDF_STATUS_SUCCESS;
  428. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  429. int ret = 0;
  430. /* Map of IRQ ids registered with one interrupt context */
  431. int irq_id_map[HIF_MAX_GRP_IRQ];
  432. int rx_mon_mask =
  433. dp_soc_get_mon_mask_for_interrupt_mode(soc, i);
  434. int rxdma2host_ring_mask =
  435. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  436. soc->intr_ctx[i].dp_intr_id = i;
  437. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  438. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  439. soc->intr_ctx[i].soc = soc;
  440. num_irq = 0;
  441. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  442. &num_irq);
  443. napi_scale = wlan_cfg_get_napi_scale_factor(soc->wlan_cfg_ctx);
  444. if (!napi_scale)
  445. napi_scale = QCA_NAPI_DEF_SCALE_BIN_SHIFT;
  446. ret = hif_register_ext_group(soc->hif_handle,
  447. num_irq, irq_id_map, dp_service_srngs_wrapper,
  448. &soc->intr_ctx[i], "dp_intr",
  449. HIF_EXEC_NAPI_TYPE, napi_scale);
  450. dp_debug(" int ctx %u num_irq %u irq_id_map %u %u",
  451. i, num_irq, irq_id_map[0], irq_id_map[1]);
  452. if (ret) {
  453. dp_init_err("%pK: failed, ret = %d", soc, ret);
  454. dp_soc_interrupt_detach_rh(txrx_soc);
  455. return QDF_STATUS_E_FAILURE;
  456. }
  457. hif_event_history_init(soc->hif_handle, i);
  458. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  459. if (dp_is_mon_mask_valid(soc, &soc->intr_ctx[i])) {
  460. soc->mon_intr_id_lmac_map[lmac_id] = i;
  461. lmac_id++;
  462. }
  463. }
  464. hif_configure_ext_group_interrupts(soc->hif_handle);
  465. return QDF_STATUS_SUCCESS;
  466. }
  467. static QDF_STATUS dp_soc_attach_poll_rh(struct cdp_soc_t *txrx_soc)
  468. {
  469. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  470. uint32_t lmac_id = 0;
  471. int i;
  472. qdf_mem_set(&soc->mon_intr_id_lmac_map,
  473. sizeof(soc->mon_intr_id_lmac_map), DP_MON_INVALID_LMAC_ID);
  474. soc->intr_mode = DP_INTR_POLL;
  475. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  476. soc->intr_ctx[i].rx_mon_ring_mask =
  477. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  478. if (dp_is_mon_mask_valid(soc, &soc->intr_ctx[i])) {
  479. hif_event_history_init(soc->hif_handle, i);
  480. soc->mon_intr_id_lmac_map[lmac_id] = i;
  481. lmac_id++;
  482. }
  483. }
  484. qdf_timer_init(soc->osdev, &soc->int_timer,
  485. dp_interrupt_timer, (void *)soc,
  486. QDF_TIMER_TYPE_WAKE_APPS);
  487. return QDF_STATUS_SUCCESS;
  488. }
  489. static uint32_t dp_service_srngs_rh(void *dp_ctx, uint32_t dp_budget, int cpu)
  490. {
  491. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  492. struct dp_soc *soc = int_ctx->soc;
  493. uint32_t work_done = 0;
  494. int budget = dp_budget;
  495. uint32_t remaining_quota = dp_budget;
  496. if (qdf_unlikely(!dp_monitor_is_vdev_timer_running(soc))) {
  497. work_done = dp_process_lmac_rings(int_ctx, remaining_quota);
  498. if (work_done) {
  499. budget -= work_done;
  500. if (budget <= 0)
  501. goto budget_done;
  502. remaining_quota = budget;
  503. }
  504. }
  505. budget_done:
  506. qdf_atomic_clear_bit(cpu, &soc->service_rings_running);
  507. if (soc->notify_fw_callback)
  508. soc->notify_fw_callback(soc);
  509. return dp_budget - budget;
  510. }
  511. /**
  512. * dp_pdev_fill_tx_endpoint_info_rh() - Prefill fixed TX endpoint information
  513. * that is used during packet transmit
  514. * @pdev: Handle to DP pdev struct
  515. *
  516. * Return: QDF_STATUS_SUCCESS/QDF_STATUS_E_NOENT
  517. */
  518. static QDF_STATUS dp_pdev_fill_tx_endpoint_info_rh(struct dp_pdev *pdev)
  519. {
  520. struct dp_pdev_rh *rh_pdev = dp_get_rh_pdev_from_dp_pdev(pdev);
  521. struct dp_soc_rh *rh_soc = dp_get_rh_soc_from_dp_soc(pdev->soc);
  522. struct dp_tx_ep_info_rh *tx_ep_info = &rh_pdev->tx_ep_info;
  523. struct hif_opaque_softc *hif_handle = pdev->soc->hif_handle;
  524. int ul_is_polled, dl_is_polled;
  525. uint8_t ul_pipe, dl_pipe;
  526. int status;
  527. status = hif_map_service_to_pipe(hif_handle, HTT_DATA2_MSG_SVC,
  528. &ul_pipe, &dl_pipe,
  529. &ul_is_polled, &dl_is_polled);
  530. if (status) {
  531. hif_err("Failed to map tx pipe: %d", status);
  532. return QDF_STATUS_E_NOENT;
  533. }
  534. tx_ep_info->ce_tx_hdl = hif_get_ce_handle(hif_handle, ul_pipe);
  535. tx_ep_info->download_len = HAL_TX_DESC_LEN_BYTES +
  536. sizeof(struct tlv_32_hdr) +
  537. DP_RH_TX_HDR_SIZE_OUTER_HDR_MAX +
  538. DP_RH_TX_HDR_SIZE_802_1Q +
  539. DP_RH_TX_HDR_SIZE_LLC_SNAP +
  540. DP_RH_TX_HDR_SIZE_IP;
  541. tx_ep_info->tx_endpoint = rh_soc->tx_endpoint;
  542. return QDF_STATUS_SUCCESS;
  543. }
  544. static QDF_STATUS dp_pdev_attach_rh(struct dp_pdev *pdev,
  545. struct cdp_pdev_attach_params *params)
  546. {
  547. return dp_pdev_fill_tx_endpoint_info_rh(pdev);
  548. }
  549. static QDF_STATUS dp_pdev_detach_rh(struct dp_pdev *pdev)
  550. {
  551. return QDF_STATUS_SUCCESS;
  552. }
  553. static QDF_STATUS dp_vdev_attach_rh(struct dp_soc *soc, struct dp_vdev *vdev)
  554. {
  555. return QDF_STATUS_SUCCESS;
  556. }
  557. static QDF_STATUS dp_vdev_detach_rh(struct dp_soc *soc, struct dp_vdev *vdev)
  558. {
  559. return QDF_STATUS_SUCCESS;
  560. }
  561. qdf_size_t dp_get_soc_context_size_rh(void)
  562. {
  563. return sizeof(struct dp_soc_rh);
  564. }
  565. #ifdef NO_RX_PKT_HDR_TLV
  566. /**
  567. * dp_rxdma_ring_sel_cfg_rh() - Setup RXDMA ring config
  568. * @soc: Common DP soc handle
  569. *
  570. * Return: QDF_STATUS
  571. */
  572. static QDF_STATUS
  573. dp_rxdma_ring_sel_cfg_rh(struct dp_soc *soc)
  574. {
  575. int i;
  576. int mac_id;
  577. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  578. struct dp_srng *rx_mac_srng;
  579. QDF_STATUS status = QDF_STATUS_SUCCESS;
  580. uint16_t buf_size;
  581. buf_size = wlan_cfg_rx_buffer_size(soc->wlan_cfg_ctx);
  582. htt_tlv_filter.mpdu_start = 1;
  583. htt_tlv_filter.msdu_start = 1;
  584. htt_tlv_filter.mpdu_end = 1;
  585. htt_tlv_filter.msdu_end = 1;
  586. htt_tlv_filter.attention = 1;
  587. htt_tlv_filter.packet = 1;
  588. htt_tlv_filter.packet_header = 0;
  589. htt_tlv_filter.ppdu_start = 0;
  590. htt_tlv_filter.ppdu_end = 0;
  591. htt_tlv_filter.ppdu_end_user_stats = 0;
  592. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  593. htt_tlv_filter.ppdu_end_status_done = 0;
  594. htt_tlv_filter.enable_fp = 1;
  595. htt_tlv_filter.enable_md = 0;
  596. htt_tlv_filter.enable_md = 0;
  597. htt_tlv_filter.enable_mo = 0;
  598. htt_tlv_filter.fp_mgmt_filter = 0;
  599. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  600. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  601. FILTER_DATA_MCAST |
  602. FILTER_DATA_DATA);
  603. htt_tlv_filter.mo_mgmt_filter = 0;
  604. htt_tlv_filter.mo_ctrl_filter = 0;
  605. htt_tlv_filter.mo_data_filter = 0;
  606. htt_tlv_filter.md_data_filter = 0;
  607. htt_tlv_filter.offset_valid = true;
  608. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  609. /*Not subscribing rx_pkt_header*/
  610. htt_tlv_filter.rx_header_offset = 0;
  611. htt_tlv_filter.rx_mpdu_start_offset =
  612. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  613. htt_tlv_filter.rx_mpdu_end_offset =
  614. hal_rx_mpdu_end_offset_get(soc->hal_soc);
  615. htt_tlv_filter.rx_msdu_start_offset =
  616. hal_rx_msdu_start_offset_get(soc->hal_soc);
  617. htt_tlv_filter.rx_msdu_end_offset =
  618. hal_rx_msdu_end_offset_get(soc->hal_soc);
  619. htt_tlv_filter.rx_attn_offset =
  620. hal_rx_attn_offset_get(soc->hal_soc);
  621. for (i = 0; i < MAX_PDEV_CNT; i++) {
  622. struct dp_pdev *pdev = soc->pdev_list[i];
  623. if (!pdev)
  624. continue;
  625. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  626. int mac_for_pdev =
  627. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  628. /*
  629. * Obtain lmac id from pdev to access the LMAC ring
  630. * in soc context
  631. */
  632. int lmac_id =
  633. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  634. pdev->pdev_id);
  635. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  636. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  637. rx_mac_srng->hal_srng,
  638. RXDMA_BUF, buf_size,
  639. &htt_tlv_filter);
  640. }
  641. }
  642. if (QDF_IS_STATUS_SUCCESS(status))
  643. status = dp_htt_h2t_rx_ring_rfs_cfg(soc->htt_handle);
  644. return status;
  645. }
  646. #else
  647. static QDF_STATUS
  648. dp_rxdma_ring_sel_cfg_rh(struct dp_soc *soc)
  649. {
  650. int i;
  651. int mac_id;
  652. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  653. struct dp_srng *rx_mac_srng;
  654. QDF_STATUS status = QDF_STATUS_SUCCESS;
  655. uint16_t buf_size;
  656. buf_size = wlan_cfg_rx_buffer_size(soc->wlan_cfg_ctx);
  657. htt_tlv_filter.mpdu_start = 1;
  658. htt_tlv_filter.msdu_start = 1;
  659. htt_tlv_filter.mpdu_end = 1;
  660. htt_tlv_filter.msdu_end = 1;
  661. htt_tlv_filter.attention = 1;
  662. htt_tlv_filter.packet = 1;
  663. htt_tlv_filter.packet_header = 1;
  664. htt_tlv_filter.ppdu_start = 0;
  665. htt_tlv_filter.ppdu_end = 0;
  666. htt_tlv_filter.ppdu_end_user_stats = 0;
  667. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  668. htt_tlv_filter.ppdu_end_status_done = 0;
  669. htt_tlv_filter.enable_fp = 1;
  670. htt_tlv_filter.enable_md = 0;
  671. htt_tlv_filter.enable_md = 0;
  672. htt_tlv_filter.enable_mo = 0;
  673. htt_tlv_filter.fp_mgmt_filter = 0;
  674. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  675. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  676. FILTER_DATA_MCAST |
  677. FILTER_DATA_DATA);
  678. htt_tlv_filter.mo_mgmt_filter = 0;
  679. htt_tlv_filter.mo_ctrl_filter = 0;
  680. htt_tlv_filter.mo_data_filter = 0;
  681. htt_tlv_filter.md_data_filter = 0;
  682. htt_tlv_filter.offset_valid = true;
  683. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  684. htt_tlv_filter.rx_header_offset =
  685. hal_rx_pkt_tlv_offset_get(soc->hal_soc);
  686. htt_tlv_filter.rx_mpdu_start_offset =
  687. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  688. htt_tlv_filter.rx_mpdu_end_offset =
  689. hal_rx_mpdu_end_offset_get(soc->hal_soc);
  690. htt_tlv_filter.rx_msdu_start_offset =
  691. hal_rx_msdu_start_offset_get(soc->hal_soc);
  692. htt_tlv_filter.rx_msdu_end_offset =
  693. hal_rx_msdu_end_offset_get(soc->hal_soc);
  694. htt_tlv_filter.rx_attn_offset =
  695. hal_rx_attn_offset_get(soc->hal_soc);
  696. for (i = 0; i < MAX_PDEV_CNT; i++) {
  697. struct dp_pdev *pdev = soc->pdev_list[i];
  698. if (!pdev)
  699. continue;
  700. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  701. int mac_for_pdev =
  702. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  703. /*
  704. * Obtain lmac id from pdev to access the LMAC ring
  705. * in soc context
  706. */
  707. int lmac_id =
  708. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  709. pdev->pdev_id);
  710. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  711. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  712. rx_mac_srng->hal_srng,
  713. RXDMA_BUF, buf_size,
  714. &htt_tlv_filter);
  715. }
  716. }
  717. if (QDF_IS_STATUS_SUCCESS(status))
  718. status = dp_htt_h2t_rx_ring_rfs_cfg(soc->htt_handle);
  719. return status;
  720. }
  721. #endif
  722. static void dp_soc_srng_deinit_rh(struct dp_soc *soc)
  723. {
  724. }
  725. static void dp_soc_srng_free_rh(struct dp_soc *soc)
  726. {
  727. }
  728. static QDF_STATUS dp_soc_srng_alloc_rh(struct dp_soc *soc)
  729. {
  730. return QDF_STATUS_SUCCESS;
  731. }
  732. static QDF_STATUS dp_soc_srng_init_rh(struct dp_soc *soc)
  733. {
  734. return QDF_STATUS_SUCCESS;
  735. }
  736. static void dp_tx_implicit_rbm_set_rh(struct dp_soc *soc,
  737. uint8_t tx_ring_id,
  738. uint8_t bm_id)
  739. {
  740. }
  741. static QDF_STATUS dp_txrx_set_vdev_param_rh(struct dp_soc *soc,
  742. struct dp_vdev *vdev,
  743. enum cdp_vdev_param_type param,
  744. cdp_config_param_type val)
  745. {
  746. return QDF_STATUS_SUCCESS;
  747. }
  748. static void dp_get_rx_hash_key_rh(struct dp_soc *soc,
  749. struct cdp_lro_hash_config *lro_hash)
  750. {
  751. dp_get_rx_hash_key_bytes(lro_hash);
  752. }
  753. #if defined(DP_POWER_SAVE) || defined(FEATURE_RUNTIME_PM)
  754. static void dp_update_ring_hptp_rh(struct dp_soc *soc, bool force_flush)
  755. {
  756. struct dp_pdev_rh *rh_pdev =
  757. dp_get_rh_pdev_from_dp_pdev(soc->pdev_list[0]);
  758. struct dp_tx_ep_info_rh *tx_ep_info = &rh_pdev->tx_ep_info;
  759. ce_flush_tx_ring_write_idx(tx_ep_info->ce_tx_hdl, force_flush);
  760. }
  761. #endif
  762. void dp_initialize_arch_ops_rh(struct dp_arch_ops *arch_ops)
  763. {
  764. arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_rh;
  765. arch_ops->tx_comp_get_params_from_hal_desc =
  766. dp_tx_comp_get_params_from_hal_desc_rh;
  767. arch_ops->dp_tx_process_htt_completion =
  768. dp_tx_process_htt_completion_rh;
  769. arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
  770. dp_wbm_get_rx_desc_from_hal_desc_rh;
  771. arch_ops->dp_tx_desc_pool_alloc = dp_tx_desc_pool_alloc_rh;
  772. arch_ops->dp_tx_desc_pool_free = dp_tx_desc_pool_free_rh;
  773. arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_rh;
  774. arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_rh;
  775. arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_rh;
  776. arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_rh;
  777. arch_ops->dp_tx_compute_hw_delay = dp_tx_compute_tx_delay_rh;
  778. arch_ops->txrx_get_context_size = dp_get_context_size_rh;
  779. arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_rh;
  780. arch_ops->txrx_soc_attach = dp_soc_attach_rh;
  781. arch_ops->txrx_soc_detach = dp_soc_detach_rh;
  782. arch_ops->txrx_soc_init = dp_soc_init_rh;
  783. arch_ops->txrx_soc_deinit = dp_soc_deinit_rh;
  784. arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_rh;
  785. arch_ops->txrx_soc_srng_init = dp_soc_srng_init_rh;
  786. arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_rh;
  787. arch_ops->txrx_soc_srng_free = dp_soc_srng_free_rh;
  788. arch_ops->txrx_pdev_attach = dp_pdev_attach_rh;
  789. arch_ops->txrx_pdev_detach = dp_pdev_detach_rh;
  790. arch_ops->txrx_vdev_attach = dp_vdev_attach_rh;
  791. arch_ops->txrx_vdev_detach = dp_vdev_detach_rh;
  792. arch_ops->txrx_peer_map_attach = dp_peer_map_attach_rh;
  793. arch_ops->txrx_peer_map_detach = dp_peer_map_detach_rh;
  794. arch_ops->get_rx_hash_key = dp_get_rx_hash_key_rh;
  795. arch_ops->dp_rx_desc_cookie_2_va =
  796. dp_rx_desc_cookie_2_va_rh;
  797. arch_ops->dp_rx_intrabss_mcast_handler =
  798. dp_rx_intrabss_handle_nawds_rh;
  799. arch_ops->dp_rx_word_mask_subscribe = dp_rx_word_mask_subscribe_rh;
  800. arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_rh;
  801. arch_ops->dp_rx_peer_metadata_peer_id_get =
  802. dp_rx_peer_metadata_peer_id_get_rh;
  803. arch_ops->soc_cfg_attach = dp_soc_cfg_attach_rh;
  804. arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_rh;
  805. arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_rh;
  806. arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_rh;
  807. arch_ops->dp_peer_rx_reorder_queue_setup =
  808. dp_peer_rx_reorder_queue_setup_rh;
  809. arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_rh;
  810. arch_ops->reo_remap_config = dp_reo_remap_config_rh;
  811. arch_ops->txrx_peer_setup = dp_peer_setup_rh;
  812. arch_ops->txrx_srng_init = dp_srng_init_rh;
  813. #if defined(DP_POWER_SAVE) || defined(FEATURE_RUNTIME_PM)
  814. arch_ops->dp_update_ring_hptp = dp_update_ring_hptp_rh;
  815. #endif
  816. arch_ops->dp_flush_tx_ring = dp_flush_tx_ring_rh;
  817. arch_ops->dp_soc_interrupt_attach = dp_soc_interrupt_attach_rh;
  818. arch_ops->dp_soc_attach_poll = dp_soc_attach_poll_rh;
  819. arch_ops->dp_soc_interrupt_detach = dp_soc_interrupt_detach_rh;
  820. arch_ops->dp_service_srngs = dp_service_srngs_rh;
  821. }