dp_li_tx.c 18 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "cdp_txrx_cmn_struct.h"
  20. #include "dp_types.h"
  21. #include "dp_tx.h"
  22. #include "dp_li_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include <dp_internal.h>
  25. #include <dp_htt.h>
  26. #include <hal_li_api.h>
  27. #include <hal_li_tx.h>
  28. #include "dp_peer.h"
  29. #ifdef FEATURE_WDS
  30. #include "dp_txrx_wds.h"
  31. #endif
  32. #include "dp_li.h"
  33. extern uint8_t sec_type_map[MAX_CDP_SEC_TYPE];
  34. void dp_tx_comp_get_params_from_hal_desc_li(struct dp_soc *soc,
  35. void *tx_comp_hal_desc,
  36. struct dp_tx_desc_s **r_tx_desc)
  37. {
  38. uint8_t pool_id;
  39. uint32_t tx_desc_id;
  40. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  41. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  42. DP_TX_DESC_ID_POOL_OS;
  43. /* Find Tx descriptor */
  44. *r_tx_desc = dp_tx_desc_find(soc, pool_id,
  45. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  46. DP_TX_DESC_ID_PAGE_OS,
  47. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  48. DP_TX_DESC_ID_OFFSET_OS,
  49. (tx_desc_id & DP_TX_DESC_ID_SPCL_MASK));
  50. /* Pool id is not matching. Error */
  51. if ((*r_tx_desc)->pool_id != pool_id) {
  52. dp_tx_comp_alert("Tx Comp pool id %d not matched %d",
  53. pool_id, (*r_tx_desc)->pool_id);
  54. qdf_assert_always(0);
  55. }
  56. (*r_tx_desc)->peer_id = hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  57. }
  58. static inline
  59. void dp_tx_process_mec_notify_li(struct dp_soc *soc, uint8_t *status)
  60. {
  61. struct dp_vdev *vdev;
  62. uint8_t vdev_id;
  63. uint32_t *htt_desc = (uint32_t *)status;
  64. /*
  65. * Get vdev id from HTT status word in case of MEC
  66. * notification
  67. */
  68. vdev_id = HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(htt_desc[3]);
  69. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  70. return;
  71. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  72. DP_MOD_ID_HTT_COMP);
  73. if (!vdev)
  74. return;
  75. dp_tx_mec_handler(vdev, status);
  76. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  77. }
  78. void dp_tx_process_htt_completion_li(struct dp_soc *soc,
  79. struct dp_tx_desc_s *tx_desc,
  80. uint8_t *status,
  81. uint8_t ring_id)
  82. {
  83. uint8_t tx_status;
  84. struct dp_pdev *pdev;
  85. struct dp_vdev *vdev = NULL;
  86. struct hal_tx_completion_status ts = {0};
  87. uint32_t *htt_desc = (uint32_t *)status;
  88. struct dp_txrx_peer *txrx_peer;
  89. dp_txrx_ref_handle txrx_ref_handle = NULL;
  90. struct cdp_tid_tx_stats *tid_stats = NULL;
  91. struct htt_soc *htt_handle;
  92. uint8_t vdev_id;
  93. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  94. htt_handle = (struct htt_soc *)soc->htt_handle;
  95. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  96. /*
  97. * There can be scenario where WBM consuming descriptor enqueued
  98. * from TQM2WBM first and TQM completion can happen before MEC
  99. * notification comes from FW2WBM. Avoid access any field of tx
  100. * descriptor in case of MEC notify.
  101. */
  102. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY)
  103. return dp_tx_process_mec_notify_li(soc, status);
  104. /*
  105. * If the descriptor is already freed in vdev_detach,
  106. * continue to next descriptor
  107. */
  108. if (qdf_unlikely(!tx_desc->flags)) {
  109. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  110. tx_desc->id);
  111. return;
  112. }
  113. if (qdf_unlikely(tx_desc->vdev_id == DP_INVALID_VDEV_ID)) {
  114. dp_tx_comp_info_rl("Invalid vdev_id %d", tx_desc->id);
  115. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  116. goto release_tx_desc;
  117. }
  118. pdev = tx_desc->pdev;
  119. if (qdf_unlikely(!pdev)) {
  120. dp_tx_comp_warn("The pdev in TX desc is NULL, dropped.");
  121. dp_tx_comp_warn("tx_status: %u", tx_status);
  122. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  123. goto release_tx_desc;
  124. }
  125. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  126. dp_tx_comp_info_rl("pdev in down state %d", tx_desc->id);
  127. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  128. goto release_tx_desc;
  129. }
  130. qdf_assert(tx_desc->pdev);
  131. vdev_id = tx_desc->vdev_id;
  132. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  133. DP_MOD_ID_HTT_COMP);
  134. if (qdf_unlikely(!vdev)) {
  135. dp_tx_comp_info_rl("Unable to get vdev ref %d", tx_desc->id);
  136. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  137. goto release_tx_desc;
  138. }
  139. switch (tx_status) {
  140. case HTT_TX_FW2WBM_TX_STATUS_OK:
  141. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  142. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  143. {
  144. uint8_t tid;
  145. uint8_t transmit_cnt_valid = 0;
  146. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  147. ts.peer_id =
  148. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  149. htt_desc[2]);
  150. ts.tid =
  151. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  152. htt_desc[2]);
  153. } else {
  154. ts.peer_id = HTT_INVALID_PEER;
  155. ts.tid = HTT_INVALID_TID;
  156. }
  157. ts.release_src = HAL_TX_COMP_RELEASE_SOURCE_FW;
  158. ts.ppdu_id =
  159. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  160. htt_desc[1]);
  161. ts.ack_frame_rssi =
  162. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  163. htt_desc[1]);
  164. transmit_cnt_valid =
  165. HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_GET(
  166. htt_desc[2]);
  167. if (transmit_cnt_valid)
  168. ts.transmit_cnt =
  169. HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_GET(
  170. htt_desc[0]);
  171. ts.tsf = htt_desc[3];
  172. ts.first_msdu = 1;
  173. ts.last_msdu = 1;
  174. switch (tx_status) {
  175. case HTT_TX_FW2WBM_TX_STATUS_OK:
  176. ts.status = HAL_TX_TQM_RR_FRAME_ACKED;
  177. break;
  178. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  179. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  180. break;
  181. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  182. ts.status = HAL_TX_TQM_RR_REM_CMD_TX;
  183. break;
  184. }
  185. tid = ts.tid;
  186. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  187. tid = CDP_MAX_DATA_TIDS - 1;
  188. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  189. if (qdf_unlikely(pdev->delay_stats_flag) ||
  190. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(vdev)))
  191. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  192. if (tx_status < CDP_MAX_TX_HTT_STATUS)
  193. tid_stats->htt_status_cnt[tx_status]++;
  194. txrx_peer = dp_txrx_peer_get_ref_by_id(soc, ts.peer_id,
  195. &txrx_ref_handle,
  196. DP_MOD_ID_HTT_COMP);
  197. if (qdf_likely(txrx_peer)) {
  198. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1,
  199. qdf_nbuf_len(tx_desc->nbuf));
  200. if (tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)
  201. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  202. }
  203. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, txrx_peer,
  204. ring_id);
  205. dp_tx_comp_process_desc(soc, tx_desc, &ts, txrx_peer);
  206. dp_tx_desc_release(soc, tx_desc, tx_desc->pool_id);
  207. if (qdf_likely(txrx_peer))
  208. dp_txrx_peer_unref_delete(txrx_ref_handle,
  209. DP_MOD_ID_HTT_COMP);
  210. break;
  211. }
  212. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  213. {
  214. uint8_t reinject_reason;
  215. reinject_reason =
  216. HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_GET(
  217. htt_desc[0]);
  218. dp_tx_reinject_handler(soc, vdev, tx_desc,
  219. status, reinject_reason);
  220. break;
  221. }
  222. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  223. {
  224. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  225. break;
  226. }
  227. case HTT_TX_FW2WBM_TX_STATUS_VDEVID_MISMATCH:
  228. {
  229. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  230. goto release_tx_desc;
  231. }
  232. default:
  233. dp_tx_comp_err("Invalid HTT tx_status %d\n",
  234. tx_status);
  235. goto release_tx_desc;
  236. }
  237. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  238. return;
  239. release_tx_desc:
  240. dp_tx_comp_free_buf(soc, tx_desc, false);
  241. dp_tx_desc_release(soc, tx_desc, tx_desc->pool_id);
  242. if (vdev)
  243. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  244. }
  245. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  246. /**
  247. * dp_tx_get_rbm_id_li() - Get the RBM ID for data transmission completion.
  248. * @soc: DP soc structure pointer
  249. * @ring_id: Transmit Queue/ring_id to be used when XPS is enabled
  250. *
  251. * Return: HAL ring handle
  252. */
  253. #ifdef IPA_OFFLOAD
  254. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  255. uint8_t ring_id)
  256. {
  257. return (ring_id + soc->wbm_sw0_bm_id);
  258. }
  259. #else
  260. #ifndef QCA_DP_ENABLE_TX_COMP_RING4
  261. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  262. uint8_t ring_id)
  263. {
  264. return (ring_id ? HAL_WBM_SW0_BM_ID + (ring_id - 1) :
  265. HAL_WBM_SW2_BM_ID);
  266. }
  267. #else
  268. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  269. uint8_t ring_id)
  270. {
  271. if (ring_id == soc->num_tcl_data_rings)
  272. return HAL_WBM_SW4_BM_ID(soc->wbm_sw0_bm_id);
  273. return (ring_id + HAL_WBM_SW0_BM_ID(soc->wbm_sw0_bm_id));
  274. }
  275. #endif
  276. #endif
  277. #else
  278. #ifdef TX_MULTI_TCL
  279. #ifdef IPA_OFFLOAD
  280. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  281. uint8_t ring_id)
  282. {
  283. if (soc->wlan_cfg_ctx->ipa_enabled)
  284. return (ring_id + soc->wbm_sw0_bm_id);
  285. return soc->wlan_cfg_ctx->tcl_wbm_map_array[ring_id].wbm_rbm_id;
  286. }
  287. #else
  288. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  289. uint8_t ring_id)
  290. {
  291. return soc->wlan_cfg_ctx->tcl_wbm_map_array[ring_id].wbm_rbm_id;
  292. }
  293. #endif
  294. #else
  295. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  296. uint8_t ring_id)
  297. {
  298. return (ring_id + soc->wbm_sw0_bm_id);
  299. }
  300. #endif
  301. #endif
  302. #if defined(CLEAR_SW2TCL_CONSUMED_DESC)
  303. /**
  304. * dp_tx_clear_consumed_hw_descs - Reset all the consumed Tx ring descs to 0
  305. *
  306. * @soc: DP soc handle
  307. * @hal_ring_hdl: Source ring pointer
  308. *
  309. * Return: void
  310. */
  311. static inline
  312. void dp_tx_clear_consumed_hw_descs(struct dp_soc *soc,
  313. hal_ring_handle_t hal_ring_hdl)
  314. {
  315. void *desc = hal_srng_src_get_next_consumed(soc->hal_soc, hal_ring_hdl);
  316. while (desc) {
  317. hal_tx_desc_clear(desc);
  318. desc = hal_srng_src_get_next_consumed(soc->hal_soc,
  319. hal_ring_hdl);
  320. }
  321. }
  322. #else
  323. static inline
  324. void dp_tx_clear_consumed_hw_descs(struct dp_soc *soc,
  325. hal_ring_handle_t hal_ring_hdl)
  326. {
  327. }
  328. #endif /* CLEAR_SW2TCL_CONSUMED_DESC */
  329. #ifdef WLAN_CONFIG_TX_DELAY
  330. static inline
  331. QDF_STATUS dp_tx_compute_hw_delay_li(struct dp_soc *soc,
  332. struct dp_vdev *vdev,
  333. struct hal_tx_completion_status *ts,
  334. uint32_t *delay_us)
  335. {
  336. return dp_tx_compute_hw_delay_us(ts, vdev->delta_tsf, delay_us);
  337. }
  338. #else
  339. static inline
  340. QDF_STATUS dp_tx_compute_hw_delay_li(struct dp_soc *soc,
  341. struct dp_vdev *vdev,
  342. struct hal_tx_completion_status *ts,
  343. uint32_t *delay_us)
  344. {
  345. return QDF_STATUS_SUCCESS;
  346. }
  347. #endif
  348. #ifdef CONFIG_SAWF
  349. /**
  350. * dp_sawf_config_li - Configure sawf specific fields in tcl
  351. *
  352. * @soc: DP soc handle
  353. * @hal_tx_desc_cached: tx descriptor
  354. * @fw_metadata: firmware metadata
  355. * @vdev_id: vdev id
  356. * @nbuf: skb buffer
  357. * @msdu_info: msdu info
  358. *
  359. * Return: void
  360. */
  361. static inline
  362. void dp_sawf_config_li(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  363. uint16_t *fw_metadata, uint16_t vdev_id,
  364. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  365. {
  366. uint8_t q_id = 0;
  367. uint32_t flow_idx = 0;
  368. if (!wlan_cfg_get_sawf_config(soc->wlan_cfg_ctx))
  369. return;
  370. q_id = dp_sawf_queue_id_get(nbuf);
  371. if (q_id == DP_SAWF_DEFAULT_Q_INVALID)
  372. return;
  373. msdu_info->tid = (q_id & (CDP_DATA_TID_MAX - 1));
  374. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached,
  375. (q_id & (CDP_DATA_TID_MAX - 1)));
  376. if ((q_id >= DP_SAWF_DEFAULT_QUEUE_MIN) &&
  377. (q_id < DP_SAWF_DEFAULT_QUEUE_MAX))
  378. return;
  379. dp_sawf_tcl_cmd(fw_metadata, nbuf);
  380. /* For SAWF, q_id starts from DP_SAWF_Q_MAX */
  381. if (!dp_sawf_get_search_index(soc, nbuf, vdev_id,
  382. q_id, &flow_idx))
  383. hal_tx_desc_set_to_fw(hal_tx_desc_cached, true);
  384. hal_tx_desc_set_search_type_li(soc->hal_soc, hal_tx_desc_cached,
  385. HAL_TX_ADDR_INDEX_SEARCH);
  386. hal_tx_desc_set_search_index_li(soc->hal_soc, hal_tx_desc_cached,
  387. flow_idx);
  388. }
  389. #else
  390. static inline
  391. void dp_sawf_config_li(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  392. uint16_t *fw_metadata, uint16_t vdev_id,
  393. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  394. {
  395. }
  396. #define dp_sawf_tx_enqueue_peer_stats(soc, tx_desc)
  397. #define dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc)
  398. #endif
  399. QDF_STATUS
  400. dp_tx_hw_enqueue_li(struct dp_soc *soc, struct dp_vdev *vdev,
  401. struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
  402. struct cdp_tx_exception_metadata *tx_exc_metadata,
  403. struct dp_tx_msdu_info_s *msdu_info)
  404. {
  405. void *hal_tx_desc;
  406. uint32_t *hal_tx_desc_cached;
  407. int coalesce = 0;
  408. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  409. uint8_t ring_id = tx_q->ring_id & DP_TX_QUEUE_MASK;
  410. uint8_t tid;
  411. /*
  412. * Setting it initialization statically here to avoid
  413. * a memset call jump with qdf_mem_set call
  414. */
  415. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  416. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  417. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  418. tx_exc_metadata->sec_type : vdev->sec_type);
  419. /* Return Buffer Manager ID */
  420. uint8_t bm_id = dp_tx_get_rbm_id_li(soc, ring_id);
  421. hal_ring_handle_t hal_ring_hdl = NULL;
  422. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  423. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  424. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  425. return QDF_STATUS_E_RESOURCES;
  426. }
  427. hal_tx_desc_cached = (void *)cached_desc;
  428. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  429. tx_desc->dma_addr, bm_id, tx_desc->id,
  430. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG));
  431. hal_tx_desc_set_lmac_id_li(soc->hal_soc, hal_tx_desc_cached,
  432. vdev->lmac_id);
  433. hal_tx_desc_set_search_type_li(soc->hal_soc, hal_tx_desc_cached,
  434. vdev->search_type);
  435. hal_tx_desc_set_search_index_li(soc->hal_soc, hal_tx_desc_cached,
  436. vdev->bss_ast_idx);
  437. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  438. vdev->dscp_tid_map_id);
  439. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  440. sec_type_map[sec_type]);
  441. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  442. (vdev->bss_ast_hash & 0xF));
  443. if (dp_sawf_tag_valid_get(tx_desc->nbuf)) {
  444. dp_sawf_config_li(soc, hal_tx_desc_cached, &fw_metadata,
  445. vdev->vdev_id, tx_desc->nbuf, msdu_info);
  446. dp_sawf_tx_enqueue_peer_stats(soc, tx_desc);
  447. }
  448. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  449. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  450. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  451. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  452. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  453. vdev->hal_desc_addr_search_flags);
  454. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  455. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  456. /* verify checksum offload configuration*/
  457. if ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) ==
  458. QDF_NBUF_TX_CKSUM_TCP_UDP) ||
  459. qdf_nbuf_is_tso(tx_desc->nbuf)) {
  460. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  461. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  462. }
  463. tid = msdu_info->tid;
  464. if (tid != HTT_TX_EXT_TID_INVALID)
  465. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  466. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  467. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  468. if (!dp_tx_desc_set_ktimestamp(vdev, tx_desc))
  469. dp_tx_desc_set_timestamp(tx_desc);
  470. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  471. tx_desc->length,
  472. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG),
  473. (uint64_t)tx_desc->dma_addr, tx_desc->pkt_offset,
  474. tx_desc->id);
  475. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  476. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  477. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  478. "%s %d : HAL RING Access Failed -- %pK",
  479. __func__, __LINE__, hal_ring_hdl);
  480. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  481. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  482. dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc);
  483. return status;
  484. }
  485. dp_tx_clear_consumed_hw_descs(soc, hal_ring_hdl);
  486. /* Sync cached descriptor with HW */
  487. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  488. if (qdf_unlikely(!hal_tx_desc)) {
  489. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  490. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  491. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  492. dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc);
  493. goto ring_access_fail;
  494. }
  495. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  496. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  497. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  498. coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid,
  499. msdu_info, ring_id);
  500. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  501. DP_STATS_INC(soc, tx.tcl_enq[ring_id], 1);
  502. dp_tx_update_stats(soc, tx_desc, ring_id);
  503. status = QDF_STATUS_SUCCESS;
  504. dp_tx_hw_desc_update_evt((uint8_t *)hal_tx_desc_cached,
  505. hal_ring_hdl, soc, ring_id);
  506. ring_access_fail:
  507. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, coalesce);
  508. dp_pkt_add_timestamp(vdev, QDF_PKT_TX_DRIVER_EXIT,
  509. qdf_get_log_timestamp(), tx_desc->nbuf);
  510. return status;
  511. }
  512. QDF_STATUS dp_tx_desc_pool_init_li(struct dp_soc *soc,
  513. uint32_t num_elem,
  514. uint8_t pool_id,
  515. bool spcl_tx_desc)
  516. {
  517. uint32_t id, count, page_id, offset, pool_id_32;
  518. struct dp_tx_desc_s *tx_desc;
  519. struct dp_tx_desc_pool_s *tx_desc_pool;
  520. uint16_t num_desc_per_page;
  521. if (spcl_tx_desc)
  522. tx_desc_pool = dp_get_spcl_tx_desc_pool(soc, pool_id);
  523. else
  524. tx_desc_pool = dp_get_tx_desc_pool(soc, pool_id);
  525. tx_desc = tx_desc_pool->freelist;
  526. count = 0;
  527. pool_id_32 = (uint32_t)pool_id;
  528. num_desc_per_page = tx_desc_pool->desc_pages.num_element_per_page;
  529. while (tx_desc) {
  530. page_id = count / num_desc_per_page;
  531. offset = count % num_desc_per_page;
  532. id = ((!!spcl_tx_desc) << DP_TX_DESC_ID_SPCL_OS |
  533. (pool_id_32 << DP_TX_DESC_ID_POOL_OS) |
  534. (page_id << DP_TX_DESC_ID_PAGE_OS) | offset);
  535. tx_desc->id = id;
  536. tx_desc->pool_id = pool_id;
  537. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  538. dp_tx_desc_set_magic(tx_desc, DP_TX_MAGIC_PATTERN_FREE);
  539. tx_desc = tx_desc->next;
  540. count++;
  541. }
  542. return QDF_STATUS_SUCCESS;
  543. }
  544. void dp_tx_desc_pool_deinit_li(struct dp_soc *soc,
  545. struct dp_tx_desc_pool_s *tx_desc_pool,
  546. uint8_t pool_id, bool spcl_tx_desc)
  547. {
  548. }
  549. QDF_STATUS dp_tx_compute_tx_delay_li(struct dp_soc *soc,
  550. struct dp_vdev *vdev,
  551. struct hal_tx_completion_status *ts,
  552. uint32_t *delay_us)
  553. {
  554. return dp_tx_compute_hw_delay_li(soc, vdev, ts, delay_us);
  555. }
  556. QDF_STATUS dp_tx_desc_pool_alloc_li(struct dp_soc *soc, uint32_t num_elem,
  557. uint8_t pool_id)
  558. {
  559. return QDF_STATUS_SUCCESS;
  560. }
  561. void dp_tx_desc_pool_free_li(struct dp_soc *soc, uint8_t pool_id)
  562. {
  563. }