dp_ipa.c 123 KB

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  1. /*
  2. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #ifdef IPA_OFFLOAD
  18. #include <wlan_ipa_ucfg_api.h>
  19. #include <wlan_ipa_core.h>
  20. #include <qdf_ipa_wdi3.h>
  21. #include <qdf_types.h>
  22. #include <qdf_lock.h>
  23. #include <hal_hw_headers.h>
  24. #include <hal_api.h>
  25. #include <hal_reo.h>
  26. #include <hif.h>
  27. #include <htt.h>
  28. #include <wdi_event.h>
  29. #include <queue.h>
  30. #include "dp_types.h"
  31. #include "dp_htt.h"
  32. #include "dp_tx.h"
  33. #include "dp_rx.h"
  34. #include "dp_ipa.h"
  35. #include "dp_internal.h"
  36. #ifdef WIFI_MONITOR_SUPPORT
  37. #include "dp_mon.h"
  38. #endif
  39. #ifdef FEATURE_WDS
  40. #include "dp_txrx_wds.h"
  41. #endif
  42. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  43. #include <pld_common.h>
  44. #endif
  45. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  46. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  47. /* WAR for IPA_OFFLOAD case. In some cases, its observed that WBM tries to
  48. * release a buffer into WBM2SW RELEASE ring for IPA, and the ring is full.
  49. * This causes back pressure, resulting in a FW crash.
  50. * By leaving some entries with no buffer attached, WBM will be able to write
  51. * to the ring, and from dumps we can figure out the buffer which is causing
  52. * this issue.
  53. */
  54. #define DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES 16
  55. /**
  56. * struct dp_ipa_reo_remap_record - history for dp ipa reo remaps
  57. * @timestamp: Timestamp when remap occurs
  58. * @ix0_reg: reo destination ring IX0 value
  59. * @ix2_reg: reo destination ring IX2 value
  60. * @ix3_reg: reo destination ring IX3 value
  61. */
  62. struct dp_ipa_reo_remap_record {
  63. uint64_t timestamp;
  64. uint32_t ix0_reg;
  65. uint32_t ix2_reg;
  66. uint32_t ix3_reg;
  67. };
  68. #define WLAN_IPA_AST_META_DATA_MASK htonl(0x000000FF)
  69. #define WLAN_IPA_META_DATA_MASK htonl(0x00FF0000)
  70. #define REO_REMAP_HISTORY_SIZE 32
  71. struct dp_ipa_reo_remap_record dp_ipa_reo_remap_history[REO_REMAP_HISTORY_SIZE];
  72. static qdf_atomic_t dp_ipa_reo_remap_history_index;
  73. static int dp_ipa_reo_remap_record_index_next(qdf_atomic_t *index)
  74. {
  75. int next = qdf_atomic_inc_return(index);
  76. if (next == REO_REMAP_HISTORY_SIZE)
  77. qdf_atomic_sub(REO_REMAP_HISTORY_SIZE, index);
  78. return next % REO_REMAP_HISTORY_SIZE;
  79. }
  80. /**
  81. * dp_ipa_reo_remap_history_add() - Record dp ipa reo remap values
  82. * @ix0_val: reo destination ring IX0 value
  83. * @ix2_val: reo destination ring IX2 value
  84. * @ix3_val: reo destination ring IX3 value
  85. *
  86. * Return: None
  87. */
  88. static void dp_ipa_reo_remap_history_add(uint32_t ix0_val, uint32_t ix2_val,
  89. uint32_t ix3_val)
  90. {
  91. int idx = dp_ipa_reo_remap_record_index_next(
  92. &dp_ipa_reo_remap_history_index);
  93. struct dp_ipa_reo_remap_record *record = &dp_ipa_reo_remap_history[idx];
  94. record->timestamp = qdf_get_log_timestamp();
  95. record->ix0_reg = ix0_val;
  96. record->ix2_reg = ix2_val;
  97. record->ix3_reg = ix3_val;
  98. }
  99. static QDF_STATUS __dp_ipa_handle_buf_smmu_mapping(struct dp_soc *soc,
  100. qdf_nbuf_t nbuf,
  101. uint32_t size,
  102. bool create,
  103. const char *func,
  104. uint32_t line)
  105. {
  106. qdf_mem_info_t mem_map_table = {0};
  107. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  108. qdf_ipa_wdi_hdl_t hdl;
  109. /* Need to handle the case when one soc will
  110. * have multiple pdev(radio's), Currently passing
  111. * pdev_id as 0 assuming 1 soc has only 1 radio.
  112. */
  113. hdl = wlan_ipa_get_hdl(soc->ctrl_psoc, 0);
  114. if (hdl == DP_IPA_HDL_INVALID) {
  115. dp_err("IPA handle is invalid");
  116. return QDF_STATUS_E_INVAL;
  117. }
  118. qdf_update_mem_map_table(soc->osdev, &mem_map_table,
  119. qdf_nbuf_get_frag_paddr(nbuf, 0),
  120. size);
  121. if (create) {
  122. /* Assert if PA is zero */
  123. qdf_assert_always(mem_map_table.pa);
  124. ret = qdf_nbuf_smmu_map_debug(nbuf, hdl, 1, &mem_map_table,
  125. func, line);
  126. } else {
  127. ret = qdf_nbuf_smmu_unmap_debug(nbuf, hdl, 1, &mem_map_table,
  128. func, line);
  129. }
  130. qdf_assert_always(!ret);
  131. /* Return status of mapping/unmapping is stored in
  132. * mem_map_table.result field, assert if the result
  133. * is failure
  134. */
  135. if (create)
  136. qdf_assert_always(!mem_map_table.result);
  137. else
  138. qdf_assert_always(mem_map_table.result >= mem_map_table.size);
  139. return ret;
  140. }
  141. QDF_STATUS dp_ipa_handle_rx_buf_smmu_mapping(struct dp_soc *soc,
  142. qdf_nbuf_t nbuf,
  143. uint32_t size,
  144. bool create, const char *func,
  145. uint32_t line)
  146. {
  147. struct dp_pdev *pdev;
  148. int i;
  149. for (i = 0; i < soc->pdev_count; i++) {
  150. pdev = soc->pdev_list[i];
  151. if (pdev && dp_monitor_is_configured(pdev))
  152. return QDF_STATUS_SUCCESS;
  153. }
  154. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx) ||
  155. !qdf_mem_smmu_s1_enabled(soc->osdev))
  156. return QDF_STATUS_SUCCESS;
  157. /*
  158. * Even if ipa pipes is disabled, but if it's unmap
  159. * operation and nbuf has done ipa smmu map before,
  160. * do ipa smmu unmap as well.
  161. */
  162. if (!qdf_atomic_read(&soc->ipa_pipes_enabled)) {
  163. if (!create && qdf_nbuf_is_rx_ipa_smmu_map(nbuf)) {
  164. DP_STATS_INC(soc, rx.err.ipa_unmap_no_pipe, 1);
  165. } else {
  166. return QDF_STATUS_SUCCESS;
  167. }
  168. }
  169. if (qdf_unlikely(create == qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  170. if (create) {
  171. DP_STATS_INC(soc, rx.err.ipa_smmu_map_dup, 1);
  172. } else {
  173. DP_STATS_INC(soc, rx.err.ipa_smmu_unmap_dup, 1);
  174. }
  175. return QDF_STATUS_E_INVAL;
  176. }
  177. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  178. return __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, size, create,
  179. func, line);
  180. }
  181. static QDF_STATUS __dp_ipa_tx_buf_smmu_mapping(
  182. struct dp_soc *soc,
  183. struct dp_pdev *pdev,
  184. bool create,
  185. const char *func,
  186. uint32_t line)
  187. {
  188. uint32_t index;
  189. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  190. uint32_t tx_buffer_cnt = soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  191. qdf_nbuf_t nbuf;
  192. uint32_t buf_len;
  193. if (!ipa_is_ready()) {
  194. dp_info("IPA is not READY");
  195. return 0;
  196. }
  197. for (index = 0; index < tx_buffer_cnt; index++) {
  198. nbuf = (qdf_nbuf_t)
  199. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[index];
  200. if (!nbuf)
  201. continue;
  202. buf_len = qdf_nbuf_get_data_len(nbuf);
  203. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, buf_len,
  204. create, func, line);
  205. }
  206. return ret;
  207. }
  208. #ifndef QCA_OL_DP_SRNG_LOCK_LESS_ACCESS
  209. static void dp_ipa_set_reo_ctx_mapping_lock_required(struct dp_soc *soc,
  210. bool lock_required)
  211. {
  212. hal_ring_handle_t hal_ring_hdl;
  213. int ring;
  214. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  215. hal_ring_hdl = soc->reo_dest_ring[ring].hal_srng;
  216. hal_srng_lock(hal_ring_hdl);
  217. soc->ipa_reo_ctx_lock_required[ring] = lock_required;
  218. hal_srng_unlock(hal_ring_hdl);
  219. }
  220. }
  221. #else
  222. static void dp_ipa_set_reo_ctx_mapping_lock_required(struct dp_soc *soc,
  223. bool lock_required)
  224. {
  225. }
  226. #endif
  227. #ifdef RX_DESC_MULTI_PAGE_ALLOC
  228. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(struct dp_soc *soc,
  229. struct dp_pdev *pdev,
  230. bool create,
  231. const char *func,
  232. uint32_t line)
  233. {
  234. struct rx_desc_pool *rx_pool;
  235. uint8_t pdev_id;
  236. uint32_t num_desc, page_id, offset, i;
  237. uint16_t num_desc_per_page;
  238. union dp_rx_desc_list_elem_t *rx_desc_elem;
  239. struct dp_rx_desc *rx_desc;
  240. qdf_nbuf_t nbuf;
  241. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  242. if (!qdf_ipa_is_ready())
  243. return ret;
  244. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  245. return ret;
  246. pdev_id = pdev->pdev_id;
  247. rx_pool = &soc->rx_desc_buf[pdev_id];
  248. dp_ipa_set_reo_ctx_mapping_lock_required(soc, true);
  249. qdf_spin_lock_bh(&rx_pool->lock);
  250. dp_ipa_rx_buf_smmu_mapping_lock(soc);
  251. num_desc = rx_pool->pool_size;
  252. num_desc_per_page = rx_pool->desc_pages.num_element_per_page;
  253. for (i = 0; i < num_desc; i++) {
  254. page_id = i / num_desc_per_page;
  255. offset = i % num_desc_per_page;
  256. if (qdf_unlikely(!(rx_pool->desc_pages.cacheable_pages)))
  257. break;
  258. rx_desc_elem = dp_rx_desc_find(page_id, offset, rx_pool);
  259. rx_desc = &rx_desc_elem->rx_desc;
  260. if ((!(rx_desc->in_use)) || rx_desc->unmapped)
  261. continue;
  262. nbuf = rx_desc->nbuf;
  263. if (qdf_unlikely(create ==
  264. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  265. if (create) {
  266. DP_STATS_INC(soc,
  267. rx.err.ipa_smmu_map_dup, 1);
  268. } else {
  269. DP_STATS_INC(soc,
  270. rx.err.ipa_smmu_unmap_dup, 1);
  271. }
  272. continue;
  273. }
  274. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  275. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf,
  276. rx_pool->buf_size,
  277. create, func, line);
  278. }
  279. dp_ipa_rx_buf_smmu_mapping_unlock(soc);
  280. qdf_spin_unlock_bh(&rx_pool->lock);
  281. dp_ipa_set_reo_ctx_mapping_lock_required(soc, false);
  282. return ret;
  283. }
  284. #else
  285. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(
  286. struct dp_soc *soc,
  287. struct dp_pdev *pdev,
  288. bool create,
  289. const char *func,
  290. uint32_t line)
  291. {
  292. struct rx_desc_pool *rx_pool;
  293. uint8_t pdev_id;
  294. qdf_nbuf_t nbuf;
  295. int i;
  296. if (!qdf_ipa_is_ready())
  297. return QDF_STATUS_SUCCESS;
  298. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  299. return QDF_STATUS_SUCCESS;
  300. pdev_id = pdev->pdev_id;
  301. rx_pool = &soc->rx_desc_buf[pdev_id];
  302. dp_ipa_set_reo_ctx_mapping_lock_required(soc, true);
  303. qdf_spin_lock_bh(&rx_pool->lock);
  304. dp_ipa_rx_buf_smmu_mapping_lock(soc);
  305. for (i = 0; i < rx_pool->pool_size; i++) {
  306. if ((!(rx_pool->array[i].rx_desc.in_use)) ||
  307. rx_pool->array[i].rx_desc.unmapped)
  308. continue;
  309. nbuf = rx_pool->array[i].rx_desc.nbuf;
  310. if (qdf_unlikely(create ==
  311. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  312. if (create) {
  313. DP_STATS_INC(soc,
  314. rx.err.ipa_smmu_map_dup, 1);
  315. } else {
  316. DP_STATS_INC(soc,
  317. rx.err.ipa_smmu_unmap_dup, 1);
  318. }
  319. continue;
  320. }
  321. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  322. __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, rx_pool->buf_size,
  323. create, func, line);
  324. }
  325. dp_ipa_rx_buf_smmu_mapping_unlock(soc);
  326. qdf_spin_unlock_bh(&rx_pool->lock);
  327. dp_ipa_set_reo_ctx_mapping_lock_required(soc, false);
  328. return QDF_STATUS_SUCCESS;
  329. }
  330. #endif /* RX_DESC_MULTI_PAGE_ALLOC */
  331. QDF_STATUS dp_ipa_set_smmu_mapped(struct cdp_soc_t *soc_hdl, int val)
  332. {
  333. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  334. qdf_atomic_set(&soc->ipa_mapped, val);
  335. return QDF_STATUS_SUCCESS;
  336. }
  337. int dp_ipa_get_smmu_mapped(struct cdp_soc_t *soc_hdl)
  338. {
  339. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  340. return qdf_atomic_read(&soc->ipa_mapped);
  341. }
  342. static QDF_STATUS dp_ipa_get_shared_mem_info(qdf_device_t osdev,
  343. qdf_shared_mem_t *shared_mem,
  344. void *cpu_addr,
  345. qdf_dma_addr_t dma_addr,
  346. uint32_t size)
  347. {
  348. qdf_dma_addr_t paddr;
  349. int ret;
  350. shared_mem->vaddr = cpu_addr;
  351. qdf_mem_set_dma_size(osdev, &shared_mem->mem_info, size);
  352. *qdf_mem_get_dma_addr_ptr(osdev, &shared_mem->mem_info) = dma_addr;
  353. paddr = qdf_mem_paddr_from_dmaaddr(osdev, dma_addr);
  354. qdf_mem_set_dma_pa(osdev, &shared_mem->mem_info, paddr);
  355. ret = qdf_mem_dma_get_sgtable(osdev->dev, &shared_mem->sgtable,
  356. shared_mem->vaddr, dma_addr, size);
  357. if (ret) {
  358. dp_err("Unable to get DMA sgtable");
  359. return QDF_STATUS_E_NOMEM;
  360. }
  361. qdf_dma_get_sgtable_dma_addr(&shared_mem->sgtable);
  362. return QDF_STATUS_SUCCESS;
  363. }
  364. /**
  365. * dp_ipa_get_tx_bank_id() - API to get TCL bank id
  366. * @soc: dp_soc handle
  367. * @bank_id: out parameter for bank id
  368. *
  369. * Return: QDF_STATUS
  370. */
  371. static QDF_STATUS dp_ipa_get_tx_bank_id(struct dp_soc *soc, uint8_t *bank_id)
  372. {
  373. if (soc->arch_ops.ipa_get_bank_id) {
  374. *bank_id = soc->arch_ops.ipa_get_bank_id(soc);
  375. if (*bank_id < 0) {
  376. return QDF_STATUS_E_INVAL;
  377. } else {
  378. dp_info("bank_id %u", *bank_id);
  379. return QDF_STATUS_SUCCESS;
  380. }
  381. } else {
  382. return QDF_STATUS_E_NOSUPPORT;
  383. }
  384. }
  385. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || \
  386. defined(CONFIG_IPA_WDI_UNIFIED_API)
  387. static void dp_ipa_setup_tx_params_bank_id(struct dp_soc *soc,
  388. qdf_ipa_wdi_pipe_setup_info_t *tx)
  389. {
  390. uint8_t bank_id;
  391. if (QDF_IS_STATUS_SUCCESS(dp_ipa_get_tx_bank_id(soc, &bank_id)))
  392. QDF_IPA_WDI_SETUP_INFO_RX_BANK_ID(tx, bank_id);
  393. }
  394. static void
  395. dp_ipa_setup_tx_smmu_params_bank_id(struct dp_soc *soc,
  396. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  397. {
  398. uint8_t bank_id;
  399. if (QDF_IS_STATUS_SUCCESS(dp_ipa_get_tx_bank_id(soc, &bank_id)))
  400. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_BANK_ID(tx_smmu, bank_id);
  401. }
  402. #else
  403. static inline void
  404. dp_ipa_setup_tx_params_bank_id(struct dp_soc *soc,
  405. qdf_ipa_wdi_pipe_setup_info_t *tx)
  406. {
  407. }
  408. static inline void
  409. dp_ipa_setup_tx_smmu_params_bank_id(struct dp_soc *soc,
  410. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  411. {
  412. }
  413. #endif
  414. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  415. static void
  416. dp_ipa_setup_tx_alt_params_pmac_id(struct dp_soc *soc,
  417. qdf_ipa_wdi_pipe_setup_info_t *tx)
  418. {
  419. uint8_t pmac_id = 0;
  420. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  421. if (soc->pdev_count > 1)
  422. pmac_id = soc->pdev_list[soc->pdev_count - 1]->lmac_id;
  423. QDF_IPA_WDI_SETUP_INFO_RX_PMAC_ID(tx, pmac_id);
  424. }
  425. static void
  426. dp_ipa_setup_tx_alt_smmu_params_pmac_id(struct dp_soc *soc,
  427. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  428. {
  429. uint8_t pmac_id = 0;
  430. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  431. if (soc->pdev_count > 1)
  432. pmac_id = soc->pdev_list[soc->pdev_count - 1]->lmac_id;
  433. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_PMAC_ID(tx_smmu, pmac_id);
  434. }
  435. static void
  436. dp_ipa_setup_tx_params_pmac_id(struct dp_soc *soc,
  437. qdf_ipa_wdi_pipe_setup_info_t *tx)
  438. {
  439. uint8_t pmac_id;
  440. pmac_id = soc->pdev_list[0]->lmac_id;
  441. QDF_IPA_WDI_SETUP_INFO_RX_PMAC_ID(tx, pmac_id);
  442. }
  443. static void
  444. dp_ipa_setup_tx_smmu_params_pmac_id(struct dp_soc *soc,
  445. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  446. {
  447. uint8_t pmac_id;
  448. pmac_id = soc->pdev_list[0]->lmac_id;
  449. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_PMAC_ID(tx_smmu, pmac_id);
  450. }
  451. #else
  452. static inline void
  453. dp_ipa_setup_tx_alt_params_pmac_id(struct dp_soc *soc,
  454. qdf_ipa_wdi_pipe_setup_info_t *tx)
  455. {
  456. }
  457. static inline void
  458. dp_ipa_setup_tx_alt_smmu_params_pmac_id(struct dp_soc *soc,
  459. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  460. {
  461. }
  462. static inline void
  463. dp_ipa_setup_tx_params_pmac_id(struct dp_soc *soc,
  464. qdf_ipa_wdi_pipe_setup_info_t *tx)
  465. {
  466. }
  467. static inline void
  468. dp_ipa_setup_tx_smmu_params_pmac_id(struct dp_soc *soc,
  469. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  470. {
  471. }
  472. #endif
  473. #ifdef IPA_WDI3_TX_TWO_PIPES
  474. static void dp_ipa_tx_alt_pool_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  475. {
  476. struct dp_ipa_resources *ipa_res;
  477. qdf_nbuf_t nbuf;
  478. int idx;
  479. for (idx = 0; idx < soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt; idx++) {
  480. nbuf = (qdf_nbuf_t)
  481. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[idx];
  482. if (!nbuf)
  483. continue;
  484. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_BIDIRECTIONAL);
  485. qdf_mem_dp_tx_skb_cnt_dec();
  486. qdf_mem_dp_tx_skb_dec(qdf_nbuf_get_end_offset(nbuf));
  487. qdf_nbuf_free(nbuf);
  488. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[idx] =
  489. (void *)NULL;
  490. }
  491. qdf_mem_free(soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned);
  492. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned = NULL;
  493. ipa_res = &pdev->ipa_resource;
  494. if (!ipa_res->is_db_ddr_mapped && ipa_res->tx_alt_comp_doorbell_vaddr)
  495. iounmap(ipa_res->tx_alt_comp_doorbell_vaddr);
  496. qdf_mem_free_sgtable(&ipa_res->tx_alt_ring.sgtable);
  497. qdf_mem_free_sgtable(&ipa_res->tx_alt_comp_ring.sgtable);
  498. }
  499. static int dp_ipa_tx_alt_pool_attach(struct dp_soc *soc)
  500. {
  501. uint32_t tx_buffer_count;
  502. uint32_t ring_base_align = 8;
  503. qdf_dma_addr_t buffer_paddr;
  504. struct hal_srng *wbm_srng = (struct hal_srng *)
  505. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  506. struct hal_srng_params srng_params;
  507. uint32_t wbm_bm_id;
  508. void *ring_entry;
  509. int num_entries;
  510. qdf_nbuf_t nbuf;
  511. int retval = QDF_STATUS_SUCCESS;
  512. int max_alloc_count = 0;
  513. /*
  514. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  515. * unsigned int uc_tx_buf_sz =
  516. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  517. */
  518. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  519. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  520. wbm_bm_id = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx,
  521. IPA_TX_ALT_RING_IDX);
  522. hal_get_srng_params(soc->hal_soc,
  523. hal_srng_to_hal_ring_handle(wbm_srng),
  524. &srng_params);
  525. num_entries = srng_params.num_entries;
  526. max_alloc_count =
  527. num_entries - DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES;
  528. if (max_alloc_count <= 0) {
  529. dp_err("incorrect value for buffer count %u", max_alloc_count);
  530. return -EINVAL;
  531. }
  532. dp_info("requested %d buffers to be posted to wbm ring",
  533. max_alloc_count);
  534. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned =
  535. qdf_mem_malloc(num_entries *
  536. sizeof(*soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned));
  537. if (!soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned) {
  538. dp_err("IPA WBM Ring Tx buf pool vaddr alloc fail");
  539. return -ENOMEM;
  540. }
  541. hal_srng_access_start_unlocked(soc->hal_soc,
  542. hal_srng_to_hal_ring_handle(wbm_srng));
  543. /*
  544. * Allocate Tx buffers as many as possible.
  545. * Leave DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES empty
  546. * Populate Tx buffers into WBM2IPA ring
  547. * This initial buffer population will simulate H/W as source ring,
  548. * and update HP
  549. */
  550. for (tx_buffer_count = 0;
  551. tx_buffer_count < max_alloc_count - 1; tx_buffer_count++) {
  552. nbuf = qdf_nbuf_frag_alloc(soc->osdev, alloc_size, 0,
  553. 256, FALSE);
  554. if (!nbuf)
  555. break;
  556. ring_entry = hal_srng_dst_get_next_hp(
  557. soc->hal_soc,
  558. hal_srng_to_hal_ring_handle(wbm_srng));
  559. if (!ring_entry) {
  560. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  561. "%s: Failed to get WBM ring entry",
  562. __func__);
  563. qdf_nbuf_free(nbuf);
  564. break;
  565. }
  566. qdf_nbuf_map_single(soc->osdev, nbuf,
  567. QDF_DMA_BIDIRECTIONAL);
  568. buffer_paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  569. qdf_mem_dp_tx_skb_cnt_inc();
  570. qdf_mem_dp_tx_skb_inc(qdf_nbuf_get_end_offset(nbuf));
  571. hal_rxdma_buff_addr_info_set(soc->hal_soc, ring_entry,
  572. buffer_paddr, 0, wbm_bm_id);
  573. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[
  574. tx_buffer_count] = (void *)nbuf;
  575. }
  576. hal_srng_access_end_unlocked(soc->hal_soc,
  577. hal_srng_to_hal_ring_handle(wbm_srng));
  578. soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt = tx_buffer_count;
  579. if (tx_buffer_count) {
  580. dp_info("IPA TX buffer pool2: %d allocated", tx_buffer_count);
  581. } else {
  582. dp_err("Failed to allocate IPA TX buffer pool2");
  583. qdf_mem_free(
  584. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned);
  585. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned = NULL;
  586. retval = -ENOMEM;
  587. }
  588. return retval;
  589. }
  590. static QDF_STATUS dp_ipa_tx_alt_ring_get_resource(struct dp_pdev *pdev)
  591. {
  592. struct dp_soc *soc = pdev->soc;
  593. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  594. ipa_res->tx_alt_ring_num_alloc_buffer =
  595. (uint32_t)soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt;
  596. dp_ipa_get_shared_mem_info(
  597. soc->osdev, &ipa_res->tx_alt_ring,
  598. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr,
  599. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr,
  600. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size);
  601. dp_ipa_get_shared_mem_info(
  602. soc->osdev, &ipa_res->tx_alt_comp_ring,
  603. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr,
  604. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr,
  605. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size);
  606. if (!qdf_mem_get_dma_addr(soc->osdev,
  607. &ipa_res->tx_alt_comp_ring.mem_info))
  608. return QDF_STATUS_E_FAILURE;
  609. return QDF_STATUS_SUCCESS;
  610. }
  611. static void dp_ipa_tx_alt_ring_resource_setup(struct dp_soc *soc)
  612. {
  613. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  614. struct hal_srng *hal_srng;
  615. struct hal_srng_params srng_params;
  616. unsigned long addr_offset, dev_base_paddr;
  617. /* IPA TCL_DATA Alternative Ring - HAL_SRNG_SW2TCL2 */
  618. hal_srng = (struct hal_srng *)
  619. soc->tcl_data_ring[IPA_TX_ALT_RING_IDX].hal_srng;
  620. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  621. hal_srng_to_hal_ring_handle(hal_srng),
  622. &srng_params);
  623. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr =
  624. srng_params.ring_base_paddr;
  625. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr =
  626. srng_params.ring_base_vaddr;
  627. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size =
  628. (srng_params.num_entries * srng_params.entry_size) << 2;
  629. /*
  630. * For the register backed memory addresses, use the scn->mem_pa to
  631. * calculate the physical address of the shadow registers
  632. */
  633. dev_base_paddr =
  634. (unsigned long)
  635. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  636. addr_offset = (unsigned long)(hal_srng->u.src_ring.hp_addr) -
  637. (unsigned long)(hal_soc->dev_base_addr);
  638. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr =
  639. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  640. dp_info("IPA TCL_DATA Alt Ring addr_offset=%x, dev_base_paddr=%x, hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  641. (unsigned int)addr_offset,
  642. (unsigned int)dev_base_paddr,
  643. (unsigned int)(soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr),
  644. (void *)soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr,
  645. (void *)soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr,
  646. srng_params.num_entries,
  647. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size);
  648. /* IPA TX Alternative COMP Ring - HAL_SRNG_WBM2SW4_RELEASE */
  649. hal_srng = (struct hal_srng *)
  650. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  651. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  652. hal_srng_to_hal_ring_handle(hal_srng),
  653. &srng_params);
  654. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr =
  655. srng_params.ring_base_paddr;
  656. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr =
  657. srng_params.ring_base_vaddr;
  658. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size =
  659. (srng_params.num_entries * srng_params.entry_size) << 2;
  660. soc->ipa_uc_tx_rsc_alt.ipa_wbm_hp_shadow_paddr =
  661. hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  662. hal_srng_to_hal_ring_handle(hal_srng));
  663. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  664. (unsigned long)(hal_soc->dev_base_addr);
  665. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr =
  666. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  667. dp_info("IPA TX Alt COMP Ring addr_offset=%x, dev_base_paddr=%x, ipa_wbm_tp_paddr=%x paddr=%pK vaddr=0%pK size= %u(%u bytes)",
  668. (unsigned int)addr_offset,
  669. (unsigned int)dev_base_paddr,
  670. (unsigned int)(soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr),
  671. (void *)soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr,
  672. (void *)soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr,
  673. srng_params.num_entries,
  674. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size);
  675. }
  676. static void dp_ipa_map_ring_doorbell_paddr(struct dp_pdev *pdev)
  677. {
  678. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  679. uint32_t rx_ready_doorbell_dmaaddr;
  680. uint32_t tx_comp_doorbell_dmaaddr;
  681. struct dp_soc *soc = pdev->soc;
  682. int ret = 0;
  683. if (ipa_res->is_db_ddr_mapped)
  684. ipa_res->tx_comp_doorbell_vaddr =
  685. phys_to_virt(ipa_res->tx_comp_doorbell_paddr);
  686. else
  687. ipa_res->tx_comp_doorbell_vaddr =
  688. ioremap(ipa_res->tx_comp_doorbell_paddr, 4);
  689. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  690. ret = pld_smmu_map(soc->osdev->dev,
  691. ipa_res->tx_comp_doorbell_paddr,
  692. &tx_comp_doorbell_dmaaddr,
  693. sizeof(uint32_t));
  694. ipa_res->tx_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  695. qdf_assert_always(!ret);
  696. ret = pld_smmu_map(soc->osdev->dev,
  697. ipa_res->rx_ready_doorbell_paddr,
  698. &rx_ready_doorbell_dmaaddr,
  699. sizeof(uint32_t));
  700. ipa_res->rx_ready_doorbell_paddr = rx_ready_doorbell_dmaaddr;
  701. qdf_assert_always(!ret);
  702. }
  703. /* Setup for alternative TX pipe */
  704. if (!ipa_res->tx_alt_comp_doorbell_paddr)
  705. return;
  706. if (ipa_res->is_db_ddr_mapped)
  707. ipa_res->tx_alt_comp_doorbell_vaddr =
  708. phys_to_virt(ipa_res->tx_alt_comp_doorbell_paddr);
  709. else
  710. ipa_res->tx_alt_comp_doorbell_vaddr =
  711. ioremap(ipa_res->tx_alt_comp_doorbell_paddr, 4);
  712. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  713. ret = pld_smmu_map(soc->osdev->dev,
  714. ipa_res->tx_alt_comp_doorbell_paddr,
  715. &tx_comp_doorbell_dmaaddr,
  716. sizeof(uint32_t));
  717. ipa_res->tx_alt_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  718. qdf_assert_always(!ret);
  719. }
  720. }
  721. static void dp_ipa_unmap_ring_doorbell_paddr(struct dp_pdev *pdev)
  722. {
  723. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  724. struct dp_soc *soc = pdev->soc;
  725. int ret = 0;
  726. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  727. return;
  728. /* Unmap must be in reverse order of map */
  729. if (ipa_res->tx_alt_comp_doorbell_paddr) {
  730. ret = pld_smmu_unmap(soc->osdev->dev,
  731. ipa_res->tx_alt_comp_doorbell_paddr,
  732. sizeof(uint32_t));
  733. qdf_assert_always(!ret);
  734. }
  735. ret = pld_smmu_unmap(soc->osdev->dev,
  736. ipa_res->rx_ready_doorbell_paddr,
  737. sizeof(uint32_t));
  738. qdf_assert_always(!ret);
  739. ret = pld_smmu_unmap(soc->osdev->dev,
  740. ipa_res->tx_comp_doorbell_paddr,
  741. sizeof(uint32_t));
  742. qdf_assert_always(!ret);
  743. }
  744. static QDF_STATUS dp_ipa_tx_alt_buf_smmu_mapping(struct dp_soc *soc,
  745. struct dp_pdev *pdev,
  746. bool create, const char *func,
  747. uint32_t line)
  748. {
  749. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  750. struct ipa_dp_tx_rsc *rsc;
  751. uint32_t tx_buffer_cnt;
  752. uint32_t buf_len;
  753. qdf_nbuf_t nbuf;
  754. uint32_t index;
  755. if (!ipa_is_ready()) {
  756. dp_info("IPA is not READY");
  757. return QDF_STATUS_SUCCESS;
  758. }
  759. rsc = &soc->ipa_uc_tx_rsc_alt;
  760. tx_buffer_cnt = rsc->alloc_tx_buf_cnt;
  761. for (index = 0; index < tx_buffer_cnt; index++) {
  762. nbuf = (qdf_nbuf_t)rsc->tx_buf_pool_vaddr_unaligned[index];
  763. if (!nbuf)
  764. continue;
  765. buf_len = qdf_nbuf_get_data_len(nbuf);
  766. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, buf_len,
  767. create, func, line);
  768. }
  769. return ret;
  770. }
  771. static void dp_ipa_wdi_tx_alt_pipe_params(struct dp_soc *soc,
  772. struct dp_ipa_resources *ipa_res,
  773. qdf_ipa_wdi_pipe_setup_info_t *tx)
  774. {
  775. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN2_CONS1;
  776. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  777. qdf_mem_get_dma_addr(soc->osdev,
  778. &ipa_res->tx_alt_comp_ring.mem_info);
  779. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  780. qdf_mem_get_dma_size(soc->osdev,
  781. &ipa_res->tx_alt_comp_ring.mem_info);
  782. /* WBM Tail Pointer Address */
  783. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  784. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr;
  785. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(tx) = true;
  786. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  787. qdf_mem_get_dma_addr(soc->osdev,
  788. &ipa_res->tx_alt_ring.mem_info);
  789. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) =
  790. qdf_mem_get_dma_size(soc->osdev,
  791. &ipa_res->tx_alt_ring.mem_info);
  792. /* TCL Head Pointer Address */
  793. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  794. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr;
  795. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(tx) = true;
  796. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  797. ipa_res->tx_alt_ring_num_alloc_buffer;
  798. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  799. dp_ipa_setup_tx_params_bank_id(soc, tx);
  800. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  801. dp_ipa_setup_tx_alt_params_pmac_id(soc, tx);
  802. }
  803. static void
  804. dp_ipa_wdi_tx_alt_pipe_smmu_params(struct dp_soc *soc,
  805. struct dp_ipa_resources *ipa_res,
  806. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  807. {
  808. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) = IPA_CLIENT_WLAN2_CONS1;
  809. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(tx_smmu),
  810. &ipa_res->tx_alt_comp_ring.sgtable,
  811. sizeof(sgtable_t));
  812. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(tx_smmu) =
  813. qdf_mem_get_dma_size(soc->osdev,
  814. &ipa_res->tx_alt_comp_ring.mem_info);
  815. /* WBM Tail Pointer Address */
  816. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(tx_smmu) =
  817. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr;
  818. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(tx_smmu) = true;
  819. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(tx_smmu),
  820. &ipa_res->tx_alt_ring.sgtable,
  821. sizeof(sgtable_t));
  822. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(tx_smmu) =
  823. qdf_mem_get_dma_size(soc->osdev,
  824. &ipa_res->tx_alt_ring.mem_info);
  825. /* TCL Head Pointer Address */
  826. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(tx_smmu) =
  827. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr;
  828. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(tx_smmu) = true;
  829. QDF_IPA_WDI_SETUP_INFO_SMMU_NUM_PKT_BUFFERS(tx_smmu) =
  830. ipa_res->tx_alt_ring_num_alloc_buffer;
  831. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(tx_smmu) = 0;
  832. dp_ipa_setup_tx_smmu_params_bank_id(soc, tx_smmu);
  833. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  834. dp_ipa_setup_tx_alt_smmu_params_pmac_id(soc, tx_smmu);
  835. }
  836. static void dp_ipa_setup_tx_alt_pipe(struct dp_soc *soc,
  837. struct dp_ipa_resources *res,
  838. qdf_ipa_wdi_conn_in_params_t *in)
  839. {
  840. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu = NULL;
  841. qdf_ipa_wdi_pipe_setup_info_t *tx = NULL;
  842. qdf_ipa_ep_cfg_t *tx_cfg;
  843. QDF_IPA_WDI_CONN_IN_PARAMS_IS_TX1_USED(in) = true;
  844. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  845. tx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_ALT_PIPE_SMMU(in);
  846. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx_smmu);
  847. dp_ipa_wdi_tx_alt_pipe_smmu_params(soc, res, tx_smmu);
  848. } else {
  849. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_ALT_PIPE(in);
  850. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx);
  851. dp_ipa_wdi_tx_alt_pipe_params(soc, res, tx);
  852. }
  853. QDF_IPA_EP_CFG_NAT_EN(tx_cfg) = IPA_BYPASS_NAT;
  854. QDF_IPA_EP_CFG_HDR_LEN(tx_cfg) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  855. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(tx_cfg) = 0;
  856. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(tx_cfg) = 0;
  857. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(tx_cfg) = 0;
  858. QDF_IPA_EP_CFG_MODE(tx_cfg) = IPA_BASIC;
  859. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(tx_cfg) = true;
  860. }
  861. static void dp_ipa_set_pipe_db(struct dp_ipa_resources *res,
  862. qdf_ipa_wdi_conn_out_params_t *out)
  863. {
  864. res->tx_comp_doorbell_paddr =
  865. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(out);
  866. res->rx_ready_doorbell_paddr =
  867. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(out);
  868. res->tx_alt_comp_doorbell_paddr =
  869. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_ALT_DB_PA(out);
  870. }
  871. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  872. uint8_t session_id)
  873. {
  874. bool is_2g_iface = session_id & IPA_SESSION_ID_SHIFT;
  875. session_id = session_id >> IPA_SESSION_ID_SHIFT;
  876. dp_debug("session_id %u is_2g_iface %d", session_id, is_2g_iface);
  877. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id << 16);
  878. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_TX1_USED(in) = is_2g_iface;
  879. }
  880. static void dp_ipa_tx_comp_ring_init_hp(struct dp_soc *soc,
  881. struct dp_ipa_resources *res)
  882. {
  883. struct hal_srng *wbm_srng;
  884. /* Init first TX comp ring */
  885. wbm_srng = (struct hal_srng *)
  886. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  887. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  888. res->tx_comp_doorbell_vaddr);
  889. /* Init the alternate TX comp ring */
  890. if (!res->tx_alt_comp_doorbell_paddr)
  891. return;
  892. wbm_srng = (struct hal_srng *)
  893. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  894. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  895. res->tx_alt_comp_doorbell_vaddr);
  896. }
  897. static void dp_ipa_set_tx_doorbell_paddr(struct dp_soc *soc,
  898. struct dp_ipa_resources *ipa_res)
  899. {
  900. struct hal_srng *wbm_srng;
  901. wbm_srng = (struct hal_srng *)
  902. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  903. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  904. ipa_res->tx_comp_doorbell_paddr);
  905. dp_info("paddr %pK vaddr %pK",
  906. (void *)ipa_res->tx_comp_doorbell_paddr,
  907. (void *)ipa_res->tx_comp_doorbell_vaddr);
  908. /* Setup for alternative TX comp ring */
  909. if (!ipa_res->tx_alt_comp_doorbell_paddr)
  910. return;
  911. wbm_srng = (struct hal_srng *)
  912. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  913. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  914. ipa_res->tx_alt_comp_doorbell_paddr);
  915. dp_info("paddr %pK vaddr %pK",
  916. (void *)ipa_res->tx_alt_comp_doorbell_paddr,
  917. (void *)ipa_res->tx_alt_comp_doorbell_vaddr);
  918. }
  919. #ifdef IPA_SET_RESET_TX_DB_PA
  920. static QDF_STATUS dp_ipa_reset_tx_doorbell_pa(struct dp_soc *soc,
  921. struct dp_ipa_resources *ipa_res)
  922. {
  923. hal_ring_handle_t wbm_srng;
  924. qdf_dma_addr_t hp_addr;
  925. wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  926. if (!wbm_srng)
  927. return QDF_STATUS_E_FAILURE;
  928. hp_addr = soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr;
  929. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  930. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  931. /* Reset alternative TX comp ring */
  932. wbm_srng = soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  933. if (!wbm_srng)
  934. return QDF_STATUS_E_FAILURE;
  935. hp_addr = soc->ipa_uc_tx_rsc_alt.ipa_wbm_hp_shadow_paddr;
  936. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  937. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  938. return QDF_STATUS_SUCCESS;
  939. }
  940. #endif /* IPA_SET_RESET_TX_DB_PA */
  941. #else /* !IPA_WDI3_TX_TWO_PIPES */
  942. static inline
  943. void dp_ipa_tx_alt_pool_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  944. {
  945. }
  946. static inline void dp_ipa_tx_alt_ring_resource_setup(struct dp_soc *soc)
  947. {
  948. }
  949. static inline int dp_ipa_tx_alt_pool_attach(struct dp_soc *soc)
  950. {
  951. return 0;
  952. }
  953. static inline QDF_STATUS dp_ipa_tx_alt_ring_get_resource(struct dp_pdev *pdev)
  954. {
  955. return QDF_STATUS_SUCCESS;
  956. }
  957. static void dp_ipa_map_ring_doorbell_paddr(struct dp_pdev *pdev)
  958. {
  959. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  960. uint32_t rx_ready_doorbell_dmaaddr;
  961. uint32_t tx_comp_doorbell_dmaaddr;
  962. struct dp_soc *soc = pdev->soc;
  963. int ret = 0;
  964. if (ipa_res->is_db_ddr_mapped)
  965. ipa_res->tx_comp_doorbell_vaddr =
  966. phys_to_virt(ipa_res->tx_comp_doorbell_paddr);
  967. else
  968. ipa_res->tx_comp_doorbell_vaddr =
  969. ioremap(ipa_res->tx_comp_doorbell_paddr, 4);
  970. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  971. ret = pld_smmu_map(soc->osdev->dev,
  972. ipa_res->tx_comp_doorbell_paddr,
  973. &tx_comp_doorbell_dmaaddr,
  974. sizeof(uint32_t));
  975. ipa_res->tx_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  976. qdf_assert_always(!ret);
  977. ret = pld_smmu_map(soc->osdev->dev,
  978. ipa_res->rx_ready_doorbell_paddr,
  979. &rx_ready_doorbell_dmaaddr,
  980. sizeof(uint32_t));
  981. ipa_res->rx_ready_doorbell_paddr = rx_ready_doorbell_dmaaddr;
  982. qdf_assert_always(!ret);
  983. }
  984. }
  985. static inline void dp_ipa_unmap_ring_doorbell_paddr(struct dp_pdev *pdev)
  986. {
  987. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  988. struct dp_soc *soc = pdev->soc;
  989. int ret = 0;
  990. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  991. return;
  992. ret = pld_smmu_unmap(soc->osdev->dev,
  993. ipa_res->rx_ready_doorbell_paddr,
  994. sizeof(uint32_t));
  995. qdf_assert_always(!ret);
  996. ret = pld_smmu_unmap(soc->osdev->dev,
  997. ipa_res->tx_comp_doorbell_paddr,
  998. sizeof(uint32_t));
  999. qdf_assert_always(!ret);
  1000. }
  1001. static inline QDF_STATUS dp_ipa_tx_alt_buf_smmu_mapping(struct dp_soc *soc,
  1002. struct dp_pdev *pdev,
  1003. bool create,
  1004. const char *func,
  1005. uint32_t line)
  1006. {
  1007. return QDF_STATUS_SUCCESS;
  1008. }
  1009. static inline
  1010. void dp_ipa_setup_tx_alt_pipe(struct dp_soc *soc, struct dp_ipa_resources *res,
  1011. qdf_ipa_wdi_conn_in_params_t *in)
  1012. {
  1013. }
  1014. static void dp_ipa_set_pipe_db(struct dp_ipa_resources *res,
  1015. qdf_ipa_wdi_conn_out_params_t *out)
  1016. {
  1017. res->tx_comp_doorbell_paddr =
  1018. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(out);
  1019. res->rx_ready_doorbell_paddr =
  1020. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(out);
  1021. }
  1022. #ifdef IPA_WDS_EASYMESH_FEATURE
  1023. /**
  1024. * dp_ipa_setup_iface_session_id() - Pass vdev id to IPA
  1025. * @in: ipa in params
  1026. * @session_id: vdev id
  1027. *
  1028. * Pass Vdev id to IPA, IPA metadata order is changed and vdev id
  1029. * is stored at higher nibble so, no shift is required.
  1030. *
  1031. * Return: none
  1032. */
  1033. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  1034. uint8_t session_id)
  1035. {
  1036. if (ucfg_ipa_is_wds_enabled())
  1037. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id);
  1038. else
  1039. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id << 16);
  1040. }
  1041. #else
  1042. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  1043. uint8_t session_id)
  1044. {
  1045. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id << 16);
  1046. }
  1047. #endif
  1048. static inline void dp_ipa_tx_comp_ring_init_hp(struct dp_soc *soc,
  1049. struct dp_ipa_resources *res)
  1050. {
  1051. struct hal_srng *wbm_srng = (struct hal_srng *)
  1052. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1053. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  1054. res->tx_comp_doorbell_vaddr);
  1055. }
  1056. static void dp_ipa_set_tx_doorbell_paddr(struct dp_soc *soc,
  1057. struct dp_ipa_resources *ipa_res)
  1058. {
  1059. struct hal_srng *wbm_srng = (struct hal_srng *)
  1060. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1061. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  1062. ipa_res->tx_comp_doorbell_paddr);
  1063. dp_info("paddr %pK vaddr %pK",
  1064. (void *)ipa_res->tx_comp_doorbell_paddr,
  1065. (void *)ipa_res->tx_comp_doorbell_vaddr);
  1066. }
  1067. #ifdef IPA_SET_RESET_TX_DB_PA
  1068. static QDF_STATUS dp_ipa_reset_tx_doorbell_pa(struct dp_soc *soc,
  1069. struct dp_ipa_resources *ipa_res)
  1070. {
  1071. hal_ring_handle_t wbm_srng =
  1072. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1073. qdf_dma_addr_t hp_addr;
  1074. if (!wbm_srng)
  1075. return QDF_STATUS_E_FAILURE;
  1076. hp_addr = soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr;
  1077. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  1078. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  1079. return QDF_STATUS_SUCCESS;
  1080. }
  1081. #endif /* IPA_SET_RESET_TX_DB_PA */
  1082. #endif /* IPA_WDI3_TX_TWO_PIPES */
  1083. /**
  1084. * dp_tx_ipa_uc_detach() - Free autonomy TX resources
  1085. * @soc: data path instance
  1086. * @pdev: core txrx pdev context
  1087. *
  1088. * Free allocated TX buffers with WBM SRNG
  1089. *
  1090. * Return: none
  1091. */
  1092. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1093. {
  1094. int idx;
  1095. qdf_nbuf_t nbuf;
  1096. struct dp_ipa_resources *ipa_res;
  1097. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  1098. nbuf = (qdf_nbuf_t)
  1099. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx];
  1100. if (!nbuf)
  1101. continue;
  1102. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_BIDIRECTIONAL);
  1103. qdf_mem_dp_tx_skb_cnt_dec();
  1104. qdf_mem_dp_tx_skb_dec(qdf_nbuf_get_end_offset(nbuf));
  1105. qdf_nbuf_free(nbuf);
  1106. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx] =
  1107. (void *)NULL;
  1108. }
  1109. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  1110. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  1111. ipa_res = &pdev->ipa_resource;
  1112. qdf_mem_free_sgtable(&ipa_res->tx_ring.sgtable);
  1113. qdf_mem_free_sgtable(&ipa_res->tx_comp_ring.sgtable);
  1114. }
  1115. /**
  1116. * dp_rx_ipa_uc_detach() - free autonomy RX resources
  1117. * @soc: data path instance
  1118. * @pdev: core txrx pdev context
  1119. *
  1120. * This function will detach DP RX into main device context
  1121. * will free DP Rx resources.
  1122. *
  1123. * Return: none
  1124. */
  1125. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1126. {
  1127. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1128. qdf_mem_free_sgtable(&ipa_res->rx_rdy_ring.sgtable);
  1129. qdf_mem_free_sgtable(&ipa_res->rx_refill_ring.sgtable);
  1130. }
  1131. /**
  1132. * dp_rx_alt_ipa_uc_detach() - free autonomy RX resources
  1133. * @soc: data path instance
  1134. * @pdev: core txrx pdev context
  1135. *
  1136. * This function will detach DP RX into main device context
  1137. * will free DP Rx resources.
  1138. *
  1139. * Return: none
  1140. */
  1141. #ifdef IPA_WDI3_VLAN_SUPPORT
  1142. static void dp_rx_alt_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1143. {
  1144. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1145. if (!wlan_ipa_is_vlan_enabled())
  1146. return;
  1147. qdf_mem_free_sgtable(&ipa_res->rx_alt_rdy_ring.sgtable);
  1148. qdf_mem_free_sgtable(&ipa_res->rx_alt_refill_ring.sgtable);
  1149. }
  1150. #else
  1151. static inline
  1152. void dp_rx_alt_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1153. { }
  1154. #endif
  1155. /**
  1156. * dp_ipa_opt_wifi_dp_cleanup() - Cleanup ipa opt wifi dp filter setup
  1157. * @soc: data path instance
  1158. * @pdev: core txrx pdev context
  1159. *
  1160. * This function will cleanup filter setup for optional wifi dp.
  1161. *
  1162. * Return: none
  1163. */
  1164. #ifdef IPA_OPT_WIFI_DP
  1165. static void dp_ipa_opt_wifi_dp_cleanup(struct dp_soc *soc, struct dp_pdev *pdev)
  1166. {
  1167. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1168. struct hif_softc *hif = (struct hif_softc *)(hal_soc->hif_handle);
  1169. int count = qdf_atomic_read(&hif->opt_wifi_dp_rtpm_cnt);
  1170. int i;
  1171. for (i = count; i > 0; i--) {
  1172. dp_info("opt_dp: cleanup call pcie link down");
  1173. dp_ipa_pcie_link_down((struct cdp_soc_t *)soc);
  1174. }
  1175. }
  1176. #else
  1177. static inline
  1178. void dp_ipa_opt_wifi_dp_cleanup(struct dp_soc *soc, struct dp_pdev *pdev)
  1179. {
  1180. }
  1181. #endif
  1182. int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1183. {
  1184. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1185. return QDF_STATUS_SUCCESS;
  1186. /* TX resource detach */
  1187. dp_tx_ipa_uc_detach(soc, pdev);
  1188. /* Cleanup 2nd TX pipe resources */
  1189. dp_ipa_tx_alt_pool_detach(soc, pdev);
  1190. /* RX resource detach */
  1191. dp_rx_ipa_uc_detach(soc, pdev);
  1192. /* Cleanup 2nd RX pipe resources */
  1193. dp_rx_alt_ipa_uc_detach(soc, pdev);
  1194. dp_ipa_opt_wifi_dp_cleanup(soc, pdev);
  1195. return QDF_STATUS_SUCCESS; /* success */
  1196. }
  1197. /**
  1198. * dp_tx_ipa_uc_attach() - Allocate autonomy TX resources
  1199. * @soc: data path instance
  1200. * @pdev: Physical device handle
  1201. *
  1202. * Allocate TX buffer from non-cacheable memory
  1203. * Attach allocated TX buffers with WBM SRNG
  1204. *
  1205. * Return: int
  1206. */
  1207. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1208. {
  1209. uint32_t tx_buffer_count;
  1210. uint32_t ring_base_align = 8;
  1211. qdf_dma_addr_t buffer_paddr;
  1212. struct hal_srng *wbm_srng = (struct hal_srng *)
  1213. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1214. struct hal_srng_params srng_params;
  1215. void *ring_entry;
  1216. int num_entries;
  1217. qdf_nbuf_t nbuf;
  1218. int retval = QDF_STATUS_SUCCESS;
  1219. int max_alloc_count = 0;
  1220. uint32_t wbm_bm_id;
  1221. /*
  1222. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  1223. * unsigned int uc_tx_buf_sz =
  1224. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  1225. */
  1226. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  1227. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  1228. wbm_bm_id = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx,
  1229. IPA_TCL_DATA_RING_IDX);
  1230. hal_get_srng_params(soc->hal_soc, hal_srng_to_hal_ring_handle(wbm_srng),
  1231. &srng_params);
  1232. num_entries = srng_params.num_entries;
  1233. max_alloc_count =
  1234. num_entries - DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES;
  1235. if (max_alloc_count <= 0) {
  1236. dp_err("incorrect value for buffer count %u", max_alloc_count);
  1237. return -EINVAL;
  1238. }
  1239. dp_info("requested %d buffers to be posted to wbm ring",
  1240. max_alloc_count);
  1241. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned =
  1242. qdf_mem_malloc(num_entries *
  1243. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned));
  1244. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned) {
  1245. dp_err("IPA WBM Ring Tx buf pool vaddr alloc fail");
  1246. return -ENOMEM;
  1247. }
  1248. hal_srng_access_start_unlocked(soc->hal_soc,
  1249. hal_srng_to_hal_ring_handle(wbm_srng));
  1250. /*
  1251. * Allocate Tx buffers as many as possible.
  1252. * Leave DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES empty
  1253. * Populate Tx buffers into WBM2IPA ring
  1254. * This initial buffer population will simulate H/W as source ring,
  1255. * and update HP
  1256. */
  1257. for (tx_buffer_count = 0;
  1258. tx_buffer_count < max_alloc_count - 1; tx_buffer_count++) {
  1259. nbuf = qdf_nbuf_frag_alloc(soc->osdev, alloc_size, 0,
  1260. 256, FALSE);
  1261. if (!nbuf)
  1262. break;
  1263. ring_entry = hal_srng_dst_get_next_hp(soc->hal_soc,
  1264. hal_srng_to_hal_ring_handle(wbm_srng));
  1265. if (!ring_entry) {
  1266. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1267. "%s: Failed to get WBM ring entry",
  1268. __func__);
  1269. qdf_nbuf_free(nbuf);
  1270. break;
  1271. }
  1272. qdf_nbuf_map_single(soc->osdev, nbuf,
  1273. QDF_DMA_BIDIRECTIONAL);
  1274. buffer_paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1275. qdf_mem_dp_tx_skb_cnt_inc();
  1276. qdf_mem_dp_tx_skb_inc(qdf_nbuf_get_end_offset(nbuf));
  1277. /*
  1278. * TODO - KIWI code can directly call the be handler
  1279. * instead of hal soc ops.
  1280. */
  1281. hal_rxdma_buff_addr_info_set(soc->hal_soc, ring_entry,
  1282. buffer_paddr, 0, wbm_bm_id);
  1283. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[tx_buffer_count]
  1284. = (void *)nbuf;
  1285. }
  1286. hal_srng_access_end_unlocked(soc->hal_soc,
  1287. hal_srng_to_hal_ring_handle(wbm_srng));
  1288. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  1289. if (tx_buffer_count) {
  1290. dp_info("IPA WDI TX buffer: %d allocated", tx_buffer_count);
  1291. } else {
  1292. dp_err("No IPA WDI TX buffer allocated!");
  1293. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  1294. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  1295. retval = -ENOMEM;
  1296. }
  1297. return retval;
  1298. }
  1299. /**
  1300. * dp_rx_ipa_uc_attach() - Allocate autonomy RX resources
  1301. * @soc: data path instance
  1302. * @pdev: core txrx pdev context
  1303. *
  1304. * This function will attach a DP RX instance into the main
  1305. * device (SOC) context.
  1306. *
  1307. * Return: QDF_STATUS_SUCCESS: success
  1308. * QDF_STATUS_E_RESOURCES: Error return
  1309. */
  1310. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1311. {
  1312. return QDF_STATUS_SUCCESS;
  1313. }
  1314. int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1315. {
  1316. int error;
  1317. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1318. return QDF_STATUS_SUCCESS;
  1319. /* TX resource attach */
  1320. error = dp_tx_ipa_uc_attach(soc, pdev);
  1321. if (error) {
  1322. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1323. "%s: DP IPA UC TX attach fail code %d",
  1324. __func__, error);
  1325. return error;
  1326. }
  1327. /* Setup 2nd TX pipe */
  1328. error = dp_ipa_tx_alt_pool_attach(soc);
  1329. if (error) {
  1330. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1331. "%s: DP IPA TX pool2 attach fail code %d",
  1332. __func__, error);
  1333. dp_tx_ipa_uc_detach(soc, pdev);
  1334. return error;
  1335. }
  1336. /* RX resource attach */
  1337. error = dp_rx_ipa_uc_attach(soc, pdev);
  1338. if (error) {
  1339. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1340. "%s: DP IPA UC RX attach fail code %d",
  1341. __func__, error);
  1342. dp_ipa_tx_alt_pool_detach(soc, pdev);
  1343. dp_tx_ipa_uc_detach(soc, pdev);
  1344. return error;
  1345. }
  1346. return QDF_STATUS_SUCCESS; /* success */
  1347. }
  1348. #ifdef IPA_WDI3_VLAN_SUPPORT
  1349. /**
  1350. * dp_ipa_rx_alt_ring_resource_setup() - setup IPA 2nd RX ring resources
  1351. * @soc: data path SoC handle
  1352. * @pdev: data path pdev handle
  1353. *
  1354. * Return: none
  1355. */
  1356. static
  1357. void dp_ipa_rx_alt_ring_resource_setup(struct dp_soc *soc, struct dp_pdev *pdev)
  1358. {
  1359. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1360. struct hal_srng *hal_srng;
  1361. struct hal_srng_params srng_params;
  1362. unsigned long addr_offset, dev_base_paddr;
  1363. qdf_dma_addr_t hp_addr;
  1364. if (!wlan_ipa_is_vlan_enabled())
  1365. return;
  1366. dev_base_paddr =
  1367. (unsigned long)
  1368. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  1369. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW3 */
  1370. hal_srng = (struct hal_srng *)
  1371. soc->reo_dest_ring[IPA_ALT_REO_DEST_RING_IDX].hal_srng;
  1372. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1373. hal_srng_to_hal_ring_handle(hal_srng),
  1374. &srng_params);
  1375. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr =
  1376. srng_params.ring_base_paddr;
  1377. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr =
  1378. srng_params.ring_base_vaddr;
  1379. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size =
  1380. (srng_params.num_entries * srng_params.entry_size) << 2;
  1381. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1382. (unsigned long)(hal_soc->dev_base_addr);
  1383. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr =
  1384. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1385. dp_info("IPA REO_DEST Ring addr_offset=%x, dev_base_paddr=%x, tp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1386. (unsigned int)addr_offset,
  1387. (unsigned int)dev_base_paddr,
  1388. (unsigned int)(soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr),
  1389. (void *)soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr,
  1390. (void *)soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr,
  1391. srng_params.num_entries,
  1392. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size);
  1393. hal_srng = (struct hal_srng *)
  1394. pdev->rx_refill_buf_ring3.hal_srng;
  1395. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1396. hal_srng_to_hal_ring_handle(hal_srng),
  1397. &srng_params);
  1398. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr =
  1399. srng_params.ring_base_paddr;
  1400. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr =
  1401. srng_params.ring_base_vaddr;
  1402. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size =
  1403. (srng_params.num_entries * srng_params.entry_size) << 2;
  1404. hp_addr = hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1405. hal_srng_to_hal_ring_handle(hal_srng));
  1406. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr =
  1407. qdf_mem_paddr_from_dmaaddr(soc->osdev, hp_addr);
  1408. dp_info("IPA REFILL_BUF Ring hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1409. (unsigned int)(soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr),
  1410. (void *)soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr,
  1411. (void *)soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr,
  1412. srng_params.num_entries,
  1413. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size);
  1414. }
  1415. #else
  1416. static inline
  1417. void dp_ipa_rx_alt_ring_resource_setup(struct dp_soc *soc, struct dp_pdev *pdev)
  1418. { }
  1419. #endif
  1420. int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1421. struct dp_pdev *pdev)
  1422. {
  1423. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1424. struct hal_srng *hal_srng;
  1425. struct hal_srng_params srng_params;
  1426. qdf_dma_addr_t hp_addr;
  1427. unsigned long addr_offset, dev_base_paddr;
  1428. uint32_t ix0;
  1429. uint8_t ix0_map[8];
  1430. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1431. return QDF_STATUS_SUCCESS;
  1432. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL3 */
  1433. hal_srng = (struct hal_srng *)
  1434. soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  1435. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1436. hal_srng_to_hal_ring_handle(hal_srng),
  1437. &srng_params);
  1438. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  1439. srng_params.ring_base_paddr;
  1440. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  1441. srng_params.ring_base_vaddr;
  1442. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  1443. (srng_params.num_entries * srng_params.entry_size) << 2;
  1444. /*
  1445. * For the register backed memory addresses, use the scn->mem_pa to
  1446. * calculate the physical address of the shadow registers
  1447. */
  1448. dev_base_paddr =
  1449. (unsigned long)
  1450. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  1451. addr_offset = (unsigned long)(hal_srng->u.src_ring.hp_addr) -
  1452. (unsigned long)(hal_soc->dev_base_addr);
  1453. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr =
  1454. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1455. dp_info("IPA TCL_DATA Ring addr_offset=%x, dev_base_paddr=%x, hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1456. (unsigned int)addr_offset,
  1457. (unsigned int)dev_base_paddr,
  1458. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr),
  1459. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  1460. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  1461. srng_params.num_entries,
  1462. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  1463. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW2_RELEASE */
  1464. hal_srng = (struct hal_srng *)
  1465. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1466. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1467. hal_srng_to_hal_ring_handle(hal_srng),
  1468. &srng_params);
  1469. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  1470. srng_params.ring_base_paddr;
  1471. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  1472. srng_params.ring_base_vaddr;
  1473. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  1474. (srng_params.num_entries * srng_params.entry_size) << 2;
  1475. soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr =
  1476. hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1477. hal_srng_to_hal_ring_handle(hal_srng));
  1478. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1479. (unsigned long)(hal_soc->dev_base_addr);
  1480. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr =
  1481. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1482. dp_info("IPA TX COMP Ring addr_offset=%x, dev_base_paddr=%x, ipa_wbm_tp_paddr=%x paddr=%pK vaddr=0%pK size= %u(%u bytes)",
  1483. (unsigned int)addr_offset,
  1484. (unsigned int)dev_base_paddr,
  1485. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr),
  1486. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  1487. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  1488. srng_params.num_entries,
  1489. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  1490. dp_ipa_tx_alt_ring_resource_setup(soc);
  1491. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  1492. hal_srng = (struct hal_srng *)
  1493. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1494. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1495. hal_srng_to_hal_ring_handle(hal_srng),
  1496. &srng_params);
  1497. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  1498. srng_params.ring_base_paddr;
  1499. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  1500. srng_params.ring_base_vaddr;
  1501. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  1502. (srng_params.num_entries * srng_params.entry_size) << 2;
  1503. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1504. (unsigned long)(hal_soc->dev_base_addr);
  1505. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr =
  1506. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1507. dp_info("IPA REO_DEST Ring addr_offset=%x, dev_base_paddr=%x, tp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1508. (unsigned int)addr_offset,
  1509. (unsigned int)dev_base_paddr,
  1510. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr),
  1511. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  1512. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  1513. srng_params.num_entries,
  1514. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  1515. hal_srng = (struct hal_srng *)
  1516. pdev->rx_refill_buf_ring2.hal_srng;
  1517. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1518. hal_srng_to_hal_ring_handle(hal_srng),
  1519. &srng_params);
  1520. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  1521. srng_params.ring_base_paddr;
  1522. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  1523. srng_params.ring_base_vaddr;
  1524. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  1525. (srng_params.num_entries * srng_params.entry_size) << 2;
  1526. hp_addr = hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1527. hal_srng_to_hal_ring_handle(hal_srng));
  1528. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr =
  1529. qdf_mem_paddr_from_dmaaddr(soc->osdev, hp_addr);
  1530. dp_info("IPA REFILL_BUF Ring hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1531. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr),
  1532. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  1533. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  1534. srng_params.num_entries,
  1535. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  1536. /*
  1537. * Set DEST_RING_MAPPING_4 to SW2 as default value for
  1538. * DESTINATION_RING_CTRL_IX_0.
  1539. */
  1540. ix0_map[0] = REO_REMAP_SW1;
  1541. ix0_map[1] = REO_REMAP_SW1;
  1542. ix0_map[2] = REO_REMAP_SW2;
  1543. ix0_map[3] = REO_REMAP_SW3;
  1544. ix0_map[4] = REO_REMAP_SW2;
  1545. ix0_map[5] = REO_REMAP_RELEASE;
  1546. ix0_map[6] = REO_REMAP_FW;
  1547. ix0_map[7] = REO_REMAP_FW;
  1548. dp_ipa_opt_dp_ixo_remap(ix0_map);
  1549. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1550. ix0_map);
  1551. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL, NULL, NULL);
  1552. dp_ipa_rx_alt_ring_resource_setup(soc, pdev);
  1553. return 0;
  1554. }
  1555. #ifdef IPA_WDI3_VLAN_SUPPORT
  1556. /**
  1557. * dp_ipa_rx_alt_ring_get_resource() - get IPA 2nd RX ring resources
  1558. * @pdev: data path pdev handle
  1559. *
  1560. * Return: Success if resourece is found
  1561. */
  1562. static QDF_STATUS dp_ipa_rx_alt_ring_get_resource(struct dp_pdev *pdev)
  1563. {
  1564. struct dp_soc *soc = pdev->soc;
  1565. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1566. if (!wlan_ipa_is_vlan_enabled())
  1567. return QDF_STATUS_SUCCESS;
  1568. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->rx_alt_rdy_ring,
  1569. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr,
  1570. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr,
  1571. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size);
  1572. dp_ipa_get_shared_mem_info(
  1573. soc->osdev, &ipa_res->rx_alt_refill_ring,
  1574. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr,
  1575. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr,
  1576. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size);
  1577. if (!qdf_mem_get_dma_addr(soc->osdev,
  1578. &ipa_res->rx_alt_rdy_ring.mem_info) ||
  1579. !qdf_mem_get_dma_addr(soc->osdev,
  1580. &ipa_res->rx_alt_refill_ring.mem_info))
  1581. return QDF_STATUS_E_FAILURE;
  1582. return QDF_STATUS_SUCCESS;
  1583. }
  1584. #else
  1585. static inline QDF_STATUS dp_ipa_rx_alt_ring_get_resource(struct dp_pdev *pdev)
  1586. {
  1587. return QDF_STATUS_SUCCESS;
  1588. }
  1589. #endif
  1590. QDF_STATUS dp_ipa_get_resource(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1591. {
  1592. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1593. struct dp_pdev *pdev =
  1594. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1595. struct dp_ipa_resources *ipa_res;
  1596. if (!pdev) {
  1597. dp_err("Invalid instance");
  1598. return QDF_STATUS_E_FAILURE;
  1599. }
  1600. ipa_res = &pdev->ipa_resource;
  1601. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1602. return QDF_STATUS_SUCCESS;
  1603. ipa_res->tx_num_alloc_buffer =
  1604. (uint32_t)soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  1605. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_ring,
  1606. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  1607. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  1608. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  1609. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_comp_ring,
  1610. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  1611. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  1612. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  1613. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->rx_rdy_ring,
  1614. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  1615. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  1616. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  1617. dp_ipa_get_shared_mem_info(
  1618. soc->osdev, &ipa_res->rx_refill_ring,
  1619. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  1620. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  1621. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  1622. if (!qdf_mem_get_dma_addr(soc->osdev, &ipa_res->tx_ring.mem_info) ||
  1623. !qdf_mem_get_dma_addr(soc->osdev,
  1624. &ipa_res->tx_comp_ring.mem_info) ||
  1625. !qdf_mem_get_dma_addr(soc->osdev, &ipa_res->rx_rdy_ring.mem_info) ||
  1626. !qdf_mem_get_dma_addr(soc->osdev,
  1627. &ipa_res->rx_refill_ring.mem_info))
  1628. return QDF_STATUS_E_FAILURE;
  1629. if (dp_ipa_tx_alt_ring_get_resource(pdev))
  1630. return QDF_STATUS_E_FAILURE;
  1631. if (dp_ipa_rx_alt_ring_get_resource(pdev))
  1632. return QDF_STATUS_E_FAILURE;
  1633. return QDF_STATUS_SUCCESS;
  1634. }
  1635. #ifdef IPA_SET_RESET_TX_DB_PA
  1636. #define DP_IPA_SET_TX_DB_PADDR(soc, ipa_res)
  1637. #else
  1638. #define DP_IPA_SET_TX_DB_PADDR(soc, ipa_res) \
  1639. dp_ipa_set_tx_doorbell_paddr(soc, ipa_res)
  1640. #endif
  1641. #ifdef IPA_WDI3_VLAN_SUPPORT
  1642. /**
  1643. * dp_ipa_map_rx_alt_ring_doorbell_paddr() - Map 2nd rx ring doorbell paddr
  1644. * @pdev: data path pdev handle
  1645. *
  1646. * Return: none
  1647. */
  1648. static void dp_ipa_map_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1649. {
  1650. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1651. uint32_t rx_ready_doorbell_dmaaddr;
  1652. struct dp_soc *soc = pdev->soc;
  1653. struct hal_srng *reo_srng = (struct hal_srng *)
  1654. soc->reo_dest_ring[IPA_ALT_REO_DEST_RING_IDX].hal_srng;
  1655. int ret = 0;
  1656. if (!wlan_ipa_is_vlan_enabled())
  1657. return;
  1658. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  1659. ret = pld_smmu_map(soc->osdev->dev,
  1660. ipa_res->rx_alt_ready_doorbell_paddr,
  1661. &rx_ready_doorbell_dmaaddr,
  1662. sizeof(uint32_t));
  1663. ipa_res->rx_alt_ready_doorbell_paddr =
  1664. rx_ready_doorbell_dmaaddr;
  1665. qdf_assert_always(!ret);
  1666. }
  1667. hal_srng_dst_set_hp_paddr_confirm(reo_srng,
  1668. ipa_res->rx_alt_ready_doorbell_paddr);
  1669. }
  1670. /**
  1671. * dp_ipa_unmap_rx_alt_ring_doorbell_paddr() - Unmap 2nd rx ring doorbell paddr
  1672. * @pdev: data path pdev handle
  1673. *
  1674. * Return: none
  1675. */
  1676. static void dp_ipa_unmap_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1677. {
  1678. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1679. struct dp_soc *soc = pdev->soc;
  1680. int ret = 0;
  1681. if (!wlan_ipa_is_vlan_enabled())
  1682. return;
  1683. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  1684. return;
  1685. ret = pld_smmu_unmap(soc->osdev->dev,
  1686. ipa_res->rx_alt_ready_doorbell_paddr,
  1687. sizeof(uint32_t));
  1688. qdf_assert_always(!ret);
  1689. }
  1690. #else
  1691. static inline void dp_ipa_map_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1692. { }
  1693. static inline void dp_ipa_unmap_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1694. { }
  1695. #endif
  1696. QDF_STATUS dp_ipa_set_doorbell_paddr(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1697. {
  1698. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1699. struct dp_pdev *pdev =
  1700. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1701. struct dp_ipa_resources *ipa_res;
  1702. struct hal_srng *reo_srng = (struct hal_srng *)
  1703. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1704. if (!pdev) {
  1705. dp_err("Invalid instance");
  1706. return QDF_STATUS_E_FAILURE;
  1707. }
  1708. ipa_res = &pdev->ipa_resource;
  1709. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1710. return QDF_STATUS_SUCCESS;
  1711. dp_ipa_map_ring_doorbell_paddr(pdev);
  1712. dp_ipa_map_rx_alt_ring_doorbell_paddr(pdev);
  1713. DP_IPA_SET_TX_DB_PADDR(soc, ipa_res);
  1714. /*
  1715. * For RX, REO module on Napier/Hastings does reordering on incoming
  1716. * Ethernet packets and writes one or more descriptors to REO2IPA Rx
  1717. * ring.It then updates the ring’s Write/Head ptr and rings a doorbell
  1718. * to IPA.
  1719. * Set the doorbell addr for the REO ring.
  1720. */
  1721. hal_srng_dst_set_hp_paddr_confirm(reo_srng,
  1722. ipa_res->rx_ready_doorbell_paddr);
  1723. return QDF_STATUS_SUCCESS;
  1724. }
  1725. QDF_STATUS dp_ipa_iounmap_doorbell_vaddr(struct cdp_soc_t *soc_hdl,
  1726. uint8_t pdev_id)
  1727. {
  1728. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1729. struct dp_pdev *pdev =
  1730. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1731. struct dp_ipa_resources *ipa_res;
  1732. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1733. return QDF_STATUS_SUCCESS;
  1734. if (!pdev) {
  1735. dp_err("Invalid instance");
  1736. return QDF_STATUS_E_FAILURE;
  1737. }
  1738. ipa_res = &pdev->ipa_resource;
  1739. if (!ipa_res->is_db_ddr_mapped)
  1740. iounmap(ipa_res->tx_comp_doorbell_vaddr);
  1741. return QDF_STATUS_SUCCESS;
  1742. }
  1743. QDF_STATUS dp_ipa_op_response(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1744. uint8_t *op_msg)
  1745. {
  1746. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1747. struct dp_pdev *pdev =
  1748. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1749. if (!pdev) {
  1750. dp_err("Invalid instance");
  1751. return QDF_STATUS_E_FAILURE;
  1752. }
  1753. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  1754. return QDF_STATUS_SUCCESS;
  1755. if (pdev->ipa_uc_op_cb) {
  1756. pdev->ipa_uc_op_cb(op_msg, pdev->usr_ctxt);
  1757. } else {
  1758. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1759. "%s: IPA callback function is not registered", __func__);
  1760. qdf_mem_free(op_msg);
  1761. return QDF_STATUS_E_FAILURE;
  1762. }
  1763. return QDF_STATUS_SUCCESS;
  1764. }
  1765. QDF_STATUS dp_ipa_register_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1766. ipa_uc_op_cb_type op_cb,
  1767. void *usr_ctxt)
  1768. {
  1769. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1770. struct dp_pdev *pdev =
  1771. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1772. if (!pdev) {
  1773. dp_err("Invalid instance");
  1774. return QDF_STATUS_E_FAILURE;
  1775. }
  1776. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  1777. return QDF_STATUS_SUCCESS;
  1778. pdev->ipa_uc_op_cb = op_cb;
  1779. pdev->usr_ctxt = usr_ctxt;
  1780. return QDF_STATUS_SUCCESS;
  1781. }
  1782. void dp_ipa_deregister_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1783. {
  1784. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1785. struct dp_pdev *pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1786. if (!pdev) {
  1787. dp_err("Invalid instance");
  1788. return;
  1789. }
  1790. dp_debug("Deregister OP handler callback");
  1791. pdev->ipa_uc_op_cb = NULL;
  1792. pdev->usr_ctxt = NULL;
  1793. }
  1794. QDF_STATUS dp_ipa_get_stat(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1795. {
  1796. /* TBD */
  1797. return QDF_STATUS_SUCCESS;
  1798. }
  1799. qdf_nbuf_t dp_tx_send_ipa_data_frame(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1800. qdf_nbuf_t skb)
  1801. {
  1802. qdf_nbuf_t ret;
  1803. /* Terminate the (single-element) list of tx frames */
  1804. qdf_nbuf_set_next(skb, NULL);
  1805. ret = dp_tx_send(soc_hdl, vdev_id, skb);
  1806. if (ret) {
  1807. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1808. "%s: Failed to tx", __func__);
  1809. return ret;
  1810. }
  1811. return NULL;
  1812. }
  1813. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  1814. /**
  1815. * dp_ipa_is_target_ready() - check if target is ready or not
  1816. * @soc: datapath soc handle
  1817. *
  1818. * Return: true if target is ready
  1819. */
  1820. static inline
  1821. bool dp_ipa_is_target_ready(struct dp_soc *soc)
  1822. {
  1823. if (hif_get_target_status(soc->hif_handle) == TARGET_STATUS_RESET)
  1824. return false;
  1825. else
  1826. return true;
  1827. }
  1828. /**
  1829. * dp_ipa_update_txr_db_status() - Indicate transfer ring DB is SMMU mapped or not
  1830. * @dev: Pointer to device
  1831. * @txrx_smmu: WDI TX/RX configuration
  1832. *
  1833. * Return: None
  1834. */
  1835. static inline
  1836. void dp_ipa_update_txr_db_status(struct device *dev,
  1837. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1838. {
  1839. int pcie_slot = pld_get_pci_slot(dev);
  1840. if (pcie_slot)
  1841. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(txrx_smmu) = false;
  1842. else
  1843. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1844. }
  1845. /**
  1846. * dp_ipa_update_evt_db_status() - Indicate evt ring DB is SMMU mapped or not
  1847. * @dev: Pointer to device
  1848. * @txrx_smmu: WDI TX/RX configuration
  1849. *
  1850. * Return: None
  1851. */
  1852. static inline
  1853. void dp_ipa_update_evt_db_status(struct device *dev,
  1854. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1855. {
  1856. int pcie_slot = pld_get_pci_slot(dev);
  1857. if (pcie_slot)
  1858. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(txrx_smmu) = false;
  1859. else
  1860. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1861. }
  1862. #else
  1863. static inline
  1864. bool dp_ipa_is_target_ready(struct dp_soc *soc)
  1865. {
  1866. return true;
  1867. }
  1868. static inline
  1869. void dp_ipa_update_txr_db_status(struct device *dev,
  1870. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1871. {
  1872. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1873. }
  1874. static inline
  1875. void dp_ipa_update_evt_db_status(struct device *dev,
  1876. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1877. {
  1878. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1879. }
  1880. #endif
  1881. QDF_STATUS dp_ipa_enable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1882. {
  1883. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1884. struct dp_pdev *pdev =
  1885. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1886. uint32_t ix0;
  1887. uint32_t ix2;
  1888. uint8_t ix_map[8];
  1889. if (!pdev) {
  1890. dp_err("Invalid instance");
  1891. return QDF_STATUS_E_FAILURE;
  1892. }
  1893. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1894. return QDF_STATUS_SUCCESS;
  1895. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  1896. return QDF_STATUS_E_AGAIN;
  1897. if (!dp_ipa_is_target_ready(soc))
  1898. return QDF_STATUS_E_AGAIN;
  1899. /* Call HAL API to remap REO rings to REO2IPA ring */
  1900. ix_map[0] = REO_REMAP_SW1;
  1901. ix_map[1] = REO_REMAP_SW4;
  1902. ix_map[2] = REO_REMAP_SW1;
  1903. if (wlan_ipa_is_vlan_enabled())
  1904. ix_map[3] = REO_REMAP_SW3;
  1905. else
  1906. ix_map[3] = REO_REMAP_SW4;
  1907. ix_map[4] = REO_REMAP_SW4;
  1908. ix_map[5] = REO_REMAP_RELEASE;
  1909. ix_map[6] = REO_REMAP_FW;
  1910. ix_map[7] = REO_REMAP_FW;
  1911. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1912. ix_map);
  1913. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1914. ix_map[0] = REO_REMAP_SW4;
  1915. ix_map[1] = REO_REMAP_SW4;
  1916. ix_map[2] = REO_REMAP_SW4;
  1917. ix_map[3] = REO_REMAP_SW4;
  1918. ix_map[4] = REO_REMAP_SW4;
  1919. ix_map[5] = REO_REMAP_SW4;
  1920. ix_map[6] = REO_REMAP_SW4;
  1921. ix_map[7] = REO_REMAP_SW4;
  1922. ix2 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX2,
  1923. ix_map);
  1924. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1925. &ix2, &ix2);
  1926. dp_ipa_reo_remap_history_add(ix0, ix2, ix2);
  1927. } else {
  1928. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1929. NULL, NULL);
  1930. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  1931. }
  1932. return QDF_STATUS_SUCCESS;
  1933. }
  1934. QDF_STATUS dp_ipa_disable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1935. {
  1936. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1937. struct dp_pdev *pdev =
  1938. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1939. uint8_t ix0_map[8];
  1940. uint32_t ix0;
  1941. uint32_t ix1;
  1942. uint32_t ix2;
  1943. uint32_t ix3;
  1944. if (!pdev) {
  1945. dp_err("Invalid instance");
  1946. return QDF_STATUS_E_FAILURE;
  1947. }
  1948. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1949. return QDF_STATUS_SUCCESS;
  1950. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  1951. return QDF_STATUS_E_AGAIN;
  1952. if (!dp_ipa_is_target_ready(soc))
  1953. return QDF_STATUS_E_AGAIN;
  1954. ix0_map[0] = REO_REMAP_SW1;
  1955. ix0_map[1] = REO_REMAP_SW1;
  1956. ix0_map[2] = REO_REMAP_SW2;
  1957. ix0_map[3] = REO_REMAP_SW3;
  1958. ix0_map[4] = REO_REMAP_SW2;
  1959. ix0_map[5] = REO_REMAP_RELEASE;
  1960. ix0_map[6] = REO_REMAP_FW;
  1961. ix0_map[7] = REO_REMAP_FW;
  1962. /* Call HAL API to remap REO rings to REO2IPA ring */
  1963. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1964. ix0_map);
  1965. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1966. dp_reo_remap_config(soc, &ix1, &ix2, &ix3);
  1967. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1968. &ix2, &ix3);
  1969. dp_ipa_reo_remap_history_add(ix0, ix2, ix3);
  1970. } else {
  1971. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1972. NULL, NULL);
  1973. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  1974. }
  1975. return QDF_STATUS_SUCCESS;
  1976. }
  1977. /* This should be configurable per H/W configuration enable status */
  1978. #define L3_HEADER_PADDING 2
  1979. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || \
  1980. defined(CONFIG_IPA_WDI_UNIFIED_API)
  1981. #if !defined(QCA_LL_TX_FLOW_CONTROL_V2) && !defined(QCA_IPA_LL_TX_FLOW_CONTROL)
  1982. static inline void dp_setup_mcc_sys_pipes(
  1983. qdf_ipa_sys_connect_params_t *sys_in,
  1984. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  1985. {
  1986. int i = 0;
  1987. /* Setup MCC sys pipe */
  1988. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) =
  1989. DP_IPA_MAX_IFACE;
  1990. for (i = 0; i < DP_IPA_MAX_IFACE; i++)
  1991. memcpy(&QDF_IPA_WDI_CONN_IN_PARAMS_SYS_IN(pipe_in)[i],
  1992. &sys_in[i], sizeof(qdf_ipa_sys_connect_params_t));
  1993. }
  1994. #else
  1995. static inline void dp_setup_mcc_sys_pipes(
  1996. qdf_ipa_sys_connect_params_t *sys_in,
  1997. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  1998. {
  1999. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) = 0;
  2000. }
  2001. #endif
  2002. static void dp_ipa_wdi_tx_params(struct dp_soc *soc,
  2003. struct dp_ipa_resources *ipa_res,
  2004. qdf_ipa_wdi_pipe_setup_info_t *tx,
  2005. bool over_gsi)
  2006. {
  2007. if (over_gsi)
  2008. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN2_CONS;
  2009. else
  2010. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  2011. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  2012. qdf_mem_get_dma_addr(soc->osdev,
  2013. &ipa_res->tx_comp_ring.mem_info);
  2014. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  2015. qdf_mem_get_dma_size(soc->osdev,
  2016. &ipa_res->tx_comp_ring.mem_info);
  2017. /* WBM Tail Pointer Address */
  2018. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  2019. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2020. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(tx) = true;
  2021. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  2022. qdf_mem_get_dma_addr(soc->osdev,
  2023. &ipa_res->tx_ring.mem_info);
  2024. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) =
  2025. qdf_mem_get_dma_size(soc->osdev,
  2026. &ipa_res->tx_ring.mem_info);
  2027. /* TCL Head Pointer Address */
  2028. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  2029. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2030. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(tx) = true;
  2031. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  2032. ipa_res->tx_num_alloc_buffer;
  2033. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  2034. dp_ipa_setup_tx_params_bank_id(soc, tx);
  2035. /* Set Pmac ID, extract pmac_id from pdev_id 0 for TX ring */
  2036. dp_ipa_setup_tx_params_pmac_id(soc, tx);
  2037. }
  2038. static void dp_ipa_wdi_rx_params(struct dp_soc *soc,
  2039. struct dp_ipa_resources *ipa_res,
  2040. qdf_ipa_wdi_pipe_setup_info_t *rx,
  2041. bool over_gsi)
  2042. {
  2043. if (over_gsi)
  2044. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2045. IPA_CLIENT_WLAN2_PROD;
  2046. else
  2047. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2048. IPA_CLIENT_WLAN1_PROD;
  2049. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2050. qdf_mem_get_dma_addr(soc->osdev,
  2051. &ipa_res->rx_rdy_ring.mem_info);
  2052. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2053. qdf_mem_get_dma_size(soc->osdev,
  2054. &ipa_res->rx_rdy_ring.mem_info);
  2055. /* REO Tail Pointer Address */
  2056. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2057. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2058. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(rx) = true;
  2059. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2060. qdf_mem_get_dma_addr(soc->osdev,
  2061. &ipa_res->rx_refill_ring.mem_info);
  2062. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2063. qdf_mem_get_dma_size(soc->osdev,
  2064. &ipa_res->rx_refill_ring.mem_info);
  2065. /* FW Head Pointer Address */
  2066. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2067. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2068. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(rx) = false;
  2069. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) =
  2070. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2071. }
  2072. static void
  2073. dp_ipa_wdi_tx_smmu_params(struct dp_soc *soc,
  2074. struct dp_ipa_resources *ipa_res,
  2075. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu,
  2076. bool over_gsi,
  2077. qdf_ipa_wdi_hdl_t hdl)
  2078. {
  2079. if (over_gsi) {
  2080. if (hdl == DP_IPA_HDL_FIRST)
  2081. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2082. IPA_CLIENT_WLAN2_CONS;
  2083. else if (hdl == DP_IPA_HDL_SECOND)
  2084. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2085. IPA_CLIENT_WLAN4_CONS;
  2086. else if (hdl == DP_IPA_HDL_THIRD)
  2087. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2088. IPA_CLIENT_WLAN1_CONS;
  2089. } else {
  2090. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2091. IPA_CLIENT_WLAN1_CONS;
  2092. }
  2093. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(tx_smmu),
  2094. &ipa_res->tx_comp_ring.sgtable,
  2095. sizeof(sgtable_t));
  2096. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(tx_smmu) =
  2097. qdf_mem_get_dma_size(soc->osdev,
  2098. &ipa_res->tx_comp_ring.mem_info);
  2099. /* WBM Tail Pointer Address */
  2100. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(tx_smmu) =
  2101. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2102. dp_ipa_update_txr_db_status(soc->osdev->dev, tx_smmu);
  2103. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(tx_smmu),
  2104. &ipa_res->tx_ring.sgtable,
  2105. sizeof(sgtable_t));
  2106. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(tx_smmu) =
  2107. qdf_mem_get_dma_size(soc->osdev,
  2108. &ipa_res->tx_ring.mem_info);
  2109. /* TCL Head Pointer Address */
  2110. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(tx_smmu) =
  2111. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2112. dp_ipa_update_evt_db_status(soc->osdev->dev, tx_smmu);
  2113. QDF_IPA_WDI_SETUP_INFO_SMMU_NUM_PKT_BUFFERS(tx_smmu) =
  2114. ipa_res->tx_num_alloc_buffer;
  2115. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(tx_smmu) = 0;
  2116. dp_ipa_setup_tx_smmu_params_bank_id(soc, tx_smmu);
  2117. /* Set Pmac ID, extract pmac_id from first pdev for TX ring */
  2118. dp_ipa_setup_tx_smmu_params_pmac_id(soc, tx_smmu);
  2119. }
  2120. static void
  2121. dp_ipa_wdi_rx_smmu_params(struct dp_soc *soc,
  2122. struct dp_ipa_resources *ipa_res,
  2123. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu,
  2124. bool over_gsi,
  2125. qdf_ipa_wdi_hdl_t hdl)
  2126. {
  2127. if (over_gsi) {
  2128. if (hdl == DP_IPA_HDL_FIRST)
  2129. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2130. IPA_CLIENT_WLAN2_PROD;
  2131. else if (hdl == DP_IPA_HDL_SECOND)
  2132. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2133. IPA_CLIENT_WLAN3_PROD;
  2134. else if (hdl == DP_IPA_HDL_THIRD)
  2135. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2136. IPA_CLIENT_WLAN1_PROD;
  2137. } else {
  2138. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2139. IPA_CLIENT_WLAN1_PROD;
  2140. }
  2141. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(rx_smmu),
  2142. &ipa_res->rx_rdy_ring.sgtable,
  2143. sizeof(sgtable_t));
  2144. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(rx_smmu) =
  2145. qdf_mem_get_dma_size(soc->osdev,
  2146. &ipa_res->rx_rdy_ring.mem_info);
  2147. /* REO Tail Pointer Address */
  2148. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(rx_smmu) =
  2149. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2150. dp_ipa_update_txr_db_status(soc->osdev->dev, rx_smmu);
  2151. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(rx_smmu),
  2152. &ipa_res->rx_refill_ring.sgtable,
  2153. sizeof(sgtable_t));
  2154. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(rx_smmu) =
  2155. qdf_mem_get_dma_size(soc->osdev,
  2156. &ipa_res->rx_refill_ring.mem_info);
  2157. /* FW Head Pointer Address */
  2158. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(rx_smmu) =
  2159. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2160. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(rx_smmu) = false;
  2161. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(rx_smmu) =
  2162. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2163. }
  2164. #ifdef IPA_WDI3_VLAN_SUPPORT
  2165. /**
  2166. * dp_ipa_wdi_rx_alt_pipe_smmu_params() - Setup 2nd rx pipe smmu params
  2167. * @soc: data path soc handle
  2168. * @ipa_res: ipa resource pointer
  2169. * @rx_smmu: smmu pipe info handle
  2170. * @over_gsi: flag for IPA offload over gsi
  2171. * @hdl: ipa registered handle
  2172. *
  2173. * Return: none
  2174. */
  2175. static void
  2176. dp_ipa_wdi_rx_alt_pipe_smmu_params(struct dp_soc *soc,
  2177. struct dp_ipa_resources *ipa_res,
  2178. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu,
  2179. bool over_gsi,
  2180. qdf_ipa_wdi_hdl_t hdl)
  2181. {
  2182. if (!wlan_ipa_is_vlan_enabled())
  2183. return;
  2184. if (over_gsi) {
  2185. if (hdl == DP_IPA_HDL_FIRST)
  2186. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2187. IPA_CLIENT_WLAN2_PROD1;
  2188. else if (hdl == DP_IPA_HDL_SECOND)
  2189. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2190. IPA_CLIENT_WLAN3_PROD1;
  2191. else if (hdl == DP_IPA_HDL_THIRD)
  2192. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx_smmu) =
  2193. IPA_CLIENT_WLAN1_PROD1;
  2194. } else {
  2195. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2196. IPA_CLIENT_WLAN1_PROD;
  2197. }
  2198. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(rx_smmu),
  2199. &ipa_res->rx_alt_rdy_ring.sgtable,
  2200. sizeof(sgtable_t));
  2201. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(rx_smmu) =
  2202. qdf_mem_get_dma_size(soc->osdev,
  2203. &ipa_res->rx_alt_rdy_ring.mem_info);
  2204. /* REO Tail Pointer Address */
  2205. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(rx_smmu) =
  2206. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr;
  2207. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(rx_smmu) = true;
  2208. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(rx_smmu),
  2209. &ipa_res->rx_alt_refill_ring.sgtable,
  2210. sizeof(sgtable_t));
  2211. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(rx_smmu) =
  2212. qdf_mem_get_dma_size(soc->osdev,
  2213. &ipa_res->rx_alt_refill_ring.mem_info);
  2214. /* FW Head Pointer Address */
  2215. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(rx_smmu) =
  2216. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr;
  2217. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(rx_smmu) = false;
  2218. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(rx_smmu) =
  2219. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2220. }
  2221. /**
  2222. * dp_ipa_wdi_rx_alt_pipe_params() - Setup 2nd rx pipe params
  2223. * @soc: data path soc handle
  2224. * @ipa_res: ipa resource pointer
  2225. * @rx: pipe info handle
  2226. * @over_gsi: flag for IPA offload over gsi
  2227. * @hdl: ipa registered handle
  2228. *
  2229. * Return: none
  2230. */
  2231. static void dp_ipa_wdi_rx_alt_pipe_params(struct dp_soc *soc,
  2232. struct dp_ipa_resources *ipa_res,
  2233. qdf_ipa_wdi_pipe_setup_info_t *rx,
  2234. bool over_gsi,
  2235. qdf_ipa_wdi_hdl_t hdl)
  2236. {
  2237. if (!wlan_ipa_is_vlan_enabled())
  2238. return;
  2239. if (over_gsi) {
  2240. if (hdl == DP_IPA_HDL_FIRST)
  2241. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2242. IPA_CLIENT_WLAN2_PROD1;
  2243. else if (hdl == DP_IPA_HDL_SECOND)
  2244. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2245. IPA_CLIENT_WLAN3_PROD1;
  2246. else if (hdl == DP_IPA_HDL_THIRD)
  2247. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2248. IPA_CLIENT_WLAN1_PROD1;
  2249. } else {
  2250. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2251. IPA_CLIENT_WLAN1_PROD;
  2252. }
  2253. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2254. qdf_mem_get_dma_addr(soc->osdev,
  2255. &ipa_res->rx_alt_rdy_ring.mem_info);
  2256. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2257. qdf_mem_get_dma_size(soc->osdev,
  2258. &ipa_res->rx_alt_rdy_ring.mem_info);
  2259. /* REO Tail Pointer Address */
  2260. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2261. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr;
  2262. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(rx) = true;
  2263. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2264. qdf_mem_get_dma_addr(soc->osdev,
  2265. &ipa_res->rx_alt_refill_ring.mem_info);
  2266. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2267. qdf_mem_get_dma_size(soc->osdev,
  2268. &ipa_res->rx_alt_refill_ring.mem_info);
  2269. /* FW Head Pointer Address */
  2270. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2271. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr;
  2272. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(rx) = false;
  2273. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) =
  2274. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2275. }
  2276. /**
  2277. * dp_ipa_setup_rx_alt_pipe() - Setup 2nd rx pipe for IPA offload
  2278. * @soc: data path soc handle
  2279. * @res: ipa resource pointer
  2280. * @in: pipe in handle
  2281. * @over_gsi: flag for IPA offload over gsi
  2282. * @hdl: ipa registered handle
  2283. *
  2284. * Return: none
  2285. */
  2286. static void dp_ipa_setup_rx_alt_pipe(struct dp_soc *soc,
  2287. struct dp_ipa_resources *res,
  2288. qdf_ipa_wdi_conn_in_params_t *in,
  2289. bool over_gsi,
  2290. qdf_ipa_wdi_hdl_t hdl)
  2291. {
  2292. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu = NULL;
  2293. qdf_ipa_wdi_pipe_setup_info_t *rx = NULL;
  2294. qdf_ipa_ep_cfg_t *rx_cfg;
  2295. if (!wlan_ipa_is_vlan_enabled())
  2296. return;
  2297. QDF_IPA_WDI_CONN_IN_PARAMS_IS_RX1_USED(in) = true;
  2298. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  2299. rx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_ALT_SMMU(in);
  2300. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx_smmu);
  2301. dp_ipa_wdi_rx_alt_pipe_smmu_params(soc, res, rx_smmu,
  2302. over_gsi, hdl);
  2303. } else {
  2304. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_ALT(in);
  2305. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx);
  2306. dp_ipa_wdi_rx_alt_pipe_params(soc, res, rx, over_gsi, hdl);
  2307. }
  2308. QDF_IPA_EP_CFG_NAT_EN(rx_cfg) = IPA_BYPASS_NAT;
  2309. /* Update with wds len(96) + 4 if wds support is enabled */
  2310. if (ucfg_ipa_is_wds_enabled())
  2311. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN_AST_VLAN;
  2312. else
  2313. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN;
  2314. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(rx_cfg) = 1;
  2315. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(rx_cfg) = 0;
  2316. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(rx_cfg) = 0;
  2317. QDF_IPA_EP_CFG_HDR_OFST_METADATA_VALID(rx_cfg) = 0;
  2318. QDF_IPA_EP_CFG_HDR_METADATA_REG_VALID(rx_cfg) = 1;
  2319. QDF_IPA_EP_CFG_MODE(rx_cfg) = IPA_BASIC;
  2320. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(rx_cfg) = true;
  2321. }
  2322. /**
  2323. * dp_ipa_set_rx_alt_pipe_db() - Setup 2nd rx pipe doorbell
  2324. * @res: ipa resource pointer
  2325. * @out: pipe out handle
  2326. *
  2327. * Return: none
  2328. */
  2329. static void dp_ipa_set_rx_alt_pipe_db(struct dp_ipa_resources *res,
  2330. qdf_ipa_wdi_conn_out_params_t *out)
  2331. {
  2332. if (!wlan_ipa_is_vlan_enabled())
  2333. return;
  2334. res->rx_alt_ready_doorbell_paddr =
  2335. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_ALT_UC_DB_PA(out);
  2336. dp_debug("Setting DB 0x%x for RX alt pipe",
  2337. res->rx_alt_ready_doorbell_paddr);
  2338. }
  2339. #else
  2340. static inline
  2341. void dp_ipa_setup_rx_alt_pipe(struct dp_soc *soc,
  2342. struct dp_ipa_resources *res,
  2343. qdf_ipa_wdi_conn_in_params_t *in,
  2344. bool over_gsi,
  2345. qdf_ipa_wdi_hdl_t hdl)
  2346. { }
  2347. static inline
  2348. void dp_ipa_set_rx_alt_pipe_db(struct dp_ipa_resources *res,
  2349. qdf_ipa_wdi_conn_out_params_t *out)
  2350. { }
  2351. #endif
  2352. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2353. void *ipa_i2w_cb, void *ipa_w2i_cb,
  2354. void *ipa_wdi_meter_notifier_cb,
  2355. uint32_t ipa_desc_size, void *ipa_priv,
  2356. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  2357. uint32_t *rx_pipe_handle, bool is_smmu_enabled,
  2358. qdf_ipa_sys_connect_params_t *sys_in, bool over_gsi,
  2359. qdf_ipa_wdi_hdl_t hdl, qdf_ipa_wdi_hdl_t id,
  2360. void *ipa_ast_notify_cb)
  2361. {
  2362. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2363. struct dp_pdev *pdev =
  2364. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2365. struct dp_ipa_resources *ipa_res;
  2366. qdf_ipa_ep_cfg_t *tx_cfg;
  2367. qdf_ipa_ep_cfg_t *rx_cfg;
  2368. qdf_ipa_wdi_pipe_setup_info_t *tx = NULL;
  2369. qdf_ipa_wdi_pipe_setup_info_t *rx = NULL;
  2370. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu;
  2371. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu = NULL;
  2372. qdf_ipa_wdi_conn_in_params_t *pipe_in = NULL;
  2373. qdf_ipa_wdi_conn_out_params_t pipe_out;
  2374. int ret;
  2375. if (!pdev) {
  2376. dp_err("Invalid instance");
  2377. return QDF_STATUS_E_FAILURE;
  2378. }
  2379. ipa_res = &pdev->ipa_resource;
  2380. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  2381. return QDF_STATUS_SUCCESS;
  2382. pipe_in = qdf_mem_malloc(sizeof(*pipe_in));
  2383. if (!pipe_in)
  2384. return QDF_STATUS_E_NOMEM;
  2385. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  2386. if (is_smmu_enabled)
  2387. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in) = true;
  2388. else
  2389. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in) = false;
  2390. dp_setup_mcc_sys_pipes(sys_in, pipe_in);
  2391. /* TX PIPE */
  2392. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in)) {
  2393. tx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_SMMU(pipe_in);
  2394. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx_smmu);
  2395. } else {
  2396. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(pipe_in);
  2397. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(tx);
  2398. }
  2399. QDF_IPA_EP_CFG_NAT_EN(tx_cfg) = IPA_BYPASS_NAT;
  2400. QDF_IPA_EP_CFG_HDR_LEN(tx_cfg) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2401. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(tx_cfg) = 0;
  2402. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(tx_cfg) = 0;
  2403. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(tx_cfg) = 0;
  2404. QDF_IPA_EP_CFG_MODE(tx_cfg) = IPA_BASIC;
  2405. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(tx_cfg) = true;
  2406. /*
  2407. * Transfer Ring: WBM Ring
  2408. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  2409. * Event Ring: TCL ring
  2410. * Event Ring Doorbell PA: TCL Head Pointer Address
  2411. */
  2412. if (is_smmu_enabled)
  2413. dp_ipa_wdi_tx_smmu_params(soc, ipa_res, tx_smmu, over_gsi, id);
  2414. else
  2415. dp_ipa_wdi_tx_params(soc, ipa_res, tx, over_gsi);
  2416. dp_ipa_setup_tx_alt_pipe(soc, ipa_res, pipe_in);
  2417. /* RX PIPE */
  2418. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in)) {
  2419. rx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_SMMU(pipe_in);
  2420. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx_smmu);
  2421. } else {
  2422. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(pipe_in);
  2423. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(rx);
  2424. }
  2425. QDF_IPA_EP_CFG_NAT_EN(rx_cfg) = IPA_BYPASS_NAT;
  2426. if (ucfg_ipa_is_wds_enabled())
  2427. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN_AST;
  2428. else
  2429. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  2430. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(rx_cfg) = 1;
  2431. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(rx_cfg) = 0;
  2432. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(rx_cfg) = 0;
  2433. QDF_IPA_EP_CFG_HDR_OFST_METADATA_VALID(rx_cfg) = 0;
  2434. QDF_IPA_EP_CFG_HDR_METADATA_REG_VALID(rx_cfg) = 1;
  2435. QDF_IPA_EP_CFG_MODE(rx_cfg) = IPA_BASIC;
  2436. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(rx_cfg) = true;
  2437. /*
  2438. * Transfer Ring: REO Ring
  2439. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  2440. * Event Ring: FW ring
  2441. * Event Ring Doorbell PA: FW Head Pointer Address
  2442. */
  2443. if (is_smmu_enabled)
  2444. dp_ipa_wdi_rx_smmu_params(soc, ipa_res, rx_smmu, over_gsi, id);
  2445. else
  2446. dp_ipa_wdi_rx_params(soc, ipa_res, rx, over_gsi);
  2447. /* setup 2nd rx pipe */
  2448. dp_ipa_setup_rx_alt_pipe(soc, ipa_res, pipe_in, over_gsi, id);
  2449. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(pipe_in) = ipa_w2i_cb;
  2450. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(pipe_in) = ipa_priv;
  2451. QDF_IPA_WDI_CONN_IN_PARAMS_HANDLE(pipe_in) = hdl;
  2452. dp_ipa_ast_notify_cb(pipe_in, ipa_ast_notify_cb);
  2453. /* Connect WDI IPA PIPEs */
  2454. ret = qdf_ipa_wdi_conn_pipes(pipe_in, &pipe_out);
  2455. if (ret) {
  2456. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2457. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  2458. __func__, ret);
  2459. qdf_mem_free(pipe_in);
  2460. return QDF_STATUS_E_FAILURE;
  2461. }
  2462. /* IPA uC Doorbell registers */
  2463. dp_info("Tx DB PA=0x%x, Rx DB PA=0x%x",
  2464. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  2465. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  2466. dp_ipa_set_pipe_db(ipa_res, &pipe_out);
  2467. dp_ipa_set_rx_alt_pipe_db(ipa_res, &pipe_out);
  2468. ipa_res->is_db_ddr_mapped =
  2469. QDF_IPA_WDI_CONN_OUT_PARAMS_IS_DB_DDR_MAPPED(&pipe_out);
  2470. soc->ipa_first_tx_db_access = true;
  2471. qdf_mem_free(pipe_in);
  2472. qdf_spinlock_create(&soc->ipa_rx_buf_map_lock);
  2473. soc->ipa_rx_buf_map_lock_initialized = true;
  2474. return QDF_STATUS_SUCCESS;
  2475. }
  2476. #ifdef IPA_WDI3_VLAN_SUPPORT
  2477. /**
  2478. * dp_ipa_set_rx1_used() - Set rx1 used flag for 2nd rx offload ring
  2479. * @in: pipe in handle
  2480. *
  2481. * Return: none
  2482. */
  2483. static inline
  2484. void dp_ipa_set_rx1_used(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2485. {
  2486. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_RX1_USED(in) = true;
  2487. }
  2488. /**
  2489. * dp_ipa_set_v4_vlan_hdr() - Set v4 vlan hdr
  2490. * @in: pipe in handle
  2491. * @hdr: pointer to hdr
  2492. *
  2493. * Return: none
  2494. */
  2495. static inline
  2496. void dp_ipa_set_v4_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2497. qdf_ipa_wdi_hdr_info_t *hdr)
  2498. {
  2499. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(in)[IPA_IP_v4_VLAN]),
  2500. hdr, sizeof(qdf_ipa_wdi_hdr_info_t));
  2501. }
  2502. /**
  2503. * dp_ipa_set_v6_vlan_hdr() - Set v6 vlan hdr
  2504. * @in: pipe in handle
  2505. * @hdr: pointer to hdr
  2506. *
  2507. * Return: none
  2508. */
  2509. static inline
  2510. void dp_ipa_set_v6_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2511. qdf_ipa_wdi_hdr_info_t *hdr)
  2512. {
  2513. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(in)[IPA_IP_v6_VLAN]),
  2514. hdr, sizeof(qdf_ipa_wdi_hdr_info_t));
  2515. }
  2516. #else
  2517. static inline
  2518. void dp_ipa_set_rx1_used(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2519. { }
  2520. static inline
  2521. void dp_ipa_set_v4_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2522. qdf_ipa_wdi_hdr_info_t *hdr)
  2523. { }
  2524. static inline
  2525. void dp_ipa_set_v6_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2526. qdf_ipa_wdi_hdr_info_t *hdr)
  2527. { }
  2528. #endif
  2529. #ifdef IPA_WDS_EASYMESH_FEATURE
  2530. /**
  2531. * dp_ipa_set_wdi_hdr_type() - Set wdi hdr type for IPA
  2532. * @hdr_info: Header info
  2533. *
  2534. * Return: None
  2535. */
  2536. static inline void
  2537. dp_ipa_set_wdi_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2538. {
  2539. if (ucfg_ipa_is_wds_enabled())
  2540. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2541. IPA_HDR_L2_ETHERNET_II_AST;
  2542. else
  2543. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2544. IPA_HDR_L2_ETHERNET_II;
  2545. }
  2546. /**
  2547. * dp_ipa_setup_meta_data_mask() - Pass meta data mask to IPA
  2548. * @in: ipa in params
  2549. *
  2550. * Pass meta data mask to IPA.
  2551. *
  2552. * Return: none
  2553. */
  2554. static void dp_ipa_setup_meta_data_mask(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2555. {
  2556. if (ucfg_ipa_is_wds_enabled())
  2557. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(in) = WLAN_IPA_AST_META_DATA_MASK;
  2558. else
  2559. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(in) = WLAN_IPA_META_DATA_MASK;
  2560. }
  2561. #else
  2562. static inline void
  2563. dp_ipa_set_wdi_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2564. {
  2565. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) = IPA_HDR_L2_ETHERNET_II;
  2566. }
  2567. static void dp_ipa_setup_meta_data_mask(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2568. {
  2569. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(in) = WLAN_IPA_META_DATA_MASK;
  2570. }
  2571. #endif
  2572. #ifdef IPA_WDI3_VLAN_SUPPORT
  2573. /**
  2574. * dp_ipa_set_wdi_vlan_hdr_type() - Set wdi vlan hdr type for IPA
  2575. * @hdr_info: Header info
  2576. *
  2577. * Return: None
  2578. */
  2579. static inline void
  2580. dp_ipa_set_wdi_vlan_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2581. {
  2582. if (ucfg_ipa_is_wds_enabled())
  2583. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2584. IPA_HDR_L2_802_1Q_AST;
  2585. else
  2586. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2587. IPA_HDR_L2_802_1Q;
  2588. }
  2589. #else
  2590. static inline void
  2591. dp_ipa_set_wdi_vlan_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2592. { }
  2593. #endif
  2594. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  2595. qdf_ipa_client_type_t prod_client,
  2596. qdf_ipa_client_type_t cons_client,
  2597. uint8_t session_id, bool is_ipv6_enabled,
  2598. qdf_ipa_wdi_hdl_t hdl)
  2599. {
  2600. qdf_ipa_wdi_reg_intf_in_params_t in;
  2601. qdf_ipa_wdi_hdr_info_t hdr_info;
  2602. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  2603. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  2604. struct dp_ipa_uc_tx_vlan_hdr uc_tx_vlan_hdr;
  2605. struct dp_ipa_uc_tx_vlan_hdr uc_tx_vlan_hdr_v6;
  2606. int ret = -EINVAL;
  2607. qdf_mem_zero(&in, sizeof(qdf_ipa_wdi_reg_intf_in_params_t));
  2608. /* Need to reset the values to 0 as all the fields are not
  2609. * updated in the Header, Unused fields will be set to 0.
  2610. */
  2611. qdf_mem_zero(&uc_tx_vlan_hdr, sizeof(struct dp_ipa_uc_tx_vlan_hdr));
  2612. qdf_mem_zero(&uc_tx_vlan_hdr_v6, sizeof(struct dp_ipa_uc_tx_vlan_hdr));
  2613. dp_debug("Add Partial hdr: %s, "QDF_MAC_ADDR_FMT, ifname,
  2614. QDF_MAC_ADDR_REF(mac_addr));
  2615. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2616. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  2617. /* IPV4 header */
  2618. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  2619. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  2620. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2621. dp_ipa_set_wdi_hdr_type(&hdr_info);
  2622. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2623. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2624. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  2625. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  2626. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2627. QDF_IPA_WDI_REG_INTF_IN_PARAMS_ALT_DST_PIPE(&in) = cons_client;
  2628. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  2629. dp_ipa_setup_meta_data_mask(&in);
  2630. QDF_IPA_WDI_REG_INTF_IN_PARAMS_HANDLE(&in) = hdl;
  2631. dp_ipa_setup_iface_session_id(&in, session_id);
  2632. dp_debug("registering for session_id: %u", session_id);
  2633. /* IPV6 header */
  2634. if (is_ipv6_enabled) {
  2635. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  2636. DP_IPA_UC_WLAN_TX_HDR_LEN);
  2637. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  2638. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  2639. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  2640. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2641. }
  2642. if (wlan_ipa_is_vlan_enabled()) {
  2643. /* Add vlan specific headers if vlan supporti is enabled */
  2644. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2645. dp_ipa_set_rx1_used(&in);
  2646. qdf_ether_addr_copy(uc_tx_vlan_hdr.eth.h_source, mac_addr);
  2647. /* IPV4 Vlan header */
  2648. uc_tx_vlan_hdr.eth.h_vlan_proto = qdf_htons(ETH_P_8021Q);
  2649. uc_tx_vlan_hdr.eth.h_vlan_encapsulated_proto = qdf_htons(ETH_P_IP);
  2650. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) =
  2651. (uint8_t *)&uc_tx_vlan_hdr;
  2652. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) =
  2653. DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN;
  2654. dp_ipa_set_wdi_vlan_hdr_type(&hdr_info);
  2655. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2656. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2657. dp_ipa_set_v4_vlan_hdr(&in, &hdr_info);
  2658. /* IPV6 Vlan header */
  2659. if (is_ipv6_enabled) {
  2660. qdf_mem_copy(&uc_tx_vlan_hdr_v6, &uc_tx_vlan_hdr,
  2661. DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN);
  2662. uc_tx_vlan_hdr_v6.eth.h_vlan_proto =
  2663. qdf_htons(ETH_P_8021Q);
  2664. uc_tx_vlan_hdr_v6.eth.h_vlan_encapsulated_proto =
  2665. qdf_htons(ETH_P_IPV6);
  2666. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) =
  2667. (uint8_t *)&uc_tx_vlan_hdr_v6;
  2668. dp_ipa_set_v6_vlan_hdr(&in, &hdr_info);
  2669. }
  2670. }
  2671. ret = qdf_ipa_wdi_reg_intf(&in);
  2672. if (ret) {
  2673. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2674. "%s: ipa_wdi_reg_intf: register IPA interface failed: ret=%d",
  2675. __func__, ret);
  2676. return QDF_STATUS_E_FAILURE;
  2677. }
  2678. return QDF_STATUS_SUCCESS;
  2679. }
  2680. #else /* !CONFIG_IPA_WDI_UNIFIED_API */
  2681. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2682. void *ipa_i2w_cb, void *ipa_w2i_cb,
  2683. void *ipa_wdi_meter_notifier_cb,
  2684. uint32_t ipa_desc_size, void *ipa_priv,
  2685. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  2686. uint32_t *rx_pipe_handle)
  2687. {
  2688. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2689. struct dp_pdev *pdev =
  2690. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2691. struct dp_ipa_resources *ipa_res;
  2692. qdf_ipa_wdi_pipe_setup_info_t *tx;
  2693. qdf_ipa_wdi_pipe_setup_info_t *rx;
  2694. qdf_ipa_wdi_conn_in_params_t pipe_in;
  2695. qdf_ipa_wdi_conn_out_params_t pipe_out;
  2696. struct tcl_data_cmd *tcl_desc_ptr;
  2697. uint8_t *desc_addr;
  2698. uint32_t desc_size;
  2699. int ret;
  2700. if (!pdev) {
  2701. dp_err("Invalid instance");
  2702. return QDF_STATUS_E_FAILURE;
  2703. }
  2704. ipa_res = &pdev->ipa_resource;
  2705. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  2706. return QDF_STATUS_SUCCESS;
  2707. qdf_mem_zero(&tx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  2708. qdf_mem_zero(&rx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  2709. qdf_mem_zero(&pipe_in, sizeof(pipe_in));
  2710. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  2711. /* TX PIPE */
  2712. /*
  2713. * Transfer Ring: WBM Ring
  2714. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  2715. * Event Ring: TCL ring
  2716. * Event Ring Doorbell PA: TCL Head Pointer Address
  2717. */
  2718. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(&pipe_in);
  2719. QDF_IPA_WDI_SETUP_INFO_NAT_EN(tx) = IPA_BYPASS_NAT;
  2720. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(tx) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2721. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(tx) = 0;
  2722. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(tx) = 0;
  2723. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(tx) = 0;
  2724. QDF_IPA_WDI_SETUP_INFO_MODE(tx) = IPA_BASIC;
  2725. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(tx) = true;
  2726. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  2727. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  2728. ipa_res->tx_comp_ring_base_paddr;
  2729. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  2730. ipa_res->tx_comp_ring_size;
  2731. /* WBM Tail Pointer Address */
  2732. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  2733. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2734. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  2735. ipa_res->tx_ring_base_paddr;
  2736. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) = ipa_res->tx_ring_size;
  2737. /* TCL Head Pointer Address */
  2738. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  2739. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2740. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  2741. ipa_res->tx_num_alloc_buffer;
  2742. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  2743. /* Preprogram TCL descriptor */
  2744. desc_addr =
  2745. (uint8_t *)QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx);
  2746. desc_size = sizeof(struct tcl_data_cmd);
  2747. HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, desc_size);
  2748. tcl_desc_ptr = (struct tcl_data_cmd *)
  2749. (QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx) + 1);
  2750. tcl_desc_ptr->buf_addr_info.return_buffer_manager =
  2751. HAL_RX_BUF_RBM_SW2_BM;
  2752. tcl_desc_ptr->addrx_en = 1; /* Address X search enable in ASE */
  2753. tcl_desc_ptr->encap_type = HAL_TX_ENCAP_TYPE_ETHERNET;
  2754. tcl_desc_ptr->packet_offset = 2; /* padding for alignment */
  2755. /* RX PIPE */
  2756. /*
  2757. * Transfer Ring: REO Ring
  2758. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  2759. * Event Ring: FW ring
  2760. * Event Ring Doorbell PA: FW Head Pointer Address
  2761. */
  2762. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(&pipe_in);
  2763. QDF_IPA_WDI_SETUP_INFO_NAT_EN(rx) = IPA_BYPASS_NAT;
  2764. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(rx) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  2765. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(rx) = 0;
  2766. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(rx) = 0;
  2767. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(rx) = 0;
  2768. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_METADATA_VALID(rx) = 0;
  2769. QDF_IPA_WDI_SETUP_INFO_HDR_METADATA_REG_VALID(rx) = 1;
  2770. QDF_IPA_WDI_SETUP_INFO_MODE(rx) = IPA_BASIC;
  2771. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(rx) = true;
  2772. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) = IPA_CLIENT_WLAN1_PROD;
  2773. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2774. ipa_res->rx_rdy_ring_base_paddr;
  2775. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2776. ipa_res->rx_rdy_ring_size;
  2777. /* REO Tail Pointer Address */
  2778. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2779. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2780. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2781. ipa_res->rx_refill_ring_base_paddr;
  2782. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2783. ipa_res->rx_refill_ring_size;
  2784. /* FW Head Pointer Address */
  2785. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2786. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2787. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) = soc->rx_pkt_tlv_size +
  2788. L3_HEADER_PADDING;
  2789. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(&pipe_in) = ipa_w2i_cb;
  2790. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(&pipe_in) = ipa_priv;
  2791. /* Connect WDI IPA PIPE */
  2792. ret = qdf_ipa_wdi_conn_pipes(&pipe_in, &pipe_out);
  2793. if (ret) {
  2794. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2795. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  2796. __func__, ret);
  2797. return QDF_STATUS_E_FAILURE;
  2798. }
  2799. /* IPA uC Doorbell registers */
  2800. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2801. "%s: Tx DB PA=0x%x, Rx DB PA=0x%x",
  2802. __func__,
  2803. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  2804. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  2805. ipa_res->tx_comp_doorbell_paddr =
  2806. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out);
  2807. ipa_res->tx_comp_doorbell_vaddr =
  2808. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_VA(&pipe_out);
  2809. ipa_res->rx_ready_doorbell_paddr =
  2810. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out);
  2811. soc->ipa_first_tx_db_access = true;
  2812. qdf_spinlock_create(&soc->ipa_rx_buf_map_lock);
  2813. soc->ipa_rx_buf_map_lock_initialized = true;
  2814. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2815. "%s: Tx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  2816. __func__,
  2817. "transfer_ring_base_pa",
  2818. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx),
  2819. "transfer_ring_size",
  2820. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx),
  2821. "transfer_ring_doorbell_pa",
  2822. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx),
  2823. "event_ring_base_pa",
  2824. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx),
  2825. "event_ring_size",
  2826. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx),
  2827. "event_ring_doorbell_pa",
  2828. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx),
  2829. "num_pkt_buffers",
  2830. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx),
  2831. "tx_comp_doorbell_paddr",
  2832. (void *)ipa_res->tx_comp_doorbell_paddr);
  2833. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2834. "%s: Rx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  2835. __func__,
  2836. "transfer_ring_base_pa",
  2837. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx),
  2838. "transfer_ring_size",
  2839. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx),
  2840. "transfer_ring_doorbell_pa",
  2841. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx),
  2842. "event_ring_base_pa",
  2843. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx),
  2844. "event_ring_size",
  2845. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx),
  2846. "event_ring_doorbell_pa",
  2847. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx),
  2848. "num_pkt_buffers",
  2849. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(rx),
  2850. "tx_comp_doorbell_paddr",
  2851. (void *)ipa_res->rx_ready_doorbell_paddr);
  2852. return QDF_STATUS_SUCCESS;
  2853. }
  2854. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  2855. qdf_ipa_client_type_t prod_client,
  2856. qdf_ipa_client_type_t cons_client,
  2857. uint8_t session_id, bool is_ipv6_enabled,
  2858. qdf_ipa_wdi_hdl_t hdl)
  2859. {
  2860. qdf_ipa_wdi_reg_intf_in_params_t in;
  2861. qdf_ipa_wdi_hdr_info_t hdr_info;
  2862. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  2863. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  2864. int ret = -EINVAL;
  2865. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2866. "%s: Add Partial hdr: %s, "QDF_MAC_ADDR_FMT,
  2867. __func__, ifname, QDF_MAC_ADDR_REF(mac_addr));
  2868. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2869. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  2870. /* IPV4 header */
  2871. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  2872. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  2873. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2874. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(&hdr_info) = IPA_HDR_L2_ETHERNET_II;
  2875. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2876. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2877. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  2878. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  2879. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2880. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  2881. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(&in) =
  2882. htonl(session_id << 16);
  2883. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(&in) = htonl(0x00FF0000);
  2884. /* IPV6 header */
  2885. if (is_ipv6_enabled) {
  2886. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  2887. DP_IPA_UC_WLAN_TX_HDR_LEN);
  2888. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  2889. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  2890. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  2891. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2892. }
  2893. ret = qdf_ipa_wdi_reg_intf(&in);
  2894. if (ret) {
  2895. dp_err("ipa_wdi_reg_intf: register IPA interface failed: ret=%d",
  2896. ret);
  2897. return QDF_STATUS_E_FAILURE;
  2898. }
  2899. return QDF_STATUS_SUCCESS;
  2900. }
  2901. #endif /* CONFIG_IPA_WDI_UNIFIED_API */
  2902. QDF_STATUS dp_ipa_cleanup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2903. uint32_t tx_pipe_handle, uint32_t rx_pipe_handle,
  2904. qdf_ipa_wdi_hdl_t hdl)
  2905. {
  2906. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2907. QDF_STATUS status = QDF_STATUS_SUCCESS;
  2908. struct dp_pdev *pdev;
  2909. int ret;
  2910. ret = qdf_ipa_wdi_disconn_pipes(hdl);
  2911. if (ret) {
  2912. dp_err("ipa_wdi_disconn_pipes: IPA pipe cleanup failed: ret=%d",
  2913. ret);
  2914. status = QDF_STATUS_E_FAILURE;
  2915. }
  2916. if (soc->ipa_rx_buf_map_lock_initialized) {
  2917. qdf_spinlock_destroy(&soc->ipa_rx_buf_map_lock);
  2918. soc->ipa_rx_buf_map_lock_initialized = false;
  2919. }
  2920. pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2921. if (qdf_unlikely(!pdev)) {
  2922. dp_err_rl("Invalid pdev for pdev_id %d", pdev_id);
  2923. status = QDF_STATUS_E_FAILURE;
  2924. goto exit;
  2925. }
  2926. dp_ipa_unmap_ring_doorbell_paddr(pdev);
  2927. dp_ipa_unmap_rx_alt_ring_doorbell_paddr(pdev);
  2928. exit:
  2929. return status;
  2930. }
  2931. QDF_STATUS dp_ipa_cleanup_iface(char *ifname, bool is_ipv6_enabled,
  2932. qdf_ipa_wdi_hdl_t hdl)
  2933. {
  2934. int ret;
  2935. ret = qdf_ipa_wdi_dereg_intf(ifname, hdl);
  2936. if (ret) {
  2937. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2938. "%s: ipa_wdi_dereg_intf: IPA pipe deregistration failed: ret=%d",
  2939. __func__, ret);
  2940. return QDF_STATUS_E_FAILURE;
  2941. }
  2942. return QDF_STATUS_SUCCESS;
  2943. }
  2944. #ifdef IPA_SET_RESET_TX_DB_PA
  2945. #define DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res) \
  2946. dp_ipa_set_tx_doorbell_paddr((soc), (ipa_res))
  2947. #define DP_IPA_RESET_TX_DB_PA(soc, ipa_res) \
  2948. dp_ipa_reset_tx_doorbell_pa((soc), (ipa_res))
  2949. #else
  2950. #define DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res)
  2951. #define DP_IPA_RESET_TX_DB_PA(soc, ipa_res)
  2952. #endif
  2953. QDF_STATUS dp_ipa_enable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2954. qdf_ipa_wdi_hdl_t hdl)
  2955. {
  2956. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2957. struct dp_pdev *pdev =
  2958. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2959. struct dp_ipa_resources *ipa_res;
  2960. QDF_STATUS result;
  2961. if (!pdev) {
  2962. dp_err("Invalid instance");
  2963. return QDF_STATUS_E_FAILURE;
  2964. }
  2965. ipa_res = &pdev->ipa_resource;
  2966. qdf_atomic_set(&soc->ipa_pipes_enabled, 1);
  2967. DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res);
  2968. if (!ipa_config_is_opt_wifi_dp_enabled())
  2969. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, true,
  2970. __func__, __LINE__);
  2971. result = qdf_ipa_wdi_enable_pipes(hdl);
  2972. if (result) {
  2973. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2974. "%s: Enable WDI PIPE fail, code %d",
  2975. __func__, result);
  2976. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  2977. DP_IPA_RESET_TX_DB_PA(soc, ipa_res);
  2978. if (qdf_atomic_read(&soc->ipa_mapped))
  2979. dp_ipa_handle_rx_buf_pool_smmu_mapping(
  2980. soc, pdev, false, __func__, __LINE__);
  2981. return QDF_STATUS_E_FAILURE;
  2982. }
  2983. if (soc->ipa_first_tx_db_access) {
  2984. dp_ipa_tx_comp_ring_init_hp(soc, ipa_res);
  2985. soc->ipa_first_tx_db_access = false;
  2986. }
  2987. return QDF_STATUS_SUCCESS;
  2988. }
  2989. QDF_STATUS dp_ipa_disable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2990. qdf_ipa_wdi_hdl_t hdl)
  2991. {
  2992. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2993. struct dp_pdev *pdev =
  2994. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2995. QDF_STATUS result;
  2996. struct dp_ipa_resources *ipa_res;
  2997. if (!pdev) {
  2998. dp_err("Invalid instance");
  2999. return QDF_STATUS_E_FAILURE;
  3000. }
  3001. ipa_res = &pdev->ipa_resource;
  3002. qdf_sleep(TX_COMP_DRAIN_WAIT_TIMEOUT_MS);
  3003. /*
  3004. * Reset the tx completion doorbell address before invoking IPA disable
  3005. * pipes API to ensure that there is no access to IPA tx doorbell
  3006. * address post disable pipes.
  3007. */
  3008. DP_IPA_RESET_TX_DB_PA(soc, ipa_res);
  3009. result = qdf_ipa_wdi_disable_pipes(hdl);
  3010. if (result) {
  3011. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3012. "%s: Disable WDI PIPE fail, code %d",
  3013. __func__, result);
  3014. qdf_assert_always(0);
  3015. return QDF_STATUS_E_FAILURE;
  3016. }
  3017. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  3018. if (qdf_atomic_read(&soc->ipa_mapped))
  3019. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, false,
  3020. __func__, __LINE__);
  3021. return result ? QDF_STATUS_E_FAILURE : QDF_STATUS_SUCCESS;
  3022. }
  3023. QDF_STATUS dp_ipa_set_perf_level(int client, uint32_t max_supported_bw_mbps,
  3024. qdf_ipa_wdi_hdl_t hdl)
  3025. {
  3026. qdf_ipa_wdi_perf_profile_t profile;
  3027. QDF_STATUS result;
  3028. profile.client = client;
  3029. profile.max_supported_bw_mbps = max_supported_bw_mbps;
  3030. result = qdf_ipa_wdi_set_perf_profile(hdl, &profile);
  3031. if (result) {
  3032. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3033. "%s: ipa_wdi_set_perf_profile fail, code %d",
  3034. __func__, result);
  3035. return QDF_STATUS_E_FAILURE;
  3036. }
  3037. return QDF_STATUS_SUCCESS;
  3038. }
  3039. /**
  3040. * dp_ipa_intrabss_send() - send IPA RX intra-bss frames
  3041. * @pdev: pdev
  3042. * @vdev: vdev
  3043. * @nbuf: skb
  3044. *
  3045. * Return: nbuf if TX fails and NULL if TX succeeds
  3046. */
  3047. static qdf_nbuf_t dp_ipa_intrabss_send(struct dp_pdev *pdev,
  3048. struct dp_vdev *vdev,
  3049. qdf_nbuf_t nbuf)
  3050. {
  3051. struct dp_peer *vdev_peer;
  3052. uint16_t len;
  3053. vdev_peer = dp_vdev_bss_peer_ref_n_get(pdev->soc, vdev, DP_MOD_ID_IPA);
  3054. if (qdf_unlikely(!vdev_peer))
  3055. return nbuf;
  3056. if (qdf_unlikely(!vdev_peer->txrx_peer)) {
  3057. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  3058. return nbuf;
  3059. }
  3060. qdf_mem_zero(nbuf->cb, sizeof(nbuf->cb));
  3061. len = qdf_nbuf_len(nbuf);
  3062. if (dp_tx_send((struct cdp_soc_t *)pdev->soc, vdev->vdev_id, nbuf)) {
  3063. DP_PEER_PER_PKT_STATS_INC_PKT(vdev_peer->txrx_peer,
  3064. rx.intra_bss.fail, 1, len,
  3065. 0);
  3066. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  3067. return nbuf;
  3068. }
  3069. DP_PEER_PER_PKT_STATS_INC_PKT(vdev_peer->txrx_peer,
  3070. rx.intra_bss.pkts, 1, len, 0);
  3071. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  3072. return NULL;
  3073. }
  3074. #ifdef IPA_OPT_WIFI_DP
  3075. /**
  3076. * dp_ipa_rx_super_rule_setup()- pass cce super rule params to fw from ipa
  3077. *
  3078. * @soc_hdl: cdp soc
  3079. * @flt_params: filter tuple
  3080. *
  3081. * Return: QDF_STATUS
  3082. */
  3083. QDF_STATUS dp_ipa_rx_super_rule_setup(struct cdp_soc_t *soc_hdl,
  3084. void *flt_params)
  3085. {
  3086. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3087. return htt_h2t_rx_cce_super_rule_setup(soc->htt_handle, flt_params);
  3088. }
  3089. /**
  3090. * dp_ipa_wdi_opt_dpath_notify_flt_add_rem_cb()- send cce super rule filter
  3091. * add/remove result to ipa
  3092. *
  3093. * @flt0_rslt : result for filter0 add/remove
  3094. * @flt1_rslt : result for filter1 add/remove
  3095. *
  3096. * Return: void
  3097. */
  3098. void dp_ipa_wdi_opt_dpath_notify_flt_add_rem_cb(int flt0_rslt, int flt1_rslt)
  3099. {
  3100. wlan_ipa_wdi_opt_dpath_notify_flt_add_rem_cb(flt0_rslt, flt1_rslt);
  3101. }
  3102. int dp_ipa_pcie_link_up(struct cdp_soc_t *soc_hdl)
  3103. {
  3104. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3105. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  3106. int response = 0;
  3107. response = hif_prevent_l1((hal_soc->hif_handle));
  3108. return response;
  3109. }
  3110. void dp_ipa_pcie_link_down(struct cdp_soc_t *soc_hdl)
  3111. {
  3112. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3113. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  3114. hif_allow_l1(hal_soc->hif_handle);
  3115. }
  3116. /**
  3117. * dp_ipa_wdi_opt_dpath_notify_flt_rlsd()- send cce super rule release
  3118. * notification to ipa
  3119. *
  3120. * @flt0_rslt : result for filter0 release
  3121. * @flt1_rslt : result for filter1 release
  3122. *
  3123. *Return: void
  3124. */
  3125. void dp_ipa_wdi_opt_dpath_notify_flt_rlsd(int flt0_rslt, int flt1_rslt)
  3126. {
  3127. wlan_ipa_wdi_opt_dpath_notify_flt_rlsd(flt0_rslt, flt1_rslt);
  3128. }
  3129. /**
  3130. * dp_ipa_wdi_opt_dpath_notify_flt_rsvd()- send cce super rule reserve
  3131. * notification to ipa
  3132. *
  3133. *@is_success : result of filter reservatiom
  3134. *
  3135. *Return: void
  3136. */
  3137. void dp_ipa_wdi_opt_dpath_notify_flt_rsvd(bool is_success)
  3138. {
  3139. wlan_ipa_wdi_opt_dpath_notify_flt_rsvd(is_success);
  3140. }
  3141. #endif
  3142. #ifdef IPA_WDS_EASYMESH_FEATURE
  3143. /**
  3144. * dp_ipa_peer_check() - Check for peer for given mac
  3145. * @soc: dp soc object
  3146. * @peer_mac_addr: peer mac address
  3147. * @vdev_id: vdev id
  3148. *
  3149. * Return: true if peer is found, else false
  3150. */
  3151. static inline bool dp_ipa_peer_check(struct dp_soc *soc,
  3152. uint8_t *peer_mac_addr, uint8_t vdev_id)
  3153. {
  3154. struct dp_ast_entry *ast_entry = NULL;
  3155. struct dp_peer *peer = NULL;
  3156. qdf_spin_lock_bh(&soc->ast_lock);
  3157. ast_entry = dp_peer_ast_hash_find_soc(soc, peer_mac_addr);
  3158. if ((!ast_entry) ||
  3159. (ast_entry->delete_in_progress && !ast_entry->callback)) {
  3160. qdf_spin_unlock_bh(&soc->ast_lock);
  3161. return false;
  3162. }
  3163. peer = dp_peer_get_ref_by_id(soc, ast_entry->peer_id,
  3164. DP_MOD_ID_IPA);
  3165. if (!peer) {
  3166. qdf_spin_unlock_bh(&soc->ast_lock);
  3167. return false;
  3168. } else {
  3169. if (peer->vdev->vdev_id == vdev_id) {
  3170. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3171. qdf_spin_unlock_bh(&soc->ast_lock);
  3172. return true;
  3173. }
  3174. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3175. qdf_spin_unlock_bh(&soc->ast_lock);
  3176. return false;
  3177. }
  3178. }
  3179. #else
  3180. static inline bool dp_ipa_peer_check(struct dp_soc *soc,
  3181. uint8_t *peer_mac_addr, uint8_t vdev_id)
  3182. {
  3183. struct cdp_peer_info peer_info = {0};
  3184. struct dp_peer *peer = NULL;
  3185. DP_PEER_INFO_PARAMS_INIT(&peer_info, vdev_id, peer_mac_addr, false,
  3186. CDP_WILD_PEER_TYPE);
  3187. peer = dp_peer_hash_find_wrapper(soc, &peer_info, DP_MOD_ID_IPA);
  3188. if (peer) {
  3189. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3190. return true;
  3191. } else {
  3192. return false;
  3193. }
  3194. }
  3195. #endif
  3196. bool dp_ipa_rx_intrabss_fwd(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3197. qdf_nbuf_t nbuf, bool *fwd_success)
  3198. {
  3199. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3200. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3201. DP_MOD_ID_IPA);
  3202. struct dp_pdev *pdev;
  3203. qdf_nbuf_t nbuf_copy;
  3204. uint8_t da_is_bcmc;
  3205. struct ethhdr *eh;
  3206. bool status = false;
  3207. *fwd_success = false; /* set default as failure */
  3208. /*
  3209. * WDI 3.0 skb->cb[] info from IPA driver
  3210. * skb->cb[0] = vdev_id
  3211. * skb->cb[1].bit#1 = da_is_bcmc
  3212. */
  3213. da_is_bcmc = ((uint8_t)nbuf->cb[1]) & 0x2;
  3214. if (qdf_unlikely(!vdev))
  3215. return false;
  3216. pdev = vdev->pdev;
  3217. if (qdf_unlikely(!pdev))
  3218. goto out;
  3219. /* no fwd for station mode and just pass up to stack */
  3220. if (vdev->opmode == wlan_op_mode_sta)
  3221. goto out;
  3222. if (da_is_bcmc) {
  3223. nbuf_copy = qdf_nbuf_copy(nbuf);
  3224. if (!nbuf_copy)
  3225. goto out;
  3226. if (dp_ipa_intrabss_send(pdev, vdev, nbuf_copy))
  3227. qdf_nbuf_free(nbuf_copy);
  3228. else
  3229. *fwd_success = true;
  3230. /* return false to pass original pkt up to stack */
  3231. goto out;
  3232. }
  3233. eh = (struct ethhdr *)qdf_nbuf_data(nbuf);
  3234. if (!qdf_mem_cmp(eh->h_dest, vdev->mac_addr.raw, QDF_MAC_ADDR_SIZE))
  3235. goto out;
  3236. if (!dp_ipa_peer_check(soc, eh->h_dest, vdev->vdev_id))
  3237. goto out;
  3238. if (!dp_ipa_peer_check(soc, eh->h_source, vdev->vdev_id))
  3239. goto out;
  3240. /*
  3241. * In intra-bss forwarding scenario, skb is allocated by IPA driver.
  3242. * Need to add skb to internal tracking table to avoid nbuf memory
  3243. * leak check for unallocated skb.
  3244. */
  3245. qdf_net_buf_debug_acquire_skb(nbuf, __FILE__, __LINE__);
  3246. if (dp_ipa_intrabss_send(pdev, vdev, nbuf))
  3247. qdf_nbuf_free(nbuf);
  3248. else
  3249. *fwd_success = true;
  3250. status = true;
  3251. out:
  3252. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_IPA);
  3253. return status;
  3254. }
  3255. #ifdef MDM_PLATFORM
  3256. bool dp_ipa_is_mdm_platform(void)
  3257. {
  3258. return true;
  3259. }
  3260. #else
  3261. bool dp_ipa_is_mdm_platform(void)
  3262. {
  3263. return false;
  3264. }
  3265. #endif
  3266. /**
  3267. * dp_ipa_frag_nbuf_linearize() - linearize nbuf for IPA
  3268. * @soc: soc
  3269. * @nbuf: source skb
  3270. *
  3271. * Return: new nbuf if success and otherwise NULL
  3272. */
  3273. static qdf_nbuf_t dp_ipa_frag_nbuf_linearize(struct dp_soc *soc,
  3274. qdf_nbuf_t nbuf)
  3275. {
  3276. uint8_t *src_nbuf_data;
  3277. uint8_t *dst_nbuf_data;
  3278. qdf_nbuf_t dst_nbuf;
  3279. qdf_nbuf_t temp_nbuf = nbuf;
  3280. uint32_t nbuf_len = qdf_nbuf_len(nbuf);
  3281. bool is_nbuf_head = true;
  3282. uint32_t copy_len = 0;
  3283. uint16_t buf_size;
  3284. buf_size = wlan_cfg_rx_buffer_size(soc->wlan_cfg_ctx);
  3285. dst_nbuf = qdf_nbuf_alloc(soc->osdev, buf_size,
  3286. RX_BUFFER_RESERVATION,
  3287. RX_DATA_BUFFER_ALIGNMENT, FALSE);
  3288. if (!dst_nbuf) {
  3289. dp_err_rl("nbuf allocate fail");
  3290. return NULL;
  3291. }
  3292. if ((nbuf_len + L3_HEADER_PADDING) > buf_size) {
  3293. qdf_nbuf_free(dst_nbuf);
  3294. dp_err_rl("nbuf is jumbo data");
  3295. return NULL;
  3296. }
  3297. /* prepeare to copy all data into new skb */
  3298. dst_nbuf_data = qdf_nbuf_data(dst_nbuf);
  3299. while (temp_nbuf) {
  3300. src_nbuf_data = qdf_nbuf_data(temp_nbuf);
  3301. /* first head nbuf */
  3302. if (is_nbuf_head) {
  3303. qdf_mem_copy(dst_nbuf_data, src_nbuf_data,
  3304. soc->rx_pkt_tlv_size);
  3305. /* leave extra 2 bytes L3_HEADER_PADDING */
  3306. dst_nbuf_data += (soc->rx_pkt_tlv_size +
  3307. L3_HEADER_PADDING);
  3308. src_nbuf_data += soc->rx_pkt_tlv_size;
  3309. copy_len = qdf_nbuf_headlen(temp_nbuf) -
  3310. soc->rx_pkt_tlv_size;
  3311. temp_nbuf = qdf_nbuf_get_ext_list(temp_nbuf);
  3312. is_nbuf_head = false;
  3313. } else {
  3314. copy_len = qdf_nbuf_len(temp_nbuf);
  3315. temp_nbuf = qdf_nbuf_queue_next(temp_nbuf);
  3316. }
  3317. qdf_mem_copy(dst_nbuf_data, src_nbuf_data, copy_len);
  3318. dst_nbuf_data += copy_len;
  3319. }
  3320. qdf_nbuf_set_len(dst_nbuf, nbuf_len);
  3321. /* copy is done, free original nbuf */
  3322. qdf_nbuf_free(nbuf);
  3323. return dst_nbuf;
  3324. }
  3325. qdf_nbuf_t dp_ipa_handle_rx_reo_reinject(struct dp_soc *soc, qdf_nbuf_t nbuf)
  3326. {
  3327. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  3328. return nbuf;
  3329. /* WLAN IPA is run-time disabled */
  3330. if (!qdf_atomic_read(&soc->ipa_pipes_enabled))
  3331. return nbuf;
  3332. if (!qdf_nbuf_is_frag(nbuf))
  3333. return nbuf;
  3334. /* linearize skb for IPA */
  3335. return dp_ipa_frag_nbuf_linearize(soc, nbuf);
  3336. }
  3337. QDF_STATUS dp_ipa_tx_buf_smmu_mapping(
  3338. struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  3339. const char *func, uint32_t line)
  3340. {
  3341. QDF_STATUS ret;
  3342. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3343. struct dp_pdev *pdev =
  3344. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3345. if (!pdev) {
  3346. dp_err("Invalid instance");
  3347. return QDF_STATUS_E_FAILURE;
  3348. }
  3349. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  3350. dp_debug("SMMU S1 disabled");
  3351. return QDF_STATUS_SUCCESS;
  3352. }
  3353. ret = __dp_ipa_tx_buf_smmu_mapping(soc, pdev, true, func, line);
  3354. if (ret)
  3355. return ret;
  3356. ret = dp_ipa_tx_alt_buf_smmu_mapping(soc, pdev, true, func, line);
  3357. if (ret)
  3358. __dp_ipa_tx_buf_smmu_mapping(soc, pdev, false, func, line);
  3359. return ret;
  3360. }
  3361. QDF_STATUS dp_ipa_tx_buf_smmu_unmapping(
  3362. struct cdp_soc_t *soc_hdl, uint8_t pdev_id, const char *func,
  3363. uint32_t line)
  3364. {
  3365. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3366. struct dp_pdev *pdev =
  3367. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3368. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  3369. dp_debug("SMMU S1 disabled");
  3370. return QDF_STATUS_SUCCESS;
  3371. }
  3372. if (!pdev) {
  3373. dp_err("Invalid pdev instance pdev_id:%d", pdev_id);
  3374. return QDF_STATUS_E_FAILURE;
  3375. }
  3376. if (__dp_ipa_tx_buf_smmu_mapping(soc, pdev, false, func, line) ||
  3377. dp_ipa_tx_alt_buf_smmu_mapping(soc, pdev, false, func, line))
  3378. return QDF_STATUS_E_FAILURE;
  3379. return QDF_STATUS_SUCCESS;
  3380. }
  3381. QDF_STATUS dp_ipa_rx_buf_pool_smmu_mapping(
  3382. struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  3383. bool create, const char *func, uint32_t line)
  3384. {
  3385. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3386. struct dp_pdev *pdev =
  3387. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3388. if (!pdev) {
  3389. dp_err("Invalid instance");
  3390. return QDF_STATUS_E_FAILURE;
  3391. }
  3392. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  3393. dp_debug("SMMU S1 disabled");
  3394. return QDF_STATUS_SUCCESS;
  3395. }
  3396. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, create, func, line);
  3397. return QDF_STATUS_SUCCESS;
  3398. }
  3399. #ifdef IPA_WDS_EASYMESH_FEATURE
  3400. QDF_STATUS dp_ipa_ast_create(struct cdp_soc_t *soc_hdl,
  3401. qdf_ipa_ast_info_type_t *data)
  3402. {
  3403. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3404. uint8_t *rx_tlv_hdr;
  3405. struct dp_peer *peer;
  3406. struct hal_rx_msdu_metadata msdu_metadata;
  3407. qdf_ipa_ast_info_type_t *ast_info;
  3408. if (!data) {
  3409. dp_err("Data is NULL !!!");
  3410. return QDF_STATUS_E_FAILURE;
  3411. }
  3412. ast_info = data;
  3413. rx_tlv_hdr = qdf_nbuf_data(ast_info->skb);
  3414. peer = dp_peer_get_ref_by_id(soc, ast_info->ta_peer_id,
  3415. DP_MOD_ID_IPA);
  3416. if (!peer) {
  3417. dp_err("Peer is NULL !!!!");
  3418. return QDF_STATUS_E_FAILURE;
  3419. }
  3420. hal_rx_msdu_metadata_get(soc->hal_soc, rx_tlv_hdr, &msdu_metadata);
  3421. dp_rx_ipa_wds_srcport_learn(soc, peer, ast_info->skb, msdu_metadata,
  3422. ast_info->mac_addr_ad4_valid,
  3423. ast_info->first_msdu_in_mpdu_flag);
  3424. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3425. return QDF_STATUS_SUCCESS;
  3426. }
  3427. #endif
  3428. #ifdef QCA_ENHANCED_STATS_SUPPORT
  3429. QDF_STATUS dp_ipa_update_peer_rx_stats(struct cdp_soc_t *soc,
  3430. uint8_t vdev_id, uint8_t *peer_mac,
  3431. qdf_nbuf_t nbuf)
  3432. {
  3433. struct dp_peer *peer = dp_peer_find_hash_find((struct dp_soc *)soc,
  3434. peer_mac, 0, vdev_id,
  3435. DP_MOD_ID_IPA);
  3436. struct dp_txrx_peer *txrx_peer;
  3437. uint8_t da_is_bcmc;
  3438. qdf_ether_header_t *eh;
  3439. if (!peer)
  3440. return QDF_STATUS_E_FAILURE;
  3441. txrx_peer = dp_get_txrx_peer(peer);
  3442. if (!txrx_peer) {
  3443. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3444. return QDF_STATUS_E_FAILURE;
  3445. }
  3446. da_is_bcmc = ((uint8_t)nbuf->cb[1]) & 0x2;
  3447. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3448. if (da_is_bcmc) {
  3449. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, rx.multicast, 1,
  3450. qdf_nbuf_len(nbuf), 0);
  3451. if (QDF_IS_ADDR_BROADCAST(eh->ether_dhost))
  3452. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, rx.bcast,
  3453. 1, qdf_nbuf_len(nbuf), 0);
  3454. }
  3455. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3456. return QDF_STATUS_SUCCESS;
  3457. }
  3458. void
  3459. dp_peer_aggregate_tid_stats(struct dp_peer *peer)
  3460. {
  3461. uint8_t i = 0;
  3462. struct dp_rx_tid *rx_tid = NULL;
  3463. struct cdp_pkt_info rx_total = {0};
  3464. struct dp_txrx_peer *txrx_peer = NULL;
  3465. if (!peer->rx_tid)
  3466. return;
  3467. txrx_peer = dp_get_txrx_peer(peer);
  3468. if (!txrx_peer)
  3469. return;
  3470. for (i = 0; i < DP_MAX_TIDS; i++) {
  3471. rx_tid = &peer->rx_tid[i];
  3472. rx_total.num += rx_tid->rx_msdu_cnt.num;
  3473. rx_total.bytes += rx_tid->rx_msdu_cnt.bytes;
  3474. }
  3475. DP_PEER_PER_PKT_STATS_UPD(txrx_peer, rx.rx_total.num,
  3476. rx_total.num, 0);
  3477. DP_PEER_PER_PKT_STATS_UPD(txrx_peer, rx.rx_total.bytes,
  3478. rx_total.bytes, 0);
  3479. }
  3480. /**
  3481. * dp_ipa_update_vdev_stats(): update vdev stats
  3482. * @soc: soc handle
  3483. * @srcobj: DP_PEER object
  3484. * @arg: point to vdev stats structure
  3485. *
  3486. * Return: void
  3487. */
  3488. static inline
  3489. void dp_ipa_update_vdev_stats(struct dp_soc *soc, struct dp_peer *srcobj,
  3490. void *arg)
  3491. {
  3492. dp_peer_aggregate_tid_stats(srcobj);
  3493. dp_update_vdev_stats(soc, srcobj, arg);
  3494. }
  3495. /**
  3496. * dp_ipa_aggregate_vdev_stats - Aggregate vdev_stats
  3497. * @vdev: Data path vdev
  3498. * @vdev_stats: buffer to hold vdev stats
  3499. *
  3500. * Return: void
  3501. */
  3502. static inline
  3503. void dp_ipa_aggregate_vdev_stats(struct dp_vdev *vdev,
  3504. struct cdp_vdev_stats *vdev_stats)
  3505. {
  3506. struct dp_soc *soc = NULL;
  3507. if (!vdev || !vdev->pdev)
  3508. return;
  3509. soc = vdev->pdev->soc;
  3510. dp_update_vdev_ingress_stats(vdev);
  3511. qdf_mem_copy(vdev_stats, &vdev->stats, sizeof(vdev->stats));
  3512. dp_vdev_iterate_peer(vdev, dp_ipa_update_vdev_stats, vdev_stats,
  3513. DP_MOD_ID_GENERIC_STATS);
  3514. dp_update_vdev_rate_stats(vdev_stats, &vdev->stats);
  3515. vdev_stats->tx.ucast.num = vdev_stats->tx.tx_ucast_total.num;
  3516. vdev_stats->tx.ucast.bytes = vdev_stats->tx.tx_ucast_total.bytes;
  3517. vdev_stats->tx.tx_success.num = vdev_stats->tx.tx_ucast_success.num;
  3518. vdev_stats->tx.tx_success.bytes = vdev_stats->tx.tx_ucast_success.bytes;
  3519. if (vdev_stats->rx.rx_total.num >= vdev_stats->rx.multicast.num)
  3520. vdev_stats->rx.unicast.num = vdev_stats->rx.rx_total.num -
  3521. vdev_stats->rx.multicast.num;
  3522. if (vdev_stats->rx.rx_total.bytes >= vdev_stats->rx.multicast.bytes)
  3523. vdev_stats->rx.unicast.bytes = vdev_stats->rx.rx_total.bytes -
  3524. vdev_stats->rx.multicast.bytes;
  3525. vdev_stats->rx.to_stack.num = vdev_stats->rx.rx_total.num;
  3526. vdev_stats->rx.to_stack.bytes = vdev_stats->rx.rx_total.bytes;
  3527. }
  3528. /**
  3529. * dp_ipa_aggregate_pdev_stats - Aggregate pdev stats
  3530. * @pdev: Data path pdev
  3531. *
  3532. * Return: void
  3533. */
  3534. static inline
  3535. void dp_ipa_aggregate_pdev_stats(struct dp_pdev *pdev)
  3536. {
  3537. struct dp_vdev *vdev = NULL;
  3538. struct dp_soc *soc;
  3539. struct cdp_vdev_stats *vdev_stats =
  3540. qdf_mem_malloc_atomic(sizeof(struct cdp_vdev_stats));
  3541. if (!vdev_stats) {
  3542. dp_err("%pK: DP alloc failure - unable to get alloc vdev stats",
  3543. pdev->soc);
  3544. return;
  3545. }
  3546. soc = pdev->soc;
  3547. qdf_mem_zero(&pdev->stats.tx, sizeof(pdev->stats.tx));
  3548. qdf_mem_zero(&pdev->stats.rx, sizeof(pdev->stats.rx));
  3549. qdf_mem_zero(&pdev->stats.tx_i, sizeof(pdev->stats.tx_i));
  3550. qdf_mem_zero(&pdev->stats.rx_i, sizeof(pdev->stats.rx_i));
  3551. qdf_spin_lock_bh(&pdev->vdev_list_lock);
  3552. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3553. dp_ipa_aggregate_vdev_stats(vdev, vdev_stats);
  3554. dp_update_pdev_stats(pdev, vdev_stats);
  3555. dp_update_pdev_ingress_stats(pdev, vdev);
  3556. }
  3557. qdf_spin_unlock_bh(&pdev->vdev_list_lock);
  3558. qdf_mem_free(vdev_stats);
  3559. }
  3560. /**
  3561. * dp_ipa_get_peer_stats - Get peer stats
  3562. * @peer: Data path peer
  3563. * @peer_stats: buffer to hold peer stats
  3564. *
  3565. * Return: void
  3566. */
  3567. static
  3568. void dp_ipa_get_peer_stats(struct dp_peer *peer,
  3569. struct cdp_peer_stats *peer_stats)
  3570. {
  3571. dp_peer_aggregate_tid_stats(peer);
  3572. dp_get_peer_stats(peer, peer_stats);
  3573. peer_stats->tx.tx_success.num =
  3574. peer_stats->tx.tx_ucast_success.num;
  3575. peer_stats->tx.tx_success.bytes =
  3576. peer_stats->tx.tx_ucast_success.bytes;
  3577. peer_stats->tx.ucast.num =
  3578. peer_stats->tx.tx_ucast_total.num;
  3579. peer_stats->tx.ucast.bytes =
  3580. peer_stats->tx.tx_ucast_total.bytes;
  3581. if (peer_stats->rx.rx_total.num >= peer_stats->rx.multicast.num)
  3582. peer_stats->rx.unicast.num = peer_stats->rx.rx_total.num -
  3583. peer_stats->rx.multicast.num;
  3584. if (peer_stats->rx.rx_total.bytes >= peer_stats->rx.multicast.bytes)
  3585. peer_stats->rx.unicast.bytes = peer_stats->rx.rx_total.bytes -
  3586. peer_stats->rx.multicast.bytes;
  3587. }
  3588. QDF_STATUS
  3589. dp_ipa_txrx_get_pdev_stats(struct cdp_soc_t *soc, uint8_t pdev_id,
  3590. struct cdp_pdev_stats *pdev_stats)
  3591. {
  3592. struct dp_pdev *pdev =
  3593. dp_get_pdev_from_soc_pdev_id_wifi3((struct dp_soc *)soc,
  3594. pdev_id);
  3595. if (!pdev)
  3596. return QDF_STATUS_E_FAILURE;
  3597. dp_ipa_aggregate_pdev_stats(pdev);
  3598. qdf_mem_copy(pdev_stats, &pdev->stats, sizeof(struct cdp_pdev_stats));
  3599. return QDF_STATUS_SUCCESS;
  3600. }
  3601. int dp_ipa_txrx_get_vdev_stats(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3602. void *buf, bool is_aggregate)
  3603. {
  3604. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3605. struct cdp_vdev_stats *vdev_stats;
  3606. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3607. DP_MOD_ID_IPA);
  3608. if (!vdev)
  3609. return 1;
  3610. vdev_stats = (struct cdp_vdev_stats *)buf;
  3611. dp_ipa_aggregate_vdev_stats(vdev, buf);
  3612. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_IPA);
  3613. return 0;
  3614. }
  3615. QDF_STATUS dp_ipa_txrx_get_peer_stats(struct cdp_soc_t *soc, uint8_t vdev_id,
  3616. uint8_t *peer_mac,
  3617. struct cdp_peer_stats *peer_stats)
  3618. {
  3619. struct dp_peer *peer = NULL;
  3620. struct cdp_peer_info peer_info = { 0 };
  3621. DP_PEER_INFO_PARAMS_INIT(&peer_info, vdev_id, peer_mac, false,
  3622. CDP_WILD_PEER_TYPE);
  3623. peer = dp_peer_hash_find_wrapper((struct dp_soc *)soc, &peer_info,
  3624. DP_MOD_ID_IPA);
  3625. qdf_mem_zero(peer_stats, sizeof(struct cdp_peer_stats));
  3626. if (!peer)
  3627. return QDF_STATUS_E_FAILURE;
  3628. dp_ipa_get_peer_stats(peer, peer_stats);
  3629. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3630. return QDF_STATUS_SUCCESS;
  3631. }
  3632. #endif
  3633. /**
  3634. * dp_ipa_get_wdi_version() - Get WDI version
  3635. * @soc_hdl: data path soc handle
  3636. * @wdi_ver: Out parameter for wdi version
  3637. *
  3638. * Get WDI version based on soc arch
  3639. *
  3640. * Return: None
  3641. */
  3642. void dp_ipa_get_wdi_version(struct cdp_soc_t *soc_hdl, uint8_t *wdi_ver)
  3643. {
  3644. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3645. if (soc->arch_ops.ipa_get_wdi_ver)
  3646. soc->arch_ops.ipa_get_wdi_ver(wdi_ver);
  3647. else
  3648. *wdi_ver = IPA_WDI_3;
  3649. }
  3650. #endif