dp_be_tx.c 55 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "cdp_txrx_cmn_struct.h"
  20. #include "dp_types.h"
  21. #include "dp_tx.h"
  22. #include "dp_be_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "hal_tx.h"
  25. #include <hal_be_api.h>
  26. #include <hal_be_tx.h>
  27. #include <dp_htt.h>
  28. #include "dp_internal.h"
  29. #ifdef FEATURE_WDS
  30. #include "dp_txrx_wds.h"
  31. #endif
  32. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  33. #define DP_TX_BANK_LOCK_CREATE(lock) qdf_mutex_create(lock)
  34. #define DP_TX_BANK_LOCK_DESTROY(lock) qdf_mutex_destroy(lock)
  35. #define DP_TX_BANK_LOCK_ACQUIRE(lock) qdf_mutex_acquire(lock)
  36. #define DP_TX_BANK_LOCK_RELEASE(lock) qdf_mutex_release(lock)
  37. #else
  38. #define DP_TX_BANK_LOCK_CREATE(lock) qdf_spinlock_create(lock)
  39. #define DP_TX_BANK_LOCK_DESTROY(lock) qdf_spinlock_destroy(lock)
  40. #define DP_TX_BANK_LOCK_ACQUIRE(lock) qdf_spin_lock_bh(lock)
  41. #define DP_TX_BANK_LOCK_RELEASE(lock) qdf_spin_unlock_bh(lock)
  42. #endif
  43. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  44. #ifdef WLAN_MCAST_MLO
  45. /* MLO peer id for reinject*/
  46. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  47. #define MAX_GSN_NUM 0x0FFF
  48. #ifdef QCA_MULTIPASS_SUPPORT
  49. #define INVALID_VLAN_ID 0xFFFF
  50. #define MULTIPASS_WITH_VLAN_ID 0xFFFE
  51. /**
  52. * struct dp_mlo_mpass_buf - Multipass buffer
  53. * @vlan_id: vlan_id of frame
  54. * @nbuf: pointer to skb buf
  55. */
  56. struct dp_mlo_mpass_buf {
  57. uint16_t vlan_id;
  58. qdf_nbuf_t nbuf;
  59. };
  60. #endif
  61. #endif
  62. #endif
  63. #define DP_TX_WBM_COMPLETION_V3_VDEV_ID_GET(_var) \
  64. HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(_var)
  65. #define DP_TX_WBM_COMPLETION_V3_VALID_GET(_var) \
  66. HTT_TX_WBM_COMPLETION_V2_VALID_GET(_var)
  67. #define DP_TX_WBM_COMPLETION_V3_SW_PEER_ID_GET(_var) \
  68. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(_var)
  69. #define DP_TX_WBM_COMPLETION_V3_TID_NUM_GET(_var) \
  70. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(_var)
  71. #define DP_TX_WBM_COMPLETION_V3_SCH_CMD_ID_GET(_var) \
  72. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(_var)
  73. #define DP_TX_WBM_COMPLETION_V3_ACK_FRAME_RSSI_GET(_var) \
  74. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(_var)
  75. #define DP_TX_WBM_COMPLETION_V3_TRANSMIT_CNT_VALID_GET(_var) \
  76. HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_GET(_var)
  77. extern uint8_t sec_type_map[MAX_CDP_SEC_TYPE];
  78. #ifdef DP_TX_COMP_RING_DESC_SANITY_CHECK
  79. /*
  80. * Value to mark ring desc is invalidated by buffer_virt_addr_63_32 field
  81. * of WBM2SW ring Desc.
  82. */
  83. #define DP_TX_COMP_DESC_BUFF_VA_32BITS_HI_INVALIDATE 0x12121212
  84. /**
  85. * dp_tx_comp_desc_check_and_invalidate() - sanity check for ring desc and
  86. * invalidate it after each reaping
  87. * @tx_comp_hal_desc: ring desc virtual address
  88. * @r_tx_desc: pointer to current dp TX Desc pointer
  89. * @tx_desc_va: the original 64 bits Desc VA got from ring Desc
  90. * @hw_cc_done: HW cookie conversion done or not
  91. *
  92. * If HW CC is done, check the buffer_virt_addr_63_32 value to know if
  93. * ring Desc is stale or not. if HW CC is not done, then compare PA between
  94. * ring Desc and current TX desc.
  95. *
  96. * Return: None.
  97. */
  98. static inline
  99. void dp_tx_comp_desc_check_and_invalidate(void *tx_comp_hal_desc,
  100. struct dp_tx_desc_s **r_tx_desc,
  101. uint64_t tx_desc_va,
  102. bool hw_cc_done)
  103. {
  104. qdf_dma_addr_t desc_dma_addr;
  105. if (qdf_likely(hw_cc_done)) {
  106. /* Check upper 32 bits */
  107. if (DP_TX_COMP_DESC_BUFF_VA_32BITS_HI_INVALIDATE ==
  108. (tx_desc_va >> 32))
  109. *r_tx_desc = NULL;
  110. /* Invalidate the ring desc for 32 ~ 63 bits of VA */
  111. hal_tx_comp_set_desc_va_63_32(
  112. tx_comp_hal_desc,
  113. DP_TX_COMP_DESC_BUFF_VA_32BITS_HI_INVALIDATE);
  114. } else {
  115. /* Compare PA between ring desc and current TX desc stored */
  116. desc_dma_addr = hal_tx_comp_get_paddr(tx_comp_hal_desc);
  117. if (desc_dma_addr != (*r_tx_desc)->dma_addr)
  118. *r_tx_desc = NULL;
  119. }
  120. }
  121. #else
  122. static inline
  123. void dp_tx_comp_desc_check_and_invalidate(void *tx_comp_hal_desc,
  124. struct dp_tx_desc_s **r_tx_desc,
  125. uint64_t tx_desc_va,
  126. bool hw_cc_done)
  127. {
  128. }
  129. #endif
  130. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  131. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  132. void dp_tx_comp_get_params_from_hal_desc_be(struct dp_soc *soc,
  133. void *tx_comp_hal_desc,
  134. struct dp_tx_desc_s **r_tx_desc)
  135. {
  136. uint32_t tx_desc_id;
  137. uint64_t tx_desc_va = 0;
  138. bool hw_cc_done =
  139. hal_tx_comp_get_cookie_convert_done(tx_comp_hal_desc);
  140. if (qdf_likely(hw_cc_done)) {
  141. /* HW cookie conversion done */
  142. tx_desc_va = hal_tx_comp_get_desc_va(tx_comp_hal_desc);
  143. *r_tx_desc = (struct dp_tx_desc_s *)(uintptr_t)tx_desc_va;
  144. } else {
  145. /* SW do cookie conversion to VA */
  146. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  147. *r_tx_desc =
  148. (struct dp_tx_desc_s *)dp_cc_desc_find(soc, tx_desc_id);
  149. }
  150. dp_tx_comp_desc_check_and_invalidate(tx_comp_hal_desc,
  151. r_tx_desc, tx_desc_va,
  152. hw_cc_done);
  153. if (*r_tx_desc)
  154. (*r_tx_desc)->peer_id =
  155. dp_tx_comp_get_peer_id_be(soc,
  156. tx_comp_hal_desc);
  157. }
  158. #else
  159. void dp_tx_comp_get_params_from_hal_desc_be(struct dp_soc *soc,
  160. void *tx_comp_hal_desc,
  161. struct dp_tx_desc_s **r_tx_desc)
  162. {
  163. uint64_t tx_desc_va;
  164. tx_desc_va = hal_tx_comp_get_desc_va(tx_comp_hal_desc);
  165. *r_tx_desc = (struct dp_tx_desc_s *)(uintptr_t)tx_desc_va;
  166. dp_tx_comp_desc_check_and_invalidate(tx_comp_hal_desc,
  167. r_tx_desc,
  168. tx_desc_va,
  169. true);
  170. if (*r_tx_desc)
  171. (*r_tx_desc)->peer_id =
  172. dp_tx_comp_get_peer_id_be(soc,
  173. tx_comp_hal_desc);
  174. }
  175. #endif /* DP_HW_COOKIE_CONVERT_EXCEPTION */
  176. #else
  177. void dp_tx_comp_get_params_from_hal_desc_be(struct dp_soc *soc,
  178. void *tx_comp_hal_desc,
  179. struct dp_tx_desc_s **r_tx_desc)
  180. {
  181. uint32_t tx_desc_id;
  182. /* SW do cookie conversion to VA */
  183. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  184. *r_tx_desc =
  185. (struct dp_tx_desc_s *)dp_cc_desc_find(soc, tx_desc_id);
  186. dp_tx_comp_desc_check_and_invalidate(tx_comp_hal_desc,
  187. r_tx_desc, 0,
  188. false);
  189. if (*r_tx_desc)
  190. (*r_tx_desc)->peer_id =
  191. dp_tx_comp_get_peer_id_be(soc,
  192. tx_comp_hal_desc);
  193. }
  194. #endif /* DP_FEATURE_HW_COOKIE_CONVERSION */
  195. static inline
  196. void dp_tx_process_mec_notify_be(struct dp_soc *soc, uint8_t *status)
  197. {
  198. struct dp_vdev *vdev;
  199. uint8_t vdev_id;
  200. uint32_t *htt_desc = (uint32_t *)status;
  201. dp_assert_always_internal(soc->mec_fw_offload);
  202. /*
  203. * Get vdev id from HTT status word in case of MEC
  204. * notification
  205. */
  206. vdev_id = DP_TX_WBM_COMPLETION_V3_VDEV_ID_GET(htt_desc[4]);
  207. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  208. return;
  209. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  210. DP_MOD_ID_HTT_COMP);
  211. if (!vdev)
  212. return;
  213. dp_tx_mec_handler(vdev, status);
  214. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  215. }
  216. void dp_tx_process_htt_completion_be(struct dp_soc *soc,
  217. struct dp_tx_desc_s *tx_desc,
  218. uint8_t *status,
  219. uint8_t ring_id)
  220. {
  221. uint8_t tx_status;
  222. struct dp_pdev *pdev;
  223. struct dp_vdev *vdev = NULL;
  224. struct hal_tx_completion_status ts = {0};
  225. uint32_t *htt_desc = (uint32_t *)status;
  226. struct dp_txrx_peer *txrx_peer;
  227. dp_txrx_ref_handle txrx_ref_handle = NULL;
  228. struct cdp_tid_tx_stats *tid_stats = NULL;
  229. struct htt_soc *htt_handle;
  230. uint8_t vdev_id;
  231. uint16_t peer_id;
  232. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  233. htt_handle = (struct htt_soc *)soc->htt_handle;
  234. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  235. /*
  236. * There can be scenario where WBM consuming descriptor enqueued
  237. * from TQM2WBM first and TQM completion can happen before MEC
  238. * notification comes from FW2WBM. Avoid access any field of tx
  239. * descriptor in case of MEC notify.
  240. */
  241. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY)
  242. return dp_tx_process_mec_notify_be(soc, status);
  243. /*
  244. * If the descriptor is already freed in vdev_detach,
  245. * continue to next descriptor
  246. */
  247. if (qdf_unlikely(!tx_desc->flags)) {
  248. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  249. tx_desc->id);
  250. return;
  251. }
  252. if (qdf_unlikely(tx_desc->vdev_id == DP_INVALID_VDEV_ID)) {
  253. dp_tx_comp_info_rl("Invalid vdev_id %d", tx_desc->id);
  254. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  255. goto release_tx_desc;
  256. }
  257. pdev = tx_desc->pdev;
  258. if (qdf_unlikely(!pdev)) {
  259. dp_tx_comp_warn("The pdev in TX desc is NULL, dropped.");
  260. dp_tx_comp_warn("tx_status: %u", tx_status);
  261. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  262. goto release_tx_desc;
  263. }
  264. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  265. dp_tx_comp_info_rl("pdev in down state %d", tx_desc->id);
  266. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  267. goto release_tx_desc;
  268. }
  269. qdf_assert(tx_desc->pdev);
  270. vdev_id = tx_desc->vdev_id;
  271. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  272. DP_MOD_ID_HTT_COMP);
  273. if (qdf_unlikely(!vdev)) {
  274. dp_tx_comp_info_rl("Unable to get vdev ref %d", tx_desc->id);
  275. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  276. goto release_tx_desc;
  277. }
  278. switch (tx_status) {
  279. case HTT_TX_FW2WBM_TX_STATUS_OK:
  280. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  281. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  282. {
  283. uint8_t tid;
  284. uint8_t transmit_cnt_valid = 0;
  285. if (DP_TX_WBM_COMPLETION_V3_VALID_GET(htt_desc[3])) {
  286. ts.peer_id =
  287. DP_TX_WBM_COMPLETION_V3_SW_PEER_ID_GET(
  288. htt_desc[3]);
  289. ts.tid =
  290. DP_TX_WBM_COMPLETION_V3_TID_NUM_GET(
  291. htt_desc[3]);
  292. } else {
  293. ts.peer_id = HTT_INVALID_PEER;
  294. ts.tid = HTT_INVALID_TID;
  295. }
  296. ts.release_src = HAL_TX_COMP_RELEASE_SOURCE_FW;
  297. ts.ppdu_id =
  298. DP_TX_WBM_COMPLETION_V3_SCH_CMD_ID_GET(
  299. htt_desc[2]);
  300. ts.ack_frame_rssi =
  301. DP_TX_WBM_COMPLETION_V3_ACK_FRAME_RSSI_GET(
  302. htt_desc[2]);
  303. transmit_cnt_valid =
  304. DP_TX_WBM_COMPLETION_V3_TRANSMIT_CNT_VALID_GET(
  305. htt_desc[3]);
  306. if (transmit_cnt_valid)
  307. ts.transmit_cnt =
  308. HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_GET(
  309. htt_desc[1]);
  310. ts.tsf = htt_desc[4];
  311. ts.first_msdu = 1;
  312. ts.last_msdu = 1;
  313. switch (tx_status) {
  314. case HTT_TX_FW2WBM_TX_STATUS_OK:
  315. ts.status = HAL_TX_TQM_RR_FRAME_ACKED;
  316. break;
  317. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  318. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  319. break;
  320. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  321. ts.status = HAL_TX_TQM_RR_REM_CMD_TX;
  322. break;
  323. }
  324. tid = ts.tid;
  325. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  326. tid = CDP_MAX_DATA_TIDS - 1;
  327. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  328. if (qdf_unlikely(pdev->delay_stats_flag) ||
  329. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(vdev)))
  330. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  331. if (tx_status < CDP_MAX_TX_HTT_STATUS)
  332. tid_stats->htt_status_cnt[tx_status]++;
  333. peer_id = dp_tx_comp_adjust_peer_id_be(soc, ts.peer_id);
  334. txrx_peer = dp_txrx_peer_get_ref_by_id(soc, peer_id,
  335. &txrx_ref_handle,
  336. DP_MOD_ID_HTT_COMP);
  337. if (qdf_likely(txrx_peer))
  338. dp_tx_update_peer_basic_stats(
  339. txrx_peer,
  340. qdf_nbuf_len(tx_desc->nbuf),
  341. tx_status,
  342. pdev->enhanced_stats_en);
  343. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, txrx_peer,
  344. ring_id);
  345. dp_tx_comp_process_desc(soc, tx_desc, &ts, txrx_peer);
  346. dp_tx_desc_release(soc, tx_desc, tx_desc->pool_id);
  347. if (qdf_likely(txrx_peer))
  348. dp_txrx_peer_unref_delete(txrx_ref_handle,
  349. DP_MOD_ID_HTT_COMP);
  350. break;
  351. }
  352. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  353. {
  354. uint8_t reinject_reason;
  355. reinject_reason =
  356. HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_GET(
  357. htt_desc[1]);
  358. dp_tx_reinject_handler(soc, vdev, tx_desc,
  359. status, reinject_reason);
  360. break;
  361. }
  362. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  363. {
  364. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  365. break;
  366. }
  367. case HTT_TX_FW2WBM_TX_STATUS_VDEVID_MISMATCH:
  368. {
  369. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  370. goto release_tx_desc;
  371. }
  372. default:
  373. dp_tx_comp_err("Invalid HTT tx_status %d\n",
  374. tx_status);
  375. goto release_tx_desc;
  376. }
  377. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  378. return;
  379. release_tx_desc:
  380. dp_tx_comp_free_buf(soc, tx_desc, false);
  381. dp_tx_desc_release(soc, tx_desc, tx_desc->pool_id);
  382. if (vdev)
  383. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  384. }
  385. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  386. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  387. /**
  388. * dp_tx_get_rbm_id_be() - Get the RBM ID for data transmission completion.
  389. * @soc: DP soc structure pointer
  390. * @ring_id: Transmit Queue/ring_id to be used when XPS is enabled
  391. *
  392. * Return: RBM ID corresponding to TCL ring_id
  393. */
  394. static inline uint8_t dp_tx_get_rbm_id_be(struct dp_soc *soc,
  395. uint8_t ring_id)
  396. {
  397. return 0;
  398. }
  399. #else
  400. static inline uint8_t dp_tx_get_rbm_id_be(struct dp_soc *soc,
  401. uint8_t ring_id)
  402. {
  403. return (ring_id ? soc->wbm_sw0_bm_id + (ring_id - 1) :
  404. HAL_WBM_SW2_BM_ID(soc->wbm_sw0_bm_id));
  405. }
  406. #endif /*DP_TX_IMPLICIT_RBM_MAPPING*/
  407. #else
  408. static inline uint8_t dp_tx_get_rbm_id_be(struct dp_soc *soc,
  409. uint8_t tcl_index)
  410. {
  411. uint8_t rbm;
  412. rbm = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx, tcl_index);
  413. dp_verbose_debug("tcl_id %u rbm %u", tcl_index, rbm);
  414. return rbm;
  415. }
  416. #endif
  417. #ifdef QCA_SUPPORT_TX_MIN_RATES_FOR_SPECIAL_FRAMES
  418. /**
  419. * dp_tx_set_min_rates_for_critical_frames()- sets min-rates for critical pkts
  420. * @soc: DP soc structure pointer
  421. * @hal_tx_desc: HAL descriptor where fields are set
  422. * @nbuf: skb to be considered for min rates
  423. *
  424. * The function relies on upper layers to set QDF_NBUF_CB_TX_EXTRA_IS_CRITICAL
  425. * and uses it to determine if the frame is critical. For a critical frame,
  426. * flow override bits are set to classify the frame into HW's high priority
  427. * queue. The HW will pick pre-configured min rates for such packets.
  428. *
  429. * Return: None
  430. */
  431. static void
  432. dp_tx_set_min_rates_for_critical_frames(struct dp_soc *soc,
  433. uint32_t *hal_tx_desc,
  434. qdf_nbuf_t nbuf)
  435. {
  436. /*
  437. * Critical frames should be queued to the high priority queue for the TID on
  438. * on which they are sent out (for the concerned peer).
  439. * FW is using HTT_MSDU_Q_IDX 2 for HOL (high priority) queue.
  440. * htt_msdu_idx = (2 * who_classify_info_sel) + flow_override
  441. * Hence, using who_classify_info_sel = 1, flow_override = 0 to select
  442. * HOL queue.
  443. */
  444. if (QDF_NBUF_CB_TX_EXTRA_IS_CRITICAL(nbuf)) {
  445. hal_tx_desc_set_flow_override_enable(hal_tx_desc, 1);
  446. hal_tx_desc_set_flow_override(hal_tx_desc, 0);
  447. hal_tx_desc_set_who_classify_info_sel(hal_tx_desc, 1);
  448. hal_tx_desc_set_tx_notify_frame(hal_tx_desc,
  449. TX_SEMI_HARD_NOTIFY_E);
  450. }
  451. }
  452. #else
  453. static inline void
  454. dp_tx_set_min_rates_for_critical_frames(struct dp_soc *soc,
  455. uint32_t *hal_tx_desc_cached,
  456. qdf_nbuf_t nbuf)
  457. {
  458. }
  459. #endif
  460. #ifdef DP_TX_PACKET_INSPECT_FOR_ILP
  461. /**
  462. * dp_tx_set_particular_tx_queue() - set particular TX TQM flow queue 3 for
  463. * TX packets, currently TCP ACK only
  464. * @soc: DP soc structure pointer
  465. * @hal_tx_desc: HAL descriptor where fields are set
  466. * @nbuf: skb to be considered for particular TX queue
  467. *
  468. * Return: None
  469. */
  470. static inline
  471. void dp_tx_set_particular_tx_queue(struct dp_soc *soc,
  472. uint32_t *hal_tx_desc,
  473. qdf_nbuf_t nbuf)
  474. {
  475. if (!soc->tx_ilp_enable)
  476. return;
  477. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  478. QDF_NBUF_CB_PACKET_TYPE_TCP_ACK)) {
  479. hal_tx_desc_set_flow_override_enable(hal_tx_desc, 1);
  480. hal_tx_desc_set_flow_override(hal_tx_desc, 1);
  481. hal_tx_desc_set_who_classify_info_sel(hal_tx_desc, 1);
  482. }
  483. }
  484. #else
  485. static inline
  486. void dp_tx_set_particular_tx_queue(struct dp_soc *soc,
  487. uint32_t *hal_tx_desc,
  488. qdf_nbuf_t nbuf)
  489. {
  490. }
  491. #endif
  492. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  493. defined(WLAN_MCAST_MLO)
  494. #ifdef QCA_MULTIPASS_SUPPORT
  495. /**
  496. * dp_tx_mlo_mcast_multipass_lookup() - lookup vlan_id in mpass peer list
  497. * @be_vdev: Handle to DP be_vdev structure
  498. * @ptnr_vdev: DP ptnr_vdev handle
  499. * @arg: pointer to dp_mlo_mpass_ buf
  500. *
  501. * Return: None
  502. */
  503. static void
  504. dp_tx_mlo_mcast_multipass_lookup(struct dp_vdev_be *be_vdev,
  505. struct dp_vdev *ptnr_vdev,
  506. void *arg)
  507. {
  508. struct dp_mlo_mpass_buf *ptr = (struct dp_mlo_mpass_buf *)arg;
  509. struct dp_txrx_peer *txrx_peer = NULL;
  510. struct vlan_ethhdr *veh = NULL;
  511. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(ptr->nbuf);
  512. uint16_t vlan_id = 0;
  513. bool not_vlan = ((ptnr_vdev->tx_encap_type == htt_cmn_pkt_type_raw) ||
  514. (htons(eh->ether_type) != ETH_P_8021Q));
  515. if (qdf_unlikely(not_vlan))
  516. return;
  517. veh = (struct vlan_ethhdr *)eh;
  518. vlan_id = (ntohs(veh->h_vlan_TCI) & VLAN_VID_MASK);
  519. qdf_spin_lock_bh(&ptnr_vdev->mpass_peer_mutex);
  520. TAILQ_FOREACH(txrx_peer, &ptnr_vdev->mpass_peer_list,
  521. mpass_peer_list_elem) {
  522. if (vlan_id == txrx_peer->vlan_id) {
  523. qdf_spin_unlock_bh(&ptnr_vdev->mpass_peer_mutex);
  524. ptr->vlan_id = vlan_id;
  525. return;
  526. }
  527. }
  528. qdf_spin_unlock_bh(&ptnr_vdev->mpass_peer_mutex);
  529. }
  530. /**
  531. * dp_tx_mlo_mcast_multipass_send() - send multipass MLO Mcast packets
  532. * @be_vdev: Handle to DP be_vdev structure
  533. * @ptnr_vdev: DP ptnr_vdev handle
  534. * @arg: pointer to dp_mlo_mpass_ buf
  535. *
  536. * Return: None
  537. */
  538. static void
  539. dp_tx_mlo_mcast_multipass_send(struct dp_vdev_be *be_vdev,
  540. struct dp_vdev *ptnr_vdev,
  541. void *arg)
  542. {
  543. struct dp_mlo_mpass_buf *ptr = (struct dp_mlo_mpass_buf *)arg;
  544. struct dp_tx_msdu_info_s msdu_info;
  545. struct dp_vdev_be *be_ptnr_vdev = NULL;
  546. qdf_nbuf_t nbuf_clone;
  547. uint16_t group_key = 0;
  548. be_ptnr_vdev = dp_get_be_vdev_from_dp_vdev(ptnr_vdev);
  549. if (be_vdev != be_ptnr_vdev) {
  550. nbuf_clone = qdf_nbuf_clone(ptr->nbuf);
  551. if (qdf_unlikely(!nbuf_clone)) {
  552. dp_tx_debug("nbuf clone failed");
  553. return;
  554. }
  555. } else {
  556. nbuf_clone = ptr->nbuf;
  557. }
  558. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  559. dp_tx_get_queue(ptnr_vdev, nbuf_clone, &msdu_info.tx_queue);
  560. msdu_info.gsn = be_vdev->mlo_dev_ctxt->seq_num;
  561. if (ptr->vlan_id == MULTIPASS_WITH_VLAN_ID) {
  562. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  563. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_SET(
  564. msdu_info.meta_data[0], 1);
  565. } else {
  566. /* return when vlan map is not initialized */
  567. if (!ptnr_vdev->iv_vlan_map)
  568. return;
  569. group_key = ptnr_vdev->iv_vlan_map[ptr->vlan_id];
  570. /*
  571. * If group key is not installed, drop the frame.
  572. */
  573. if (!group_key)
  574. return;
  575. dp_tx_remove_vlan_tag(ptnr_vdev, nbuf_clone);
  576. dp_tx_add_groupkey_metadata(ptnr_vdev, &msdu_info, group_key);
  577. msdu_info.exception_fw = 1;
  578. }
  579. nbuf_clone = dp_tx_send_msdu_single(
  580. ptnr_vdev,
  581. nbuf_clone,
  582. &msdu_info,
  583. DP_MLO_MCAST_REINJECT_PEER_ID,
  584. NULL);
  585. if (qdf_unlikely(nbuf_clone)) {
  586. dp_info("pkt send failed");
  587. qdf_nbuf_free(nbuf_clone);
  588. return;
  589. }
  590. }
  591. /**
  592. * dp_tx_mlo_mcast_multipass_handler - If frame needs multipass processing
  593. * @soc: DP soc handle
  594. * @vdev: DP vdev handle
  595. * @nbuf: nbuf to be enqueued
  596. *
  597. * Return: true if handling is done else false
  598. */
  599. static bool
  600. dp_tx_mlo_mcast_multipass_handler(struct dp_soc *soc,
  601. struct dp_vdev *vdev,
  602. qdf_nbuf_t nbuf)
  603. {
  604. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  605. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  606. qdf_nbuf_t nbuf_copy = NULL;
  607. struct dp_mlo_mpass_buf mpass_buf;
  608. memset(&mpass_buf, 0, sizeof(struct dp_mlo_mpass_buf));
  609. mpass_buf.vlan_id = INVALID_VLAN_ID;
  610. mpass_buf.nbuf = nbuf;
  611. dp_tx_mlo_mcast_multipass_lookup(be_vdev, vdev, &mpass_buf);
  612. if (mpass_buf.vlan_id == INVALID_VLAN_ID) {
  613. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  614. dp_tx_mlo_mcast_multipass_lookup,
  615. &mpass_buf, DP_MOD_ID_TX,
  616. DP_ALL_VDEV_ITER,
  617. DP_VDEV_ITERATE_SKIP_SELF);
  618. /*
  619. * Do not drop the frame when vlan_id doesn't match.
  620. * Send the frame as it is.
  621. */
  622. if (mpass_buf.vlan_id == INVALID_VLAN_ID)
  623. return false;
  624. }
  625. /* AP can have classic clients, special clients &
  626. * classic repeaters.
  627. * 1. Classic clients & special client:
  628. * Remove vlan header, find corresponding group key
  629. * index, fill in metaheader and enqueue multicast
  630. * frame to TCL.
  631. * 2. Classic repeater:
  632. * Pass through to classic repeater with vlan tag
  633. * intact without any group key index. Hardware
  634. * will know which key to use to send frame to
  635. * repeater.
  636. */
  637. nbuf_copy = qdf_nbuf_copy(nbuf);
  638. /*
  639. * Send multicast frame to special peers even
  640. * if pass through to classic repeater fails.
  641. */
  642. if (nbuf_copy) {
  643. struct dp_mlo_mpass_buf mpass_buf_copy = {0};
  644. mpass_buf_copy.vlan_id = MULTIPASS_WITH_VLAN_ID;
  645. mpass_buf_copy.nbuf = nbuf_copy;
  646. /* send frame on partner vdevs */
  647. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  648. dp_tx_mlo_mcast_multipass_send,
  649. &mpass_buf_copy, DP_MOD_ID_TX,
  650. DP_LINK_VDEV_ITER,
  651. DP_VDEV_ITERATE_SKIP_SELF);
  652. /* send frame on mcast primary vdev */
  653. dp_tx_mlo_mcast_multipass_send(be_vdev, vdev, &mpass_buf_copy);
  654. if (qdf_unlikely(be_vdev->mlo_dev_ctxt->seq_num > MAX_GSN_NUM))
  655. be_vdev->mlo_dev_ctxt->seq_num = 0;
  656. else
  657. be_vdev->mlo_dev_ctxt->seq_num++;
  658. }
  659. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  660. dp_tx_mlo_mcast_multipass_send,
  661. &mpass_buf, DP_MOD_ID_TX, DP_LINK_VDEV_ITER,
  662. DP_VDEV_ITERATE_SKIP_SELF);
  663. dp_tx_mlo_mcast_multipass_send(be_vdev, vdev, &mpass_buf);
  664. if (qdf_unlikely(be_vdev->mlo_dev_ctxt->seq_num > MAX_GSN_NUM))
  665. be_vdev->mlo_dev_ctxt->seq_num = 0;
  666. else
  667. be_vdev->mlo_dev_ctxt->seq_num++;
  668. return true;
  669. }
  670. #else
  671. static bool
  672. dp_tx_mlo_mcast_multipass_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  673. qdf_nbuf_t nbuf)
  674. {
  675. return false;
  676. }
  677. #endif
  678. void
  679. dp_tx_mlo_mcast_pkt_send(struct dp_vdev_be *be_vdev,
  680. struct dp_vdev *ptnr_vdev,
  681. void *arg)
  682. {
  683. qdf_nbuf_t nbuf = (qdf_nbuf_t)arg;
  684. qdf_nbuf_t nbuf_clone;
  685. struct dp_vdev_be *be_ptnr_vdev = NULL;
  686. struct dp_tx_msdu_info_s msdu_info;
  687. be_ptnr_vdev = dp_get_be_vdev_from_dp_vdev(ptnr_vdev);
  688. if (be_vdev != be_ptnr_vdev) {
  689. nbuf_clone = qdf_nbuf_clone(nbuf);
  690. if (qdf_unlikely(!nbuf_clone)) {
  691. dp_tx_debug("nbuf clone failed");
  692. return;
  693. }
  694. } else {
  695. nbuf_clone = nbuf;
  696. }
  697. /* NAWDS clients will accepts on 4 addr format MCAST packets
  698. * This will ensure to send packets in 4 addr format to NAWDS clients.
  699. */
  700. if (qdf_unlikely(ptnr_vdev->nawds_enabled)) {
  701. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  702. dp_tx_get_queue(ptnr_vdev, nbuf_clone, &msdu_info.tx_queue);
  703. dp_tx_nawds_handler(ptnr_vdev->pdev->soc, ptnr_vdev,
  704. &msdu_info, nbuf_clone, DP_INVALID_PEER);
  705. }
  706. if (qdf_unlikely(dp_tx_proxy_arp(ptnr_vdev, nbuf_clone) !=
  707. QDF_STATUS_SUCCESS)) {
  708. qdf_nbuf_free(nbuf_clone);
  709. return;
  710. }
  711. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  712. dp_tx_get_queue(ptnr_vdev, nbuf_clone, &msdu_info.tx_queue);
  713. msdu_info.gsn = be_vdev->mlo_dev_ctxt->seq_num;
  714. DP_STATS_INC(ptnr_vdev, tx_i.mlo_mcast.send_pkt_count, 1);
  715. nbuf_clone = dp_tx_send_msdu_single(
  716. ptnr_vdev,
  717. nbuf_clone,
  718. &msdu_info,
  719. DP_MLO_MCAST_REINJECT_PEER_ID,
  720. NULL);
  721. if (qdf_unlikely(nbuf_clone)) {
  722. DP_STATS_INC(ptnr_vdev, tx_i.mlo_mcast.fail_pkt_count, 1);
  723. dp_info("pkt send failed");
  724. qdf_nbuf_free(nbuf_clone);
  725. return;
  726. }
  727. }
  728. static inline void
  729. dp_tx_vdev_id_set_hal_tx_desc(uint32_t *hal_tx_desc_cached,
  730. struct dp_vdev *vdev,
  731. struct dp_tx_msdu_info_s *msdu_info)
  732. {
  733. hal_tx_desc_set_vdev_id(hal_tx_desc_cached, msdu_info->vdev_id);
  734. }
  735. void dp_tx_mlo_mcast_handler_be(struct dp_soc *soc,
  736. struct dp_vdev *vdev,
  737. qdf_nbuf_t nbuf)
  738. {
  739. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  740. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  741. if (qdf_unlikely(vdev->multipass_en) &&
  742. dp_tx_mlo_mcast_multipass_handler(soc, vdev, nbuf))
  743. return;
  744. /* send frame on partner vdevs */
  745. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  746. dp_tx_mlo_mcast_pkt_send,
  747. nbuf, DP_MOD_ID_REINJECT, DP_LINK_VDEV_ITER,
  748. DP_VDEV_ITERATE_SKIP_SELF);
  749. /* send frame on mcast primary vdev */
  750. dp_tx_mlo_mcast_pkt_send(be_vdev, vdev, nbuf);
  751. if (qdf_unlikely(be_vdev->mlo_dev_ctxt->seq_num > MAX_GSN_NUM))
  752. be_vdev->mlo_dev_ctxt->seq_num = 0;
  753. else
  754. be_vdev->mlo_dev_ctxt->seq_num++;
  755. }
  756. bool dp_tx_mlo_is_mcast_primary_be(struct dp_soc *soc,
  757. struct dp_vdev *vdev)
  758. {
  759. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  760. if (be_vdev->mcast_primary)
  761. return true;
  762. return false;
  763. }
  764. #if defined(CONFIG_MLO_SINGLE_DEV)
  765. static void
  766. dp_tx_mlo_mcast_enhance_be(struct dp_vdev_be *be_vdev,
  767. struct dp_vdev *ptnr_vdev,
  768. void *arg)
  769. {
  770. struct dp_vdev *vdev = (struct dp_vdev *)be_vdev;
  771. qdf_nbuf_t nbuf = (qdf_nbuf_t)arg;
  772. if (vdev == ptnr_vdev)
  773. return;
  774. /*
  775. * Hold the reference to avoid free of nbuf in
  776. * dp_tx_mcast_enhance() in case of successful
  777. * conversion
  778. */
  779. qdf_nbuf_ref(nbuf);
  780. if (qdf_unlikely(!dp_tx_mcast_enhance(ptnr_vdev, nbuf)))
  781. return;
  782. qdf_nbuf_free(nbuf);
  783. }
  784. qdf_nbuf_t
  785. dp_tx_mlo_mcast_send_be(struct dp_soc *soc, struct dp_vdev *vdev,
  786. qdf_nbuf_t nbuf,
  787. struct cdp_tx_exception_metadata *tx_exc_metadata)
  788. {
  789. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  790. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  791. if (!tx_exc_metadata->is_mlo_mcast)
  792. return nbuf;
  793. if (!be_vdev->mcast_primary) {
  794. qdf_nbuf_free(nbuf);
  795. return NULL;
  796. }
  797. /*
  798. * In the single netdev model avoid reinjection path as mcast
  799. * packet is identified in upper layers while peer search to find
  800. * primary TQM based on dest mac addr
  801. *
  802. * New bonding interface added into the bridge so MCSD will update
  803. * snooping table and wifi driver populates the entries in appropriate
  804. * child net devices.
  805. */
  806. if (vdev->mcast_enhancement_en) {
  807. /*
  808. * As dp_tx_mcast_enhance() can consume the nbuf incase of
  809. * successful conversion hold the reference of nbuf.
  810. *
  811. * Hold the reference to tx on partner links
  812. */
  813. qdf_nbuf_ref(nbuf);
  814. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf))) {
  815. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  816. dp_tx_mlo_mcast_enhance_be,
  817. nbuf, DP_MOD_ID_TX,
  818. DP_ALL_VDEV_ITER,
  819. DP_VDEV_ITERATE_SKIP_SELF);
  820. qdf_nbuf_free(nbuf);
  821. return NULL;
  822. }
  823. /* release reference taken above */
  824. qdf_nbuf_free(nbuf);
  825. }
  826. dp_tx_mlo_mcast_handler_be(soc, vdev, nbuf);
  827. return NULL;
  828. }
  829. #endif
  830. #else
  831. static inline void
  832. dp_tx_vdev_id_set_hal_tx_desc(uint32_t *hal_tx_desc_cached,
  833. struct dp_vdev *vdev,
  834. struct dp_tx_msdu_info_s *msdu_info)
  835. {
  836. hal_tx_desc_set_vdev_id(hal_tx_desc_cached, vdev->vdev_id);
  837. }
  838. #endif
  839. #if defined(WLAN_FEATURE_11BE_MLO) && !defined(WLAN_MLO_MULTI_CHIP) && \
  840. !defined(WLAN_MCAST_MLO)
  841. void dp_tx_mlo_mcast_handler_be(struct dp_soc *soc,
  842. struct dp_vdev *vdev,
  843. qdf_nbuf_t nbuf)
  844. {
  845. }
  846. bool dp_tx_mlo_is_mcast_primary_be(struct dp_soc *soc,
  847. struct dp_vdev *vdev)
  848. {
  849. return false;
  850. }
  851. #endif
  852. #ifdef CONFIG_SAWF
  853. /**
  854. * dp_sawf_config_be - Configure sawf specific fields in tcl
  855. *
  856. * @soc: DP soc handle
  857. * @hal_tx_desc_cached: tx descriptor
  858. * @fw_metadata: firmware metadata
  859. * @nbuf: skb buffer
  860. * @msdu_info: msdu info
  861. *
  862. * Return: void
  863. */
  864. void dp_sawf_config_be(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  865. uint16_t *fw_metadata, qdf_nbuf_t nbuf,
  866. struct dp_tx_msdu_info_s *msdu_info)
  867. {
  868. uint8_t q_id = 0;
  869. if (!wlan_cfg_get_sawf_config(soc->wlan_cfg_ctx))
  870. return;
  871. q_id = dp_sawf_queue_id_get(nbuf);
  872. if (q_id == DP_SAWF_DEFAULT_Q_INVALID)
  873. return;
  874. msdu_info->tid = (q_id & (CDP_DATA_TID_MAX - 1));
  875. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached,
  876. (q_id & (CDP_DATA_TID_MAX - 1)));
  877. if ((q_id >= DP_SAWF_DEFAULT_QUEUE_MIN) &&
  878. (q_id < DP_SAWF_DEFAULT_QUEUE_MAX))
  879. return;
  880. dp_sawf_tcl_cmd(fw_metadata, nbuf);
  881. hal_tx_desc_set_flow_override_enable(hal_tx_desc_cached,
  882. DP_TX_FLOW_OVERRIDE_ENABLE);
  883. hal_tx_desc_set_flow_override(hal_tx_desc_cached,
  884. DP_TX_FLOW_OVERRIDE_GET(q_id));
  885. hal_tx_desc_set_who_classify_info_sel(hal_tx_desc_cached,
  886. DP_TX_WHO_CLFY_INF_SEL_GET(q_id));
  887. }
  888. #else
  889. static inline
  890. void dp_sawf_config_be(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  891. uint16_t *fw_metadata, qdf_nbuf_t nbuf,
  892. struct dp_tx_msdu_info_s *msdu_info)
  893. {
  894. }
  895. static inline
  896. QDF_STATUS dp_sawf_tx_enqueue_peer_stats(struct dp_soc *soc,
  897. struct dp_tx_desc_s *tx_desc)
  898. {
  899. return QDF_STATUS_SUCCESS;
  900. }
  901. static inline
  902. QDF_STATUS dp_sawf_tx_enqueue_fail_peer_stats(struct dp_soc *soc,
  903. struct dp_tx_desc_s *tx_desc)
  904. {
  905. return QDF_STATUS_SUCCESS;
  906. }
  907. #endif
  908. #ifdef WLAN_SUPPORT_PPEDS
  909. /**
  910. * dp_ppeds_stats() - Accounting fw2wbm_tx_drop drops in Tx path
  911. * @soc: Handle to DP Soc structure
  912. * @peer_id: Peer ID in the descriptor
  913. *
  914. * Return: NONE
  915. */
  916. static inline
  917. void dp_ppeds_stats(struct dp_soc *soc, uint16_t peer_id)
  918. {
  919. struct dp_vdev *vdev = NULL;
  920. struct dp_txrx_peer *txrx_peer = NULL;
  921. dp_txrx_ref_handle txrx_ref_handle = NULL;
  922. DP_STATS_INC(soc, tx.fw2wbm_tx_drop, 1);
  923. txrx_peer = dp_txrx_peer_get_ref_by_id(soc,
  924. peer_id,
  925. &txrx_ref_handle,
  926. DP_MOD_ID_TX_COMP);
  927. if (txrx_peer) {
  928. vdev = txrx_peer->vdev;
  929. DP_STATS_INC(vdev, tx_i.dropped.fw2wbm_tx_drop, 1);
  930. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  931. }
  932. }
  933. int dp_ppeds_tx_comp_handler(struct dp_soc_be *be_soc, uint32_t quota)
  934. {
  935. uint32_t num_avail_for_reap = 0;
  936. void *tx_comp_hal_desc;
  937. uint8_t buf_src, status = 0;
  938. uint32_t count = 0;
  939. struct dp_tx_desc_s *tx_desc = NULL;
  940. struct dp_tx_desc_s *head_desc = NULL;
  941. struct dp_tx_desc_s *tail_desc = NULL;
  942. struct dp_soc *soc = &be_soc->soc;
  943. void *last_prefetch_hw_desc = NULL;
  944. struct dp_tx_desc_s *last_prefetch_sw_desc = NULL;
  945. qdf_nbuf_t nbuf;
  946. hal_soc_handle_t hal_soc = soc->hal_soc;
  947. hal_ring_handle_t hal_ring_hdl =
  948. be_soc->ppeds_wbm_release_ring.hal_srng;
  949. struct dp_txrx_peer *txrx_peer = NULL;
  950. uint16_t peer_id = CDP_INVALID_PEER;
  951. dp_txrx_ref_handle txrx_ref_handle = NULL;
  952. struct dp_vdev *vdev = NULL;
  953. struct dp_pdev *pdev = NULL;
  954. struct dp_srng *srng;
  955. if (qdf_unlikely(dp_srng_access_start(NULL, soc, hal_ring_hdl))) {
  956. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  957. return 0;
  958. }
  959. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, 0);
  960. if (num_avail_for_reap >= quota)
  961. num_avail_for_reap = quota;
  962. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  963. last_prefetch_hw_desc = dp_srng_dst_prefetch(hal_soc, hal_ring_hdl,
  964. num_avail_for_reap);
  965. srng = &be_soc->ppeds_wbm_release_ring;
  966. if (srng) {
  967. hal_update_ring_util(soc->hal_soc, srng->hal_srng,
  968. WBM2SW_RELEASE,
  969. &be_soc->ppeds_wbm_release_ring.stats);
  970. }
  971. while (qdf_likely(num_avail_for_reap--)) {
  972. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  973. if (qdf_unlikely(!tx_comp_hal_desc))
  974. break;
  975. buf_src = hal_tx_comp_get_buffer_source(hal_soc,
  976. tx_comp_hal_desc);
  977. if (qdf_unlikely(buf_src != HAL_TX_COMP_RELEASE_SOURCE_TQM &&
  978. buf_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  979. dp_err("Tx comp release_src != TQM | FW but from %d",
  980. buf_src);
  981. dp_assert_always_internal_ds_stat(0, be_soc,
  982. tx.tx_comp_buf_src);
  983. continue;
  984. }
  985. dp_tx_comp_get_params_from_hal_desc_be(soc, tx_comp_hal_desc,
  986. &tx_desc);
  987. if (!tx_desc) {
  988. dp_err("unable to retrieve tx_desc!");
  989. dp_assert_always_internal_ds_stat(0, be_soc,
  990. tx.tx_comp_desc_null);
  991. continue;
  992. }
  993. if (qdf_unlikely(!(tx_desc->flags &
  994. DP_TX_DESC_FLAG_ALLOCATED) ||
  995. !(tx_desc->flags & DP_TX_DESC_FLAG_PPEDS))) {
  996. dp_assert_always_internal_ds_stat(0, be_soc,
  997. tx.tx_comp_invalid_flag);
  998. continue;
  999. }
  1000. tx_desc->buffer_src = buf_src;
  1001. if (qdf_unlikely(buf_src == HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  1002. status = hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  1003. if (status != HTT_TX_FW2WBM_TX_STATUS_OK)
  1004. dp_ppeds_stats(soc, tx_desc->peer_id);
  1005. nbuf = dp_ppeds_tx_desc_free(soc, tx_desc);
  1006. qdf_nbuf_free(nbuf);
  1007. } else {
  1008. tx_desc->tx_status =
  1009. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  1010. /*
  1011. * Add desc sync to account for extended statistics
  1012. * during Tx completion.
  1013. */
  1014. if (peer_id != tx_desc->peer_id) {
  1015. if (txrx_peer) {
  1016. dp_txrx_peer_unref_delete(txrx_ref_handle,
  1017. DP_MOD_ID_TX_COMP);
  1018. txrx_peer = NULL;
  1019. vdev = NULL;
  1020. pdev = NULL;
  1021. }
  1022. peer_id = tx_desc->peer_id;
  1023. txrx_peer =
  1024. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  1025. &txrx_ref_handle,
  1026. DP_MOD_ID_TX_COMP);
  1027. if (txrx_peer) {
  1028. vdev = txrx_peer->vdev;
  1029. if (!vdev)
  1030. goto next_desc;
  1031. pdev = vdev->pdev;
  1032. if (!pdev)
  1033. goto next_desc;
  1034. dp_tx_desc_update_fast_comp_flag(soc,
  1035. tx_desc,
  1036. !pdev->enhanced_stats_en);
  1037. if (pdev->enhanced_stats_en) {
  1038. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  1039. &tx_desc->comp, 1);
  1040. }
  1041. }
  1042. } else if (txrx_peer && vdev && pdev) {
  1043. dp_tx_desc_update_fast_comp_flag(soc,
  1044. tx_desc,
  1045. !pdev->enhanced_stats_en);
  1046. if (pdev->enhanced_stats_en) {
  1047. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  1048. &tx_desc->comp, 1);
  1049. }
  1050. }
  1051. next_desc:
  1052. if (!head_desc) {
  1053. head_desc = tx_desc;
  1054. tail_desc = tx_desc;
  1055. }
  1056. tail_desc->next = tx_desc;
  1057. tx_desc->next = NULL;
  1058. tail_desc = tx_desc;
  1059. count++;
  1060. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  1061. num_avail_for_reap,
  1062. hal_ring_hdl,
  1063. &last_prefetch_hw_desc,
  1064. &last_prefetch_sw_desc);
  1065. }
  1066. }
  1067. dp_srng_access_end(NULL, soc, hal_ring_hdl);
  1068. if (txrx_peer)
  1069. dp_txrx_peer_unref_delete(txrx_ref_handle,
  1070. DP_MOD_ID_TX_COMP);
  1071. if (head_desc)
  1072. dp_tx_comp_process_desc_list(soc, head_desc,
  1073. CDP_MAX_TX_COMP_PPE_RING);
  1074. return count;
  1075. }
  1076. #endif
  1077. #if defined(QCA_SUPPORT_WDS_EXTENDED)
  1078. static inline void
  1079. dp_get_peer_from_tx_exc_meta(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  1080. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1081. uint16_t *ast_idx, uint16_t *ast_hash)
  1082. {
  1083. struct dp_peer *peer = NULL;
  1084. if (tx_exc_metadata->is_wds_extended) {
  1085. peer = dp_peer_get_ref_by_id(soc, tx_exc_metadata->peer_id,
  1086. DP_MOD_ID_TX);
  1087. if (peer) {
  1088. *ast_idx = peer->ast_idx;
  1089. *ast_hash = peer->ast_hash;
  1090. hal_tx_desc_set_index_lookup_override
  1091. (soc->hal_soc,
  1092. hal_tx_desc_cached,
  1093. 0x1);
  1094. dp_peer_unref_delete(peer, DP_MOD_ID_TX);
  1095. }
  1096. } else {
  1097. return;
  1098. }
  1099. }
  1100. #else
  1101. static inline void
  1102. dp_get_peer_from_tx_exc_meta(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  1103. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1104. uint16_t *ast_idx, uint16_t *ast_hash)
  1105. {
  1106. }
  1107. #endif
  1108. QDF_STATUS
  1109. dp_tx_hw_enqueue_be(struct dp_soc *soc, struct dp_vdev *vdev,
  1110. struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
  1111. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1112. struct dp_tx_msdu_info_s *msdu_info)
  1113. {
  1114. void *hal_tx_desc;
  1115. uint32_t *hal_tx_desc_cached;
  1116. int coalesce = 0;
  1117. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1118. uint8_t ring_id = tx_q->ring_id;
  1119. uint8_t tid;
  1120. struct dp_vdev_be *be_vdev;
  1121. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1122. uint8_t bm_id = dp_tx_get_rbm_id_be(soc, ring_id);
  1123. hal_ring_handle_t hal_ring_hdl = NULL;
  1124. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1125. uint8_t num_desc_bytes = HAL_TX_DESC_LEN_BYTES;
  1126. uint16_t ast_idx = vdev->bss_ast_idx;
  1127. uint16_t ast_hash = vdev->bss_ast_hash;
  1128. be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1129. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1130. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1131. return QDF_STATUS_E_RESOURCES;
  1132. }
  1133. if (qdf_unlikely(tx_exc_metadata)) {
  1134. qdf_assert_always((tx_exc_metadata->tx_encap_type ==
  1135. CDP_INVALID_TX_ENCAP_TYPE) ||
  1136. (tx_exc_metadata->tx_encap_type ==
  1137. vdev->tx_encap_type));
  1138. if (tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)
  1139. qdf_assert_always((tx_exc_metadata->sec_type ==
  1140. CDP_INVALID_SEC_TYPE) ||
  1141. tx_exc_metadata->sec_type ==
  1142. vdev->sec_type);
  1143. dp_get_peer_from_tx_exc_meta(soc, (void *)cached_desc,
  1144. tx_exc_metadata,
  1145. &ast_idx, &ast_hash);
  1146. }
  1147. hal_tx_desc_cached = (void *)cached_desc;
  1148. if (dp_sawf_tag_valid_get(tx_desc->nbuf)) {
  1149. dp_sawf_config_be(soc, hal_tx_desc_cached,
  1150. &fw_metadata, tx_desc->nbuf, msdu_info);
  1151. dp_sawf_tx_enqueue_peer_stats(soc, tx_desc);
  1152. }
  1153. hal_tx_desc_set_buf_addr_be(soc->hal_soc, hal_tx_desc_cached,
  1154. tx_desc->dma_addr, bm_id, tx_desc->id,
  1155. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG));
  1156. hal_tx_desc_set_lmac_id_be(soc->hal_soc, hal_tx_desc_cached,
  1157. vdev->lmac_id);
  1158. hal_tx_desc_set_search_index_be(soc->hal_soc, hal_tx_desc_cached,
  1159. ast_idx);
  1160. /*
  1161. * Bank_ID is used as DSCP_TABLE number in beryllium
  1162. * So there is no explicit field used for DSCP_TID_TABLE_NUM.
  1163. */
  1164. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1165. (ast_hash & 0xF));
  1166. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1167. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1168. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1169. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1170. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1171. /* verify checksum offload configuration*/
  1172. if ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) ==
  1173. QDF_NBUF_TX_CKSUM_TCP_UDP) ||
  1174. qdf_nbuf_is_tso(tx_desc->nbuf)) {
  1175. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1176. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1177. }
  1178. hal_tx_desc_set_bank_id(hal_tx_desc_cached, vdev->bank_id);
  1179. dp_tx_vdev_id_set_hal_tx_desc(hal_tx_desc_cached, vdev, msdu_info);
  1180. tid = msdu_info->tid;
  1181. if (tid != HTT_TX_EXT_TID_INVALID)
  1182. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1183. dp_tx_set_min_rates_for_critical_frames(soc, hal_tx_desc_cached,
  1184. tx_desc->nbuf);
  1185. dp_tx_set_particular_tx_queue(soc, hal_tx_desc_cached,
  1186. tx_desc->nbuf);
  1187. dp_tx_desc_set_ktimestamp(vdev, tx_desc);
  1188. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1189. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1190. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  1191. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1192. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1193. dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc);
  1194. return status;
  1195. }
  1196. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1197. if (qdf_unlikely(!hal_tx_desc)) {
  1198. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1199. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1200. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1201. dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc);
  1202. goto ring_access_fail;
  1203. }
  1204. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1205. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1206. /* Sync cached descriptor with HW */
  1207. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc, num_desc_bytes);
  1208. coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid,
  1209. msdu_info, ring_id);
  1210. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, dp_tx_get_pkt_len(tx_desc));
  1211. DP_STATS_INC(soc, tx.tcl_enq[ring_id], 1);
  1212. dp_tx_update_stats(soc, tx_desc, ring_id);
  1213. status = QDF_STATUS_SUCCESS;
  1214. dp_tx_hw_desc_update_evt((uint8_t *)hal_tx_desc_cached,
  1215. hal_ring_hdl, soc, ring_id);
  1216. ring_access_fail:
  1217. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, coalesce);
  1218. dp_pkt_add_timestamp(vdev, QDF_PKT_TX_DRIVER_EXIT,
  1219. qdf_get_log_timestamp(), tx_desc->nbuf);
  1220. return status;
  1221. }
  1222. #ifdef IPA_OFFLOAD
  1223. static void
  1224. dp_tx_get_ipa_bank_config(struct dp_soc_be *be_soc,
  1225. union hal_tx_bank_config *bank_config)
  1226. {
  1227. bank_config->epd = 0;
  1228. bank_config->encap_type = wlan_cfg_pkt_type(be_soc->soc.wlan_cfg_ctx);
  1229. bank_config->encrypt_type = 0;
  1230. bank_config->src_buffer_swap = 0;
  1231. bank_config->link_meta_swap = 0;
  1232. bank_config->index_lookup_enable = 0;
  1233. bank_config->mcast_pkt_ctrl = HAL_TX_MCAST_CTRL_FW_EXCEPTION;
  1234. bank_config->addrx_en = 1;
  1235. bank_config->addry_en = 1;
  1236. bank_config->mesh_enable = 0;
  1237. bank_config->dscp_tid_map_id = 0;
  1238. bank_config->vdev_id_check_en = 0;
  1239. bank_config->pmac_id = 0;
  1240. }
  1241. static void dp_tx_init_ipa_bank_profile(struct dp_soc_be *be_soc)
  1242. {
  1243. union hal_tx_bank_config ipa_config = {0};
  1244. int bid;
  1245. if (!wlan_cfg_is_ipa_enabled(be_soc->soc.wlan_cfg_ctx)) {
  1246. be_soc->ipa_bank_id = DP_BE_INVALID_BANK_ID;
  1247. return;
  1248. }
  1249. dp_tx_get_ipa_bank_config(be_soc, &ipa_config);
  1250. /* Let IPA use last HOST owned bank */
  1251. bid = be_soc->num_bank_profiles - 1;
  1252. be_soc->bank_profiles[bid].is_configured = true;
  1253. be_soc->bank_profiles[bid].bank_config.val = ipa_config.val;
  1254. hal_tx_populate_bank_register(be_soc->soc.hal_soc,
  1255. &be_soc->bank_profiles[bid].bank_config,
  1256. bid);
  1257. qdf_atomic_inc(&be_soc->bank_profiles[bid].ref_count);
  1258. dp_info("IPA bank at slot %d config:0x%x", bid,
  1259. be_soc->bank_profiles[bid].bank_config.val);
  1260. be_soc->ipa_bank_id = bid;
  1261. }
  1262. #else /* !IPA_OFFLOAD */
  1263. static inline void dp_tx_init_ipa_bank_profile(struct dp_soc_be *be_soc)
  1264. {
  1265. }
  1266. #endif /* IPA_OFFLOAD */
  1267. QDF_STATUS dp_tx_init_bank_profiles(struct dp_soc_be *be_soc)
  1268. {
  1269. int i, num_tcl_banks;
  1270. num_tcl_banks = hal_tx_get_num_tcl_banks(be_soc->soc.hal_soc);
  1271. dp_assert_always_internal(num_tcl_banks);
  1272. be_soc->num_bank_profiles = num_tcl_banks;
  1273. be_soc->bank_profiles = qdf_mem_malloc(num_tcl_banks *
  1274. sizeof(*be_soc->bank_profiles));
  1275. if (!be_soc->bank_profiles) {
  1276. dp_err("unable to allocate memory for DP TX Profiles!");
  1277. return QDF_STATUS_E_NOMEM;
  1278. }
  1279. DP_TX_BANK_LOCK_CREATE(&be_soc->tx_bank_lock);
  1280. for (i = 0; i < num_tcl_banks; i++) {
  1281. be_soc->bank_profiles[i].is_configured = false;
  1282. qdf_atomic_init(&be_soc->bank_profiles[i].ref_count);
  1283. }
  1284. dp_info("initialized %u bank profiles", be_soc->num_bank_profiles);
  1285. dp_tx_init_ipa_bank_profile(be_soc);
  1286. return QDF_STATUS_SUCCESS;
  1287. }
  1288. void dp_tx_deinit_bank_profiles(struct dp_soc_be *be_soc)
  1289. {
  1290. qdf_mem_free(be_soc->bank_profiles);
  1291. DP_TX_BANK_LOCK_DESTROY(&be_soc->tx_bank_lock);
  1292. }
  1293. static
  1294. void dp_tx_get_vdev_bank_config(struct dp_vdev_be *be_vdev,
  1295. union hal_tx_bank_config *bank_config)
  1296. {
  1297. struct dp_vdev *vdev = &be_vdev->vdev;
  1298. bank_config->epd = 0;
  1299. bank_config->encap_type = vdev->tx_encap_type;
  1300. /* Only valid for raw frames. Needs work for RAW mode */
  1301. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw) {
  1302. bank_config->encrypt_type = sec_type_map[vdev->sec_type];
  1303. } else {
  1304. bank_config->encrypt_type = 0;
  1305. }
  1306. bank_config->src_buffer_swap = 0;
  1307. bank_config->link_meta_swap = 0;
  1308. if ((vdev->search_type == HAL_TX_ADDR_INDEX_SEARCH) &&
  1309. vdev->opmode == wlan_op_mode_sta) {
  1310. bank_config->index_lookup_enable = 1;
  1311. bank_config->mcast_pkt_ctrl = HAL_TX_MCAST_CTRL_MEC_NOTIFY;
  1312. bank_config->addrx_en = 0;
  1313. bank_config->addry_en = 0;
  1314. } else {
  1315. bank_config->index_lookup_enable = 0;
  1316. bank_config->mcast_pkt_ctrl = HAL_TX_MCAST_CTRL_FW_EXCEPTION;
  1317. bank_config->addrx_en =
  1318. (vdev->hal_desc_addr_search_flags &
  1319. HAL_TX_DESC_ADDRX_EN) ? 1 : 0;
  1320. bank_config->addry_en =
  1321. (vdev->hal_desc_addr_search_flags &
  1322. HAL_TX_DESC_ADDRY_EN) ? 1 : 0;
  1323. }
  1324. bank_config->mesh_enable = vdev->mesh_vdev ? 1 : 0;
  1325. bank_config->dscp_tid_map_id = vdev->dscp_tid_map_id;
  1326. /* Disabling vdev id check for now. Needs revist. */
  1327. bank_config->vdev_id_check_en = be_vdev->vdev_id_check_en;
  1328. bank_config->pmac_id = vdev->lmac_id;
  1329. }
  1330. int dp_tx_get_bank_profile(struct dp_soc_be *be_soc,
  1331. struct dp_vdev_be *be_vdev)
  1332. {
  1333. char *temp_str = "";
  1334. bool found_match = false;
  1335. int bank_id = DP_BE_INVALID_BANK_ID;
  1336. int i;
  1337. int unconfigured_slot = DP_BE_INVALID_BANK_ID;
  1338. int zero_ref_count_slot = DP_BE_INVALID_BANK_ID;
  1339. union hal_tx_bank_config vdev_config = {0};
  1340. /* convert vdev params into hal_tx_bank_config */
  1341. dp_tx_get_vdev_bank_config(be_vdev, &vdev_config);
  1342. DP_TX_BANK_LOCK_ACQUIRE(&be_soc->tx_bank_lock);
  1343. /* go over all banks and find a matching/unconfigured/unused bank */
  1344. for (i = 0; i < be_soc->num_bank_profiles; i++) {
  1345. if (be_soc->bank_profiles[i].is_configured &&
  1346. (be_soc->bank_profiles[i].bank_config.val ^
  1347. vdev_config.val) == 0) {
  1348. found_match = true;
  1349. break;
  1350. }
  1351. if (unconfigured_slot == DP_BE_INVALID_BANK_ID &&
  1352. !be_soc->bank_profiles[i].is_configured)
  1353. unconfigured_slot = i;
  1354. else if (zero_ref_count_slot == DP_BE_INVALID_BANK_ID &&
  1355. !qdf_atomic_read(&be_soc->bank_profiles[i].ref_count))
  1356. zero_ref_count_slot = i;
  1357. }
  1358. if (found_match) {
  1359. temp_str = "matching";
  1360. bank_id = i;
  1361. goto inc_ref_and_return;
  1362. }
  1363. if (unconfigured_slot != DP_BE_INVALID_BANK_ID) {
  1364. temp_str = "unconfigured";
  1365. bank_id = unconfigured_slot;
  1366. goto configure_and_return;
  1367. }
  1368. if (zero_ref_count_slot != DP_BE_INVALID_BANK_ID) {
  1369. temp_str = "zero_ref_count";
  1370. bank_id = zero_ref_count_slot;
  1371. }
  1372. if (bank_id == DP_BE_INVALID_BANK_ID) {
  1373. dp_alert("unable to find TX bank!");
  1374. QDF_BUG(0);
  1375. return bank_id;
  1376. }
  1377. configure_and_return:
  1378. be_soc->bank_profiles[bank_id].is_configured = true;
  1379. be_soc->bank_profiles[bank_id].bank_config.val = vdev_config.val;
  1380. hal_tx_populate_bank_register(be_soc->soc.hal_soc,
  1381. &be_soc->bank_profiles[bank_id].bank_config,
  1382. bank_id);
  1383. inc_ref_and_return:
  1384. qdf_atomic_inc(&be_soc->bank_profiles[bank_id].ref_count);
  1385. DP_TX_BANK_LOCK_RELEASE(&be_soc->tx_bank_lock);
  1386. dp_info("found %s slot at index %d, input:0x%x match:0x%x ref_count %u",
  1387. temp_str, bank_id, vdev_config.val,
  1388. be_soc->bank_profiles[bank_id].bank_config.val,
  1389. qdf_atomic_read(&be_soc->bank_profiles[bank_id].ref_count));
  1390. dp_info("epd:%x encap:%x encryp:%x src_buf_swap:%x link_meta_swap:%x addrx_en:%x addry_en:%x mesh_en:%x vdev_id_check:%x pmac_id:%x mcast_pkt_ctrl:%x",
  1391. be_soc->bank_profiles[bank_id].bank_config.epd,
  1392. be_soc->bank_profiles[bank_id].bank_config.encap_type,
  1393. be_soc->bank_profiles[bank_id].bank_config.encrypt_type,
  1394. be_soc->bank_profiles[bank_id].bank_config.src_buffer_swap,
  1395. be_soc->bank_profiles[bank_id].bank_config.link_meta_swap,
  1396. be_soc->bank_profiles[bank_id].bank_config.addrx_en,
  1397. be_soc->bank_profiles[bank_id].bank_config.addry_en,
  1398. be_soc->bank_profiles[bank_id].bank_config.mesh_enable,
  1399. be_soc->bank_profiles[bank_id].bank_config.vdev_id_check_en,
  1400. be_soc->bank_profiles[bank_id].bank_config.pmac_id,
  1401. be_soc->bank_profiles[bank_id].bank_config.mcast_pkt_ctrl);
  1402. return bank_id;
  1403. }
  1404. void dp_tx_put_bank_profile(struct dp_soc_be *be_soc,
  1405. struct dp_vdev_be *be_vdev)
  1406. {
  1407. DP_TX_BANK_LOCK_ACQUIRE(&be_soc->tx_bank_lock);
  1408. qdf_atomic_dec(&be_soc->bank_profiles[be_vdev->bank_id].ref_count);
  1409. DP_TX_BANK_LOCK_RELEASE(&be_soc->tx_bank_lock);
  1410. }
  1411. void dp_tx_update_bank_profile(struct dp_soc_be *be_soc,
  1412. struct dp_vdev_be *be_vdev)
  1413. {
  1414. dp_tx_put_bank_profile(be_soc, be_vdev);
  1415. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  1416. be_vdev->vdev.bank_id = be_vdev->bank_id;
  1417. }
  1418. QDF_STATUS dp_tx_desc_pool_init_be(struct dp_soc *soc,
  1419. uint32_t num_elem,
  1420. uint8_t pool_id,
  1421. bool spcl_tx_desc)
  1422. {
  1423. struct dp_tx_desc_pool_s *tx_desc_pool;
  1424. struct dp_hw_cookie_conversion_t *cc_ctx;
  1425. struct dp_spt_page_desc *page_desc;
  1426. struct dp_tx_desc_s *tx_desc;
  1427. uint32_t ppt_idx = 0;
  1428. uint32_t avail_entry_index = 0;
  1429. if (!num_elem) {
  1430. dp_err("desc_num 0 !!");
  1431. return QDF_STATUS_E_FAILURE;
  1432. }
  1433. if (spcl_tx_desc) {
  1434. tx_desc_pool = dp_get_spcl_tx_desc_pool(soc, pool_id);
  1435. cc_ctx = dp_get_spcl_tx_cookie_t(soc, pool_id);
  1436. } else {
  1437. tx_desc_pool = dp_get_tx_desc_pool(soc, pool_id);;
  1438. cc_ctx = dp_get_tx_cookie_t(soc, pool_id);
  1439. }
  1440. tx_desc = tx_desc_pool->freelist;
  1441. page_desc = &cc_ctx->page_desc_base[0];
  1442. while (tx_desc) {
  1443. if (avail_entry_index == 0) {
  1444. if (ppt_idx >= cc_ctx->total_page_num) {
  1445. dp_alert("insufficient secondary page tables");
  1446. qdf_assert_always(0);
  1447. }
  1448. page_desc = &cc_ctx->page_desc_base[ppt_idx++];
  1449. }
  1450. /* put each TX Desc VA to SPT pages and
  1451. * get corresponding ID
  1452. */
  1453. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  1454. avail_entry_index,
  1455. tx_desc);
  1456. tx_desc->id =
  1457. dp_cc_desc_id_generate(page_desc->ppt_index,
  1458. avail_entry_index);
  1459. tx_desc->pool_id = pool_id;
  1460. dp_tx_desc_set_magic(tx_desc, DP_TX_MAGIC_PATTERN_FREE);
  1461. tx_desc = tx_desc->next;
  1462. avail_entry_index = (avail_entry_index + 1) &
  1463. DP_CC_SPT_PAGE_MAX_ENTRIES_MASK;
  1464. }
  1465. return QDF_STATUS_SUCCESS;
  1466. }
  1467. void dp_tx_desc_pool_deinit_be(struct dp_soc *soc,
  1468. struct dp_tx_desc_pool_s *tx_desc_pool,
  1469. uint8_t pool_id, bool spcl_tx_desc)
  1470. {
  1471. struct dp_spt_page_desc *page_desc;
  1472. int i = 0;
  1473. struct dp_hw_cookie_conversion_t *cc_ctx;
  1474. if (spcl_tx_desc)
  1475. cc_ctx = dp_get_spcl_tx_cookie_t(soc, pool_id);
  1476. else
  1477. cc_ctx = dp_get_tx_cookie_t(soc, pool_id);
  1478. for (i = 0; i < cc_ctx->total_page_num; i++) {
  1479. page_desc = &cc_ctx->page_desc_base[i];
  1480. qdf_mem_zero(page_desc->page_v_addr, qdf_page_size);
  1481. }
  1482. }
  1483. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1484. uint32_t dp_tx_comp_nf_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  1485. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  1486. uint32_t quota)
  1487. {
  1488. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  1489. uint32_t work_done = 0;
  1490. if (dp_srng_get_near_full_level(soc, tx_comp_ring) <
  1491. DP_SRNG_THRESH_NEAR_FULL)
  1492. return 0;
  1493. qdf_atomic_set(&tx_comp_ring->near_full, 1);
  1494. work_done++;
  1495. return work_done;
  1496. }
  1497. #endif
  1498. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1499. defined(WLAN_CONFIG_TX_DELAY)
  1500. #define PPDUID_GET_HW_LINK_ID(PPDU_ID, LINK_ID_OFFSET, LINK_ID_BITS) \
  1501. (((PPDU_ID) >> (LINK_ID_OFFSET)) & ((1 << (LINK_ID_BITS)) - 1))
  1502. #define HW_TX_DELAY_MAX 0x1000000
  1503. #define TX_COMPL_SHIFT_BUFFER_TIMESTAMP_US 10
  1504. #define HW_TX_DELAY_MASK 0x1FFFFFFF
  1505. #define TX_COMPL_BUFFER_TSTAMP_US(TSTAMP) \
  1506. (((TSTAMP) << TX_COMPL_SHIFT_BUFFER_TIMESTAMP_US) & \
  1507. HW_TX_DELAY_MASK)
  1508. static inline
  1509. QDF_STATUS dp_mlo_compute_hw_delay_us(struct dp_soc *soc,
  1510. struct dp_vdev *vdev,
  1511. struct hal_tx_completion_status *ts,
  1512. uint32_t *delay_us)
  1513. {
  1514. uint32_t ppdu_id;
  1515. uint8_t link_id_offset, link_id_bits;
  1516. uint8_t hw_link_id;
  1517. uint32_t msdu_tqm_enqueue_tstamp_us, final_msdu_tqm_enqueue_tstamp_us;
  1518. uint32_t msdu_compl_tsf_tstamp_us, final_msdu_compl_tsf_tstamp_us;
  1519. uint32_t delay;
  1520. int32_t delta_tsf2, delta_tqm;
  1521. if (!ts->valid)
  1522. return QDF_STATUS_E_INVAL;
  1523. link_id_offset = soc->link_id_offset;
  1524. link_id_bits = soc->link_id_bits;
  1525. ppdu_id = ts->ppdu_id;
  1526. hw_link_id = PPDUID_GET_HW_LINK_ID(ppdu_id, link_id_offset,
  1527. link_id_bits);
  1528. msdu_tqm_enqueue_tstamp_us =
  1529. TX_COMPL_BUFFER_TSTAMP_US(ts->buffer_timestamp);
  1530. msdu_compl_tsf_tstamp_us = ts->tsf;
  1531. delta_tsf2 = dp_mlo_get_delta_tsf2_wrt_mlo_offset(soc, hw_link_id);
  1532. delta_tqm = dp_mlo_get_delta_tqm_wrt_mlo_offset(soc);
  1533. final_msdu_tqm_enqueue_tstamp_us = (msdu_tqm_enqueue_tstamp_us +
  1534. delta_tqm) & HW_TX_DELAY_MASK;
  1535. final_msdu_compl_tsf_tstamp_us = (msdu_compl_tsf_tstamp_us +
  1536. delta_tsf2) & HW_TX_DELAY_MASK;
  1537. delay = (final_msdu_compl_tsf_tstamp_us -
  1538. final_msdu_tqm_enqueue_tstamp_us) & HW_TX_DELAY_MASK;
  1539. if (delay > HW_TX_DELAY_MAX)
  1540. return QDF_STATUS_E_FAILURE;
  1541. if (delay_us)
  1542. *delay_us = delay;
  1543. return QDF_STATUS_SUCCESS;
  1544. }
  1545. #else
  1546. static inline
  1547. QDF_STATUS dp_mlo_compute_hw_delay_us(struct dp_soc *soc,
  1548. struct dp_vdev *vdev,
  1549. struct hal_tx_completion_status *ts,
  1550. uint32_t *delay_us)
  1551. {
  1552. return QDF_STATUS_SUCCESS;
  1553. }
  1554. #endif
  1555. QDF_STATUS dp_tx_compute_tx_delay_be(struct dp_soc *soc,
  1556. struct dp_vdev *vdev,
  1557. struct hal_tx_completion_status *ts,
  1558. uint32_t *delay_us)
  1559. {
  1560. return dp_mlo_compute_hw_delay_us(soc, vdev, ts, delay_us);
  1561. }
  1562. static inline
  1563. qdf_dma_addr_t dp_tx_nbuf_map_be(struct dp_vdev *vdev,
  1564. struct dp_tx_desc_s *tx_desc,
  1565. qdf_nbuf_t nbuf)
  1566. {
  1567. qdf_nbuf_dma_clean_range_no_dsb((void *)nbuf->data,
  1568. (void *)(nbuf->data + 256));
  1569. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1570. }
  1571. static inline
  1572. void dp_tx_nbuf_unmap_be(struct dp_soc *soc,
  1573. struct dp_tx_desc_s *desc)
  1574. {
  1575. }
  1576. #ifdef QCA_DP_TX_NBUF_LIST_FREE
  1577. qdf_nbuf_t dp_tx_fast_send_be(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1578. qdf_nbuf_t nbuf)
  1579. {
  1580. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1581. struct dp_vdev *vdev = NULL;
  1582. struct dp_pdev *pdev = NULL;
  1583. struct dp_tx_desc_s *tx_desc;
  1584. uint16_t desc_pool_id;
  1585. uint16_t pkt_len;
  1586. qdf_dma_addr_t paddr;
  1587. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1588. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1589. hal_ring_handle_t hal_ring_hdl = NULL;
  1590. uint32_t *hal_tx_desc_cached;
  1591. void *hal_tx_desc;
  1592. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  1593. return nbuf;
  1594. vdev = soc->vdev_id_map[vdev_id];
  1595. if (qdf_unlikely(!vdev))
  1596. return nbuf;
  1597. desc_pool_id = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  1598. pkt_len = qdf_nbuf_headlen(nbuf);
  1599. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, pkt_len);
  1600. DP_STATS_INC(vdev, tx_i.rcvd_in_fast_xmit_flow, 1);
  1601. DP_STATS_INC(vdev, tx_i.rcvd_per_core[desc_pool_id], 1);
  1602. pdev = vdev->pdev;
  1603. if (dp_tx_limit_check(vdev, nbuf))
  1604. return nbuf;
  1605. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1606. if (qdf_unlikely(!tx_desc)) {
  1607. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1608. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  1609. return nbuf;
  1610. }
  1611. dp_tx_outstanding_inc(pdev);
  1612. /* Initialize the SW tx descriptor */
  1613. tx_desc->nbuf = nbuf;
  1614. tx_desc->frm_type = dp_tx_frm_std;
  1615. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1616. tx_desc->vdev_id = vdev_id;
  1617. tx_desc->pdev = pdev;
  1618. tx_desc->pkt_offset = 0;
  1619. tx_desc->length = pkt_len;
  1620. tx_desc->flags |= DP_TX_DESC_FLAG_SIMPLE;
  1621. if (soc->hw_txrx_stats_en)
  1622. tx_desc->flags |= DP_TX_DESC_FLAG_FASTPATH_SIMPLE;
  1623. tx_desc->nbuf->fast_recycled = 1;
  1624. if (nbuf->is_from_recycler && nbuf->fast_xmit)
  1625. tx_desc->flags |= DP_TX_DESC_FLAG_FAST;
  1626. paddr = dp_tx_nbuf_map_be(vdev, tx_desc, nbuf);
  1627. if (!paddr) {
  1628. /* Handle failure */
  1629. dp_err("qdf_nbuf_map failed");
  1630. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1631. goto release_desc;
  1632. }
  1633. tx_desc->dma_addr = paddr;
  1634. hal_tx_desc_cached = (void *)cached_desc;
  1635. hal_tx_desc_cached[0] = (uint32_t)tx_desc->dma_addr;
  1636. hal_tx_desc_cached[1] = tx_desc->id <<
  1637. TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB;
  1638. /* bank_id */
  1639. hal_tx_desc_cached[2] = vdev->bank_id << TCL_DATA_CMD_BANK_ID_LSB;
  1640. hal_tx_desc_cached[3] = vdev->htt_tcl_metadata <<
  1641. TCL_DATA_CMD_TCL_CMD_NUMBER_LSB;
  1642. hal_tx_desc_cached[4] = tx_desc->length;
  1643. /* l3 and l4 checksum enable */
  1644. hal_tx_desc_cached[4] |= DP_TX_L3_L4_CSUM_ENABLE <<
  1645. TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB;
  1646. hal_tx_desc_cached[5] = vdev->lmac_id << TCL_DATA_CMD_PMAC_ID_LSB;
  1647. hal_tx_desc_cached[5] |= vdev->vdev_id << TCL_DATA_CMD_VDEV_ID_LSB;
  1648. if (vdev->opmode == wlan_op_mode_sta)
  1649. hal_tx_desc_cached[6] = vdev->bss_ast_idx |
  1650. ((vdev->bss_ast_hash & 0xF) <<
  1651. TCL_DATA_CMD_CACHE_SET_NUM_LSB);
  1652. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, desc_pool_id);
  1653. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1654. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  1655. DP_STATS_INC(soc, tx.tcl_ring_full[desc_pool_id], 1);
  1656. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1657. goto ring_access_fail2;
  1658. }
  1659. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1660. if (qdf_unlikely(!hal_tx_desc)) {
  1661. dp_verbose_debug("TCL ring full ring_id:%d", desc_pool_id);
  1662. DP_STATS_INC(soc, tx.tcl_ring_full[desc_pool_id], 1);
  1663. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1664. goto ring_access_fail;
  1665. }
  1666. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1667. /* Sync cached descriptor with HW */
  1668. qdf_mem_copy(hal_tx_desc, hal_tx_desc_cached, DP_TX_FAST_DESC_SIZE);
  1669. qdf_dsb();
  1670. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  1671. DP_STATS_INC(soc, tx.tcl_enq[desc_pool_id], 1);
  1672. status = QDF_STATUS_SUCCESS;
  1673. ring_access_fail:
  1674. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1675. ring_access_fail2:
  1676. if (status != QDF_STATUS_SUCCESS) {
  1677. dp_tx_nbuf_unmap_be(soc, tx_desc);
  1678. goto release_desc;
  1679. }
  1680. return NULL;
  1681. release_desc:
  1682. dp_tx_desc_release(soc, tx_desc, desc_pool_id);
  1683. return nbuf;
  1684. }
  1685. #endif
  1686. QDF_STATUS dp_tx_desc_pool_alloc_be(struct dp_soc *soc, uint32_t num_elem,
  1687. uint8_t pool_id)
  1688. {
  1689. return QDF_STATUS_SUCCESS;
  1690. }
  1691. void dp_tx_desc_pool_free_be(struct dp_soc *soc, uint8_t pool_id)
  1692. {
  1693. }