1de47959b6
Some targets have a single synthesizer and it allows a single Spectral detector to scan in 160 MHz /165 MHz. Enable Agile Spectral scanning in 160 MHz / 165 MHz for such targets. Agile creq2 will be populated in the WMI command after WMI interface changes are merged. CRs-Fixed: 2648480 Change-Id: I8522cbeeab29ac41479e3041eea376b081c0758a
151 line
5.1 KiB
C
151 line
5.1 KiB
C
/*
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* Copyright (c) 2016-2018, 2020 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _WMI_UNIFIED_DBR_PARAM_H_
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#define _WMI_UNIFIED_DBR_PARAM_H_
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#define WMI_HOST_DBR_RING_ADDR_LO_S 0
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#define WMI_HOST_DBR_RING_ADDR_LO_M 0xffffffff
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#define WMI_HOST_DBR_RING_ADDR_LO \
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(WMI_HOST_DBR_RING_ADDR_LO_M << WMI_HOST_DBR_RING_ADDR_LO_S)
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#define WMI_HOST_DBR_RING_ADDR_LO_GET(dword) \
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WMI_HOST_F_MS(dword, WMI_HOST_DBR_RING_ADDR_LO)
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#define WMI_HOST_DBR_RING_ADDR_LO_SET(dword, val) \
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WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_RING_ADDR_LO)
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#define WMI_HOST_DBR_RING_ADDR_HI_S 0
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#define WMI_HOST_DBR_RING_ADDR_HI_M 0xf
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#define WMI_HOST_DBR_RING_ADDR_HI \
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(WMI_HOST_DBR_RING_ADDR_HI_M << WMI_HOST_DBR_RING_ADDR_HI_S)
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#define WMI_HOST_DBR_RING_ADDR_HI_GET(dword) \
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WMI_HOST_F_MS(dword, WMI_HOST_DBR_RING_ADDR_HI)
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#define WMI_HOST_DBR_RING_ADDR_HI_SET(dword, val) \
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WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_RING_ADDR_HI)
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#define WMI_HOST_DBR_DATA_ADDR_LO_S 0
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#define WMI_HOST_DBR_DATA_ADDR_LO_M 0xffffffff
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#define WMI_HOST_DBR_DATA_ADDR_LO \
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(WMI_HOST_DBR_DATA_ADDR_LO_M << WMI_HOST_DBR_DATA_ADDR_LO_S)
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#define WMI_HOST_DBR_DATA_ADDR_LO_GET(dword) \
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WMI_HOST_F_MS(dword, WMI_HOST_DBR_DATA_ADDR_LO)
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#define WMI_HOST_DBR_DATA_ADDR_LO_SET(dword, val) \
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WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_DATA_ADDR_LO)
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#define WMI_HOST_DBR_DATA_ADDR_HI_S 0
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#define WMI_HOST_DBR_DATA_ADDR_HI_M 0xf
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#define WMI_HOST_DBR_DATA_ADDR_HI \
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(WMI_HOST_DBR_DATA_ADDR_HI_M << WMI_HOST_DBR_DATA_ADDR_HI_S)
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#define WMI_HOST_DBR_DATA_ADDR_HI_GET(dword) \
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WMI_HOST_F_MS(dword, WMI_HOST_DBR_DATA_ADDR_HI)
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#define WMI_HOST_DBR_DATA_ADDR_HI_SET(dword, val) \
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WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_DATA_ADDR_HI)
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#define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_S 12
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#define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_M 0x7ffff
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#define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA \
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(WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_M << \
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WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_S)
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#define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_GET(dword) \
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WMI_HOST_F_MS(dword, WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA)
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#define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_SET(dword, val) \
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WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA)
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#define WMI_HOST_MAX_NUM_CHAINS 8
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/**
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* struct direct_buf_rx_rsp: direct buffer rx response structure
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*
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* @pdev_id: Index of the pdev for which response is received
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* @mod_mod: Index of the module for which respone is received
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* @num_buf_release_entry: Number of buffers released through event
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* @dbr_entries: Pointer to direct buffer rx entry struct
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*/
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struct direct_buf_rx_rsp {
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uint32_t pdev_id;
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uint32_t mod_id;
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uint32_t num_buf_release_entry;
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uint32_t num_meta_data_entry;
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struct direct_buf_rx_entry *dbr_entries;
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};
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/**
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* struct direct_buf_rx_cfg_req: direct buffer rx config request structure
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*
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* @pdev_id: Index of the pdev for which response is received
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* @mod_id: Index of the module for which respone is received
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* @base_paddr_lo: Lower 32bits of ring base address
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* @base_paddr_hi: Higher 32bits of ring base address
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* @head_idx_paddr_lo: Lower 32bits of head idx register address
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* @head_idx_paddr_hi: Higher 32bits of head idx register address
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* @tail_idx_paddr_lo: Lower 32bits of tail idx register address
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* @tail_idx_paddr_hi: Higher 32bits of tail idx register address
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* @buf_size: Size of the buffer for each pointer in the ring
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* @num_elems: Number of pointers allocated and part of the source ring
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*/
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struct direct_buf_rx_cfg_req {
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uint32_t pdev_id;
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uint32_t mod_id;
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uint32_t base_paddr_lo;
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uint32_t base_paddr_hi;
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uint32_t head_idx_paddr_lo;
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uint32_t head_idx_paddr_hi;
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uint32_t tail_idx_paddr_hi;
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uint32_t tail_idx_paddr_lo;
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uint32_t buf_size;
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uint32_t num_elems;
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uint32_t event_timeout_ms;
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uint32_t num_resp_per_event;
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};
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/**
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* struct direct_buf_rx_metadata: direct buffer metadata
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*
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* @noisefloor: noisefloor
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* @reset_delay: reset delay
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* @cfreq1: center frequency 1
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* @cfreq2: center frequency 2
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* @ch_width: channel width
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*/
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struct direct_buf_rx_metadata {
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int32_t noisefloor[WMI_HOST_MAX_NUM_CHAINS];
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uint32_t reset_delay;
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uint32_t cfreq1;
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uint32_t cfreq2;
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uint32_t ch_width;
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};
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/**
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* struct direct_buf_rx_entry: direct buffer rx release entry structure
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*
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* @addr_lo: LSB 32-bits of the buffer
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* @addr_hi: MSB 32-bits of the buffer
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* @len: Length of the buffer
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*/
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struct direct_buf_rx_entry {
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uint32_t paddr_lo;
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uint32_t paddr_hi;
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uint32_t len;
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};
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#endif /* _WMI_UNIFIED_DBR_PARAM_H_ */
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