sde_kms.c 89 KB

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  1. /*
  2. * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <drm/drm_crtc.h>
  20. #include <drm/drm_fixed.h>
  21. #include <linux/debugfs.h>
  22. #include <linux/of_address.h>
  23. #include <linux/of_irq.h>
  24. #include <linux/dma-buf.h>
  25. #include <linux/memblock.h>
  26. #include <drm/drm_atomic_uapi.h>
  27. #include <drm/drm_probe_helper.h>
  28. #include "msm_drv.h"
  29. #include "msm_mmu.h"
  30. #include "msm_gem.h"
  31. #include "dsi_display.h"
  32. #include "dsi_drm.h"
  33. #include "sde_wb.h"
  34. #include "dp_display.h"
  35. #include "dp_drm.h"
  36. #include "sde_kms.h"
  37. #include "sde_core_irq.h"
  38. #include "sde_formats.h"
  39. #include "sde_hw_vbif.h"
  40. #include "sde_vbif.h"
  41. #include "sde_encoder.h"
  42. #include "sde_plane.h"
  43. #include "sde_crtc.h"
  44. #include "sde_reg_dma.h"
  45. #include "sde_connector.h"
  46. #include <soc/qcom/scm.h>
  47. #include "soc/qcom/secure_buffer.h"
  48. #include <linux/qtee_shmbridge.h>
  49. #define CREATE_TRACE_POINTS
  50. #include "sde_trace.h"
  51. /* defines for secure channel call */
  52. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  53. #define MDP_DEVICE_ID 0x1A
  54. static const char * const iommu_ports[] = {
  55. "mdp_0",
  56. };
  57. /**
  58. * Controls size of event log buffer. Specified as a power of 2.
  59. */
  60. #define SDE_EVTLOG_SIZE 1024
  61. /*
  62. * To enable overall DRM driver logging
  63. * # echo 0x2 > /sys/module/drm/parameters/debug
  64. *
  65. * To enable DRM driver h/w logging
  66. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  67. *
  68. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  69. */
  70. #define SDE_DEBUGFS_DIR "msm_sde"
  71. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  72. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  73. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  74. /**
  75. * sdecustom - enable certain driver customizations for sde clients
  76. * Enabling this modifies the standard DRM behavior slightly and assumes
  77. * that the clients have specific knowledge about the modifications that
  78. * are involved, so don't enable this unless you know what you're doing.
  79. *
  80. * Parts of the driver that are affected by this setting may be located by
  81. * searching for invocations of the 'sde_is_custom_client()' function.
  82. *
  83. * This is disabled by default.
  84. */
  85. static bool sdecustom = true;
  86. module_param(sdecustom, bool, 0400);
  87. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  88. static int sde_kms_hw_init(struct msm_kms *kms);
  89. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  90. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  91. static int _sde_kms_register_events(struct msm_kms *kms,
  92. struct drm_mode_object *obj, u32 event, bool en);
  93. bool sde_is_custom_client(void)
  94. {
  95. return sdecustom;
  96. }
  97. #ifdef CONFIG_DEBUG_FS
  98. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  99. {
  100. struct msm_drm_private *priv;
  101. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  102. return NULL;
  103. priv = sde_kms->dev->dev_private;
  104. return priv->debug_root;
  105. }
  106. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  107. {
  108. void *p;
  109. int rc;
  110. void *debugfs_root;
  111. p = sde_hw_util_get_log_mask_ptr();
  112. if (!sde_kms || !p)
  113. return -EINVAL;
  114. debugfs_root = sde_debugfs_get_root(sde_kms);
  115. if (!debugfs_root)
  116. return -EINVAL;
  117. /* allow debugfs_root to be NULL */
  118. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  119. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  120. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  121. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  122. if (rc) {
  123. SDE_ERROR("failed to init perf %d\n", rc);
  124. return rc;
  125. }
  126. if (sde_kms->catalog->qdss_count)
  127. debugfs_create_u32("qdss", 0600, debugfs_root,
  128. (u32 *)&sde_kms->qdss_enabled);
  129. return 0;
  130. }
  131. static void _sde_debugfs_destroy(struct sde_kms *sde_kms)
  132. {
  133. /* don't need to NULL check debugfs_root */
  134. if (sde_kms) {
  135. sde_debugfs_vbif_destroy(sde_kms);
  136. sde_debugfs_core_irq_destroy(sde_kms);
  137. }
  138. }
  139. #else
  140. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  141. {
  142. return 0;
  143. }
  144. static void _sde_debugfs_destroy(struct sde_kms *sde_kms)
  145. {
  146. }
  147. #endif
  148. static int sde_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  149. {
  150. int ret = 0;
  151. SDE_ATRACE_BEGIN("sde_kms_enable_vblank");
  152. ret = sde_crtc_vblank(crtc, true);
  153. SDE_ATRACE_END("sde_kms_enable_vblank");
  154. return ret;
  155. }
  156. static void sde_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  157. {
  158. SDE_ATRACE_BEGIN("sde_kms_disable_vblank");
  159. sde_crtc_vblank(crtc, false);
  160. SDE_ATRACE_END("sde_kms_disable_vblank");
  161. }
  162. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  163. struct drm_crtc *crtc)
  164. {
  165. struct drm_encoder *encoder;
  166. struct drm_device *dev;
  167. int ret;
  168. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  169. SDE_ERROR("invalid params\n");
  170. return;
  171. }
  172. if (!crtc->state->enable) {
  173. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  174. return;
  175. }
  176. if (!crtc->state->active) {
  177. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  178. return;
  179. }
  180. dev = crtc->dev;
  181. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  182. if (encoder->crtc != crtc)
  183. continue;
  184. /*
  185. * Video Mode - Wait for VSYNC
  186. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  187. * complete
  188. */
  189. SDE_EVT32_VERBOSE(DRMID(crtc));
  190. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  191. if (ret && ret != -EWOULDBLOCK) {
  192. SDE_ERROR(
  193. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  194. crtc->base.id, encoder->base.id, ret);
  195. break;
  196. }
  197. }
  198. }
  199. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  200. struct drm_crtc *crtc, bool enable)
  201. {
  202. struct drm_device *dev;
  203. struct msm_drm_private *priv;
  204. struct sde_mdss_cfg *sde_cfg;
  205. struct drm_plane *plane;
  206. int i, ret;
  207. dev = sde_kms->dev;
  208. priv = dev->dev_private;
  209. sde_cfg = sde_kms->catalog;
  210. ret = sde_vbif_halt_xin_mask(sde_kms,
  211. sde_cfg->sui_block_xin_mask, enable);
  212. if (ret) {
  213. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  214. return ret;
  215. }
  216. if (enable) {
  217. for (i = 0; i < priv->num_planes; i++) {
  218. plane = priv->planes[i];
  219. sde_plane_secure_ctrl_xin_client(plane, crtc);
  220. }
  221. }
  222. return 0;
  223. }
  224. /**
  225. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  226. * @sde_kms: Pointer to sde_kms struct
  227. * @vimd: switch the stage 2 translation to this VMID
  228. */
  229. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  230. {
  231. struct drm_device *dev;
  232. struct scm_desc desc = {0};
  233. uint32_t num_sids;
  234. uint32_t *sec_sid;
  235. uint32_t mem_protect_sd_ctrl_id = MEM_PROTECT_SD_CTRL_SWITCH;
  236. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  237. int ret = 0, i;
  238. struct qtee_shm shm;
  239. bool qtee_en = qtee_shmbridge_is_enabled();
  240. dev = sde_kms->dev;
  241. num_sids = sde_cfg->sec_sid_mask_count;
  242. if (!num_sids) {
  243. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  244. return -EINVAL;
  245. }
  246. if (qtee_en) {
  247. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  248. &shm);
  249. if (ret)
  250. return -ENOMEM;
  251. sec_sid = (uint32_t *) shm.vaddr;
  252. desc.args[1] = shm.paddr;
  253. desc.args[2] = shm.size;
  254. } else {
  255. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  256. if (!sec_sid)
  257. return -ENOMEM;
  258. desc.args[1] = SCM_BUFFER_PHYS(sec_sid);
  259. desc.args[2] = sizeof(uint32_t) * num_sids;
  260. }
  261. desc.arginfo = SCM_ARGS(4, SCM_VAL, SCM_RW, SCM_VAL, SCM_VAL);
  262. desc.args[0] = MDP_DEVICE_ID;
  263. desc.args[3] = vmid;
  264. for (i = 0; i < num_sids; i++) {
  265. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  266. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  267. }
  268. dma_map_single(dev->dev, sec_sid, num_sids *sizeof(uint32_t),
  269. DMA_TO_DEVICE);
  270. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  271. vmid, num_sids, qtee_en);
  272. ret = scm_call2(SCM_SIP_FNID(SCM_SVC_MP,
  273. mem_protect_sd_ctrl_id), &desc);
  274. if (ret)
  275. SDE_ERROR("Error:scm_call2, vmid %lld, ret%d\n",
  276. desc.args[3], ret);
  277. SDE_EVT32(mem_protect_sd_ctrl_id, desc.args[0], desc.args[2],
  278. desc.args[3], qtee_en, num_sids, ret);
  279. if (qtee_en)
  280. qtee_shmbridge_free_shm(&shm);
  281. else
  282. kfree(sec_sid);
  283. return ret;
  284. }
  285. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  286. {
  287. u32 ret;
  288. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  289. return 0;
  290. /* detach_all_contexts */
  291. ret = sde_kms_mmu_detach(sde_kms, false);
  292. if (ret) {
  293. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  294. goto mmu_error;
  295. }
  296. ret = _sde_kms_scm_call(sde_kms, vmid);
  297. if (ret) {
  298. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  299. goto scm_error;
  300. }
  301. return 0;
  302. scm_error:
  303. sde_kms_mmu_attach(sde_kms, false);
  304. mmu_error:
  305. atomic_dec(&sde_kms->detach_all_cb);
  306. return ret;
  307. }
  308. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, u32 vmid,
  309. u32 old_vmid)
  310. {
  311. u32 ret;
  312. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  313. return 0;
  314. ret = _sde_kms_scm_call(sde_kms, vmid);
  315. if (ret) {
  316. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  317. goto scm_error;
  318. }
  319. /* attach_all_contexts */
  320. ret = sde_kms_mmu_attach(sde_kms, false);
  321. if (ret) {
  322. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  323. goto mmu_error;
  324. }
  325. return 0;
  326. mmu_error:
  327. _sde_kms_scm_call(sde_kms, old_vmid);
  328. scm_error:
  329. atomic_inc(&sde_kms->detach_all_cb);
  330. return ret;
  331. }
  332. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  333. {
  334. u32 ret;
  335. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  336. return 0;
  337. /* detach secure_context */
  338. ret = sde_kms_mmu_detach(sde_kms, true);
  339. if (ret) {
  340. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  341. goto mmu_error;
  342. }
  343. ret = _sde_kms_scm_call(sde_kms, vmid);
  344. if (ret) {
  345. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  346. goto scm_error;
  347. }
  348. return 0;
  349. scm_error:
  350. sde_kms_mmu_attach(sde_kms, true);
  351. mmu_error:
  352. atomic_dec(&sde_kms->detach_sec_cb);
  353. return ret;
  354. }
  355. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, u32 vmid,
  356. u32 old_vmid)
  357. {
  358. u32 ret;
  359. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  360. return 0;
  361. ret = _sde_kms_scm_call(sde_kms, vmid);
  362. if (ret) {
  363. goto scm_error;
  364. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  365. }
  366. ret = sde_kms_mmu_attach(sde_kms, true);
  367. if (ret) {
  368. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  369. goto mmu_error;
  370. }
  371. return 0;
  372. mmu_error:
  373. _sde_kms_scm_call(sde_kms, old_vmid);
  374. scm_error:
  375. atomic_inc(&sde_kms->detach_sec_cb);
  376. return ret;
  377. }
  378. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  379. struct drm_crtc *crtc, bool enable)
  380. {
  381. int ret;
  382. if (enable) {
  383. ret = pm_runtime_get_sync(sde_kms->dev->dev);
  384. if (ret < 0) {
  385. SDE_ERROR("failed to enable resource, ret:%d\n", ret);
  386. return ret;
  387. }
  388. sde_crtc_misr_setup(crtc, true, 1);
  389. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  390. if (ret) {
  391. sde_crtc_misr_setup(crtc, false, 0);
  392. pm_runtime_put_sync(sde_kms->dev->dev);
  393. return ret;
  394. }
  395. } else {
  396. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  397. sde_crtc_misr_setup(crtc, false, 0);
  398. pm_runtime_put_sync(sde_kms->dev->dev);
  399. }
  400. return 0;
  401. }
  402. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  403. bool post_commit)
  404. {
  405. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  406. int old_smmu_state = smmu_state->state;
  407. int ret = 0;
  408. u32 vmid;
  409. if (!sde_kms || !crtc) {
  410. SDE_ERROR("invalid argument(s)\n");
  411. return -EINVAL;
  412. }
  413. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  414. post_commit, smmu_state->sui_misr_state,
  415. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  416. if ((!smmu_state->transition_type) ||
  417. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  418. /* Bail out */
  419. return 0;
  420. /* enable sui misr if requested, before the transition */
  421. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  422. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  423. if (ret) {
  424. smmu_state->sui_misr_state = NONE;
  425. goto end;
  426. }
  427. }
  428. mutex_lock(&sde_kms->secure_transition_lock);
  429. switch (smmu_state->state) {
  430. case DETACH_ALL_REQ:
  431. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  432. if (!ret)
  433. smmu_state->state = DETACHED;
  434. break;
  435. case ATTACH_ALL_REQ:
  436. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL,
  437. VMID_CP_SEC_DISPLAY);
  438. if (!ret) {
  439. smmu_state->state = ATTACHED;
  440. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  441. }
  442. break;
  443. case DETACH_SEC_REQ:
  444. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  445. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  446. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  447. if (!ret)
  448. smmu_state->state = DETACHED_SEC;
  449. break;
  450. case ATTACH_SEC_REQ:
  451. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  452. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  453. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL, vmid);
  454. if (!ret) {
  455. smmu_state->state = ATTACHED;
  456. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  457. }
  458. break;
  459. default:
  460. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  461. DRMID(crtc), smmu_state->state,
  462. smmu_state->transition_type);
  463. ret = -EINVAL;
  464. break;
  465. }
  466. mutex_unlock(&sde_kms->secure_transition_lock);
  467. /* disable sui misr if requested, after the transition */
  468. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  469. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  470. if (ret)
  471. goto end;
  472. }
  473. end:
  474. smmu_state->transition_error = false;
  475. if (ret) {
  476. smmu_state->transition_error = true;
  477. SDE_ERROR(
  478. "crtc%d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  479. DRMID(crtc), old_smmu_state, smmu_state->state,
  480. smmu_state->secure_level, ret);
  481. smmu_state->state = smmu_state->prev_state;
  482. smmu_state->secure_level = smmu_state->prev_secure_level;
  483. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ)
  484. _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  485. }
  486. SDE_DEBUG("crtc %d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  487. DRMID(crtc), old_smmu_state, smmu_state->state,
  488. smmu_state->secure_level, ret);
  489. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->prev_state,
  490. smmu_state->transition_type,
  491. smmu_state->transition_error,
  492. smmu_state->secure_level, smmu_state->prev_secure_level,
  493. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  494. smmu_state->sui_misr_state = NONE;
  495. smmu_state->transition_type = NONE;
  496. return ret;
  497. }
  498. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  499. struct drm_atomic_state *state)
  500. {
  501. struct drm_crtc *crtc;
  502. struct drm_crtc_state *old_crtc_state;
  503. struct drm_plane *plane;
  504. struct drm_plane_state *plane_state;
  505. struct sde_kms *sde_kms = to_sde_kms(kms);
  506. struct drm_device *dev = sde_kms->dev;
  507. int i, ops = 0, ret = 0;
  508. bool old_valid_fb = false;
  509. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  510. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  511. if (!crtc->state || !crtc->state->active)
  512. continue;
  513. /*
  514. * It is safe to assume only one active crtc,
  515. * and compatible translation modes on the
  516. * planes staged on this crtc.
  517. * otherwise validation would have failed.
  518. * For this CRTC,
  519. */
  520. /*
  521. * 1. Check if old state on the CRTC has planes
  522. * staged with valid fbs
  523. */
  524. for_each_old_plane_in_state(state, plane, plane_state, i) {
  525. if (!plane_state->crtc)
  526. continue;
  527. if (plane_state->fb) {
  528. old_valid_fb = true;
  529. break;
  530. }
  531. }
  532. /*
  533. * 2.Get the operations needed to be performed before
  534. * secure transition can be initiated.
  535. */
  536. ops = sde_crtc_get_secure_transition_ops(crtc,
  537. old_crtc_state, old_valid_fb);
  538. if (ops < 0) {
  539. SDE_ERROR("invalid secure operations %x\n", ops);
  540. return ops;
  541. }
  542. if (!ops) {
  543. smmu_state->transition_error = false;
  544. goto no_ops;
  545. }
  546. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  547. crtc->base.id, ops, crtc->state);
  548. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  549. /* 3. Perform operations needed for secure transition */
  550. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  551. SDE_DEBUG("wait_for_transfer_done\n");
  552. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  553. }
  554. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  555. SDE_DEBUG("cleanup planes\n");
  556. drm_atomic_helper_cleanup_planes(dev, state);
  557. }
  558. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  559. SDE_DEBUG("secure ctrl\n");
  560. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  561. }
  562. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  563. SDE_DEBUG("prepare planes %d",
  564. crtc->state->plane_mask);
  565. drm_atomic_crtc_for_each_plane(plane,
  566. crtc) {
  567. const struct drm_plane_helper_funcs *funcs;
  568. plane_state = plane->state;
  569. funcs = plane->helper_private;
  570. SDE_DEBUG("psde:%d FB[%u]\n",
  571. plane->base.id,
  572. plane->fb->base.id);
  573. if (!funcs)
  574. continue;
  575. if (funcs->prepare_fb(plane, plane_state)) {
  576. ret = funcs->prepare_fb(plane,
  577. plane_state);
  578. if (ret)
  579. return ret;
  580. }
  581. }
  582. }
  583. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  584. SDE_DEBUG("secure operations completed\n");
  585. }
  586. no_ops:
  587. return 0;
  588. }
  589. static int _sde_kms_release_splash_buffer(unsigned int mem_addr,
  590. unsigned int splash_buffer_size,
  591. unsigned int ramdump_base,
  592. unsigned int ramdump_buffer_size)
  593. {
  594. unsigned long pfn_start, pfn_end, pfn_idx;
  595. int ret = 0;
  596. if (!mem_addr || !splash_buffer_size) {
  597. SDE_ERROR("invalid params\n");
  598. return -EINVAL;
  599. }
  600. /* leave ramdump memory only if base address matches */
  601. if (ramdump_base == mem_addr &&
  602. ramdump_buffer_size <= splash_buffer_size) {
  603. mem_addr += ramdump_buffer_size;
  604. splash_buffer_size -= ramdump_buffer_size;
  605. }
  606. pfn_start = mem_addr >> PAGE_SHIFT;
  607. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  608. ret = memblock_free(mem_addr, splash_buffer_size);
  609. if (ret) {
  610. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  611. return ret;
  612. }
  613. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  614. free_reserved_page(pfn_to_page(pfn_idx));
  615. return ret;
  616. }
  617. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  618. struct sde_splash_mem *splash)
  619. {
  620. struct msm_mmu *mmu = NULL;
  621. int ret = 0;
  622. if (!sde_kms->aspace[0]) {
  623. SDE_ERROR("aspace not found for sde kms node\n");
  624. return -EINVAL;
  625. }
  626. mmu = sde_kms->aspace[0]->mmu;
  627. if (!mmu) {
  628. SDE_ERROR("mmu not found for aspace\n");
  629. return -EINVAL;
  630. }
  631. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  632. SDE_ERROR("invalid input params for map\n");
  633. return -EINVAL;
  634. }
  635. if (!splash->ref_cnt) {
  636. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  637. splash->splash_buf_base,
  638. splash->splash_buf_size,
  639. IOMMU_READ | IOMMU_NOEXEC);
  640. if (ret)
  641. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  642. }
  643. splash->ref_cnt++;
  644. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  645. splash->splash_buf_base,
  646. splash->splash_buf_size,
  647. splash->ref_cnt);
  648. return ret;
  649. }
  650. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  651. {
  652. int i = 0;
  653. int ret = 0;
  654. if (!sde_kms)
  655. return -EINVAL;
  656. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  657. ret = _sde_kms_splash_mem_get(sde_kms,
  658. sde_kms->splash_data.splash_display[i].splash);
  659. if (ret)
  660. return ret;
  661. }
  662. return ret;
  663. }
  664. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  665. struct sde_splash_mem *splash)
  666. {
  667. struct msm_mmu *mmu = NULL;
  668. int rc = 0;
  669. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  670. SDE_ERROR("invalid params\n");
  671. return -EINVAL;
  672. }
  673. mmu = sde_kms->aspace[0]->mmu;
  674. if (!splash || !splash->ref_cnt ||
  675. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  676. return -EINVAL;
  677. splash->ref_cnt--;
  678. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  679. splash->splash_buf_base, splash->ref_cnt);
  680. if (!splash->ref_cnt) {
  681. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  682. splash->splash_buf_size);
  683. rc = _sde_kms_release_splash_buffer(splash->splash_buf_base,
  684. splash->splash_buf_size, splash->ramdump_base,
  685. splash->ramdump_size);
  686. splash->splash_buf_base = 0;
  687. splash->splash_buf_size = 0;
  688. }
  689. return rc;
  690. }
  691. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  692. {
  693. int i = 0;
  694. int ret = 0;
  695. if (!sde_kms)
  696. return -EINVAL;
  697. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  698. ret = _sde_kms_splash_mem_put(sde_kms,
  699. sde_kms->splash_data.splash_display[i].splash);
  700. if (ret)
  701. return ret;
  702. }
  703. return ret;
  704. }
  705. static void sde_kms_prepare_commit(struct msm_kms *kms,
  706. struct drm_atomic_state *state)
  707. {
  708. struct sde_kms *sde_kms;
  709. struct msm_drm_private *priv;
  710. struct drm_device *dev;
  711. struct drm_encoder *encoder;
  712. struct drm_crtc *crtc;
  713. struct drm_crtc_state *crtc_state;
  714. int i, rc;
  715. if (!kms)
  716. return;
  717. sde_kms = to_sde_kms(kms);
  718. dev = sde_kms->dev;
  719. if (!dev || !dev->dev_private)
  720. return;
  721. priv = dev->dev_private;
  722. SDE_ATRACE_BEGIN("prepare_commit");
  723. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  724. if (rc < 0) {
  725. SDE_ERROR("failed to enable power resources %d\n", rc);
  726. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  727. goto end;
  728. }
  729. if (sde_kms->first_kickoff) {
  730. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  731. sde_kms->first_kickoff = false;
  732. }
  733. for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
  734. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  735. head) {
  736. if (encoder->crtc != crtc)
  737. continue;
  738. sde_encoder_prepare_commit(encoder);
  739. }
  740. }
  741. /*
  742. * NOTE: for secure use cases we want to apply the new HW
  743. * configuration only after completing preparation for secure
  744. * transitions prepare below if any transtions is required.
  745. */
  746. sde_kms_prepare_secure_transition(kms, state);
  747. end:
  748. SDE_ATRACE_END("prepare_commit");
  749. }
  750. static void sde_kms_commit(struct msm_kms *kms,
  751. struct drm_atomic_state *old_state)
  752. {
  753. struct sde_kms *sde_kms;
  754. struct drm_crtc *crtc;
  755. struct drm_crtc_state *old_crtc_state;
  756. int i;
  757. if (!kms || !old_state)
  758. return;
  759. sde_kms = to_sde_kms(kms);
  760. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  761. SDE_ERROR("power resource is not enabled\n");
  762. return;
  763. }
  764. SDE_ATRACE_BEGIN("sde_kms_commit");
  765. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  766. if (crtc->state->active) {
  767. SDE_EVT32(DRMID(crtc));
  768. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  769. }
  770. }
  771. SDE_ATRACE_END("sde_kms_commit");
  772. }
  773. static void _sde_kms_free_splash_region(struct sde_kms *sde_kms,
  774. struct sde_splash_display *splash_display)
  775. {
  776. if (!sde_kms || !splash_display ||
  777. !sde_kms->splash_data.num_splash_displays)
  778. return;
  779. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  780. sde_kms->splash_data.num_splash_displays--;
  781. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  782. sde_kms->splash_data.num_splash_displays);
  783. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  784. }
  785. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  786. struct drm_crtc *crtc)
  787. {
  788. struct msm_drm_private *priv;
  789. struct sde_splash_display *splash_display;
  790. int i;
  791. if (!sde_kms || !crtc)
  792. return;
  793. priv = sde_kms->dev->dev_private;
  794. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  795. return;
  796. SDE_EVT32(DRMID(crtc), crtc->state->active,
  797. sde_kms->splash_data.num_splash_displays);
  798. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  799. splash_display = &sde_kms->splash_data.splash_display[i];
  800. if (splash_display->encoder &&
  801. crtc == splash_display->encoder->crtc)
  802. break;
  803. }
  804. if (i >= MAX_DSI_DISPLAYS)
  805. return;
  806. if (splash_display->cont_splash_enabled) {
  807. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  808. splash_display, false);
  809. _sde_kms_free_splash_region(sde_kms, splash_display);
  810. }
  811. /* remove the votes if all displays are done with splash */
  812. if (!sde_kms->splash_data.num_splash_displays) {
  813. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  814. sde_power_data_bus_set_quota(&priv->phandle, i,
  815. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  816. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  817. pm_runtime_put_sync(sde_kms->dev->dev);
  818. }
  819. }
  820. static void sde_kms_complete_commit(struct msm_kms *kms,
  821. struct drm_atomic_state *old_state)
  822. {
  823. struct sde_kms *sde_kms;
  824. struct msm_drm_private *priv;
  825. struct drm_crtc *crtc;
  826. struct drm_crtc_state *old_crtc_state;
  827. struct drm_connector *connector;
  828. struct drm_connector_state *old_conn_state;
  829. struct msm_display_conn_params params;
  830. int i, rc = 0;
  831. if (!kms || !old_state)
  832. return;
  833. sde_kms = to_sde_kms(kms);
  834. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  835. return;
  836. priv = sde_kms->dev->dev_private;
  837. if (sde_kms_power_resource_is_enabled(sde_kms->dev) < 0) {
  838. SDE_ERROR("power resource is not enabled\n");
  839. return;
  840. }
  841. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  842. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  843. sde_crtc_complete_commit(crtc, old_crtc_state);
  844. /* complete secure transitions if any */
  845. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  846. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  847. }
  848. for_each_old_connector_in_state(old_state, connector,
  849. old_conn_state, i) {
  850. struct sde_connector *c_conn;
  851. c_conn = to_sde_connector(connector);
  852. if (!c_conn->ops.post_kickoff)
  853. continue;
  854. memset(&params, 0, sizeof(params));
  855. sde_connector_complete_qsync_commit(connector, &params);
  856. rc = c_conn->ops.post_kickoff(connector, &params);
  857. if (rc) {
  858. pr_err("Connector Post kickoff failed rc=%d\n",
  859. rc);
  860. }
  861. }
  862. pm_runtime_put_sync(sde_kms->dev->dev);
  863. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  864. _sde_kms_release_splash_resource(sde_kms, crtc);
  865. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  866. SDE_ATRACE_END("sde_kms_complete_commit");
  867. }
  868. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  869. struct drm_crtc *crtc)
  870. {
  871. struct drm_encoder *encoder;
  872. struct drm_device *dev;
  873. int ret;
  874. if (!kms || !crtc || !crtc->state) {
  875. SDE_ERROR("invalid params\n");
  876. return;
  877. }
  878. dev = crtc->dev;
  879. if (!crtc->state->enable) {
  880. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  881. return;
  882. }
  883. if (!crtc->state->active) {
  884. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  885. return;
  886. }
  887. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  888. SDE_ERROR("power resource is not enabled\n");
  889. return;
  890. }
  891. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  892. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  893. if (encoder->crtc != crtc)
  894. continue;
  895. /*
  896. * Wait for post-flush if necessary to delay before
  897. * plane_cleanup. For example, wait for vsync in case of video
  898. * mode panels. This may be a no-op for command mode panels.
  899. */
  900. SDE_EVT32_VERBOSE(DRMID(crtc));
  901. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
  902. if (ret && ret != -EWOULDBLOCK) {
  903. SDE_ERROR("wait for commit done returned %d\n", ret);
  904. sde_crtc_request_frame_reset(crtc);
  905. break;
  906. }
  907. sde_crtc_complete_flip(crtc, NULL);
  908. }
  909. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  910. }
  911. static void sde_kms_prepare_fence(struct msm_kms *kms,
  912. struct drm_atomic_state *old_state)
  913. {
  914. struct drm_crtc *crtc;
  915. struct drm_crtc_state *old_crtc_state;
  916. int i, rc;
  917. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  918. SDE_ERROR("invalid argument(s)\n");
  919. return;
  920. }
  921. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  922. retry:
  923. /* attempt to acquire ww mutex for connection */
  924. rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
  925. old_state->acquire_ctx);
  926. if (rc == -EDEADLK) {
  927. drm_modeset_backoff(old_state->acquire_ctx);
  928. goto retry;
  929. }
  930. /* old_state actually contains updated crtc pointers */
  931. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  932. if (crtc->state->active || crtc->state->active_changed)
  933. sde_crtc_prepare_commit(crtc, old_crtc_state);
  934. }
  935. SDE_ATRACE_END("sde_kms_prepare_fence");
  936. }
  937. /**
  938. * _sde_kms_get_displays - query for underlying display handles and cache them
  939. * @sde_kms: Pointer to sde kms structure
  940. * Returns: Zero on success
  941. */
  942. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  943. {
  944. int rc = -ENOMEM;
  945. if (!sde_kms) {
  946. SDE_ERROR("invalid sde kms\n");
  947. return -EINVAL;
  948. }
  949. /* dsi */
  950. sde_kms->dsi_displays = NULL;
  951. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  952. if (sde_kms->dsi_display_count) {
  953. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  954. sizeof(void *),
  955. GFP_KERNEL);
  956. if (!sde_kms->dsi_displays) {
  957. SDE_ERROR("failed to allocate dsi displays\n");
  958. goto exit_deinit_dsi;
  959. }
  960. sde_kms->dsi_display_count =
  961. dsi_display_get_active_displays(sde_kms->dsi_displays,
  962. sde_kms->dsi_display_count);
  963. }
  964. /* wb */
  965. sde_kms->wb_displays = NULL;
  966. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  967. if (sde_kms->wb_display_count) {
  968. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  969. sizeof(void *),
  970. GFP_KERNEL);
  971. if (!sde_kms->wb_displays) {
  972. SDE_ERROR("failed to allocate wb displays\n");
  973. goto exit_deinit_wb;
  974. }
  975. sde_kms->wb_display_count =
  976. wb_display_get_displays(sde_kms->wb_displays,
  977. sde_kms->wb_display_count);
  978. }
  979. /* dp */
  980. sde_kms->dp_displays = NULL;
  981. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  982. if (sde_kms->dp_display_count) {
  983. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  984. sizeof(void *), GFP_KERNEL);
  985. if (!sde_kms->dp_displays) {
  986. SDE_ERROR("failed to allocate dp displays\n");
  987. goto exit_deinit_dp;
  988. }
  989. sde_kms->dp_display_count =
  990. dp_display_get_displays(sde_kms->dp_displays,
  991. sde_kms->dp_display_count);
  992. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  993. }
  994. return 0;
  995. exit_deinit_dp:
  996. kfree(sde_kms->dp_displays);
  997. sde_kms->dp_stream_count = 0;
  998. sde_kms->dp_display_count = 0;
  999. sde_kms->dp_displays = NULL;
  1000. exit_deinit_wb:
  1001. kfree(sde_kms->wb_displays);
  1002. sde_kms->wb_display_count = 0;
  1003. sde_kms->wb_displays = NULL;
  1004. exit_deinit_dsi:
  1005. kfree(sde_kms->dsi_displays);
  1006. sde_kms->dsi_display_count = 0;
  1007. sde_kms->dsi_displays = NULL;
  1008. return rc;
  1009. }
  1010. /**
  1011. * _sde_kms_release_displays - release cache of underlying display handles
  1012. * @sde_kms: Pointer to sde kms structure
  1013. */
  1014. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  1015. {
  1016. if (!sde_kms) {
  1017. SDE_ERROR("invalid sde kms\n");
  1018. return;
  1019. }
  1020. kfree(sde_kms->wb_displays);
  1021. sde_kms->wb_displays = NULL;
  1022. sde_kms->wb_display_count = 0;
  1023. kfree(sde_kms->dsi_displays);
  1024. sde_kms->dsi_displays = NULL;
  1025. sde_kms->dsi_display_count = 0;
  1026. }
  1027. /**
  1028. * _sde_kms_setup_displays - create encoders, bridges and connectors
  1029. * for underlying displays
  1030. * @dev: Pointer to drm device structure
  1031. * @priv: Pointer to private drm device data
  1032. * @sde_kms: Pointer to sde kms structure
  1033. * Returns: Zero on success
  1034. */
  1035. static int _sde_kms_setup_displays(struct drm_device *dev,
  1036. struct msm_drm_private *priv,
  1037. struct sde_kms *sde_kms)
  1038. {
  1039. static const struct sde_connector_ops dsi_ops = {
  1040. .set_info_blob = dsi_conn_set_info_blob,
  1041. .detect = dsi_conn_detect,
  1042. .get_modes = dsi_connector_get_modes,
  1043. .pre_destroy = dsi_connector_put_modes,
  1044. .mode_valid = dsi_conn_mode_valid,
  1045. .get_info = dsi_display_get_info,
  1046. .set_backlight = dsi_display_set_backlight,
  1047. .soft_reset = dsi_display_soft_reset,
  1048. .pre_kickoff = dsi_conn_pre_kickoff,
  1049. .clk_ctrl = dsi_display_clk_ctrl,
  1050. .set_power = dsi_display_set_power,
  1051. .get_mode_info = dsi_conn_get_mode_info,
  1052. .get_dst_format = dsi_display_get_dst_format,
  1053. .post_kickoff = dsi_conn_post_kickoff,
  1054. .check_status = dsi_display_check_status,
  1055. .enable_event = dsi_conn_enable_event,
  1056. .cmd_transfer = dsi_display_cmd_transfer,
  1057. .cont_splash_config = dsi_display_cont_splash_config,
  1058. .get_panel_vfp = dsi_display_get_panel_vfp,
  1059. .get_default_lms = dsi_display_get_default_lms,
  1060. };
  1061. static const struct sde_connector_ops wb_ops = {
  1062. .post_init = sde_wb_connector_post_init,
  1063. .set_info_blob = sde_wb_connector_set_info_blob,
  1064. .detect = sde_wb_connector_detect,
  1065. .get_modes = sde_wb_connector_get_modes,
  1066. .set_property = sde_wb_connector_set_property,
  1067. .get_info = sde_wb_get_info,
  1068. .soft_reset = NULL,
  1069. .get_mode_info = sde_wb_get_mode_info,
  1070. .get_dst_format = NULL,
  1071. .check_status = NULL,
  1072. .cmd_transfer = NULL,
  1073. .cont_splash_config = NULL,
  1074. .get_panel_vfp = NULL,
  1075. };
  1076. static const struct sde_connector_ops dp_ops = {
  1077. .post_init = dp_connector_post_init,
  1078. .detect = dp_connector_detect,
  1079. .get_modes = dp_connector_get_modes,
  1080. .atomic_check = dp_connector_atomic_check,
  1081. .mode_valid = dp_connector_mode_valid,
  1082. .get_info = dp_connector_get_info,
  1083. .get_mode_info = dp_connector_get_mode_info,
  1084. .post_open = dp_connector_post_open,
  1085. .check_status = NULL,
  1086. .set_colorspace = dp_connector_set_colorspace,
  1087. .config_hdr = dp_connector_config_hdr,
  1088. .cmd_transfer = NULL,
  1089. .cont_splash_config = NULL,
  1090. .get_panel_vfp = NULL,
  1091. .update_pps = dp_connector_update_pps,
  1092. };
  1093. struct msm_display_info info;
  1094. struct drm_encoder *encoder;
  1095. void *display, *connector;
  1096. int i, max_encoders;
  1097. int rc = 0;
  1098. if (!dev || !priv || !sde_kms) {
  1099. SDE_ERROR("invalid argument(s)\n");
  1100. return -EINVAL;
  1101. }
  1102. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1103. sde_kms->dp_display_count +
  1104. sde_kms->dp_stream_count;
  1105. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1106. max_encoders = ARRAY_SIZE(priv->encoders);
  1107. SDE_ERROR("capping number of displays to %d", max_encoders);
  1108. }
  1109. /* dsi */
  1110. for (i = 0; i < sde_kms->dsi_display_count &&
  1111. priv->num_encoders < max_encoders; ++i) {
  1112. display = sde_kms->dsi_displays[i];
  1113. encoder = NULL;
  1114. memset(&info, 0x0, sizeof(info));
  1115. rc = dsi_display_get_info(NULL, &info, display);
  1116. if (rc) {
  1117. SDE_ERROR("dsi get_info %d failed\n", i);
  1118. continue;
  1119. }
  1120. encoder = sde_encoder_init(dev, &info);
  1121. if (IS_ERR_OR_NULL(encoder)) {
  1122. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1123. continue;
  1124. }
  1125. rc = dsi_display_drm_bridge_init(display, encoder);
  1126. if (rc) {
  1127. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1128. sde_encoder_destroy(encoder);
  1129. continue;
  1130. }
  1131. connector = sde_connector_init(dev,
  1132. encoder,
  1133. dsi_display_get_drm_panel(display),
  1134. display,
  1135. &dsi_ops,
  1136. DRM_CONNECTOR_POLL_HPD,
  1137. DRM_MODE_CONNECTOR_DSI);
  1138. if (connector) {
  1139. priv->encoders[priv->num_encoders++] = encoder;
  1140. priv->connectors[priv->num_connectors++] = connector;
  1141. } else {
  1142. SDE_ERROR("dsi %d connector init failed\n", i);
  1143. dsi_display_drm_bridge_deinit(display);
  1144. sde_encoder_destroy(encoder);
  1145. continue;
  1146. }
  1147. rc = dsi_display_drm_ext_bridge_init(display,
  1148. encoder, connector);
  1149. if (rc) {
  1150. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1151. dsi_display_drm_bridge_deinit(display);
  1152. sde_connector_destroy(connector);
  1153. sde_encoder_destroy(encoder);
  1154. }
  1155. }
  1156. /* wb */
  1157. for (i = 0; i < sde_kms->wb_display_count &&
  1158. priv->num_encoders < max_encoders; ++i) {
  1159. display = sde_kms->wb_displays[i];
  1160. encoder = NULL;
  1161. memset(&info, 0x0, sizeof(info));
  1162. rc = sde_wb_get_info(NULL, &info, display);
  1163. if (rc) {
  1164. SDE_ERROR("wb get_info %d failed\n", i);
  1165. continue;
  1166. }
  1167. encoder = sde_encoder_init(dev, &info);
  1168. if (IS_ERR_OR_NULL(encoder)) {
  1169. SDE_ERROR("encoder init failed for wb %d\n", i);
  1170. continue;
  1171. }
  1172. rc = sde_wb_drm_init(display, encoder);
  1173. if (rc) {
  1174. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1175. sde_encoder_destroy(encoder);
  1176. continue;
  1177. }
  1178. connector = sde_connector_init(dev,
  1179. encoder,
  1180. 0,
  1181. display,
  1182. &wb_ops,
  1183. DRM_CONNECTOR_POLL_HPD,
  1184. DRM_MODE_CONNECTOR_VIRTUAL);
  1185. if (connector) {
  1186. priv->encoders[priv->num_encoders++] = encoder;
  1187. priv->connectors[priv->num_connectors++] = connector;
  1188. } else {
  1189. SDE_ERROR("wb %d connector init failed\n", i);
  1190. sde_wb_drm_deinit(display);
  1191. sde_encoder_destroy(encoder);
  1192. }
  1193. }
  1194. /* dp */
  1195. for (i = 0; i < sde_kms->dp_display_count &&
  1196. priv->num_encoders < max_encoders; ++i) {
  1197. int idx;
  1198. display = sde_kms->dp_displays[i];
  1199. encoder = NULL;
  1200. memset(&info, 0x0, sizeof(info));
  1201. rc = dp_connector_get_info(NULL, &info, display);
  1202. if (rc) {
  1203. SDE_ERROR("dp get_info %d failed\n", i);
  1204. continue;
  1205. }
  1206. encoder = sde_encoder_init(dev, &info);
  1207. if (IS_ERR_OR_NULL(encoder)) {
  1208. SDE_ERROR("dp encoder init failed %d\n", i);
  1209. continue;
  1210. }
  1211. rc = dp_drm_bridge_init(display, encoder);
  1212. if (rc) {
  1213. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1214. sde_encoder_destroy(encoder);
  1215. continue;
  1216. }
  1217. connector = sde_connector_init(dev,
  1218. encoder,
  1219. NULL,
  1220. display,
  1221. &dp_ops,
  1222. DRM_CONNECTOR_POLL_HPD,
  1223. DRM_MODE_CONNECTOR_DisplayPort);
  1224. if (connector) {
  1225. priv->encoders[priv->num_encoders++] = encoder;
  1226. priv->connectors[priv->num_connectors++] = connector;
  1227. } else {
  1228. SDE_ERROR("dp %d connector init failed\n", i);
  1229. dp_drm_bridge_deinit(display);
  1230. sde_encoder_destroy(encoder);
  1231. }
  1232. /* update display cap to MST_MODE for DP MST encoders */
  1233. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1234. for (idx = 0; idx < sde_kms->dp_stream_count; idx++) {
  1235. info.h_tile_instance[0] = idx;
  1236. encoder = sde_encoder_init(dev, &info);
  1237. if (IS_ERR_OR_NULL(encoder)) {
  1238. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1239. continue;
  1240. }
  1241. rc = dp_mst_drm_bridge_init(display, encoder);
  1242. if (rc) {
  1243. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1244. i, rc);
  1245. sde_encoder_destroy(encoder);
  1246. continue;
  1247. }
  1248. priv->encoders[priv->num_encoders++] = encoder;
  1249. }
  1250. }
  1251. return 0;
  1252. }
  1253. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1254. {
  1255. struct msm_drm_private *priv;
  1256. int i;
  1257. if (!sde_kms) {
  1258. SDE_ERROR("invalid sde_kms\n");
  1259. return;
  1260. } else if (!sde_kms->dev) {
  1261. SDE_ERROR("invalid dev\n");
  1262. return;
  1263. } else if (!sde_kms->dev->dev_private) {
  1264. SDE_ERROR("invalid dev_private\n");
  1265. return;
  1266. }
  1267. priv = sde_kms->dev->dev_private;
  1268. for (i = 0; i < priv->num_crtcs; i++)
  1269. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1270. priv->num_crtcs = 0;
  1271. for (i = 0; i < priv->num_planes; i++)
  1272. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1273. priv->num_planes = 0;
  1274. for (i = 0; i < priv->num_connectors; i++)
  1275. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1276. priv->num_connectors = 0;
  1277. for (i = 0; i < priv->num_encoders; i++)
  1278. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1279. priv->num_encoders = 0;
  1280. _sde_kms_release_displays(sde_kms);
  1281. }
  1282. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1283. {
  1284. struct drm_device *dev;
  1285. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1286. struct drm_crtc *crtc;
  1287. struct msm_drm_private *priv;
  1288. struct sde_mdss_cfg *catalog;
  1289. int primary_planes_idx = 0, i, ret;
  1290. int max_crtc_count;
  1291. u32 sspp_id[MAX_PLANES];
  1292. u32 master_plane_id[MAX_PLANES];
  1293. u32 num_virt_planes = 0;
  1294. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1295. SDE_ERROR("invalid sde_kms\n");
  1296. return -EINVAL;
  1297. }
  1298. dev = sde_kms->dev;
  1299. priv = dev->dev_private;
  1300. catalog = sde_kms->catalog;
  1301. ret = sde_core_irq_domain_add(sde_kms);
  1302. if (ret)
  1303. goto fail_irq;
  1304. /*
  1305. * Query for underlying display drivers, and create connectors,
  1306. * bridges and encoders for them.
  1307. */
  1308. if (!_sde_kms_get_displays(sde_kms))
  1309. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1310. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1311. /* Create the planes */
  1312. for (i = 0; i < catalog->sspp_count; i++) {
  1313. bool primary = true;
  1314. if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
  1315. || primary_planes_idx >= max_crtc_count)
  1316. primary = false;
  1317. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1318. (1UL << max_crtc_count) - 1, 0);
  1319. if (IS_ERR(plane)) {
  1320. SDE_ERROR("sde_plane_init failed\n");
  1321. ret = PTR_ERR(plane);
  1322. goto fail;
  1323. }
  1324. priv->planes[priv->num_planes++] = plane;
  1325. if (primary)
  1326. primary_planes[primary_planes_idx++] = plane;
  1327. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1328. sde_is_custom_client()) {
  1329. int priority =
  1330. catalog->sspp[i].sblk->smart_dma_priority;
  1331. sspp_id[priority - 1] = catalog->sspp[i].id;
  1332. master_plane_id[priority - 1] = plane->base.id;
  1333. num_virt_planes++;
  1334. }
  1335. }
  1336. /* Initialize smart DMA virtual planes */
  1337. for (i = 0; i < num_virt_planes; i++) {
  1338. plane = sde_plane_init(dev, sspp_id[i], false,
  1339. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1340. if (IS_ERR(plane)) {
  1341. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1342. ret = PTR_ERR(plane);
  1343. goto fail;
  1344. }
  1345. priv->planes[priv->num_planes++] = plane;
  1346. }
  1347. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1348. /* Create one CRTC per encoder */
  1349. for (i = 0; i < max_crtc_count; i++) {
  1350. crtc = sde_crtc_init(dev, primary_planes[i]);
  1351. if (IS_ERR(crtc)) {
  1352. ret = PTR_ERR(crtc);
  1353. goto fail;
  1354. }
  1355. priv->crtcs[priv->num_crtcs++] = crtc;
  1356. }
  1357. if (sde_is_custom_client()) {
  1358. /* All CRTCs are compatible with all planes */
  1359. for (i = 0; i < priv->num_planes; i++)
  1360. priv->planes[i]->possible_crtcs =
  1361. (1 << priv->num_crtcs) - 1;
  1362. }
  1363. /* All CRTCs are compatible with all encoders */
  1364. for (i = 0; i < priv->num_encoders; i++)
  1365. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1366. return 0;
  1367. fail:
  1368. _sde_kms_drm_obj_destroy(sde_kms);
  1369. fail_irq:
  1370. sde_core_irq_domain_fini(sde_kms);
  1371. return ret;
  1372. }
  1373. /**
  1374. * sde_kms_timeline_status - provides current timeline status
  1375. * This API should be called without mode config lock.
  1376. * @dev: Pointer to drm device
  1377. */
  1378. void sde_kms_timeline_status(struct drm_device *dev)
  1379. {
  1380. struct drm_crtc *crtc;
  1381. struct drm_connector *conn;
  1382. struct drm_connector_list_iter conn_iter;
  1383. if (!dev) {
  1384. SDE_ERROR("invalid drm device node\n");
  1385. return;
  1386. }
  1387. drm_for_each_crtc(crtc, dev)
  1388. sde_crtc_timeline_status(crtc);
  1389. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1390. /*
  1391. *Probably locked from last close dumping status anyway
  1392. */
  1393. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1394. drm_connector_list_iter_begin(dev, &conn_iter);
  1395. drm_for_each_connector_iter(conn, &conn_iter)
  1396. sde_conn_timeline_status(conn);
  1397. drm_connector_list_iter_end(&conn_iter);
  1398. return;
  1399. }
  1400. mutex_lock(&dev->mode_config.mutex);
  1401. drm_connector_list_iter_begin(dev, &conn_iter);
  1402. drm_for_each_connector_iter(conn, &conn_iter)
  1403. sde_conn_timeline_status(conn);
  1404. drm_connector_list_iter_end(&conn_iter);
  1405. mutex_unlock(&dev->mode_config.mutex);
  1406. }
  1407. static int sde_kms_postinit(struct msm_kms *kms)
  1408. {
  1409. struct sde_kms *sde_kms = to_sde_kms(kms);
  1410. struct drm_device *dev;
  1411. struct drm_crtc *crtc;
  1412. int rc;
  1413. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1414. SDE_ERROR("invalid sde_kms\n");
  1415. return -EINVAL;
  1416. }
  1417. dev = sde_kms->dev;
  1418. rc = _sde_debugfs_init(sde_kms);
  1419. if (rc)
  1420. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1421. drm_for_each_crtc(crtc, dev)
  1422. sde_crtc_post_init(dev, crtc);
  1423. return rc;
  1424. }
  1425. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1426. struct drm_encoder *encoder)
  1427. {
  1428. return rate;
  1429. }
  1430. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1431. struct platform_device *pdev)
  1432. {
  1433. struct drm_device *dev;
  1434. struct msm_drm_private *priv;
  1435. int i;
  1436. if (!sde_kms || !pdev)
  1437. return;
  1438. dev = sde_kms->dev;
  1439. if (!dev)
  1440. return;
  1441. priv = dev->dev_private;
  1442. if (!priv)
  1443. return;
  1444. if (sde_kms->genpd_init) {
  1445. sde_kms->genpd_init = false;
  1446. pm_genpd_remove(&sde_kms->genpd);
  1447. of_genpd_del_provider(pdev->dev.of_node);
  1448. }
  1449. if (sde_kms->hw_intr)
  1450. sde_hw_intr_destroy(sde_kms->hw_intr);
  1451. sde_kms->hw_intr = NULL;
  1452. if (sde_kms->power_event)
  1453. sde_power_handle_unregister_event(
  1454. &priv->phandle, sde_kms->power_event);
  1455. _sde_kms_release_displays(sde_kms);
  1456. _sde_kms_unmap_all_splash_regions(sde_kms);
  1457. /* safe to call these more than once during shutdown */
  1458. _sde_debugfs_destroy(sde_kms);
  1459. _sde_kms_mmu_destroy(sde_kms);
  1460. if (sde_kms->catalog) {
  1461. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1462. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1463. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1464. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1465. }
  1466. }
  1467. if (sde_kms->rm_init)
  1468. sde_rm_destroy(&sde_kms->rm);
  1469. sde_kms->rm_init = false;
  1470. if (sde_kms->catalog)
  1471. sde_hw_catalog_deinit(sde_kms->catalog);
  1472. sde_kms->catalog = NULL;
  1473. if (sde_kms->sid)
  1474. msm_iounmap(pdev, sde_kms->sid);
  1475. sde_kms->sid = NULL;
  1476. if (sde_kms->reg_dma)
  1477. msm_iounmap(pdev, sde_kms->reg_dma);
  1478. sde_kms->reg_dma = NULL;
  1479. if (sde_kms->vbif[VBIF_NRT])
  1480. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1481. sde_kms->vbif[VBIF_NRT] = NULL;
  1482. if (sde_kms->vbif[VBIF_RT])
  1483. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1484. sde_kms->vbif[VBIF_RT] = NULL;
  1485. if (sde_kms->mmio)
  1486. msm_iounmap(pdev, sde_kms->mmio);
  1487. sde_kms->mmio = NULL;
  1488. sde_reg_dma_deinit();
  1489. }
  1490. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1491. {
  1492. int i;
  1493. if (!sde_kms)
  1494. return -EINVAL;
  1495. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1496. struct msm_mmu *mmu;
  1497. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1498. if (!aspace)
  1499. continue;
  1500. mmu = sde_kms->aspace[i]->mmu;
  1501. if (secure_only &&
  1502. !aspace->mmu->funcs->is_domain_secure(mmu))
  1503. continue;
  1504. /* cleanup aspace before detaching */
  1505. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1506. SDE_DEBUG("Detaching domain:%d\n", i);
  1507. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1508. ARRAY_SIZE(iommu_ports));
  1509. aspace->domain_attached = false;
  1510. }
  1511. return 0;
  1512. }
  1513. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1514. {
  1515. int i;
  1516. if (!sde_kms)
  1517. return -EINVAL;
  1518. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1519. struct msm_mmu *mmu;
  1520. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1521. if (!aspace)
  1522. continue;
  1523. mmu = sde_kms->aspace[i]->mmu;
  1524. if (secure_only &&
  1525. !aspace->mmu->funcs->is_domain_secure(mmu))
  1526. continue;
  1527. SDE_DEBUG("Attaching domain:%d\n", i);
  1528. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1529. ARRAY_SIZE(iommu_ports));
  1530. aspace->domain_attached = true;
  1531. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1532. }
  1533. return 0;
  1534. }
  1535. static void sde_kms_destroy(struct msm_kms *kms)
  1536. {
  1537. struct sde_kms *sde_kms;
  1538. struct drm_device *dev;
  1539. if (!kms) {
  1540. SDE_ERROR("invalid kms\n");
  1541. return;
  1542. }
  1543. sde_kms = to_sde_kms(kms);
  1544. dev = sde_kms->dev;
  1545. if (!dev || !dev->dev) {
  1546. SDE_ERROR("invalid device\n");
  1547. return;
  1548. }
  1549. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1550. kfree(sde_kms);
  1551. }
  1552. static void _sde_kms_plane_force_remove(struct drm_plane *plane,
  1553. struct drm_atomic_state *state)
  1554. {
  1555. struct drm_plane_state *plane_state;
  1556. int ret = 0;
  1557. plane_state = drm_atomic_get_plane_state(state, plane);
  1558. if (IS_ERR(plane_state)) {
  1559. ret = PTR_ERR(plane_state);
  1560. SDE_ERROR("error %d getting plane %d state\n",
  1561. ret, plane->base.id);
  1562. return;
  1563. }
  1564. plane->old_fb = plane->fb;
  1565. SDE_DEBUG("disabling plane %d\n", plane->base.id);
  1566. ret = __drm_atomic_helper_disable_plane(plane, plane_state);
  1567. if (ret != 0)
  1568. SDE_ERROR("error %d disabling plane %d\n", ret,
  1569. plane->base.id);
  1570. }
  1571. static int _sde_kms_remove_fbs(struct sde_kms *sde_kms, struct drm_file *file,
  1572. struct drm_atomic_state *state)
  1573. {
  1574. struct drm_device *dev = sde_kms->dev;
  1575. struct drm_framebuffer *fb, *tfb;
  1576. struct list_head fbs;
  1577. struct drm_plane *plane;
  1578. int ret = 0;
  1579. u32 plane_mask = 0;
  1580. INIT_LIST_HEAD(&fbs);
  1581. list_for_each_entry_safe(fb, tfb, &file->fbs, filp_head) {
  1582. if (drm_framebuffer_read_refcount(fb) > 1) {
  1583. list_move_tail(&fb->filp_head, &fbs);
  1584. drm_for_each_plane(plane, dev) {
  1585. if (plane->fb == fb) {
  1586. plane_mask |=
  1587. 1 << drm_plane_index(plane);
  1588. _sde_kms_plane_force_remove(
  1589. plane, state);
  1590. }
  1591. }
  1592. } else {
  1593. list_del_init(&fb->filp_head);
  1594. drm_framebuffer_put(fb);
  1595. }
  1596. }
  1597. if (list_empty(&fbs)) {
  1598. SDE_DEBUG("skip commit as no fb(s)\n");
  1599. drm_atomic_state_put(state);
  1600. return 0;
  1601. }
  1602. SDE_DEBUG("committing after removing all the pipes\n");
  1603. ret = drm_atomic_commit(state);
  1604. if (ret) {
  1605. /*
  1606. * move the fbs back to original list, so it would be
  1607. * handled during drm_release
  1608. */
  1609. list_for_each_entry_safe(fb, tfb, &fbs, filp_head)
  1610. list_move_tail(&fb->filp_head, &file->fbs);
  1611. SDE_ERROR("atomic commit failed in preclose, ret:%d\n", ret);
  1612. goto end;
  1613. }
  1614. while (!list_empty(&fbs)) {
  1615. fb = list_first_entry(&fbs, typeof(*fb), filp_head);
  1616. list_del_init(&fb->filp_head);
  1617. drm_framebuffer_put(fb);
  1618. }
  1619. end:
  1620. return ret;
  1621. }
  1622. static void sde_kms_preclose(struct msm_kms *kms, struct drm_file *file)
  1623. {
  1624. struct sde_kms *sde_kms = to_sde_kms(kms);
  1625. struct drm_device *dev = sde_kms->dev;
  1626. struct msm_drm_private *priv = dev->dev_private;
  1627. unsigned int i;
  1628. struct drm_atomic_state *state = NULL;
  1629. struct drm_modeset_acquire_ctx ctx;
  1630. int ret = 0;
  1631. /* cancel pending flip event */
  1632. for (i = 0; i < priv->num_crtcs; i++)
  1633. sde_crtc_complete_flip(priv->crtcs[i], file);
  1634. drm_modeset_acquire_init(&ctx, 0);
  1635. retry:
  1636. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  1637. if (ret == -EDEADLK) {
  1638. drm_modeset_backoff(&ctx);
  1639. goto retry;
  1640. } else if (WARN_ON(ret)) {
  1641. goto end;
  1642. }
  1643. state = drm_atomic_state_alloc(dev);
  1644. if (!state) {
  1645. ret = -ENOMEM;
  1646. goto end;
  1647. }
  1648. state->acquire_ctx = &ctx;
  1649. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  1650. ret = _sde_kms_remove_fbs(sde_kms, file, state);
  1651. if (ret != -EDEADLK)
  1652. break;
  1653. drm_atomic_state_clear(state);
  1654. drm_modeset_backoff(&ctx);
  1655. }
  1656. end:
  1657. if (state)
  1658. drm_atomic_state_put(state);
  1659. SDE_DEBUG("sde preclose done, ret:%d\n", ret);
  1660. drm_modeset_drop_locks(&ctx);
  1661. drm_modeset_acquire_fini(&ctx);
  1662. }
  1663. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  1664. struct drm_atomic_state *state)
  1665. {
  1666. struct drm_device *dev = sde_kms->dev;
  1667. struct drm_plane *plane;
  1668. struct drm_plane_state *plane_state;
  1669. struct drm_crtc *crtc;
  1670. struct drm_crtc_state *crtc_state;
  1671. struct drm_connector *conn;
  1672. struct drm_connector_state *conn_state;
  1673. struct drm_connector_list_iter conn_iter;
  1674. int ret = 0;
  1675. drm_for_each_plane(plane, dev) {
  1676. plane_state = drm_atomic_get_plane_state(state, plane);
  1677. if (IS_ERR(plane_state)) {
  1678. ret = PTR_ERR(plane_state);
  1679. SDE_ERROR("error %d getting plane %d state\n",
  1680. ret, DRMID(plane));
  1681. return ret;
  1682. }
  1683. ret = sde_plane_helper_reset_custom_properties(plane,
  1684. plane_state);
  1685. if (ret) {
  1686. SDE_ERROR("error %d resetting plane props %d\n",
  1687. ret, DRMID(plane));
  1688. return ret;
  1689. }
  1690. }
  1691. drm_for_each_crtc(crtc, dev) {
  1692. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  1693. if (IS_ERR(crtc_state)) {
  1694. ret = PTR_ERR(crtc_state);
  1695. SDE_ERROR("error %d getting crtc %d state\n",
  1696. ret, DRMID(crtc));
  1697. return ret;
  1698. }
  1699. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  1700. if (ret) {
  1701. SDE_ERROR("error %d resetting crtc props %d\n",
  1702. ret, DRMID(crtc));
  1703. return ret;
  1704. }
  1705. }
  1706. drm_connector_list_iter_begin(dev, &conn_iter);
  1707. drm_for_each_connector_iter(conn, &conn_iter) {
  1708. conn_state = drm_atomic_get_connector_state(state, conn);
  1709. if (IS_ERR(conn_state)) {
  1710. ret = PTR_ERR(conn_state);
  1711. SDE_ERROR("error %d getting connector %d state\n",
  1712. ret, DRMID(conn));
  1713. return ret;
  1714. }
  1715. ret = sde_connector_helper_reset_custom_properties(conn,
  1716. conn_state);
  1717. if (ret) {
  1718. SDE_ERROR("error %d resetting connector props %d\n",
  1719. ret, DRMID(conn));
  1720. return ret;
  1721. }
  1722. }
  1723. drm_connector_list_iter_end(&conn_iter);
  1724. return ret;
  1725. }
  1726. static void sde_kms_lastclose(struct msm_kms *kms,
  1727. struct drm_modeset_acquire_ctx *ctx)
  1728. {
  1729. struct sde_kms *sde_kms;
  1730. struct drm_device *dev;
  1731. struct drm_atomic_state *state;
  1732. int ret, i;
  1733. if (!kms) {
  1734. SDE_ERROR("invalid argument\n");
  1735. return;
  1736. }
  1737. sde_kms = to_sde_kms(kms);
  1738. dev = sde_kms->dev;
  1739. state = drm_atomic_state_alloc(dev);
  1740. if (!state)
  1741. return;
  1742. state->acquire_ctx = ctx;
  1743. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  1744. /* add reset of custom properties to the state */
  1745. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  1746. if (ret)
  1747. break;
  1748. ret = drm_atomic_commit(state);
  1749. if (ret != -EDEADLK)
  1750. break;
  1751. drm_atomic_state_clear(state);
  1752. drm_modeset_backoff(ctx);
  1753. SDE_DEBUG("deadlock backoff on attempt %d\n", i);
  1754. }
  1755. if (ret)
  1756. SDE_ERROR("failed to run last close: %d\n", ret);
  1757. drm_atomic_state_put(state);
  1758. }
  1759. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  1760. struct drm_atomic_state *state)
  1761. {
  1762. struct sde_kms *sde_kms;
  1763. struct drm_device *dev;
  1764. struct drm_crtc *crtc;
  1765. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  1766. struct drm_crtc_state *crtc_state;
  1767. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  1768. bool sec_session = false, global_sec_session = false;
  1769. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  1770. int i;
  1771. if (!kms || !state) {
  1772. return -EINVAL;
  1773. SDE_ERROR("invalid arguments\n");
  1774. }
  1775. sde_kms = to_sde_kms(kms);
  1776. dev = sde_kms->dev;
  1777. /* iterate state object for active secure/non-secure crtc */
  1778. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  1779. if (!crtc_state->active)
  1780. continue;
  1781. active_crtc_cnt++;
  1782. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  1783. &fb_sec, &fb_sec_dir);
  1784. if (fb_sec_dir)
  1785. sec_session = true;
  1786. cur_crtc = crtc;
  1787. }
  1788. /* iterate global list for active and secure/non-secure crtc */
  1789. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1790. if (!crtc->state->active)
  1791. continue;
  1792. global_active_crtc_cnt++;
  1793. /* update only when crtc is not the same as current crtc */
  1794. if (crtc != cur_crtc) {
  1795. fb_ns = fb_sec = fb_sec_dir = 0;
  1796. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  1797. &fb_sec, &fb_sec_dir);
  1798. if (fb_sec_dir)
  1799. global_sec_session = true;
  1800. global_crtc = crtc;
  1801. }
  1802. }
  1803. if (!global_sec_session && !sec_session)
  1804. return 0;
  1805. /*
  1806. * - fail crtc commit, if secure-camera/secure-ui session is
  1807. * in-progress in any other display
  1808. * - fail secure-camera/secure-ui crtc commit, if any other display
  1809. * session is in-progress
  1810. */
  1811. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  1812. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  1813. SDE_ERROR(
  1814. "crtc%d secure check failed global_active:%d active:%d\n",
  1815. cur_crtc ? cur_crtc->base.id : -1,
  1816. global_active_crtc_cnt, active_crtc_cnt);
  1817. return -EPERM;
  1818. /*
  1819. * As only one crtc is allowed during secure session, the crtc
  1820. * in this commit should match with the global crtc
  1821. */
  1822. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  1823. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  1824. cur_crtc->base.id, sec_session,
  1825. global_crtc->base.id, global_sec_session);
  1826. return -EPERM;
  1827. }
  1828. return 0;
  1829. }
  1830. static int sde_kms_atomic_check(struct msm_kms *kms,
  1831. struct drm_atomic_state *state)
  1832. {
  1833. struct sde_kms *sde_kms;
  1834. struct drm_device *dev;
  1835. int ret;
  1836. if (!kms || !state)
  1837. return -EINVAL;
  1838. sde_kms = to_sde_kms(kms);
  1839. dev = sde_kms->dev;
  1840. SDE_ATRACE_BEGIN("atomic_check");
  1841. if (sde_kms_is_suspend_blocked(dev)) {
  1842. SDE_DEBUG("suspended, skip atomic_check\n");
  1843. ret = -EBUSY;
  1844. goto end;
  1845. }
  1846. ret = drm_atomic_helper_check(dev, state);
  1847. if (ret)
  1848. goto end;
  1849. /*
  1850. * Check if any secure transition(moving CRTC between secure and
  1851. * non-secure state and vice-versa) is allowed or not. when moving
  1852. * to secure state, planes with fb_mode set to dir_translated only can
  1853. * be staged on the CRTC, and only one CRTC can be active during
  1854. * Secure state
  1855. */
  1856. ret = sde_kms_check_secure_transition(kms, state);
  1857. end:
  1858. SDE_ATRACE_END("atomic_check");
  1859. return ret;
  1860. }
  1861. static struct msm_gem_address_space*
  1862. _sde_kms_get_address_space(struct msm_kms *kms,
  1863. unsigned int domain)
  1864. {
  1865. struct sde_kms *sde_kms;
  1866. if (!kms) {
  1867. SDE_ERROR("invalid kms\n");
  1868. return NULL;
  1869. }
  1870. sde_kms = to_sde_kms(kms);
  1871. if (!sde_kms) {
  1872. SDE_ERROR("invalid sde_kms\n");
  1873. return NULL;
  1874. }
  1875. if (domain >= MSM_SMMU_DOMAIN_MAX)
  1876. return NULL;
  1877. return (sde_kms->aspace[domain] &&
  1878. sde_kms->aspace[domain]->domain_attached) ?
  1879. sde_kms->aspace[domain] : NULL;
  1880. }
  1881. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  1882. unsigned int domain)
  1883. {
  1884. struct msm_gem_address_space *aspace =
  1885. _sde_kms_get_address_space(kms, domain);
  1886. return (aspace && aspace->domain_attached) ?
  1887. msm_gem_get_aspace_device(aspace) : NULL;
  1888. }
  1889. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  1890. {
  1891. struct drm_device *dev = NULL;
  1892. struct sde_kms *sde_kms = NULL;
  1893. struct drm_connector *connector = NULL;
  1894. struct drm_connector_list_iter conn_iter;
  1895. struct sde_connector *sde_conn = NULL;
  1896. if (!kms) {
  1897. SDE_ERROR("invalid kms\n");
  1898. return;
  1899. }
  1900. sde_kms = to_sde_kms(kms);
  1901. dev = sde_kms->dev;
  1902. if (!dev) {
  1903. SDE_ERROR("invalid device\n");
  1904. return;
  1905. }
  1906. if (!dev->mode_config.poll_enabled)
  1907. return;
  1908. mutex_lock(&dev->mode_config.mutex);
  1909. drm_connector_list_iter_begin(dev, &conn_iter);
  1910. drm_for_each_connector_iter(connector, &conn_iter) {
  1911. /* Only handle HPD capable connectors. */
  1912. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  1913. continue;
  1914. sde_conn = to_sde_connector(connector);
  1915. if (sde_conn->ops.post_open)
  1916. sde_conn->ops.post_open(&sde_conn->base,
  1917. sde_conn->display);
  1918. }
  1919. drm_connector_list_iter_end(&conn_iter);
  1920. mutex_unlock(&dev->mode_config.mutex);
  1921. }
  1922. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  1923. struct sde_splash_display *splash_display,
  1924. struct drm_crtc *crtc)
  1925. {
  1926. struct msm_drm_private *priv;
  1927. struct drm_plane *plane;
  1928. struct sde_splash_mem *splash;
  1929. enum sde_sspp plane_id;
  1930. bool is_virtual;
  1931. int i, j;
  1932. if (!sde_kms || !splash_display || !crtc) {
  1933. SDE_ERROR("invalid input args\n");
  1934. return -EINVAL;
  1935. }
  1936. priv = sde_kms->dev->dev_private;
  1937. for (i = 0; i < priv->num_planes; i++) {
  1938. plane = priv->planes[i];
  1939. plane_id = sde_plane_pipe(plane);
  1940. is_virtual = is_sde_plane_virtual(plane);
  1941. splash = splash_display->splash;
  1942. for (j = 0; j < splash_display->pipe_cnt; j++) {
  1943. if ((plane_id != splash_display->pipes[j].sspp) ||
  1944. (splash_display->pipes[j].is_virtual
  1945. != is_virtual))
  1946. continue;
  1947. if (splash && sde_plane_validate_src_addr(plane,
  1948. splash->splash_buf_base,
  1949. splash->splash_buf_size)) {
  1950. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  1951. plane_id, crtc->base.id);
  1952. }
  1953. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  1954. crtc->base.id, plane_id, is_virtual);
  1955. }
  1956. }
  1957. return 0;
  1958. }
  1959. static int sde_kms_cont_splash_config(struct msm_kms *kms)
  1960. {
  1961. void *display;
  1962. struct dsi_display *dsi_display;
  1963. struct msm_display_info info;
  1964. struct drm_encoder *encoder = NULL;
  1965. struct drm_crtc *crtc = NULL;
  1966. int i, rc = 0;
  1967. struct drm_display_mode *drm_mode = NULL;
  1968. struct drm_device *dev;
  1969. struct msm_drm_private *priv;
  1970. struct sde_kms *sde_kms;
  1971. struct drm_connector_list_iter conn_iter;
  1972. struct drm_connector *connector = NULL;
  1973. struct sde_connector *sde_conn = NULL;
  1974. struct sde_splash_display *splash_display;
  1975. if (!kms) {
  1976. SDE_ERROR("invalid kms\n");
  1977. return -EINVAL;
  1978. }
  1979. sde_kms = to_sde_kms(kms);
  1980. dev = sde_kms->dev;
  1981. if (!dev) {
  1982. SDE_ERROR("invalid device\n");
  1983. return -EINVAL;
  1984. }
  1985. if (!sde_kms->splash_data.num_splash_regions ||
  1986. !sde_kms->splash_data.num_splash_displays) {
  1987. DRM_INFO("cont_splash feature not enabled\n");
  1988. return rc;
  1989. }
  1990. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  1991. sde_kms->splash_data.num_splash_displays,
  1992. sde_kms->dsi_display_count);
  1993. /* dsi */
  1994. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  1995. display = sde_kms->dsi_displays[i];
  1996. dsi_display = (struct dsi_display *)display;
  1997. splash_display = &sde_kms->splash_data.splash_display[i];
  1998. if (!splash_display->cont_splash_enabled) {
  1999. SDE_DEBUG("display->name = %s splash not enabled\n",
  2000. dsi_display->name);
  2001. continue;
  2002. }
  2003. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  2004. if (dsi_display->bridge->base.encoder) {
  2005. encoder = dsi_display->bridge->base.encoder;
  2006. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2007. }
  2008. memset(&info, 0x0, sizeof(info));
  2009. rc = dsi_display_get_info(NULL, &info, display);
  2010. if (rc) {
  2011. SDE_ERROR("dsi get_info %d failed\n", i);
  2012. encoder = NULL;
  2013. continue;
  2014. }
  2015. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  2016. ((info.is_connected) ? "true" : "false"),
  2017. info.display_type);
  2018. if (!encoder) {
  2019. SDE_ERROR("encoder not initialized\n");
  2020. return -EINVAL;
  2021. }
  2022. priv = sde_kms->dev->dev_private;
  2023. encoder->crtc = priv->crtcs[i];
  2024. crtc = encoder->crtc;
  2025. splash_display->encoder = encoder;
  2026. SDE_DEBUG("for dsi-display:%d crtc id = %d enc id =%d\n",
  2027. i, crtc->base.id, encoder->base.id);
  2028. mutex_lock(&dev->mode_config.mutex);
  2029. drm_connector_list_iter_begin(dev, &conn_iter);
  2030. drm_for_each_connector_iter(connector, &conn_iter) {
  2031. /**
  2032. * SDE_KMS doesn't attach more than one encoder to
  2033. * a DSI connector. So it is safe to check only with
  2034. * the first encoder entry. Revisit this logic if we
  2035. * ever have to support continuous splash for
  2036. * external displays in MST configuration.
  2037. */
  2038. if (connector->encoder_ids[0] == encoder->base.id)
  2039. break;
  2040. }
  2041. drm_connector_list_iter_end(&conn_iter);
  2042. if (!connector) {
  2043. SDE_ERROR("connector not initialized\n");
  2044. mutex_unlock(&dev->mode_config.mutex);
  2045. return -EINVAL;
  2046. }
  2047. if (connector->funcs->fill_modes) {
  2048. connector->funcs->fill_modes(connector,
  2049. dev->mode_config.max_width,
  2050. dev->mode_config.max_height);
  2051. } else {
  2052. SDE_ERROR("fill_modes api not defined\n");
  2053. mutex_unlock(&dev->mode_config.mutex);
  2054. return -EINVAL;
  2055. }
  2056. mutex_unlock(&dev->mode_config.mutex);
  2057. crtc->state->encoder_mask = (1 << drm_encoder_index(encoder));
  2058. /* currently consider modes[0] as the preferred mode */
  2059. drm_mode = list_first_entry(&connector->modes,
  2060. struct drm_display_mode, head);
  2061. SDE_DEBUG("drm_mode->name = %s, type=0x%x, flags=0x%x\n",
  2062. drm_mode->name, drm_mode->type,
  2063. drm_mode->flags);
  2064. /* Update CRTC drm structure */
  2065. crtc->state->active = true;
  2066. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  2067. if (rc) {
  2068. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  2069. return rc;
  2070. }
  2071. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  2072. drm_mode_copy(&crtc->mode, drm_mode);
  2073. /* Update encoder structure */
  2074. sde_encoder_update_caps_for_cont_splash(encoder,
  2075. splash_display, true);
  2076. sde_crtc_update_cont_splash_settings(crtc);
  2077. sde_conn = to_sde_connector(connector);
  2078. if (sde_conn && sde_conn->ops.cont_splash_config)
  2079. sde_conn->ops.cont_splash_config(sde_conn->display);
  2080. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  2081. splash_display, crtc);
  2082. if (rc) {
  2083. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  2084. return rc;
  2085. }
  2086. }
  2087. return rc;
  2088. }
  2089. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  2090. {
  2091. struct sde_kms *sde_kms;
  2092. if (!kms) {
  2093. SDE_ERROR("invalid kms\n");
  2094. return false;
  2095. }
  2096. sde_kms = to_sde_kms(kms);
  2097. return sde_kms->splash_data.num_splash_displays;
  2098. }
  2099. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  2100. const struct drm_display_mode *mode,
  2101. const struct msm_resource_caps_info *res, u32 *num_lm)
  2102. {
  2103. struct sde_kms *sde_kms;
  2104. s64 mode_clock_hz = 0;
  2105. s64 max_mdp_clock_hz = 0;
  2106. s64 mdp_fudge_factor = 0;
  2107. s64 temp = 0;
  2108. s64 htotal_fp = 0;
  2109. s64 vtotal_fp = 0;
  2110. s64 vrefresh_fp = 0;
  2111. if (!num_lm) {
  2112. SDE_ERROR("invalid num_lm pointer\n");
  2113. return -EINVAL;
  2114. }
  2115. *num_lm = 1;
  2116. if (!kms || !mode || !res) {
  2117. SDE_ERROR("invalid input args\n");
  2118. return -EINVAL;
  2119. }
  2120. sde_kms = to_sde_kms(kms);
  2121. max_mdp_clock_hz = drm_fixp_from_fraction(
  2122. sde_kms->perf.max_core_clk_rate, 1);
  2123. mdp_fudge_factor = drm_fixp_from_fraction(105, 100); /* 1.05 */
  2124. htotal_fp = drm_fixp_from_fraction(mode->htotal, 1);
  2125. vtotal_fp = drm_fixp_from_fraction(mode->vtotal, 1);
  2126. vrefresh_fp = drm_fixp_from_fraction(mode->vrefresh, 1);
  2127. temp = drm_fixp_mul(htotal_fp, vtotal_fp);
  2128. temp = drm_fixp_mul(temp, vrefresh_fp);
  2129. mode_clock_hz = drm_fixp_mul(temp, mdp_fudge_factor);
  2130. if (mode_clock_hz > max_mdp_clock_hz ||
  2131. mode->hdisplay > res->max_mixer_width)
  2132. *num_lm = 2;
  2133. SDE_DEBUG("[%s] h=%d, v=%d, fps=%d, max_mdp_clk_hz=%llu, num_lm=%d\n",
  2134. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2135. sde_kms->perf.max_core_clk_rate, *num_lm);
  2136. return 0;
  2137. }
  2138. static void _sde_kms_null_commit(struct drm_device *dev,
  2139. struct drm_encoder *enc)
  2140. {
  2141. struct drm_modeset_acquire_ctx ctx;
  2142. struct drm_connector *conn = NULL;
  2143. struct drm_connector *tmp_conn = NULL;
  2144. struct drm_connector_list_iter conn_iter;
  2145. struct drm_atomic_state *state = NULL;
  2146. struct drm_crtc_state *crtc_state = NULL;
  2147. struct drm_connector_state *conn_state = NULL;
  2148. int retry_cnt = 0;
  2149. int ret = 0;
  2150. drm_modeset_acquire_init(&ctx, 0);
  2151. retry:
  2152. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2153. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  2154. drm_modeset_backoff(&ctx);
  2155. retry_cnt++;
  2156. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  2157. goto retry;
  2158. } else if (WARN_ON(ret)) {
  2159. goto end;
  2160. }
  2161. state = drm_atomic_state_alloc(dev);
  2162. if (!state) {
  2163. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  2164. goto end;
  2165. }
  2166. state->acquire_ctx = &ctx;
  2167. drm_connector_list_iter_begin(dev, &conn_iter);
  2168. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2169. if (enc == tmp_conn->state->best_encoder) {
  2170. conn = tmp_conn;
  2171. break;
  2172. }
  2173. }
  2174. drm_connector_list_iter_end(&conn_iter);
  2175. if (!conn) {
  2176. SDE_ERROR("error in finding conn for enc:%d\n", DRMID(enc));
  2177. goto end;
  2178. }
  2179. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2180. conn_state = drm_atomic_get_connector_state(state, conn);
  2181. if (IS_ERR(conn_state)) {
  2182. SDE_ERROR("error %d getting connector %d state\n",
  2183. ret, DRMID(conn));
  2184. goto end;
  2185. }
  2186. crtc_state->active = true;
  2187. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2188. if (ret)
  2189. SDE_ERROR("error %d setting the crtc\n", ret);
  2190. ret = drm_atomic_commit(state);
  2191. if (ret)
  2192. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  2193. end:
  2194. if (state)
  2195. drm_atomic_state_put(state);
  2196. drm_modeset_drop_locks(&ctx);
  2197. drm_modeset_acquire_fini(&ctx);
  2198. }
  2199. static void _sde_kms_pm_suspend_idle_helper(struct sde_kms *sde_kms,
  2200. struct device *dev)
  2201. {
  2202. int i, ret;
  2203. struct drm_device *ddev = dev_get_drvdata(dev);
  2204. struct drm_connector *conn;
  2205. struct drm_connector_list_iter conn_iter;
  2206. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  2207. drm_connector_list_iter_begin(ddev, &conn_iter);
  2208. drm_for_each_connector_iter(conn, &conn_iter) {
  2209. uint64_t lp;
  2210. lp = sde_connector_get_lp(conn);
  2211. if (lp != SDE_MODE_DPMS_LP2)
  2212. continue;
  2213. ret = sde_encoder_wait_for_event(conn->encoder,
  2214. MSM_ENC_TX_COMPLETE);
  2215. if (ret && ret != -EWOULDBLOCK)
  2216. SDE_ERROR(
  2217. "[conn: %d] wait for commit done returned %d\n",
  2218. conn->base.id, ret);
  2219. else if (!ret)
  2220. sde_encoder_idle_request(conn->encoder);
  2221. }
  2222. drm_connector_list_iter_end(&conn_iter);
  2223. for (i = 0; i < priv->num_crtcs; i++) {
  2224. if (priv->disp_thread[i].thread)
  2225. kthread_flush_worker(
  2226. &priv->disp_thread[i].worker);
  2227. if (priv->event_thread[i].thread)
  2228. kthread_flush_worker(
  2229. &priv->event_thread[i].worker);
  2230. }
  2231. kthread_flush_worker(&priv->pp_event_worker);
  2232. }
  2233. static int sde_kms_pm_suspend(struct device *dev)
  2234. {
  2235. struct drm_device *ddev;
  2236. struct drm_modeset_acquire_ctx ctx;
  2237. struct drm_connector *conn;
  2238. struct drm_encoder *enc;
  2239. struct drm_connector_list_iter conn_iter;
  2240. struct drm_atomic_state *state = NULL;
  2241. struct sde_kms *sde_kms;
  2242. int ret = 0, num_crtcs = 0;
  2243. if (!dev)
  2244. return -EINVAL;
  2245. ddev = dev_get_drvdata(dev);
  2246. if (!ddev || !ddev_to_msm_kms(ddev))
  2247. return -EINVAL;
  2248. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2249. SDE_EVT32(0);
  2250. /* disable hot-plug polling */
  2251. drm_kms_helper_poll_disable(ddev);
  2252. /* if a display stuck in CS trigger a null commit to complete handoff */
  2253. drm_for_each_encoder(enc, ddev) {
  2254. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  2255. _sde_kms_null_commit(ddev, enc);
  2256. }
  2257. /* acquire modeset lock(s) */
  2258. drm_modeset_acquire_init(&ctx, 0);
  2259. retry:
  2260. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2261. if (ret)
  2262. goto unlock;
  2263. /* save current state for resume */
  2264. if (sde_kms->suspend_state)
  2265. drm_atomic_state_put(sde_kms->suspend_state);
  2266. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  2267. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  2268. ret = PTR_ERR(sde_kms->suspend_state);
  2269. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  2270. sde_kms->suspend_state = NULL;
  2271. goto unlock;
  2272. }
  2273. /* create atomic state to disable all CRTCs */
  2274. state = drm_atomic_state_alloc(ddev);
  2275. if (!state) {
  2276. ret = -ENOMEM;
  2277. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  2278. goto unlock;
  2279. }
  2280. state->acquire_ctx = &ctx;
  2281. drm_connector_list_iter_begin(ddev, &conn_iter);
  2282. drm_for_each_connector_iter(conn, &conn_iter) {
  2283. struct drm_crtc_state *crtc_state;
  2284. uint64_t lp;
  2285. if (!conn->state || !conn->state->crtc ||
  2286. conn->dpms != DRM_MODE_DPMS_ON)
  2287. continue;
  2288. lp = sde_connector_get_lp(conn);
  2289. if (lp == SDE_MODE_DPMS_LP1) {
  2290. /* transition LP1->LP2 on pm suspend */
  2291. ret = sde_connector_set_property_for_commit(conn, state,
  2292. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  2293. if (ret) {
  2294. DRM_ERROR("failed to set lp2 for conn %d\n",
  2295. conn->base.id);
  2296. drm_connector_list_iter_end(&conn_iter);
  2297. goto unlock;
  2298. }
  2299. }
  2300. if (lp != SDE_MODE_DPMS_LP2) {
  2301. /* force CRTC to be inactive */
  2302. crtc_state = drm_atomic_get_crtc_state(state,
  2303. conn->state->crtc);
  2304. if (IS_ERR_OR_NULL(crtc_state)) {
  2305. DRM_ERROR("failed to get crtc %d state\n",
  2306. conn->state->crtc->base.id);
  2307. drm_connector_list_iter_end(&conn_iter);
  2308. goto unlock;
  2309. }
  2310. if (lp != SDE_MODE_DPMS_LP1)
  2311. crtc_state->active = false;
  2312. ++num_crtcs;
  2313. }
  2314. }
  2315. drm_connector_list_iter_end(&conn_iter);
  2316. /* check for nothing to do */
  2317. if (num_crtcs == 0) {
  2318. DRM_DEBUG("all crtcs are already in the off state\n");
  2319. sde_kms->suspend_block = true;
  2320. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2321. goto unlock;
  2322. }
  2323. /* commit the "disable all" state */
  2324. ret = drm_atomic_commit(state);
  2325. if (ret < 0) {
  2326. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  2327. goto unlock;
  2328. }
  2329. sde_kms->suspend_block = true;
  2330. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2331. unlock:
  2332. if (state) {
  2333. drm_atomic_state_put(state);
  2334. state = NULL;
  2335. }
  2336. if (ret == -EDEADLK) {
  2337. drm_modeset_backoff(&ctx);
  2338. goto retry;
  2339. }
  2340. drm_modeset_drop_locks(&ctx);
  2341. drm_modeset_acquire_fini(&ctx);
  2342. /*
  2343. * pm runtime driver avoids multiple runtime_suspend API call by
  2344. * checking runtime_status. However, this call helps when there is a
  2345. * race condition between pm_suspend call and doze_suspend/power_off
  2346. * commit. It removes the extra vote from suspend and adds it back
  2347. * later to allow power collapse during pm_suspend call
  2348. */
  2349. pm_runtime_put_sync(dev);
  2350. pm_runtime_get_noresume(dev);
  2351. return ret;
  2352. }
  2353. static int sde_kms_pm_resume(struct device *dev)
  2354. {
  2355. struct drm_device *ddev;
  2356. struct sde_kms *sde_kms;
  2357. struct drm_modeset_acquire_ctx ctx;
  2358. int ret, i;
  2359. if (!dev)
  2360. return -EINVAL;
  2361. ddev = dev_get_drvdata(dev);
  2362. if (!ddev || !ddev_to_msm_kms(ddev))
  2363. return -EINVAL;
  2364. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2365. SDE_EVT32(sde_kms->suspend_state != NULL);
  2366. drm_mode_config_reset(ddev);
  2367. drm_modeset_acquire_init(&ctx, 0);
  2368. retry:
  2369. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2370. if (ret == -EDEADLK) {
  2371. drm_modeset_backoff(&ctx);
  2372. goto retry;
  2373. } else if (WARN_ON(ret)) {
  2374. goto end;
  2375. }
  2376. sde_kms->suspend_block = false;
  2377. if (sde_kms->suspend_state) {
  2378. sde_kms->suspend_state->acquire_ctx = &ctx;
  2379. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  2380. ret = drm_atomic_helper_commit_duplicated_state(
  2381. sde_kms->suspend_state, &ctx);
  2382. if (ret != -EDEADLK)
  2383. break;
  2384. drm_modeset_backoff(&ctx);
  2385. }
  2386. if (ret < 0)
  2387. DRM_ERROR("failed to restore state, %d\n", ret);
  2388. drm_atomic_state_put(sde_kms->suspend_state);
  2389. sde_kms->suspend_state = NULL;
  2390. }
  2391. end:
  2392. drm_modeset_drop_locks(&ctx);
  2393. drm_modeset_acquire_fini(&ctx);
  2394. /* enable hot-plug polling */
  2395. drm_kms_helper_poll_enable(ddev);
  2396. return 0;
  2397. }
  2398. static const struct msm_kms_funcs kms_funcs = {
  2399. .hw_init = sde_kms_hw_init,
  2400. .postinit = sde_kms_postinit,
  2401. .irq_preinstall = sde_irq_preinstall,
  2402. .irq_postinstall = sde_irq_postinstall,
  2403. .irq_uninstall = sde_irq_uninstall,
  2404. .irq = sde_irq,
  2405. .preclose = sde_kms_preclose,
  2406. .lastclose = sde_kms_lastclose,
  2407. .prepare_fence = sde_kms_prepare_fence,
  2408. .prepare_commit = sde_kms_prepare_commit,
  2409. .commit = sde_kms_commit,
  2410. .complete_commit = sde_kms_complete_commit,
  2411. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  2412. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  2413. .enable_vblank = sde_kms_enable_vblank,
  2414. .disable_vblank = sde_kms_disable_vblank,
  2415. .check_modified_format = sde_format_check_modified_format,
  2416. .atomic_check = sde_kms_atomic_check,
  2417. .get_format = sde_get_msm_format,
  2418. .round_pixclk = sde_kms_round_pixclk,
  2419. .pm_suspend = sde_kms_pm_suspend,
  2420. .pm_resume = sde_kms_pm_resume,
  2421. .destroy = sde_kms_destroy,
  2422. .cont_splash_config = sde_kms_cont_splash_config,
  2423. .register_events = _sde_kms_register_events,
  2424. .get_address_space = _sde_kms_get_address_space,
  2425. .get_address_space_device = _sde_kms_get_address_space_device,
  2426. .postopen = _sde_kms_post_open,
  2427. .check_for_splash = sde_kms_check_for_splash,
  2428. .get_mixer_count = sde_kms_get_mixer_count,
  2429. };
  2430. /* the caller api needs to turn on clock before calling it */
  2431. static inline void _sde_kms_core_hw_rev_init(struct sde_kms *sde_kms)
  2432. {
  2433. sde_kms->core_rev = readl_relaxed(sde_kms->mmio + 0x0);
  2434. }
  2435. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  2436. {
  2437. int i;
  2438. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  2439. if (!sde_kms->aspace[i])
  2440. continue;
  2441. msm_gem_address_space_put(sde_kms->aspace[i]);
  2442. sde_kms->aspace[i] = NULL;
  2443. }
  2444. return 0;
  2445. }
  2446. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  2447. {
  2448. struct msm_mmu *mmu;
  2449. int i, ret;
  2450. int early_map = 0;
  2451. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev)
  2452. return -EINVAL;
  2453. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  2454. struct msm_gem_address_space *aspace;
  2455. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  2456. if (IS_ERR(mmu)) {
  2457. ret = PTR_ERR(mmu);
  2458. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  2459. i, ret);
  2460. continue;
  2461. }
  2462. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  2463. mmu, "sde");
  2464. if (IS_ERR(aspace)) {
  2465. ret = PTR_ERR(aspace);
  2466. goto fail;
  2467. }
  2468. sde_kms->aspace[i] = aspace;
  2469. aspace->domain_attached = true;
  2470. /* Mapping splash memory block */
  2471. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  2472. sde_kms->splash_data.num_splash_regions) {
  2473. ret = _sde_kms_map_all_splash_regions(sde_kms);
  2474. if (ret) {
  2475. SDE_ERROR("failed to map ret:%d\n", ret);
  2476. goto fail;
  2477. }
  2478. }
  2479. /*
  2480. * disable early-map which would have been enabled during
  2481. * bootup by smmu through the device-tree hint for cont-spash
  2482. */
  2483. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  2484. &early_map);
  2485. if (ret) {
  2486. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  2487. ret, early_map);
  2488. goto early_map_fail;
  2489. }
  2490. }
  2491. return 0;
  2492. early_map_fail:
  2493. _sde_kms_unmap_all_splash_regions(sde_kms);
  2494. fail:
  2495. mmu->funcs->destroy(mmu);
  2496. _sde_kms_mmu_destroy(sde_kms);
  2497. return ret;
  2498. }
  2499. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  2500. {
  2501. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  2502. return;
  2503. if (sde_kms->hw_mdp->ops.reset_ubwc)
  2504. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  2505. sde_kms->catalog);
  2506. sde_hw_sid_rotator_set(sde_kms->hw_sid);
  2507. }
  2508. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  2509. {
  2510. struct sde_vbif_set_qos_params qos_params;
  2511. struct sde_mdss_cfg *catalog;
  2512. if (!sde_kms->catalog)
  2513. return;
  2514. catalog = sde_kms->catalog;
  2515. memset(&qos_params, 0, sizeof(qos_params));
  2516. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  2517. qos_params.xin_id = catalog->dma_cfg.xin_id;
  2518. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  2519. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  2520. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  2521. }
  2522. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  2523. {
  2524. struct sde_kms *sde_kms = usr;
  2525. struct msm_kms *msm_kms;
  2526. msm_kms = &sde_kms->base;
  2527. if (!sde_kms)
  2528. return;
  2529. SDE_DEBUG("event_type:%d\n", event_type);
  2530. SDE_EVT32_VERBOSE(event_type);
  2531. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  2532. sde_irq_update(msm_kms, true);
  2533. sde_vbif_init_memtypes(sde_kms);
  2534. sde_kms_init_shared_hw(sde_kms);
  2535. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  2536. sde_kms->first_kickoff = true;
  2537. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  2538. sde_irq_update(msm_kms, false);
  2539. sde_kms->first_kickoff = false;
  2540. }
  2541. }
  2542. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  2543. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  2544. {
  2545. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  2546. int rc = -EINVAL;
  2547. SDE_DEBUG("\n");
  2548. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  2549. if (rc > 0)
  2550. rc = 0;
  2551. SDE_EVT32(rc, genpd->device_count);
  2552. return rc;
  2553. }
  2554. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  2555. {
  2556. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  2557. SDE_DEBUG("\n");
  2558. pm_runtime_put_sync(sde_kms->dev->dev);
  2559. SDE_EVT32(genpd->device_count);
  2560. return 0;
  2561. }
  2562. static int _sde_kms_get_splash_data(struct sde_splash_data *data)
  2563. {
  2564. int i = 0;
  2565. int ret = 0;
  2566. struct device_node *parent, *node, *node1;
  2567. struct resource r, r1;
  2568. const char *node_name = "cont_splash_region";
  2569. struct sde_splash_mem *mem;
  2570. bool share_splash_mem = false;
  2571. int num_displays, num_regions;
  2572. struct sde_splash_display *splash_display;
  2573. if (!data)
  2574. return -EINVAL;
  2575. memset(data, 0, sizeof(*data));
  2576. parent = of_find_node_by_path("/reserved-memory");
  2577. if (!parent) {
  2578. SDE_ERROR("failed to find reserved-memory node\n");
  2579. return -EINVAL;
  2580. }
  2581. node = of_find_node_by_name(parent, node_name);
  2582. if (!node) {
  2583. SDE_DEBUG("failed to find node %s\n", node_name);
  2584. return -EINVAL;
  2585. }
  2586. node1 = of_find_node_by_name(parent, "disp_rdump_region");
  2587. if (!node1)
  2588. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  2589. /**
  2590. * Support sharing a single splash memory for all the built in displays
  2591. * and also independent splash region per displays. Incase of
  2592. * independent splash region for each connected display, dtsi node of
  2593. * cont_splash_region should be collection of all memory regions
  2594. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  2595. */
  2596. num_displays = dsi_display_get_num_of_displays();
  2597. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  2598. data->num_splash_displays = num_displays;
  2599. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  2600. if (num_displays > num_regions) {
  2601. share_splash_mem = true;
  2602. pr_info(":%d displays share same splash buf\n", num_displays);
  2603. }
  2604. for (i = 0; i < num_displays; i++) {
  2605. splash_display = &data->splash_display[i];
  2606. if (!i || !share_splash_mem) {
  2607. if (of_address_to_resource(node, i, &r)) {
  2608. SDE_ERROR("invalid data for:%s\n", node_name);
  2609. return -EINVAL;
  2610. }
  2611. mem = &data->splash_mem[i];
  2612. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  2613. SDE_DEBUG("failed to find ramdump memory\n");
  2614. mem->ramdump_base = 0;
  2615. mem->ramdump_size = 0;
  2616. } else {
  2617. mem->ramdump_base = (unsigned long)r1.start;
  2618. mem->ramdump_size = (r1.end - r1.start) + 1;
  2619. }
  2620. mem->splash_buf_base = (unsigned long)r.start;
  2621. mem->splash_buf_size = (r.end - r.start) + 1;
  2622. mem->ref_cnt = 0;
  2623. splash_display->splash = mem;
  2624. data->num_splash_regions++;
  2625. } else {
  2626. data->splash_display[i].splash = &data->splash_mem[0];
  2627. }
  2628. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  2629. splash_display->splash->splash_buf_base,
  2630. splash_display->splash->splash_buf_size);
  2631. }
  2632. return ret;
  2633. }
  2634. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  2635. struct platform_device *platformdev)
  2636. {
  2637. int rc = -EINVAL;
  2638. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  2639. if (IS_ERR(sde_kms->mmio)) {
  2640. rc = PTR_ERR(sde_kms->mmio);
  2641. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  2642. sde_kms->mmio = NULL;
  2643. goto error;
  2644. }
  2645. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  2646. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  2647. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  2648. sde_kms->mmio_len);
  2649. if (rc)
  2650. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  2651. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",
  2652. "vbif_phys");
  2653. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  2654. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  2655. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  2656. sde_kms->vbif[VBIF_RT] = NULL;
  2657. goto error;
  2658. }
  2659. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,
  2660. "vbif_phys");
  2661. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  2662. sde_kms->vbif_len[VBIF_RT]);
  2663. if (rc)
  2664. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  2665. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",
  2666. "vbif_nrt_phys");
  2667. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  2668. sde_kms->vbif[VBIF_NRT] = NULL;
  2669. SDE_DEBUG("VBIF NRT is not defined");
  2670. } else {
  2671. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
  2672. "vbif_nrt_phys");
  2673. rc = sde_dbg_reg_register_base("vbif_nrt",
  2674. sde_kms->vbif[VBIF_NRT],
  2675. sde_kms->vbif_len[VBIF_NRT]);
  2676. if (rc)
  2677. SDE_ERROR("dbg base register vbif_nrt failed: %d\n",
  2678. rc);
  2679. }
  2680. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",
  2681. "regdma_phys");
  2682. if (IS_ERR(sde_kms->reg_dma)) {
  2683. sde_kms->reg_dma = NULL;
  2684. SDE_DEBUG("REG_DMA is not defined");
  2685. } else {
  2686. sde_kms->reg_dma_len = msm_iomap_size(platformdev,
  2687. "regdma_phys");
  2688. rc = sde_dbg_reg_register_base("reg_dma",
  2689. sde_kms->reg_dma,
  2690. sde_kms->reg_dma_len);
  2691. if (rc)
  2692. SDE_ERROR("dbg base register reg_dma failed: %d\n",
  2693. rc);
  2694. }
  2695. sde_kms->sid = msm_ioremap(platformdev, "sid_phys",
  2696. "sid_phys");
  2697. if (IS_ERR(sde_kms->sid)) {
  2698. rc = PTR_ERR(sde_kms->sid);
  2699. SDE_ERROR("sid register memory map failed: %d\n", rc);
  2700. sde_kms->sid = NULL;
  2701. goto error;
  2702. }
  2703. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  2704. rc = sde_dbg_reg_register_base("sid", sde_kms->sid, sde_kms->sid_len);
  2705. if (rc)
  2706. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  2707. error:
  2708. return rc;
  2709. }
  2710. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  2711. struct sde_kms *sde_kms)
  2712. {
  2713. int rc = 0;
  2714. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  2715. sde_kms->genpd.name = dev->unique;
  2716. sde_kms->genpd.power_off = sde_kms_pd_disable;
  2717. sde_kms->genpd.power_on = sde_kms_pd_enable;
  2718. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  2719. if (rc < 0) {
  2720. SDE_ERROR("failed to init genpd provider %s: %d\n",
  2721. sde_kms->genpd.name, rc);
  2722. return rc;
  2723. }
  2724. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  2725. &sde_kms->genpd);
  2726. if (rc < 0) {
  2727. SDE_ERROR("failed to add genpd provider %s: %d\n",
  2728. sde_kms->genpd.name, rc);
  2729. pm_genpd_remove(&sde_kms->genpd);
  2730. return rc;
  2731. }
  2732. sde_kms->genpd_init = true;
  2733. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  2734. }
  2735. return rc;
  2736. }
  2737. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  2738. struct drm_device *dev,
  2739. struct msm_drm_private *priv)
  2740. {
  2741. struct sde_rm *rm = NULL;
  2742. int i, rc = -EINVAL;
  2743. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  2744. sde_power_data_bus_set_quota(&priv->phandle, i,
  2745. SDE_POWER_HANDLE_CONT_SPLASH_BUS_AB_QUOTA,
  2746. SDE_POWER_HANDLE_CONT_SPLASH_BUS_IB_QUOTA);
  2747. _sde_kms_core_hw_rev_init(sde_kms);
  2748. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  2749. sde_kms->catalog = sde_hw_catalog_init(dev, sde_kms->core_rev);
  2750. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  2751. rc = PTR_ERR(sde_kms->catalog);
  2752. if (!sde_kms->catalog)
  2753. rc = -EINVAL;
  2754. SDE_ERROR("catalog init failed: %d\n", rc);
  2755. sde_kms->catalog = NULL;
  2756. goto power_error;
  2757. }
  2758. /* initialize power domain if defined */
  2759. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  2760. if (rc) {
  2761. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  2762. goto genpd_err;
  2763. }
  2764. rc = _sde_kms_mmu_init(sde_kms);
  2765. if (rc) {
  2766. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  2767. goto power_error;
  2768. }
  2769. /* Initialize reg dma block which is a singleton */
  2770. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  2771. sde_kms->dev);
  2772. if (rc) {
  2773. SDE_ERROR("failed: reg dma init failed\n");
  2774. goto power_error;
  2775. }
  2776. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  2777. rm = &sde_kms->rm;
  2778. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  2779. sde_kms->dev);
  2780. if (rc) {
  2781. SDE_ERROR("rm init failed: %d\n", rc);
  2782. goto power_error;
  2783. }
  2784. sde_kms->rm_init = true;
  2785. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  2786. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  2787. rc = PTR_ERR(sde_kms->hw_intr);
  2788. SDE_ERROR("hw_intr init failed: %d\n", rc);
  2789. sde_kms->hw_intr = NULL;
  2790. goto hw_intr_init_err;
  2791. }
  2792. /*
  2793. * Attempt continuous splash handoff only if reserved
  2794. * splash memory is found & release resources on any error
  2795. * in finding display hw config in splash
  2796. */
  2797. if (sde_kms->splash_data.num_splash_regions) {
  2798. struct sde_splash_display *display;
  2799. int ret, display_count =
  2800. sde_kms->splash_data.num_splash_displays;
  2801. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  2802. &sde_kms->splash_data, sde_kms->catalog);
  2803. for (i = 0; i < display_count; i++) {
  2804. display = &sde_kms->splash_data.splash_display[i];
  2805. /*
  2806. * free splash region on resource init failure and
  2807. * cont-splash disabled case
  2808. */
  2809. if (!display->cont_splash_enabled || ret)
  2810. _sde_kms_free_splash_region(sde_kms, display);
  2811. }
  2812. }
  2813. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  2814. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  2815. rc = PTR_ERR(sde_kms->hw_mdp);
  2816. if (!sde_kms->hw_mdp)
  2817. rc = -EINVAL;
  2818. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  2819. sde_kms->hw_mdp = NULL;
  2820. goto power_error;
  2821. }
  2822. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  2823. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  2824. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  2825. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  2826. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  2827. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  2828. if (!sde_kms->hw_vbif[vbif_idx])
  2829. rc = -EINVAL;
  2830. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  2831. sde_kms->hw_vbif[vbif_idx] = NULL;
  2832. goto power_error;
  2833. }
  2834. }
  2835. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  2836. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  2837. sde_kms->mmio_len, sde_kms->catalog);
  2838. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  2839. rc = PTR_ERR(sde_kms->hw_uidle);
  2840. if (!sde_kms->hw_uidle)
  2841. rc = -EINVAL;
  2842. /* uidle is optional, so do not make it a fatal error */
  2843. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  2844. sde_kms->hw_uidle = NULL;
  2845. rc = 0;
  2846. }
  2847. } else {
  2848. sde_kms->hw_uidle = NULL;
  2849. }
  2850. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  2851. sde_kms->sid_len, sde_kms->catalog);
  2852. if (IS_ERR(sde_kms->hw_sid)) {
  2853. SDE_ERROR("failed to init sid %ld\n", PTR_ERR(sde_kms->hw_sid));
  2854. sde_kms->hw_sid = NULL;
  2855. goto power_error;
  2856. }
  2857. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  2858. &priv->phandle, "core_clk");
  2859. if (rc) {
  2860. SDE_ERROR("failed to init perf %d\n", rc);
  2861. goto perf_err;
  2862. }
  2863. /*
  2864. * _sde_kms_drm_obj_init should create the DRM related objects
  2865. * i.e. CRTCs, planes, encoders, connectors and so forth
  2866. */
  2867. rc = _sde_kms_drm_obj_init(sde_kms);
  2868. if (rc) {
  2869. SDE_ERROR("modeset init failed: %d\n", rc);
  2870. goto drm_obj_init_err;
  2871. }
  2872. return 0;
  2873. genpd_err:
  2874. drm_obj_init_err:
  2875. sde_core_perf_destroy(&sde_kms->perf);
  2876. hw_intr_init_err:
  2877. perf_err:
  2878. power_error:
  2879. return rc;
  2880. }
  2881. static int sde_kms_hw_init(struct msm_kms *kms)
  2882. {
  2883. struct sde_kms *sde_kms;
  2884. struct drm_device *dev;
  2885. struct msm_drm_private *priv;
  2886. struct platform_device *platformdev;
  2887. int i, rc = -EINVAL;
  2888. if (!kms) {
  2889. SDE_ERROR("invalid kms\n");
  2890. goto end;
  2891. }
  2892. sde_kms = to_sde_kms(kms);
  2893. dev = sde_kms->dev;
  2894. if (!dev || !dev->dev) {
  2895. SDE_ERROR("invalid device\n");
  2896. goto end;
  2897. }
  2898. platformdev = to_platform_device(dev->dev);
  2899. priv = dev->dev_private;
  2900. if (!priv) {
  2901. SDE_ERROR("invalid private data\n");
  2902. goto end;
  2903. }
  2904. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  2905. if (rc)
  2906. goto error;
  2907. rc = _sde_kms_get_splash_data(&sde_kms->splash_data);
  2908. if (rc)
  2909. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  2910. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  2911. if (rc < 0) {
  2912. SDE_ERROR("resource enable failed: %d\n", rc);
  2913. goto error;
  2914. }
  2915. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  2916. if (rc)
  2917. goto hw_init_err;
  2918. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  2919. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  2920. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  2921. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  2922. mutex_init(&sde_kms->secure_transition_lock);
  2923. atomic_set(&sde_kms->detach_sec_cb, 0);
  2924. atomic_set(&sde_kms->detach_all_cb, 0);
  2925. /*
  2926. * Support format modifiers for compression etc.
  2927. */
  2928. dev->mode_config.allow_fb_modifiers = true;
  2929. /*
  2930. * Handle (re)initializations during power enable
  2931. */
  2932. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  2933. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  2934. SDE_POWER_EVENT_POST_ENABLE |
  2935. SDE_POWER_EVENT_PRE_DISABLE,
  2936. sde_kms_handle_power_event, sde_kms, "kms");
  2937. if (sde_kms->splash_data.num_splash_displays) {
  2938. SDE_DEBUG("Skipping MDP Resources disable\n");
  2939. } else {
  2940. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  2941. sde_power_data_bus_set_quota(&priv->phandle, i,
  2942. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  2943. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  2944. pm_runtime_put_sync(sde_kms->dev->dev);
  2945. }
  2946. return 0;
  2947. hw_init_err:
  2948. pm_runtime_put_sync(sde_kms->dev->dev);
  2949. error:
  2950. _sde_kms_hw_destroy(sde_kms, platformdev);
  2951. end:
  2952. return rc;
  2953. }
  2954. struct msm_kms *sde_kms_init(struct drm_device *dev)
  2955. {
  2956. struct msm_drm_private *priv;
  2957. struct sde_kms *sde_kms;
  2958. if (!dev || !dev->dev_private) {
  2959. SDE_ERROR("drm device node invalid\n");
  2960. return ERR_PTR(-EINVAL);
  2961. }
  2962. priv = dev->dev_private;
  2963. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  2964. if (!sde_kms) {
  2965. SDE_ERROR("failed to allocate sde kms\n");
  2966. return ERR_PTR(-ENOMEM);
  2967. }
  2968. msm_kms_init(&sde_kms->base, &kms_funcs);
  2969. sde_kms->dev = dev;
  2970. return &sde_kms->base;
  2971. }
  2972. static int _sde_kms_register_events(struct msm_kms *kms,
  2973. struct drm_mode_object *obj, u32 event, bool en)
  2974. {
  2975. int ret = 0;
  2976. struct drm_crtc *crtc = NULL;
  2977. struct drm_connector *conn = NULL;
  2978. struct sde_kms *sde_kms = NULL;
  2979. if (!kms || !obj) {
  2980. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  2981. return -EINVAL;
  2982. }
  2983. sde_kms = to_sde_kms(kms);
  2984. switch (obj->type) {
  2985. case DRM_MODE_OBJECT_CRTC:
  2986. crtc = obj_to_crtc(obj);
  2987. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  2988. break;
  2989. case DRM_MODE_OBJECT_CONNECTOR:
  2990. conn = obj_to_connector(obj);
  2991. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  2992. en);
  2993. break;
  2994. }
  2995. return ret;
  2996. }
  2997. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  2998. {
  2999. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  3000. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  3001. }